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be2net: Implement initiate FW dump feature for Lancer
[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_cmds.h
CommitLineData
6b7c5b94 1/*
c7bb15a6 2 * Copyright (C) 2005 - 2013 Emulex
6b7c5b94
SP		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
d2145cde 11 * linux-drivers@emulex.com
6b7c5b94 12 *
d2145cde
AK		 13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6b7c5b94
SP		 16 */
17
18/*
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
24 */
25
26struct be_sge {
27 u32 pa_lo;
28 u32 pa_hi;
29 u32 len;
30};
31
32#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
35struct be_mcc_wrb {
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
41 union {
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
44 } payload;
45};
46
47#define CQE_FLAGS_VALID_MASK (1 << 31)
48#define CQE_FLAGS_ASYNC_MASK (1 << 30)
49#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
51
52/* Completion Status */
53enum {
2b3f291b
SP		 54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
49643848 60 MCC_STATUS_NOT_SUPPORTED = 66
6b7c5b94
SP		 61};
62
63#define CQE_STATUS_COMPL_MASK 0xFFFF
64#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
65#define CQE_STATUS_EXTD_MASK 0xFFFF
f5209b44 66#define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
6b7c5b94 67
efd2e40a 68struct be_mcc_compl {
6b7c5b94
SP		 69 u32 status; /* dword 0 */
70 u32 tag0; /* dword 1 */
71 u32 tag1; /* dword 2 */
72 u32 flags; /* dword 3 */
73};
74
a8f447bd
SP		 75/* When the async bit of mcc_compl is set, the last 4 bytes of
76 * mcc_compl is interpreted as follows:
77 */
78#define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
79#define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
cc4ce020
SK		 80#define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
81#define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
a8f447bd 82#define ASYNC_EVENT_CODE_LINK_STATE 0x1
cc4ce020
SK		 83#define ASYNC_EVENT_CODE_GRP_5 0x5
84#define ASYNC_EVENT_QOS_SPEED 0x1
85#define ASYNC_EVENT_COS_PRIORITY 0x2
3968fa1e 86#define ASYNC_EVENT_PVID_STATE 0x3
bc0c3405
AK		 87#define ASYNC_EVENT_CODE_QNQ 0x6
88#define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
89
a8f447bd
SP		 90struct be_async_event_trailer {
91 u32 code;
92};
93
94enum {
ea172a01
SP		 95 LINK_DOWN = 0x0,
96 LINK_UP = 0x1
a8f447bd 97};
ea172a01 98#define LINK_STATUS_MASK 0x1
2e177a5c 99#define LOGICAL_LINK_STATUS_MASK 0x2
a8f447bd
SP		 100
101/* When the event code of an async trailer is link-state, the mcc_compl
102 * must be interpreted as follows
103 */
104struct be_async_event_link_state {
105 u8 physical_port;
106 u8 port_link_status;
107 u8 port_duplex;
108 u8 port_speed;
109 u8 port_fault;
110 u8 rsvd0[7];
111 struct be_async_event_trailer trailer;
112} __packed;
113
cc4ce020
SK		 114/* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
115 * the mcc_compl must be interpreted as follows
116 */
117struct be_async_event_grp5_qos_link_speed {
118 u8 physical_port;
119 u8 rsvd[5];
120 u16 qos_link_speed;
121 u32 event_tag;
122 struct be_async_event_trailer trailer;
123} __packed;
124
125/* When the event code of an async trailer is GRP5 and event type is
126 * CoS-Priority, the mcc_compl must be interpreted as follows
127 */
128struct be_async_event_grp5_cos_priority {
129 u8 physical_port;
130 u8 available_priority_bmap;
131 u8 reco_default_priority;
132 u8 valid;
133 u8 rsvd0;
134 u8 event_tag;
135 struct be_async_event_trailer trailer;
136} __packed;
137
3968fa1e
AK		 138/* When the event code of an async trailer is GRP5 and event type is
139 * PVID state, the mcc_compl must be interpreted as follows
140 */
141struct be_async_event_grp5_pvid_state {
142 u8 enabled;
143 u8 rsvd0;
144 u16 tag;
145 u32 event_tag;
146 u32 rsvd1;
147 struct be_async_event_trailer trailer;
148} __packed;
149
bc0c3405
AK		 150/* async event indicating outer VLAN tag in QnQ */
151struct be_async_event_qnq {
152 u8 valid; /* Indicates if outer VLAN is valid */
153 u8 rsvd0;
154 u16 vlan_tag;
155 u32 event_tag;
156 u8 rsvd1[4];
157 struct be_async_event_trailer trailer;
158} __packed;
159
6b7c5b94
SP		 160struct be_mcc_mailbox {
161 struct be_mcc_wrb wrb;
efd2e40a 162 struct be_mcc_compl compl;
6b7c5b94
SP		 163};
164
165#define CMD_SUBSYSTEM_COMMON 0x1
166#define CMD_SUBSYSTEM_ETH 0x3
ff33a6e2 167#define CMD_SUBSYSTEM_LOWLEVEL 0xb
6b7c5b94
SP		 168
169#define OPCODE_COMMON_NTWK_MAC_QUERY 1
170#define OPCODE_COMMON_NTWK_MAC_SET 2
171#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
172#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
173#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
fa9a6fed 174#define OPCODE_COMMON_READ_FLASHROM 6
84517482 175#define OPCODE_COMMON_WRITE_FLASHROM 7
6b7c5b94
SP		 176#define OPCODE_COMMON_CQ_CREATE 12
177#define OPCODE_COMMON_EQ_CREATE 13
cc4ce020 178#define OPCODE_COMMON_MCC_CREATE 21
e1d18735 179#define OPCODE_COMMON_SET_QOS 28
cc4ce020 180#define OPCODE_COMMON_MCC_CREATE_EXT 90
368c0ca2 181#define OPCODE_COMMON_SEEPROM_READ 30
9e1453c5 182#define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
6b7c5b94
SP		 183#define OPCODE_COMMON_NTWK_RX_FILTER 34
184#define OPCODE_COMMON_GET_FW_VERSION 35
185#define OPCODE_COMMON_SET_FLOW_CONTROL 36
186#define OPCODE_COMMON_GET_FLOW_CONTROL 37
187#define OPCODE_COMMON_SET_FRAME_SIZE 39
188#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
189#define OPCODE_COMMON_FIRMWARE_CONFIG 42
190#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
191#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
5fb379ee 192#define OPCODE_COMMON_MCC_DESTROY 53
6b7c5b94
SP		 193#define OPCODE_COMMON_CQ_DESTROY 54
194#define OPCODE_COMMON_EQ_DESTROY 55
195#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
196#define OPCODE_COMMON_NTWK_PMAC_ADD 59
197#define OPCODE_COMMON_NTWK_PMAC_DEL 60
14074eab 198#define OPCODE_COMMON_FUNCTION_RESET 61
311fddc7 199#define OPCODE_COMMON_MANAGE_FAT 68
fad9ab2c
SB		 200#define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
201#define OPCODE_COMMON_GET_BEACON_STATE 70
0388f251 202#define OPCODE_COMMON_READ_TRANSRECV_DATA 73
b4e32a71 203#define OPCODE_COMMON_GET_PORT_NAME 77
68c45a2d 204#define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
ee3cb629 205#define OPCODE_COMMON_GET_PHY_DETAILS 102
2e588f84 206#define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
609ff3bb 207#define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
941a77d5
SK		 208#define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
209#define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
590c391d
PR		 210#define OPCODE_COMMON_GET_MAC_LIST 147
211#define OPCODE_COMMON_SET_MAC_LIST 148
f1f3ee1b 212#define OPCODE_COMMON_GET_HSW_CONFIG 152
abb93951
PR		 213#define OPCODE_COMMON_GET_FUNC_CONFIG 160
214#define OPCODE_COMMON_GET_PROFILE_CONFIG 164
d5c18473 215#define OPCODE_COMMON_SET_PROFILE_CONFIG 165
f1f3ee1b 216#define OPCODE_COMMON_SET_HSW_CONFIG 153
f25b119c 217#define OPCODE_COMMON_GET_FN_PRIVILEGES 170
de49bd5a 218#define OPCODE_COMMON_READ_OBJECT 171
485bf569 219#define OPCODE_COMMON_WRITE_OBJECT 172
4c876616 220#define OPCODE_COMMON_GET_IFACE_LIST 194
dcf7ebba 221#define OPCODE_COMMON_ENABLE_DISABLE_VF 196
6b7c5b94 222
3abcdeda 223#define OPCODE_ETH_RSS_CONFIG 1
6b7c5b94
SP		 224#define OPCODE_ETH_ACPI_CONFIG 2
225#define OPCODE_ETH_PROMISCUOUS 3
226#define OPCODE_ETH_GET_STATISTICS 4
227#define OPCODE_ETH_TX_CREATE 7
228#define OPCODE_ETH_RX_CREATE 8
229#define OPCODE_ETH_TX_DESTROY 9
230#define OPCODE_ETH_RX_DESTROY 10
71d8d1b5 231#define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
005d5696 232#define OPCODE_ETH_GET_PPORT_STATS 18
6b7c5b94 233
ff33a6e2
S		 234#define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
235#define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
fced9999 236#define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
ff33a6e2 237
6b7c5b94
SP		 238struct be_cmd_req_hdr {
239 u8 opcode; /* dword 0 */
240 u8 subsystem; /* dword 0 */
241 u8 port_number; /* dword 0 */
242 u8 domain; /* dword 0 */
243 u32 timeout; /* dword 1 */
244 u32 request_length; /* dword 2 */
7b139c83
AK		 245 u8 version; /* dword 3 */
246 u8 rsvd[3]; /* dword 3 */
6b7c5b94
SP		 247};
248
249#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
250#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
251struct be_cmd_resp_hdr {
652bf646
PR		 252 u8 opcode; /* dword 0 */
253 u8 subsystem; /* dword 0 */
254 u8 rsvd[2]; /* dword 0 */
255 u8 status; /* dword 1 */
256 u8 add_status; /* dword 1 */
257 u8 rsvd1[2]; /* dword 1 */
6b7c5b94
SP		 258 u32 response_length; /* dword 2 */
259 u32 actual_resp_len; /* dword 3 */
260};
261
262struct phys_addr {
263 u32 lo;
264 u32 hi;
265};
266
267/**************************
268 * BE Command definitions *
269 **************************/
270
271/* Pseudo amap definition in which each bit of the actual structure is defined
272 * as a byte: used to calculate offset/shift/mask of each field */
273struct amap_eq_context {
274 u8 cidx[13]; /* dword 0*/
275 u8 rsvd0[3]; /* dword 0*/
276 u8 epidx[13]; /* dword 0*/
277 u8 valid; /* dword 0*/
278 u8 rsvd1; /* dword 0*/
279 u8 size; /* dword 0*/
280 u8 pidx[13]; /* dword 1*/
281 u8 rsvd2[3]; /* dword 1*/
282 u8 pd[10]; /* dword 1*/
283 u8 count[3]; /* dword 1*/
284 u8 solevent; /* dword 1*/
285 u8 stalled; /* dword 1*/
286 u8 armed; /* dword 1*/
287 u8 rsvd3[4]; /* dword 2*/
288 u8 func[8]; /* dword 2*/
289 u8 rsvd4; /* dword 2*/
290 u8 delaymult[10]; /* dword 2*/
291 u8 rsvd5[2]; /* dword 2*/
292 u8 phase[2]; /* dword 2*/
293 u8 nodelay; /* dword 2*/
294 u8 rsvd6[4]; /* dword 2*/
295 u8 rsvd7[32]; /* dword 3*/
296} __packed;
297
298struct be_cmd_req_eq_create {
299 struct be_cmd_req_hdr hdr;
300 u16 num_pages; /* sword */
301 u16 rsvd0; /* sword */
302 u8 context[sizeof(struct amap_eq_context) / 8];
303 struct phys_addr pages[8];
304} __packed;
305
306struct be_cmd_resp_eq_create {
307 struct be_cmd_resp_hdr resp_hdr;
308 u16 eq_id; /* sword */
309 u16 rsvd0; /* sword */
310} __packed;
311
312/******************** Mac query ***************************/
313enum {
314 MAC_ADDRESS_TYPE_STORAGE = 0x0,
315 MAC_ADDRESS_TYPE_NETWORK = 0x1,
316 MAC_ADDRESS_TYPE_PD = 0x2,
317 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
318};
319
320struct mac_addr {
321 u16 size_of_struct;
322 u8 addr[ETH_ALEN];
323} __packed;
324
325struct be_cmd_req_mac_query {
326 struct be_cmd_req_hdr hdr;
327 u8 type;
328 u8 permanent;
329 u16 if_id;
590c391d 330 u32 pmac_id;
6b7c5b94
SP		 331} __packed;
332
333struct be_cmd_resp_mac_query {
334 struct be_cmd_resp_hdr hdr;
335 struct mac_addr mac;
336};
337
338/******************** PMac Add ***************************/
339struct be_cmd_req_pmac_add {
340 struct be_cmd_req_hdr hdr;
341 u32 if_id;
342 u8 mac_address[ETH_ALEN];
343 u8 rsvd0[2];
344} __packed;
345
346struct be_cmd_resp_pmac_add {
347 struct be_cmd_resp_hdr hdr;
348 u32 pmac_id;
349};
350
351/******************** PMac Del ***************************/
352struct be_cmd_req_pmac_del {
353 struct be_cmd_req_hdr hdr;
354 u32 if_id;
355 u32 pmac_id;
356};
357
358/******************** Create CQ ***************************/
359/* Pseudo amap definition in which each bit of the actual structure is defined
360 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 361struct amap_cq_context_be {
6b7c5b94
SP		 362 u8 cidx[11]; /* dword 0*/
363 u8 rsvd0; /* dword 0*/
364 u8 coalescwm[2]; /* dword 0*/
365 u8 nodelay; /* dword 0*/
366 u8 epidx[11]; /* dword 0*/
367 u8 rsvd1; /* dword 0*/
368 u8 count[2]; /* dword 0*/
369 u8 valid; /* dword 0*/
370 u8 solevent; /* dword 0*/
371 u8 eventable; /* dword 0*/
372 u8 pidx[11]; /* dword 1*/
373 u8 rsvd2; /* dword 1*/
374 u8 pd[10]; /* dword 1*/
375 u8 eqid[8]; /* dword 1*/
376 u8 stalled; /* dword 1*/
377 u8 armed; /* dword 1*/
378 u8 rsvd3[4]; /* dword 2*/
379 u8 func[8]; /* dword 2*/
380 u8 rsvd4[20]; /* dword 2*/
381 u8 rsvd5[32]; /* dword 3*/
382} __packed;
383
bbdc42f8 384struct amap_cq_context_v2 {
fe6d2a38
SP		 385 u8 rsvd0[12]; /* dword 0*/
386 u8 coalescwm[2]; /* dword 0*/
387 u8 nodelay; /* dword 0*/
388 u8 rsvd1[12]; /* dword 0*/
389 u8 count[2]; /* dword 0*/
390 u8 valid; /* dword 0*/
391 u8 rsvd2; /* dword 0*/
392 u8 eventable; /* dword 0*/
393 u8 eqid[16]; /* dword 1*/
394 u8 rsvd3[15]; /* dword 1*/
395 u8 armed; /* dword 1*/
396 u8 rsvd4[32]; /* dword 2*/
397 u8 rsvd5[32]; /* dword 3*/
398} __packed;
399
6b7c5b94
SP		 400struct be_cmd_req_cq_create {
401 struct be_cmd_req_hdr hdr;
402 u16 num_pages;
fe6d2a38
SP		 403 u8 page_size;
404 u8 rsvd0;
405 u8 context[sizeof(struct amap_cq_context_be) / 8];
6b7c5b94
SP		 406 struct phys_addr pages[8];
407} __packed;
408
fe6d2a38 409
6b7c5b94
SP		 410struct be_cmd_resp_cq_create {
411 struct be_cmd_resp_hdr hdr;
412 u16 cq_id;
413 u16 rsvd0;
414} __packed;
415
311fddc7
SK		 416struct be_cmd_req_get_fat {
417 struct be_cmd_req_hdr hdr;
418 u32 fat_operation;
419 u32 read_log_offset;
420 u32 read_log_length;
421 u32 data_buffer_size;
422 u32 data_buffer[1];
423} __packed;
424
425struct be_cmd_resp_get_fat {
426 struct be_cmd_resp_hdr hdr;
427 u32 log_size;
428 u32 read_log_length;
429 u32 rsvd[2];
430 u32 data_buffer[1];
431} __packed;
432
433
5fb379ee
SP		 434/******************** Create MCCQ ***************************/
435/* Pseudo amap definition in which each bit of the actual structure is defined
436 * as a byte: used to calculate offset/shift/mask of each field */
fe6d2a38 437struct amap_mcc_context_be {
5fb379ee
SP		 438 u8 con_index[14];
439 u8 rsvd0[2];
440 u8 ring_size[4];
441 u8 fetch_wrb;
442 u8 fetch_r2t;
443 u8 cq_id[10];
444 u8 prod_index[14];
445 u8 fid[8];
446 u8 pdid[9];
447 u8 valid;
448 u8 rsvd1[32];
449 u8 rsvd2[32];
450} __packed;
451
fe6d2a38
SP		 452struct amap_mcc_context_lancer {
453 u8 async_cq_id[16];
454 u8 ring_size[4];
455 u8 rsvd0[12];
456 u8 rsvd1[31];
457 u8 valid;
458 u8 async_cq_valid[1];
459 u8 rsvd2[31];
460 u8 rsvd3[32];
461} __packed;
462
5fb379ee 463struct be_cmd_req_mcc_create {
34b1ef04
SK		 464 struct be_cmd_req_hdr hdr;
465 u16 num_pages;
466 u16 cq_id;
467 u8 context[sizeof(struct amap_mcc_context_be) / 8];
468 struct phys_addr pages[8];
469} __packed;
470
471struct be_cmd_req_mcc_ext_create {
5fb379ee
SP		 472 struct be_cmd_req_hdr hdr;
473 u16 num_pages;
fe6d2a38 474 u16 cq_id;
cc4ce020 475 u32 async_event_bitmap[1];
fe6d2a38 476 u8 context[sizeof(struct amap_mcc_context_be) / 8];
5fb379ee
SP		 477 struct phys_addr pages[8];
478} __packed;
479
480struct be_cmd_resp_mcc_create {
481 struct be_cmd_resp_hdr hdr;
482 u16 id;
483 u16 rsvd0;
484} __packed;
485
6b7c5b94
SP		 486/******************** Create TxQ ***************************/
487#define BE_ETH_TX_RING_TYPE_STANDARD 2
488#define BE_ULP1_NUM 1
489
6b7c5b94
SP		 490struct be_cmd_req_eth_tx_create {
491 struct be_cmd_req_hdr hdr;
492 u8 num_pages;
493 u8 ulp_num;
94d73aaa
VV		 494 u16 type;
495 u16 if_id;
496 u8 queue_size;
497 u8 rsvd0;
498 u32 rsvd1;
499 u16 cq_id;
500 u16 rsvd2;
501 u32 rsvd3[13];
6b7c5b94
SP		 502 struct phys_addr pages[8];
503} __packed;
504
505struct be_cmd_resp_eth_tx_create {
506 struct be_cmd_resp_hdr hdr;
507 u16 cid;
94d73aaa
VV		 508 u16 rid;
509 u32 db_offset;
510 u32 rsvd0[4];
6b7c5b94
SP		 511} __packed;
512
513/******************** Create RxQ ***************************/
514struct be_cmd_req_eth_rx_create {
515 struct be_cmd_req_hdr hdr;
516 u16 cq_id;
517 u8 frag_size;
518 u8 num_pages;
519 struct phys_addr pages[2];
520 u32 interface_id;
521 u16 max_frame_size;
522 u16 rsvd0;
523 u32 rss_queue;
524} __packed;
525
526struct be_cmd_resp_eth_rx_create {
527 struct be_cmd_resp_hdr hdr;
528 u16 id;
3abcdeda 529 u8 rss_id;
6b7c5b94
SP		 530 u8 rsvd0;
531} __packed;
532
533/******************** Q Destroy ***************************/
534/* Type of Queue to be destroyed */
535enum {
536 QTYPE_EQ = 1,
537 QTYPE_CQ,
538 QTYPE_TXQ,
5fb379ee
SP		 539 QTYPE_RXQ,
540 QTYPE_MCCQ
6b7c5b94
SP		 541};
542
543struct be_cmd_req_q_destroy {
544 struct be_cmd_req_hdr hdr;
545 u16 id;
546 u16 bypass_flush; /* valid only for rx q destroy */
547} __packed;
548
549/************ I/f Create (it's actually I/f Config Create)**********/
550
551/* Capability flags for the i/f */
552enum be_if_flags {
553 BE_IF_FLAGS_RSS = 0x4,
554 BE_IF_FLAGS_PROMISCUOUS = 0x8,
555 BE_IF_FLAGS_BROADCAST = 0x10,
556 BE_IF_FLAGS_UNTAGGED = 0x20,
557 BE_IF_FLAGS_ULP = 0x40,
558 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
559 BE_IF_FLAGS_VLAN = 0x100,
560 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
561 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
f21b538c
PR		 562 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
563 BE_IF_FLAGS_MULTICAST = 0x1000
6b7c5b94
SP		 564};
565
566/* An RX interface is an object with one or more MAC addresses and
567 * filtering capabilities. */
568struct be_cmd_req_if_create {
569 struct be_cmd_req_hdr hdr;
af901ca1 570 u32 version; /* ignore currently */
6b7c5b94
SP		 571 u32 capability_flags;
572 u32 enable_flags;
573 u8 mac_addr[ETH_ALEN];
574 u8 rsvd0;
575 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
576 u32 vlan_tag; /* not used currently */
577} __packed;
578
579struct be_cmd_resp_if_create {
580 struct be_cmd_resp_hdr hdr;
581 u32 interface_id;
582 u32 pmac_id;
583};
584
585/****** I/f Destroy(it's actually I/f Config Destroy )**********/
586struct be_cmd_req_if_destroy {
587 struct be_cmd_req_hdr hdr;
588 u32 interface_id;
589};
590
591/*************** HW Stats Get **********************************/
89a88ab8 592struct be_port_rxf_stats_v0 {
6b7c5b94
SP		 593 u32 rx_bytes_lsd; /* dword 0*/
594 u32 rx_bytes_msd; /* dword 1*/
595 u32 rx_total_frames; /* dword 2*/
596 u32 rx_unicast_frames; /* dword 3*/
597 u32 rx_multicast_frames; /* dword 4*/
598 u32 rx_broadcast_frames; /* dword 5*/
599 u32 rx_crc_errors; /* dword 6*/
600 u32 rx_alignment_symbol_errors; /* dword 7*/
601 u32 rx_pause_frames; /* dword 8*/
602 u32 rx_control_frames; /* dword 9*/
603 u32 rx_in_range_errors; /* dword 10*/
604 u32 rx_out_range_errors; /* dword 11*/
605 u32 rx_frame_too_long; /* dword 12*/
18fb06a1
SR		 606 u32 rx_address_filtered; /* dword 13*/
607 u32 rx_vlan_filtered; /* dword 14*/
6b7c5b94
SP		 608 u32 rx_dropped_too_small; /* dword 15*/
609 u32 rx_dropped_too_short; /* dword 16*/
610 u32 rx_dropped_header_too_small; /* dword 17*/
611 u32 rx_dropped_tcp_length; /* dword 18*/
612 u32 rx_dropped_runt; /* dword 19*/
613 u32 rx_64_byte_packets; /* dword 20*/
614 u32 rx_65_127_byte_packets; /* dword 21*/
615 u32 rx_128_256_byte_packets; /* dword 22*/
616 u32 rx_256_511_byte_packets; /* dword 23*/
617 u32 rx_512_1023_byte_packets; /* dword 24*/
618 u32 rx_1024_1518_byte_packets; /* dword 25*/
619 u32 rx_1519_2047_byte_packets; /* dword 26*/
620 u32 rx_2048_4095_byte_packets; /* dword 27*/
621 u32 rx_4096_8191_byte_packets; /* dword 28*/
622 u32 rx_8192_9216_byte_packets; /* dword 29*/
623 u32 rx_ip_checksum_errs; /* dword 30*/
624 u32 rx_tcp_checksum_errs; /* dword 31*/
625 u32 rx_udp_checksum_errs; /* dword 32*/
626 u32 rx_non_rss_packets; /* dword 33*/
627 u32 rx_ipv4_packets; /* dword 34*/
628 u32 rx_ipv6_packets; /* dword 35*/
629 u32 rx_ipv4_bytes_lsd; /* dword 36*/
630 u32 rx_ipv4_bytes_msd; /* dword 37*/
631 u32 rx_ipv6_bytes_lsd; /* dword 38*/
632 u32 rx_ipv6_bytes_msd; /* dword 39*/
633 u32 rx_chute1_packets; /* dword 40*/
634 u32 rx_chute2_packets; /* dword 41*/
635 u32 rx_chute3_packets; /* dword 42*/
636 u32 rx_management_packets; /* dword 43*/
637 u32 rx_switched_unicast_packets; /* dword 44*/
638 u32 rx_switched_multicast_packets; /* dword 45*/
639 u32 rx_switched_broadcast_packets; /* dword 46*/
640 u32 tx_bytes_lsd; /* dword 47*/
641 u32 tx_bytes_msd; /* dword 48*/
642 u32 tx_unicastframes; /* dword 49*/
643 u32 tx_multicastframes; /* dword 50*/
644 u32 tx_broadcastframes; /* dword 51*/
645 u32 tx_pauseframes; /* dword 52*/
646 u32 tx_controlframes; /* dword 53*/
647 u32 tx_64_byte_packets; /* dword 54*/
648 u32 tx_65_127_byte_packets; /* dword 55*/
649 u32 tx_128_256_byte_packets; /* dword 56*/
650 u32 tx_256_511_byte_packets; /* dword 57*/
651 u32 tx_512_1023_byte_packets; /* dword 58*/
652 u32 tx_1024_1518_byte_packets; /* dword 59*/
653 u32 tx_1519_2047_byte_packets; /* dword 60*/
654 u32 tx_2048_4095_byte_packets; /* dword 61*/
655 u32 tx_4096_8191_byte_packets; /* dword 62*/
656 u32 tx_8192_9216_byte_packets; /* dword 63*/
657 u32 rx_fifo_overflow; /* dword 64*/
658 u32 rx_input_fifo_overflow; /* dword 65*/
659};
660
89a88ab8
AK		 661struct be_rxf_stats_v0 {
662 struct be_port_rxf_stats_v0 port[2];
6b7c5b94
SP		 663 u32 rx_drops_no_pbuf; /* dword 132*/
664 u32 rx_drops_no_txpb; /* dword 133*/
665 u32 rx_drops_no_erx_descr; /* dword 134*/
666 u32 rx_drops_no_tpre_descr; /* dword 135*/
667 u32 management_rx_port_packets; /* dword 136*/
668 u32 management_rx_port_bytes; /* dword 137*/
669 u32 management_rx_port_pause_frames; /* dword 138*/
670 u32 management_rx_port_errors; /* dword 139*/
671 u32 management_tx_port_packets; /* dword 140*/
672 u32 management_tx_port_bytes; /* dword 141*/
673 u32 management_tx_port_pause; /* dword 142*/
674 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
675 u32 rx_drops_too_many_frags; /* dword 144*/
676 u32 rx_drops_invalid_ring; /* dword 145*/
677 u32 forwarded_packets; /* dword 146*/
678 u32 rx_drops_mtu; /* dword 147*/
f6c4bf3e
AK		 679 u32 rsvd0[7];
680 u32 port0_jabber_events;
681 u32 port1_jabber_events;
682 u32 rsvd1[6];
6b7c5b94
SP		 683};
684
89a88ab8 685struct be_erx_stats_v0 {
6b7c5b94 686 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
89a88ab8 687 u32 rsvd[4];
6b7c5b94
SP		 688};
689
f6c4bf3e
AK		 690struct be_pmem_stats {
691 u32 eth_red_drops;
89a88ab8 692 u32 rsvd[5];
f6c4bf3e
AK		 693};
694
89a88ab8
AK		 695struct be_hw_stats_v0 {
696 struct be_rxf_stats_v0 rxf;
6b7c5b94 697 u32 rsvd[48];
89a88ab8 698 struct be_erx_stats_v0 erx;
f6c4bf3e 699 struct be_pmem_stats pmem;
6b7c5b94
SP		 700};
701
89a88ab8 702struct be_cmd_req_get_stats_v0 {
6b7c5b94 703 struct be_cmd_req_hdr hdr;
89a88ab8 704 u8 rsvd[sizeof(struct be_hw_stats_v0)];
6b7c5b94
SP		 705};
706
89a88ab8 707struct be_cmd_resp_get_stats_v0 {
6b7c5b94 708 struct be_cmd_resp_hdr hdr;
89a88ab8 709 struct be_hw_stats_v0 hw_stats;
6b7c5b94
SP		 710};
711
ac124ff9 712struct lancer_pport_stats {
005d5696
SX		 713 u32 tx_packets_lo;
714 u32 tx_packets_hi;
715 u32 tx_unicast_packets_lo;
716 u32 tx_unicast_packets_hi;
717 u32 tx_multicast_packets_lo;
718 u32 tx_multicast_packets_hi;
719 u32 tx_broadcast_packets_lo;
720 u32 tx_broadcast_packets_hi;
721 u32 tx_bytes_lo;
722 u32 tx_bytes_hi;
723 u32 tx_unicast_bytes_lo;
724 u32 tx_unicast_bytes_hi;
725 u32 tx_multicast_bytes_lo;
726 u32 tx_multicast_bytes_hi;
727 u32 tx_broadcast_bytes_lo;
728 u32 tx_broadcast_bytes_hi;
729 u32 tx_discards_lo;
730 u32 tx_discards_hi;
731 u32 tx_errors_lo;
732 u32 tx_errors_hi;
733 u32 tx_pause_frames_lo;
734 u32 tx_pause_frames_hi;
735 u32 tx_pause_on_frames_lo;
736 u32 tx_pause_on_frames_hi;
737 u32 tx_pause_off_frames_lo;
738 u32 tx_pause_off_frames_hi;
739 u32 tx_internal_mac_errors_lo;
740 u32 tx_internal_mac_errors_hi;
741 u32 tx_control_frames_lo;
742 u32 tx_control_frames_hi;
743 u32 tx_packets_64_bytes_lo;
744 u32 tx_packets_64_bytes_hi;
745 u32 tx_packets_65_to_127_bytes_lo;
746 u32 tx_packets_65_to_127_bytes_hi;
747 u32 tx_packets_128_to_255_bytes_lo;
748 u32 tx_packets_128_to_255_bytes_hi;
749 u32 tx_packets_256_to_511_bytes_lo;
750 u32 tx_packets_256_to_511_bytes_hi;
751 u32 tx_packets_512_to_1023_bytes_lo;
752 u32 tx_packets_512_to_1023_bytes_hi;
753 u32 tx_packets_1024_to_1518_bytes_lo;
754 u32 tx_packets_1024_to_1518_bytes_hi;
755 u32 tx_packets_1519_to_2047_bytes_lo;
756 u32 tx_packets_1519_to_2047_bytes_hi;
757 u32 tx_packets_2048_to_4095_bytes_lo;
758 u32 tx_packets_2048_to_4095_bytes_hi;
759 u32 tx_packets_4096_to_8191_bytes_lo;
760 u32 tx_packets_4096_to_8191_bytes_hi;
761 u32 tx_packets_8192_to_9216_bytes_lo;
762 u32 tx_packets_8192_to_9216_bytes_hi;
763 u32 tx_lso_packets_lo;
764 u32 tx_lso_packets_hi;
765 u32 rx_packets_lo;
766 u32 rx_packets_hi;
767 u32 rx_unicast_packets_lo;
768 u32 rx_unicast_packets_hi;
769 u32 rx_multicast_packets_lo;
770 u32 rx_multicast_packets_hi;
771 u32 rx_broadcast_packets_lo;
772 u32 rx_broadcast_packets_hi;
773 u32 rx_bytes_lo;
774 u32 rx_bytes_hi;
775 u32 rx_unicast_bytes_lo;
776 u32 rx_unicast_bytes_hi;
777 u32 rx_multicast_bytes_lo;
778 u32 rx_multicast_bytes_hi;
779 u32 rx_broadcast_bytes_lo;
780 u32 rx_broadcast_bytes_hi;
781 u32 rx_unknown_protos;
782 u32 rsvd_69; /* Word 69 is reserved */
783 u32 rx_discards_lo;
784 u32 rx_discards_hi;
785 u32 rx_errors_lo;
786 u32 rx_errors_hi;
787 u32 rx_crc_errors_lo;
788 u32 rx_crc_errors_hi;
789 u32 rx_alignment_errors_lo;
790 u32 rx_alignment_errors_hi;
791 u32 rx_symbol_errors_lo;
792 u32 rx_symbol_errors_hi;
793 u32 rx_pause_frames_lo;
794 u32 rx_pause_frames_hi;
795 u32 rx_pause_on_frames_lo;
796 u32 rx_pause_on_frames_hi;
797 u32 rx_pause_off_frames_lo;
798 u32 rx_pause_off_frames_hi;
799 u32 rx_frames_too_long_lo;
800 u32 rx_frames_too_long_hi;
801 u32 rx_internal_mac_errors_lo;
802 u32 rx_internal_mac_errors_hi;
803 u32 rx_undersize_packets;
804 u32 rx_oversize_packets;
805 u32 rx_fragment_packets;
806 u32 rx_jabbers;
807 u32 rx_control_frames_lo;
808 u32 rx_control_frames_hi;
809 u32 rx_control_frames_unknown_opcode_lo;
810 u32 rx_control_frames_unknown_opcode_hi;
811 u32 rx_in_range_errors;
812 u32 rx_out_of_range_errors;
18fb06a1
SR		 813 u32 rx_address_filtered;
814 u32 rx_vlan_filtered;
005d5696
SX		 815 u32 rx_dropped_too_small;
816 u32 rx_dropped_too_short;
817 u32 rx_dropped_header_too_small;
818 u32 rx_dropped_invalid_tcp_length;
819 u32 rx_dropped_runt;
820 u32 rx_ip_checksum_errors;
821 u32 rx_tcp_checksum_errors;
822 u32 rx_udp_checksum_errors;
823 u32 rx_non_rss_packets;
824 u32 rsvd_111;
825 u32 rx_ipv4_packets_lo;
826 u32 rx_ipv4_packets_hi;
827 u32 rx_ipv6_packets_lo;
828 u32 rx_ipv6_packets_hi;
829 u32 rx_ipv4_bytes_lo;
830 u32 rx_ipv4_bytes_hi;
831 u32 rx_ipv6_bytes_lo;
832 u32 rx_ipv6_bytes_hi;
833 u32 rx_nic_packets_lo;
834 u32 rx_nic_packets_hi;
835 u32 rx_tcp_packets_lo;
836 u32 rx_tcp_packets_hi;
837 u32 rx_iscsi_packets_lo;
838 u32 rx_iscsi_packets_hi;
839 u32 rx_management_packets_lo;
840 u32 rx_management_packets_hi;
841 u32 rx_switched_unicast_packets_lo;
842 u32 rx_switched_unicast_packets_hi;
843 u32 rx_switched_multicast_packets_lo;
844 u32 rx_switched_multicast_packets_hi;
845 u32 rx_switched_broadcast_packets_lo;
846 u32 rx_switched_broadcast_packets_hi;
847 u32 num_forwards_lo;
848 u32 num_forwards_hi;
849 u32 rx_fifo_overflow;
850 u32 rx_input_fifo_overflow;
851 u32 rx_drops_too_many_frags_lo;
852 u32 rx_drops_too_many_frags_hi;
853 u32 rx_drops_invalid_queue;
854 u32 rsvd_141;
855 u32 rx_drops_mtu_lo;
856 u32 rx_drops_mtu_hi;
857 u32 rx_packets_64_bytes_lo;
858 u32 rx_packets_64_bytes_hi;
859 u32 rx_packets_65_to_127_bytes_lo;
860 u32 rx_packets_65_to_127_bytes_hi;
861 u32 rx_packets_128_to_255_bytes_lo;
862 u32 rx_packets_128_to_255_bytes_hi;
863 u32 rx_packets_256_to_511_bytes_lo;
864 u32 rx_packets_256_to_511_bytes_hi;
865 u32 rx_packets_512_to_1023_bytes_lo;
866 u32 rx_packets_512_to_1023_bytes_hi;
867 u32 rx_packets_1024_to_1518_bytes_lo;
868 u32 rx_packets_1024_to_1518_bytes_hi;
869 u32 rx_packets_1519_to_2047_bytes_lo;
870 u32 rx_packets_1519_to_2047_bytes_hi;
871 u32 rx_packets_2048_to_4095_bytes_lo;
872 u32 rx_packets_2048_to_4095_bytes_hi;
873 u32 rx_packets_4096_to_8191_bytes_lo;
874 u32 rx_packets_4096_to_8191_bytes_hi;
875 u32 rx_packets_8192_to_9216_bytes_lo;
876 u32 rx_packets_8192_to_9216_bytes_hi;
877};
878
879struct pport_stats_params {
880 u16 pport_num;
881 u8 rsvd;
882 u8 reset_stats;
883};
884
885struct lancer_cmd_req_pport_stats {
886 struct be_cmd_req_hdr hdr;
887 union {
888 struct pport_stats_params params;
ac124ff9 889 u8 rsvd[sizeof(struct lancer_pport_stats)];
005d5696
SX		 890 } cmd_params;
891};
892
893struct lancer_cmd_resp_pport_stats {
894 struct be_cmd_resp_hdr hdr;
ac124ff9 895 struct lancer_pport_stats pport_stats;
005d5696
SX		 896};
897
ac124ff9 898static inline struct lancer_pport_stats*
005d5696
SX		 899 pport_stats_from_cmd(struct be_adapter *adapter)
900{
901 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
902 return &cmd->pport_stats;
903}
904
609ff3bb
AK		 905struct be_cmd_req_get_cntl_addnl_attribs {
906 struct be_cmd_req_hdr hdr;
907 u8 rsvd[8];
908};
909
910struct be_cmd_resp_get_cntl_addnl_attribs {
911 struct be_cmd_resp_hdr hdr;
912 u16 ipl_file_number;
913 u8 ipl_file_version;
914 u8 rsvd0;
915 u8 on_die_temperature; /* in degrees centigrade*/
916 u8 rsvd1[3];
917};
918
6b7c5b94
SP		 919struct be_cmd_req_vlan_config {
920 struct be_cmd_req_hdr hdr;
921 u8 interface_id;
922 u8 promiscuous;
923 u8 untagged;
924 u8 num_vlan;
925 u16 normal_vlan[64];
926} __packed;
927
5b8821b7 928/******************* RX FILTER ******************************/
e7b909a6 929#define BE_MAX_MC 64 /* set mcast promisc if > 64 */
6b7c5b94
SP		 930struct macaddr {
931 u8 byte[ETH_ALEN];
932};
933
ecd0bf0f
PR		 934struct be_cmd_req_rx_filter {
935 struct be_cmd_req_hdr hdr;
936 u32 global_flags_mask;
937 u32 global_flags;
938 u32 if_flags_mask;
939 u32 if_flags;
940 u32 if_id;
5b8821b7
SP		 941 u32 mcast_num;
942 struct macaddr mcast_mac[BE_MAX_MC];
ecd0bf0f
PR		 943};
944
6b7c5b94
SP		 945/******************** Link Status Query *******************/
946struct be_cmd_req_link_status {
947 struct be_cmd_req_hdr hdr;
948 u32 rsvd;
949};
950
6b7c5b94
SP		 951enum {
952 PHY_LINK_DUPLEX_NONE = 0x0,
953 PHY_LINK_DUPLEX_HALF = 0x1,
954 PHY_LINK_DUPLEX_FULL = 0x2
955};
956
957enum {
958 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
959 PHY_LINK_SPEED_10MBPS = 0x1,
960 PHY_LINK_SPEED_100MBPS = 0x2,
961 PHY_LINK_SPEED_1GBPS = 0x3,
962 PHY_LINK_SPEED_10GBPS = 0x4
963};
964
965struct be_cmd_resp_link_status {
966 struct be_cmd_resp_hdr hdr;
967 u8 physical_port;
968 u8 mac_duplex;
969 u8 mac_speed;
970 u8 mac_fault;
971 u8 mgmt_mac_duplex;
972 u8 mgmt_mac_speed;
0388f251 973 u16 link_speed;
b236916a
AK		 974 u8 logical_link_status;
975 u8 rsvd1[3];
6b7c5b94
SP		 976} __packed;
977
0388f251
SB		 978/******************** Port Identification ***************************/
979/* Identifies the type of port attached to NIC */
980struct be_cmd_req_port_type {
981 struct be_cmd_req_hdr hdr;
982 u32 page_num;
983 u32 port;
984};
985
986enum {
987 TR_PAGE_A0 = 0xa0,
988 TR_PAGE_A2 = 0xa2
989};
990
991struct be_cmd_resp_port_type {
992 struct be_cmd_resp_hdr hdr;
993 u32 page_num;
994 u32 port;
995 struct data {
996 u8 identifier;
997 u8 identifier_ext;
998 u8 connector;
999 u8 transceiver[8];
1000 u8 rsvd0[3];
1001 u8 length_km;
1002 u8 length_hm;
1003 u8 length_om1;
1004 u8 length_om2;
1005 u8 length_cu;
1006 u8 length_cu_m;
1007 u8 vendor_name[16];
1008 u8 rsvd;
1009 u8 vendor_oui[3];
1010 u8 vendor_pn[16];
1011 u8 vendor_rev[4];
1012 } data;
1013};
1014
6b7c5b94 1015/******************** Get FW Version *******************/
6b7c5b94
SP		 1016struct be_cmd_req_get_fw_version {
1017 struct be_cmd_req_hdr hdr;
1018 u8 rsvd0[FW_VER_LEN];
1019 u8 rsvd1[FW_VER_LEN];
1020} __packed;
1021
1022struct be_cmd_resp_get_fw_version {
1023 struct be_cmd_resp_hdr hdr;
1024 u8 firmware_version_string[FW_VER_LEN];
1025 u8 fw_on_flash_version_string[FW_VER_LEN];
1026} __packed;
1027
1028/******************** Set Flow Contrl *******************/
1029struct be_cmd_req_set_flow_control {
1030 struct be_cmd_req_hdr hdr;
1031 u16 tx_flow_control;
1032 u16 rx_flow_control;
1033} __packed;
1034
1035/******************** Get Flow Contrl *******************/
1036struct be_cmd_req_get_flow_control {
1037 struct be_cmd_req_hdr hdr;
1038 u32 rsvd;
1039};
1040
1041struct be_cmd_resp_get_flow_control {
1042 struct be_cmd_resp_hdr hdr;
1043 u16 tx_flow_control;
1044 u16 rx_flow_control;
1045} __packed;
1046
1047/******************** Modify EQ Delay *******************/
1048struct be_cmd_req_modify_eq_delay {
1049 struct be_cmd_req_hdr hdr;
1050 u32 num_eq;
1051 struct {
1052 u32 eq_id;
1053 u32 phase;
1054 u32 delay_multiplier;
1055 } delay[8];
1056} __packed;
1057
1058struct be_cmd_resp_modify_eq_delay {
1059 struct be_cmd_resp_hdr hdr;
1060 u32 rsvd0;
1061} __packed;
1062
1063/******************** Get FW Config *******************/
752961a1
SP		 1064/* The HW can come up in either of the following multi-channel modes
1065 * based on the skew/IPL.
1066 */
045508a8 1067#define RDMA_ENABLED 0x4
752961a1
SP		 1068#define FLEX10_MODE 0x400
1069#define VNIC_MODE 0x20000
1070#define UMC_ENABLED 0x1000000
6b7c5b94
SP		 1071struct be_cmd_req_query_fw_cfg {
1072 struct be_cmd_req_hdr hdr;
3abcdeda 1073 u32 rsvd[31];
6b7c5b94
SP		 1074};
1075
1076struct be_cmd_resp_query_fw_cfg {
1077 struct be_cmd_resp_hdr hdr;
1078 u32 be_config_number;
1079 u32 asic_revision;
1080 u32 phys_port;
3486be29 1081 u32 function_mode;
6b7c5b94 1082 u32 rsvd[26];
3abcdeda
SP		 1083 u32 function_caps;
1084};
1085
73dea398
PR		 1086/******************** RSS Config ****************************************/
1087/* RSS type Input parameters used to compute RX hash
1088 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1089 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1090 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1091 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1092 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1093 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1094 *
1095 * When multiple RSS types are enabled, HW picks the best hash policy
1096 * based on the type of the received packet.
1097 */
3abcdeda
SP		 1098#define RSS_ENABLE_NONE 0x0
1099#define RSS_ENABLE_IPV4 0x1
1100#define RSS_ENABLE_TCP_IPV4 0x2
1101#define RSS_ENABLE_IPV6 0x4
1102#define RSS_ENABLE_TCP_IPV6 0x8
d3bd3a5e
PR		 1103#define RSS_ENABLE_UDP_IPV4 0x10
1104#define RSS_ENABLE_UDP_IPV6 0x20
3abcdeda 1105
594ad54a
SR		 1106#define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1107#define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1108
3abcdeda
SP		 1109struct be_cmd_req_rss_config {
1110 struct be_cmd_req_hdr hdr;
1111 u32 if_id;
1112 u16 enable_rss;
1113 u16 cpu_table_size_log2;
1114 u32 hash[10];
1115 u8 cpu_table[128];
1116 u8 flush;
1117 u8 rsvd0[3];
6b7c5b94
SP		 1118};
1119
fad9ab2c
SB		 1120/******************** Port Beacon ***************************/
1121
1122#define BEACON_STATE_ENABLED 0x1
1123#define BEACON_STATE_DISABLED 0x0
1124
1125struct be_cmd_req_enable_disable_beacon {
1126 struct be_cmd_req_hdr hdr;
1127 u8 port_num;
1128 u8 beacon_state;
1129 u8 beacon_duration;
1130 u8 status_duration;
1131} __packed;
1132
1133struct be_cmd_resp_enable_disable_beacon {
1134 struct be_cmd_resp_hdr resp_hdr;
1135 u32 rsvd0;
1136} __packed;
1137
1138struct be_cmd_req_get_beacon_state {
1139 struct be_cmd_req_hdr hdr;
1140 u8 port_num;
1141 u8 rsvd0;
1142 u16 rsvd1;
1143} __packed;
1144
1145struct be_cmd_resp_get_beacon_state {
1146 struct be_cmd_resp_hdr resp_hdr;
1147 u8 beacon_state;
1148 u8 rsvd0[3];
1149} __packed;
1150
84517482
AK		 1151/****************** Firmware Flash ******************/
1152struct flashrom_params {
1153 u32 op_code;
1154 u32 op_type;
1155 u32 data_buf_size;
1156 u32 offset;
84517482
AK		 1157};
1158
1159struct be_cmd_write_flashrom {
1160 struct be_cmd_req_hdr hdr;
1161 struct flashrom_params params;
be716446
PR		 1162 u8 data_buf[32768];
1163 u8 rsvd[4];
1164} __packed;
84517482 1165
be716446
PR		 1166/* cmd to read flash crc */
1167struct be_cmd_read_flash_crc {
1168 struct be_cmd_req_hdr hdr;
1169 struct flashrom_params params;
1170 u8 crc[4];
1171 u8 rsvd[4];
1172};
485bf569
SN		 1173/**************** Lancer Firmware Flash ************/
1174struct amap_lancer_write_obj_context {
1175 u8 write_length[24];
1176 u8 reserved1[7];
1177 u8 eof;
1178} __packed;
1179
1180struct lancer_cmd_req_write_object {
1181 struct be_cmd_req_hdr hdr;
1182 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1183 u32 write_offset;
1184 u8 object_name[104];
1185 u32 descriptor_count;
1186 u32 buf_len;
1187 u32 addr_low;
1188 u32 addr_high;
1189};
1190
f67ef7ba
PR		 1191#define LANCER_NO_RESET_NEEDED 0x00
1192#define LANCER_FW_RESET_NEEDED 0x02
485bf569
SN		 1193struct lancer_cmd_resp_write_object {
1194 u8 opcode;
1195 u8 subsystem;
1196 u8 rsvd1[2];
1197 u8 status;
1198 u8 additional_status;
1199 u8 rsvd2[2];
1200 u32 resp_len;
1201 u32 actual_resp_len;
1202 u32 actual_write_len;
f67ef7ba
PR		 1203 u8 change_status;
1204 u8 rsvd3[3];
485bf569
SN		 1205};
1206
de49bd5a
PR		 1207/************************ Lancer Read FW info **************/
1208#define LANCER_READ_FILE_CHUNK (32*1024)
1209#define LANCER_READ_FILE_EOF_MASK 0x80000000
1210
1211#define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
af5875bd
PR		 1212#define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1213#define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
de49bd5a
PR		 1214
1215struct lancer_cmd_req_read_object {
1216 struct be_cmd_req_hdr hdr;
1217 u32 desired_read_len;
1218 u32 read_offset;
1219 u8 object_name[104];
1220 u32 descriptor_count;
1221 u32 buf_len;
1222 u32 addr_low;
1223 u32 addr_high;
1224};
1225
1226struct lancer_cmd_resp_read_object {
1227 u8 opcode;
1228 u8 subsystem;
1229 u8 rsvd1[2];
1230 u8 status;
1231 u8 additional_status;
1232 u8 rsvd2[2];
1233 u32 resp_len;
1234 u32 actual_resp_len;
1235 u32 actual_read_len;
1236 u32 eof;
1237};
1238
71d8d1b5
AK		 1239/************************ WOL *******************************/
1240struct be_cmd_req_acpi_wol_magic_config{
1241 struct be_cmd_req_hdr hdr;
1242 u32 rsvd0[145];
1243 u8 magic_mac[6];
1244 u8 rsvd2[2];
1245} __packed;
1246
4762f6ce
AK		 1247struct be_cmd_req_acpi_wol_magic_config_v1 {
1248 struct be_cmd_req_hdr hdr;
1249 u8 rsvd0[2];
1250 u8 query_options;
1251 u8 rsvd1[5];
1252 u32 rsvd2[288];
1253 u8 magic_mac[6];
1254 u8 rsvd3[22];
1255} __packed;
1256
1257struct be_cmd_resp_acpi_wol_magic_config_v1 {
1258 struct be_cmd_resp_hdr hdr;
1259 u8 rsvd0[2];
1260 u8 wol_settings;
1261 u8 rsvd1[5];
1262 u32 rsvd2[295];
1263} __packed;
1264
1265#define BE_GET_WOL_CAP 2
1266
1267#define BE_WOL_CAP 0x1
1268#define BE_PME_D0_CAP 0x8
1269#define BE_PME_D1_CAP 0x10
1270#define BE_PME_D2_CAP 0x20
1271#define BE_PME_D3HOT_CAP 0x40
1272#define BE_PME_D3COLD_CAP 0x80
1273
ff33a6e2
S		 1274/********************** LoopBack test *********************/
1275struct be_cmd_req_loopback_test {
1276 struct be_cmd_req_hdr hdr;
1277 u32 loopback_type;
1278 u32 num_pkts;
1279 u64 pattern;
1280 u32 src_port;
1281 u32 dest_port;
1282 u32 pkt_size;
1283};
1284
1285struct be_cmd_resp_loopback_test {
1286 struct be_cmd_resp_hdr resp_hdr;
1287 u32 status;
1288 u32 num_txfer;
1289 u32 num_rx;
1290 u32 miscomp_off;
1291 u32 ticks_compl;
1292};
1293
fced9999
SB		 1294struct be_cmd_req_set_lmode {
1295 struct be_cmd_req_hdr hdr;
1296 u8 src_port;
1297 u8 dest_port;
1298 u8 loopback_type;
1299 u8 loopback_state;
1300};
1301
1302struct be_cmd_resp_set_lmode {
1303 struct be_cmd_resp_hdr resp_hdr;
1304 u8 rsvd0[4];
1305};
1306
ff33a6e2
S		 1307/********************** DDR DMA test *********************/
1308struct be_cmd_req_ddrdma_test {
1309 struct be_cmd_req_hdr hdr;
1310 u64 pattern;
1311 u32 byte_count;
1312 u32 rsvd0;
1313 u8 snd_buff[4096];
1314 u8 rsvd1[4096];
1315};
1316
1317struct be_cmd_resp_ddrdma_test {
1318 struct be_cmd_resp_hdr hdr;
1319 u64 pattern;
1320 u32 byte_cnt;
1321 u32 snd_err;
1322 u8 rsvd0[4096];
1323 u8 rcv_buff[4096];
1324};
1325
368c0ca2
SB		 1326/*********************** SEEPROM Read ***********************/
1327
1328#define BE_READ_SEEPROM_LEN 1024
1329struct be_cmd_req_seeprom_read {
1330 struct be_cmd_req_hdr hdr;
1331 u8 rsvd0[BE_READ_SEEPROM_LEN];
1332};
1333
1334struct be_cmd_resp_seeprom_read {
1335 struct be_cmd_req_hdr hdr;
1336 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1337};
1338
ee3cb629
AK		 1339enum {
1340 PHY_TYPE_CX4_10GB = 0,
1341 PHY_TYPE_XFP_10GB,
1342 PHY_TYPE_SFP_1GB,
1343 PHY_TYPE_SFP_PLUS_10GB,
1344 PHY_TYPE_KR_10GB,
1345 PHY_TYPE_KX4_10GB,
1346 PHY_TYPE_BASET_10GB,
1347 PHY_TYPE_BASET_1GB,
42f11cf2
AK		 1348 PHY_TYPE_BASEX_1GB,
1349 PHY_TYPE_SGMII,
ee3cb629
AK		 1350 PHY_TYPE_DISABLED = 255
1351};
1352
42f11cf2
AK		 1353#define BE_SUPPORTED_SPEED_NONE 0
1354#define BE_SUPPORTED_SPEED_10MBPS 1
1355#define BE_SUPPORTED_SPEED_100MBPS 2
1356#define BE_SUPPORTED_SPEED_1GBPS 4
1357#define BE_SUPPORTED_SPEED_10GBPS 8
1358
1359#define BE_AN_EN 0x2
1360#define BE_PAUSE_SYM_EN 0x80
1361
1362/* MAC speed valid values */
1363#define SPEED_DEFAULT 0x0
1364#define SPEED_FORCED_10GB 0x1
1365#define SPEED_FORCED_1GB 0x2
1366#define SPEED_AUTONEG_10GB 0x3
1367#define SPEED_AUTONEG_1GB 0x4
1368#define SPEED_AUTONEG_100MB 0x5
1369#define SPEED_AUTONEG_10GB_1GB 0x6
1370#define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1371#define SPEED_AUTONEG_1GB_100MB 0x8
1372#define SPEED_AUTONEG_10MB 0x9
1373#define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1374#define SPEED_AUTONEG_100MB_10MB 0xb
1375#define SPEED_FORCED_100MB 0xc
1376#define SPEED_FORCED_10MB 0xd
1377
ee3cb629
AK		 1378struct be_cmd_req_get_phy_info {
1379 struct be_cmd_req_hdr hdr;
1380 u8 rsvd0[24];
1381};
306f1348
SP		 1382
1383struct be_phy_info {
ee3cb629
AK		 1384 u16 phy_type;
1385 u16 interface_type;
1386 u32 misc_params;
42f11cf2
AK		 1387 u16 ext_phy_details;
1388 u16 rsvd;
1389 u16 auto_speeds_supported;
1390 u16 fixed_speeds_supported;
1391 u32 future_use[2];
ee3cb629
AK		 1392};
1393
306f1348
SP		 1394struct be_cmd_resp_get_phy_info {
1395 struct be_cmd_req_hdr hdr;
1396 struct be_phy_info phy_info;
1397};
1398
e1d18735
AK		 1399/*********************** Set QOS ***********************/
1400
1401#define BE_QOS_BITS_NIC 1
1402
1403struct be_cmd_req_set_qos {
1404 struct be_cmd_req_hdr hdr;
1405 u32 valid_bits;
1406 u32 max_bps_nic;
1407 u32 rsvd[7];
1408};
1409
1410struct be_cmd_resp_set_qos {
1411 struct be_cmd_resp_hdr hdr;
1412 u32 rsvd;
1413};
1414
9e1453c5
AK		 1415/*********************** Controller Attributes ***********************/
1416struct be_cmd_req_cntl_attribs {
1417 struct be_cmd_req_hdr hdr;
1418};
1419
1420struct be_cmd_resp_cntl_attribs {
1421 struct be_cmd_resp_hdr hdr;
1422 struct mgmt_controller_attrib attribs;
1423};
1424
2e588f84
SP		 1425/*********************** Set driver function ***********************/
1426#define CAPABILITY_SW_TIMESTAMPS 2
1427#define CAPABILITY_BE3_NATIVE_ERX_API 4
1428
1429struct be_cmd_req_set_func_cap {
1430 struct be_cmd_req_hdr hdr;
1431 u32 valid_cap_flags;
1432 u32 cap_flags;
1433 u8 rsvd[212];
1434};
1435
1436struct be_cmd_resp_set_func_cap {
1437 struct be_cmd_resp_hdr hdr;
1438 u32 valid_cap_flags;
1439 u32 cap_flags;
1440 u8 rsvd[212];
1441};
1442
f25b119c
PR		 1443/*********************** Function Privileges ***********************/
1444enum {
1445 BE_PRIV_DEFAULT = 0x1,
1446 BE_PRIV_LNKQUERY = 0x2,
1447 BE_PRIV_LNKSTATS = 0x4,
1448 BE_PRIV_LNKMGMT = 0x8,
1449 BE_PRIV_LNKDIAG = 0x10,
1450 BE_PRIV_UTILQUERY = 0x20,
1451 BE_PRIV_FILTMGMT = 0x40,
1452 BE_PRIV_IFACEMGMT = 0x80,
1453 BE_PRIV_VHADM = 0x100,
1454 BE_PRIV_DEVCFG = 0x200,
1455 BE_PRIV_DEVSEC = 0x400
1456};
1457#define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1458 BE_PRIV_DEVSEC)
1459#define MIN_PRIVILEGES BE_PRIV_DEFAULT
1460
1461struct be_cmd_priv_map {
1462 u8 opcode;
1463 u8 subsystem;
1464 u32 priv_mask;
1465};
1466
1467struct be_cmd_req_get_fn_privileges {
1468 struct be_cmd_req_hdr hdr;
1469 u32 rsvd;
1470};
1471
1472struct be_cmd_resp_get_fn_privileges {
1473 struct be_cmd_resp_hdr hdr;
1474 u32 privilege_mask;
1475};
1476
1477
590c391d
PR		 1478/******************** GET/SET_MACLIST **************************/
1479#define BE_MAX_MAC 64
590c391d
PR		 1480struct be_cmd_req_get_mac_list {
1481 struct be_cmd_req_hdr hdr;
e5e1ee89
PR		 1482 u8 mac_type;
1483 u8 perm_override;
1484 u16 iface_id;
1485 u32 mac_id;
1486 u32 rsvd[3];
1487} __packed;
1488
1489struct get_list_macaddr {
1490 u16 mac_addr_size;
1491 union {
1492 u8 macaddr[6];
1493 struct {
1494 u8 rsvd[2];
1495 u32 mac_id;
1496 } __packed s_mac_id;
1497 } __packed mac_addr_id;
590c391d
PR		 1498} __packed;
1499
1500struct be_cmd_resp_get_mac_list {
1501 struct be_cmd_resp_hdr hdr;
e5e1ee89
PR		 1502 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1503 struct get_list_macaddr macid_macaddr; /* soft mac */
1504 u8 true_mac_count;
1505 u8 pseudo_mac_count;
1506 u8 mac_list_size;
1507 u8 rsvd;
1508 /* perm override mac */
1509 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
590c391d
PR		 1510} __packed;
1511
1512struct be_cmd_req_set_mac_list {
1513 struct be_cmd_req_hdr hdr;
1514 u8 mac_count;
1515 u8 rsvd1;
1516 u16 rsvd2;
1517 struct macaddr mac[BE_MAX_MAC];
1518} __packed;
1519
f1f3ee1b
AK		 1520/*********************** HSW Config ***********************/
1521struct amap_set_hsw_context {
1522 u8 interface_id[16];
1523 u8 rsvd0[14];
1524 u8 pvid_valid;
1525 u8 rsvd1;
1526 u8 rsvd2[16];
1527 u8 pvid[16];
1528 u8 rsvd3[32];
1529 u8 rsvd4[32];
1530 u8 rsvd5[32];
1531} __packed;
1532
1533struct be_cmd_req_set_hsw_config {
1534 struct be_cmd_req_hdr hdr;
1535 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1536} __packed;
1537
1538struct be_cmd_resp_set_hsw_config {
1539 struct be_cmd_resp_hdr hdr;
1540 u32 rsvd;
1541};
1542
1543struct amap_get_hsw_req_context {
1544 u8 interface_id[16];
1545 u8 rsvd0[14];
1546 u8 pvid_valid;
1547 u8 pport;
1548} __packed;
1549
1550struct amap_get_hsw_resp_context {
1551 u8 rsvd1[16];
1552 u8 pvid[16];
1553 u8 rsvd2[32];
1554 u8 rsvd3[32];
1555 u8 rsvd4[32];
1556} __packed;
1557
1558struct be_cmd_req_get_hsw_config {
1559 struct be_cmd_req_hdr hdr;
1560 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1561} __packed;
1562
1563struct be_cmd_resp_get_hsw_config {
1564 struct be_cmd_resp_hdr hdr;
1565 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1566 u32 rsvd;
1567};
1568
b4e32a71
PR		 1569/******************* get port names ***************/
1570struct be_cmd_req_get_port_name {
1571 struct be_cmd_req_hdr hdr;
1572 u32 rsvd0;
1573};
1574
1575struct be_cmd_resp_get_port_name {
1576 struct be_cmd_req_hdr hdr;
1577 u8 port_name[4];
1578};
1579
89a88ab8
AK		 1580/*************** HW Stats Get v1 **********************************/
1581#define BE_TXP_SW_SZ 48
1582struct be_port_rxf_stats_v1 {
1583 u32 rsvd0[12];
1584 u32 rx_crc_errors;
1585 u32 rx_alignment_symbol_errors;
1586 u32 rx_pause_frames;
1587 u32 rx_priority_pause_frames;
1588 u32 rx_control_frames;
1589 u32 rx_in_range_errors;
1590 u32 rx_out_range_errors;
1591 u32 rx_frame_too_long;
18fb06a1 1592 u32 rx_address_filtered;
89a88ab8
AK		 1593 u32 rx_dropped_too_small;
1594 u32 rx_dropped_too_short;
1595 u32 rx_dropped_header_too_small;
1596 u32 rx_dropped_tcp_length;
1597 u32 rx_dropped_runt;
1598 u32 rsvd1[10];
1599 u32 rx_ip_checksum_errs;
1600 u32 rx_tcp_checksum_errs;
1601 u32 rx_udp_checksum_errs;
1602 u32 rsvd2[7];
1603 u32 rx_switched_unicast_packets;
1604 u32 rx_switched_multicast_packets;
1605 u32 rx_switched_broadcast_packets;
1606 u32 rsvd3[3];
1607 u32 tx_pauseframes;
1608 u32 tx_priority_pauseframes;
1609 u32 tx_controlframes;
1610 u32 rsvd4[10];
1611 u32 rxpp_fifo_overflow_drop;
1612 u32 rx_input_fifo_overflow_drop;
1613 u32 pmem_fifo_overflow_drop;
1614 u32 jabber_events;
1615 u32 rsvd5[3];
1616};
1617
1618
1619struct be_rxf_stats_v1 {
1620 struct be_port_rxf_stats_v1 port[4];
1621 u32 rsvd0[2];
1622 u32 rx_drops_no_pbuf;
1623 u32 rx_drops_no_txpb;
1624 u32 rx_drops_no_erx_descr;
1625 u32 rx_drops_no_tpre_descr;
1626 u32 rsvd1[6];
1627 u32 rx_drops_too_many_frags;
1628 u32 rx_drops_invalid_ring;
1629 u32 forwarded_packets;
1630 u32 rx_drops_mtu;
1631 u32 rsvd2[14];
1632};
1633
1634struct be_erx_stats_v1 {
1635 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1636 u32 rsvd[4];
1637};
1638
1639struct be_hw_stats_v1 {
1640 struct be_rxf_stats_v1 rxf;
1641 u32 rsvd0[BE_TXP_SW_SZ];
1642 struct be_erx_stats_v1 erx;
1643 struct be_pmem_stats pmem;
0b3f0e7a 1644 u32 rsvd1[18];
89a88ab8
AK		 1645};
1646
1647struct be_cmd_req_get_stats_v1 {
1648 struct be_cmd_req_hdr hdr;
1649 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1650};
1651
1652struct be_cmd_resp_get_stats_v1 {
1653 struct be_cmd_resp_hdr hdr;
1654 struct be_hw_stats_v1 hw_stats;
1655};
1656
941a77d5
SK		 1657/************** get fat capabilites *******************/
1658#define MAX_MODULES 27
1659#define MAX_MODES 4
1660#define MODE_UART 0
1661#define FW_LOG_LEVEL_DEFAULT 48
1662#define FW_LOG_LEVEL_FATAL 64
1663
1664struct ext_fat_mode {
1665 u8 mode;
1666 u8 rsvd0;
1667 u16 port_mask;
1668 u32 dbg_lvl;
1669 u64 fun_mask;
1670} __packed;
1671
1672struct ext_fat_modules {
1673 u8 modules_str[32];
1674 u32 modules_id;
1675 u32 num_modes;
1676 struct ext_fat_mode trace_lvl[MAX_MODES];
1677} __packed;
1678
1679struct be_fat_conf_params {
1680 u32 max_log_entries;
1681 u32 log_entry_size;
1682 u8 log_type;
1683 u8 max_log_funs;
1684 u8 max_log_ports;
1685 u8 rsvd0;
1686 u32 supp_modes;
1687 u32 num_modules;
1688 struct ext_fat_modules module[MAX_MODULES];
1689} __packed;
1690
1691struct be_cmd_req_get_ext_fat_caps {
1692 struct be_cmd_req_hdr hdr;
1693 u32 parameter_type;
1694};
1695
1696struct be_cmd_resp_get_ext_fat_caps {
1697 struct be_cmd_resp_hdr hdr;
1698 struct be_fat_conf_params get_params;
1699};
1700
1701struct be_cmd_req_set_ext_fat_caps {
1702 struct be_cmd_req_hdr hdr;
1703 struct be_fat_conf_params set_params;
1704};
1705
a05f99db
VV		 1706#define RESOURCE_DESC_SIZE 88
1707#define NIC_RESOURCE_DESC_TYPE_V0 0x41
1708#define NIC_RESOURCE_DESC_TYPE_V1 0x51
abb93951 1709#define MAX_RESOURCE_DESC 4
a05f99db 1710#define MAX_RESOURCE_DESC_V1 32
d5c18473
PR		 1711
1712/* QOS unit number */
1713#define QUN 4
1714/* Immediate */
1715#define IMM 6
1716/* No save */
1717#define NOSV 7
1718
abb93951
PR		 1719struct be_nic_resource_desc {
1720 u8 desc_type;
1721 u8 desc_len;
1722 u8 rsvd1;
1723 u8 flags;
1724 u8 vf_num;
1725 u8 rsvd2;
1726 u8 pf_num;
1727 u8 rsvd3;
1728 u16 unicast_mac_count;
1729 u8 rsvd4[6];
1730 u16 mcc_count;
1731 u16 vlan_count;
1732 u16 mcast_mac_count;
1733 u16 txq_count;
1734 u16 rq_count;
1735 u16 rssq_count;
1736 u16 lro_count;
1737 u16 cq_count;
1738 u16 toe_conn_count;
1739 u16 eq_count;
1740 u32 rsvd5;
1741 u32 cap_flags;
1742 u8 link_param;
1743 u8 rsvd6[3];
1744 u32 bw_min;
1745 u32 bw_max;
1746 u8 acpi_params;
1747 u8 wol_param;
1748 u16 rsvd7;
1749 u32 rsvd8[3];
1750};
1751
1752struct be_cmd_req_get_func_config {
1753 struct be_cmd_req_hdr hdr;
1754};
1755
1756struct be_cmd_resp_get_func_config {
28710c55 1757 struct be_cmd_resp_hdr hdr;
abb93951
PR		 1758 u32 desc_count;
1759 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1760};
1761
1762#define ACTIVE_PROFILE_TYPE 0x2
1763struct be_cmd_req_get_profile_config {
1764 struct be_cmd_req_hdr hdr;
1765 u8 rsvd;
1766 u8 type;
1767 u16 rsvd1;
1768};
1769
1770struct be_cmd_resp_get_profile_config {
1771 struct be_cmd_req_hdr hdr;
1772 u32 desc_count;
1773 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE];
1774};
1775
a05f99db
VV		 1776struct be_cmd_resp_get_profile_config_v1 {
1777 struct be_cmd_req_hdr hdr;
1778 u32 desc_count;
1779 u8 func_param[MAX_RESOURCE_DESC_V1 * RESOURCE_DESC_SIZE];
1780};
1781
d5c18473
PR		 1782struct be_cmd_req_set_profile_config {
1783 struct be_cmd_req_hdr hdr;
1784 u32 rsvd;
1785 u32 desc_count;
1786 struct be_nic_resource_desc nic_desc;
1787};
1788
1789struct be_cmd_resp_set_profile_config {
1790 struct be_cmd_req_hdr hdr;
1791};
1792
dcf7ebba
PR		 1793struct be_cmd_enable_disable_vf {
1794 struct be_cmd_req_hdr hdr;
1795 u8 enable;
1796 u8 rsvd[3];
1797};
1798
68c45a2d
SK		 1799struct be_cmd_req_intr_set {
1800 struct be_cmd_req_hdr hdr;
1801 u8 intr_enabled;
1802 u8 rsvd[3];
1803};
1804
f25b119c
PR		 1805static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1806{
1807 return flags & adapter->cmd_privileges ? true : false;
1808}
1809
4c876616
SP		 1810/************** Get IFACE LIST *******************/
1811struct be_if_desc {
1812 u32 if_id;
1813 u32 cap_flags;
1814 u32 en_flags;
1815};
1816
1817struct be_cmd_req_get_iface_list {
1818 struct be_cmd_req_hdr hdr;
1819};
1820
1821struct be_cmd_resp_get_iface_list {
1822 struct be_cmd_req_hdr hdr;
1823 u32 if_cnt;
1824 struct be_if_desc if_desc;
1825};
1826
8788fdc2 1827extern int be_pci_fnum_get(struct be_adapter *adapter);
bf99e50d 1828extern int be_fw_wait_ready(struct be_adapter *adapter);
8788fdc2 1829extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
5ee4979b 1830 bool permanent, u32 if_handle, u32 pmac_id);
8788fdc2 1831extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
f8617e08
AK		 1832 u32 if_id, u32 *pmac_id, u32 domain);
1833extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id,
30128031 1834 int pmac_id, u32 domain);
73d540f2 1835extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
1578e777 1836 u32 en_flags, u32 *if_handle, u32 domain);
30128031 1837extern int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle,
658681f7 1838 u32 domain);
8788fdc2 1839extern int be_cmd_eq_create(struct be_adapter *adapter,
6b7c5b94 1840 struct be_queue_info *eq, int eq_delay);
8788fdc2 1841extern int be_cmd_cq_create(struct be_adapter *adapter,
6b7c5b94 1842 struct be_queue_info *cq, struct be_queue_info *eq,
10ef9ab4 1843 bool no_delay, int num_cqe_dma_coalesce);
8788fdc2 1844extern int be_cmd_mccq_create(struct be_adapter *adapter,
5fb379ee
SP		 1845 struct be_queue_info *mccq,
1846 struct be_queue_info *cq);
8788fdc2 1847extern int be_cmd_txq_create(struct be_adapter *adapter,
94d73aaa 1848 struct be_tx_obj *txo);
8788fdc2 1849extern int be_cmd_rxq_create(struct be_adapter *adapter,
6b7c5b94 1850 struct be_queue_info *rxq, u16 cq_id,
10ef9ab4 1851 u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
8788fdc2 1852extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
6b7c5b94 1853 int type);
482c9e79
SP		 1854extern int be_cmd_rxq_destroy(struct be_adapter *adapter,
1855 struct be_queue_info *q);
323ff71e
SP		 1856extern int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1857 u8 *link_status, u32 dom);
8788fdc2
SP		 1858extern int be_cmd_reset(struct be_adapter *adapter);
1859extern int be_cmd_get_stats(struct be_adapter *adapter,
6b7c5b94 1860 struct be_dma_mem *nonemb_cmd);
005d5696
SX		 1861extern int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1862 struct be_dma_mem *nonemb_cmd);
04b71175
SP		 1863extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1864 char *fw_on_flash);
6b7c5b94 1865
8788fdc2
SP		 1866extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
1867extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
6b7c5b94
SP		 1868 u16 *vtag_array, u32 num, bool untagged,
1869 bool promiscuous);
5b8821b7 1870extern int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
8788fdc2 1871extern int be_cmd_set_flow_control(struct be_adapter *adapter,
6b7c5b94 1872 u32 tx_fc, u32 rx_fc);
8788fdc2 1873extern int be_cmd_get_flow_control(struct be_adapter *adapter,
6b7c5b94 1874 u32 *tx_fc, u32 *rx_fc);
0ad3157e
VV		 1875extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1876 u32 *function_mode, u32 *function_caps, u16 *asic_rev);
14074eab 1877extern int be_cmd_reset_function(struct be_adapter *adapter);
3abcdeda 1878extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
594ad54a 1879 u32 rss_hash_opts, u16 table_size);
10ef9ab4 1880extern int be_process_mcc(struct be_adapter *adapter);
fad9ab2c
SB		 1881extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
1882 u8 port_num, u8 beacon, u8 status, u8 state);
1883extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
1884 u8 port_num, u32 *state);
84517482
AK		 1885extern int be_cmd_write_flashrom(struct be_adapter *adapter,
1886 struct be_dma_mem *cmd, u32 flash_oper,
1887 u32 flash_opcode, u32 buf_size);
485bf569 1888extern int lancer_cmd_write_object(struct be_adapter *adapter,
f67ef7ba
PR		 1889 struct be_dma_mem *cmd,
1890 u32 data_size, u32 data_offset,
1891 const char *obj_name,
1892 u32 *data_written, u8 *change_status,
1893 u8 *addn_status);
de49bd5a
PR		 1894int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1895 u32 data_size, u32 data_offset, const char *obj_name,
1896 u32 *data_read, u32 *eof, u8 *addn_status);
3f0d4560
AK		 1897int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1898 int offset);
71d8d1b5
AK		 1899extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1900 struct be_dma_mem *nonemb_cmd);
2243e2e9
SP		 1901extern int be_cmd_fw_init(struct be_adapter *adapter);
1902extern int be_cmd_fw_clean(struct be_adapter *adapter);
7a1e9b20
SP		 1903extern void be_async_mcc_enable(struct be_adapter *adapter);
1904extern void be_async_mcc_disable(struct be_adapter *adapter);
ff33a6e2
S		 1905extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1906 u32 loopback_type, u32 pkt_size,
1907 u32 num_pkts, u64 pattern);
1908extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1909 u32 byte_cnt, struct be_dma_mem *cmd);
368c0ca2
SB		 1910extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1911 struct be_dma_mem *nonemb_cmd);
fced9999
SB		 1912extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1913 u8 loopback_type, u8 enable);
42f11cf2 1914extern int be_cmd_get_phy_info(struct be_adapter *adapter);
e1d18735 1915extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
f67ef7ba 1916extern void be_detect_error(struct be_adapter *adapter);
609ff3bb 1917extern int be_cmd_get_die_temperature(struct be_adapter *adapter);
9e1453c5 1918extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2dc1deb6 1919extern int be_cmd_req_native_mode(struct be_adapter *adapter);
311fddc7
SK		 1920extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
1921extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
f25b119c
PR		 1922extern int be_cmd_get_fn_privileges(struct be_adapter *adapter,
1923 u32 *privilege, u32 domain);
1578e777
PR		 1924extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
1925 bool *pmac_id_active, u32 *pmac_id,
1926 u8 domain);
590c391d
PR		 1927extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
1928 u8 mac_count, u32 domain);
f1f3ee1b
AK		 1929extern int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
1930 u32 domain, u16 intf_id);
1931extern int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
1932 u32 domain, u16 intf_id);
4762f6ce 1933extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
941a77d5
SK		 1934extern int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
1935 struct be_dma_mem *cmd);
1936extern int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
1937 struct be_dma_mem *cmd,
1938 struct be_fat_conf_params *cfgs);
bf99e50d 1939extern int lancer_wait_ready(struct be_adapter *adapter);
5c510811
SK		 1940extern int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
1941extern int lancer_initiate_dump(struct be_adapter *adapter);
1942extern bool dump_present(struct be_adapter *adapter);
bf99e50d 1943extern int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
b4e32a71 1944extern int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
abb93951
PR		 1945extern int be_cmd_get_func_config(struct be_adapter *adapter);
1946extern int be_cmd_get_profile_config(struct be_adapter *adapter, u32 *cap_flags,
a05f99db 1947 u16 *txq_count, u8 domain);
d5c18473
PR		 1948
1949extern int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps,
1950 u8 domain);
4c876616
SP		 1951extern int be_cmd_get_if_id(struct be_adapter *adapter,
1952 struct be_vf_cfg *vf_cfg, int vf_num);
dcf7ebba 1953extern int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
68c45a2d 1954extern int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);
Linux kernel - Deliverables
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