[deliverable/linux.git] / drivers / net / ethernet / emulex / benet / be_hw.h

/*
 * Copyright (C) 2005 - 2013 Emulex
 * All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.  The full GNU General
 * Public License is included in this distribution in the file called COPYING.
 *
 * Contact Information:
 * linux-drivers@emulex.com
 *
 * Emulex
 * 3333 Susan Street
 * Costa Mesa, CA 92626
 */

/********* Mailbox door bell *************/
/* Used for driver communication with the FW.
 * The software must write this register twice to post any command. First,
 * it writes the register with hi=1 and the upper bits of the physical address
 * for the MAILBOX structure. Software must poll the ready bit until this
 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
 * bits in the address. It must poll the ready bit until the command is
 * complete. Upon completion, the MAILBOX will contain a valid completion
 * queue entry.
 */
#define MPU_MAILBOX_DB_OFFSET	0x160
#define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
#define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */

#define MPU_EP_CONTROL 		0

/********** MPU semphore: used for SH & BE  *************/
#define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac  /* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
#define POST_STAGE_MASK				0x0000FFFF
#define POST_ERR_MASK				0x1
#define POST_ERR_SHIFT				31

/* MPU semphore POST stage values */
#define POST_STAGE_AWAITING_HOST_RDY 	0x1 /* FW awaiting goahead from host */
#define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
#define POST_STAGE_BE_RESET		0x3 /* Host wants to reset chip */
#define POST_STAGE_ARMFW_RDY		0xc000	/* FW is done with POST */


/* Lancer SLIPORT registers */
#define SLIPORT_STATUS_OFFSET		0x404
#define SLIPORT_CONTROL_OFFSET		0x408
#define SLIPORT_ERROR1_OFFSET		0x40C
#define SLIPORT_ERROR2_OFFSET		0x410
#define PHYSDEV_CONTROL_OFFSET		0x414

#define SLIPORT_STATUS_ERR_MASK		0x80000000
#define SLIPORT_STATUS_DIP_MASK		0x02000000
#define SLIPORT_STATUS_RN_MASK		0x01000000
#define SLIPORT_STATUS_RDY_MASK		0x00800000
#define SLI_PORT_CONTROL_IP_MASK	0x08000000
#define PHYSDEV_CONTROL_FW_RESET_MASK	0x00000002
#define PHYSDEV_CONTROL_DD_MASK		0x00000004
#define PHYSDEV_CONTROL_INP_MASK	0x40000000

#define SLIPORT_ERROR_NO_RESOURCE1	0x2
#define SLIPORT_ERROR_NO_RESOURCE2	0x9

/********* Memory BAR register ************/
#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 	0xfc
/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 * Disable" may still globally block interrupts in addition to individual
 * interrupt masks; a mechanism for the device driver to block all interrupts
 * atomically without having to arbitrate for the PCI Interrupt Disable bit
 * with the OS.
 */
#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	(1 << 29) /* bit 29 */

/********* PCI Function Capability *********/
#define BE_FUNCTION_CAPS_RSS			0x2
#define BE_FUNCTION_CAPS_SUPER_NIC		0x40

/********* Power management (WOL) **********/
#define PCICFG_PM_CONTROL_OFFSET		0x44
#define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */

/********* Online Control Registers *******/
#define PCICFG_ONLINE0				0xB0
#define PCICFG_ONLINE1				0xB4

/********* UE Status and Mask Registers ***/
#define PCICFG_UE_STATUS_LOW			0xA0
#define PCICFG_UE_STATUS_HIGH			0xA4
#define PCICFG_UE_STATUS_LOW_MASK		0xA8
#define PCICFG_UE_STATUS_HI_MASK		0xAC

/******** SLI_INTF ***********************/
#define SLI_INTF_REG_OFFSET			0x58
#define SLI_INTF_VALID_MASK			0xE0000000
#define SLI_INTF_VALID				0xC0000000
#define SLI_INTF_HINT2_MASK			0x1F000000
#define SLI_INTF_HINT2_SHIFT			24
#define SLI_INTF_HINT1_MASK			0x00FF0000
#define SLI_INTF_HINT1_SHIFT			16
#define SLI_INTF_FAMILY_MASK			0x00000F00
#define SLI_INTF_FAMILY_SHIFT			8
#define SLI_INTF_IF_TYPE_MASK			0x0000F000
#define SLI_INTF_IF_TYPE_SHIFT			12
#define SLI_INTF_REV_MASK			0x000000F0
#define SLI_INTF_REV_SHIFT			4
#define SLI_INTF_FT_MASK			0x00000001

#define SLI_INTF_TYPE_2		2
#define SLI_INTF_TYPE_3		3

/********* ISR0 Register offset **********/
#define CEV_ISR0_OFFSET 			0xC18
#define CEV_ISR_SIZE				4

/********* Event Q door bell *************/
#define DB_EQ_OFFSET			DB_CQ_OFFSET
#define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
#define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
#define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */

/* Clear the interrupt for this eq */
#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
/* Must be 1 */
#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
/* Number of event entries processed */
#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
/* Rearm bit */
#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */

/********* Compl Q door bell *************/
#define DB_CQ_OFFSET 			0x120
#define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
#define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
#define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
						 placing at 11-15 */

/* Number of event entries processed */
#define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
/* Rearm bit */
#define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */

/********** TX ULP door bell *************/
#define DB_TXULP1_OFFSET		0x60
#define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
/* Number of tx entries posted */
#define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
#define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */

/********** RQ(erx) door bell ************/
#define DB_RQ_OFFSET 			0x100
#define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
/* Number of rx frags posted */
#define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */

/********** MCC door bell ************/
#define DB_MCCQ_OFFSET 			0x140
#define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
/* Number of entries posted */
#define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */

/********** SRIOV VF PCICFG OFFSET ********/
#define SRIOV_VF_PCICFG_OFFSET		(4096)

/********** FAT TABLE  ********/
#define RETRIEVE_FAT	0
#define QUERY_FAT	1

/* Flashrom related descriptors */
#define MAX_FLASH_COMP			32
#define IMAGE_TYPE_FIRMWARE		160
#define IMAGE_TYPE_BOOTCODE		224
#define IMAGE_TYPE_OPTIONROM		32

#define NUM_FLASHDIR_ENTRIES		32

#define OPTYPE_ISCSI_ACTIVE		0
#define OPTYPE_REDBOOT			1
#define OPTYPE_BIOS			2
#define OPTYPE_PXE_BIOS			3
#define OPTYPE_FCOE_BIOS		8
#define OPTYPE_ISCSI_BACKUP		9
#define OPTYPE_FCOE_FW_ACTIVE		10
#define OPTYPE_FCOE_FW_BACKUP		11
#define OPTYPE_NCSI_FW			13
#define OPTYPE_PHY_FW			99
#define TN_8022				13

#define ILLEGAL_IOCTL_REQ		2
#define FLASHROM_OPER_PHY_FLASH		9
#define FLASHROM_OPER_PHY_SAVE		10
#define FLASHROM_OPER_FLASH		1
#define FLASHROM_OPER_SAVE		2
#define FLASHROM_OPER_REPORT		4

#define FLASH_IMAGE_MAX_SIZE_g2		(1310720) /* Max firmware image size */
#define FLASH_BIOS_IMAGE_MAX_SIZE_g2	(262144)  /* Max OPTION ROM image sz */
#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2	(262144)  /* Max Redboot image sz    */
#define FLASH_IMAGE_MAX_SIZE_g3		(2097152) /* Max firmware image size */
#define FLASH_BIOS_IMAGE_MAX_SIZE_g3	(524288)  /* Max OPTION ROM image sz */
#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3	(1048576)  /* Max Redboot image sz    */
#define FLASH_NCSI_IMAGE_MAX_SIZE_g3	(262144)
#define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3	262144

#define FLASH_NCSI_MAGIC		(0x16032009)
#define FLASH_NCSI_DISABLED		(0)
#define FLASH_NCSI_ENABLED		(1)

#define FLASH_NCSI_BITFILE_HDR_OFFSET	(0x600000)

/* Offsets for components on Flash. */
#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
#define FLASH_iSCSI_BACKUP_IMAGE_START_g2  (2359296)
#define FLASH_FCoE_PRIMARY_IMAGE_START_g2  (3670016)
#define FLASH_FCoE_BACKUP_IMAGE_START_g2   (4980736)
#define FLASH_iSCSI_BIOS_START_g2          (7340032)
#define FLASH_PXE_BIOS_START_g2            (7864320)
#define FLASH_FCoE_BIOS_START_g2           (524288)
#define FLASH_REDBOOT_START_g2		  (0)

#define FLASH_NCSI_START_g3		   (15990784)
#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
#define FLASH_iSCSI_BACKUP_IMAGE_START_g3  (4194304)
#define FLASH_FCoE_PRIMARY_IMAGE_START_g3  (6291456)
#define FLASH_FCoE_BACKUP_IMAGE_START_g3   (8388608)
#define FLASH_iSCSI_BIOS_START_g3          (12582912)
#define FLASH_PXE_BIOS_START_g3            (13107200)
#define FLASH_FCoE_BIOS_START_g3           (13631488)
#define FLASH_REDBOOT_START_g3             (262144)
#define FLASH_PHY_FW_START_g3		   1310720

#define IMAGE_NCSI			16
#define IMAGE_OPTION_ROM_PXE		32
#define IMAGE_OPTION_ROM_FCoE		33
#define IMAGE_OPTION_ROM_ISCSI		34
#define IMAGE_FLASHISM_JUMPVECTOR	48
#define IMAGE_FLASH_ISM			49
#define IMAGE_JUMP_VECTOR		50
#define IMAGE_FIRMWARE_iSCSI		160
#define IMAGE_FIRMWARE_COMP_iSCSI	161
#define IMAGE_FIRMWARE_FCoE		162
#define IMAGE_FIRMWARE_COMP_FCoE	163
#define IMAGE_FIRMWARE_BACKUP_iSCSI	176
#define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
#define IMAGE_FIRMWARE_BACKUP_FCoE	178
#define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
#define IMAGE_FIRMWARE_PHY		192
#define IMAGE_BOOT_CODE			224

/************* Rx Packet Type Encoding **************/
#define BE_UNICAST_PACKET		0
#define BE_MULTICAST_PACKET		1
#define BE_BROADCAST_PACKET		2
#define BE_RSVD_PACKET			3

/*
 * BE descriptors: host memory data structures whose formats
 * are hardwired in BE silicon.
 */
/* Event Queue Descriptor */
#define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
#define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
#define EQ_ENTRY_RES_ID_SHIFT 		16

struct be_eq_entry {
	u32 evt;
};

/* TX Queue Descriptor */
#define ETH_WRB_FRAG_LEN_MASK		0xFFFF
struct be_eth_wrb {
	u32 frag_pa_hi;		/* dword 0 */
	u32 frag_pa_lo;		/* dword 1 */
	u32 rsvd0;		/* dword 2 */
	u32 frag_len;		/* dword 3: bits 0 - 15 */
} __packed;

/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 * actual structure is defined as a byte : used to calculate
 * offset/shift/mask of each field */
struct amap_eth_hdr_wrb {
	u8 rsvd0[32];		/* dword 0 */
	u8 rsvd1[32];		/* dword 1 */
	u8 complete;		/* dword 2 */
	u8 event;
	u8 crc;
	u8 forward;
	u8 lso6;
	u8 mgmt;
	u8 ipcs;
	u8 udpcs;
	u8 tcpcs;
	u8 lso;
	u8 vlan;
	u8 gso[2];
	u8 num_wrb[5];
	u8 lso_mss[14];
	u8 len[16];		/* dword 3 */
	u8 vlan_tag[16];
} __packed;

struct be_eth_hdr_wrb {
	u32 dw[4];
};

/* TX Compl Queue Descriptor */

/* Pseudo amap definition for eth_tx_compl in which each bit of the
 * actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_tx_compl {
	u8 wrb_index[16];	/* dword 0 */
	u8 ct[2]; 		/* dword 0 */
	u8 port[2];		/* dword 0 */
	u8 rsvd0[8];		/* dword 0 */
	u8 status[4];		/* dword 0 */
	u8 user_bytes[16];	/* dword 1 */
	u8 nwh_bytes[8];	/* dword 1 */
	u8 lso;			/* dword 1 */
	u8 cast_enc[2];		/* dword 1 */
	u8 rsvd1[5];		/* dword 1 */
	u8 rsvd2[32];		/* dword 2 */
	u8 pkts[16];		/* dword 3 */
	u8 ringid[11];		/* dword 3 */
	u8 hash_val[4];		/* dword 3 */
	u8 valid;		/* dword 3 */
} __packed;

struct be_eth_tx_compl {
	u32 dw[4];
};

/* RX Queue Descriptor */
struct be_eth_rx_d {
	u32 fragpa_hi;
	u32 fragpa_lo;
};

/* RX Compl Queue Descriptor */

/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
 * each bit of the actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_rx_compl_v0 {
	u8 vlan_tag[16];	/* dword 0 */
	u8 pktsize[14];		/* dword 0 */
	u8 port;		/* dword 0 */
	u8 ip_opt;		/* dword 0 */
	u8 err;			/* dword 1 */
	u8 rsshp;		/* dword 1 */
	u8 ipf;			/* dword 1 */
	u8 tcpf;		/* dword 1 */
	u8 udpf;		/* dword 1 */
	u8 ipcksm;		/* dword 1 */
	u8 l4_cksm;		/* dword 1 */
	u8 ip_version;		/* dword 1 */
	u8 macdst[6];		/* dword 1 */
	u8 vtp;			/* dword 1 */
	u8 rsvd0;		/* dword 1 */
	u8 fragndx[10];		/* dword 1 */
	u8 ct[2];		/* dword 1 */
	u8 sw;			/* dword 1 */
	u8 numfrags[3];		/* dword 1 */
	u8 rss_flush;		/* dword 2 */
	u8 cast_enc[2];		/* dword 2 */
	u8 vtm;			/* dword 2 */
	u8 rss_bank;		/* dword 2 */
	u8 rsvd1[23];		/* dword 2 */
	u8 lro_pkt;		/* dword 2 */
	u8 rsvd2[2];		/* dword 2 */
	u8 valid;		/* dword 2 */
	u8 rsshash[32];		/* dword 3 */
} __packed;

/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
 * each bit of the actual structure is defined as a byte: used to calculate
 * offset/shift/mask of each field */
struct amap_eth_rx_compl_v1 {
	u8 vlan_tag[16];	/* dword 0 */
	u8 pktsize[14];		/* dword 0 */
	u8 vtp;			/* dword 0 */
	u8 ip_opt;		/* dword 0 */
	u8 err;			/* dword 1 */
	u8 rsshp;		/* dword 1 */
	u8 ipf;			/* dword 1 */
	u8 tcpf;		/* dword 1 */
	u8 udpf;		/* dword 1 */
	u8 ipcksm;		/* dword 1 */
	u8 l4_cksm;		/* dword 1 */
	u8 ip_version;		/* dword 1 */
	u8 macdst[7];		/* dword 1 */
	u8 rsvd0;		/* dword 1 */
	u8 fragndx[10];		/* dword 1 */
	u8 ct[2];		/* dword 1 */
	u8 sw;			/* dword 1 */
	u8 numfrags[3];		/* dword 1 */
	u8 rss_flush;		/* dword 2 */
	u8 cast_enc[2];		/* dword 2 */
	u8 vtm;			/* dword 2 */
	u8 rss_bank;		/* dword 2 */
	u8 port[2];		/* dword 2 */
	u8 vntagp;		/* dword 2 */
	u8 header_len[8];	/* dword 2 */
	u8 header_split[2];	/* dword 2 */
	u8 rsvd1[13];		/* dword 2 */
	u8 valid;		/* dword 2 */
	u8 rsshash[32];		/* dword 3 */
} __packed;

struct be_eth_rx_compl {
	u32 dw[4];
};

struct mgmt_hba_attribs {
	u8 flashrom_version_string[32];
	u8 manufacturer_name[32];
	u32 supported_modes;
	u32 rsvd0[3];
	u8 ncsi_ver_string[12];
	u32 default_extended_timeout;
	u8 controller_model_number[32];
	u8 controller_description[64];
	u8 controller_serial_number[32];
	u8 ip_version_string[32];
	u8 firmware_version_string[32];
	u8 bios_version_string[32];
	u8 redboot_version_string[32];
	u8 driver_version_string[32];
	u8 fw_on_flash_version_string[32];
	u32 functionalities_supported;
	u16 max_cdblength;
	u8 asic_revision;
	u8 generational_guid[16];
	u8 hba_port_count;
	u16 default_link_down_timeout;
	u8 iscsi_ver_min_max;
	u8 multifunction_device;
	u8 cache_valid;
	u8 hba_status;
	u8 max_domains_supported;
	u8 phy_port;
	u32 firmware_post_status;
	u32 hba_mtu[8];
	u32 rsvd1[4];
};

struct mgmt_controller_attrib {
	struct mgmt_hba_attribs hba_attribs;
	u16 pci_vendor_id;
	u16 pci_device_id;
	u16 pci_sub_vendor_id;
	u16 pci_sub_system_id;
	u8 pci_bus_number;
	u8 pci_device_number;
	u8 pci_function_number;
	u8 interface_type;
	u64 unique_identifier;
	u32 rsvd0[5];
};

struct controller_id {
	u32 vendor;
	u32 device;
	u32 subvendor;
	u32 subdevice;
};

struct flash_comp {
	unsigned long offset;
	int optype;
	int size;
	int img_type;
};

struct image_hdr {
	u32 imageid;
	u32 imageoffset;
	u32 imagelength;
	u32 image_checksum;
	u8 image_version[32];
};
struct flash_file_hdr_g2 {
	u8 sign[32];
	u32 cksum;
	u32 antidote;
	struct controller_id cont_id;
	u32 file_len;
	u32 chunk_num;
	u32 total_chunks;
	u32 num_imgs;
	u8 build[24];
};

struct flash_file_hdr_g3 {
	u8 sign[52];
	u8 ufi_version[4];
	u32 file_len;
	u32 cksum;
	u32 antidote;
	u32 num_imgs;
	u8 build[24];
	u8 asic_type_rev;
	u8 rsvd[31];
};

struct flash_section_hdr {
	u32 format_rev;
	u32 cksum;
	u32 antidote;
	u32 num_images;
	u8 id_string[128];
	u32 rsvd[4];
} __packed;

struct flash_section_hdr_g2 {
	u32 format_rev;
	u32 cksum;
	u32 antidote;
	u32 build_num;
	u8 id_string[128];
	u32 rsvd[8];
} __packed;

struct flash_section_entry {
	u32 type;
	u32 offset;
	u32 pad_size;
	u32 image_size;
	u32 cksum;
	u32 entry_point;
	u32 rsvd0;
	u32 rsvd1;
	u8 ver_data[32];
} __packed;

struct flash_section_info {
	u8 cookie[32];
	struct flash_section_hdr fsec_hdr;
	struct flash_section_entry fsec_entry[32];
} __packed;

struct flash_section_info_g2 {
	u8 cookie[32];
	struct flash_section_hdr_g2 fsec_hdr;
	struct flash_section_entry fsec_entry[32];
} __packed;
Commit	Line	Data
6b7c5b94	1	/*
c7bb15a6	2	* Copyright (C) 2005 - 2013 Emulex
6b7c5b94 SP	3	* All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation. The full GNU General
	8	* Public License is included in this distribution in the file called COPYING.
	9	*
	10	* Contact Information:
d2145cde	11	* linux-drivers@emulex.com
6b7c5b94	12	*
d2145cde AK	13	* Emulex
	14	* 3333 Susan Street
	15	* Costa Mesa, CA 92626
6b7c5b94 SP	16	*/
	17
	18	/******* Mailbox door bell ***********/
	19	/* Used for driver communication with the FW.
	20	* The software must write this register twice to post any command. First,
	21	* it writes the register with hi=1 and the upper bits of the physical address
	22	* for the MAILBOX structure. Software must poll the ready bit until this
	23	* is acknowledged. Then, sotware writes the register with hi=0 with the lower
	24	* bits in the address. It must poll the ready bit until the command is
	25	* complete. Upon completion, the MAILBOX will contain a valid completion
	26	* queue entry.
	27	*/
	28	#define MPU_MAILBOX_DB_OFFSET 0x160
	29	#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
	30	#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
	31
	32	#define MPU_EP_CONTROL 0
	33
1bc8e7e4	34	/******** MPU semphore: used for SH & BE ***********/
c5b3ad4c SP	35	#define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
c5b3ad4c SP	36	#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
1bc8e7e4 SP	37	#define POST_STAGE_MASK 0x0000FFFF
	38	#define POST_ERR_MASK 0x1
	39	#define POST_ERR_SHIFT 31
fe6d2a38	40
6b7c5b94 SP	41	/* MPU semphore POST stage values */
	42	#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
	43	#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
	44	#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
	45	#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
	46
37eed1cb	47
f67ef7ba	48	/* Lancer SLIPORT registers */
37eed1cb PR	49	#define SLIPORT_STATUS_OFFSET 0x404
37eed1cb PR	50	#define SLIPORT_CONTROL_OFFSET 0x408
e1cfb67a PR	51	#define SLIPORT_ERROR1_OFFSET 0x40C
e1cfb67a PR	52	#define SLIPORT_ERROR2_OFFSET 0x410
f67ef7ba	53	#define PHYSDEV_CONTROL_OFFSET 0x414
37eed1cb PR	54
37eed1cb PR	55	#define SLIPORT_STATUS_ERR_MASK 0x80000000
5c510811	56	#define SLIPORT_STATUS_DIP_MASK 0x02000000
37eed1cb PR	57	#define SLIPORT_STATUS_RN_MASK 0x01000000
37eed1cb PR	58	#define SLIPORT_STATUS_RDY_MASK 0x00800000
37eed1cb	59	#define SLI_PORT_CONTROL_IP_MASK 0x08000000
f67ef7ba	60	#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002
5c510811	61	#define PHYSDEV_CONTROL_DD_MASK 0x00000004
f67ef7ba	62	#define PHYSDEV_CONTROL_INP_MASK 0x40000000
37eed1cb	63
67297ad8 PR	64	#define SLIPORT_ERROR_NO_RESOURCE1 0x2
	65	#define SLIPORT_ERROR_NO_RESOURCE2 0x9
	66
6b7c5b94 SP	67	/******* Memory BAR register **********/
	68	#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
	69	/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
	70	* Disable" may still globally block interrupts in addition to individual
	71	* interrupt masks; a mechanism for the device driver to block all interrupts
	72	* atomically without having to arbitrate for the PCI Interrupt Disable bit
	73	* with the OS.
	74	*/
	75	#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
6b7c5b94	76
94d73aaa VV	77	/******* PCI Function Capability *******/
	78	#define BE_FUNCTION_CAPS_RSS 0x2
	79	#define BE_FUNCTION_CAPS_SUPER_NIC 0x40
	80
65155b37	81	/******* Power management (WOL) ********/
71d8d1b5 AK	82	#define PCICFG_PM_CONTROL_OFFSET 0x44
	83	#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
	84
7c185276 AK	85	/******* Online Control Registers *****/
	86	#define PCICFG_ONLINE0 0xB0
	87	#define PCICFG_ONLINE1 0xB4
	88
	89	/******* UE Status and Mask Registers */
	90	#define PCICFG_UE_STATUS_LOW 0xA0
	91	#define PCICFG_UE_STATUS_HIGH 0xA4
	92	#define PCICFG_UE_STATUS_LOW_MASK 0xA8
	93	#define PCICFG_UE_STATUS_HI_MASK 0xAC
	94
fe6d2a38 SP	95	/****** SLI_INTF *********************/
	96	#define SLI_INTF_REG_OFFSET 0x58
	97	#define SLI_INTF_VALID_MASK 0xE0000000
	98	#define SLI_INTF_VALID 0xC0000000
	99	#define SLI_INTF_HINT2_MASK 0x1F000000
	100	#define SLI_INTF_HINT2_SHIFT 24
	101	#define SLI_INTF_HINT1_MASK 0x00FF0000
	102	#define SLI_INTF_HINT1_SHIFT 16
	103	#define SLI_INTF_FAMILY_MASK 0x00000F00
	104	#define SLI_INTF_FAMILY_SHIFT 8
	105	#define SLI_INTF_IF_TYPE_MASK 0x0000F000
	106	#define SLI_INTF_IF_TYPE_SHIFT 12
	107	#define SLI_INTF_REV_MASK 0x000000F0
	108	#define SLI_INTF_REV_SHIFT 4
	109	#define SLI_INTF_FT_MASK 0x00000001
	110
045508a8 PP	111	#define SLI_INTF_TYPE_2 2
045508a8 PP	112	#define SLI_INTF_TYPE_3 3
fe6d2a38	113
c001c213 SP	114	/******* ISR0 Register offset ********/
	115	#define CEV_ISR0_OFFSET 0xC18
	116	#define CEV_ISR_SIZE 4
	117
6b7c5b94 SP	118	/******* Event Q door bell ***********/
	119	#define DB_EQ_OFFSET DB_CQ_OFFSET
	120	#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
fe6d2a38 SP	121	#define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
	122	#define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
	123
6b7c5b94 SP	124	/* Clear the interrupt for this eq */
	125	#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
	126	/* Must be 1 */
5fb379ee	127	#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
6b7c5b94 SP	128	/* Number of event entries processed */
	129	#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
	130	/* Rearm bit */
	131	#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
	132
	133	/******* Compl Q door bell ***********/
	134	#define DB_CQ_OFFSET 0x120
	135	#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
fe6d2a38 SP	136	#define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
	137	#define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
	138	placing at 11-15 */
	139
6b7c5b94 SP	140	/* Number of event entries processed */
	141	#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
	142	/* Rearm bit */
	143	#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
	144
	145	/******** TX ULP door bell ***********/
	146	#define DB_TXULP1_OFFSET 0x60
	147	#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
	148	/* Number of tx entries posted */
	149	#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
	150	#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
	151
	152	/******** RQ(erx) door bell **********/
	153	#define DB_RQ_OFFSET 0x100
	154	#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
	155	/* Number of rx frags posted */
	156	#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
	157
5fb379ee SP	158	/******** MCC door bell **********/
	159	#define DB_MCCQ_OFFSET 0x140
	160	#define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
	161	/* Number of entries posted */
	162	#define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
	163
ba343c77 SB	164	/******** SRIOV VF PCICFG OFFSET ******/
	165	#define SRIOV_VF_PCICFG_OFFSET (4096)
	166
311fddc7 SK	167	/******** FAT TABLE ******/
	168	#define RETRIEVE_FAT 0
	169	#define QUERY_FAT 1
	170
3f0d4560	171	/* Flashrom related descriptors */
c165541e	172	#define MAX_FLASH_COMP 32
3f0d4560 AK	173	#define IMAGE_TYPE_FIRMWARE 160
	174	#define IMAGE_TYPE_BOOTCODE 224
	175	#define IMAGE_TYPE_OPTIONROM 32
	176
	177	#define NUM_FLASHDIR_ENTRIES 32
	178
c165541e PR	179	#define OPTYPE_ISCSI_ACTIVE 0
	180	#define OPTYPE_REDBOOT 1
	181	#define OPTYPE_BIOS 2
	182	#define OPTYPE_PXE_BIOS 3
	183	#define OPTYPE_FCOE_BIOS 8
	184	#define OPTYPE_ISCSI_BACKUP 9
	185	#define OPTYPE_FCOE_FW_ACTIVE 10
	186	#define OPTYPE_FCOE_FW_BACKUP 11
	187	#define OPTYPE_NCSI_FW 13
	188	#define OPTYPE_PHY_FW 99
306f1348	189	#define TN_8022 13
3f0d4560	190
306f1348 SP	191	#define ILLEGAL_IOCTL_REQ 2
	192	#define FLASHROM_OPER_PHY_FLASH 9
	193	#define FLASHROM_OPER_PHY_SAVE 10
3f0d4560 AK	194	#define FLASHROM_OPER_FLASH 1
	195	#define FLASHROM_OPER_SAVE 2
	196	#define FLASHROM_OPER_REPORT 4
	197
306f1348 SP	198	#define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image size */
	199	#define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM image sz */
	200	#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
	201	#define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max firmware image size */
	202	#define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM image sz */
	203	#define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
	204	#define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144)
	205	#define FLASH_PHY_FW_IMAGE_MAX_SIZE_g3 262144
3f0d4560 AK	206
	207	#define FLASH_NCSI_MAGIC (0x16032009)
	208	#define FLASH_NCSI_DISABLED (0)
	209	#define FLASH_NCSI_ENABLED (1)
	210
	211	#define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
	212
	213	/* Offsets for components on Flash. */
	214	#define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
	215	#define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
	216	#define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
	217	#define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
	218	#define FLASH_iSCSI_BIOS_START_g2 (7340032)
	219	#define FLASH_PXE_BIOS_START_g2 (7864320)
	220	#define FLASH_FCoE_BIOS_START_g2 (524288)
	221	#define FLASH_REDBOOT_START_g2 (0)
	222
9fe96934	223	#define FLASH_NCSI_START_g3 (15990784)
3f0d4560 AK	224	#define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
	225	#define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
	226	#define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
	227	#define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
	228	#define FLASH_iSCSI_BIOS_START_g3 (12582912)
	229	#define FLASH_PXE_BIOS_START_g3 (13107200)
	230	#define FLASH_FCoE_BIOS_START_g3 (13631488)
	231	#define FLASH_REDBOOT_START_g3 (262144)
306f1348	232	#define FLASH_PHY_FW_START_g3 1310720
3f0d4560	233
c165541e PR	234	#define IMAGE_NCSI 16
	235	#define IMAGE_OPTION_ROM_PXE 32
	236	#define IMAGE_OPTION_ROM_FCoE 33
	237	#define IMAGE_OPTION_ROM_ISCSI 34
	238	#define IMAGE_FLASHISM_JUMPVECTOR 48
	239	#define IMAGE_FLASH_ISM 49
	240	#define IMAGE_JUMP_VECTOR 50
	241	#define IMAGE_FIRMWARE_iSCSI 160
	242	#define IMAGE_FIRMWARE_COMP_iSCSI 161
	243	#define IMAGE_FIRMWARE_FCoE 162
	244	#define IMAGE_FIRMWARE_COMP_FCoE 163
	245	#define IMAGE_FIRMWARE_BACKUP_iSCSI 176
	246	#define IMAGE_FIRMWARE_BACKUP_COMP_iSCSI 177
	247	#define IMAGE_FIRMWARE_BACKUP_FCoE 178
	248	#define IMAGE_FIRMWARE_BACKUP_COMP_FCoE 179
	249	#define IMAGE_FIRMWARE_PHY 192
	250	#define IMAGE_BOOT_CODE 224
	251
1ef78abe AK	252	/*********** Rx Packet Type Encoding ************/
	253	#define BE_UNICAST_PACKET 0
	254	#define BE_MULTICAST_PACKET 1
	255	#define BE_BROADCAST_PACKET 2
	256	#define BE_RSVD_PACKET 3
3f0d4560	257
6b7c5b94 SP	258	/*
	259	* BE descriptors: host memory data structures whose formats
	260	* are hardwired in BE silicon.
	261	*/
	262	/* Event Queue Descriptor */
	263	#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
	264	#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
	265	#define EQ_ENTRY_RES_ID_SHIFT 16
3f0d4560	266
6b7c5b94 SP	267	struct be_eq_entry {
	268	u32 evt;
	269	};
	270
	271	/* TX Queue Descriptor */
	272	#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
	273	struct be_eth_wrb {
	274	u32 frag_pa_hi; /* dword 0 */
	275	u32 frag_pa_lo; /* dword 1 */
	276	u32 rsvd0; /* dword 2 */
	277	u32 frag_len; /* dword 3: bits 0 - 15 */
	278	} __packed;
	279
	280	/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
	281	* actual structure is defined as a byte : used to calculate
	282	* offset/shift/mask of each field */
	283	struct amap_eth_hdr_wrb {
	284	u8 rsvd0[32]; /* dword 0 */
	285	u8 rsvd1[32]; /* dword 1 */
	286	u8 complete; /* dword 2 */
	287	u8 event;
	288	u8 crc;
	289	u8 forward;
49e4b847	290	u8 lso6;
6b7c5b94 SP	291	u8 mgmt;
	292	u8 ipcs;
	293	u8 udpcs;
	294	u8 tcpcs;
	295	u8 lso;
	296	u8 vlan;
	297	u8 gso[2];
	298	u8 num_wrb[5];
	299	u8 lso_mss[14];
	300	u8 len[16]; /* dword 3 */
	301	u8 vlan_tag[16];
	302	} __packed;
	303
	304	struct be_eth_hdr_wrb {
	305	u32 dw[4];
	306	};
	307
	308	/* TX Compl Queue Descriptor */
	309
	310	/* Pseudo amap definition for eth_tx_compl in which each bit of the
	311	* actual structure is defined as a byte: used to calculate
	312	* offset/shift/mask of each field */
	313	struct amap_eth_tx_compl {
	314	u8 wrb_index[16]; /* dword 0 */
	315	u8 ct[2]; /* dword 0 */
	316	u8 port[2]; /* dword 0 */
	317	u8 rsvd0[8]; /* dword 0 */
	318	u8 status[4]; /* dword 0 */
	319	u8 user_bytes[16]; /* dword 1 */
	320	u8 nwh_bytes[8]; /* dword 1 */
	321	u8 lso; /* dword 1 */
	322	u8 cast_enc[2]; /* dword 1 */
	323	u8 rsvd1[5]; /* dword 1 */
	324	u8 rsvd2[32]; /* dword 2 */
	325	u8 pkts[16]; /* dword 3 */
	326	u8 ringid[11]; /* dword 3 */
	327	u8 hash_val[4]; /* dword 3 */
	328	u8 valid; /* dword 3 */
	329	} __packed;
	330
	331	struct be_eth_tx_compl {
	332	u32 dw[4];
	333	};
	334
	335	/* RX Queue Descriptor */
	336	struct be_eth_rx_d {
	337	u32 fragpa_hi;
	338	u32 fragpa_lo;
	339	};
	340
	341	/* RX Compl Queue Descriptor */
	342
2e588f84 SP	343	/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
2e588f84 SP	344	* each bit of the actual structure is defined as a byte: used to calculate
6b7c5b94	345	* offset/shift/mask of each field */
2e588f84	346	struct amap_eth_rx_compl_v0 {
6b7c5b94 SP	347	u8 vlan_tag[16]; /* dword 0 */
	348	u8 pktsize[14]; /* dword 0 */
	349	u8 port; /* dword 0 */
	350	u8 ip_opt; /* dword 0 */
	351	u8 err; /* dword 1 */
	352	u8 rsshp; /* dword 1 */
	353	u8 ipf; /* dword 1 */
	354	u8 tcpf; /* dword 1 */
	355	u8 udpf; /* dword 1 */
	356	u8 ipcksm; /* dword 1 */
	357	u8 l4_cksm; /* dword 1 */
	358	u8 ip_version; /* dword 1 */
	359	u8 macdst[6]; /* dword 1 */
	360	u8 vtp; /* dword 1 */
	361	u8 rsvd0; /* dword 1 */
	362	u8 fragndx[10]; /* dword 1 */
	363	u8 ct[2]; /* dword 1 */
	364	u8 sw; /* dword 1 */
	365	u8 numfrags[3]; /* dword 1 */
	366	u8 rss_flush; /* dword 2 */
	367	u8 cast_enc[2]; /* dword 2 */
84517482	368	u8 vtm; /* dword 2 */
6b7c5b94 SP	369	u8 rss_bank; /* dword 2 */
	370	u8 rsvd1[23]; /* dword 2 */
	371	u8 lro_pkt; /* dword 2 */
	372	u8 rsvd2[2]; /* dword 2 */
	373	u8 valid; /* dword 2 */
	374	u8 rsshash[32]; /* dword 3 */
	375	} __packed;
	376
2e588f84 SP	377	/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
	378	* each bit of the actual structure is defined as a byte: used to calculate
	379	* offset/shift/mask of each field */
	380	struct amap_eth_rx_compl_v1 {
	381	u8 vlan_tag[16]; /* dword 0 */
	382	u8 pktsize[14]; /* dword 0 */
	383	u8 vtp; /* dword 0 */
	384	u8 ip_opt; /* dword 0 */
	385	u8 err; /* dword 1 */
	386	u8 rsshp; /* dword 1 */
	387	u8 ipf; /* dword 1 */
	388	u8 tcpf; /* dword 1 */
	389	u8 udpf; /* dword 1 */
	390	u8 ipcksm; /* dword 1 */
	391	u8 l4_cksm; /* dword 1 */
	392	u8 ip_version; /* dword 1 */
	393	u8 macdst[7]; /* dword 1 */
	394	u8 rsvd0; /* dword 1 */
	395	u8 fragndx[10]; /* dword 1 */
	396	u8 ct[2]; /* dword 1 */
	397	u8 sw; /* dword 1 */
	398	u8 numfrags[3]; /* dword 1 */
	399	u8 rss_flush; /* dword 2 */
	400	u8 cast_enc[2]; /* dword 2 */
	401	u8 vtm; /* dword 2 */
	402	u8 rss_bank; /* dword 2 */
	403	u8 port[2]; /* dword 2 */
	404	u8 vntagp; /* dword 2 */
	405	u8 header_len[8]; /* dword 2 */
	406	u8 header_split[2]; /* dword 2 */
	407	u8 rsvd1[13]; /* dword 2 */
	408	u8 valid; /* dword 2 */
	409	u8 rsshash[32]; /* dword 3 */
	410	} __packed;
	411
6b7c5b94 SP	412	struct be_eth_rx_compl {
	413	u32 dw[4];
	414	};
84517482	415
9e1453c5 AK	416	struct mgmt_hba_attribs {
	417	u8 flashrom_version_string[32];
	418	u8 manufacturer_name[32];
	419	u32 supported_modes;
	420	u32 rsvd0[3];
	421	u8 ncsi_ver_string[12];
	422	u32 default_extended_timeout;
	423	u8 controller_model_number[32];
	424	u8 controller_description[64];
	425	u8 controller_serial_number[32];
	426	u8 ip_version_string[32];
	427	u8 firmware_version_string[32];
	428	u8 bios_version_string[32];
	429	u8 redboot_version_string[32];
	430	u8 driver_version_string[32];
	431	u8 fw_on_flash_version_string[32];
	432	u32 functionalities_supported;
	433	u16 max_cdblength;
	434	u8 asic_revision;
	435	u8 generational_guid[16];
	436	u8 hba_port_count;
	437	u16 default_link_down_timeout;
	438	u8 iscsi_ver_min_max;
	439	u8 multifunction_device;
	440	u8 cache_valid;
	441	u8 hba_status;
	442	u8 max_domains_supported;
	443	u8 phy_port;
	444	u32 firmware_post_status;
	445	u32 hba_mtu[8];
	446	u32 rsvd1[4];
	447	};
	448
	449	struct mgmt_controller_attrib {
	450	struct mgmt_hba_attribs hba_attribs;
	451	u16 pci_vendor_id;
	452	u16 pci_device_id;
	453	u16 pci_sub_vendor_id;
	454	u16 pci_sub_system_id;
	455	u8 pci_bus_number;
	456	u8 pci_device_number;
	457	u8 pci_function_number;
	458	u8 interface_type;
	459	u64 unique_identifier;
	460	u32 rsvd0[5];
	461	};
	462
84517482 AK	463	struct controller_id {
	464	u32 vendor;
	465	u32 device;
	466	u32 subvendor;
	467	u32 subdevice;
	468	};
	469
3f0d4560 AK	470	struct flash_comp {
	471	unsigned long offset;
	472	int optype;
	473	int size;
c165541e	474	int img_type;
3f0d4560 AK	475	};
	476
	477	struct image_hdr {
	478	u32 imageid;
	479	u32 imageoffset;
	480	u32 imagelength;
	481	u32 image_checksum;
	482	u8 image_version[32];
	483	};
	484	struct flash_file_hdr_g2 {
84517482 AK	485	u8 sign[32];
	486	u32 cksum;
	487	u32 antidote;
	488	struct controller_id cont_id;
	489	u32 file_len;
	490	u32 chunk_num;
	491	u32 total_chunks;
	492	u32 num_imgs;
	493	u8 build[24];
	494	};
	495
3f0d4560 AK	496	struct flash_file_hdr_g3 {
	497	u8 sign[52];
	498	u8 ufi_version[4];
	499	u32 file_len;
	500	u32 cksum;
	501	u32 antidote;
	502	u32 num_imgs;
	503	u8 build[24];
0ad3157e VV	504	u8 asic_type_rev;
0ad3157e VV	505	u8 rsvd[31];
3f0d4560 AK	506	};
3f0d4560 AK	507
84517482 AK	508	struct flash_section_hdr {
	509	u32 format_rev;
	510	u32 cksum;
	511	u32 antidote;
c165541e PR	512	u32 num_images;
	513	u8 id_string[128];
	514	u32 rsvd[4];
	515	} __packed;
	516
	517	struct flash_section_hdr_g2 {
	518	u32 format_rev;
	519	u32 cksum;
	520	u32 antidote;
	521	u32 build_num;
	522	u8 id_string[128];
	523	u32 rsvd[8];
	524	} __packed;
84517482 AK	525
	526	struct flash_section_entry {
	527	u32 type;
	528	u32 offset;
	529	u32 pad_size;
	530	u32 image_size;
	531	u32 cksum;
	532	u32 entry_point;
	533	u32 rsvd0;
	534	u32 rsvd1;
	535	u8 ver_data[32];
c165541e	536	} __packed;
84517482 AK	537
	538	struct flash_section_info {
	539	u8 cookie[32];
	540	struct flash_section_hdr fsec_hdr;
	541	struct flash_section_entry fsec_entry[32];
c165541e PR	542	} __packed;
	543
	544	struct flash_section_info_g2 {
	545	u8 cookie[32];
	546	struct flash_section_hdr_g2 fsec_hdr;
	547	struct flash_section_entry fsec_entry[32];
	548	} __packed;