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69785b79 PYC |
1 | /* |
2 | * Faraday FTGMAC100 Gigabit Ethernet | |
3 | * | |
4 | * (C) Copyright 2009-2011 Faraday Technology | |
5 | * Po-Yu Chuang <ratbert@faraday-tech.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
23 | ||
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/ethtool.h> | |
17f1bbca | 27 | #include <linux/interrupt.h> |
69785b79 PYC |
28 | #include <linux/io.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/phy.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <net/ip.h> | |
34 | ||
35 | #include "ftgmac100.h" | |
36 | ||
37 | #define DRV_NAME "ftgmac100" | |
38 | #define DRV_VERSION "0.7" | |
39 | ||
40 | #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */ | |
41 | #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */ | |
42 | ||
43 | #define MAX_PKT_SIZE 1518 | |
44 | #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */ | |
45 | ||
46 | /****************************************************************************** | |
47 | * private data | |
48 | *****************************************************************************/ | |
49 | struct ftgmac100_descs { | |
50 | struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES]; | |
51 | struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES]; | |
52 | }; | |
53 | ||
54 | struct ftgmac100 { | |
55 | struct resource *res; | |
56 | void __iomem *base; | |
57 | int irq; | |
58 | ||
59 | struct ftgmac100_descs *descs; | |
60 | dma_addr_t descs_dma_addr; | |
61 | ||
62 | unsigned int rx_pointer; | |
63 | unsigned int tx_clean_pointer; | |
64 | unsigned int tx_pointer; | |
65 | unsigned int tx_pending; | |
66 | ||
67 | spinlock_t tx_lock; | |
68 | ||
69 | struct net_device *netdev; | |
70 | struct device *dev; | |
71 | struct napi_struct napi; | |
72 | ||
73 | struct mii_bus *mii_bus; | |
69785b79 PYC |
74 | struct phy_device *phydev; |
75 | int old_speed; | |
76 | }; | |
77 | ||
78 | static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, | |
79 | struct ftgmac100_rxdes *rxdes, gfp_t gfp); | |
80 | ||
81 | /****************************************************************************** | |
82 | * internal functions (hardware register access) | |
83 | *****************************************************************************/ | |
84 | #define INT_MASK_ALL_ENABLED (FTGMAC100_INT_RPKT_LOST | \ | |
85 | FTGMAC100_INT_XPKT_ETH | \ | |
86 | FTGMAC100_INT_XPKT_LOST | \ | |
87 | FTGMAC100_INT_AHB_ERR | \ | |
88 | FTGMAC100_INT_PHYSTS_CHG | \ | |
89 | FTGMAC100_INT_RPKT_BUF | \ | |
90 | FTGMAC100_INT_NO_RXBUF) | |
91 | ||
92 | static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr) | |
93 | { | |
94 | iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR); | |
95 | } | |
96 | ||
97 | static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv, | |
98 | unsigned int size) | |
99 | { | |
100 | size = FTGMAC100_RBSR_SIZE(size); | |
101 | iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR); | |
102 | } | |
103 | ||
104 | static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv, | |
105 | dma_addr_t addr) | |
106 | { | |
107 | iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR); | |
108 | } | |
109 | ||
110 | static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv) | |
111 | { | |
112 | iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD); | |
113 | } | |
114 | ||
115 | static int ftgmac100_reset_hw(struct ftgmac100 *priv) | |
116 | { | |
117 | struct net_device *netdev = priv->netdev; | |
118 | int i; | |
119 | ||
120 | /* NOTE: reset clears all registers */ | |
121 | iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR); | |
122 | for (i = 0; i < 5; i++) { | |
123 | unsigned int maccr; | |
124 | ||
125 | maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR); | |
126 | if (!(maccr & FTGMAC100_MACCR_SW_RST)) | |
127 | return 0; | |
128 | ||
129 | udelay(1000); | |
130 | } | |
131 | ||
132 | netdev_err(netdev, "software reset failed\n"); | |
133 | return -EIO; | |
134 | } | |
135 | ||
136 | static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac) | |
137 | { | |
138 | unsigned int maddr = mac[0] << 8 | mac[1]; | |
139 | unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; | |
140 | ||
141 | iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR); | |
142 | iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR); | |
143 | } | |
144 | ||
145 | static void ftgmac100_init_hw(struct ftgmac100 *priv) | |
146 | { | |
147 | /* setup ring buffer base registers */ | |
148 | ftgmac100_set_rx_ring_base(priv, | |
149 | priv->descs_dma_addr + | |
150 | offsetof(struct ftgmac100_descs, rxdes)); | |
151 | ftgmac100_set_normal_prio_tx_ring_base(priv, | |
152 | priv->descs_dma_addr + | |
153 | offsetof(struct ftgmac100_descs, txdes)); | |
154 | ||
155 | ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE); | |
156 | ||
157 | iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC); | |
158 | ||
159 | ftgmac100_set_mac(priv, priv->netdev->dev_addr); | |
160 | } | |
161 | ||
162 | #define MACCR_ENABLE_ALL (FTGMAC100_MACCR_TXDMA_EN | \ | |
163 | FTGMAC100_MACCR_RXDMA_EN | \ | |
164 | FTGMAC100_MACCR_TXMAC_EN | \ | |
165 | FTGMAC100_MACCR_RXMAC_EN | \ | |
166 | FTGMAC100_MACCR_FULLDUP | \ | |
167 | FTGMAC100_MACCR_CRC_APD | \ | |
168 | FTGMAC100_MACCR_RX_RUNT | \ | |
169 | FTGMAC100_MACCR_RX_BROADPKT) | |
170 | ||
171 | static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed) | |
172 | { | |
173 | int maccr = MACCR_ENABLE_ALL; | |
174 | ||
175 | switch (speed) { | |
176 | default: | |
177 | case 10: | |
178 | break; | |
179 | ||
180 | case 100: | |
181 | maccr |= FTGMAC100_MACCR_FAST_MODE; | |
182 | break; | |
183 | ||
184 | case 1000: | |
185 | maccr |= FTGMAC100_MACCR_GIGA_MODE; | |
186 | break; | |
187 | } | |
188 | ||
189 | iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR); | |
190 | } | |
191 | ||
192 | static void ftgmac100_stop_hw(struct ftgmac100 *priv) | |
193 | { | |
194 | iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR); | |
195 | } | |
196 | ||
197 | /****************************************************************************** | |
198 | * internal functions (receive descriptor) | |
199 | *****************************************************************************/ | |
200 | static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes) | |
201 | { | |
202 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS); | |
203 | } | |
204 | ||
205 | static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes) | |
206 | { | |
207 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS); | |
208 | } | |
209 | ||
210 | static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes) | |
211 | { | |
212 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY); | |
213 | } | |
214 | ||
215 | static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes) | |
216 | { | |
217 | /* clear status bits */ | |
218 | rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR); | |
219 | } | |
220 | ||
221 | static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes) | |
222 | { | |
223 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR); | |
224 | } | |
225 | ||
226 | static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes) | |
227 | { | |
228 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR); | |
229 | } | |
230 | ||
231 | static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes) | |
232 | { | |
233 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL); | |
234 | } | |
235 | ||
236 | static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes) | |
237 | { | |
238 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT); | |
239 | } | |
240 | ||
241 | static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes) | |
242 | { | |
243 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB); | |
244 | } | |
245 | ||
246 | static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes) | |
247 | { | |
248 | return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC; | |
249 | } | |
250 | ||
251 | static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes) | |
252 | { | |
253 | return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST); | |
254 | } | |
255 | ||
256 | static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes) | |
257 | { | |
258 | rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR); | |
259 | } | |
260 | ||
261 | static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes, | |
262 | dma_addr_t addr) | |
263 | { | |
264 | rxdes->rxdes3 = cpu_to_le32(addr); | |
265 | } | |
266 | ||
267 | static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes) | |
268 | { | |
269 | return le32_to_cpu(rxdes->rxdes3); | |
270 | } | |
271 | ||
272 | static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes) | |
273 | { | |
274 | return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == | |
275 | cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP); | |
276 | } | |
277 | ||
278 | static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes) | |
279 | { | |
280 | return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) == | |
281 | cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP); | |
282 | } | |
283 | ||
284 | static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes) | |
285 | { | |
286 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR); | |
287 | } | |
288 | ||
289 | static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes) | |
290 | { | |
291 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR); | |
292 | } | |
293 | ||
294 | static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes) | |
295 | { | |
296 | return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR); | |
297 | } | |
298 | ||
299 | /* | |
300 | * rxdes2 is not used by hardware. We use it to keep track of page. | |
301 | * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). | |
302 | */ | |
303 | static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page) | |
304 | { | |
305 | rxdes->rxdes2 = (unsigned int)page; | |
306 | } | |
307 | ||
308 | static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes) | |
309 | { | |
310 | return (struct page *)rxdes->rxdes2; | |
311 | } | |
312 | ||
313 | /****************************************************************************** | |
314 | * internal functions (receive) | |
315 | *****************************************************************************/ | |
316 | static int ftgmac100_next_rx_pointer(int pointer) | |
317 | { | |
318 | return (pointer + 1) & (RX_QUEUE_ENTRIES - 1); | |
319 | } | |
320 | ||
321 | static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv) | |
322 | { | |
323 | priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer); | |
324 | } | |
325 | ||
326 | static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv) | |
327 | { | |
328 | return &priv->descs->rxdes[priv->rx_pointer]; | |
329 | } | |
330 | ||
331 | static struct ftgmac100_rxdes * | |
332 | ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv) | |
333 | { | |
334 | struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); | |
335 | ||
336 | while (ftgmac100_rxdes_packet_ready(rxdes)) { | |
337 | if (ftgmac100_rxdes_first_segment(rxdes)) | |
338 | return rxdes; | |
339 | ||
340 | ftgmac100_rxdes_set_dma_own(rxdes); | |
341 | ftgmac100_rx_pointer_advance(priv); | |
342 | rxdes = ftgmac100_current_rxdes(priv); | |
343 | } | |
344 | ||
345 | return NULL; | |
346 | } | |
347 | ||
348 | static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv, | |
349 | struct ftgmac100_rxdes *rxdes) | |
350 | { | |
351 | struct net_device *netdev = priv->netdev; | |
352 | bool error = false; | |
353 | ||
354 | if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) { | |
355 | if (net_ratelimit()) | |
356 | netdev_info(netdev, "rx err\n"); | |
357 | ||
358 | netdev->stats.rx_errors++; | |
359 | error = true; | |
360 | } | |
361 | ||
362 | if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) { | |
363 | if (net_ratelimit()) | |
364 | netdev_info(netdev, "rx crc err\n"); | |
365 | ||
366 | netdev->stats.rx_crc_errors++; | |
367 | error = true; | |
368 | } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) { | |
369 | if (net_ratelimit()) | |
370 | netdev_info(netdev, "rx IP checksum err\n"); | |
371 | ||
372 | error = true; | |
373 | } | |
374 | ||
375 | if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) { | |
376 | if (net_ratelimit()) | |
377 | netdev_info(netdev, "rx frame too long\n"); | |
378 | ||
379 | netdev->stats.rx_length_errors++; | |
380 | error = true; | |
381 | } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) { | |
382 | if (net_ratelimit()) | |
383 | netdev_info(netdev, "rx runt\n"); | |
384 | ||
385 | netdev->stats.rx_length_errors++; | |
386 | error = true; | |
387 | } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) { | |
388 | if (net_ratelimit()) | |
389 | netdev_info(netdev, "rx odd nibble\n"); | |
390 | ||
391 | netdev->stats.rx_length_errors++; | |
392 | error = true; | |
393 | } | |
394 | ||
395 | return error; | |
396 | } | |
397 | ||
398 | static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv) | |
399 | { | |
400 | struct net_device *netdev = priv->netdev; | |
401 | struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv); | |
402 | bool done = false; | |
403 | ||
404 | if (net_ratelimit()) | |
405 | netdev_dbg(netdev, "drop packet %p\n", rxdes); | |
406 | ||
407 | do { | |
408 | if (ftgmac100_rxdes_last_segment(rxdes)) | |
409 | done = true; | |
410 | ||
411 | ftgmac100_rxdes_set_dma_own(rxdes); | |
412 | ftgmac100_rx_pointer_advance(priv); | |
413 | rxdes = ftgmac100_current_rxdes(priv); | |
414 | } while (!done && ftgmac100_rxdes_packet_ready(rxdes)); | |
415 | ||
416 | netdev->stats.rx_dropped++; | |
417 | } | |
418 | ||
419 | static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed) | |
420 | { | |
421 | struct net_device *netdev = priv->netdev; | |
422 | struct ftgmac100_rxdes *rxdes; | |
423 | struct sk_buff *skb; | |
424 | bool done = false; | |
425 | ||
426 | rxdes = ftgmac100_rx_locate_first_segment(priv); | |
427 | if (!rxdes) | |
428 | return false; | |
429 | ||
430 | if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) { | |
431 | ftgmac100_rx_drop_packet(priv); | |
432 | return true; | |
433 | } | |
434 | ||
435 | /* start processing */ | |
436 | skb = netdev_alloc_skb_ip_align(netdev, 128); | |
437 | if (unlikely(!skb)) { | |
438 | if (net_ratelimit()) | |
439 | netdev_err(netdev, "rx skb alloc failed\n"); | |
440 | ||
441 | ftgmac100_rx_drop_packet(priv); | |
442 | return true; | |
443 | } | |
444 | ||
445 | if (unlikely(ftgmac100_rxdes_multicast(rxdes))) | |
446 | netdev->stats.multicast++; | |
447 | ||
448 | /* | |
449 | * It seems that HW does checksum incorrectly with fragmented packets, | |
450 | * so we are conservative here - if HW checksum error, let software do | |
451 | * the checksum again. | |
452 | */ | |
453 | if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) || | |
454 | (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes))) | |
455 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
456 | ||
457 | do { | |
458 | dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); | |
459 | struct page *page = ftgmac100_rxdes_get_page(rxdes); | |
460 | unsigned int size; | |
461 | ||
462 | dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
463 | ||
464 | size = ftgmac100_rxdes_data_length(rxdes); | |
465 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size); | |
466 | ||
467 | skb->len += size; | |
468 | skb->data_len += size; | |
5935f81c | 469 | skb->truesize += PAGE_SIZE; |
69785b79 PYC |
470 | |
471 | if (ftgmac100_rxdes_last_segment(rxdes)) | |
472 | done = true; | |
473 | ||
474 | ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC); | |
475 | ||
476 | ftgmac100_rx_pointer_advance(priv); | |
477 | rxdes = ftgmac100_current_rxdes(priv); | |
478 | } while (!done); | |
479 | ||
6ecd09dd ED |
480 | /* Small frames are copied into linear part of skb to free one page */ |
481 | if (skb->len <= 128) { | |
5935f81c | 482 | skb->truesize -= PAGE_SIZE; |
6ecd09dd ED |
483 | __pskb_pull_tail(skb, skb->len); |
484 | } else { | |
485 | /* We pull the minimum amount into linear part */ | |
486 | __pskb_pull_tail(skb, ETH_HLEN); | |
487 | } | |
69785b79 PYC |
488 | skb->protocol = eth_type_trans(skb, netdev); |
489 | ||
490 | netdev->stats.rx_packets++; | |
491 | netdev->stats.rx_bytes += skb->len; | |
492 | ||
493 | /* push packet to protocol stack */ | |
494 | napi_gro_receive(&priv->napi, skb); | |
495 | ||
496 | (*processed)++; | |
497 | return true; | |
498 | } | |
499 | ||
500 | /****************************************************************************** | |
501 | * internal functions (transmit descriptor) | |
502 | *****************************************************************************/ | |
503 | static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes) | |
504 | { | |
505 | /* clear all except end of ring bit */ | |
506 | txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); | |
507 | txdes->txdes1 = 0; | |
508 | txdes->txdes2 = 0; | |
509 | txdes->txdes3 = 0; | |
510 | } | |
511 | ||
512 | static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes) | |
513 | { | |
514 | return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); | |
515 | } | |
516 | ||
517 | static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes) | |
518 | { | |
519 | /* | |
520 | * Make sure dma own bit will not be set before any other | |
521 | * descriptor fields. | |
522 | */ | |
523 | wmb(); | |
524 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN); | |
525 | } | |
526 | ||
527 | static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes) | |
528 | { | |
529 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR); | |
530 | } | |
531 | ||
532 | static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes) | |
533 | { | |
534 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS); | |
535 | } | |
536 | ||
537 | static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes) | |
538 | { | |
539 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS); | |
540 | } | |
541 | ||
542 | static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes, | |
543 | unsigned int len) | |
544 | { | |
545 | txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len)); | |
546 | } | |
547 | ||
548 | static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes) | |
549 | { | |
550 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC); | |
551 | } | |
552 | ||
553 | static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes) | |
554 | { | |
555 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM); | |
556 | } | |
557 | ||
558 | static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes) | |
559 | { | |
560 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM); | |
561 | } | |
562 | ||
563 | static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes) | |
564 | { | |
565 | txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM); | |
566 | } | |
567 | ||
568 | static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes, | |
569 | dma_addr_t addr) | |
570 | { | |
571 | txdes->txdes3 = cpu_to_le32(addr); | |
572 | } | |
573 | ||
574 | static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes) | |
575 | { | |
576 | return le32_to_cpu(txdes->txdes3); | |
577 | } | |
578 | ||
579 | /* | |
580 | * txdes2 is not used by hardware. We use it to keep track of socket buffer. | |
581 | * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu(). | |
582 | */ | |
583 | static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes, | |
584 | struct sk_buff *skb) | |
585 | { | |
586 | txdes->txdes2 = (unsigned int)skb; | |
587 | } | |
588 | ||
589 | static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes) | |
590 | { | |
591 | return (struct sk_buff *)txdes->txdes2; | |
592 | } | |
593 | ||
594 | /****************************************************************************** | |
595 | * internal functions (transmit) | |
596 | *****************************************************************************/ | |
597 | static int ftgmac100_next_tx_pointer(int pointer) | |
598 | { | |
599 | return (pointer + 1) & (TX_QUEUE_ENTRIES - 1); | |
600 | } | |
601 | ||
602 | static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv) | |
603 | { | |
604 | priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer); | |
605 | } | |
606 | ||
607 | static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv) | |
608 | { | |
609 | priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer); | |
610 | } | |
611 | ||
612 | static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv) | |
613 | { | |
614 | return &priv->descs->txdes[priv->tx_pointer]; | |
615 | } | |
616 | ||
617 | static struct ftgmac100_txdes * | |
618 | ftgmac100_current_clean_txdes(struct ftgmac100 *priv) | |
619 | { | |
620 | return &priv->descs->txdes[priv->tx_clean_pointer]; | |
621 | } | |
622 | ||
623 | static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv) | |
624 | { | |
625 | struct net_device *netdev = priv->netdev; | |
626 | struct ftgmac100_txdes *txdes; | |
627 | struct sk_buff *skb; | |
628 | dma_addr_t map; | |
629 | ||
630 | if (priv->tx_pending == 0) | |
631 | return false; | |
632 | ||
633 | txdes = ftgmac100_current_clean_txdes(priv); | |
634 | ||
635 | if (ftgmac100_txdes_owned_by_dma(txdes)) | |
636 | return false; | |
637 | ||
638 | skb = ftgmac100_txdes_get_skb(txdes); | |
639 | map = ftgmac100_txdes_get_dma_addr(txdes); | |
640 | ||
641 | netdev->stats.tx_packets++; | |
642 | netdev->stats.tx_bytes += skb->len; | |
643 | ||
644 | dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); | |
645 | ||
646 | dev_kfree_skb(skb); | |
647 | ||
648 | ftgmac100_txdes_reset(txdes); | |
649 | ||
650 | ftgmac100_tx_clean_pointer_advance(priv); | |
651 | ||
652 | spin_lock(&priv->tx_lock); | |
653 | priv->tx_pending--; | |
654 | spin_unlock(&priv->tx_lock); | |
655 | netif_wake_queue(netdev); | |
656 | ||
657 | return true; | |
658 | } | |
659 | ||
660 | static void ftgmac100_tx_complete(struct ftgmac100 *priv) | |
661 | { | |
662 | while (ftgmac100_tx_complete_packet(priv)) | |
663 | ; | |
664 | } | |
665 | ||
666 | static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb, | |
667 | dma_addr_t map) | |
668 | { | |
669 | struct net_device *netdev = priv->netdev; | |
670 | struct ftgmac100_txdes *txdes; | |
671 | unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len; | |
672 | ||
673 | txdes = ftgmac100_current_txdes(priv); | |
674 | ftgmac100_tx_pointer_advance(priv); | |
675 | ||
676 | /* setup TX descriptor */ | |
677 | ftgmac100_txdes_set_skb(txdes, skb); | |
678 | ftgmac100_txdes_set_dma_addr(txdes, map); | |
679 | ftgmac100_txdes_set_buffer_size(txdes, len); | |
680 | ||
681 | ftgmac100_txdes_set_first_segment(txdes); | |
682 | ftgmac100_txdes_set_last_segment(txdes); | |
683 | ftgmac100_txdes_set_txint(txdes); | |
684 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
685 | __be16 protocol = skb->protocol; | |
686 | ||
687 | if (protocol == cpu_to_be16(ETH_P_IP)) { | |
688 | u8 ip_proto = ip_hdr(skb)->protocol; | |
689 | ||
690 | ftgmac100_txdes_set_ipcs(txdes); | |
691 | if (ip_proto == IPPROTO_TCP) | |
692 | ftgmac100_txdes_set_tcpcs(txdes); | |
693 | else if (ip_proto == IPPROTO_UDP) | |
694 | ftgmac100_txdes_set_udpcs(txdes); | |
695 | } | |
696 | } | |
697 | ||
698 | spin_lock(&priv->tx_lock); | |
699 | priv->tx_pending++; | |
700 | if (priv->tx_pending == TX_QUEUE_ENTRIES) | |
701 | netif_stop_queue(netdev); | |
702 | ||
703 | /* start transmit */ | |
704 | ftgmac100_txdes_set_dma_own(txdes); | |
705 | spin_unlock(&priv->tx_lock); | |
706 | ||
707 | ftgmac100_txdma_normal_prio_start_polling(priv); | |
708 | ||
709 | return NETDEV_TX_OK; | |
710 | } | |
711 | ||
712 | /****************************************************************************** | |
713 | * internal functions (buffer) | |
714 | *****************************************************************************/ | |
715 | static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv, | |
716 | struct ftgmac100_rxdes *rxdes, gfp_t gfp) | |
717 | { | |
718 | struct net_device *netdev = priv->netdev; | |
719 | struct page *page; | |
720 | dma_addr_t map; | |
721 | ||
722 | page = alloc_page(gfp); | |
723 | if (!page) { | |
724 | if (net_ratelimit()) | |
725 | netdev_err(netdev, "failed to allocate rx page\n"); | |
726 | return -ENOMEM; | |
727 | } | |
728 | ||
729 | map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
730 | if (unlikely(dma_mapping_error(priv->dev, map))) { | |
731 | if (net_ratelimit()) | |
732 | netdev_err(netdev, "failed to map rx page\n"); | |
733 | __free_page(page); | |
734 | return -ENOMEM; | |
735 | } | |
736 | ||
737 | ftgmac100_rxdes_set_page(rxdes, page); | |
738 | ftgmac100_rxdes_set_dma_addr(rxdes, map); | |
739 | ftgmac100_rxdes_set_dma_own(rxdes); | |
740 | return 0; | |
741 | } | |
742 | ||
743 | static void ftgmac100_free_buffers(struct ftgmac100 *priv) | |
744 | { | |
745 | int i; | |
746 | ||
747 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { | |
748 | struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; | |
749 | struct page *page = ftgmac100_rxdes_get_page(rxdes); | |
750 | dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes); | |
751 | ||
752 | if (!page) | |
753 | continue; | |
754 | ||
755 | dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE); | |
756 | __free_page(page); | |
757 | } | |
758 | ||
759 | for (i = 0; i < TX_QUEUE_ENTRIES; i++) { | |
760 | struct ftgmac100_txdes *txdes = &priv->descs->txdes[i]; | |
761 | struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes); | |
762 | dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes); | |
763 | ||
764 | if (!skb) | |
765 | continue; | |
766 | ||
767 | dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE); | |
0113e34b | 768 | kfree_skb(skb); |
69785b79 PYC |
769 | } |
770 | ||
771 | dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs), | |
772 | priv->descs, priv->descs_dma_addr); | |
773 | } | |
774 | ||
775 | static int ftgmac100_alloc_buffers(struct ftgmac100 *priv) | |
776 | { | |
777 | int i; | |
778 | ||
ede23fa8 JP |
779 | priv->descs = dma_zalloc_coherent(priv->dev, |
780 | sizeof(struct ftgmac100_descs), | |
781 | &priv->descs_dma_addr, GFP_KERNEL); | |
69785b79 PYC |
782 | if (!priv->descs) |
783 | return -ENOMEM; | |
784 | ||
69785b79 PYC |
785 | /* initialize RX ring */ |
786 | ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]); | |
787 | ||
788 | for (i = 0; i < RX_QUEUE_ENTRIES; i++) { | |
789 | struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i]; | |
790 | ||
791 | if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL)) | |
792 | goto err; | |
793 | } | |
794 | ||
795 | /* initialize TX ring */ | |
796 | ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]); | |
797 | return 0; | |
798 | ||
799 | err: | |
800 | ftgmac100_free_buffers(priv); | |
801 | return -ENOMEM; | |
802 | } | |
803 | ||
804 | /****************************************************************************** | |
805 | * internal functions (mdio) | |
806 | *****************************************************************************/ | |
807 | static void ftgmac100_adjust_link(struct net_device *netdev) | |
808 | { | |
809 | struct ftgmac100 *priv = netdev_priv(netdev); | |
810 | struct phy_device *phydev = priv->phydev; | |
811 | int ier; | |
812 | ||
813 | if (phydev->speed == priv->old_speed) | |
814 | return; | |
815 | ||
816 | priv->old_speed = phydev->speed; | |
817 | ||
818 | ier = ioread32(priv->base + FTGMAC100_OFFSET_IER); | |
819 | ||
820 | /* disable all interrupts */ | |
821 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
822 | ||
823 | netif_stop_queue(netdev); | |
824 | ftgmac100_stop_hw(priv); | |
825 | ||
826 | netif_start_queue(netdev); | |
827 | ftgmac100_init_hw(priv); | |
828 | ftgmac100_start_hw(priv, phydev->speed); | |
829 | ||
830 | /* re-enable interrupts */ | |
831 | iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER); | |
832 | } | |
833 | ||
834 | static int ftgmac100_mii_probe(struct ftgmac100 *priv) | |
835 | { | |
836 | struct net_device *netdev = priv->netdev; | |
e574f398 | 837 | struct phy_device *phydev; |
69785b79 | 838 | |
e574f398 | 839 | phydev = phy_find_first(priv->mii_bus); |
69785b79 PYC |
840 | if (!phydev) { |
841 | netdev_info(netdev, "%s: no PHY found\n", netdev->name); | |
842 | return -ENODEV; | |
843 | } | |
844 | ||
84eff6d1 | 845 | phydev = phy_connect(netdev, phydev_name(phydev), |
f9a8f83b | 846 | &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII); |
69785b79 PYC |
847 | |
848 | if (IS_ERR(phydev)) { | |
849 | netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name); | |
850 | return PTR_ERR(phydev); | |
851 | } | |
852 | ||
853 | priv->phydev = phydev; | |
854 | return 0; | |
855 | } | |
856 | ||
857 | /****************************************************************************** | |
858 | * struct mii_bus functions | |
859 | *****************************************************************************/ | |
860 | static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) | |
861 | { | |
862 | struct net_device *netdev = bus->priv; | |
863 | struct ftgmac100 *priv = netdev_priv(netdev); | |
864 | unsigned int phycr; | |
865 | int i; | |
866 | ||
867 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
868 | ||
869 | /* preserve MDC cycle threshold */ | |
870 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
871 | ||
872 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
873 | FTGMAC100_PHYCR_REGAD(regnum) | | |
874 | FTGMAC100_PHYCR_MIIRD; | |
875 | ||
876 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
877 | ||
878 | for (i = 0; i < 10; i++) { | |
879 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
880 | ||
881 | if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) { | |
882 | int data; | |
883 | ||
884 | data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA); | |
885 | return FTGMAC100_PHYDATA_MIIRDATA(data); | |
886 | } | |
887 | ||
888 | udelay(100); | |
889 | } | |
890 | ||
891 | netdev_err(netdev, "mdio read timed out\n"); | |
892 | return -EIO; | |
893 | } | |
894 | ||
895 | static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr, | |
896 | int regnum, u16 value) | |
897 | { | |
898 | struct net_device *netdev = bus->priv; | |
899 | struct ftgmac100 *priv = netdev_priv(netdev); | |
900 | unsigned int phycr; | |
901 | int data; | |
902 | int i; | |
903 | ||
904 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
905 | ||
906 | /* preserve MDC cycle threshold */ | |
907 | phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK; | |
908 | ||
909 | phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) | | |
910 | FTGMAC100_PHYCR_REGAD(regnum) | | |
911 | FTGMAC100_PHYCR_MIIWR; | |
912 | ||
913 | data = FTGMAC100_PHYDATA_MIIWDATA(value); | |
914 | ||
915 | iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA); | |
916 | iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR); | |
917 | ||
918 | for (i = 0; i < 10; i++) { | |
919 | phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR); | |
920 | ||
921 | if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) | |
922 | return 0; | |
923 | ||
924 | udelay(100); | |
925 | } | |
926 | ||
927 | netdev_err(netdev, "mdio write timed out\n"); | |
928 | return -EIO; | |
929 | } | |
930 | ||
69785b79 PYC |
931 | /****************************************************************************** |
932 | * struct ethtool_ops functions | |
933 | *****************************************************************************/ | |
934 | static void ftgmac100_get_drvinfo(struct net_device *netdev, | |
935 | struct ethtool_drvinfo *info) | |
936 | { | |
7826d43f JP |
937 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
938 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
939 | strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info)); | |
69785b79 PYC |
940 | } |
941 | ||
942 | static int ftgmac100_get_settings(struct net_device *netdev, | |
943 | struct ethtool_cmd *cmd) | |
944 | { | |
945 | struct ftgmac100 *priv = netdev_priv(netdev); | |
946 | ||
947 | return phy_ethtool_gset(priv->phydev, cmd); | |
948 | } | |
949 | ||
950 | static int ftgmac100_set_settings(struct net_device *netdev, | |
951 | struct ethtool_cmd *cmd) | |
952 | { | |
953 | struct ftgmac100 *priv = netdev_priv(netdev); | |
954 | ||
955 | return phy_ethtool_sset(priv->phydev, cmd); | |
956 | } | |
957 | ||
958 | static const struct ethtool_ops ftgmac100_ethtool_ops = { | |
959 | .set_settings = ftgmac100_set_settings, | |
960 | .get_settings = ftgmac100_get_settings, | |
961 | .get_drvinfo = ftgmac100_get_drvinfo, | |
962 | .get_link = ethtool_op_get_link, | |
963 | }; | |
964 | ||
965 | /****************************************************************************** | |
966 | * interrupt handler | |
967 | *****************************************************************************/ | |
968 | static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id) | |
969 | { | |
970 | struct net_device *netdev = dev_id; | |
971 | struct ftgmac100 *priv = netdev_priv(netdev); | |
972 | ||
973 | if (likely(netif_running(netdev))) { | |
974 | /* Disable interrupts for polling */ | |
975 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
976 | napi_schedule(&priv->napi); | |
977 | } | |
978 | ||
979 | return IRQ_HANDLED; | |
980 | } | |
981 | ||
982 | /****************************************************************************** | |
983 | * struct napi_struct functions | |
984 | *****************************************************************************/ | |
985 | static int ftgmac100_poll(struct napi_struct *napi, int budget) | |
986 | { | |
987 | struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi); | |
988 | struct net_device *netdev = priv->netdev; | |
989 | unsigned int status; | |
990 | bool completed = true; | |
991 | int rx = 0; | |
992 | ||
993 | status = ioread32(priv->base + FTGMAC100_OFFSET_ISR); | |
994 | iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR); | |
995 | ||
996 | if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) { | |
997 | /* | |
998 | * FTGMAC100_INT_RPKT_BUF: | |
999 | * RX DMA has received packets into RX buffer successfully | |
1000 | * | |
1001 | * FTGMAC100_INT_NO_RXBUF: | |
1002 | * RX buffer unavailable | |
1003 | */ | |
1004 | bool retry; | |
1005 | ||
1006 | do { | |
1007 | retry = ftgmac100_rx_packet(priv, &rx); | |
1008 | } while (retry && rx < budget); | |
1009 | ||
1010 | if (retry && rx == budget) | |
1011 | completed = false; | |
1012 | } | |
1013 | ||
1014 | if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) { | |
1015 | /* | |
1016 | * FTGMAC100_INT_XPKT_ETH: | |
1017 | * packet transmitted to ethernet successfully | |
1018 | * | |
1019 | * FTGMAC100_INT_XPKT_LOST: | |
1020 | * packet transmitted to ethernet lost due to late | |
1021 | * collision or excessive collision | |
1022 | */ | |
1023 | ftgmac100_tx_complete(priv); | |
1024 | } | |
1025 | ||
1026 | if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST | | |
1027 | FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) { | |
1028 | if (net_ratelimit()) | |
1029 | netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status, | |
1030 | status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "", | |
1031 | status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "", | |
1032 | status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "", | |
1033 | status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : ""); | |
1034 | ||
1035 | if (status & FTGMAC100_INT_NO_RXBUF) { | |
1036 | /* RX buffer unavailable */ | |
1037 | netdev->stats.rx_over_errors++; | |
1038 | } | |
1039 | ||
1040 | if (status & FTGMAC100_INT_RPKT_LOST) { | |
1041 | /* received packet lost due to RX FIFO full */ | |
1042 | netdev->stats.rx_fifo_errors++; | |
1043 | } | |
1044 | } | |
1045 | ||
1046 | if (completed) { | |
1047 | napi_complete(napi); | |
1048 | ||
1049 | /* enable all interrupts */ | |
1050 | iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); | |
1051 | } | |
1052 | ||
1053 | return rx; | |
1054 | } | |
1055 | ||
1056 | /****************************************************************************** | |
1057 | * struct net_device_ops functions | |
1058 | *****************************************************************************/ | |
1059 | static int ftgmac100_open(struct net_device *netdev) | |
1060 | { | |
1061 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1062 | int err; | |
1063 | ||
1064 | err = ftgmac100_alloc_buffers(priv); | |
1065 | if (err) { | |
1066 | netdev_err(netdev, "failed to allocate buffers\n"); | |
1067 | goto err_alloc; | |
1068 | } | |
1069 | ||
1070 | err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev); | |
1071 | if (err) { | |
1072 | netdev_err(netdev, "failed to request irq %d\n", priv->irq); | |
1073 | goto err_irq; | |
1074 | } | |
1075 | ||
1076 | priv->rx_pointer = 0; | |
1077 | priv->tx_clean_pointer = 0; | |
1078 | priv->tx_pointer = 0; | |
1079 | priv->tx_pending = 0; | |
1080 | ||
1081 | err = ftgmac100_reset_hw(priv); | |
1082 | if (err) | |
1083 | goto err_hw; | |
1084 | ||
1085 | ftgmac100_init_hw(priv); | |
1086 | ftgmac100_start_hw(priv, 10); | |
1087 | ||
1088 | phy_start(priv->phydev); | |
1089 | ||
1090 | napi_enable(&priv->napi); | |
1091 | netif_start_queue(netdev); | |
1092 | ||
1093 | /* enable all interrupts */ | |
1094 | iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER); | |
1095 | return 0; | |
1096 | ||
1097 | err_hw: | |
1098 | free_irq(priv->irq, netdev); | |
1099 | err_irq: | |
1100 | ftgmac100_free_buffers(priv); | |
1101 | err_alloc: | |
1102 | return err; | |
1103 | } | |
1104 | ||
1105 | static int ftgmac100_stop(struct net_device *netdev) | |
1106 | { | |
1107 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1108 | ||
1109 | /* disable all interrupts */ | |
1110 | iowrite32(0, priv->base + FTGMAC100_OFFSET_IER); | |
1111 | ||
1112 | netif_stop_queue(netdev); | |
1113 | napi_disable(&priv->napi); | |
1114 | phy_stop(priv->phydev); | |
1115 | ||
1116 | ftgmac100_stop_hw(priv); | |
1117 | free_irq(priv->irq, netdev); | |
1118 | ftgmac100_free_buffers(priv); | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | static int ftgmac100_hard_start_xmit(struct sk_buff *skb, | |
1124 | struct net_device *netdev) | |
1125 | { | |
1126 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1127 | dma_addr_t map; | |
1128 | ||
1129 | if (unlikely(skb->len > MAX_PKT_SIZE)) { | |
1130 | if (net_ratelimit()) | |
1131 | netdev_dbg(netdev, "tx packet too big\n"); | |
1132 | ||
1133 | netdev->stats.tx_dropped++; | |
0113e34b | 1134 | kfree_skb(skb); |
69785b79 PYC |
1135 | return NETDEV_TX_OK; |
1136 | } | |
1137 | ||
1138 | map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); | |
1139 | if (unlikely(dma_mapping_error(priv->dev, map))) { | |
1140 | /* drop packet */ | |
1141 | if (net_ratelimit()) | |
1142 | netdev_err(netdev, "map socket buffer failed\n"); | |
1143 | ||
1144 | netdev->stats.tx_dropped++; | |
0113e34b | 1145 | kfree_skb(skb); |
69785b79 PYC |
1146 | return NETDEV_TX_OK; |
1147 | } | |
1148 | ||
1149 | return ftgmac100_xmit(priv, skb, map); | |
1150 | } | |
1151 | ||
1152 | /* optional */ | |
1153 | static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
1154 | { | |
1155 | struct ftgmac100 *priv = netdev_priv(netdev); | |
1156 | ||
1157 | return phy_mii_ioctl(priv->phydev, ifr, cmd); | |
1158 | } | |
1159 | ||
1160 | static const struct net_device_ops ftgmac100_netdev_ops = { | |
1161 | .ndo_open = ftgmac100_open, | |
1162 | .ndo_stop = ftgmac100_stop, | |
1163 | .ndo_start_xmit = ftgmac100_hard_start_xmit, | |
1164 | .ndo_set_mac_address = eth_mac_addr, | |
1165 | .ndo_validate_addr = eth_validate_addr, | |
1166 | .ndo_do_ioctl = ftgmac100_do_ioctl, | |
1167 | }; | |
1168 | ||
1169 | /****************************************************************************** | |
1170 | * struct platform_driver functions | |
1171 | *****************************************************************************/ | |
1172 | static int ftgmac100_probe(struct platform_device *pdev) | |
1173 | { | |
1174 | struct resource *res; | |
1175 | int irq; | |
1176 | struct net_device *netdev; | |
1177 | struct ftgmac100 *priv; | |
1178 | int err; | |
69785b79 PYC |
1179 | |
1180 | if (!pdev) | |
1181 | return -ENODEV; | |
1182 | ||
1183 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1184 | if (!res) | |
1185 | return -ENXIO; | |
1186 | ||
1187 | irq = platform_get_irq(pdev, 0); | |
1188 | if (irq < 0) | |
1189 | return irq; | |
1190 | ||
1191 | /* setup net_device */ | |
1192 | netdev = alloc_etherdev(sizeof(*priv)); | |
1193 | if (!netdev) { | |
1194 | err = -ENOMEM; | |
1195 | goto err_alloc_etherdev; | |
1196 | } | |
1197 | ||
1198 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1199 | ||
7ad24ea4 | 1200 | netdev->ethtool_ops = &ftgmac100_ethtool_ops; |
69785b79 PYC |
1201 | netdev->netdev_ops = &ftgmac100_netdev_ops; |
1202 | netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO; | |
1203 | ||
1204 | platform_set_drvdata(pdev, netdev); | |
1205 | ||
1206 | /* setup private data */ | |
1207 | priv = netdev_priv(netdev); | |
1208 | priv->netdev = netdev; | |
1209 | priv->dev = &pdev->dev; | |
1210 | ||
1211 | spin_lock_init(&priv->tx_lock); | |
1212 | ||
1213 | /* initialize NAPI */ | |
1214 | netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64); | |
1215 | ||
1216 | /* map io memory */ | |
1217 | priv->res = request_mem_region(res->start, resource_size(res), | |
1218 | dev_name(&pdev->dev)); | |
1219 | if (!priv->res) { | |
1220 | dev_err(&pdev->dev, "Could not reserve memory region\n"); | |
1221 | err = -ENOMEM; | |
1222 | goto err_req_mem; | |
1223 | } | |
1224 | ||
1225 | priv->base = ioremap(res->start, resource_size(res)); | |
1226 | if (!priv->base) { | |
1227 | dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n"); | |
1228 | err = -EIO; | |
1229 | goto err_ioremap; | |
1230 | } | |
1231 | ||
1232 | priv->irq = irq; | |
1233 | ||
1234 | /* initialize mdio bus */ | |
1235 | priv->mii_bus = mdiobus_alloc(); | |
1236 | if (!priv->mii_bus) { | |
1237 | err = -EIO; | |
1238 | goto err_alloc_mdiobus; | |
1239 | } | |
1240 | ||
1241 | priv->mii_bus->name = "ftgmac100_mdio"; | |
1242 | snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii"); | |
1243 | ||
1244 | priv->mii_bus->priv = netdev; | |
1245 | priv->mii_bus->read = ftgmac100_mdiobus_read; | |
1246 | priv->mii_bus->write = ftgmac100_mdiobus_write; | |
69785b79 PYC |
1247 | |
1248 | err = mdiobus_register(priv->mii_bus); | |
1249 | if (err) { | |
1250 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1251 | goto err_register_mdiobus; | |
1252 | } | |
1253 | ||
1254 | err = ftgmac100_mii_probe(priv); | |
1255 | if (err) { | |
1256 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1257 | goto err_mii_probe; | |
1258 | } | |
1259 | ||
1260 | /* register network device */ | |
1261 | err = register_netdev(netdev); | |
1262 | if (err) { | |
1263 | dev_err(&pdev->dev, "Failed to register netdev\n"); | |
1264 | goto err_register_netdev; | |
1265 | } | |
1266 | ||
1267 | netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base); | |
1268 | ||
1269 | if (!is_valid_ether_addr(netdev->dev_addr)) { | |
f2cedb63 | 1270 | eth_hw_addr_random(netdev); |
69785b79 PYC |
1271 | netdev_info(netdev, "generated random MAC address %pM\n", |
1272 | netdev->dev_addr); | |
1273 | } | |
1274 | ||
1275 | return 0; | |
1276 | ||
1277 | err_register_netdev: | |
1278 | phy_disconnect(priv->phydev); | |
1279 | err_mii_probe: | |
1280 | mdiobus_unregister(priv->mii_bus); | |
1281 | err_register_mdiobus: | |
1282 | mdiobus_free(priv->mii_bus); | |
1283 | err_alloc_mdiobus: | |
1284 | iounmap(priv->base); | |
1285 | err_ioremap: | |
1286 | release_resource(priv->res); | |
1287 | err_req_mem: | |
1288 | netif_napi_del(&priv->napi); | |
69785b79 PYC |
1289 | free_netdev(netdev); |
1290 | err_alloc_etherdev: | |
1291 | return err; | |
1292 | } | |
1293 | ||
1294 | static int __exit ftgmac100_remove(struct platform_device *pdev) | |
1295 | { | |
1296 | struct net_device *netdev; | |
1297 | struct ftgmac100 *priv; | |
1298 | ||
1299 | netdev = platform_get_drvdata(pdev); | |
1300 | priv = netdev_priv(netdev); | |
1301 | ||
1302 | unregister_netdev(netdev); | |
1303 | ||
1304 | phy_disconnect(priv->phydev); | |
1305 | mdiobus_unregister(priv->mii_bus); | |
1306 | mdiobus_free(priv->mii_bus); | |
1307 | ||
1308 | iounmap(priv->base); | |
1309 | release_resource(priv->res); | |
1310 | ||
1311 | netif_napi_del(&priv->napi); | |
69785b79 PYC |
1312 | free_netdev(netdev); |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | static struct platform_driver ftgmac100_driver = { | |
1317 | .probe = ftgmac100_probe, | |
1318 | .remove = __exit_p(ftgmac100_remove), | |
1319 | .driver = { | |
1320 | .name = DRV_NAME, | |
69785b79 PYC |
1321 | }, |
1322 | }; | |
1323 | ||
14f645d0 | 1324 | module_platform_driver(ftgmac100_driver); |
69785b79 PYC |
1325 | |
1326 | MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>"); | |
1327 | MODULE_DESCRIPTION("FTGMAC100 driver"); | |
1328 | MODULE_LICENSE("GPL"); |