Commit | Line | Data |
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1da177e4 LT |
1 | /****************************************************************************/ |
2 | ||
3 | /* | |
7a77d918 GU |
4 | * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC |
5 | * processors. | |
1da177e4 | 6 | * |
7a77d918 | 7 | * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) |
1da177e4 LT |
8 | * (C) Copyright 2000-2001, Lineo (www.lineo.com) |
9 | */ | |
10 | ||
11 | /****************************************************************************/ | |
12 | #ifndef FEC_H | |
13 | #define FEC_H | |
14 | /****************************************************************************/ | |
15 | ||
6605b730 FL |
16 | #include <linux/clocksource.h> |
17 | #include <linux/net_tstamp.h> | |
18 | #include <linux/ptp_clock_kernel.h> | |
6605b730 | 19 | |
7a77d918 | 20 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
b5680e0b SG |
21 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || \ |
22 | defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) | |
1da177e4 LT |
23 | /* |
24 | * Just figures, Motorola would have to change the offsets for | |
25 | * registers in the same peripheral device on different models | |
26 | * of the ColdFire! | |
27 | */ | |
f44d6305 SH |
28 | #define FEC_IEVENT 0x004 /* Interrupt event reg */ |
29 | #define FEC_IMASK 0x008 /* Interrupt mask reg */ | |
4d494cdc FD |
30 | #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ |
31 | #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ | |
f44d6305 SH |
32 | #define FEC_ECNTRL 0x024 /* Ethernet control reg */ |
33 | #define FEC_MII_DATA 0x040 /* MII manage frame reg */ | |
34 | #define FEC_MII_SPEED 0x044 /* MII speed control reg */ | |
35 | #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ | |
36 | #define FEC_R_CNTRL 0x084 /* Receive control reg */ | |
37 | #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ | |
38 | #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ | |
39 | #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ | |
40 | #define FEC_OPD 0x0ec /* Opcode + Pause duration */ | |
41 | #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ | |
42 | #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ | |
43 | #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ | |
44 | #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ | |
45 | #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ | |
46 | #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ | |
47 | #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ | |
4d494cdc FD |
48 | #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ |
49 | #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ | |
50 | #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ | |
51 | #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ | |
52 | #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ | |
53 | #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ | |
f44d6305 | 54 | #define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */ |
baa70a5c FL |
55 | #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ |
56 | #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ | |
57 | #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ | |
58 | #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ | |
4c09eed9 | 59 | #define FEC_RACC 0x1C4 /* Receive Accelerator function */ |
4d494cdc FD |
60 | #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ |
61 | #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ | |
62 | #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ | |
63 | #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ | |
64 | #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ | |
65 | #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ | |
66 | #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ | |
67 | #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ | |
5eb32bd0 BS |
68 | #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ |
69 | #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ | |
1da177e4 | 70 | |
8d82f219 EB |
71 | #define BM_MIIGSK_CFGR_MII 0x00 |
72 | #define BM_MIIGSK_CFGR_RMII 0x01 | |
73 | #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 | |
74 | ||
38ae92dc CH |
75 | #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ |
76 | #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ | |
77 | #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ | |
78 | #define RMON_T_MC_PKT 0x20C /* RMON TX multicast pkts */ | |
79 | #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ | |
80 | #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ | |
81 | #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ | |
82 | #define RMON_T_FRAG 0x21C /* RMON TX pkts < 64 bytes, bad CRC */ | |
83 | #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ | |
84 | #define RMON_T_COL 0x224 /* RMON TX collision count */ | |
85 | #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ | |
86 | #define RMON_T_P65TO127 0x22C /* RMON TX 65 to 127 byte pkts */ | |
87 | #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ | |
88 | #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ | |
89 | #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ | |
90 | #define RMON_T_P1024TO2047 0x23C /* RMON TX 1024 to 2047 byte pkts */ | |
91 | #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ | |
92 | #define RMON_T_OCTETS 0x244 /* RMON TX octets */ | |
93 | #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ | |
94 | #define IEEE_T_FRAME_OK 0x24C /* Frames tx'd OK */ | |
95 | #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ | |
96 | #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ | |
97 | #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ | |
98 | #define IEEE_T_LCOL 0x25C /* Frames tx'd with late collision */ | |
99 | #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ | |
100 | #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ | |
101 | #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ | |
102 | #define IEEE_T_SQE 0x26C /* Frames tx'd with SQE err */ | |
103 | #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ | |
104 | #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ | |
105 | #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ | |
106 | #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ | |
107 | #define RMON_R_MC_PKT 0x28C /* RMON RX multicast pkts */ | |
108 | #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ | |
109 | #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ | |
110 | #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ | |
111 | #define RMON_R_FRAG 0x29C /* RMON RX pkts < 64 bytes, bad CRC */ | |
112 | #define RMON_R_JAB 0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ | |
113 | #define RMON_R_RESVD_O 0x2A4 /* Reserved */ | |
114 | #define RMON_R_P64 0x2A8 /* RMON RX 64 byte pkts */ | |
115 | #define RMON_R_P65TO127 0x2AC /* RMON RX 65 to 127 byte pkts */ | |
116 | #define RMON_R_P128TO255 0x2B0 /* RMON RX 128 to 255 byte pkts */ | |
117 | #define RMON_R_P256TO511 0x2B4 /* RMON RX 256 to 511 byte pkts */ | |
118 | #define RMON_R_P512TO1023 0x2B8 /* RMON RX 512 to 1023 byte pkts */ | |
119 | #define RMON_R_P1024TO2047 0x2BC /* RMON RX 1024 to 2047 byte pkts */ | |
120 | #define RMON_R_P_GTE2048 0x2C0 /* RMON RX pkts > 2048 bytes */ | |
121 | #define RMON_R_OCTETS 0x2C4 /* RMON RX octets */ | |
122 | #define IEEE_R_DROP 0x2C8 /* Count frames not counted correctly */ | |
123 | #define IEEE_R_FRAME_OK 0x2CC /* Frames rx'd OK */ | |
124 | #define IEEE_R_CRC 0x2D0 /* Frames rx'd with CRC err */ | |
125 | #define IEEE_R_ALIGN 0x2D4 /* Frames rx'd with alignment err */ | |
126 | #define IEEE_R_MACERR 0x2D8 /* Receive FIFO overflow count */ | |
127 | #define IEEE_R_FDXFC 0x2DC /* Flow control pause frames rx'd */ | |
128 | #define IEEE_R_OCTETS_OK 0x2E0 /* Octet cnt for frames rx'd w/o err */ | |
129 | ||
1da177e4 LT |
130 | #else |
131 | ||
9ff1a91c GU |
132 | #define FEC_ECNTRL 0x000 /* Ethernet control reg */ |
133 | #define FEC_IEVENT 0x004 /* Interrupt even reg */ | |
134 | #define FEC_IMASK 0x008 /* Interrupt mask reg */ | |
135 | #define FEC_IVEC 0x00c /* Interrupt vec status reg */ | |
136 | #define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */ | |
5ca1ea23 | 137 | #define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */ |
f44d6305 SH |
138 | #define FEC_MII_DATA 0x040 /* MII manage frame reg */ |
139 | #define FEC_MII_SPEED 0x044 /* MII speed control reg */ | |
140 | #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ | |
141 | #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ | |
142 | #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ | |
143 | #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ | |
144 | #define FEC_R_CNTRL 0x104 /* Receive control reg */ | |
145 | #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ | |
146 | #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ | |
147 | #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ | |
148 | #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ | |
149 | #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ | |
150 | #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ | |
151 | #define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */ | |
152 | #define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */ | |
153 | #define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */ | |
154 | #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ | |
1da177e4 LT |
155 | |
156 | #endif /* CONFIG_M5272 */ | |
157 | ||
158 | ||
159 | /* | |
160 | * Define the buffer descriptor structure. | |
161 | */ | |
b5680e0b | 162 | #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28) |
2e28532f | 163 | struct bufdesc { |
196719ec SH |
164 | unsigned short cbd_datlen; /* Data length */ |
165 | unsigned short cbd_sc; /* Control and status info */ | |
166 | unsigned long cbd_bufaddr; /* Buffer address */ | |
ff43da86 | 167 | }; |
acac8406 FL |
168 | #else |
169 | struct bufdesc { | |
170 | unsigned short cbd_sc; /* Control and status info */ | |
171 | unsigned short cbd_datlen; /* Data length */ | |
172 | unsigned long cbd_bufaddr; /* Buffer address */ | |
173 | }; | |
174 | #endif | |
ff43da86 FL |
175 | |
176 | struct bufdesc_ex { | |
177 | struct bufdesc desc; | |
6605b730 FL |
178 | unsigned long cbd_esc; |
179 | unsigned long cbd_prot; | |
180 | unsigned long cbd_bdu; | |
181 | unsigned long ts; | |
182 | unsigned short res0[4]; | |
2e28532f | 183 | }; |
ff43da86 | 184 | |
1da177e4 LT |
185 | /* |
186 | * The following definitions courtesy of commproc.h, which where | |
187 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). | |
188 | */ | |
25985edc | 189 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ |
1da177e4 LT |
190 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ |
191 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | |
192 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | |
25985edc | 193 | #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ |
1da177e4 LT |
194 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ |
195 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | |
196 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | |
197 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | |
198 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | |
199 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | |
200 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | |
201 | ||
202 | /* Buffer descriptor control/status used by Ethernet receive. | |
203 | */ | |
204 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | |
205 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | |
206 | #define BD_ENET_RX_INTR ((ushort)0x1000) | |
207 | #define BD_ENET_RX_LAST ((ushort)0x0800) | |
208 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | |
209 | #define BD_ENET_RX_MISS ((ushort)0x0100) | |
210 | #define BD_ENET_RX_LG ((ushort)0x0020) | |
211 | #define BD_ENET_RX_NO ((ushort)0x0010) | |
212 | #define BD_ENET_RX_SH ((ushort)0x0008) | |
213 | #define BD_ENET_RX_CR ((ushort)0x0004) | |
214 | #define BD_ENET_RX_OV ((ushort)0x0002) | |
215 | #define BD_ENET_RX_CL ((ushort)0x0001) | |
216 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | |
217 | ||
cdffcf1b JB |
218 | /* Enhanced buffer descriptor control/status used by Ethernet receive */ |
219 | #define BD_ENET_RX_VLAN 0x00000004 | |
220 | ||
1da177e4 LT |
221 | /* Buffer descriptor control/status used by Ethernet transmit. |
222 | */ | |
223 | #define BD_ENET_TX_READY ((ushort)0x8000) | |
224 | #define BD_ENET_TX_PAD ((ushort)0x4000) | |
225 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | |
226 | #define BD_ENET_TX_INTR ((ushort)0x1000) | |
227 | #define BD_ENET_TX_LAST ((ushort)0x0800) | |
228 | #define BD_ENET_TX_TC ((ushort)0x0400) | |
229 | #define BD_ENET_TX_DEF ((ushort)0x0200) | |
230 | #define BD_ENET_TX_HB ((ushort)0x0100) | |
231 | #define BD_ENET_TX_LC ((ushort)0x0080) | |
232 | #define BD_ENET_TX_RL ((ushort)0x0040) | |
233 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | |
234 | #define BD_ENET_TX_UN ((ushort)0x0002) | |
235 | #define BD_ENET_TX_CSL ((ushort)0x0001) | |
6e909283 | 236 | #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ |
1da177e4 | 237 | |
4c09eed9 | 238 | /*enhanced buffer descriptor control/status used by Ethernet transmit*/ |
405f257f FL |
239 | #define BD_ENET_TX_INT 0x40000000 |
240 | #define BD_ENET_TX_TS 0x20000000 | |
4c09eed9 JB |
241 | #define BD_ENET_TX_PINS 0x10000000 |
242 | #define BD_ENET_TX_IINS 0x08000000 | |
405f257f FL |
243 | |
244 | ||
245 | /* This device has up to three irqs on some platforms */ | |
246 | #define FEC_IRQ_NUM 3 | |
247 | ||
4d494cdc FD |
248 | /* Maximum number of queues supported |
249 | * ENET with AVB IP can support up to 3 independent tx queues and rx queues. | |
250 | * User can point the queue number that is less than or equal to 3. | |
251 | */ | |
252 | #define FEC_ENET_MAX_TX_QS 3 | |
253 | #define FEC_ENET_MAX_RX_QS 3 | |
254 | ||
255 | #define FEC_R_DES_START(X) ((X == 1) ? FEC_R_DES_START_1 : \ | |
256 | ((X == 2) ? \ | |
257 | FEC_R_DES_START_2 : FEC_R_DES_START_0)) | |
258 | #define FEC_X_DES_START(X) ((X == 1) ? FEC_X_DES_START_1 : \ | |
259 | ((X == 2) ? \ | |
260 | FEC_X_DES_START_2 : FEC_X_DES_START_0)) | |
261 | #define FEC_R_DES_ACTIVE(X) ((X == 1) ? FEC_R_DES_ACTIVE_1 : \ | |
262 | ((X == 2) ? \ | |
263 | FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0)) | |
264 | #define FEC_X_DES_ACTIVE(X) ((X == 1) ? FEC_X_DES_ACTIVE_1 : \ | |
265 | ((X == 2) ? \ | |
266 | FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0)) | |
267 | ||
268 | #define FEC_DMA_CFG(X) ((X == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) | |
269 | ||
270 | #define DMA_CLASS_EN (1 << 16) | |
271 | #define FEC_RCMR(X) ((X == 2) ? FEC_RCMR_2 : FEC_RCMR_1) | |
272 | #define IDLE_SLOPE_MASK 0xFFFF | |
273 | #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ | |
274 | #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ | |
275 | #define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ | |
276 | (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) | |
277 | #define RCMR_MATCHEN (0x1 << 16) | |
278 | #define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2)) | |
279 | #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ | |
280 | RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) | |
281 | #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ | |
282 | RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) | |
283 | #define RCMR_CMP(X) ((X == 1) ? RCMR_CMP_1 : RCMR_CMP_2) | |
284 | ||
405f257f FL |
285 | /* The number of Tx and Rx buffers. These are allocated from the page |
286 | * pool. The code may assume these are power of two, so it it best | |
287 | * to keep them that size. | |
288 | * We don't need to allocate pages for the transmitter. We just use | |
289 | * the skbuffer directly. | |
290 | */ | |
291 | ||
292 | #define FEC_ENET_RX_PAGES 8 | |
293 | #define FEC_ENET_RX_FRSIZE 2048 | |
294 | #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) | |
295 | #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) | |
296 | #define FEC_ENET_TX_FRSIZE 2048 | |
297 | #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) | |
55d0218a NA |
298 | #define TX_RING_SIZE 512 /* Must be power of two */ |
299 | #define TX_RING_MOD_MASK 511 /* for this to work */ | |
405f257f FL |
300 | |
301 | #define BD_ENET_RX_INT 0x00800000 | |
302 | #define BD_ENET_RX_PTP ((ushort)0x0400) | |
4c09eed9 JB |
303 | #define BD_ENET_RX_ICE 0x00000020 |
304 | #define BD_ENET_RX_PCR 0x00000010 | |
305 | #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) | |
306 | #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) | |
405f257f | 307 | |
4d494cdc FD |
308 | struct fec_enet_priv_tx_q { |
309 | int index; | |
310 | unsigned char *tx_bounce[TX_RING_SIZE]; | |
311 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
312 | ||
313 | dma_addr_t bd_dma; | |
314 | struct bufdesc *tx_bd_base; | |
315 | uint tx_ring_size; | |
316 | ||
317 | unsigned short tx_stop_threshold; | |
318 | unsigned short tx_wake_threshold; | |
319 | ||
320 | struct bufdesc *cur_tx; | |
321 | struct bufdesc *dirty_tx; | |
322 | char *tso_hdrs; | |
323 | dma_addr_t tso_hdrs_dma; | |
324 | }; | |
325 | ||
326 | struct fec_enet_priv_rx_q { | |
327 | int index; | |
328 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
329 | ||
330 | dma_addr_t bd_dma; | |
331 | struct bufdesc *rx_bd_base; | |
332 | uint rx_ring_size; | |
333 | ||
334 | struct bufdesc *cur_rx; | |
335 | }; | |
336 | ||
405f257f FL |
337 | /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and |
338 | * tx_bd_base always point to the base of the buffer descriptors. The | |
339 | * cur_rx and cur_tx point to the currently available buffer. | |
340 | * The dirty_tx tracks the current buffer that is being sent by the | |
341 | * controller. The cur_tx and dirty_tx are equal under both completely | |
342 | * empty and completely full conditions. The empty/ready indicator in | |
343 | * the buffer descriptor determines the actual condition. | |
344 | */ | |
345 | struct fec_enet_private { | |
346 | /* Hardware registers of the FEC device */ | |
347 | void __iomem *hwp; | |
348 | ||
349 | struct net_device *netdev; | |
350 | ||
351 | struct clk *clk_ipg; | |
352 | struct clk *clk_ahb; | |
9b5330ed | 353 | struct clk *clk_ref; |
daa7d392 | 354 | struct clk *clk_enet_out; |
6605b730 | 355 | struct clk *clk_ptp; |
405f257f | 356 | |
91c0d987 NA |
357 | bool ptp_clk_on; |
358 | struct mutex ptp_clk_mutex; | |
9fc095f1 FD |
359 | unsigned int num_tx_queues; |
360 | unsigned int num_rx_queues; | |
91c0d987 | 361 | |
405f257f | 362 | /* The saved address of a sent-in-place packet/buffer, for skfree(). */ |
4d494cdc FD |
363 | struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; |
364 | struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; | |
405f257f | 365 | |
4d494cdc FD |
366 | unsigned int total_tx_ring_size; |
367 | unsigned int total_rx_ring_size; | |
405f257f | 368 | |
4d494cdc FD |
369 | unsigned long work_tx; |
370 | unsigned long work_rx; | |
371 | unsigned long work_ts; | |
372 | unsigned long work_mdio; | |
79f33912 | 373 | |
4d494cdc | 374 | unsigned short bufdesc_size; |
36e24e2e | 375 | |
405f257f FL |
376 | struct platform_device *pdev; |
377 | ||
405f257f FL |
378 | int dev_id; |
379 | ||
380 | /* Phylib and MDIO interface */ | |
381 | struct mii_bus *mii_bus; | |
382 | struct phy_device *phy_dev; | |
383 | int mii_timeout; | |
384 | uint phy_speed; | |
385 | phy_interface_t phy_interface; | |
407066f8 | 386 | struct device_node *phy_node; |
405f257f FL |
387 | int link; |
388 | int full_duplex; | |
d97e7497 | 389 | int speed; |
405f257f FL |
390 | struct completion mdio_done; |
391 | int irq[FEC_IRQ_NUM]; | |
ff43da86 | 392 | int bufdesc_ex; |
baa70a5c | 393 | int pause_flag; |
6605b730 | 394 | |
dc975382 | 395 | struct napi_struct napi; |
4c09eed9 | 396 | int csum_flags; |
dc975382 | 397 | |
36cdc743 RK |
398 | struct work_struct tx_timeout_work; |
399 | ||
6605b730 FL |
400 | struct ptp_clock *ptp_clock; |
401 | struct ptp_clock_info ptp_caps; | |
402 | unsigned long last_overflow_check; | |
403 | spinlock_t tmreg_lock; | |
404 | struct cyclecounter cc; | |
405 | struct timecounter tc; | |
406 | int rx_hwtstamp_filter; | |
407 | u32 base_incval; | |
408 | u32 cycle_speed; | |
409 | int hwts_rx_en; | |
410 | int hwts_tx_en; | |
91c0d987 | 411 | struct delayed_work time_keep; |
f4e9f3d2 | 412 | struct regulator *reg_phy; |
405f257f | 413 | }; |
1da177e4 | 414 | |
ca162a82 | 415 | void fec_ptp_init(struct platform_device *pdev); |
6605b730 | 416 | void fec_ptp_start_cyclecounter(struct net_device *ndev); |
1d5244d0 BH |
417 | int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); |
418 | int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); | |
6605b730 | 419 | |
1da177e4 LT |
420 | /****************************************************************************/ |
421 | #endif /* FEC_H */ |