[deliverable/linux.git] / drivers / net / ethernet / freescale / fec.h

/****************************************************************************/

/*
 *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
 *		   processors.
 *
 *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
 *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
 */

/****************************************************************************/
#ifndef FEC_H
#define	FEC_H
/****************************************************************************/

#include <linux/clocksource.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>

#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
/*
 *	Just figures, Motorola would have to change the offsets for
 *	registers in the same peripheral device on different models
 *	of the ColdFire!
 */
#define FEC_IEVENT		0x004 /* Interrupt event reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_ECNTRL		0x024 /* Ethernet control reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_MIB_CTRLSTAT	0x064 /* MIB control/status reg */
#define FEC_R_CNTRL		0x084 /* Receive control reg */
#define FEC_X_CNTRL		0x0c4 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
#define FEC_OPD			0x0ec /* Opcode + Pause duration */
#define FEC_HASH_TABLE_HIGH	0x118 /* High 32bits hash table */
#define FEC_HASH_TABLE_LOW	0x11c /* Low 32bits hash table */
#define FEC_GRP_HASH_TABLE_HIGH	0x120 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x124 /* Low 32bits hash table */
#define FEC_X_WMRK		0x144 /* FIFO transmit water mark */
#define FEC_R_BOUND		0x14c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x150 /* FIFO receive start reg */
#define FEC_R_DES_START		0x180 /* Receive descriptor ring */
#define FEC_X_DES_START		0x184 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x188 /* Maximum receive buff size */
#define FEC_R_FIFO_RSFL		0x190 /* Receive FIFO section full threshold */
#define FEC_R_FIFO_RSEM		0x194 /* Receive FIFO section empty threshold */
#define FEC_R_FIFO_RAEM		0x198 /* Receive FIFO almost empty threshold */
#define FEC_R_FIFO_RAFL		0x19c /* Receive FIFO almost full threshold */
#define FEC_RACC		0x1C4 /* Receive Accelerator function */
#define FEC_MIIGSK_CFGR		0x300 /* MIIGSK Configuration reg */
#define FEC_MIIGSK_ENR		0x308 /* MIIGSK Enable reg */

#define BM_MIIGSK_CFGR_MII		0x00
#define BM_MIIGSK_CFGR_RMII		0x01
#define BM_MIIGSK_CFGR_FRCONT_10M	0x40

#define RMON_T_DROP		0x200 /* Count of frames not cntd correctly */
#define RMON_T_PACKETS		0x204 /* RMON TX packet count */
#define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
#define RMON_T_MC_PKT		0x20C /* RMON TX multicast pkts */
#define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
#define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
#define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
#define RMON_T_FRAG		0x21C /* RMON TX pkts < 64 bytes, bad CRC */
#define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
#define RMON_T_COL		0x224 /* RMON TX collision count */
#define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
#define RMON_T_P65TO127		0x22C /* RMON TX 65 to 127 byte pkts */
#define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
#define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
#define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
#define RMON_T_P1024TO2047	0x23C /* RMON TX 1024 to 2047 byte pkts */
#define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
#define RMON_T_OCTETS		0x244 /* RMON TX octets */
#define IEEE_T_DROP		0x248 /* Count of frames not counted crtly */
#define IEEE_T_FRAME_OK		0x24C /* Frames tx'd OK */
#define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
#define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
#define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
#define IEEE_T_LCOL		0x25C /* Frames tx'd with late collision */
#define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
#define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
#define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
#define IEEE_T_SQE		0x26C /* Frames tx'd with SQE err */
#define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
#define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
#define RMON_R_PACKETS		0x284 /* RMON RX packet count */
#define RMON_R_BC_PKT		0x288 /* RMON RX broadcast pkts */
#define RMON_R_MC_PKT		0x28C /* RMON RX multicast pkts */
#define RMON_R_CRC_ALIGN	0x290 /* RMON RX pkts with CRC alignment err */
#define RMON_R_UNDERSIZE	0x294 /* RMON RX pkts < 64 bytes, good CRC */
#define RMON_R_OVERSIZE		0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
#define RMON_R_FRAG		0x29C /* RMON RX pkts < 64 bytes, bad CRC */
#define RMON_R_JAB		0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
#define RMON_R_RESVD_O		0x2A4 /* Reserved */
#define RMON_R_P64		0x2A8 /* RMON RX 64 byte pkts */
#define RMON_R_P65TO127		0x2AC /* RMON RX 65 to 127 byte pkts */
#define RMON_R_P128TO255	0x2B0 /* RMON RX 128 to 255 byte pkts */
#define RMON_R_P256TO511	0x2B4 /* RMON RX 256 to 511 byte pkts */
#define RMON_R_P512TO1023	0x2B8 /* RMON RX 512 to 1023 byte pkts */
#define RMON_R_P1024TO2047	0x2BC /* RMON RX 1024 to 2047 byte pkts */
#define RMON_R_P_GTE2048	0x2C0 /* RMON RX pkts > 2048 bytes */
#define RMON_R_OCTETS		0x2C4 /* RMON RX octets */
#define IEEE_R_DROP		0x2C8 /* Count frames not counted correctly */
#define IEEE_R_FRAME_OK		0x2CC /* Frames rx'd OK */
#define IEEE_R_CRC		0x2D0 /* Frames rx'd with CRC err */
#define IEEE_R_ALIGN		0x2D4 /* Frames rx'd with alignment err */
#define IEEE_R_MACERR		0x2D8 /* Receive FIFO overflow count */
#define IEEE_R_FDXFC		0x2DC /* Flow control pause frames rx'd */
#define IEEE_R_OCTETS_OK	0x2E0 /* Octet cnt for frames rx'd w/o err */

#else

#define FEC_ECNTRL		0x000 /* Ethernet control reg */
#define FEC_IEVENT		0x004 /* Interrupt even reg */
#define FEC_IMASK		0x008 /* Interrupt mask reg */
#define FEC_IVEC		0x00c /* Interrupt vec status reg */
#define FEC_R_DES_ACTIVE	0x010 /* Receive descriptor reg */
#define FEC_X_DES_ACTIVE	0x014 /* Transmit descriptor reg */
#define FEC_MII_DATA		0x040 /* MII manage frame reg */
#define FEC_MII_SPEED		0x044 /* MII speed control reg */
#define FEC_R_BOUND		0x08c /* FIFO receive bound reg */
#define FEC_R_FSTART		0x090 /* FIFO receive start reg */
#define FEC_X_WMRK		0x0a4 /* FIFO transmit water mark */
#define FEC_X_FSTART		0x0ac /* FIFO transmit start reg */
#define FEC_R_CNTRL		0x104 /* Receive control reg */
#define FEC_MAX_FRM_LEN		0x108 /* Maximum frame length reg */
#define FEC_X_CNTRL		0x144 /* Transmit Control reg */
#define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
#define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
#define FEC_GRP_HASH_TABLE_HIGH	0x3c8 /* High 32bits hash table */
#define FEC_GRP_HASH_TABLE_LOW	0x3cc /* Low 32bits hash table */
#define FEC_R_DES_START		0x3d0 /* Receive descriptor ring */
#define FEC_X_DES_START		0x3d4 /* Transmit descriptor ring */
#define FEC_R_BUFF_SIZE		0x3d8 /* Maximum receive buff size */
#define FEC_FIFO_RAM		0x400 /* FIFO RAM buffer */

#endif /* CONFIG_M5272 */


/*
 *	Define the buffer descriptor structure.
 */
#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
struct bufdesc {
	unsigned short cbd_datlen;	/* Data length */
	unsigned short cbd_sc;	/* Control and status info */
	unsigned long cbd_bufaddr;	/* Buffer address */
};
#else
struct bufdesc {
	unsigned short	cbd_sc;			/* Control and status info */
	unsigned short	cbd_datlen;		/* Data length */
	unsigned long	cbd_bufaddr;		/* Buffer address */
};
#endif

struct bufdesc_ex {
	struct bufdesc desc;
	unsigned long cbd_esc;
	unsigned long cbd_prot;
	unsigned long cbd_bdu;
	unsigned long ts;
	unsigned short res0[4];
};

/*
 *	The following definitions courtesy of commproc.h, which where
 *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
 */
#define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
#define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
#define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
#define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
#define BD_SC_CM        ((ushort)0x0200)        /* Continuous mode */
#define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
#define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
#define BD_SC_BR        ((ushort)0x0020)        /* Break received */
#define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
#define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
#define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
#define BD_SC_CD        ((ushort)0x0001)        /* ?? */

/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY        ((ushort)0x8000)
#define BD_ENET_RX_WRAP         ((ushort)0x2000)
#define BD_ENET_RX_INTR         ((ushort)0x1000)
#define BD_ENET_RX_LAST         ((ushort)0x0800)
#define BD_ENET_RX_FIRST        ((ushort)0x0400)
#define BD_ENET_RX_MISS         ((ushort)0x0100)
#define BD_ENET_RX_LG           ((ushort)0x0020)
#define BD_ENET_RX_NO           ((ushort)0x0010)
#define BD_ENET_RX_SH           ((ushort)0x0008)
#define BD_ENET_RX_CR           ((ushort)0x0004)
#define BD_ENET_RX_OV           ((ushort)0x0002)
#define BD_ENET_RX_CL           ((ushort)0x0001)
#define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */

/* Enhanced buffer descriptor control/status used by Ethernet receive */
#define BD_ENET_RX_VLAN         0x00000004

/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY        ((ushort)0x8000)
#define BD_ENET_TX_PAD          ((ushort)0x4000)
#define BD_ENET_TX_WRAP         ((ushort)0x2000)
#define BD_ENET_TX_INTR         ((ushort)0x1000)
#define BD_ENET_TX_LAST         ((ushort)0x0800)
#define BD_ENET_TX_TC           ((ushort)0x0400)
#define BD_ENET_TX_DEF          ((ushort)0x0200)
#define BD_ENET_TX_HB           ((ushort)0x0100)
#define BD_ENET_TX_LC           ((ushort)0x0080)
#define BD_ENET_TX_RL           ((ushort)0x0040)
#define BD_ENET_TX_RCMASK       ((ushort)0x003c)
#define BD_ENET_TX_UN           ((ushort)0x0002)
#define BD_ENET_TX_CSL          ((ushort)0x0001)
#define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */

/*enhanced buffer descriptor control/status used by Ethernet transmit*/
#define BD_ENET_TX_INT          0x40000000
#define BD_ENET_TX_TS           0x20000000
#define BD_ENET_TX_PINS         0x10000000
#define BD_ENET_TX_IINS         0x08000000


/* This device has up to three irqs on some platforms */
#define FEC_IRQ_NUM		3

/* The number of Tx and Rx buffers.  These are allocated from the page
 * pool.  The code may assume these are power of two, so it it best
 * to keep them that size.
 * We don't need to allocate pages for the transmitter.  We just use
 * the skbuffer directly.
 */

#define FEC_ENET_RX_PAGES	8
#define FEC_ENET_RX_FRSIZE	2048
#define FEC_ENET_RX_FRPPG	(PAGE_SIZE / FEC_ENET_RX_FRSIZE)
#define RX_RING_SIZE		(FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
#define FEC_ENET_TX_FRSIZE	2048
#define FEC_ENET_TX_FRPPG	(PAGE_SIZE / FEC_ENET_TX_FRSIZE)
#define TX_RING_SIZE		16	/* Must be power of two */
#define TX_RING_MOD_MASK	15	/*   for this to work */

#define BD_ENET_RX_INT          0x00800000
#define BD_ENET_RX_PTP          ((ushort)0x0400)
#define BD_ENET_RX_ICE		0x00000020
#define BD_ENET_RX_PCR		0x00000010
#define FLAG_RX_CSUM_ENABLED	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)
#define FLAG_RX_CSUM_ERROR	(BD_ENET_RX_ICE | BD_ENET_RX_PCR)

struct fec_enet_delayed_work {
	struct delayed_work delay_work;
	bool timeout;
	bool trig_tx;
};

/* The FEC buffer descriptors track the ring buffers.  The rx_bd_base and
 * tx_bd_base always point to the base of the buffer descriptors.  The
 * cur_rx and cur_tx point to the currently available buffer.
 * The dirty_tx tracks the current buffer that is being sent by the
 * controller.  The cur_tx and dirty_tx are equal under both completely
 * empty and completely full conditions.  The empty/ready indicator in
 * the buffer descriptor determines the actual condition.
 */
struct fec_enet_private {
	/* Hardware registers of the FEC device */
	void __iomem *hwp;

	struct net_device *netdev;

	struct clk *clk_ipg;
	struct clk *clk_ahb;
	struct clk *clk_enet_out;
	struct clk *clk_ptp;

	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	unsigned char *tx_bounce[TX_RING_SIZE];
	struct	sk_buff *tx_skbuff[TX_RING_SIZE];
	struct	sk_buff *rx_skbuff[RX_RING_SIZE];

	/* CPM dual port RAM relative addresses */
	dma_addr_t	bd_dma;
	/* Address of Rx and Tx buffers */
	struct bufdesc	*rx_bd_base;
	struct bufdesc	*tx_bd_base;
	/* The next free ring entry */
	struct bufdesc	*cur_rx, *cur_tx;
	/* The ring entries to be free()ed */
	struct bufdesc	*dirty_tx;

	unsigned short tx_ring_size;
	unsigned short rx_ring_size;

	struct	platform_device *pdev;

	int	opened;
	int	dev_id;

	/* Phylib and MDIO interface */
	struct	mii_bus *mii_bus;
	struct	phy_device *phy_dev;
	int	mii_timeout;
	uint	phy_speed;
	phy_interface_t	phy_interface;
	int	link;
	int	full_duplex;
	int	speed;
	struct	completion mdio_done;
	int	irq[FEC_IRQ_NUM];
	int	bufdesc_ex;
	int	pause_flag;

	struct	napi_struct napi;
	int	csum_flags;

	struct ptp_clock *ptp_clock;
	struct ptp_clock_info ptp_caps;
	unsigned long last_overflow_check;
	spinlock_t tmreg_lock;
	struct cyclecounter cc;
	struct timecounter tc;
	int rx_hwtstamp_filter;
	u32 base_incval;
	u32 cycle_speed;
	int hwts_rx_en;
	int hwts_tx_en;
	struct timer_list time_keep;
	struct fec_enet_delayed_work delay_work;
	struct regulator *reg_phy;
};

void fec_ptp_init(struct platform_device *pdev);
void fec_ptp_start_cyclecounter(struct net_device *ndev);
int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);

/****************************************************************************/
#endif /* FEC_H */
Commit	Line	Data
1da177e4 LT	1	/****************************************************************************/
	2
	3	/*
7a77d918 GU	4	* fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
7a77d918 GU	5	* processors.
1da177e4	6	*
7a77d918	7	* (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
1da177e4 LT	8	* (C) Copyright 2000-2001, Lineo (www.lineo.com)
	9	*/
	10
	11	/****************************************************************************/
	12	#ifndef FEC_H
	13	#define FEC_H
	14	/****************************************************************************/
	15
6605b730 FL	16	#include <linux/clocksource.h>
	17	#include <linux/net_tstamp.h>
	18	#include <linux/ptp_clock_kernel.h>
6605b730	19
7a77d918	20	#if defined(CONFIG_M523x) \|\| defined(CONFIG_M527x) \|\| defined(CONFIG_M528x) \|\| \
b5680e0b SG	21	defined(CONFIG_M520x) \|\| defined(CONFIG_M532x) \|\| \
b5680e0b SG	22	defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
1da177e4 LT	23	/*
	24	* Just figures, Motorola would have to change the offsets for
	25	* registers in the same peripheral device on different models
	26	* of the ColdFire!
	27	*/
f44d6305 SH	28	#define FEC_IEVENT 0x004 /* Interrupt event reg */
	29	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	30	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
	31	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
	32	#define FEC_ECNTRL 0x024 /* Ethernet control reg */
	33	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	34	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	35	#define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */
	36	#define FEC_R_CNTRL 0x084 /* Receive control reg */
	37	#define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */
	38	#define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
	39	#define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
	40	#define FEC_OPD 0x0ec /* Opcode + Pause duration */
	41	#define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
	42	#define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
	43	#define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
	44	#define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */
	45	#define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
	46	#define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
	47	#define FEC_R_FSTART 0x150 /* FIFO receive start reg */
	48	#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
	49	#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
	50	#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
baa70a5c FL	51	#define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
	52	#define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
	53	#define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
	54	#define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
4c09eed9	55	#define FEC_RACC 0x1C4 /* Receive Accelerator function */
5eb32bd0 BS	56	#define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
5eb32bd0 BS	57	#define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
1da177e4	58
8d82f219 EB	59	#define BM_MIIGSK_CFGR_MII 0x00
	60	#define BM_MIIGSK_CFGR_RMII 0x01
	61	#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
	62
38ae92dc CH	63	#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
	64	#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
	65	#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
	66	#define RMON_T_MC_PKT 0x20C /* RMON TX multicast pkts */
	67	#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
	68	#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
	69	#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
	70	#define RMON_T_FRAG 0x21C /* RMON TX pkts < 64 bytes, bad CRC */
	71	#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
	72	#define RMON_T_COL 0x224 /* RMON TX collision count */
	73	#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
	74	#define RMON_T_P65TO127 0x22C /* RMON TX 65 to 127 byte pkts */
	75	#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
	76	#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
	77	#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
	78	#define RMON_T_P1024TO2047 0x23C /* RMON TX 1024 to 2047 byte pkts */
	79	#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
	80	#define RMON_T_OCTETS 0x244 /* RMON TX octets */
	81	#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
	82	#define IEEE_T_FRAME_OK 0x24C /* Frames tx'd OK */
	83	#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
	84	#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
	85	#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
	86	#define IEEE_T_LCOL 0x25C /* Frames tx'd with late collision */
	87	#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
	88	#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
	89	#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
	90	#define IEEE_T_SQE 0x26C /* Frames tx'd with SQE err */
	91	#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
	92	#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
	93	#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
	94	#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
	95	#define RMON_R_MC_PKT 0x28C /* RMON RX multicast pkts */
	96	#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
	97	#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
	98	#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
	99	#define RMON_R_FRAG 0x29C /* RMON RX pkts < 64 bytes, bad CRC */
	100	#define RMON_R_JAB 0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
	101	#define RMON_R_RESVD_O 0x2A4 /* Reserved */
	102	#define RMON_R_P64 0x2A8 /* RMON RX 64 byte pkts */
	103	#define RMON_R_P65TO127 0x2AC /* RMON RX 65 to 127 byte pkts */
	104	#define RMON_R_P128TO255 0x2B0 /* RMON RX 128 to 255 byte pkts */
	105	#define RMON_R_P256TO511 0x2B4 /* RMON RX 256 to 511 byte pkts */
	106	#define RMON_R_P512TO1023 0x2B8 /* RMON RX 512 to 1023 byte pkts */
	107	#define RMON_R_P1024TO2047 0x2BC /* RMON RX 1024 to 2047 byte pkts */
	108	#define RMON_R_P_GTE2048 0x2C0 /* RMON RX pkts > 2048 bytes */
	109	#define RMON_R_OCTETS 0x2C4 /* RMON RX octets */
	110	#define IEEE_R_DROP 0x2C8 /* Count frames not counted correctly */
	111	#define IEEE_R_FRAME_OK 0x2CC /* Frames rx'd OK */
	112	#define IEEE_R_CRC 0x2D0 /* Frames rx'd with CRC err */
	113	#define IEEE_R_ALIGN 0x2D4 /* Frames rx'd with alignment err */
	114	#define IEEE_R_MACERR 0x2D8 /* Receive FIFO overflow count */
	115	#define IEEE_R_FDXFC 0x2DC /* Flow control pause frames rx'd */
	116	#define IEEE_R_OCTETS_OK 0x2E0 /* Octet cnt for frames rx'd w/o err */
	117
1da177e4 LT	118	#else
1da177e4 LT	119
9ff1a91c GU	120	#define FEC_ECNTRL 0x000 /* Ethernet control reg */
	121	#define FEC_IEVENT 0x004 /* Interrupt even reg */
	122	#define FEC_IMASK 0x008 /* Interrupt mask reg */
	123	#define FEC_IVEC 0x00c /* Interrupt vec status reg */
	124	#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
5ca1ea23	125	#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
f44d6305 SH	126	#define FEC_MII_DATA 0x040 /* MII manage frame reg */
	127	#define FEC_MII_SPEED 0x044 /* MII speed control reg */
	128	#define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
	129	#define FEC_R_FSTART 0x090 /* FIFO receive start reg */
	130	#define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */
	131	#define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */
	132	#define FEC_R_CNTRL 0x104 /* Receive control reg */
	133	#define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */
	134	#define FEC_X_CNTRL 0x144 /* Transmit Control reg */
	135	#define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */
	136	#define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
	137	#define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
	138	#define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
	139	#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
	140	#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
	141	#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
	142	#define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
1da177e4 LT	143
	144	#endif /* CONFIG_M5272 */
	145
	146
	147	/*
	148	* Define the buffer descriptor structure.
	149	*/
b5680e0b	150	#if defined(CONFIG_ARCH_MXC) \|\| defined(CONFIG_SOC_IMX28)
2e28532f	151	struct bufdesc {
196719ec SH	152	unsigned short cbd_datlen; /* Data length */
	153	unsigned short cbd_sc; /* Control and status info */
	154	unsigned long cbd_bufaddr; /* Buffer address */
ff43da86	155	};
acac8406 FL	156	#else
	157	struct bufdesc {
	158	unsigned short cbd_sc; /* Control and status info */
	159	unsigned short cbd_datlen; /* Data length */
	160	unsigned long cbd_bufaddr; /* Buffer address */
	161	};
	162	#endif
ff43da86 FL	163
	164	struct bufdesc_ex {
	165	struct bufdesc desc;
6605b730 FL	166	unsigned long cbd_esc;
	167	unsigned long cbd_prot;
	168	unsigned long cbd_bdu;
	169	unsigned long ts;
	170	unsigned short res0[4];
2e28532f	171	};
ff43da86	172
1da177e4 LT	173	/*
	174	* The following definitions courtesy of commproc.h, which where
	175	* Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
	176	*/
25985edc	177	#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
1da177e4 LT	178	#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
	179	#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
	180	#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
25985edc	181	#define BD_SC_CM ((ushort)0x0200) /* Continuous mode */
1da177e4 LT	182	#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
	183	#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
	184	#define BD_SC_BR ((ushort)0x0020) /* Break received */
	185	#define BD_SC_FR ((ushort)0x0010) /* Framing error */
	186	#define BD_SC_PR ((ushort)0x0008) /* Parity error */
	187	#define BD_SC_OV ((ushort)0x0002) /* Overrun */
	188	#define BD_SC_CD ((ushort)0x0001) /* ?? */
	189
	190	/* Buffer descriptor control/status used by Ethernet receive.
	191	*/
	192	#define BD_ENET_RX_EMPTY ((ushort)0x8000)
	193	#define BD_ENET_RX_WRAP ((ushort)0x2000)
	194	#define BD_ENET_RX_INTR ((ushort)0x1000)
	195	#define BD_ENET_RX_LAST ((ushort)0x0800)
	196	#define BD_ENET_RX_FIRST ((ushort)0x0400)
	197	#define BD_ENET_RX_MISS ((ushort)0x0100)
	198	#define BD_ENET_RX_LG ((ushort)0x0020)
	199	#define BD_ENET_RX_NO ((ushort)0x0010)
	200	#define BD_ENET_RX_SH ((ushort)0x0008)
	201	#define BD_ENET_RX_CR ((ushort)0x0004)
	202	#define BD_ENET_RX_OV ((ushort)0x0002)
	203	#define BD_ENET_RX_CL ((ushort)0x0001)
	204	#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
	205
cdffcf1b JB	206	/* Enhanced buffer descriptor control/status used by Ethernet receive */
	207	#define BD_ENET_RX_VLAN 0x00000004
	208
1da177e4 LT	209	/* Buffer descriptor control/status used by Ethernet transmit.
	210	*/
	211	#define BD_ENET_TX_READY ((ushort)0x8000)
	212	#define BD_ENET_TX_PAD ((ushort)0x4000)
	213	#define BD_ENET_TX_WRAP ((ushort)0x2000)
	214	#define BD_ENET_TX_INTR ((ushort)0x1000)
	215	#define BD_ENET_TX_LAST ((ushort)0x0800)
	216	#define BD_ENET_TX_TC ((ushort)0x0400)
	217	#define BD_ENET_TX_DEF ((ushort)0x0200)
	218	#define BD_ENET_TX_HB ((ushort)0x0100)
	219	#define BD_ENET_TX_LC ((ushort)0x0080)
	220	#define BD_ENET_TX_RL ((ushort)0x0040)
	221	#define BD_ENET_TX_RCMASK ((ushort)0x003c)
	222	#define BD_ENET_TX_UN ((ushort)0x0002)
	223	#define BD_ENET_TX_CSL ((ushort)0x0001)
	224	#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
	225
4c09eed9	226	/enhanced buffer descriptor control/status used by Ethernet transmit/
405f257f FL	227	#define BD_ENET_TX_INT 0x40000000
405f257f FL	228	#define BD_ENET_TX_TS 0x20000000
4c09eed9 JB	229	#define BD_ENET_TX_PINS 0x10000000
4c09eed9 JB	230	#define BD_ENET_TX_IINS 0x08000000
405f257f FL	231
	232
	233	/* This device has up to three irqs on some platforms */
	234	#define FEC_IRQ_NUM 3
	235
	236	/* The number of Tx and Rx buffers. These are allocated from the page
	237	* pool. The code may assume these are power of two, so it it best
	238	* to keep them that size.
	239	* We don't need to allocate pages for the transmitter. We just use
	240	* the skbuffer directly.
	241	*/
	242
	243	#define FEC_ENET_RX_PAGES 8
	244	#define FEC_ENET_RX_FRSIZE 2048
	245	#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
	246	#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
	247	#define FEC_ENET_TX_FRSIZE 2048
	248	#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
	249	#define TX_RING_SIZE 16 /* Must be power of two */
	250	#define TX_RING_MOD_MASK 15 /* for this to work */
	251
	252	#define BD_ENET_RX_INT 0x00800000
	253	#define BD_ENET_RX_PTP ((ushort)0x0400)
4c09eed9 JB	254	#define BD_ENET_RX_ICE 0x00000020
	255	#define BD_ENET_RX_PCR 0x00000010
	256	#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE \| BD_ENET_RX_PCR)
	257	#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE \| BD_ENET_RX_PCR)
405f257f	258
54309fa6 FL	259	struct fec_enet_delayed_work {
	260	struct delayed_work delay_work;
	261	bool timeout;
03191656	262	bool trig_tx;
54309fa6 FL	263	};
54309fa6 FL	264
405f257f FL	265	/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
	266	* tx_bd_base always point to the base of the buffer descriptors. The
	267	* cur_rx and cur_tx point to the currently available buffer.
	268	* The dirty_tx tracks the current buffer that is being sent by the
	269	* controller. The cur_tx and dirty_tx are equal under both completely
	270	* empty and completely full conditions. The empty/ready indicator in
	271	* the buffer descriptor determines the actual condition.
	272	*/
	273	struct fec_enet_private {
	274	/* Hardware registers of the FEC device */
	275	void __iomem *hwp;
	276
	277	struct net_device *netdev;
	278
	279	struct clk *clk_ipg;
	280	struct clk *clk_ahb;
daa7d392	281	struct clk *clk_enet_out;
6605b730	282	struct clk *clk_ptp;
405f257f FL	283
	284	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	285	unsigned char *tx_bounce[TX_RING_SIZE];
	286	struct sk_buff *tx_skbuff[TX_RING_SIZE];
	287	struct sk_buff *rx_skbuff[RX_RING_SIZE];
405f257f FL	288
	289	/* CPM dual port RAM relative addresses */
	290	dma_addr_t bd_dma;
	291	/* Address of Rx and Tx buffers */
	292	struct bufdesc *rx_bd_base;
	293	struct bufdesc *tx_bd_base;
	294	/* The next free ring entry */
	295	struct bufdesc cur_rx, cur_tx;
	296	/* The ring entries to be free()ed */
	297	struct bufdesc *dirty_tx;
	298
36e24e2e DFB	299	unsigned short tx_ring_size;
	300	unsigned short rx_ring_size;
	301
405f257f FL	302	struct platform_device *pdev;
	303
	304	int opened;
	305	int dev_id;
	306
	307	/* Phylib and MDIO interface */
	308	struct mii_bus *mii_bus;
	309	struct phy_device *phy_dev;
	310	int mii_timeout;
	311	uint phy_speed;
	312	phy_interface_t phy_interface;
	313	int link;
	314	int full_duplex;
d97e7497	315	int speed;
405f257f FL	316	struct completion mdio_done;
405f257f FL	317	int irq[FEC_IRQ_NUM];
ff43da86	318	int bufdesc_ex;
baa70a5c	319	int pause_flag;
6605b730	320
dc975382	321	struct napi_struct napi;
4c09eed9	322	int csum_flags;
dc975382	323
6605b730 FL	324	struct ptp_clock *ptp_clock;
	325	struct ptp_clock_info ptp_caps;
	326	unsigned long last_overflow_check;
	327	spinlock_t tmreg_lock;
	328	struct cyclecounter cc;
	329	struct timecounter tc;
	330	int rx_hwtstamp_filter;
	331	u32 base_incval;
	332	u32 cycle_speed;
	333	int hwts_rx_en;
	334	int hwts_tx_en;
	335	struct timer_list time_keep;
54309fa6	336	struct fec_enet_delayed_work delay_work;
f4e9f3d2	337	struct regulator *reg_phy;
405f257f	338	};
1da177e4	339
ca162a82	340	void fec_ptp_init(struct platform_device *pdev);
6605b730 FL	341	void fec_ptp_start_cyclecounter(struct net_device *ndev);
6605b730 FL	342	int fec_ptp_ioctl(struct net_device ndev, struct ifreq ifr, int cmd);
6605b730	343
1da177e4 LT	344	/****************************************************************************/
1da177e4 LT	345	#endif /* FEC_H */