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Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
8fff755e 27#include <linux/pm_runtime.h>
1da177e4
LT		 28#include <linux/ptrace.h>
29#include <linux/errno.h>
30#include <linux/ioport.h>
31#include <linux/slab.h>
32#include <linux/interrupt.h>
1da177e4
LT		 33#include <linux/delay.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
4c09eed9
JB		 37#include <linux/in.h>
38#include <linux/ip.h>
39#include <net/ip.h>
79f33912 40#include <net/tso.h>
4c09eed9
JB		 41#include <linux/tcp.h>
42#include <linux/udp.h>
43#include <linux/icmp.h>
1da177e4
LT		 44#include <linux/spinlock.h>
45#include <linux/workqueue.h>
46#include <linux/bitops.h>
6f501b17
SH		 47#include <linux/io.h>
48#include <linux/irq.h>
196719ec 49#include <linux/clk.h>
ead73183 50#include <linux/platform_device.h>
7f854420 51#include <linux/mdio.h>
e6b043d5 52#include <linux/phy.h>
5eb32bd0 53#include <linux/fec.h>
ca2cc333
SG		 54#include <linux/of.h>
55#include <linux/of_device.h>
56#include <linux/of_gpio.h>
407066f8 57#include <linux/of_mdio.h>
ca2cc333 58#include <linux/of_net.h>
5fa9c0fe 59#include <linux/regulator/consumer.h>
cdffcf1b 60#include <linux/if_vlan.h>
a68ab98e 61#include <linux/pinctrl/consumer.h>
c259c132 62#include <linux/prefetch.h>
1da177e4 63
080853af 64#include <asm/cacheflush.h>
196719ec 65
1da177e4 66#include "fec.h"
1da177e4 67
772e42b0 68static void set_multicast_list(struct net_device *ndev);
d851b47b 69static void fec_enet_itr_coal_init(struct net_device *ndev);
772e42b0 70
b5680e0b
SG		 71#define DRIVER_NAME "fec"
72
4d494cdc
FD		 73#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
74
baa70a5c
FL		 75/* Pause frame feild and FIFO threshold */
76#define FEC_ENET_FCE (1 << 5)
77#define FEC_ENET_RSEM_V 0x84
78#define FEC_ENET_RSFL_V 16
79#define FEC_ENET_RAEM_V 0x8
80#define FEC_ENET_RAFL_V 0x8
81#define FEC_ENET_OPD_V 0xFFF0
8fff755e 82#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
baa70a5c 83
b5680e0b
SG		 84static struct platform_device_id fec_devtype[] = {
85 {
0ca1e290 86 /* keep it for coldfire */
b5680e0b
SG		 87 .name = DRIVER_NAME,
88 .driver_data = 0,
0ca1e290
SG		 89 }, {
90 .name = "imx25-fec",
18803495 91 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 92 }, {
93 .name = "imx27-fec",
18803495 94 .driver_data = FEC_QUIRK_HAS_RACC,
b5680e0b
SG		 95 }, {
96 .name = "imx28-fec",
3d125f9c 97 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
18803495 98 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC,
230dec61
SG		 99 }, {
100 .name = "imx6q-fec",
ff43da86 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 102 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
18803495
GU		 103 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
104 FEC_QUIRK_HAS_RACC,
ca7c4a45 105 }, {
36803542 106 .name = "mvf600-fec",
18803495 107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
95a77470
FD		 108 }, {
109 .name = "imx6sx-fec",
110 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
111 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
f88c7ede 112 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
18803495
GU		 113 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
114 FEC_QUIRK_HAS_RACC,
0ca1e290
SG		 115 }, {
116 /* sentinel */
117 }
b5680e0b 118};
0ca1e290 119MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 120
ca2cc333 121enum imx_fec_type {
a7dd3219 122 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 123 IMX27_FEC, /* runs on i.mx27/35/51 */
124 IMX28_FEC,
230dec61 125 IMX6Q_FEC,
36803542 126 MVF600_FEC,
ba593e00 127 IMX6SX_FEC,
ca2cc333
SG		 128};
129
130static const struct of_device_id fec_dt_ids[] = {
131 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
132 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
133 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 134 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 135 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ba593e00 136 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
ca2cc333
SG		 137 { /* sentinel */ }
138};
139MODULE_DEVICE_TABLE(of, fec_dt_ids);
140
49da97dc
SG		 141static unsigned char macaddr[ETH_ALEN];
142module_param_array(macaddr, byte, NULL, 0);
143MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 144
49da97dc 145#if defined(CONFIG_M5272)
1da177e4
LT		 146/*
147 * Some hardware gets it MAC address out of local flash memory.
148 * if this is non-zero then assume it is the address to get MAC from.
149 */
150#if defined(CONFIG_NETtel)
151#define FEC_FLASHMAC 0xf0006006
152#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
153#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 154#elif defined(CONFIG_CANCam)
155#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 156#elif defined (CONFIG_M5272C3)
157#define FEC_FLASHMAC (0xffe04000 + 4)
158#elif defined(CONFIG_MOD5272)
a7dd3219 159#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 160#else
161#define FEC_FLASHMAC 0
162#endif
43be6366 163#endif /* CONFIG_M5272 */
ead73183 164
cdffcf1b 165/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 166 */
cdffcf1b 167#define PKT_MAXBUF_SIZE 1522
1da177e4 168#define PKT_MINBUF_SIZE 64
cdffcf1b 169#define PKT_MAXBLR_SIZE 1536
1da177e4 170
4c09eed9
JB		 171/* FEC receive acceleration */
172#define FEC_RACC_IPDIS (1 << 1)
173#define FEC_RACC_PRODIS (1 << 2)
174#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
175
1da177e4 176/*
6b265293 177 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 178 * size bits. Other FEC hardware does not, so we need to take that into
179 * account when setting it.
180 */
562d2f8c 181#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 182 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 183#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
184#else
185#define OPT_FRAME_SIZE 0
186#endif
187
e6b043d5
BW		 188/* FEC MII MMFR bits definition */
189#define FEC_MMFR_ST (1 << 30)
190#define FEC_MMFR_OP_READ (2 << 28)
191#define FEC_MMFR_OP_WRITE (1 << 28)
192#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
193#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
194#define FEC_MMFR_TA (2 << 16)
195#define FEC_MMFR_DATA(v) (v & 0xffff)
de40ed31
NA		 196/* FEC ECR bits definition */
197#define FEC_ECR_MAGICEN (1 << 2)
198#define FEC_ECR_SLEEP (1 << 3)
1da177e4 199
c3b084c2 200#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 201
22f6b860
SH		 202/* Transmitter timeout */
203#define TX_TIMEOUT (2 * HZ)
1da177e4 204
baa70a5c
FL		 205#define FEC_PAUSE_FLAG_AUTONEG 0x1
206#define FEC_PAUSE_FLAG_ENABLE 0x2
de40ed31
NA		 207#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
208#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
209#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
baa70a5c 210
1b7bde6d
NA		 211#define COPYBREAK_DEFAULT 256
212
79f33912
NA		 213#define TSO_HEADER_SIZE 128
214/* Max number of allowed TCP segments for software TSO */
215#define FEC_MAX_TSO_SEGS 100
216#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
217
218#define IS_TSO_HEADER(txq, addr) \
219 ((addr >= txq->tso_hdrs_dma) && \
7355f276 220 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
79f33912 221
e163cc97
LW		 222static int mii_cnt;
223
7355f276
TK		 224static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
225 struct bufdesc_prop *bd)
226{
227 return (bdp >= bd->last) ? bd->base
228 : (struct bufdesc *)(((unsigned)bdp) + bd->dsize);
229}
36e24e2e 230
7355f276
TK		 231static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
232 struct bufdesc_prop *bd)
233{
234 return (bdp <= bd->base) ? bd->last
235 : (struct bufdesc *)(((unsigned)bdp) - bd->dsize);
ff43da86
FL		 236}
237
7355f276
TK		 238static int fec_enet_get_bd_index(struct bufdesc *bdp,
239 struct bufdesc_prop *bd)
61a4427b 240{
7355f276 241 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
61a4427b
NA		 242}
243
7355f276 244static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
6e909283
NA		 245{
246 int entries;
247
7355f276
TK		 248 entries = (((const char *)txq->dirty_tx -
249 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
6e909283 250
7355f276 251 return entries >= 0 ? entries : entries + txq->bd.ring_size;
6e909283
NA		 252}
253
c20e599b 254static void swap_buffer(void *bufaddr, int len)
b5680e0b
SG		 255{
256 int i;
257 unsigned int *buf = bufaddr;
258
7b487d07 259 for (i = 0; i < len; i += 4, buf++)
e453789a 260 swab32s(buf);
b5680e0b
SG		 261}
262
1310b544
LW		 263static void swap_buffer2(void *dst_buf, void *src_buf, int len)
264{
265 int i;
266 unsigned int *src = src_buf;
267 unsigned int *dst = dst_buf;
268
269 for (i = 0; i < len; i += 4, src++, dst++)
270 *dst = swab32p(src);
271}
272
344756f6
RK		 273static void fec_dump(struct net_device *ndev)
274{
275 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc
FD		 276 struct bufdesc *bdp;
277 struct fec_enet_priv_tx_q *txq;
278 int index = 0;
344756f6
RK		 279
280 netdev_info(ndev, "TX ring dump\n");
281 pr_info("Nr SC addr len SKB\n");
282
4d494cdc 283 txq = fep->tx_queue[0];
7355f276 284 bdp = txq->bd.base;
4d494cdc 285
344756f6 286 do {
5cfa3039 287 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
344756f6 288 index,
7355f276 289 bdp == txq->bd.cur ? 'S' : ' ',
4d494cdc 290 bdp == txq->dirty_tx ? 'H' : ' ',
5cfa3039
JB		 291 fec16_to_cpu(bdp->cbd_sc),
292 fec32_to_cpu(bdp->cbd_bufaddr),
293 fec16_to_cpu(bdp->cbd_datlen),
4d494cdc 294 txq->tx_skbuff[index]);
7355f276 295 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
344756f6 296 index++;
7355f276 297 } while (bdp != txq->bd.base);
344756f6
RK		 298}
299
62a02c98
FD		 300static inline bool is_ipv4_pkt(struct sk_buff *skb)
301{
302 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
303}
304
4c09eed9
JB		 305static int
306fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
307{
308 /* Only run for packets requiring a checksum. */
309 if (skb->ip_summed != CHECKSUM_PARTIAL)
310 return 0;
311
312 if (unlikely(skb_cow_head(skb, 0)))
313 return -1;
314
62a02c98
FD		 315 if (is_ipv4_pkt(skb))
316 ip_hdr(skb)->check = 0;
4c09eed9
JB		 317 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
318
319 return 0;
320}
321
c4bc44c6 322static struct bufdesc *
4d494cdc
FD		 323fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
324 struct sk_buff *skb,
325 struct net_device *ndev)
1da177e4 326{
c556167f 327 struct fec_enet_private *fep = netdev_priv(ndev);
7355f276 328 struct bufdesc *bdp = txq->bd.cur;
6e909283
NA		 329 struct bufdesc_ex *ebdp;
330 int nr_frags = skb_shinfo(skb)->nr_frags;
331 int frag, frag_len;
332 unsigned short status;
333 unsigned int estatus = 0;
334 skb_frag_t *this_frag;
de5fb0a0 335 unsigned int index;
6e909283 336 void *bufaddr;
d6bf3143 337 dma_addr_t addr;
6e909283 338 int i;
1da177e4 339
6e909283
NA		 340 for (frag = 0; frag < nr_frags; frag++) {
341 this_frag = &skb_shinfo(skb)->frags[frag];
7355f276 342 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6e909283
NA		 343 ebdp = (struct bufdesc_ex *)bdp;
344
5cfa3039 345 status = fec16_to_cpu(bdp->cbd_sc);
6e909283
NA		 346 status &= ~BD_ENET_TX_STATS;
347 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
348 frag_len = skb_shinfo(skb)->frags[frag].size;
349
350 /* Handle the last BD specially */
351 if (frag == nr_frags - 1) {
352 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
353 if (fep->bufdesc_ex) {
354 estatus |= BD_ENET_TX_INT;
355 if (unlikely(skb_shinfo(skb)->tx_flags &
356 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
357 estatus |= BD_ENET_TX_TS;
358 }
359 }
360
361 if (fep->bufdesc_ex) {
6b7e4008 362 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 363 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
6e909283
NA		 364 if (skb->ip_summed == CHECKSUM_PARTIAL)
365 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
366 ebdp->cbd_bdu = 0;
5cfa3039 367 ebdp->cbd_esc = cpu_to_fec32(estatus);
6e909283
NA		 368 }
369
370 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
371
7355f276 372 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 373 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 374 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 375 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
376 bufaddr = txq->tx_bounce[index];
6e909283 377
6b7e4008 378 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 379 swap_buffer(bufaddr, frag_len);
380 }
381
d6bf3143
RK		 382 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
383 DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 385 if (net_ratelimit())
386 netdev_err(ndev, "Tx DMA memory map failed\n");
387 goto dma_mapping_error;
388 }
389
5cfa3039
JB		 390 bdp->cbd_bufaddr = cpu_to_fec32(addr);
391 bdp->cbd_datlen = cpu_to_fec16(frag_len);
be293467
TK		 392 /* Make sure the updates to rest of the descriptor are
393 * performed before transferring ownership.
394 */
395 wmb();
5cfa3039 396 bdp->cbd_sc = cpu_to_fec16(status);
6e909283
NA		 397 }
398
c4bc44c6 399 return bdp;
6e909283 400dma_mapping_error:
7355f276 401 bdp = txq->bd.cur;
6e909283 402 for (i = 0; i < frag; i++) {
7355f276 403 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
5cfa3039
JB		 404 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
405 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
6e909283 406 }
c4bc44c6 407 return ERR_PTR(-ENOMEM);
6e909283 408}
1da177e4 409
4d494cdc
FD		 410static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
411 struct sk_buff *skb, struct net_device *ndev)
6e909283
NA		 412{
413 struct fec_enet_private *fep = netdev_priv(ndev);
6e909283
NA		 414 int nr_frags = skb_shinfo(skb)->nr_frags;
415 struct bufdesc *bdp, *last_bdp;
416 void *bufaddr;
d6bf3143 417 dma_addr_t addr;
6e909283
NA		 418 unsigned short status;
419 unsigned short buflen;
420 unsigned int estatus = 0;
421 unsigned int index;
79f33912 422 int entries_free;
22f6b860 423
7355f276 424 entries_free = fec_enet_get_free_txdesc_num(txq);
79f33912
NA		 425 if (entries_free < MAX_SKB_FRAGS + 1) {
426 dev_kfree_skb_any(skb);
427 if (net_ratelimit())
428 netdev_err(ndev, "NOT enough BD for SG!\n");
429 return NETDEV_TX_OK;
430 }
431
4c09eed9
JB		 432 /* Protocol checksum off-load for TCP and UDP. */
433 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 434 dev_kfree_skb_any(skb);
4c09eed9
JB		 435 return NETDEV_TX_OK;
436 }
437
6e909283 438 /* Fill in a Tx ring entry */
7355f276 439 bdp = txq->bd.cur;
c4bc44c6 440 last_bdp = bdp;
5cfa3039 441 status = fec16_to_cpu(bdp->cbd_sc);
0e702ab3 442 status &= ~BD_ENET_TX_STATS;
1da177e4 443
22f6b860 444 /* Set buffer length and buffer pointer */
9555b31e 445 bufaddr = skb->data;
6e909283 446 buflen = skb_headlen(skb);
1da177e4 447
7355f276 448 index = fec_enet_get_bd_index(bdp, &txq->bd);
41ef84ce 449 if (((unsigned long) bufaddr) & fep->tx_align ||
6b7e4008 450 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 451 memcpy(txq->tx_bounce[index], skb->data, buflen);
452 bufaddr = txq->tx_bounce[index];
1da177e4 453
6b7e4008 454 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
6e909283
NA		 455 swap_buffer(bufaddr, buflen);
456 }
6aa20a22 457
d6bf3143
RK		 458 /* Push the data cache so the CPM does not get stale memory data. */
459 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
460 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 461 dev_kfree_skb_any(skb);
462 if (net_ratelimit())
463 netdev_err(ndev, "Tx DMA memory map failed\n");
464 return NETDEV_TX_OK;
465 }
1da177e4 466
6e909283 467 if (nr_frags) {
c4bc44c6 468 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
fc75ba51
TK		 469 if (IS_ERR(last_bdp)) {
470 dma_unmap_single(&fep->pdev->dev, addr,
471 buflen, DMA_TO_DEVICE);
472 dev_kfree_skb_any(skb);
c4bc44c6 473 return NETDEV_TX_OK;
fc75ba51 474 }
6e909283
NA		 475 } else {
476 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
477 if (fep->bufdesc_ex) {
478 estatus = BD_ENET_TX_INT;
479 if (unlikely(skb_shinfo(skb)->tx_flags &
480 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
481 estatus |= BD_ENET_TX_TS;
482 }
483 }
fc75ba51
TK		 484 bdp->cbd_bufaddr = cpu_to_fec32(addr);
485 bdp->cbd_datlen = cpu_to_fec16(buflen);
6e909283 486
ff43da86
FL		 487 if (fep->bufdesc_ex) {
488
489 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 490
ff43da86 491 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 492 fep->hwts_tx_en))
6605b730 493 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 494
6b7e4008 495 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 496 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
befe8213 497
6e909283
NA		 498 if (skb->ip_summed == CHECKSUM_PARTIAL)
499 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
500
501 ebdp->cbd_bdu = 0;
5cfa3039 502 ebdp->cbd_esc = cpu_to_fec32(estatus);
6605b730 503 }
03191656 504
7355f276 505 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
6e909283 506 /* Save skb pointer */
4d494cdc 507 txq->tx_skbuff[index] = skb;
6e909283 508
be293467
TK		 509 /* Make sure the updates to rest of the descriptor are performed before
510 * transferring ownership.
511 */
512 wmb();
6e909283 513
fb8ef788
DFB		 514 /* Send it on its way. Tell FEC it's ready, interrupt when done,
515 * it's the last BD of the frame, and to put the CRC on the end.
516 */
6e909283 517 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
5cfa3039 518 bdp->cbd_sc = cpu_to_fec16(status);
fb8ef788 519
22f6b860 520 /* If this was the last BD in the ring, start at the beginning again. */
7355f276 521 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
1da177e4 522
7a2a8451
ED		 523 skb_tx_timestamp(skb);
524
c4bc44c6 525 /* Make sure the update to bdp and tx_skbuff are performed before
7355f276 526 * txq->bd.cur.
c4bc44c6
KH		 527 */
528 wmb();
7355f276 529 txq->bd.cur = bdp;
de5fb0a0 530
de5fb0a0 531 /* Trigger transmission start */
53bb20d1 532 writel(0, txq->bd.reg_desc_active);
1da177e4 533
6e909283 534 return 0;
1da177e4
LT		 535}
536
79f33912 537static int
4d494cdc
FD		 538fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
539 struct net_device *ndev,
540 struct bufdesc *bdp, int index, char *data,
541 int size, bool last_tcp, bool is_last)
61a4427b
NA		 542{
543 struct fec_enet_private *fep = netdev_priv(ndev);
61cd2ebb 544 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 545 unsigned short status;
546 unsigned int estatus = 0;
d6bf3143 547 dma_addr_t addr;
61a4427b 548
5cfa3039 549 status = fec16_to_cpu(bdp->cbd_sc);
79f33912 550 status &= ~BD_ENET_TX_STATS;
61a4427b 551
79f33912 552 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912 553
41ef84ce 554 if (((unsigned long) data) & fep->tx_align ||
6b7e4008 555 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 556 memcpy(txq->tx_bounce[index], data, size);
557 data = txq->tx_bounce[index];
79f33912 558
6b7e4008 559 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 560 swap_buffer(data, size);
561 }
562
d6bf3143
RK		 563 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
564 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 565 dev_kfree_skb_any(skb);
6e909283 566 if (net_ratelimit())
79f33912 567 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 568 return NETDEV_TX_BUSY;
569 }
570
5cfa3039
JB		 571 bdp->cbd_datlen = cpu_to_fec16(size);
572 bdp->cbd_bufaddr = cpu_to_fec32(addr);
d6bf3143 573
79f33912 574 if (fep->bufdesc_ex) {
6b7e4008 575 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 576 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 577 if (skb->ip_summed == CHECKSUM_PARTIAL)
578 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
579 ebdp->cbd_bdu = 0;
5cfa3039 580 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 581 }
582
583 /* Handle the last BD specially */
584 if (last_tcp)
585 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
586 if (is_last) {
587 status |= BD_ENET_TX_INTR;
588 if (fep->bufdesc_ex)
5cfa3039 589 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
79f33912
NA		 590 }
591
5cfa3039 592 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 593
594 return 0;
595}
596
597static int
4d494cdc
FD		 598fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
599 struct sk_buff *skb, struct net_device *ndev,
600 struct bufdesc *bdp, int index)
79f33912
NA		 601{
602 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912 603 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
61cd2ebb 604 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
79f33912
NA		 605 void *bufaddr;
606 unsigned long dmabuf;
607 unsigned short status;
608 unsigned int estatus = 0;
609
5cfa3039 610 status = fec16_to_cpu(bdp->cbd_sc);
79f33912
NA		 611 status &= ~BD_ENET_TX_STATS;
612 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
613
4d494cdc
FD		 614 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
615 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
41ef84ce 616 if (((unsigned long)bufaddr) & fep->tx_align ||
6b7e4008 617 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
4d494cdc
FD		 618 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
619 bufaddr = txq->tx_bounce[index];
79f33912 620
6b7e4008 621 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
79f33912
NA		 622 swap_buffer(bufaddr, hdr_len);
623
624 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
625 hdr_len, DMA_TO_DEVICE);
626 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
627 dev_kfree_skb_any(skb);
628 if (net_ratelimit())
629 netdev_err(ndev, "Tx DMA memory map failed\n");
630 return NETDEV_TX_BUSY;
631 }
632 }
633
5cfa3039
JB		 634 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
635 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
79f33912
NA		 636
637 if (fep->bufdesc_ex) {
6b7e4008 638 if (fep->quirks & FEC_QUIRK_HAS_AVB)
53bb20d1 639 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
79f33912
NA		 640 if (skb->ip_summed == CHECKSUM_PARTIAL)
641 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
642 ebdp->cbd_bdu = 0;
5cfa3039 643 ebdp->cbd_esc = cpu_to_fec32(estatus);
79f33912
NA		 644 }
645
5cfa3039 646 bdp->cbd_sc = cpu_to_fec16(status);
79f33912
NA		 647
648 return 0;
649}
650
4d494cdc
FD		 651static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
652 struct sk_buff *skb,
653 struct net_device *ndev)
79f33912
NA		 654{
655 struct fec_enet_private *fep = netdev_priv(ndev);
656 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
657 int total_len, data_left;
7355f276 658 struct bufdesc *bdp = txq->bd.cur;
79f33912
NA		 659 struct tso_t tso;
660 unsigned int index = 0;
661 int ret;
662
7355f276 663 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
79f33912
NA		 664 dev_kfree_skb_any(skb);
665 if (net_ratelimit())
666 netdev_err(ndev, "NOT enough BD for TSO!\n");
667 return NETDEV_TX_OK;
668 }
669
670 /* Protocol checksum off-load for TCP and UDP. */
671 if (fec_enet_clear_csum(skb, ndev)) {
672 dev_kfree_skb_any(skb);
673 return NETDEV_TX_OK;
674 }
675
676 /* Initialize the TSO handler, and prepare the first payload */
677 tso_start(skb, &tso);
678
679 total_len = skb->len - hdr_len;
680 while (total_len > 0) {
681 char *hdr;
682
7355f276 683 index = fec_enet_get_bd_index(bdp, &txq->bd);
79f33912
NA		 684 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
685 total_len -= data_left;
686
687 /* prepare packet headers: MAC + IP + TCP */
4d494cdc 688 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
79f33912 689 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
4d494cdc 690 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
79f33912
NA		 691 if (ret)
692 goto err_release;
693
694 while (data_left > 0) {
695 int size;
696
697 size = min_t(int, tso.size, data_left);
7355f276
TK		 698 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
699 index = fec_enet_get_bd_index(bdp, &txq->bd);
4d494cdc
FD		 700 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
701 bdp, index,
702 tso.data, size,
703 size == data_left,
79f33912
NA		 704 total_len == 0);
705 if (ret)
706 goto err_release;
707
708 data_left -= size;
709 tso_build_data(skb, &tso, size);
710 }
711
7355f276 712 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
79f33912
NA		 713 }
714
715 /* Save skb pointer */
4d494cdc 716 txq->tx_skbuff[index] = skb;
79f33912 717
79f33912 718 skb_tx_timestamp(skb);
7355f276 719 txq->bd.cur = bdp;
79f33912
NA		 720
721 /* Trigger transmission start */
6b7e4008 722 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
53bb20d1
TK		 723 !readl(txq->bd.reg_desc_active) ||
724 !readl(txq->bd.reg_desc_active) ||
725 !readl(txq->bd.reg_desc_active) ||
726 !readl(txq->bd.reg_desc_active))
727 writel(0, txq->bd.reg_desc_active);
79f33912
NA		 728
729 return 0;
730
731err_release:
732 /* TODO: Release all used data descriptors for TSO */
733 return ret;
734}
735
736static netdev_tx_t
737fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
738{
739 struct fec_enet_private *fep = netdev_priv(ndev);
740 int entries_free;
4d494cdc
FD		 741 unsigned short queue;
742 struct fec_enet_priv_tx_q *txq;
743 struct netdev_queue *nq;
79f33912
NA		 744 int ret;
745
4d494cdc
FD		 746 queue = skb_get_queue_mapping(skb);
747 txq = fep->tx_queue[queue];
748 nq = netdev_get_tx_queue(ndev, queue);
749
79f33912 750 if (skb_is_gso(skb))
4d494cdc 751 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
79f33912 752 else
4d494cdc 753 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
6e909283
NA		 754 if (ret)
755 return ret;
61a4427b 756
7355f276 757 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 758 if (entries_free <= txq->tx_stop_threshold)
759 netif_tx_stop_queue(nq);
61a4427b
NA		 760
761 return NETDEV_TX_OK;
762}
763
14109a59
FL		 764/* Init RX & TX buffer descriptors
765 */
766static void fec_enet_bd_init(struct net_device *dev)
767{
768 struct fec_enet_private *fep = netdev_priv(dev);
4d494cdc
FD		 769 struct fec_enet_priv_tx_q *txq;
770 struct fec_enet_priv_rx_q *rxq;
14109a59
FL		 771 struct bufdesc *bdp;
772 unsigned int i;
59d0f746 773 unsigned int q;
14109a59 774
59d0f746
FL		 775 for (q = 0; q < fep->num_rx_queues; q++) {
776 /* Initialize the receive buffer descriptors. */
777 rxq = fep->rx_queue[q];
7355f276 778 bdp = rxq->bd.base;
4d494cdc 779
7355f276 780 for (i = 0; i < rxq->bd.ring_size; i++) {
14109a59 781
59d0f746
FL		 782 /* Initialize the BD for every fragment in the page. */
783 if (bdp->cbd_bufaddr)
5cfa3039 784 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
59d0f746 785 else
5cfa3039 786 bdp->cbd_sc = cpu_to_fec16(0);
7355f276 787 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 788 }
789
790 /* Set the last buffer to wrap */
7355f276 791 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 792 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 793
7355f276 794 rxq->bd.cur = rxq->bd.base;
59d0f746
FL		 795 }
796
797 for (q = 0; q < fep->num_tx_queues; q++) {
798 /* ...and the same for transmit */
799 txq = fep->tx_queue[q];
7355f276
TK		 800 bdp = txq->bd.base;
801 txq->bd.cur = bdp;
59d0f746 802
7355f276 803 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746 804 /* Initialize the BD for every fragment in the page. */
5cfa3039 805 bdp->cbd_sc = cpu_to_fec16(0);
59d0f746
FL		 806 if (txq->tx_skbuff[i]) {
807 dev_kfree_skb_any(txq->tx_skbuff[i]);
808 txq->tx_skbuff[i] = NULL;
809 }
5cfa3039 810 bdp->cbd_bufaddr = cpu_to_fec32(0);
7355f276 811 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
59d0f746
FL		 812 }
813
814 /* Set the last buffer to wrap */
7355f276 815 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 816 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 817 txq->dirty_tx = bdp;
14109a59 818 }
59d0f746 819}
14109a59 820
ce99d0d3
FL		 821static void fec_enet_active_rxring(struct net_device *ndev)
822{
823 struct fec_enet_private *fep = netdev_priv(ndev);
824 int i;
825
826 for (i = 0; i < fep->num_rx_queues; i++)
53bb20d1 827 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
ce99d0d3
FL		 828}
829
59d0f746
FL		 830static void fec_enet_enable_ring(struct net_device *ndev)
831{
832 struct fec_enet_private *fep = netdev_priv(ndev);
833 struct fec_enet_priv_tx_q *txq;
834 struct fec_enet_priv_rx_q *rxq;
835 int i;
14109a59 836
59d0f746
FL		 837 for (i = 0; i < fep->num_rx_queues; i++) {
838 rxq = fep->rx_queue[i];
7355f276 839 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
d543a762 840 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
14109a59 841
59d0f746
FL		 842 /* enable DMA1/2 */
843 if (i)
844 writel(RCMR_MATCHEN | RCMR_CMP(i),
845 fep->hwp + FEC_RCMR(i));
846 }
14109a59 847
59d0f746
FL		 848 for (i = 0; i < fep->num_tx_queues; i++) {
849 txq = fep->tx_queue[i];
7355f276 850 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
59d0f746
FL		 851
852 /* enable DMA1/2 */
853 if (i)
854 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
855 fep->hwp + FEC_DMA_CFG(i));
14109a59 856 }
59d0f746 857}
14109a59 858
59d0f746
FL		 859static void fec_enet_reset_skb(struct net_device *ndev)
860{
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 int i, j;
864
865 for (i = 0; i < fep->num_tx_queues; i++) {
866 txq = fep->tx_queue[i];
867
7355f276 868 for (j = 0; j < txq->bd.ring_size; j++) {
59d0f746
FL		 869 if (txq->tx_skbuff[j]) {
870 dev_kfree_skb_any(txq->tx_skbuff[j]);
871 txq->tx_skbuff[j] = NULL;
872 }
873 }
874 }
14109a59
FL		 875}
876
dbc64a8e
RK		 877/*
878 * This function is called to start or restart the FEC during a link
879 * change, transmit timeout, or to reconfigure the FEC. The network
880 * packet processing for this device must be stopped before this call.
45993653 881 */
1da177e4 882static void
ef83337d 883fec_restart(struct net_device *ndev)
1da177e4 884{
c556167f 885 struct fec_enet_private *fep = netdev_priv(ndev);
4c09eed9 886 u32 val;
cd1f402c
UKK		 887 u32 temp_mac[2];
888 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 889 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 890
106c314c
FD		 891 /* Whack a reset. We should wait for this.
892 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
893 * instead of reset MAC itself.
894 */
6b7e4008 895 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
106c314c
FD		 896 writel(0, fep->hwp + FEC_ECNTRL);
897 } else {
898 writel(1, fep->hwp + FEC_ECNTRL);
899 udelay(10);
900 }
1da177e4 901
45993653
UKK		 902 /*
903 * enet-mac reset will reset mac address registers too,
904 * so need to reconfigure it.
905 */
6b7e4008 906 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
45993653 907 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
5cfa3039
JB		 908 writel((__force u32)cpu_to_be32(temp_mac[0]),
909 fep->hwp + FEC_ADDR_LOW);
910 writel((__force u32)cpu_to_be32(temp_mac[1]),
911 fep->hwp + FEC_ADDR_HIGH);
45993653 912 }
1da177e4 913
45993653 914 /* Clear any outstanding interrupt. */
e17f7fec 915 writel(0xffffffff, fep->hwp + FEC_IEVENT);
1da177e4 916
14109a59
FL		 917 fec_enet_bd_init(ndev);
918
59d0f746 919 fec_enet_enable_ring(ndev);
45993653 920
59d0f746
FL		 921 /* Reset tx SKB buffers. */
922 fec_enet_reset_skb(ndev);
97b72e43 923
45993653 924 /* Enable MII mode */
ef83337d 925 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 926 /* FD enable */
45993653
UKK		 927 writel(0x04, fep->hwp + FEC_X_CNTRL);
928 } else {
cd1f402c
UKK		 929 /* No Rcv on Xmit */
930 rcntl |= 0x02;
45993653
UKK		 931 writel(0x0, fep->hwp + FEC_X_CNTRL);
932 }
cd1f402c 933
45993653
UKK		 934 /* Set MII speed */
935 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
936
d1391930 937#if !defined(CONFIG_M5272)
18803495
GU		 938 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
939 /* set RX checksum */
940 val = readl(fep->hwp + FEC_RACC);
941 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
942 val |= FEC_RACC_OPTIONS;
943 else
944 val &= ~FEC_RACC_OPTIONS;
945 writel(val, fep->hwp + FEC_RACC);
32867fcc 946 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
18803495 947 }
d1391930 948#endif
4c09eed9 949
45993653
UKK		 950 /*
951 * The phy interface and speed need to get configured
952 * differently on enet-mac.
953 */
6b7e4008 954 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 955 /* Enable flow control and length check */
956 rcntl |= 0x40000000 | 0x00000020;
45993653 957
230dec61 958 /* RGMII, RMII or MII */
e813bb2b
MP		 959 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
960 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
961 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
962 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
230dec61
SG		 963 rcntl |= (1 << 6);
964 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 965 rcntl |= (1 << 8);
45993653 966 else
cd1f402c 967 rcntl &= ~(1 << 8);
45993653 968
230dec61 969 /* 1G, 100M or 10M */
45f5c327
PR		 970 if (ndev->phydev) {
971 if (ndev->phydev->speed == SPEED_1000)
230dec61 972 ecntl |= (1 << 5);
45f5c327 973 else if (ndev->phydev->speed == SPEED_100)
230dec61
SG		 974 rcntl &= ~(1 << 9);
975 else
976 rcntl |= (1 << 9);
977 }
45993653
UKK		 978 } else {
979#ifdef FEC_MIIGSK_ENR
6b7e4008 980 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
8d82f219 981 u32 cfgr;
45993653
UKK		 982 /* disable the gasket and wait */
983 writel(0, fep->hwp + FEC_MIIGSK_ENR);
984 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
985 udelay(1);
986
987 /*
988 * configure the gasket:
989 * RMII, 50 MHz, no loopback, no echo
0ca1e290 990 * MII, 25 MHz, no loopback, no echo
45993653 991 */
8d82f219
EB		 992 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
993 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
45f5c327 994 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
8d82f219
EB		 995 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
996 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 997
998 /* re-enable the gasket */
999 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 1000 }
45993653
UKK		 1001#endif
1002 }
baa70a5c 1003
d1391930 1004#if !defined(CONFIG_M5272)
baa70a5c
FL		 1005 /* enable pause frame*/
1006 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1007 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
45f5c327 1008 ndev->phydev && ndev->phydev->pause)) {
baa70a5c
FL		 1009 rcntl |= FEC_ENET_FCE;
1010
4c09eed9 1011 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 1012 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1013 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1014 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1015 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1016
1017 /* OPD */
1018 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1019 } else {
1020 rcntl &= ~FEC_ENET_FCE;
1021 }
d1391930 1022#endif /* !defined(CONFIG_M5272) */
baa70a5c 1023
cd1f402c 1024 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 1025
84fe6182
SW		 1026 /* Setup multicast filter. */
1027 set_multicast_list(ndev);
1028#ifndef CONFIG_M5272
1029 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1030 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1031#endif
1032
6b7e4008 1033 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
230dec61
SG		 1034 /* enable ENET endian swap */
1035 ecntl |= (1 << 8);
1036 /* enable ENET store and forward mode */
1037 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1038 }
1039
ff43da86
FL		 1040 if (fep->bufdesc_ex)
1041 ecntl |= (1 << 4);
6605b730 1042
38ae92dc 1043#ifndef CONFIG_M5272
b9eef55c
JB		 1044 /* Enable the MIB statistic event counters */
1045 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 1046#endif
1047
45993653 1048 /* And last, enable the transmit and receive processing */
230dec61 1049 writel(ecntl, fep->hwp + FEC_ECNTRL);
ce99d0d3 1050 fec_enet_active_rxring(ndev);
45993653 1051
ff43da86
FL		 1052 if (fep->bufdesc_ex)
1053 fec_ptp_start_cyclecounter(ndev);
1054
45993653 1055 /* Enable interrupts we wish to service */
0c5a3aef
NA		 1056 if (fep->link)
1057 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1058 else
1059 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
d851b47b
FD		 1060
1061 /* Init the interrupt coalescing */
1062 fec_enet_itr_coal_init(ndev);
1063
45993653
UKK		 1064}
1065
1066static void
1067fec_stop(struct net_device *ndev)
1068{
1069 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 1070 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
42431dc2 1071 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
de40ed31 1072 u32 val;
45993653
UKK		 1073
1074 /* We cannot expect a graceful transmit stop without link !!! */
1075 if (fep->link) {
1076 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1077 udelay(10);
1078 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 1079 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1080 }
1081
106c314c
FD		 1082 /* Whack a reset. We should wait for this.
1083 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1084 * instead of reset MAC itself.
1085 */
de40ed31
NA		 1086 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1087 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1088 writel(0, fep->hwp + FEC_ECNTRL);
1089 } else {
1090 writel(1, fep->hwp + FEC_ECNTRL);
1091 udelay(10);
1092 }
1093 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
106c314c 1094 } else {
de40ed31
NA		 1095 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1096 val = readl(fep->hwp + FEC_ECNTRL);
1097 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1098 writel(val, fep->hwp + FEC_ECNTRL);
1099
1100 if (pdata && pdata->sleep_mode_enable)
1101 pdata->sleep_mode_enable(true);
106c314c 1102 }
45993653 1103 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
230dec61
SG		 1104
1105 /* We have to keep ENET enabled to have MII interrupt stay working */
de40ed31
NA		 1106 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1107 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
230dec61 1108 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1109 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1110 }
1da177e4
LT		 1111}
1112
1113
45993653
UKK		 1114static void
1115fec_timeout(struct net_device *ndev)
1116{
1117 struct fec_enet_private *fep = netdev_priv(ndev);
1118
344756f6
RK		 1119 fec_dump(ndev);
1120
45993653
UKK		 1121 ndev->stats.tx_errors++;
1122
36cdc743 1123 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1124}
1125
36cdc743 1126static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1127{
1128 struct fec_enet_private *fep =
36cdc743 1129 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1130 struct net_device *ndev = fep->netdev;
54309fa6 1131
36cdc743
RK		 1132 rtnl_lock();
1133 if (netif_device_present(ndev) || netif_running(ndev)) {
1134 napi_disable(&fep->napi);
1135 netif_tx_lock_bh(ndev);
1136 fec_restart(ndev);
1137 netif_wake_queue(ndev);
1138 netif_tx_unlock_bh(ndev);
1139 napi_enable(&fep->napi);
54309fa6 1140 }
36cdc743 1141 rtnl_unlock();
45993653
UKK		 1142}
1143
bfd4ecdd
RK		 1144static void
1145fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1146 struct skb_shared_hwtstamps *hwtstamps)
1147{
1148 unsigned long flags;
1149 u64 ns;
1150
1151 spin_lock_irqsave(&fep->tmreg_lock, flags);
1152 ns = timecounter_cyc2time(&fep->tc, ts);
1153 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1154
1155 memset(hwtstamps, 0, sizeof(*hwtstamps));
1156 hwtstamps->hwtstamp = ns_to_ktime(ns);
1157}
1158
1da177e4 1159static void
4d494cdc 1160fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1da177e4
LT		 1161{
1162 struct fec_enet_private *fep;
a2fe37b6 1163 struct bufdesc *bdp;
0e702ab3 1164 unsigned short status;
1da177e4 1165 struct sk_buff *skb;
4d494cdc
FD		 1166 struct fec_enet_priv_tx_q *txq;
1167 struct netdev_queue *nq;
de5fb0a0 1168 int index = 0;
79f33912 1169 int entries_free;
1da177e4 1170
c556167f 1171 fep = netdev_priv(ndev);
4d494cdc
FD		 1172
1173 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1174
1175 txq = fep->tx_queue[queue_id];
1176 /* get next bdp of dirty_tx */
1177 nq = netdev_get_tx_queue(ndev, queue_id);
1178 bdp = txq->dirty_tx;
1da177e4 1179
de5fb0a0 1180 /* get next bdp of dirty_tx */
7355f276 1181 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
de5fb0a0 1182
7355f276
TK		 1183 while (bdp != READ_ONCE(txq->bd.cur)) {
1184 /* Order the load of bd.cur and cbd_sc */
c4bc44c6 1185 rmb();
5cfa3039 1186 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
c4bc44c6 1187 if (status & BD_ENET_TX_READY)
f0b3fbea
SH		 1188 break;
1189
7355f276 1190 index = fec_enet_get_bd_index(bdp, &txq->bd);
2b995f63 1191
a2fe37b6 1192 skb = txq->tx_skbuff[index];
2b995f63 1193 txq->tx_skbuff[index] = NULL;
5cfa3039
JB		 1194 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1195 dma_unmap_single(&fep->pdev->dev,
1196 fec32_to_cpu(bdp->cbd_bufaddr),
1197 fec16_to_cpu(bdp->cbd_datlen),
1198 DMA_TO_DEVICE);
1199 bdp->cbd_bufaddr = cpu_to_fec32(0);
7fafe803
TK		 1200 if (!skb)
1201 goto skb_done;
de5fb0a0 1202
1da177e4 1203 /* Check for errors. */
0e702ab3 1204 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1205 BD_ENET_TX_RL | BD_ENET_TX_UN |
1206 BD_ENET_TX_CSL)) {
c556167f 1207 ndev->stats.tx_errors++;
0e702ab3 1208 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1209 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1210 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1211 ndev->stats.tx_window_errors++;
0e702ab3 1212 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1213 ndev->stats.tx_aborted_errors++;
0e702ab3 1214 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1215 ndev->stats.tx_fifo_errors++;
0e702ab3 1216 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1217 ndev->stats.tx_carrier_errors++;
1da177e4 1218 } else {
c556167f 1219 ndev->stats.tx_packets++;
6e909283 1220 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1221 }
1222
ff43da86
FL		 1223 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1224 fep->bufdesc_ex) {
6605b730 1225 struct skb_shared_hwtstamps shhwtstamps;
ff43da86 1226 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730 1227
5cfa3039 1228 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
6605b730
FL		 1229 skb_tstamp_tx(skb, &shhwtstamps);
1230 }
ff43da86 1231
1da177e4
LT		 1232 /* Deferred means some collisions occurred during transmit,
1233 * but we eventually sent the packet OK.
1234 */
0e702ab3 1235 if (status & BD_ENET_TX_DEF)
c556167f 1236 ndev->stats.collisions++;
6aa20a22 1237
22f6b860 1238 /* Free the sk buffer associated with this last transmit */
1da177e4 1239 dev_kfree_skb_any(skb);
7fafe803 1240skb_done:
c4bc44c6
KH		 1241 /* Make sure the update to bdp and tx_skbuff are performed
1242 * before dirty_tx
1243 */
1244 wmb();
4d494cdc 1245 txq->dirty_tx = bdp;
6aa20a22 1246
22f6b860 1247 /* Update pointer to next buffer descriptor to be transmitted */
7355f276 1248 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
6aa20a22 1249
22f6b860 1250 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1251 */
79f33912 1252 if (netif_queue_stopped(ndev)) {
7355f276 1253 entries_free = fec_enet_get_free_txdesc_num(txq);
4d494cdc
FD		 1254 if (entries_free >= txq->tx_wake_threshold)
1255 netif_tx_wake_queue(nq);
79f33912 1256 }
1da177e4 1257 }
ccea2968
RK		 1258
1259 /* ERR006538: Keep the transmitter going */
7355f276 1260 if (bdp != txq->bd.cur &&
53bb20d1
TK		 1261 readl(txq->bd.reg_desc_active) == 0)
1262 writel(0, txq->bd.reg_desc_active);
4d494cdc
FD		 1263}
1264
1265static void
1266fec_enet_tx(struct net_device *ndev)
1267{
1268 struct fec_enet_private *fep = netdev_priv(ndev);
1269 u16 queue_id;
1270 /* First process class A queue, then Class B and Best Effort queue */
1271 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1272 clear_bit(queue_id, &fep->work_tx);
1273 fec_enet_tx_queue(ndev, queue_id);
1274 }
1275 return;
1da177e4
LT		 1276}
1277
1b7bde6d
NA		 1278static int
1279fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1280{
1281 struct fec_enet_private *fep = netdev_priv(ndev);
1282 int off;
1283
1284 off = ((unsigned long)skb->data) & fep->rx_align;
1285 if (off)
1286 skb_reserve(skb, fep->rx_align + 1 - off);
1287
5cfa3039
JB		 1288 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1289 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1b7bde6d
NA		 1290 if (net_ratelimit())
1291 netdev_err(ndev, "Rx DMA memory map failed\n");
1292 return -ENOMEM;
1293 }
1294
1295 return 0;
1296}
1297
1298static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1310b544 1299 struct bufdesc *bdp, u32 length, bool swap)
1b7bde6d
NA		 1300{
1301 struct fec_enet_private *fep = netdev_priv(ndev);
1302 struct sk_buff *new_skb;
1303
1304 if (length > fep->rx_copybreak)
1305 return false;
1306
1307 new_skb = netdev_alloc_skb(ndev, length);
1308 if (!new_skb)
1309 return false;
1310
5cfa3039
JB		 1311 dma_sync_single_for_cpu(&fep->pdev->dev,
1312 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1313 FEC_ENET_RX_FRSIZE - fep->rx_align,
1314 DMA_FROM_DEVICE);
1310b544
LW		 1315 if (!swap)
1316 memcpy(new_skb->data, (*skb)->data, length);
1317 else
1318 swap_buffer2(new_skb->data, (*skb)->data, length);
1b7bde6d
NA		 1319 *skb = new_skb;
1320
1321 return true;
1322}
1323
7355f276 1324/* During a receive, the bd_rx.cur points to the current incoming buffer.
1da177e4
LT		 1325 * When we update through the ring, if the next incoming buffer has
1326 * not been given to the system, we just set the empty indicator,
1327 * effectively tossing the packet.
1328 */
dc975382 1329static int
4d494cdc 1330fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1da177e4 1331{
c556167f 1332 struct fec_enet_private *fep = netdev_priv(ndev);
4d494cdc 1333 struct fec_enet_priv_rx_q *rxq;
2e28532f 1334 struct bufdesc *bdp;
0e702ab3 1335 unsigned short status;
1b7bde6d
NA		 1336 struct sk_buff *skb_new = NULL;
1337 struct sk_buff *skb;
1da177e4
LT		 1338 ushort pkt_len;
1339 __u8 *data;
dc975382 1340 int pkt_received = 0;
cdffcf1b
JB		 1341 struct bufdesc_ex *ebdp = NULL;
1342 bool vlan_packet_rcvd = false;
1343 u16 vlan_tag;
d842a31f 1344 int index = 0;
1b7bde6d 1345 bool is_copybreak;
6b7e4008 1346 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
6aa20a22 1347
0e702ab3
GU		 1348#ifdef CONFIG_M532x
1349 flush_cache_all();
6aa20a22 1350#endif
4d494cdc
FD		 1351 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1352 rxq = fep->rx_queue[queue_id];
1da177e4 1353
1da177e4
LT		 1354 /* First, grab all of the stats for the incoming packet.
1355 * These get messed up if we get called due to a busy condition.
1356 */
7355f276 1357 bdp = rxq->bd.cur;
1da177e4 1358
5cfa3039 1359 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1da177e4 1360
dc975382
FL		 1361 if (pkt_received >= budget)
1362 break;
1363 pkt_received++;
1364
ed63f1dc 1365 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
db3421c1 1366
22f6b860 1367 /* Check for errors. */
095098e1 1368 status ^= BD_ENET_RX_LAST;
22f6b860 1369 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
095098e1
TK		 1370 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1371 BD_ENET_RX_CL)) {
c556167f 1372 ndev->stats.rx_errors++;
095098e1
TK		 1373 if (status & BD_ENET_RX_OV) {
1374 /* FIFO overrun */
1375 ndev->stats.rx_fifo_errors++;
1376 goto rx_processing_done;
1377 }
1378 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1379 | BD_ENET_RX_LAST)) {
22f6b860 1380 /* Frame too long or too short. */
c556167f 1381 ndev->stats.rx_length_errors++;
095098e1
TK		 1382 if (status & BD_ENET_RX_LAST)
1383 netdev_err(ndev, "rcv is not +last\n");
22f6b860 1384 }
22f6b860 1385 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1386 ndev->stats.rx_crc_errors++;
095098e1
TK		 1387 /* Report late collisions as a frame error. */
1388 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1389 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1390 goto rx_processing_done;
1391 }
1da177e4 1392
22f6b860 1393 /* Process the incoming frame. */
c556167f 1394 ndev->stats.rx_packets++;
5cfa3039 1395 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
c556167f 1396 ndev->stats.rx_bytes += pkt_len;
1da177e4 1397
7355f276 1398 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1b7bde6d 1399 skb = rxq->rx_skbuff[index];
ccdc4f19 1400
1b7bde6d
NA		 1401 /* The packet length includes FCS, but we don't want to
1402 * include that when passing upstream as it messes up
1403 * bridging applications.
1404 */
1310b544
LW		 1405 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1406 need_swap);
1b7bde6d
NA		 1407 if (!is_copybreak) {
1408 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1409 if (unlikely(!skb_new)) {
1410 ndev->stats.rx_dropped++;
1411 goto rx_processing_done;
1412 }
5cfa3039
JB		 1413 dma_unmap_single(&fep->pdev->dev,
1414 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1415 FEC_ENET_RX_FRSIZE - fep->rx_align,
1416 DMA_FROM_DEVICE);
1417 }
1418
1419 prefetch(skb->data - NET_IP_ALIGN);
1420 skb_put(skb, pkt_len - 4);
1421 data = skb->data;
1310b544 1422 if (!is_copybreak && need_swap)
b5680e0b
SG		 1423 swap_buffer(data, pkt_len);
1424
cdffcf1b
JB		 1425 /* Extract the enhanced buffer descriptor */
1426 ebdp = NULL;
1427 if (fep->bufdesc_ex)
1428 ebdp = (struct bufdesc_ex *)bdp;
1429
1430 /* If this is a VLAN packet remove the VLAN Tag */
1431 vlan_packet_rcvd = false;
1432 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
5cfa3039
JB		 1433 fep->bufdesc_ex &&
1434 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
cdffcf1b
JB		 1435 /* Push and remove the vlan tag */
1436 struct vlan_hdr *vlan_header =
1437 (struct vlan_hdr *) (data + ETH_HLEN);
1438 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
cdffcf1b
JB		 1439
1440 vlan_packet_rcvd = true;
1b7bde6d 1441
af5cbc98 1442 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1b7bde6d 1443 skb_pull(skb, VLAN_HLEN);
cdffcf1b
JB		 1444 }
1445
1b7bde6d 1446 skb->protocol = eth_type_trans(skb, ndev);
1da177e4 1447
1b7bde6d
NA		 1448 /* Get receive timestamp from the skb */
1449 if (fep->hwts_rx_en && fep->bufdesc_ex)
5cfa3039 1450 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1b7bde6d
NA		 1451 skb_hwtstamps(skb));
1452
1453 if (fep->bufdesc_ex &&
1454 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
5cfa3039 1455 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1b7bde6d
NA		 1456 /* don't check it */
1457 skb->ip_summed = CHECKSUM_UNNECESSARY;
1458 } else {
1459 skb_checksum_none_assert(skb);
4c09eed9 1460 }
1b7bde6d 1461 }
4c09eed9 1462
1b7bde6d
NA		 1463 /* Handle received VLAN packets */
1464 if (vlan_packet_rcvd)
1465 __vlan_hwaccel_put_tag(skb,
1466 htons(ETH_P_8021Q),
1467 vlan_tag);
cdffcf1b 1468
1b7bde6d
NA		 1469 napi_gro_receive(&fep->napi, skb);
1470
1471 if (is_copybreak) {
5cfa3039
JB		 1472 dma_sync_single_for_device(&fep->pdev->dev,
1473 fec32_to_cpu(bdp->cbd_bufaddr),
1b7bde6d
NA		 1474 FEC_ENET_RX_FRSIZE - fep->rx_align,
1475 DMA_FROM_DEVICE);
1476 } else {
1477 rxq->rx_skbuff[index] = skb_new;
1478 fec_enet_new_rxbdp(ndev, bdp, skb_new);
22f6b860 1479 }
f0b3fbea 1480
22f6b860
SH		 1481rx_processing_done:
1482 /* Clear the status flags for this buffer */
1483 status &= ~BD_ENET_RX_STATS;
1da177e4 1484
22f6b860
SH		 1485 /* Mark the buffer empty */
1486 status |= BD_ENET_RX_EMPTY;
6aa20a22 1487
ff43da86
FL		 1488 if (fep->bufdesc_ex) {
1489 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1490
5cfa3039 1491 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 1492 ebdp->cbd_prot = 0;
1493 ebdp->cbd_bdu = 0;
1494 }
be293467
TK		 1495 /* Make sure the updates to rest of the descriptor are
1496 * performed before transferring ownership.
1497 */
1498 wmb();
1499 bdp->cbd_sc = cpu_to_fec16(status);
6605b730 1500
22f6b860 1501 /* Update BD pointer to next entry */
7355f276 1502 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
36e24e2e 1503
22f6b860
SH		 1504 /* Doing this here will keep the FEC running while we process
1505 * incoming frames. On a heavily loaded network, we should be
1506 * able to keep up at the expense of system resources.
1507 */
53bb20d1 1508 writel(0, rxq->bd.reg_desc_active);
22f6b860 1509 }
7355f276 1510 rxq->bd.cur = bdp;
4d494cdc
FD		 1511 return pkt_received;
1512}
1da177e4 1513
4d494cdc
FD		 1514static int
1515fec_enet_rx(struct net_device *ndev, int budget)
1516{
1517 int pkt_received = 0;
1518 u16 queue_id;
1519 struct fec_enet_private *fep = netdev_priv(ndev);
1520
1521 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1c021bb7
UKK		 1522 int ret;
1523
1524 ret = fec_enet_rx_queue(ndev,
4d494cdc 1525 budget - pkt_received, queue_id);
1c021bb7
UKK		 1526
1527 if (ret < budget - pkt_received)
1528 clear_bit(queue_id, &fep->work_rx);
1529
1530 pkt_received += ret;
4d494cdc 1531 }
dc975382 1532 return pkt_received;
1da177e4
LT		 1533}
1534
4d494cdc
FD		 1535static bool
1536fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1537{
1538 if (int_events == 0)
1539 return false;
1540
1541 if (int_events & FEC_ENET_RXF)
1542 fep->work_rx |= (1 << 2);
ce99d0d3
FL		 1543 if (int_events & FEC_ENET_RXF_1)
1544 fep->work_rx |= (1 << 0);
1545 if (int_events & FEC_ENET_RXF_2)
1546 fep->work_rx |= (1 << 1);
4d494cdc
FD		 1547
1548 if (int_events & FEC_ENET_TXF)
1549 fep->work_tx |= (1 << 2);
ce99d0d3
FL		 1550 if (int_events & FEC_ENET_TXF_1)
1551 fep->work_tx |= (1 << 0);
1552 if (int_events & FEC_ENET_TXF_2)
1553 fep->work_tx |= (1 << 1);
4d494cdc
FD		 1554
1555 return true;
1556}
1557
45993653
UKK		 1558static irqreturn_t
1559fec_enet_interrupt(int irq, void *dev_id)
1560{
1561 struct net_device *ndev = dev_id;
1562 struct fec_enet_private *fep = netdev_priv(ndev);
1563 uint int_events;
1564 irqreturn_t ret = IRQ_NONE;
1565
7a16807c 1566 int_events = readl(fep->hwp + FEC_IEVENT);
94191fd6 1567 writel(int_events, fep->hwp + FEC_IEVENT);
4d494cdc 1568 fec_enet_collect_events(fep, int_events);
45993653 1569
61615cd2 1570 if ((fep->work_tx || fep->work_rx) && fep->link) {
7a16807c 1571 ret = IRQ_HANDLED;
dc975382 1572
94191fd6
NA		 1573 if (napi_schedule_prep(&fep->napi)) {
1574 /* Disable the NAPI interrupts */
80dc6a9f 1575 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
94191fd6
NA		 1576 __napi_schedule(&fep->napi);
1577 }
7a16807c 1578 }
45993653 1579
7a16807c
RK		 1580 if (int_events & FEC_ENET_MII) {
1581 ret = IRQ_HANDLED;
1582 complete(&fep->mdio_done);
1583 }
45993653 1584
81f35ffd
PZ		 1585 if (fep->ptp_clock)
1586 fec_ptp_check_pps_event(fep);
278d2404 1587
45993653
UKK		 1588 return ret;
1589}
1590
dc975382
FL		 1591static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1592{
1593 struct net_device *ndev = napi->dev;
dc975382 1594 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1595 int pkts;
1596
7a16807c 1597 pkts = fec_enet_rx(ndev, budget);
45993653 1598
de5fb0a0
FL		 1599 fec_enet_tx(ndev);
1600
dc975382
FL		 1601 if (pkts < budget) {
1602 napi_complete(napi);
1603 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1604 }
1605 return pkts;
1606}
45993653 1607
e6b043d5 1608/* ------------------------------------------------------------------------- */
0c7768a0 1609static void fec_get_mac(struct net_device *ndev)
1da177e4 1610{
c556167f 1611 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1612 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1613 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1614
49da97dc
SG		 1615 /*
1616 * try to get mac address in following order:
1617 *
1618 * 1) module parameter via kernel command line in form
1619 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1620 */
1621 iap = macaddr;
1622
ca2cc333
SG		 1623 /*
1624 * 2) from device tree data
1625 */
1626 if (!is_valid_ether_addr(iap)) {
1627 struct device_node *np = fep->pdev->dev.of_node;
1628 if (np) {
1629 const char *mac = of_get_mac_address(np);
1630 if (mac)
1631 iap = (unsigned char *) mac;
1632 }
1633 }
ca2cc333 1634
49da97dc 1635 /*
ca2cc333 1636 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1637 */
1638 if (!is_valid_ether_addr(iap)) {
1639#ifdef CONFIG_M5272
1640 if (FEC_FLASHMAC)
1641 iap = (unsigned char *)FEC_FLASHMAC;
1642#else
1643 if (pdata)
589efdc7 1644 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1645#endif
1646 }
1647
1648 /*
ca2cc333 1649 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1650 */
1651 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1652 *((__be32 *) &tmpaddr[0]) =
1653 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1654 *((__be16 *) &tmpaddr[4]) =
1655 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1656 iap = &tmpaddr[0];
1da177e4
LT		 1657 }
1658
ff5b2fab
LS		 1659 /*
1660 * 5) random mac address
1661 */
1662 if (!is_valid_ether_addr(iap)) {
1663 /* Report it and use a random ethernet address instead */
1664 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1665 eth_hw_addr_random(ndev);
1666 netdev_info(ndev, "Using random MAC address: %pM\n",
1667 ndev->dev_addr);
1668 return;
1669 }
1670
c556167f 1671 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1672
49da97dc
SG		 1673 /* Adjust MAC if using macaddr */
1674 if (iap == macaddr)
43af940c 1675 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1676}
1677
e6b043d5 1678/* ------------------------------------------------------------------------- */
1da177e4 1679
e6b043d5
BW		 1680/*
1681 * Phy section
1682 */
c556167f 1683static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1684{
c556167f 1685 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 1686 struct phy_device *phy_dev = ndev->phydev;
e6b043d5 1687 int status_change = 0;
1da177e4 1688
e6b043d5
BW		 1689 /* Prevent a state halted on mii error */
1690 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1691 phy_dev->state = PHY_RESUMING;
54309fa6 1692 return;
e6b043d5 1693 }
1da177e4 1694
8ce5624f
RK		 1695 /*
1696 * If the netdev is down, or is going down, we're not interested
1697 * in link state events, so just mark our idea of the link as down
1698 * and ignore the event.
1699 */
1700 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1701 fep->link = 0;
1702 } else if (phy_dev->link) {
d97e7497 1703 if (!fep->link) {
6ea0722f 1704 fep->link = phy_dev->link;
e6b043d5
BW		 1705 status_change = 1;
1706 }
1da177e4 1707
ef83337d
RK		 1708 if (fep->full_duplex != phy_dev->duplex) {
1709 fep->full_duplex = phy_dev->duplex;
d97e7497 1710 status_change = 1;
ef83337d 1711 }
d97e7497
LS		 1712
1713 if (phy_dev->speed != fep->speed) {
1714 fep->speed = phy_dev->speed;
1715 status_change = 1;
1716 }
1717
1718 /* if any of the above changed restart the FEC */
dbc64a8e 1719 if (status_change) {
dbc64a8e 1720 napi_disable(&fep->napi);
dbc64a8e 1721 netif_tx_lock_bh(ndev);
ef83337d 1722 fec_restart(ndev);
dbc64a8e 1723 netif_wake_queue(ndev);
6af42d42 1724 netif_tx_unlock_bh(ndev);
dbc64a8e 1725 napi_enable(&fep->napi);
dbc64a8e 1726 }
d97e7497
LS		 1727 } else {
1728 if (fep->link) {
f208ce10
RK		 1729 napi_disable(&fep->napi);
1730 netif_tx_lock_bh(ndev);
c556167f 1731 fec_stop(ndev);
f208ce10
RK		 1732 netif_tx_unlock_bh(ndev);
1733 napi_enable(&fep->napi);
8d7ed0f0 1734 fep->link = phy_dev->link;
d97e7497
LS		 1735 status_change = 1;
1736 }
1da177e4 1737 }
6aa20a22 1738
e6b043d5
BW		 1739 if (status_change)
1740 phy_print_status(phy_dev);
1741}
1da177e4 1742
e6b043d5 1743static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1744{
e6b043d5 1745 struct fec_enet_private *fep = bus->priv;
8fff755e 1746 struct device *dev = &fep->pdev->dev;
97b72e43 1747 unsigned long time_left;
8fff755e
AL		 1748 int ret = 0;
1749
1750 ret = pm_runtime_get_sync(dev);
b0c6ce24 1751 if (ret < 0)
8fff755e 1752 return ret;
1da177e4 1753
e6b043d5 1754 fep->mii_timeout = 0;
aac27c7a 1755 reinit_completion(&fep->mdio_done);
e6b043d5
BW		 1756
1757 /* start a read op */
1758 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1759 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1760 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1761
1762 /* wait for end of transfer */
97b72e43
BS		 1763 time_left = wait_for_completion_timeout(&fep->mdio_done,
1764 usecs_to_jiffies(FEC_MII_TIMEOUT));
1765 if (time_left == 0) {
1766 fep->mii_timeout = 1;
31b7720c 1767 netdev_err(fep->netdev, "MDIO read timeout\n");
8fff755e
AL		 1768 ret = -ETIMEDOUT;
1769 goto out;
1da177e4 1770 }
1da177e4 1771
8fff755e
AL		 1772 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1773
1774out:
1775 pm_runtime_mark_last_busy(dev);
1776 pm_runtime_put_autosuspend(dev);
1777
1778 return ret;
7dd6a2aa 1779}
6aa20a22 1780
e6b043d5
BW		 1781static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1782 u16 value)
1da177e4 1783{
e6b043d5 1784 struct fec_enet_private *fep = bus->priv;
8fff755e 1785 struct device *dev = &fep->pdev->dev;
97b72e43 1786 unsigned long time_left;
42ea4457 1787 int ret;
8fff755e
AL		 1788
1789 ret = pm_runtime_get_sync(dev);
b0c6ce24 1790 if (ret < 0)
8fff755e 1791 return ret;
42ea4457
MS		 1792 else
1793 ret = 0;
1da177e4 1794
e6b043d5 1795 fep->mii_timeout = 0;
aac27c7a 1796 reinit_completion(&fep->mdio_done);
1da177e4 1797
862f0982
SG		 1798 /* start a write op */
1799 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1800 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1801 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1802 fep->hwp + FEC_MII_DATA);
1803
1804 /* wait for end of transfer */
97b72e43
BS		 1805 time_left = wait_for_completion_timeout(&fep->mdio_done,
1806 usecs_to_jiffies(FEC_MII_TIMEOUT));
1807 if (time_left == 0) {
1808 fep->mii_timeout = 1;
31b7720c 1809 netdev_err(fep->netdev, "MDIO write timeout\n");
8fff755e 1810 ret = -ETIMEDOUT;
e6b043d5 1811 }
1da177e4 1812
8fff755e
AL		 1813 pm_runtime_mark_last_busy(dev);
1814 pm_runtime_put_autosuspend(dev);
1815
1816 return ret;
e6b043d5 1817}
1da177e4 1818
e8fcfcd5
NA		 1819static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1820{
1821 struct fec_enet_private *fep = netdev_priv(ndev);
1822 int ret;
1823
1824 if (enable) {
1825 ret = clk_prepare_enable(fep->clk_ahb);
1826 if (ret)
1827 return ret;
e8fcfcd5
NA		 1828 if (fep->clk_enet_out) {
1829 ret = clk_prepare_enable(fep->clk_enet_out);
1830 if (ret)
1831 goto failed_clk_enet_out;
1832 }
1833 if (fep->clk_ptp) {
91c0d987 1834 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1835 ret = clk_prepare_enable(fep->clk_ptp);
91c0d987
NA		 1836 if (ret) {
1837 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1838 goto failed_clk_ptp;
91c0d987
NA		 1839 } else {
1840 fep->ptp_clk_on = true;
1841 }
1842 mutex_unlock(&fep->ptp_clk_mutex);
e8fcfcd5 1843 }
9b5330ed
FD		 1844 if (fep->clk_ref) {
1845 ret = clk_prepare_enable(fep->clk_ref);
1846 if (ret)
1847 goto failed_clk_ref;
1848 }
e8fcfcd5
NA		 1849 } else {
1850 clk_disable_unprepare(fep->clk_ahb);
e8fcfcd5
NA		 1851 if (fep->clk_enet_out)
1852 clk_disable_unprepare(fep->clk_enet_out);
91c0d987
NA		 1853 if (fep->clk_ptp) {
1854 mutex_lock(&fep->ptp_clk_mutex);
e8fcfcd5 1855 clk_disable_unprepare(fep->clk_ptp);
91c0d987
NA		 1856 fep->ptp_clk_on = false;
1857 mutex_unlock(&fep->ptp_clk_mutex);
1858 }
9b5330ed
FD		 1859 if (fep->clk_ref)
1860 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1861 }
1862
1863 return 0;
9b5330ed
FD		 1864
1865failed_clk_ref:
1866 if (fep->clk_ref)
1867 clk_disable_unprepare(fep->clk_ref);
e8fcfcd5
NA		 1868failed_clk_ptp:
1869 if (fep->clk_enet_out)
1870 clk_disable_unprepare(fep->clk_enet_out);
1871failed_clk_enet_out:
e8fcfcd5
NA		 1872 clk_disable_unprepare(fep->clk_ahb);
1873
1874 return ret;
1875}
1876
c556167f 1877static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1878{
c556167f 1879 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1880 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1881 char mdio_bus_id[MII_BUS_ID_SIZE];
1882 char phy_name[MII_BUS_ID_SIZE + 3];
1883 int phy_id;
43af940c 1884 int dev_id = fep->dev_id;
562d2f8c 1885
407066f8
UKK		 1886 if (fep->phy_node) {
1887 phy_dev = of_phy_connect(ndev, fep->phy_node,
1888 &fec_enet_adjust_link, 0,
1889 fep->phy_interface);
213a9922
NA		 1890 if (!phy_dev)
1891 return -ENODEV;
407066f8
UKK		 1892 } else {
1893 /* check for attached phy */
1894 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
7f854420 1895 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
407066f8
UKK		 1896 continue;
1897 if (dev_id--)
1898 continue;
949bdd20 1899 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
407066f8
UKK		 1900 break;
1901 }
1da177e4 1902
407066f8
UKK		 1903 if (phy_id >= PHY_MAX_ADDR) {
1904 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
949bdd20 1905 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
407066f8
UKK		 1906 phy_id = 0;
1907 }
1908
1909 snprintf(phy_name, sizeof(phy_name),
1910 PHY_ID_FMT, mdio_bus_id, phy_id);
1911 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1912 fep->phy_interface);
6fcc040f
GU		 1913 }
1914
6fcc040f 1915 if (IS_ERR(phy_dev)) {
31b7720c 1916 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1917 return PTR_ERR(phy_dev);
e6b043d5 1918 }
1da177e4 1919
e6b043d5 1920 /* mask with MAC supported features */
6b7e4008 1921 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
230dec61 1922 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1923 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1924#if !defined(CONFIG_M5272)
baa70a5c 1925 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1926#endif
baa70a5c 1927 }
230dec61
SG		 1928 else
1929 phy_dev->supported &= PHY_BASIC_FEATURES;
1930
e6b043d5 1931 phy_dev->advertising = phy_dev->supported;
1da177e4 1932
e6b043d5
BW		 1933 fep->link = 0;
1934 fep->full_duplex = 0;
1da177e4 1935
2220943a 1936 phy_attached_info(phy_dev);
418bd0d4 1937
e6b043d5 1938 return 0;
1da177e4
LT		 1939}
1940
e6b043d5 1941static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1942{
b5680e0b 1943 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1944 struct net_device *ndev = platform_get_drvdata(pdev);
1945 struct fec_enet_private *fep = netdev_priv(ndev);
407066f8 1946 struct device_node *node;
e7f4dc35 1947 int err = -ENXIO;
63c60732 1948 u32 mii_speed, holdtime;
6b265293 1949
b5680e0b 1950 /*
3d125f9c 1951 * The i.MX28 dual fec interfaces are not equal.
b5680e0b
SG		 1952 * Here are the differences:
1953 *
1954 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1955 * - fec0 acts as the 1588 time master while fec1 is slave
1956 * - external phys can only be configured by fec0
1957 *
1958 * That is to say fec1 can not work independently. It only works
1959 * when fec0 is working. The reason behind this design is that the
1960 * second interface is added primarily for Switch mode.
1961 *
1962 * Because of the last point above, both phys are attached on fec0
1963 * mdio interface in board design, and need to be configured by
1964 * fec0 mii_bus.
1965 */
3d125f9c 1966 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
b5680e0b 1967 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1968 if (mii_cnt && fec0_mii_bus) {
1969 fep->mii_bus = fec0_mii_bus;
1970 mii_cnt++;
1971 return 0;
1972 }
1973 return -ENOENT;
b5680e0b
SG		 1974 }
1975
e6b043d5 1976 fep->mii_timeout = 0;
1da177e4 1977
e6b043d5
BW		 1978 /*
1979 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1980 *
1981 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1982 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1983 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1984 * document.
e6b043d5 1985 */
63c60732 1986 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
6b7e4008 1987 if (fep->quirks & FEC_QUIRK_ENET_MAC)
63c60732
UKK		 1988 mii_speed--;
1989 if (mii_speed > 63) {
1990 dev_err(&pdev->dev,
1991 "fec clock (%lu) to fast to get right mii speed\n",
1992 clk_get_rate(fep->clk_ipg));
1993 err = -EINVAL;
1994 goto err_out;
1995 }
1996
1997 /*
1998 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
1999 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2000 * versions are RAZ there, so just ignore the difference and write the
2001 * register always.
2002 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2003 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2004 * output.
2005 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2006 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2007 * holdtime cannot result in a value greater than 3.
2008 */
2009 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2010
2011 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2012
e6b043d5 2013 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 2014
e6b043d5
BW		 2015 fep->mii_bus = mdiobus_alloc();
2016 if (fep->mii_bus == NULL) {
2017 err = -ENOMEM;
2018 goto err_out;
1da177e4
LT		 2019 }
2020
e6b043d5
BW		 2021 fep->mii_bus->name = "fec_enet_mii_bus";
2022 fep->mii_bus->read = fec_enet_mdio_read;
2023 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 2024 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2025 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 2026 fep->mii_bus->priv = fep;
2027 fep->mii_bus->parent = &pdev->dev;
2028
407066f8
UKK		 2029 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2030 if (node) {
2031 err = of_mdiobus_register(fep->mii_bus, node);
2032 of_node_put(node);
2033 } else {
2034 err = mdiobus_register(fep->mii_bus);
2035 }
2036
2037 if (err)
e7f4dc35 2038 goto err_out_free_mdiobus;
1da177e4 2039
e163cc97
LW		 2040 mii_cnt++;
2041
b5680e0b 2042 /* save fec0 mii_bus */
3d125f9c 2043 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
b5680e0b
SG		 2044 fec0_mii_bus = fep->mii_bus;
2045
e6b043d5 2046 return 0;
1da177e4 2047
e6b043d5
BW		 2048err_out_free_mdiobus:
2049 mdiobus_free(fep->mii_bus);
2050err_out:
2051 return err;
1da177e4
LT		 2052}
2053
e6b043d5 2054static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 2055{
e163cc97
LW		 2056 if (--mii_cnt == 0) {
2057 mdiobus_unregister(fep->mii_bus);
e163cc97
LW		 2058 mdiobus_free(fep->mii_bus);
2059 }
1da177e4
LT		 2060}
2061
c556167f 2062static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 2063 struct ethtool_drvinfo *info)
1da177e4 2064{
c556167f 2065 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 2066
7826d43f
JP		 2067 strlcpy(info->driver, fep->pdev->dev.driver->name,
2068 sizeof(info->driver));
2069 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2070 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 2071}
2072
db65f35f
PR		 2073static int fec_enet_get_regs_len(struct net_device *ndev)
2074{
2075 struct fec_enet_private *fep = netdev_priv(ndev);
2076 struct resource *r;
2077 int s = 0;
2078
2079 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2080 if (r)
2081 s = resource_size(r);
2082
2083 return s;
2084}
2085
2086/* List of registers that can be safety be read to dump them with ethtool */
2087#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
05f3b50e 2088 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
db65f35f
PR		 2089static u32 fec_enet_register_offset[] = {
2090 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2091 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2092 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2093 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2094 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2095 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2096 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2097 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2098 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2099 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2100 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2101 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2102 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2103 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2104 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2105 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2106 RMON_T_P_GTE2048, RMON_T_OCTETS,
2107 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2108 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2109 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2110 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2111 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2112 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2113 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2114 RMON_R_P_GTE2048, RMON_R_OCTETS,
2115 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2116 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2117};
2118#else
2119static u32 fec_enet_register_offset[] = {
2120 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2121 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2122 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2123 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2124 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2125 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2126 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2127 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2128 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2129};
2130#endif
2131
2132static void fec_enet_get_regs(struct net_device *ndev,
2133 struct ethtool_regs *regs, void *regbuf)
2134{
2135 struct fec_enet_private *fep = netdev_priv(ndev);
2136 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2137 u32 *buf = (u32 *)regbuf;
2138 u32 i, off;
2139
2140 memset(buf, 0, regs->len);
2141
2142 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2143 off = fec_enet_register_offset[i] / 4;
2144 buf[off] = readl(&theregs[off]);
2145 }
2146}
2147
5ebae489
FL		 2148static int fec_enet_get_ts_info(struct net_device *ndev,
2149 struct ethtool_ts_info *info)
2150{
2151 struct fec_enet_private *fep = netdev_priv(ndev);
2152
2153 if (fep->bufdesc_ex) {
2154
2155 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2156 SOF_TIMESTAMPING_RX_SOFTWARE |
2157 SOF_TIMESTAMPING_SOFTWARE |
2158 SOF_TIMESTAMPING_TX_HARDWARE |
2159 SOF_TIMESTAMPING_RX_HARDWARE |
2160 SOF_TIMESTAMPING_RAW_HARDWARE;
2161 if (fep->ptp_clock)
2162 info->phc_index = ptp_clock_index(fep->ptp_clock);
2163 else
2164 info->phc_index = -1;
2165
2166 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2167 (1 << HWTSTAMP_TX_ON);
2168
2169 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2170 (1 << HWTSTAMP_FILTER_ALL);
2171 return 0;
2172 } else {
2173 return ethtool_op_get_ts_info(ndev, info);
2174 }
2175}
2176
d1391930
GR		 2177#if !defined(CONFIG_M5272)
2178
baa70a5c
FL		 2179static void fec_enet_get_pauseparam(struct net_device *ndev,
2180 struct ethtool_pauseparam *pause)
2181{
2182 struct fec_enet_private *fep = netdev_priv(ndev);
2183
2184 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2185 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2186 pause->rx_pause = pause->tx_pause;
2187}
2188
2189static int fec_enet_set_pauseparam(struct net_device *ndev,
2190 struct ethtool_pauseparam *pause)
2191{
2192 struct fec_enet_private *fep = netdev_priv(ndev);
2193
45f5c327 2194 if (!ndev->phydev)
0b146ca8
RK		 2195 return -ENODEV;
2196
baa70a5c
FL		 2197 if (pause->tx_pause != pause->rx_pause) {
2198 netdev_info(ndev,
2199 "hardware only support enable/disable both tx and rx");
2200 return -EINVAL;
2201 }
2202
2203 fep->pause_flag = 0;
2204
2205 /* tx pause must be same as rx pause */
2206 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2207 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2208
2209 if (pause->rx_pause || pause->autoneg) {
45f5c327
PR		 2210 ndev->phydev->supported |= ADVERTISED_Pause;
2211 ndev->phydev->advertising |= ADVERTISED_Pause;
baa70a5c 2212 } else {
45f5c327
PR		 2213 ndev->phydev->supported &= ~ADVERTISED_Pause;
2214 ndev->phydev->advertising &= ~ADVERTISED_Pause;
baa70a5c
FL		 2215 }
2216
2217 if (pause->autoneg) {
2218 if (netif_running(ndev))
2219 fec_stop(ndev);
45f5c327 2220 phy_start_aneg(ndev->phydev);
baa70a5c 2221 }
dbc64a8e 2222 if (netif_running(ndev)) {
dbc64a8e 2223 napi_disable(&fep->napi);
dbc64a8e 2224 netif_tx_lock_bh(ndev);
ef83337d 2225 fec_restart(ndev);
dbc64a8e 2226 netif_wake_queue(ndev);
6af42d42 2227 netif_tx_unlock_bh(ndev);
dbc64a8e 2228 napi_enable(&fep->napi);
dbc64a8e 2229 }
baa70a5c
FL		 2230
2231 return 0;
2232}
2233
38ae92dc
CH		 2234static const struct fec_stat {
2235 char name[ETH_GSTRING_LEN];
2236 u16 offset;
2237} fec_stats[] = {
2238 /* RMON TX */
2239 { "tx_dropped", RMON_T_DROP },
2240 { "tx_packets", RMON_T_PACKETS },
2241 { "tx_broadcast", RMON_T_BC_PKT },
2242 { "tx_multicast", RMON_T_MC_PKT },
2243 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2244 { "tx_undersize", RMON_T_UNDERSIZE },
2245 { "tx_oversize", RMON_T_OVERSIZE },
2246 { "tx_fragment", RMON_T_FRAG },
2247 { "tx_jabber", RMON_T_JAB },
2248 { "tx_collision", RMON_T_COL },
2249 { "tx_64byte", RMON_T_P64 },
2250 { "tx_65to127byte", RMON_T_P65TO127 },
2251 { "tx_128to255byte", RMON_T_P128TO255 },
2252 { "tx_256to511byte", RMON_T_P256TO511 },
2253 { "tx_512to1023byte", RMON_T_P512TO1023 },
2254 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2255 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2256 { "tx_octets", RMON_T_OCTETS },
2257
2258 /* IEEE TX */
2259 { "IEEE_tx_drop", IEEE_T_DROP },
2260 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2261 { "IEEE_tx_1col", IEEE_T_1COL },
2262 { "IEEE_tx_mcol", IEEE_T_MCOL },
2263 { "IEEE_tx_def", IEEE_T_DEF },
2264 { "IEEE_tx_lcol", IEEE_T_LCOL },
2265 { "IEEE_tx_excol", IEEE_T_EXCOL },
2266 { "IEEE_tx_macerr", IEEE_T_MACERR },
2267 { "IEEE_tx_cserr", IEEE_T_CSERR },
2268 { "IEEE_tx_sqe", IEEE_T_SQE },
2269 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2270 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2271
2272 /* RMON RX */
2273 { "rx_packets", RMON_R_PACKETS },
2274 { "rx_broadcast", RMON_R_BC_PKT },
2275 { "rx_multicast", RMON_R_MC_PKT },
2276 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2277 { "rx_undersize", RMON_R_UNDERSIZE },
2278 { "rx_oversize", RMON_R_OVERSIZE },
2279 { "rx_fragment", RMON_R_FRAG },
2280 { "rx_jabber", RMON_R_JAB },
2281 { "rx_64byte", RMON_R_P64 },
2282 { "rx_65to127byte", RMON_R_P65TO127 },
2283 { "rx_128to255byte", RMON_R_P128TO255 },
2284 { "rx_256to511byte", RMON_R_P256TO511 },
2285 { "rx_512to1023byte", RMON_R_P512TO1023 },
2286 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2287 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2288 { "rx_octets", RMON_R_OCTETS },
2289
2290 /* IEEE RX */
2291 { "IEEE_rx_drop", IEEE_R_DROP },
2292 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2293 { "IEEE_rx_crc", IEEE_R_CRC },
2294 { "IEEE_rx_align", IEEE_R_ALIGN },
2295 { "IEEE_rx_macerr", IEEE_R_MACERR },
2296 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2297 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2298};
2299
2300static void fec_enet_get_ethtool_stats(struct net_device *dev,
2301 struct ethtool_stats *stats, u64 *data)
2302{
2303 struct fec_enet_private *fep = netdev_priv(dev);
2304 int i;
2305
2306 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2307 data[i] = readl(fep->hwp + fec_stats[i].offset);
2308}
2309
2310static void fec_enet_get_strings(struct net_device *netdev,
2311 u32 stringset, u8 *data)
2312{
2313 int i;
2314 switch (stringset) {
2315 case ETH_SS_STATS:
2316 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2317 memcpy(data + i * ETH_GSTRING_LEN,
2318 fec_stats[i].name, ETH_GSTRING_LEN);
2319 break;
2320 }
2321}
2322
2323static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2324{
2325 switch (sset) {
2326 case ETH_SS_STATS:
2327 return ARRAY_SIZE(fec_stats);
2328 default:
2329 return -EOPNOTSUPP;
2330 }
2331}
d1391930 2332#endif /* !defined(CONFIG_M5272) */
38ae92dc 2333
32bc9b46
CH		 2334static int fec_enet_nway_reset(struct net_device *dev)
2335{
45f5c327 2336 struct phy_device *phydev = dev->phydev;
32bc9b46
CH		 2337
2338 if (!phydev)
2339 return -ENODEV;
2340
2341 return genphy_restart_aneg(phydev);
2342}
2343
d851b47b
FD		 2344/* ITR clock source is enet system clock (clk_ahb).
2345 * TCTT unit is cycle_ns * 64 cycle
2346 * So, the ICTT value = X us / (cycle_ns * 64)
2347 */
2348static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2349{
2350 struct fec_enet_private *fep = netdev_priv(ndev);
2351
2352 return us * (fep->itr_clk_rate / 64000) / 1000;
2353}
2354
2355/* Set threshold for interrupt coalescing */
2356static void fec_enet_itr_coal_set(struct net_device *ndev)
2357{
2358 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2359 int rx_itr, tx_itr;
2360
6b7e4008 2361 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2362 return;
2363
2364 /* Must be greater than zero to avoid unpredictable behavior */
2365 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2366 !fep->tx_time_itr || !fep->tx_pkts_itr)
2367 return;
2368
2369 /* Select enet system clock as Interrupt Coalescing
2370 * timer Clock Source
2371 */
2372 rx_itr = FEC_ITR_CLK_SEL;
2373 tx_itr = FEC_ITR_CLK_SEL;
2374
2375 /* set ICFT and ICTT */
2376 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2377 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2378 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2379 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2380
2381 rx_itr |= FEC_ITR_EN;
2382 tx_itr |= FEC_ITR_EN;
2383
2384 writel(tx_itr, fep->hwp + FEC_TXIC0);
2385 writel(rx_itr, fep->hwp + FEC_RXIC0);
2386 writel(tx_itr, fep->hwp + FEC_TXIC1);
2387 writel(rx_itr, fep->hwp + FEC_RXIC1);
2388 writel(tx_itr, fep->hwp + FEC_TXIC2);
2389 writel(rx_itr, fep->hwp + FEC_RXIC2);
2390}
2391
2392static int
2393fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2394{
2395 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b 2396
6b7e4008 2397 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2398 return -EOPNOTSUPP;
2399
2400 ec->rx_coalesce_usecs = fep->rx_time_itr;
2401 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2402
2403 ec->tx_coalesce_usecs = fep->tx_time_itr;
2404 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2405
2406 return 0;
2407}
2408
2409static int
2410fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2411{
2412 struct fec_enet_private *fep = netdev_priv(ndev);
d851b47b
FD		 2413 unsigned int cycle;
2414
6b7e4008 2415 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
d851b47b
FD		 2416 return -EOPNOTSUPP;
2417
2418 if (ec->rx_max_coalesced_frames > 255) {
2419 pr_err("Rx coalesced frames exceed hardware limiation");
2420 return -EINVAL;
2421 }
2422
2423 if (ec->tx_max_coalesced_frames > 255) {
2424 pr_err("Tx coalesced frame exceed hardware limiation");
2425 return -EINVAL;
2426 }
2427
2428 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2429 if (cycle > 0xFFFF) {
2430 pr_err("Rx coalesed usec exceeed hardware limiation");
2431 return -EINVAL;
2432 }
2433
2434 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2435 if (cycle > 0xFFFF) {
2436 pr_err("Rx coalesed usec exceeed hardware limiation");
2437 return -EINVAL;
2438 }
2439
2440 fep->rx_time_itr = ec->rx_coalesce_usecs;
2441 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2442
2443 fep->tx_time_itr = ec->tx_coalesce_usecs;
2444 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2445
2446 fec_enet_itr_coal_set(ndev);
2447
2448 return 0;
2449}
2450
2451static void fec_enet_itr_coal_init(struct net_device *ndev)
2452{
2453 struct ethtool_coalesce ec;
2454
2455 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2456 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2457
2458 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2459 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2460
2461 fec_enet_set_coalesce(ndev, &ec);
2462}
2463
1b7bde6d
NA		 2464static int fec_enet_get_tunable(struct net_device *netdev,
2465 const struct ethtool_tunable *tuna,
2466 void *data)
2467{
2468 struct fec_enet_private *fep = netdev_priv(netdev);
2469 int ret = 0;
2470
2471 switch (tuna->id) {
2472 case ETHTOOL_RX_COPYBREAK:
2473 *(u32 *)data = fep->rx_copybreak;
2474 break;
2475 default:
2476 ret = -EINVAL;
2477 break;
2478 }
2479
2480 return ret;
2481}
2482
2483static int fec_enet_set_tunable(struct net_device *netdev,
2484 const struct ethtool_tunable *tuna,
2485 const void *data)
2486{
2487 struct fec_enet_private *fep = netdev_priv(netdev);
2488 int ret = 0;
2489
2490 switch (tuna->id) {
2491 case ETHTOOL_RX_COPYBREAK:
2492 fep->rx_copybreak = *(u32 *)data;
2493 break;
2494 default:
2495 ret = -EINVAL;
2496 break;
2497 }
2498
2499 return ret;
2500}
2501
de40ed31
NA		 2502static void
2503fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2504{
2505 struct fec_enet_private *fep = netdev_priv(ndev);
2506
2507 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2508 wol->supported = WAKE_MAGIC;
2509 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2510 } else {
2511 wol->supported = wol->wolopts = 0;
2512 }
2513}
2514
2515static int
2516fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2517{
2518 struct fec_enet_private *fep = netdev_priv(ndev);
2519
2520 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2521 return -EINVAL;
2522
2523 if (wol->wolopts & ~WAKE_MAGIC)
2524 return -EINVAL;
2525
2526 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2527 if (device_may_wakeup(&ndev->dev)) {
2528 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2529 if (fep->irq[0] > 0)
2530 enable_irq_wake(fep->irq[0]);
2531 } else {
2532 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2533 if (fep->irq[0] > 0)
2534 disable_irq_wake(fep->irq[0]);
2535 }
2536
2537 return 0;
2538}
2539
9b07be4b 2540static const struct ethtool_ops fec_enet_ethtool_ops = {
e6b043d5 2541 .get_drvinfo = fec_enet_get_drvinfo,
db65f35f
PR		 2542 .get_regs_len = fec_enet_get_regs_len,
2543 .get_regs = fec_enet_get_regs,
32bc9b46 2544 .nway_reset = fec_enet_nway_reset,
c1d7c48f 2545 .get_link = ethtool_op_get_link,
d851b47b
FD		 2546 .get_coalesce = fec_enet_get_coalesce,
2547 .set_coalesce = fec_enet_set_coalesce,
38ae92dc 2548#ifndef CONFIG_M5272
c1d7c48f
RK		 2549 .get_pauseparam = fec_enet_get_pauseparam,
2550 .set_pauseparam = fec_enet_set_pauseparam,
38ae92dc 2551 .get_strings = fec_enet_get_strings,
c1d7c48f 2552 .get_ethtool_stats = fec_enet_get_ethtool_stats,
38ae92dc
CH		 2553 .get_sset_count = fec_enet_get_sset_count,
2554#endif
c1d7c48f 2555 .get_ts_info = fec_enet_get_ts_info,
1b7bde6d
NA		 2556 .get_tunable = fec_enet_get_tunable,
2557 .set_tunable = fec_enet_set_tunable,
de40ed31
NA		 2558 .get_wol = fec_enet_get_wol,
2559 .set_wol = fec_enet_set_wol,
9365fbf5
PR		 2560 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2561 .set_link_ksettings = phy_ethtool_set_link_ksettings,
e6b043d5 2562};
1da177e4 2563
c556167f 2564static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2565{
c556167f 2566 struct fec_enet_private *fep = netdev_priv(ndev);
45f5c327 2567 struct phy_device *phydev = ndev->phydev;
1da177e4 2568
c556167f 2569 if (!netif_running(ndev))
e6b043d5 2570 return -EINVAL;
1da177e4 2571
e6b043d5
BW		 2572 if (!phydev)
2573 return -ENODEV;
2574
1d5244d0
BH		 2575 if (fep->bufdesc_ex) {
2576 if (cmd == SIOCSHWTSTAMP)
2577 return fec_ptp_set(ndev, rq);
2578 if (cmd == SIOCGHWTSTAMP)
2579 return fec_ptp_get(ndev, rq);
2580 }
ff43da86 2581
28b04113 2582 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2583}
2584
c556167f 2585static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2586{
c556167f 2587 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2588 unsigned int i;
f0b3fbea
SH		 2589 struct sk_buff *skb;
2590 struct bufdesc *bdp;
4d494cdc
FD		 2591 struct fec_enet_priv_tx_q *txq;
2592 struct fec_enet_priv_rx_q *rxq;
59d0f746
FL		 2593 unsigned int q;
2594
2595 for (q = 0; q < fep->num_rx_queues; q++) {
2596 rxq = fep->rx_queue[q];
7355f276
TK		 2597 bdp = rxq->bd.base;
2598 for (i = 0; i < rxq->bd.ring_size; i++) {
59d0f746
FL		 2599 skb = rxq->rx_skbuff[i];
2600 rxq->rx_skbuff[i] = NULL;
2601 if (skb) {
2602 dma_unmap_single(&fep->pdev->dev,
5cfa3039 2603 fec32_to_cpu(bdp->cbd_bufaddr),
b64bf4b7 2604 FEC_ENET_RX_FRSIZE - fep->rx_align,
59d0f746
FL		 2605 DMA_FROM_DEVICE);
2606 dev_kfree_skb(skb);
2607 }
7355f276 2608 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
59d0f746
FL		 2609 }
2610 }
4d494cdc 2611
59d0f746
FL		 2612 for (q = 0; q < fep->num_tx_queues; q++) {
2613 txq = fep->tx_queue[q];
7355f276
TK		 2614 bdp = txq->bd.base;
2615 for (i = 0; i < txq->bd.ring_size; i++) {
59d0f746
FL		 2616 kfree(txq->tx_bounce[i]);
2617 txq->tx_bounce[i] = NULL;
2618 skb = txq->tx_skbuff[i];
2619 txq->tx_skbuff[i] = NULL;
f0b3fbea 2620 dev_kfree_skb(skb);
730ee360 2621 }
f0b3fbea 2622 }
59d0f746 2623}
f0b3fbea 2624
59d0f746
FL		 2625static void fec_enet_free_queue(struct net_device *ndev)
2626{
2627 struct fec_enet_private *fep = netdev_priv(ndev);
2628 int i;
2629 struct fec_enet_priv_tx_q *txq;
2630
2631 for (i = 0; i < fep->num_tx_queues; i++)
2632 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2633 txq = fep->tx_queue[i];
2634 dma_free_coherent(NULL,
7355f276 2635 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2636 txq->tso_hdrs,
2637 txq->tso_hdrs_dma);
2638 }
2639
2640 for (i = 0; i < fep->num_rx_queues; i++)
1b4b32c6 2641 kfree(fep->rx_queue[i]);
59d0f746 2642 for (i = 0; i < fep->num_tx_queues; i++)
1b4b32c6 2643 kfree(fep->tx_queue[i]);
59d0f746
FL		 2644}
2645
2646static int fec_enet_alloc_queue(struct net_device *ndev)
2647{
2648 struct fec_enet_private *fep = netdev_priv(ndev);
2649 int i;
2650 int ret = 0;
2651 struct fec_enet_priv_tx_q *txq;
2652
2653 for (i = 0; i < fep->num_tx_queues; i++) {
2654 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2655 if (!txq) {
2656 ret = -ENOMEM;
2657 goto alloc_failed;
2658 }
2659
2660 fep->tx_queue[i] = txq;
7355f276
TK		 2661 txq->bd.ring_size = TX_RING_SIZE;
2662 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
59d0f746
FL		 2663
2664 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2665 txq->tx_wake_threshold =
7355f276 2666 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
59d0f746
FL		 2667
2668 txq->tso_hdrs = dma_alloc_coherent(NULL,
7355f276 2669 txq->bd.ring_size * TSO_HEADER_SIZE,
59d0f746
FL		 2670 &txq->tso_hdrs_dma,
2671 GFP_KERNEL);
2672 if (!txq->tso_hdrs) {
2673 ret = -ENOMEM;
2674 goto alloc_failed;
2675 }
8b7c9efa 2676 }
59d0f746
FL		 2677
2678 for (i = 0; i < fep->num_rx_queues; i++) {
2679 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2680 GFP_KERNEL);
2681 if (!fep->rx_queue[i]) {
2682 ret = -ENOMEM;
2683 goto alloc_failed;
2684 }
2685
7355f276
TK		 2686 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2687 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
59d0f746
FL		 2688 }
2689 return ret;
2690
2691alloc_failed:
2692 fec_enet_free_queue(ndev);
2693 return ret;
f0b3fbea
SH		 2694}
2695
59d0f746
FL		 2696static int
2697fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
f0b3fbea 2698{
c556167f 2699 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2700 unsigned int i;
f0b3fbea
SH		 2701 struct sk_buff *skb;
2702 struct bufdesc *bdp;
4d494cdc 2703 struct fec_enet_priv_rx_q *rxq;
f0b3fbea 2704
59d0f746 2705 rxq = fep->rx_queue[queue];
7355f276
TK		 2706 bdp = rxq->bd.base;
2707 for (i = 0; i < rxq->bd.ring_size; i++) {
b72061a3 2708 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2709 if (!skb)
2710 goto err_alloc;
f0b3fbea 2711
1b7bde6d 2712 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
730ee360 2713 dev_kfree_skb(skb);
ffdce2cc 2714 goto err_alloc;
d842a31f 2715 }
730ee360 2716
4d494cdc 2717 rxq->rx_skbuff[i] = skb;
5cfa3039 2718 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
ff43da86
FL		 2719
2720 if (fep->bufdesc_ex) {
2721 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2722 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
ff43da86
FL		 2723 }
2724
7355f276 2725 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
f0b3fbea
SH		 2726 }
2727
2728 /* Set the last buffer to wrap. */
7355f276 2729 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
5cfa3039 2730 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
59d0f746 2731 return 0;
f0b3fbea 2732
59d0f746
FL		 2733 err_alloc:
2734 fec_enet_free_buffers(ndev);
2735 return -ENOMEM;
2736}
2737
2738static int
2739fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2740{
2741 struct fec_enet_private *fep = netdev_priv(ndev);
2742 unsigned int i;
2743 struct bufdesc *bdp;
2744 struct fec_enet_priv_tx_q *txq;
2745
2746 txq = fep->tx_queue[queue];
7355f276
TK		 2747 bdp = txq->bd.base;
2748 for (i = 0; i < txq->bd.ring_size; i++) {
4d494cdc
FD		 2749 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2750 if (!txq->tx_bounce[i])
ffdce2cc 2751 goto err_alloc;
f0b3fbea 2752
5cfa3039
JB		 2753 bdp->cbd_sc = cpu_to_fec16(0);
2754 bdp->cbd_bufaddr = cpu_to_fec32(0);
6605b730 2755
ff43da86
FL		 2756 if (fep->bufdesc_ex) {
2757 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
5cfa3039 2758 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
ff43da86
FL		 2759 }
2760
7355f276 2761 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
f0b3fbea
SH		 2762 }
2763
2764 /* Set the last buffer to wrap. */
7355f276 2765 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
5cfa3039 2766 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
f0b3fbea
SH		 2767
2768 return 0;
ffdce2cc
RK		 2769
2770 err_alloc:
2771 fec_enet_free_buffers(ndev);
2772 return -ENOMEM;
f0b3fbea
SH		 2773}
2774
59d0f746
FL		 2775static int fec_enet_alloc_buffers(struct net_device *ndev)
2776{
2777 struct fec_enet_private *fep = netdev_priv(ndev);
2778 unsigned int i;
2779
2780 for (i = 0; i < fep->num_rx_queues; i++)
2781 if (fec_enet_alloc_rxq_buffers(ndev, i))
2782 return -ENOMEM;
2783
2784 for (i = 0; i < fep->num_tx_queues; i++)
2785 if (fec_enet_alloc_txq_buffers(ndev, i))
2786 return -ENOMEM;
2787 return 0;
2788}
2789
1da177e4 2790static int
c556167f 2791fec_enet_open(struct net_device *ndev)
1da177e4 2792{
c556167f 2793 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2794 int ret;
1da177e4 2795
8fff755e 2796 ret = pm_runtime_get_sync(&fep->pdev->dev);
b0c6ce24 2797 if (ret < 0)
8fff755e
AL		 2798 return ret;
2799
5bbde4d2 2800 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2801 ret = fec_enet_clk_enable(ndev, true);
2802 if (ret)
8fff755e 2803 goto clk_enable;
e8fcfcd5 2804
1da177e4
LT		 2805 /* I should reset the ring buffers here, but I don't yet know
2806 * a simple way to do that.
2807 */
1da177e4 2808
c556167f 2809 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea 2810 if (ret)
681d2421 2811 goto err_enet_alloc;
f0b3fbea 2812
55dd2753
NA		 2813 /* Init MAC prior to mii bus probe */
2814 fec_restart(ndev);
2815
418bd0d4 2816 /* Probe and connect to PHY when open the interface */
c556167f 2817 ret = fec_enet_mii_probe(ndev);
681d2421
FE		 2818 if (ret)
2819 goto err_enet_mii_probe;
ce5eaf02
RK		 2820
2821 napi_enable(&fep->napi);
45f5c327 2822 phy_start(ndev->phydev);
4d494cdc
FD		 2823 netif_tx_start_all_queues(ndev);
2824
de40ed31
NA		 2825 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2826 FEC_WOL_FLAG_ENABLE);
2827
22f6b860 2828 return 0;
681d2421
FE		 2829
2830err_enet_mii_probe:
2831 fec_enet_free_buffers(ndev);
2832err_enet_alloc:
2833 fec_enet_clk_enable(ndev, false);
8fff755e
AL		 2834clk_enable:
2835 pm_runtime_mark_last_busy(&fep->pdev->dev);
2836 pm_runtime_put_autosuspend(&fep->pdev->dev);
681d2421
FE		 2837 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2838 return ret;
1da177e4
LT		 2839}
2840
2841static int
c556167f 2842fec_enet_close(struct net_device *ndev)
1da177e4 2843{
c556167f 2844 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2845
45f5c327 2846 phy_stop(ndev->phydev);
d76cfae9 2847
31a6de34
RK		 2848 if (netif_device_present(ndev)) {
2849 napi_disable(&fep->napi);
2850 netif_tx_disable(ndev);
8bbbd3c1 2851 fec_stop(ndev);
31a6de34 2852 }
1da177e4 2853
45f5c327 2854 phy_disconnect(ndev->phydev);
418bd0d4 2855
e8fcfcd5 2856 fec_enet_clk_enable(ndev, false);
5bbde4d2 2857 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
8fff755e
AL		 2858 pm_runtime_mark_last_busy(&fep->pdev->dev);
2859 pm_runtime_put_autosuspend(&fep->pdev->dev);
2860
db8880bc 2861 fec_enet_free_buffers(ndev);
f0b3fbea 2862
1da177e4
LT		 2863 return 0;
2864}
2865
1da177e4
LT		 2866/* Set or clear the multicast filter for this adaptor.
2867 * Skeleton taken from sunlance driver.
2868 * The CPM Ethernet implementation allows Multicast as well as individual
2869 * MAC address filtering. Some of the drivers check to make sure it is
2870 * a group multicast address, and discard those that are not. I guess I
2871 * will do the same for now, but just remove the test if you want
2872 * individual filtering as well (do the upper net layers want or support
2873 * this kind of feature?).
2874 */
2875
2876#define HASH_BITS 6 /* #bits in hash */
2877#define CRC32_POLY 0xEDB88320
2878
c556167f 2879static void set_multicast_list(struct net_device *ndev)
1da177e4 2880{
c556167f 2881 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2882 struct netdev_hw_addr *ha;
48e2f183 2883 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2884 unsigned char hash;
2885
c556167f 2886 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2887 tmp = readl(fep->hwp + FEC_R_CNTRL);
2888 tmp |= 0x8;
2889 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2890 return;
2891 }
1da177e4 2892
4e831836
SH		 2893 tmp = readl(fep->hwp + FEC_R_CNTRL);
2894 tmp &= ~0x8;
2895 writel(tmp, fep->hwp + FEC_R_CNTRL);
2896
c556167f 2897 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2898 /* Catch all multicast addresses, so set the
2899 * filter to all 1's
2900 */
2901 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2902 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2903
2904 return;
2905 }
2906
2907 /* Clear filter and add the addresses in hash register
2908 */
2909 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2910 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2911
c556167f 2912 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2913 /* calculate crc32 value of mac address */
2914 crc = 0xffffffff;
2915
c556167f 2916 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2917 data = ha->addr[i];
4e831836
SH		 2918 for (bit = 0; bit < 8; bit++, data >>= 1) {
2919 crc = (crc >> 1) ^
2920 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2921 }
2922 }
4e831836
SH		 2923
2924 /* only upper 6 bits (HASH_BITS) are used
2925 * which point to specific bit in he hash registers
2926 */
2927 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2928
2929 if (hash > 31) {
2930 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2931 tmp |= 1 << (hash - 32);
2932 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2933 } else {
2934 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2935 tmp |= 1 << hash;
2936 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2937 }
1da177e4
LT		 2938 }
2939}
2940
22f6b860 2941/* Set a MAC change in hardware. */
009fda83 2942static int
c556167f 2943fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2944{
c556167f 2945 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2946 struct sockaddr *addr = p;
2947
44934fac
LS		 2948 if (addr) {
2949 if (!is_valid_ether_addr(addr->sa_data))
2950 return -EADDRNOTAVAIL;
2951 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2952 }
1da177e4 2953
9638d19e
NA		 2954 /* Add netif status check here to avoid system hang in below case:
2955 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
2956 * After ethx down, fec all clocks are gated off and then register
2957 * access causes system hang.
2958 */
2959 if (!netif_running(ndev))
2960 return 0;
2961
c556167f
UKK		 2962 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2963 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2964 fep->hwp + FEC_ADDR_LOW);
c556167f 2965 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2966 fep->hwp + FEC_ADDR_HIGH);
009fda83 2967 return 0;
1da177e4
LT		 2968}
2969
7f5c6add 2970#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2971/**
2972 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2973 * @dev: The FEC network adapter
2974 *
2975 * Polled functionality used by netconsole and others in non interrupt mode
2976 *
2977 */
47a5247f 2978static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2979{
2980 int i;
2981 struct fec_enet_private *fep = netdev_priv(dev);
2982
2983 for (i = 0; i < FEC_IRQ_NUM; i++) {
2984 if (fep->irq[i] > 0) {
2985 disable_irq(fep->irq[i]);
2986 fec_enet_interrupt(fep->irq[i], dev);
2987 enable_irq(fep->irq[i]);
2988 }
2989 }
2990}
2991#endif
2992
5bc26726 2993static inline void fec_enet_set_netdev_features(struct net_device *netdev,
4c09eed9
JB		 2994 netdev_features_t features)
2995{
2996 struct fec_enet_private *fep = netdev_priv(netdev);
2997 netdev_features_t changed = features ^ netdev->features;
2998
2999 netdev->features = features;
3000
3001 /* Receive checksum has been changed */
3002 if (changed & NETIF_F_RXCSUM) {
3003 if (features & NETIF_F_RXCSUM)
3004 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3005 else
3006 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 3007 }
5bc26726
NA		 3008}
3009
3010static int fec_set_features(struct net_device *netdev,
3011 netdev_features_t features)
3012{
3013 struct fec_enet_private *fep = netdev_priv(netdev);
3014 netdev_features_t changed = features ^ netdev->features;
4c09eed9 3015
5b40f709 3016 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
5bc26726
NA		 3017 napi_disable(&fep->napi);
3018 netif_tx_lock_bh(netdev);
3019 fec_stop(netdev);
3020 fec_enet_set_netdev_features(netdev, features);
ef83337d 3021 fec_restart(netdev);
4d494cdc 3022 netif_tx_wake_all_queues(netdev);
8506fa1d
RK		 3023 netif_tx_unlock_bh(netdev);
3024 napi_enable(&fep->napi);
5bc26726
NA		 3025 } else {
3026 fec_enet_set_netdev_features(netdev, features);
4c09eed9
JB		 3027 }
3028
3029 return 0;
3030}
3031
009fda83
SH		 3032static const struct net_device_ops fec_netdev_ops = {
3033 .ndo_open = fec_enet_open,
3034 .ndo_stop = fec_enet_close,
3035 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 3036 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 3037 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 3038 .ndo_validate_addr = eth_validate_addr,
3039 .ndo_tx_timeout = fec_timeout,
3040 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 3041 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 3042#ifdef CONFIG_NET_POLL_CONTROLLER
3043 .ndo_poll_controller = fec_poll_controller,
3044#endif
4c09eed9 3045 .ndo_set_features = fec_set_features,
009fda83
SH		 3046};
3047
53bb20d1
TK		 3048static const unsigned short offset_des_active_rxq[] = {
3049 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3050};
3051
3052static const unsigned short offset_des_active_txq[] = {
3053 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3054};
3055
1da177e4
LT		 3056 /*
3057 * XXX: We need to clean up on failure exits here.
ead73183 3058 *
1da177e4 3059 */
c556167f 3060static int fec_enet_init(struct net_device *ndev)
1da177e4 3061{
c556167f 3062 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 3063 struct bufdesc *cbd_base;
4d494cdc 3064 dma_addr_t bd_dma;
55d0218a 3065 int bd_size;
59d0f746 3066 unsigned int i;
7355f276
TK		 3067 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3068 sizeof(struct bufdesc);
3069 unsigned dsize_log2 = __fls(dsize);
55d0218a 3070
7355f276 3071 WARN_ON(dsize != (1 << dsize_log2));
41ef84ce
FD		 3072#if defined(CONFIG_ARM)
3073 fep->rx_align = 0xf;
3074 fep->tx_align = 0xf;
3075#else
3076 fep->rx_align = 0x3;
3077 fep->tx_align = 0x3;
3078#endif
3079
59d0f746 3080 fec_enet_alloc_queue(ndev);
79f33912 3081
7355f276 3082 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
1da177e4 3083
8d4dd5cf 3084 /* Allocate memory for buffer descriptors. */
c0a1a0a6
LS		 3085 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3086 GFP_KERNEL);
4d494cdc 3087 if (!cbd_base) {
79f33912
NA		 3088 return -ENOMEM;
3089 }
3090
4d494cdc 3091 memset(cbd_base, 0, bd_size);
1da177e4 3092
49da97dc 3093 /* Get the Ethernet address */
c556167f 3094 fec_get_mac(ndev);
44934fac
LS		 3095 /* make sure MAC we just acquired is programmed into the hw */
3096 fec_set_mac_address(ndev, NULL);
1da177e4 3097
8d4dd5cf 3098 /* Set receive and transmit descriptor base. */
59d0f746 3099 for (i = 0; i < fep->num_rx_queues; i++) {
7355f276
TK		 3100 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3101 unsigned size = dsize * rxq->bd.ring_size;
3102
3103 rxq->bd.qid = i;
3104 rxq->bd.base = cbd_base;
3105 rxq->bd.cur = cbd_base;
3106 rxq->bd.dma = bd_dma;
3107 rxq->bd.dsize = dsize;
3108 rxq->bd.dsize_log2 = dsize_log2;
53bb20d1 3109 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
7355f276
TK		 3110 bd_dma += size;
3111 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3112 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746
FL		 3113 }
3114
3115 for (i = 0; i < fep->num_tx_queues; i++) {
7355f276
TK		 3116 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3117 unsigned size = dsize * txq->bd.ring_size;
3118
3119 txq->bd.qid = i;
3120 txq->bd.base = cbd_base;
3121 txq->bd.cur = cbd_base;
3122 txq->bd.dma = bd_dma;
3123 txq->bd.dsize = dsize;
3124 txq->bd.dsize_log2 = dsize_log2;
53bb20d1 3125 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
7355f276
TK		 3126 bd_dma += size;
3127 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3128 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
59d0f746 3129 }
4d494cdc 3130
1da177e4 3131
22f6b860 3132 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 3133 ndev->watchdog_timeo = TX_TIMEOUT;
3134 ndev->netdev_ops = &fec_netdev_ops;
3135 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 3136
dc975382 3137 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 3138 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 3139
6b7e4008 3140 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 3141 /* enable hw VLAN support */
3142 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 3143
6b7e4008 3144 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 3145 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3146
48496255
SG		 3147 /* enable hw accelerator */
3148 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 3149 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 3150 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3151 }
4c09eed9 3152
6b7e4008 3153 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
41ef84ce
FD		 3154 fep->tx_align = 0;
3155 fep->rx_align = 0x3f;
3156 }
3157
09d1e541
NA		 3158 ndev->hw_features = ndev->features;
3159
ef83337d 3160 fec_restart(ndev);
1da177e4 3161
1da177e4
LT		 3162 return 0;
3163}
3164
ca2cc333 3165#ifdef CONFIG_OF
33897cc8 3166static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3167{
3168 int err, phy_reset;
962d8cdc 3169 bool active_high = false;
a3caad0a 3170 int msec = 1;
ca2cc333
SG		 3171 struct device_node *np = pdev->dev.of_node;
3172
3173 if (!np)
a9b2c8ef 3174 return;
ca2cc333 3175
a3caad0a
SG		 3176 of_property_read_u32(np, "phy-reset-duration", &msec);
3177 /* A sane reset duration should not be longer than 1s */
3178 if (msec > 1000)
3179 msec = 1;
3180
ca2cc333 3181 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 3182 if (!gpio_is_valid(phy_reset))
3183 return;
3184
962d8cdc 3185 active_high = of_property_read_bool(np, "phy-reset-active-high");
64f10f6e 3186
119fc007 3187 err = devm_gpio_request_one(&pdev->dev, phy_reset,
962d8cdc 3188 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
64f10f6e 3189 "phy-reset");
ca2cc333 3190 if (err) {
07dcf8e9 3191 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 3192 return;
ca2cc333 3193 }
a3caad0a 3194 msleep(msec);
962d8cdc 3195 gpio_set_value_cansleep(phy_reset, !active_high);
ca2cc333
SG		 3196}
3197#else /* CONFIG_OF */
0c7768a0 3198static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 3199{
3200 /*
3201 * In case of platform probe, the reset has been done
3202 * by machine code.
3203 */
ca2cc333
SG		 3204}
3205#endif /* CONFIG_OF */
3206
9fc095f1
FD		 3207static void
3208fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3209{
3210 struct device_node *np = pdev->dev.of_node;
9fc095f1
FD		 3211
3212 *num_tx = *num_rx = 1;
3213
3214 if (!np || !of_device_is_available(np))
3215 return;
3216
3217 /* parse the num of tx and rx queues */
73b1c90d 3218 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
b7bd75cf 3219
73b1c90d 3220 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
9fc095f1
FD		 3221
3222 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
b7bd75cf
FL		 3223 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3224 *num_tx);
9fc095f1
FD		 3225 *num_tx = 1;
3226 return;
3227 }
3228
3229 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
b7bd75cf
FL		 3230 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3231 *num_rx);
9fc095f1
FD		 3232 *num_rx = 1;
3233 return;
3234 }
3235
3236}
3237
33897cc8 3238static int
ead73183
SH		 3239fec_probe(struct platform_device *pdev)
3240{
3241 struct fec_enet_private *fep;
5eb32bd0 3242 struct fec_platform_data *pdata;
ead73183
SH		 3243 struct net_device *ndev;
3244 int i, irq, ret = 0;
3245 struct resource *r;
ca2cc333 3246 const struct of_device_id *of_id;
43af940c 3247 static int dev_id;
407066f8 3248 struct device_node *np = pdev->dev.of_node, *phy_node;
b7bd75cf
FL		 3249 int num_tx_qs;
3250 int num_rx_qs;
ca2cc333 3251
9fc095f1
FD		 3252 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3253
ead73183 3254 /* Init network device */
9fc095f1
FD		 3255 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3256 num_tx_qs, num_rx_qs);
83e519b6
FE		 3257 if (!ndev)
3258 return -ENOMEM;
ead73183
SH		 3259
3260 SET_NETDEV_DEV(ndev, &pdev->dev);
3261
3262 /* setup board info structure */
3263 fep = netdev_priv(ndev);
ead73183 3264
6b7e4008
LW		 3265 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3266 if (of_id)
3267 pdev->id_entry = of_id->data;
3268 fep->quirks = pdev->id_entry->driver_data;
3269
0c818594 3270 fep->netdev = ndev;
9fc095f1
FD		 3271 fep->num_rx_queues = num_rx_qs;
3272 fep->num_tx_queues = num_tx_qs;
3273
d1391930 3274#if !defined(CONFIG_M5272)
baa70a5c 3275 /* default enable pause frame auto negotiation */
6b7e4008 3276 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
baa70a5c 3277 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 3278#endif
baa70a5c 3279
5bbde4d2
NA		 3280 /* Select default pin state */
3281 pinctrl_pm_select_default_state(&pdev->dev);
3282
399db75b 3283 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 3284 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3285 if (IS_ERR(fep->hwp)) {
3286 ret = PTR_ERR(fep->hwp);
3287 goto failed_ioremap;
3288 }
3289
e6b043d5 3290 fep->pdev = pdev;
43af940c 3291 fep->dev_id = dev_id++;
ead73183 3292
ead73183
SH		 3293 platform_set_drvdata(pdev, ndev);
3294
de40ed31
NA		 3295 if (of_get_property(np, "fsl,magic-packet", NULL))
3296 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3297
407066f8
UKK		 3298 phy_node = of_parse_phandle(np, "phy-handle", 0);
3299 if (!phy_node && of_phy_is_fixed_link(np)) {
3300 ret = of_phy_register_fixed_link(np);
3301 if (ret < 0) {
3302 dev_err(&pdev->dev,
3303 "broken fixed-link specification\n");
3304 goto failed_phy;
3305 }
3306 phy_node = of_node_get(np);
3307 }
3308 fep->phy_node = phy_node;
3309
6c5f7808 3310 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 3311 if (ret < 0) {
94660ba0 3312 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 3313 if (pdata)
3314 fep->phy_interface = pdata->phy;
3315 else
3316 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3317 } else {
3318 fep->phy_interface = ret;
3319 }
3320
f4d40de3
SH		 3321 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3322 if (IS_ERR(fep->clk_ipg)) {
3323 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 3324 goto failed_clk;
3325 }
f4d40de3
SH		 3326
3327 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3328 if (IS_ERR(fep->clk_ahb)) {
3329 ret = PTR_ERR(fep->clk_ahb);
3330 goto failed_clk;
3331 }
3332
d851b47b
FD		 3333 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3334
daa7d392
WS		 3335 /* enet_out is optional, depends on board */
3336 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3337 if (IS_ERR(fep->clk_enet_out))
3338 fep->clk_enet_out = NULL;
3339
91c0d987
NA		 3340 fep->ptp_clk_on = false;
3341 mutex_init(&fep->ptp_clk_mutex);
9b5330ed
FD		 3342
3343 /* clk_ref is optional, depends on board */
3344 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3345 if (IS_ERR(fep->clk_ref))
3346 fep->clk_ref = NULL;
3347
6b7e4008 3348 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730
FL		 3349 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3350 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 3351 fep->clk_ptp = NULL;
217b5844 3352 fep->bufdesc_ex = false;
6605b730 3353 }
6605b730 3354
e8fcfcd5 3355 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 3356 if (ret)
3357 goto failed_clk;
3358
8fff755e
AL		 3359 ret = clk_prepare_enable(fep->clk_ipg);
3360 if (ret)
3361 goto failed_clk_ipg;
3362
f4e9f3d2
FE		 3363 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3364 if (!IS_ERR(fep->reg_phy)) {
3365 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 3366 if (ret) {
3367 dev_err(&pdev->dev,
3368 "Failed to enable phy regulator: %d\n", ret);
3369 goto failed_regulator;
3370 }
f6a4d607
FE		 3371 } else {
3372 fep->reg_phy = NULL;
5fa9c0fe
SG		 3373 }
3374
8fff755e
AL		 3375 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3376 pm_runtime_use_autosuspend(&pdev->dev);
14d2b7c1 3377 pm_runtime_get_noresume(&pdev->dev);
8fff755e
AL		 3378 pm_runtime_set_active(&pdev->dev);
3379 pm_runtime_enable(&pdev->dev);
3380
2ca9b2aa
SG		 3381 fec_reset_phy(pdev);
3382
e2f8d555 3383 if (fep->bufdesc_ex)
ca162a82 3384 fec_ptp_init(pdev);
e2f8d555
FE		 3385
3386 ret = fec_enet_init(ndev);
3387 if (ret)
3388 goto failed_init;
3389
3390 for (i = 0; i < FEC_IRQ_NUM; i++) {
3391 irq = platform_get_irq(pdev, i);
3392 if (irq < 0) {
3393 if (i)
3394 break;
3395 ret = irq;
3396 goto failed_irq;
3397 }
0d9b2ab1 3398 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 3399 0, pdev->name, ndev);
0d9b2ab1 3400 if (ret)
e2f8d555 3401 goto failed_irq;
de40ed31
NA		 3402
3403 fep->irq[i] = irq;
e2f8d555
FE		 3404 }
3405
b4d39b53 3406 init_completion(&fep->mdio_done);
e6b043d5
BW		 3407 ret = fec_enet_mii_init(pdev);
3408 if (ret)
3409 goto failed_mii_init;
3410
03c698c9
OS		 3411 /* Carrier starts down, phylib will bring it up */
3412 netif_carrier_off(ndev);
e8fcfcd5 3413 fec_enet_clk_enable(ndev, false);
5bbde4d2 3414 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 3415
ead73183
SH		 3416 ret = register_netdev(ndev);
3417 if (ret)
3418 goto failed_register;
3419
de40ed31
NA		 3420 device_init_wakeup(&ndev->dev, fep->wol_flag &
3421 FEC_WOL_HAS_MAGIC_PACKET);
3422
eb1d0640
FE		 3423 if (fep->bufdesc_ex && fep->ptp_clock)
3424 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3425
1b7bde6d 3426 fep->rx_copybreak = COPYBREAK_DEFAULT;
36cdc743 3427 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
8fff755e
AL		 3428
3429 pm_runtime_mark_last_busy(&pdev->dev);
3430 pm_runtime_put_autosuspend(&pdev->dev);
3431
ead73183
SH		 3432 return 0;
3433
3434failed_register:
e6b043d5
BW		 3435 fec_enet_mii_remove(fep);
3436failed_mii_init:
7a2bbd8d 3437failed_irq:
7a2bbd8d 3438failed_init:
32cba57b 3439 fec_ptp_stop(pdev);
f6a4d607
FE		 3440 if (fep->reg_phy)
3441 regulator_disable(fep->reg_phy);
5fa9c0fe 3442failed_regulator:
8fff755e
AL		 3443 clk_disable_unprepare(fep->clk_ipg);
3444failed_clk_ipg:
e8fcfcd5 3445 fec_enet_clk_enable(ndev, false);
ead73183 3446failed_clk:
407066f8
UKK		 3447failed_phy:
3448 of_node_put(phy_node);
ead73183
SH		 3449failed_ioremap:
3450 free_netdev(ndev);
3451
3452 return ret;
3453}
3454
33897cc8 3455static int
ead73183
SH		 3456fec_drv_remove(struct platform_device *pdev)
3457{
3458 struct net_device *ndev = platform_get_drvdata(pdev);
3459 struct fec_enet_private *fep = netdev_priv(ndev);
3460
36cdc743 3461 cancel_work_sync(&fep->tx_timeout_work);
32cba57b 3462 fec_ptp_stop(pdev);
e163cc97 3463 unregister_netdev(ndev);
e6b043d5 3464 fec_enet_mii_remove(fep);
f6a4d607
FE		 3465 if (fep->reg_phy)
3466 regulator_disable(fep->reg_phy);
407066f8 3467 of_node_put(fep->phy_node);
ead73183 3468 free_netdev(ndev);
28e2188e 3469
ead73183
SH		 3470 return 0;
3471}
3472
dd66d386 3473static int __maybe_unused fec_suspend(struct device *dev)
ead73183 3474{
87cad5c3 3475 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3476 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 3477
da1774e5 3478 rtnl_lock();
04e5216d 3479 if (netif_running(ndev)) {
de40ed31
NA		 3480 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3481 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
45f5c327 3482 phy_stop(ndev->phydev);
31a6de34
RK		 3483 napi_disable(&fep->napi);
3484 netif_tx_lock_bh(ndev);
04e5216d 3485 netif_device_detach(ndev);
31a6de34
RK		 3486 netif_tx_unlock_bh(ndev);
3487 fec_stop(ndev);
f4c4a4e0 3488 fec_enet_clk_enable(ndev, false);
de40ed31
NA		 3489 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3490 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
ead73183 3491 }
da1774e5
RK		 3492 rtnl_unlock();
3493
de40ed31 3494 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
238f7bc7
FE		 3495 regulator_disable(fep->reg_phy);
3496
858eeb7d
NA		 3497 /* SOC supply clock to phy, when clock is disabled, phy link down
3498 * SOC control phy regulator, when regulator is disabled, phy link down
3499 */
3500 if (fep->clk_enet_out || fep->reg_phy)
3501 fep->link = 0;
3502
ead73183
SH		 3503 return 0;
3504}
3505
dd66d386 3506static int __maybe_unused fec_resume(struct device *dev)
ead73183 3507{
87cad5c3 3508 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 3509 struct fec_enet_private *fep = netdev_priv(ndev);
de40ed31 3510 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
238f7bc7 3511 int ret;
de40ed31 3512 int val;
238f7bc7 3513
de40ed31 3514 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
238f7bc7
FE		 3515 ret = regulator_enable(fep->reg_phy);
3516 if (ret)
3517 return ret;
3518 }
ead73183 3519
da1774e5 3520 rtnl_lock();
04e5216d 3521 if (netif_running(ndev)) {
f4c4a4e0
NA		 3522 ret = fec_enet_clk_enable(ndev, true);
3523 if (ret) {
3524 rtnl_unlock();
3525 goto failed_clk;
3526 }
de40ed31
NA		 3527 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3528 if (pdata && pdata->sleep_mode_enable)
3529 pdata->sleep_mode_enable(false);
3530 val = readl(fep->hwp + FEC_ECNTRL);
3531 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3532 writel(val, fep->hwp + FEC_ECNTRL);
3533 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3534 } else {
3535 pinctrl_pm_select_default_state(&fep->pdev->dev);
3536 }
ef83337d 3537 fec_restart(ndev);
31a6de34 3538 netif_tx_lock_bh(ndev);
6af42d42 3539 netif_device_attach(ndev);
dbc64a8e 3540 netif_tx_unlock_bh(ndev);
6af42d42 3541 napi_enable(&fep->napi);
45f5c327 3542 phy_start(ndev->phydev);
ead73183 3543 }
da1774e5 3544 rtnl_unlock();
04e5216d 3545
ead73183 3546 return 0;
13a097bd 3547
e8fcfcd5 3548failed_clk:
13a097bd
FE		 3549 if (fep->reg_phy)
3550 regulator_disable(fep->reg_phy);
3551 return ret;
ead73183
SH		 3552}
3553
8fff755e
AL		 3554static int __maybe_unused fec_runtime_suspend(struct device *dev)
3555{
3556 struct net_device *ndev = dev_get_drvdata(dev);
3557 struct fec_enet_private *fep = netdev_priv(ndev);
3558
3559 clk_disable_unprepare(fep->clk_ipg);
3560
3561 return 0;
3562}
3563
3564static int __maybe_unused fec_runtime_resume(struct device *dev)
3565{
3566 struct net_device *ndev = dev_get_drvdata(dev);
3567 struct fec_enet_private *fep = netdev_priv(ndev);
3568
3569 return clk_prepare_enable(fep->clk_ipg);
3570}
3571
3572static const struct dev_pm_ops fec_pm_ops = {
3573 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3574 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3575};
59d4289b 3576
ead73183
SH		 3577static struct platform_driver fec_driver = {
3578 .driver = {
b5680e0b 3579 .name = DRIVER_NAME,
87cad5c3 3580 .pm = &fec_pm_ops,
ca2cc333 3581 .of_match_table = fec_dt_ids,
ead73183 3582 },
b5680e0b 3583 .id_table = fec_devtype,
87cad5c3 3584 .probe = fec_probe,
33897cc8 3585 .remove = fec_drv_remove,
ead73183
SH		 3586};
3587
aaca2377 3588module_platform_driver(fec_driver);
1da177e4 3589
f8c0aca9 3590MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 3591MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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