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net: fec: replace delayed work with standard work
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
CommitLineData
1da177e4
LT		 1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
7dd6a2aa 5 * Right now, I am very wasteful with the buffers. I allocate memory
1da177e4
LT		 6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
562d2f8c
GU		 15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
7dd6a2aa
GU		 17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
677177c5 19 * Copyright (c) 2004-2006 Macq Electronique SA.
b5680e0b 20 *
230dec61 21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
1da177e4
LT		 22 */
23
1da177e4
LT		 24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
1da177e4
LT		 32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
4c09eed9
JB		 36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
79f33912 39#include <net/tso.h>
4c09eed9
JB		 40#include <linux/tcp.h>
41#include <linux/udp.h>
42#include <linux/icmp.h>
1da177e4
LT		 43#include <linux/spinlock.h>
44#include <linux/workqueue.h>
45#include <linux/bitops.h>
6f501b17
SH		 46#include <linux/io.h>
47#include <linux/irq.h>
196719ec 48#include <linux/clk.h>
ead73183 49#include <linux/platform_device.h>
e6b043d5 50#include <linux/phy.h>
5eb32bd0 51#include <linux/fec.h>
ca2cc333
SG		 52#include <linux/of.h>
53#include <linux/of_device.h>
54#include <linux/of_gpio.h>
55#include <linux/of_net.h>
5fa9c0fe 56#include <linux/regulator/consumer.h>
cdffcf1b 57#include <linux/if_vlan.h>
a68ab98e 58#include <linux/pinctrl/consumer.h>
1da177e4 59
080853af 60#include <asm/cacheflush.h>
196719ec 61
1da177e4 62#include "fec.h"
1da177e4 63
772e42b0
CM		 64static void set_multicast_list(struct net_device *ndev);
65
085e79ed 66#if defined(CONFIG_ARM)
196719ec
SH		 67#define FEC_ALIGNMENT 0xf
68#else
69#define FEC_ALIGNMENT 0x3
70#endif
71
b5680e0b
SG		 72#define DRIVER_NAME "fec"
73
baa70a5c
FL		 74/* Pause frame feild and FIFO threshold */
75#define FEC_ENET_FCE (1 << 5)
76#define FEC_ENET_RSEM_V 0x84
77#define FEC_ENET_RSFL_V 16
78#define FEC_ENET_RAEM_V 0x8
79#define FEC_ENET_RAFL_V 0x8
80#define FEC_ENET_OPD_V 0xFFF0
81
b5680e0b
SG		 82/* Controller is ENET-MAC */
83#define FEC_QUIRK_ENET_MAC (1 << 0)
84/* Controller needs driver to swap frame */
85#define FEC_QUIRK_SWAP_FRAME (1 << 1)
0ca1e290
SG		 86/* Controller uses gasket */
87#define FEC_QUIRK_USE_GASKET (1 << 2)
230dec61
SG		 88/* Controller has GBIT support */
89#define FEC_QUIRK_HAS_GBIT (1 << 3)
ff43da86
FL		 90/* Controller has extend desc buffer */
91#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
48496255
SG		 92/* Controller has hardware checksum support */
93#define FEC_QUIRK_HAS_CSUM (1 << 5)
cdffcf1b
JB		 94/* Controller has hardware vlan support */
95#define FEC_QUIRK_HAS_VLAN (1 << 6)
03191656
FL		 96/* ENET IP errata ERR006358
97 *
98 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
99 * detected as not set during a prior frame transmission, then the
100 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
101 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
03191656
FL		 102 * frames not being transmitted until there is a 0-to-1 transition on
103 * ENET_TDAR[TDAR].
104 */
105#define FEC_QUIRK_ERR006358 (1 << 7)
b5680e0b
SG		 106
107static struct platform_device_id fec_devtype[] = {
108 {
0ca1e290 109 /* keep it for coldfire */
b5680e0b
SG		 110 .name = DRIVER_NAME,
111 .driver_data = 0,
0ca1e290
SG		 112 }, {
113 .name = "imx25-fec",
114 .driver_data = FEC_QUIRK_USE_GASKET,
115 }, {
116 .name = "imx27-fec",
117 .driver_data = 0,
b5680e0b
SG		 118 }, {
119 .name = "imx28-fec",
120 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
230dec61
SG		 121 }, {
122 .name = "imx6q-fec",
ff43da86 123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
cdffcf1b 124 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
03191656 125 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
ca7c4a45 126 }, {
36803542 127 .name = "mvf600-fec",
ca7c4a45 128 .driver_data = FEC_QUIRK_ENET_MAC,
0ca1e290
SG		 129 }, {
130 /* sentinel */
131 }
b5680e0b 132};
0ca1e290 133MODULE_DEVICE_TABLE(platform, fec_devtype);
b5680e0b 134
ca2cc333 135enum imx_fec_type {
a7dd3219 136 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
ca2cc333
SG		 137 IMX27_FEC, /* runs on i.mx27/35/51 */
138 IMX28_FEC,
230dec61 139 IMX6Q_FEC,
36803542 140 MVF600_FEC,
ca2cc333
SG		 141};
142
143static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
230dec61 147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
36803542 148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
ca2cc333
SG		 149 { /* sentinel */ }
150};
151MODULE_DEVICE_TABLE(of, fec_dt_ids);
152
49da97dc
SG		 153static unsigned char macaddr[ETH_ALEN];
154module_param_array(macaddr, byte, NULL, 0);
155MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
1da177e4 156
49da97dc 157#if defined(CONFIG_M5272)
1da177e4
LT		 158/*
159 * Some hardware gets it MAC address out of local flash memory.
160 * if this is non-zero then assume it is the address to get MAC from.
161 */
162#if defined(CONFIG_NETtel)
163#define FEC_FLASHMAC 0xf0006006
164#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
165#define FEC_FLASHMAC 0xf0006000
1da177e4
LT		 166#elif defined(CONFIG_CANCam)
167#define FEC_FLASHMAC 0xf0020000
7dd6a2aa
GU		 168#elif defined (CONFIG_M5272C3)
169#define FEC_FLASHMAC (0xffe04000 + 4)
170#elif defined(CONFIG_MOD5272)
a7dd3219 171#define FEC_FLASHMAC 0xffc0406b
1da177e4
LT		 172#else
173#define FEC_FLASHMAC 0
174#endif
43be6366 175#endif /* CONFIG_M5272 */
ead73183 176
22f6b860 177/* Interrupt events/masks. */
1da177e4
LT		 178#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
179#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
180#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
181#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
182#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
183#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
184#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
185#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
186#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
187#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
188
4bee1f9a 189#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
dc975382 190#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
4bee1f9a 191
cdffcf1b 192/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
1da177e4 193 */
cdffcf1b 194#define PKT_MAXBUF_SIZE 1522
1da177e4 195#define PKT_MINBUF_SIZE 64
cdffcf1b 196#define PKT_MAXBLR_SIZE 1536
1da177e4 197
4c09eed9
JB		 198/* FEC receive acceleration */
199#define FEC_RACC_IPDIS (1 << 1)
200#define FEC_RACC_PRODIS (1 << 2)
201#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
202
1da177e4 203/*
6b265293 204 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
1da177e4
LT		 205 * size bits. Other FEC hardware does not, so we need to take that into
206 * account when setting it.
207 */
562d2f8c 208#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
085e79ed 209 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
1da177e4
LT		 210#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
211#else
212#define OPT_FRAME_SIZE 0
213#endif
214
e6b043d5
BW		 215/* FEC MII MMFR bits definition */
216#define FEC_MMFR_ST (1 << 30)
217#define FEC_MMFR_OP_READ (2 << 28)
218#define FEC_MMFR_OP_WRITE (1 << 28)
219#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
220#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
221#define FEC_MMFR_TA (2 << 16)
222#define FEC_MMFR_DATA(v) (v & 0xffff)
1da177e4 223
c3b084c2 224#define FEC_MII_TIMEOUT 30000 /* us */
1da177e4 225
22f6b860
SH		 226/* Transmitter timeout */
227#define TX_TIMEOUT (2 * HZ)
1da177e4 228
baa70a5c
FL		 229#define FEC_PAUSE_FLAG_AUTONEG 0x1
230#define FEC_PAUSE_FLAG_ENABLE 0x2
231
79f33912
NA		 232#define TSO_HEADER_SIZE 128
233/* Max number of allowed TCP segments for software TSO */
234#define FEC_MAX_TSO_SEGS 100
235#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
236
237#define IS_TSO_HEADER(txq, addr) \
238 ((addr >= txq->tso_hdrs_dma) && \
239 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
240
e163cc97
LW		 241static int mii_cnt;
242
36e24e2e
DFB		 243static inline
244struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 245{
36e24e2e
DFB		 246 struct bufdesc *new_bd = bdp + 1;
247 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
248 struct bufdesc_ex *ex_base;
249 struct bufdesc *base;
250 int ring_size;
251
252 if (bdp >= fep->tx_bd_base) {
253 base = fep->tx_bd_base;
254 ring_size = fep->tx_ring_size;
255 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
256 } else {
257 base = fep->rx_bd_base;
258 ring_size = fep->rx_ring_size;
259 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
260 }
261
262 if (fep->bufdesc_ex)
263 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
264 ex_base : ex_new_bd);
ff43da86 265 else
36e24e2e
DFB		 266 return (new_bd >= (base + ring_size)) ?
267 base : new_bd;
ff43da86
FL		 268}
269
36e24e2e
DFB		 270static inline
271struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
ff43da86 272{
36e24e2e
DFB		 273 struct bufdesc *new_bd = bdp - 1;
274 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
275 struct bufdesc_ex *ex_base;
276 struct bufdesc *base;
277 int ring_size;
278
279 if (bdp >= fep->tx_bd_base) {
280 base = fep->tx_bd_base;
281 ring_size = fep->tx_ring_size;
282 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
283 } else {
284 base = fep->rx_bd_base;
285 ring_size = fep->rx_ring_size;
286 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
287 }
288
289 if (fep->bufdesc_ex)
290 return (struct bufdesc *)((ex_new_bd < ex_base) ?
291 (ex_new_bd + ring_size) : ex_new_bd);
ff43da86 292 else
36e24e2e 293 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
ff43da86
FL		 294}
295
61a4427b
NA		 296static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
297 struct fec_enet_private *fep)
298{
299 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
300}
301
6e909283
NA		 302static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep)
303{
304 int entries;
305
306 entries = ((const char *)fep->dirty_tx -
307 (const char *)fep->cur_tx) / fep->bufdesc_size - 1;
308
309 return entries > 0 ? entries : entries + fep->tx_ring_size;
310}
311
b5680e0b
SG		 312static void *swap_buffer(void *bufaddr, int len)
313{
314 int i;
315 unsigned int *buf = bufaddr;
316
ffed61e6 317 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
b5680e0b
SG		 318 *buf = cpu_to_be32(*buf);
319
320 return bufaddr;
321}
322
62a02c98
FD		 323static inline bool is_ipv4_pkt(struct sk_buff *skb)
324{
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
326}
327
4c09eed9
JB		 328static int
329fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
330{
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
333 return 0;
334
335 if (unlikely(skb_cow_head(skb, 0)))
336 return -1;
337
62a02c98
FD		 338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
4c09eed9
JB		 340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
341
342 return 0;
343}
344
6e909283
NA		 345static int
346fec_enet_txq_submit_frag_skb(struct sk_buff *skb, struct net_device *ndev)
1da177e4 347{
c556167f 348 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 349 const struct platform_device_id *id_entry =
350 platform_get_device_id(fep->pdev);
6e909283
NA		 351 struct bufdesc *bdp = fep->cur_tx;
352 struct bufdesc_ex *ebdp;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
354 int frag, frag_len;
355 unsigned short status;
356 unsigned int estatus = 0;
357 skb_frag_t *this_frag;
de5fb0a0 358 unsigned int index;
6e909283 359 void *bufaddr;
d6bf3143 360 dma_addr_t addr;
6e909283 361 int i;
1da177e4 362
6e909283
NA		 363 for (frag = 0; frag < nr_frags; frag++) {
364 this_frag = &skb_shinfo(skb)->frags[frag];
365 bdp = fec_enet_get_nextdesc(bdp, fep);
366 ebdp = (struct bufdesc_ex *)bdp;
367
368 status = bdp->cbd_sc;
369 status &= ~BD_ENET_TX_STATS;
370 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
371 frag_len = skb_shinfo(skb)->frags[frag].size;
372
373 /* Handle the last BD specially */
374 if (frag == nr_frags - 1) {
375 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
376 if (fep->bufdesc_ex) {
377 estatus |= BD_ENET_TX_INT;
378 if (unlikely(skb_shinfo(skb)->tx_flags &
379 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
380 estatus |= BD_ENET_TX_TS;
381 }
382 }
383
384 if (fep->bufdesc_ex) {
385 if (skb->ip_summed == CHECKSUM_PARTIAL)
386 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
387 ebdp->cbd_bdu = 0;
388 ebdp->cbd_esc = estatus;
389 }
390
391 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
392
393 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
394 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
395 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
396 memcpy(fep->tx_bounce[index], bufaddr, frag_len);
397 bufaddr = fep->tx_bounce[index];
398
399 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
400 swap_buffer(bufaddr, frag_len);
401 }
402
d6bf3143
RK		 403 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
404 DMA_TO_DEVICE);
405 if (dma_mapping_error(&fep->pdev->dev, addr)) {
6e909283
NA		 406 dev_kfree_skb_any(skb);
407 if (net_ratelimit())
408 netdev_err(ndev, "Tx DMA memory map failed\n");
409 goto dma_mapping_error;
410 }
411
d6bf3143 412 bdp->cbd_bufaddr = addr;
6e909283
NA		 413 bdp->cbd_datlen = frag_len;
414 bdp->cbd_sc = status;
415 }
416
417 fep->cur_tx = bdp;
418
419 return 0;
420
421dma_mapping_error:
1da177e4 422 bdp = fep->cur_tx;
6e909283
NA		 423 for (i = 0; i < frag; i++) {
424 bdp = fec_enet_get_nextdesc(bdp, fep);
425 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
426 bdp->cbd_datlen, DMA_TO_DEVICE);
427 }
428 return NETDEV_TX_OK;
429}
1da177e4 430
6e909283
NA		 431static int fec_enet_txq_submit_skb(struct sk_buff *skb, struct net_device *ndev)
432{
433 struct fec_enet_private *fep = netdev_priv(ndev);
434 const struct platform_device_id *id_entry =
435 platform_get_device_id(fep->pdev);
436 int nr_frags = skb_shinfo(skb)->nr_frags;
437 struct bufdesc *bdp, *last_bdp;
438 void *bufaddr;
d6bf3143 439 dma_addr_t addr;
6e909283
NA		 440 unsigned short status;
441 unsigned short buflen;
442 unsigned int estatus = 0;
443 unsigned int index;
79f33912 444 int entries_free;
6e909283 445 int ret;
22f6b860 446
79f33912
NA		 447 entries_free = fec_enet_get_free_txdesc_num(fep);
448 if (entries_free < MAX_SKB_FRAGS + 1) {
449 dev_kfree_skb_any(skb);
450 if (net_ratelimit())
451 netdev_err(ndev, "NOT enough BD for SG!\n");
452 return NETDEV_TX_OK;
453 }
454
4c09eed9
JB		 455 /* Protocol checksum off-load for TCP and UDP. */
456 if (fec_enet_clear_csum(skb, ndev)) {
8e7e6874 457 dev_kfree_skb_any(skb);
4c09eed9
JB		 458 return NETDEV_TX_OK;
459 }
460
6e909283
NA		 461 /* Fill in a Tx ring entry */
462 bdp = fep->cur_tx;
463 status = bdp->cbd_sc;
0e702ab3 464 status &= ~BD_ENET_TX_STATS;
1da177e4 465
22f6b860 466 /* Set buffer length and buffer pointer */
9555b31e 467 bufaddr = skb->data;
6e909283 468 buflen = skb_headlen(skb);
1da177e4 469
61a4427b 470 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
6e909283
NA		 471 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
472 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
473 memcpy(fep->tx_bounce[index], skb->data, buflen);
9555b31e 474 bufaddr = fep->tx_bounce[index];
1da177e4 475
6e909283
NA		 476 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
477 swap_buffer(bufaddr, buflen);
478 }
6aa20a22 479
d6bf3143
RK		 480 /* Push the data cache so the CPM does not get stale memory data. */
481 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
482 if (dma_mapping_error(&fep->pdev->dev, addr)) {
d842a31f
DFB		 483 dev_kfree_skb_any(skb);
484 if (net_ratelimit())
485 netdev_err(ndev, "Tx DMA memory map failed\n");
486 return NETDEV_TX_OK;
487 }
1da177e4 488
6e909283
NA		 489 if (nr_frags) {
490 ret = fec_enet_txq_submit_frag_skb(skb, ndev);
491 if (ret)
492 return ret;
493 } else {
494 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
495 if (fep->bufdesc_ex) {
496 estatus = BD_ENET_TX_INT;
497 if (unlikely(skb_shinfo(skb)->tx_flags &
498 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
499 estatus |= BD_ENET_TX_TS;
500 }
501 }
502
ff43da86
FL		 503 if (fep->bufdesc_ex) {
504
505 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6e909283 506
ff43da86 507 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
6e909283 508 fep->hwts_tx_en))
6605b730 509 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4c09eed9 510
6e909283
NA		 511 if (skb->ip_summed == CHECKSUM_PARTIAL)
512 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
513
514 ebdp->cbd_bdu = 0;
515 ebdp->cbd_esc = estatus;
6605b730 516 }
03191656 517
6e909283
NA		 518 last_bdp = fep->cur_tx;
519 index = fec_enet_get_bd_index(fep->tx_bd_base, last_bdp, fep);
520 /* Save skb pointer */
521 fep->tx_skbuff[index] = skb;
522
523 bdp->cbd_datlen = buflen;
d6bf3143 524 bdp->cbd_bufaddr = addr;
6e909283 525
fb8ef788
DFB		 526 /* Send it on its way. Tell FEC it's ready, interrupt when done,
527 * it's the last BD of the frame, and to put the CRC on the end.
528 */
6e909283 529 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
fb8ef788
DFB		 530 bdp->cbd_sc = status;
531
22f6b860 532 /* If this was the last BD in the ring, start at the beginning again. */
6e909283 533 bdp = fec_enet_get_nextdesc(last_bdp, fep);
1da177e4 534
7a2a8451
ED		 535 skb_tx_timestamp(skb);
536
de5fb0a0
FL		 537 fep->cur_tx = bdp;
538
de5fb0a0
FL		 539 /* Trigger transmission start */
540 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1da177e4 541
6e909283 542 return 0;
1da177e4
LT		 543}
544
79f33912
NA		 545static int
546fec_enet_txq_put_data_tso(struct sk_buff *skb, struct net_device *ndev,
547 struct bufdesc *bdp, int index, char *data,
548 int size, bool last_tcp, bool is_last)
61a4427b
NA		 549{
550 struct fec_enet_private *fep = netdev_priv(ndev);
79f33912
NA		 551 const struct platform_device_id *id_entry =
552 platform_get_device_id(fep->pdev);
553 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
554 unsigned short status;
555 unsigned int estatus = 0;
d6bf3143 556 dma_addr_t addr;
61a4427b
NA		 557
558 status = bdp->cbd_sc;
79f33912 559 status &= ~BD_ENET_TX_STATS;
61a4427b 560
79f33912 561 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
79f33912
NA		 562
563 if (((unsigned long) data) & FEC_ALIGNMENT ||
564 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
565 memcpy(fep->tx_bounce[index], data, size);
566 data = fep->tx_bounce[index];
567
568 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
569 swap_buffer(data, size);
570 }
571
d6bf3143
RK		 572 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
573 if (dma_mapping_error(&fep->pdev->dev, addr)) {
79f33912 574 dev_kfree_skb_any(skb);
6e909283 575 if (net_ratelimit())
79f33912 576 netdev_err(ndev, "Tx DMA memory map failed\n");
61a4427b
NA		 577 return NETDEV_TX_BUSY;
578 }
579
d6bf3143
RK		 580 bdp->cbd_datlen = size;
581 bdp->cbd_bufaddr = addr;
582
79f33912
NA		 583 if (fep->bufdesc_ex) {
584 if (skb->ip_summed == CHECKSUM_PARTIAL)
585 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
586 ebdp->cbd_bdu = 0;
587 ebdp->cbd_esc = estatus;
588 }
589
590 /* Handle the last BD specially */
591 if (last_tcp)
592 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
593 if (is_last) {
594 status |= BD_ENET_TX_INTR;
595 if (fep->bufdesc_ex)
596 ebdp->cbd_esc |= BD_ENET_TX_INT;
597 }
598
599 bdp->cbd_sc = status;
600
601 return 0;
602}
603
604static int
605fec_enet_txq_put_hdr_tso(struct sk_buff *skb, struct net_device *ndev,
606 struct bufdesc *bdp, int index)
607{
608 struct fec_enet_private *fep = netdev_priv(ndev);
609 const struct platform_device_id *id_entry =
610 platform_get_device_id(fep->pdev);
611 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
612 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
613 void *bufaddr;
614 unsigned long dmabuf;
615 unsigned short status;
616 unsigned int estatus = 0;
617
618 status = bdp->cbd_sc;
619 status &= ~BD_ENET_TX_STATS;
620 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
621
622 bufaddr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
623 dmabuf = fep->tso_hdrs_dma + index * TSO_HEADER_SIZE;
624 if (((unsigned long) bufaddr) & FEC_ALIGNMENT ||
625 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
626 memcpy(fep->tx_bounce[index], skb->data, hdr_len);
627 bufaddr = fep->tx_bounce[index];
628
629 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
630 swap_buffer(bufaddr, hdr_len);
631
632 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
633 hdr_len, DMA_TO_DEVICE);
634 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
635 dev_kfree_skb_any(skb);
636 if (net_ratelimit())
637 netdev_err(ndev, "Tx DMA memory map failed\n");
638 return NETDEV_TX_BUSY;
639 }
640 }
641
642 bdp->cbd_bufaddr = dmabuf;
643 bdp->cbd_datlen = hdr_len;
644
645 if (fep->bufdesc_ex) {
646 if (skb->ip_summed == CHECKSUM_PARTIAL)
647 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
648 ebdp->cbd_bdu = 0;
649 ebdp->cbd_esc = estatus;
650 }
651
652 bdp->cbd_sc = status;
653
654 return 0;
655}
656
657static int fec_enet_txq_submit_tso(struct sk_buff *skb, struct net_device *ndev)
658{
659 struct fec_enet_private *fep = netdev_priv(ndev);
660 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
661 int total_len, data_left;
662 struct bufdesc *bdp = fep->cur_tx;
663 struct tso_t tso;
664 unsigned int index = 0;
665 int ret;
666
667 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep)) {
668 dev_kfree_skb_any(skb);
669 if (net_ratelimit())
670 netdev_err(ndev, "NOT enough BD for TSO!\n");
671 return NETDEV_TX_OK;
672 }
673
674 /* Protocol checksum off-load for TCP and UDP. */
675 if (fec_enet_clear_csum(skb, ndev)) {
676 dev_kfree_skb_any(skb);
677 return NETDEV_TX_OK;
678 }
679
680 /* Initialize the TSO handler, and prepare the first payload */
681 tso_start(skb, &tso);
682
683 total_len = skb->len - hdr_len;
684 while (total_len > 0) {
685 char *hdr;
686
687 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
688 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
689 total_len -= data_left;
690
691 /* prepare packet headers: MAC + IP + TCP */
692 hdr = fep->tso_hdrs + index * TSO_HEADER_SIZE;
693 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
694 ret = fec_enet_txq_put_hdr_tso(skb, ndev, bdp, index);
695 if (ret)
696 goto err_release;
697
698 while (data_left > 0) {
699 int size;
700
701 size = min_t(int, tso.size, data_left);
702 bdp = fec_enet_get_nextdesc(bdp, fep);
703 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
704 ret = fec_enet_txq_put_data_tso(skb, ndev, bdp, index, tso.data,
705 size, size == data_left,
706 total_len == 0);
707 if (ret)
708 goto err_release;
709
710 data_left -= size;
711 tso_build_data(skb, &tso, size);
712 }
713
714 bdp = fec_enet_get_nextdesc(bdp, fep);
715 }
716
717 /* Save skb pointer */
718 fep->tx_skbuff[index] = skb;
719
79f33912
NA		 720 skb_tx_timestamp(skb);
721 fep->cur_tx = bdp;
722
723 /* Trigger transmission start */
724 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
725
726 return 0;
727
728err_release:
729 /* TODO: Release all used data descriptors for TSO */
730 return ret;
731}
732
733static netdev_tx_t
734fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
735{
736 struct fec_enet_private *fep = netdev_priv(ndev);
737 int entries_free;
738 int ret;
739
740 if (skb_is_gso(skb))
741 ret = fec_enet_txq_submit_tso(skb, ndev);
742 else
743 ret = fec_enet_txq_submit_skb(skb, ndev);
6e909283
NA		 744 if (ret)
745 return ret;
61a4427b 746
6e909283 747 entries_free = fec_enet_get_free_txdesc_num(fep);
79f33912 748 if (entries_free <= fep->tx_stop_threshold)
61a4427b
NA		 749 netif_stop_queue(ndev);
750
751 return NETDEV_TX_OK;
752}
753
14109a59
FL		 754/* Init RX & TX buffer descriptors
755 */
756static void fec_enet_bd_init(struct net_device *dev)
757{
758 struct fec_enet_private *fep = netdev_priv(dev);
759 struct bufdesc *bdp;
760 unsigned int i;
761
762 /* Initialize the receive buffer descriptors. */
763 bdp = fep->rx_bd_base;
36e24e2e 764 for (i = 0; i < fep->rx_ring_size; i++) {
14109a59
FL		 765
766 /* Initialize the BD for every fragment in the page. */
767 if (bdp->cbd_bufaddr)
768 bdp->cbd_sc = BD_ENET_RX_EMPTY;
769 else
770 bdp->cbd_sc = 0;
36e24e2e 771 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 772 }
773
774 /* Set the last buffer to wrap */
36e24e2e 775 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 776 bdp->cbd_sc |= BD_SC_WRAP;
777
778 fep->cur_rx = fep->rx_bd_base;
779
780 /* ...and the same for transmit */
781 bdp = fep->tx_bd_base;
782 fep->cur_tx = bdp;
36e24e2e 783 for (i = 0; i < fep->tx_ring_size; i++) {
14109a59
FL		 784
785 /* Initialize the BD for every fragment in the page. */
786 bdp->cbd_sc = 0;
d6bf3143 787 if (fep->tx_skbuff[i]) {
14109a59
FL		 788 dev_kfree_skb_any(fep->tx_skbuff[i]);
789 fep->tx_skbuff[i] = NULL;
790 }
791 bdp->cbd_bufaddr = 0;
36e24e2e 792 bdp = fec_enet_get_nextdesc(bdp, fep);
14109a59
FL		 793 }
794
795 /* Set the last buffer to wrap */
36e24e2e 796 bdp = fec_enet_get_prevdesc(bdp, fep);
14109a59
FL		 797 bdp->cbd_sc |= BD_SC_WRAP;
798 fep->dirty_tx = bdp;
799}
800
dbc64a8e
RK		 801/*
802 * This function is called to start or restart the FEC during a link
803 * change, transmit timeout, or to reconfigure the FEC. The network
804 * packet processing for this device must be stopped before this call.
45993653 805 */
1da177e4 806static void
ef83337d 807fec_restart(struct net_device *ndev)
1da177e4 808{
c556167f 809 struct fec_enet_private *fep = netdev_priv(ndev);
45993653
UKK		 810 const struct platform_device_id *id_entry =
811 platform_get_device_id(fep->pdev);
812 int i;
4c09eed9 813 u32 val;
cd1f402c
UKK		 814 u32 temp_mac[2];
815 u32 rcntl = OPT_FRAME_SIZE | 0x04;
230dec61 816 u32 ecntl = 0x2; /* ETHEREN */
1da177e4 817
45993653
UKK		 818 /* Whack a reset. We should wait for this. */
819 writel(1, fep->hwp + FEC_ECNTRL);
820 udelay(10);
1da177e4 821
45993653
UKK		 822 /*
823 * enet-mac reset will reset mac address registers too,
824 * so need to reconfigure it.
825 */
826 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
827 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
828 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
829 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
830 }
1da177e4 831
45993653
UKK		 832 /* Clear any outstanding interrupt. */
833 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1da177e4 834
45993653
UKK		 835 /* Set maximum receive buffer size. */
836 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1da177e4 837
14109a59
FL		 838 fec_enet_bd_init(ndev);
839
45993653
UKK		 840 /* Set receive and transmit descriptor base. */
841 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
ff43da86
FL		 842 if (fep->bufdesc_ex)
843 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
36e24e2e 844 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
ff43da86
FL		 845 else
846 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
36e24e2e 847 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
45993653 848
45993653 849
45993653
UKK		 850 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
851 if (fep->tx_skbuff[i]) {
852 dev_kfree_skb_any(fep->tx_skbuff[i]);
853 fep->tx_skbuff[i] = NULL;
1da177e4 854 }
45993653 855 }
97b72e43 856
45993653 857 /* Enable MII mode */
ef83337d 858 if (fep->full_duplex == DUPLEX_FULL) {
cd1f402c 859 /* FD enable */
45993653
UKK		 860 writel(0x04, fep->hwp + FEC_X_CNTRL);
861 } else {
cd1f402c
UKK		 862 /* No Rcv on Xmit */
863 rcntl |= 0x02;
45993653
UKK		 864 writel(0x0, fep->hwp + FEC_X_CNTRL);
865 }
cd1f402c 866
45993653
UKK		 867 /* Set MII speed */
868 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
869
d1391930 870#if !defined(CONFIG_M5272)
4c09eed9
JB		 871 /* set RX checksum */
872 val = readl(fep->hwp + FEC_RACC);
873 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
874 val |= FEC_RACC_OPTIONS;
875 else
876 val &= ~FEC_RACC_OPTIONS;
877 writel(val, fep->hwp + FEC_RACC);
d1391930 878#endif
4c09eed9 879
45993653
UKK		 880 /*
881 * The phy interface and speed need to get configured
882 * differently on enet-mac.
883 */
884 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
cd1f402c
UKK		 885 /* Enable flow control and length check */
886 rcntl |= 0x40000000 | 0x00000020;
45993653 887
230dec61
SG		 888 /* RGMII, RMII or MII */
889 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
890 rcntl |= (1 << 6);
891 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
cd1f402c 892 rcntl |= (1 << 8);
45993653 893 else
cd1f402c 894 rcntl &= ~(1 << 8);
45993653 895
230dec61
SG		 896 /* 1G, 100M or 10M */
897 if (fep->phy_dev) {
898 if (fep->phy_dev->speed == SPEED_1000)
899 ecntl |= (1 << 5);
900 else if (fep->phy_dev->speed == SPEED_100)
901 rcntl &= ~(1 << 9);
902 else
903 rcntl |= (1 << 9);
904 }
45993653
UKK		 905 } else {
906#ifdef FEC_MIIGSK_ENR
0ca1e290 907 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
8d82f219 908 u32 cfgr;
45993653
UKK		 909 /* disable the gasket and wait */
910 writel(0, fep->hwp + FEC_MIIGSK_ENR);
911 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
912 udelay(1);
913
914 /*
915 * configure the gasket:
916 * RMII, 50 MHz, no loopback, no echo
0ca1e290 917 * MII, 25 MHz, no loopback, no echo
45993653 918 */
8d82f219
EB		 919 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
920 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
921 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
922 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
923 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
45993653
UKK		 924
925 /* re-enable the gasket */
926 writel(2, fep->hwp + FEC_MIIGSK_ENR);
97b72e43 927 }
45993653
UKK		 928#endif
929 }
baa70a5c 930
d1391930 931#if !defined(CONFIG_M5272)
baa70a5c
FL		 932 /* enable pause frame*/
933 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
934 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
935 fep->phy_dev && fep->phy_dev->pause)) {
936 rcntl |= FEC_ENET_FCE;
937
4c09eed9 938 /* set FIFO threshold parameter to reduce overrun */
baa70a5c
FL		 939 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
940 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
941 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
942 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
943
944 /* OPD */
945 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
946 } else {
947 rcntl &= ~FEC_ENET_FCE;
948 }
d1391930 949#endif /* !defined(CONFIG_M5272) */
baa70a5c 950
cd1f402c 951 writel(rcntl, fep->hwp + FEC_R_CNTRL);
3b2b74ca 952
84fe6182
SW		 953 /* Setup multicast filter. */
954 set_multicast_list(ndev);
955#ifndef CONFIG_M5272
956 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
957 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
958#endif
959
230dec61
SG		 960 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
961 /* enable ENET endian swap */
962 ecntl |= (1 << 8);
963 /* enable ENET store and forward mode */
964 writel(1 << 8, fep->hwp + FEC_X_WMRK);
965 }
966
ff43da86
FL		 967 if (fep->bufdesc_ex)
968 ecntl |= (1 << 4);
6605b730 969
38ae92dc 970#ifndef CONFIG_M5272
b9eef55c
JB		 971 /* Enable the MIB statistic event counters */
972 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
38ae92dc
CH		 973#endif
974
45993653 975 /* And last, enable the transmit and receive processing */
230dec61 976 writel(ecntl, fep->hwp + FEC_ECNTRL);
45993653
UKK		 977 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
978
ff43da86
FL		 979 if (fep->bufdesc_ex)
980 fec_ptp_start_cyclecounter(ndev);
981
45993653
UKK		 982 /* Enable interrupts we wish to service */
983 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
984}
985
986static void
987fec_stop(struct net_device *ndev)
988{
989 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 990 const struct platform_device_id *id_entry =
991 platform_get_device_id(fep->pdev);
42431dc2 992 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
45993653
UKK		 993
994 /* We cannot expect a graceful transmit stop without link !!! */
995 if (fep->link) {
996 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
997 udelay(10);
998 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
31b7720c 999 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
45993653
UKK		 1000 }
1001
1002 /* Whack a reset. We should wait for this. */
1003 writel(1, fep->hwp + FEC_ECNTRL);
1004 udelay(10);
1005 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1006 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
230dec61
SG		 1007
1008 /* We have to keep ENET enabled to have MII interrupt stay working */
42431dc2 1009 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
230dec61 1010 writel(2, fep->hwp + FEC_ECNTRL);
42431dc2
LW		 1011 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1012 }
1da177e4
LT		 1013}
1014
1015
45993653
UKK		 1016static void
1017fec_timeout(struct net_device *ndev)
1018{
1019 struct fec_enet_private *fep = netdev_priv(ndev);
1020
1021 ndev->stats.tx_errors++;
1022
36cdc743 1023 schedule_work(&fep->tx_timeout_work);
54309fa6
FL		 1024}
1025
36cdc743 1026static void fec_enet_timeout_work(struct work_struct *work)
54309fa6
FL		 1027{
1028 struct fec_enet_private *fep =
36cdc743 1029 container_of(work, struct fec_enet_private, tx_timeout_work);
8ce5624f 1030 struct net_device *ndev = fep->netdev;
54309fa6 1031
36cdc743
RK		 1032 rtnl_lock();
1033 if (netif_device_present(ndev) || netif_running(ndev)) {
1034 napi_disable(&fep->napi);
1035 netif_tx_lock_bh(ndev);
1036 fec_restart(ndev);
1037 netif_wake_queue(ndev);
1038 netif_tx_unlock_bh(ndev);
1039 napi_enable(&fep->napi);
54309fa6 1040 }
36cdc743 1041 rtnl_unlock();
45993653
UKK		 1042}
1043
1da177e4 1044static void
c556167f 1045fec_enet_tx(struct net_device *ndev)
1da177e4
LT		 1046{
1047 struct fec_enet_private *fep;
2e28532f 1048 struct bufdesc *bdp;
0e702ab3 1049 unsigned short status;
1da177e4 1050 struct sk_buff *skb;
de5fb0a0 1051 int index = 0;
79f33912 1052 int entries_free;
1da177e4 1053
c556167f 1054 fep = netdev_priv(ndev);
1da177e4
LT		 1055 bdp = fep->dirty_tx;
1056
de5fb0a0 1057 /* get next bdp of dirty_tx */
36e24e2e 1058 bdp = fec_enet_get_nextdesc(bdp, fep);
de5fb0a0 1059
0e702ab3 1060 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
de5fb0a0
FL		 1061
1062 /* current queue is empty */
1063 if (bdp == fep->cur_tx)
f0b3fbea
SH		 1064 break;
1065
61a4427b 1066 index = fec_enet_get_bd_index(fep->tx_bd_base, bdp, fep);
de5fb0a0 1067
de5fb0a0 1068 skb = fep->tx_skbuff[index];
d6bf3143 1069 fep->tx_skbuff[index] = NULL;
79f33912
NA		 1070 if (!IS_TSO_HEADER(fep, bdp->cbd_bufaddr))
1071 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1072 bdp->cbd_datlen, DMA_TO_DEVICE);
2488a54e 1073 bdp->cbd_bufaddr = 0;
6e909283
NA		 1074 if (!skb) {
1075 bdp = fec_enet_get_nextdesc(bdp, fep);
1076 continue;
1077 }
de5fb0a0 1078
1da177e4 1079 /* Check for errors. */
0e702ab3 1080 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1da177e4
LT		 1081 BD_ENET_TX_RL | BD_ENET_TX_UN |
1082 BD_ENET_TX_CSL)) {
c556167f 1083 ndev->stats.tx_errors++;
0e702ab3 1084 if (status & BD_ENET_TX_HB) /* No heartbeat */
c556167f 1085 ndev->stats.tx_heartbeat_errors++;
0e702ab3 1086 if (status & BD_ENET_TX_LC) /* Late collision */
c556167f 1087 ndev->stats.tx_window_errors++;
0e702ab3 1088 if (status & BD_ENET_TX_RL) /* Retrans limit */
c556167f 1089 ndev->stats.tx_aborted_errors++;
0e702ab3 1090 if (status & BD_ENET_TX_UN) /* Underrun */
c556167f 1091 ndev->stats.tx_fifo_errors++;
0e702ab3 1092 if (status & BD_ENET_TX_CSL) /* Carrier lost */
c556167f 1093 ndev->stats.tx_carrier_errors++;
1da177e4 1094 } else {
c556167f 1095 ndev->stats.tx_packets++;
6e909283 1096 ndev->stats.tx_bytes += skb->len;
1da177e4
LT		 1097 }
1098
ff43da86
FL		 1099 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1100 fep->bufdesc_ex) {
6605b730
FL		 1101 struct skb_shared_hwtstamps shhwtstamps;
1102 unsigned long flags;
ff43da86 1103 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
6605b730
FL		 1104
1105 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1106 spin_lock_irqsave(&fep->tmreg_lock, flags);
1107 shhwtstamps.hwtstamp = ns_to_ktime(
ff43da86 1108 timecounter_cyc2time(&fep->tc, ebdp->ts));
6605b730
FL		 1109 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1110 skb_tstamp_tx(skb, &shhwtstamps);
1111 }
ff43da86 1112
0e702ab3 1113 if (status & BD_ENET_TX_READY)
31b7720c 1114 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
22f6b860 1115
1da177e4
LT		 1116 /* Deferred means some collisions occurred during transmit,
1117 * but we eventually sent the packet OK.
1118 */
0e702ab3 1119 if (status & BD_ENET_TX_DEF)
c556167f 1120 ndev->stats.collisions++;
6aa20a22 1121
22f6b860 1122 /* Free the sk buffer associated with this last transmit */
1da177e4 1123 dev_kfree_skb_any(skb);
de5fb0a0
FL		 1124
1125 fep->dirty_tx = bdp;
6aa20a22 1126
22f6b860 1127 /* Update pointer to next buffer descriptor to be transmitted */
36e24e2e 1128 bdp = fec_enet_get_nextdesc(bdp, fep);
6aa20a22 1129
22f6b860 1130 /* Since we have freed up a buffer, the ring is no longer full
1da177e4 1131 */
79f33912
NA		 1132 if (netif_queue_stopped(ndev)) {
1133 entries_free = fec_enet_get_free_txdesc_num(fep);
1134 if (entries_free >= fep->tx_wake_threshold)
1135 netif_wake_queue(ndev);
1136 }
1da177e4 1137 }
ccea2968
RK		 1138
1139 /* ERR006538: Keep the transmitter going */
1140 if (bdp != fep->cur_tx && readl(fep->hwp + FEC_X_DES_ACTIVE) == 0)
1141 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
1da177e4
LT		 1142}
1143
1da177e4
LT		 1144/* During a receive, the cur_rx points to the current incoming buffer.
1145 * When we update through the ring, if the next incoming buffer has
1146 * not been given to the system, we just set the empty indicator,
1147 * effectively tossing the packet.
1148 */
dc975382
FL		 1149static int
1150fec_enet_rx(struct net_device *ndev, int budget)
1da177e4 1151{
c556167f 1152 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1153 const struct platform_device_id *id_entry =
1154 platform_get_device_id(fep->pdev);
2e28532f 1155 struct bufdesc *bdp;
0e702ab3 1156 unsigned short status;
1da177e4
LT		 1157 struct sk_buff *skb;
1158 ushort pkt_len;
1159 __u8 *data;
dc975382 1160 int pkt_received = 0;
cdffcf1b
JB		 1161 struct bufdesc_ex *ebdp = NULL;
1162 bool vlan_packet_rcvd = false;
1163 u16 vlan_tag;
d842a31f 1164 int index = 0;
6aa20a22 1165
0e702ab3
GU		 1166#ifdef CONFIG_M532x
1167 flush_cache_all();
6aa20a22 1168#endif
1da177e4 1169
1da177e4
LT		 1170 /* First, grab all of the stats for the incoming packet.
1171 * These get messed up if we get called due to a busy condition.
1172 */
1173 bdp = fep->cur_rx;
1174
22f6b860 1175 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1da177e4 1176
dc975382
FL		 1177 if (pkt_received >= budget)
1178 break;
1179 pkt_received++;
1180
22f6b860
SH		 1181 /* Since we have allocated space to hold a complete frame,
1182 * the last indicator should be set.
1183 */
1184 if ((status & BD_ENET_RX_LAST) == 0)
31b7720c 1185 netdev_err(ndev, "rcv is not +last\n");
1da177e4 1186
22f6b860
SH		 1187 /* Check for errors. */
1188 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1da177e4 1189 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
c556167f 1190 ndev->stats.rx_errors++;
22f6b860
SH		 1191 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1192 /* Frame too long or too short. */
c556167f 1193 ndev->stats.rx_length_errors++;
22f6b860
SH		 1194 }
1195 if (status & BD_ENET_RX_NO) /* Frame alignment */
c556167f 1196 ndev->stats.rx_frame_errors++;
22f6b860 1197 if (status & BD_ENET_RX_CR) /* CRC Error */
c556167f 1198 ndev->stats.rx_crc_errors++;
22f6b860 1199 if (status & BD_ENET_RX_OV) /* FIFO overrun */
c556167f 1200 ndev->stats.rx_fifo_errors++;
1da177e4 1201 }
1da177e4 1202
22f6b860
SH		 1203 /* Report late collisions as a frame error.
1204 * On this error, the BD is closed, but we don't know what we
1205 * have in the buffer. So, just drop this frame on the floor.
1206 */
1207 if (status & BD_ENET_RX_CL) {
c556167f
UKK		 1208 ndev->stats.rx_errors++;
1209 ndev->stats.rx_frame_errors++;
22f6b860
SH		 1210 goto rx_processing_done;
1211 }
1da177e4 1212
22f6b860 1213 /* Process the incoming frame. */
c556167f 1214 ndev->stats.rx_packets++;
22f6b860 1215 pkt_len = bdp->cbd_datlen;
c556167f 1216 ndev->stats.rx_bytes += pkt_len;
1da177e4 1217
61a4427b 1218 index = fec_enet_get_bd_index(fep->rx_bd_base, bdp, fep);
d842a31f
DFB		 1219 data = fep->rx_skbuff[index]->data;
1220 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1221 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
ccdc4f19 1222
b5680e0b
SG		 1223 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1224 swap_buffer(data, pkt_len);
1225
cdffcf1b
JB		 1226 /* Extract the enhanced buffer descriptor */
1227 ebdp = NULL;
1228 if (fep->bufdesc_ex)
1229 ebdp = (struct bufdesc_ex *)bdp;
1230
1231 /* If this is a VLAN packet remove the VLAN Tag */
1232 vlan_packet_rcvd = false;
1233 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1234 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1235 /* Push and remove the vlan tag */
1236 struct vlan_hdr *vlan_header =
1237 (struct vlan_hdr *) (data + ETH_HLEN);
1238 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1239 pkt_len -= VLAN_HLEN;
1240
1241 vlan_packet_rcvd = true;
1242 }
1243
22f6b860
SH		 1244 /* This does 16 byte alignment, exactly what we need.
1245 * The packet length includes FCS, but we don't want to
1246 * include that when passing upstream as it messes up
1247 * bridging applications.
1248 */
b72061a3 1249 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
1da177e4 1250
8549889c 1251 if (unlikely(!skb)) {
c556167f 1252 ndev->stats.rx_dropped++;
22f6b860 1253 } else {
cdffcf1b 1254 int payload_offset = (2 * ETH_ALEN);
8549889c 1255 skb_reserve(skb, NET_IP_ALIGN);
22f6b860 1256 skb_put(skb, pkt_len - 4); /* Make room */
cdffcf1b
JB		 1257
1258 /* Extract the frame data without the VLAN header. */
1259 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
1260 if (vlan_packet_rcvd)
1261 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
1262 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
1263 data + payload_offset,
1264 pkt_len - 4 - (2 * ETH_ALEN));
1265
c556167f 1266 skb->protocol = eth_type_trans(skb, ndev);
ff43da86 1267
6605b730 1268 /* Get receive timestamp from the skb */
ff43da86 1269 if (fep->hwts_rx_en && fep->bufdesc_ex) {
6605b730
FL		 1270 struct skb_shared_hwtstamps *shhwtstamps =
1271 skb_hwtstamps(skb);
1272 unsigned long flags;
1273
1274 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1275
1276 spin_lock_irqsave(&fep->tmreg_lock, flags);
1277 shhwtstamps->hwtstamp = ns_to_ktime(
ff43da86 1278 timecounter_cyc2time(&fep->tc, ebdp->ts));
6605b730
FL		 1279 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1280 }
ff43da86 1281
4c09eed9 1282 if (fep->bufdesc_ex &&
cdffcf1b 1283 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
4c09eed9
JB		 1284 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1285 /* don't check it */
1286 skb->ip_summed = CHECKSUM_UNNECESSARY;
1287 } else {
1288 skb_checksum_none_assert(skb);
1289 }
1290 }
1291
cdffcf1b
JB		 1292 /* Handle received VLAN packets */
1293 if (vlan_packet_rcvd)
1294 __vlan_hwaccel_put_tag(skb,
1295 htons(ETH_P_8021Q),
1296 vlan_tag);
1297
0affdf34 1298 napi_gro_receive(&fep->napi, skb);
22f6b860 1299 }
f0b3fbea 1300
d842a31f
DFB		 1301 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1302 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
22f6b860
SH		 1303rx_processing_done:
1304 /* Clear the status flags for this buffer */
1305 status &= ~BD_ENET_RX_STATS;
1da177e4 1306
22f6b860
SH		 1307 /* Mark the buffer empty */
1308 status |= BD_ENET_RX_EMPTY;
1309 bdp->cbd_sc = status;
6aa20a22 1310
ff43da86
FL		 1311 if (fep->bufdesc_ex) {
1312 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1313
1314 ebdp->cbd_esc = BD_ENET_RX_INT;
1315 ebdp->cbd_prot = 0;
1316 ebdp->cbd_bdu = 0;
1317 }
6605b730 1318
22f6b860 1319 /* Update BD pointer to next entry */
36e24e2e
DFB		 1320 bdp = fec_enet_get_nextdesc(bdp, fep);
1321
22f6b860
SH		 1322 /* Doing this here will keep the FEC running while we process
1323 * incoming frames. On a heavily loaded network, we should be
1324 * able to keep up at the expense of system resources.
1325 */
1326 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1327 }
2e28532f 1328 fep->cur_rx = bdp;
1da177e4 1329
dc975382 1330 return pkt_received;
1da177e4
LT		 1331}
1332
45993653
UKK		 1333static irqreturn_t
1334fec_enet_interrupt(int irq, void *dev_id)
1335{
1336 struct net_device *ndev = dev_id;
1337 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c 1338 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
45993653
UKK		 1339 uint int_events;
1340 irqreturn_t ret = IRQ_NONE;
1341
7a16807c
RK		 1342 int_events = readl(fep->hwp + FEC_IEVENT);
1343 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
45993653 1344
7a16807c
RK		 1345 if (int_events & napi_mask) {
1346 ret = IRQ_HANDLED;
dc975382 1347
7a16807c
RK		 1348 /* Disable the NAPI interrupts */
1349 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1350 napi_schedule(&fep->napi);
1351 }
45993653 1352
7a16807c
RK		 1353 if (int_events & FEC_ENET_MII) {
1354 ret = IRQ_HANDLED;
1355 complete(&fep->mdio_done);
1356 }
45993653
UKK		 1357
1358 return ret;
1359}
1360
dc975382
FL		 1361static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1362{
1363 struct net_device *ndev = napi->dev;
dc975382 1364 struct fec_enet_private *fep = netdev_priv(ndev);
7a16807c
RK		 1365 int pkts;
1366
1367 /*
1368 * Clear any pending transmit or receive interrupts before
1369 * processing the rings to avoid racing with the hardware.
1370 */
1371 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1372
1373 pkts = fec_enet_rx(ndev, budget);
45993653 1374
de5fb0a0
FL		 1375 fec_enet_tx(ndev);
1376
dc975382
FL		 1377 if (pkts < budget) {
1378 napi_complete(napi);
1379 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1380 }
1381 return pkts;
1382}
45993653 1383
e6b043d5 1384/* ------------------------------------------------------------------------- */
0c7768a0 1385static void fec_get_mac(struct net_device *ndev)
1da177e4 1386{
c556167f 1387 struct fec_enet_private *fep = netdev_priv(ndev);
94660ba0 1388 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
e6b043d5 1389 unsigned char *iap, tmpaddr[ETH_ALEN];
1da177e4 1390
49da97dc
SG		 1391 /*
1392 * try to get mac address in following order:
1393 *
1394 * 1) module parameter via kernel command line in form
1395 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1396 */
1397 iap = macaddr;
1398
ca2cc333
SG		 1399 /*
1400 * 2) from device tree data
1401 */
1402 if (!is_valid_ether_addr(iap)) {
1403 struct device_node *np = fep->pdev->dev.of_node;
1404 if (np) {
1405 const char *mac = of_get_mac_address(np);
1406 if (mac)
1407 iap = (unsigned char *) mac;
1408 }
1409 }
ca2cc333 1410
49da97dc 1411 /*
ca2cc333 1412 * 3) from flash or fuse (via platform data)
49da97dc
SG		 1413 */
1414 if (!is_valid_ether_addr(iap)) {
1415#ifdef CONFIG_M5272
1416 if (FEC_FLASHMAC)
1417 iap = (unsigned char *)FEC_FLASHMAC;
1418#else
1419 if (pdata)
589efdc7 1420 iap = (unsigned char *)&pdata->mac;
49da97dc
SG		 1421#endif
1422 }
1423
1424 /*
ca2cc333 1425 * 4) FEC mac registers set by bootloader
49da97dc
SG		 1426 */
1427 if (!is_valid_ether_addr(iap)) {
7d7628f3
DC		 1428 *((__be32 *) &tmpaddr[0]) =
1429 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1430 *((__be16 *) &tmpaddr[4]) =
1431 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
e6b043d5 1432 iap = &tmpaddr[0];
1da177e4
LT		 1433 }
1434
ff5b2fab
LS		 1435 /*
1436 * 5) random mac address
1437 */
1438 if (!is_valid_ether_addr(iap)) {
1439 /* Report it and use a random ethernet address instead */
1440 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1441 eth_hw_addr_random(ndev);
1442 netdev_info(ndev, "Using random MAC address: %pM\n",
1443 ndev->dev_addr);
1444 return;
1445 }
1446
c556167f 1447 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1da177e4 1448
49da97dc
SG		 1449 /* Adjust MAC if using macaddr */
1450 if (iap == macaddr)
43af940c 1451 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1da177e4
LT		 1452}
1453
e6b043d5 1454/* ------------------------------------------------------------------------- */
1da177e4 1455
e6b043d5
BW		 1456/*
1457 * Phy section
1458 */
c556167f 1459static void fec_enet_adjust_link(struct net_device *ndev)
1da177e4 1460{
c556167f 1461 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1462 struct phy_device *phy_dev = fep->phy_dev;
e6b043d5 1463 int status_change = 0;
1da177e4 1464
e6b043d5
BW		 1465 /* Prevent a state halted on mii error */
1466 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1467 phy_dev->state = PHY_RESUMING;
54309fa6 1468 return;
e6b043d5 1469 }
1da177e4 1470
8ce5624f
RK		 1471 /*
1472 * If the netdev is down, or is going down, we're not interested
1473 * in link state events, so just mark our idea of the link as down
1474 * and ignore the event.
1475 */
1476 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1477 fep->link = 0;
1478 } else if (phy_dev->link) {
d97e7497 1479 if (!fep->link) {
6ea0722f 1480 fep->link = phy_dev->link;
e6b043d5
BW		 1481 status_change = 1;
1482 }
1da177e4 1483
ef83337d
RK		 1484 if (fep->full_duplex != phy_dev->duplex) {
1485 fep->full_duplex = phy_dev->duplex;
d97e7497 1486 status_change = 1;
ef83337d 1487 }
d97e7497
LS		 1488
1489 if (phy_dev->speed != fep->speed) {
1490 fep->speed = phy_dev->speed;
1491 status_change = 1;
1492 }
1493
1494 /* if any of the above changed restart the FEC */
dbc64a8e 1495 if (status_change) {
dbc64a8e 1496 napi_disable(&fep->napi);
dbc64a8e 1497 netif_tx_lock_bh(ndev);
ef83337d 1498 fec_restart(ndev);
dbc64a8e 1499 netif_wake_queue(ndev);
6af42d42 1500 netif_tx_unlock_bh(ndev);
dbc64a8e 1501 napi_enable(&fep->napi);
dbc64a8e 1502 }
d97e7497
LS		 1503 } else {
1504 if (fep->link) {
f208ce10
RK		 1505 napi_disable(&fep->napi);
1506 netif_tx_lock_bh(ndev);
c556167f 1507 fec_stop(ndev);
f208ce10
RK		 1508 netif_tx_unlock_bh(ndev);
1509 napi_enable(&fep->napi);
8d7ed0f0 1510 fep->link = phy_dev->link;
d97e7497
LS		 1511 status_change = 1;
1512 }
1da177e4 1513 }
6aa20a22 1514
e6b043d5
BW		 1515 if (status_change)
1516 phy_print_status(phy_dev);
1517}
1da177e4 1518
e6b043d5 1519static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1da177e4 1520{
e6b043d5 1521 struct fec_enet_private *fep = bus->priv;
97b72e43 1522 unsigned long time_left;
1da177e4 1523
e6b043d5 1524 fep->mii_timeout = 0;
97b72e43 1525 init_completion(&fep->mdio_done);
e6b043d5
BW		 1526
1527 /* start a read op */
1528 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1529 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1530 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1531
1532 /* wait for end of transfer */
97b72e43
BS		 1533 time_left = wait_for_completion_timeout(&fep->mdio_done,
1534 usecs_to_jiffies(FEC_MII_TIMEOUT));
1535 if (time_left == 0) {
1536 fep->mii_timeout = 1;
31b7720c 1537 netdev_err(fep->netdev, "MDIO read timeout\n");
97b72e43 1538 return -ETIMEDOUT;
1da177e4 1539 }
1da177e4 1540
e6b043d5
BW		 1541 /* return value */
1542 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
7dd6a2aa 1543}
6aa20a22 1544
e6b043d5
BW		 1545static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1546 u16 value)
1da177e4 1547{
e6b043d5 1548 struct fec_enet_private *fep = bus->priv;
97b72e43 1549 unsigned long time_left;
1da177e4 1550
e6b043d5 1551 fep->mii_timeout = 0;
97b72e43 1552 init_completion(&fep->mdio_done);
1da177e4 1553
862f0982
SG		 1554 /* start a write op */
1555 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
e6b043d5
BW		 1556 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1557 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1558 fep->hwp + FEC_MII_DATA);
1559
1560 /* wait for end of transfer */
97b72e43
BS		 1561 time_left = wait_for_completion_timeout(&fep->mdio_done,
1562 usecs_to_jiffies(FEC_MII_TIMEOUT));
1563 if (time_left == 0) {
1564 fep->mii_timeout = 1;
31b7720c 1565 netdev_err(fep->netdev, "MDIO write timeout\n");
97b72e43 1566 return -ETIMEDOUT;
e6b043d5 1567 }
1da177e4 1568
e6b043d5
BW		 1569 return 0;
1570}
1da177e4 1571
e8fcfcd5
NA		 1572static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1573{
1574 struct fec_enet_private *fep = netdev_priv(ndev);
1575 int ret;
1576
1577 if (enable) {
1578 ret = clk_prepare_enable(fep->clk_ahb);
1579 if (ret)
1580 return ret;
1581 ret = clk_prepare_enable(fep->clk_ipg);
1582 if (ret)
1583 goto failed_clk_ipg;
1584 if (fep->clk_enet_out) {
1585 ret = clk_prepare_enable(fep->clk_enet_out);
1586 if (ret)
1587 goto failed_clk_enet_out;
1588 }
1589 if (fep->clk_ptp) {
1590 ret = clk_prepare_enable(fep->clk_ptp);
1591 if (ret)
1592 goto failed_clk_ptp;
1593 }
1594 } else {
1595 clk_disable_unprepare(fep->clk_ahb);
1596 clk_disable_unprepare(fep->clk_ipg);
1597 if (fep->clk_enet_out)
1598 clk_disable_unprepare(fep->clk_enet_out);
1599 if (fep->clk_ptp)
1600 clk_disable_unprepare(fep->clk_ptp);
1601 }
1602
1603 return 0;
1604failed_clk_ptp:
1605 if (fep->clk_enet_out)
1606 clk_disable_unprepare(fep->clk_enet_out);
1607failed_clk_enet_out:
1608 clk_disable_unprepare(fep->clk_ipg);
1609failed_clk_ipg:
1610 clk_disable_unprepare(fep->clk_ahb);
1611
1612 return ret;
1613}
1614
c556167f 1615static int fec_enet_mii_probe(struct net_device *ndev)
562d2f8c 1616{
c556167f 1617 struct fec_enet_private *fep = netdev_priv(ndev);
230dec61
SG		 1618 const struct platform_device_id *id_entry =
1619 platform_get_device_id(fep->pdev);
e6b043d5 1620 struct phy_device *phy_dev = NULL;
6fcc040f
GU		 1621 char mdio_bus_id[MII_BUS_ID_SIZE];
1622 char phy_name[MII_BUS_ID_SIZE + 3];
1623 int phy_id;
43af940c 1624 int dev_id = fep->dev_id;
562d2f8c 1625
418bd0d4
BW		 1626 fep->phy_dev = NULL;
1627
6fcc040f
GU		 1628 /* check for attached phy */
1629 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1630 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1631 continue;
1632 if (fep->mii_bus->phy_map[phy_id] == NULL)
1633 continue;
1634 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1635 continue;
b5680e0b
SG		 1636 if (dev_id--)
1637 continue;
6fcc040f
GU		 1638 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1639 break;
e6b043d5 1640 }
1da177e4 1641
6fcc040f 1642 if (phy_id >= PHY_MAX_ADDR) {
31b7720c 1643 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
ea51ade9 1644 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
6fcc040f
GU		 1645 phy_id = 0;
1646 }
1647
a7ed07d5 1648 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
f9a8f83b 1649 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
230dec61 1650 fep->phy_interface);
6fcc040f 1651 if (IS_ERR(phy_dev)) {
31b7720c 1652 netdev_err(ndev, "could not attach to PHY\n");
6fcc040f 1653 return PTR_ERR(phy_dev);
e6b043d5 1654 }
1da177e4 1655
e6b043d5 1656 /* mask with MAC supported features */
baa70a5c 1657 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
230dec61 1658 phy_dev->supported &= PHY_GBIT_FEATURES;
b44592ff 1659 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
d1391930 1660#if !defined(CONFIG_M5272)
baa70a5c 1661 phy_dev->supported |= SUPPORTED_Pause;
d1391930 1662#endif
baa70a5c 1663 }
230dec61
SG		 1664 else
1665 phy_dev->supported &= PHY_BASIC_FEATURES;
1666
e6b043d5 1667 phy_dev->advertising = phy_dev->supported;
1da177e4 1668
e6b043d5
BW		 1669 fep->phy_dev = phy_dev;
1670 fep->link = 0;
1671 fep->full_duplex = 0;
1da177e4 1672
31b7720c
JP		 1673 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1674 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1675 fep->phy_dev->irq);
418bd0d4 1676
e6b043d5 1677 return 0;
1da177e4
LT		 1678}
1679
e6b043d5 1680static int fec_enet_mii_init(struct platform_device *pdev)
562d2f8c 1681{
b5680e0b 1682 static struct mii_bus *fec0_mii_bus;
c556167f
UKK		 1683 struct net_device *ndev = platform_get_drvdata(pdev);
1684 struct fec_enet_private *fep = netdev_priv(ndev);
b5680e0b
SG		 1685 const struct platform_device_id *id_entry =
1686 platform_get_device_id(fep->pdev);
e6b043d5 1687 int err = -ENXIO, i;
6b265293 1688
b5680e0b
SG		 1689 /*
1690 * The dual fec interfaces are not equivalent with enet-mac.
1691 * Here are the differences:
1692 *
1693 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1694 * - fec0 acts as the 1588 time master while fec1 is slave
1695 * - external phys can only be configured by fec0
1696 *
1697 * That is to say fec1 can not work independently. It only works
1698 * when fec0 is working. The reason behind this design is that the
1699 * second interface is added primarily for Switch mode.
1700 *
1701 * Because of the last point above, both phys are attached on fec0
1702 * mdio interface in board design, and need to be configured by
1703 * fec0 mii_bus.
1704 */
43af940c 1705 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
b5680e0b 1706 /* fec1 uses fec0 mii_bus */
e163cc97
LW		 1707 if (mii_cnt && fec0_mii_bus) {
1708 fep->mii_bus = fec0_mii_bus;
1709 mii_cnt++;
1710 return 0;
1711 }
1712 return -ENOENT;
b5680e0b
SG		 1713 }
1714
e6b043d5 1715 fep->mii_timeout = 0;
1da177e4 1716
e6b043d5
BW		 1717 /*
1718 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
230dec61
SG		 1719 *
1720 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1721 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1722 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1723 * document.
e6b043d5 1724 */
98a6eeb8 1725 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
230dec61
SG		 1726 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1727 fep->phy_speed--;
1728 fep->phy_speed <<= 1;
e6b043d5 1729 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1da177e4 1730
e6b043d5
BW		 1731 fep->mii_bus = mdiobus_alloc();
1732 if (fep->mii_bus == NULL) {
1733 err = -ENOMEM;
1734 goto err_out;
1da177e4
LT		 1735 }
1736
e6b043d5
BW		 1737 fep->mii_bus->name = "fec_enet_mii_bus";
1738 fep->mii_bus->read = fec_enet_mdio_read;
1739 fep->mii_bus->write = fec_enet_mdio_write;
391420f7
FF		 1740 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1741 pdev->name, fep->dev_id + 1);
e6b043d5
BW		 1742 fep->mii_bus->priv = fep;
1743 fep->mii_bus->parent = &pdev->dev;
1744
1745 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1746 if (!fep->mii_bus->irq) {
1747 err = -ENOMEM;
1748 goto err_out_free_mdiobus;
1da177e4
LT		 1749 }
1750
e6b043d5
BW		 1751 for (i = 0; i < PHY_MAX_ADDR; i++)
1752 fep->mii_bus->irq[i] = PHY_POLL;
1da177e4 1753
e6b043d5
BW		 1754 if (mdiobus_register(fep->mii_bus))
1755 goto err_out_free_mdio_irq;
1da177e4 1756
e163cc97
LW		 1757 mii_cnt++;
1758
b5680e0b
SG		 1759 /* save fec0 mii_bus */
1760 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1761 fec0_mii_bus = fep->mii_bus;
1762
e6b043d5 1763 return 0;
1da177e4 1764
e6b043d5
BW		 1765err_out_free_mdio_irq:
1766 kfree(fep->mii_bus->irq);
1767err_out_free_mdiobus:
1768 mdiobus_free(fep->mii_bus);
1769err_out:
1770 return err;
1da177e4
LT		 1771}
1772
e6b043d5 1773static void fec_enet_mii_remove(struct fec_enet_private *fep)
1da177e4 1774{
e163cc97
LW		 1775 if (--mii_cnt == 0) {
1776 mdiobus_unregister(fep->mii_bus);
1777 kfree(fep->mii_bus->irq);
1778 mdiobus_free(fep->mii_bus);
1779 }
1da177e4
LT		 1780}
1781
c556167f 1782static int fec_enet_get_settings(struct net_device *ndev,
e6b043d5 1783 struct ethtool_cmd *cmd)
1da177e4 1784{
c556167f 1785 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1786 struct phy_device *phydev = fep->phy_dev;
1da177e4 1787
e6b043d5
BW		 1788 if (!phydev)
1789 return -ENODEV;
1da177e4 1790
e6b043d5 1791 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 1792}
1793
c556167f 1794static int fec_enet_set_settings(struct net_device *ndev,
e6b043d5 1795 struct ethtool_cmd *cmd)
1da177e4 1796{
c556167f 1797 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 1798 struct phy_device *phydev = fep->phy_dev;
1da177e4 1799
e6b043d5
BW		 1800 if (!phydev)
1801 return -ENODEV;
1da177e4 1802
e6b043d5 1803 return phy_ethtool_sset(phydev, cmd);
1da177e4
LT		 1804}
1805
c556167f 1806static void fec_enet_get_drvinfo(struct net_device *ndev,
e6b043d5 1807 struct ethtool_drvinfo *info)
1da177e4 1808{
c556167f 1809 struct fec_enet_private *fep = netdev_priv(ndev);
6aa20a22 1810
7826d43f
JP		 1811 strlcpy(info->driver, fep->pdev->dev.driver->name,
1812 sizeof(info->driver));
1813 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1814 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1da177e4
LT		 1815}
1816
5ebae489
FL		 1817static int fec_enet_get_ts_info(struct net_device *ndev,
1818 struct ethtool_ts_info *info)
1819{
1820 struct fec_enet_private *fep = netdev_priv(ndev);
1821
1822 if (fep->bufdesc_ex) {
1823
1824 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1825 SOF_TIMESTAMPING_RX_SOFTWARE |
1826 SOF_TIMESTAMPING_SOFTWARE |
1827 SOF_TIMESTAMPING_TX_HARDWARE |
1828 SOF_TIMESTAMPING_RX_HARDWARE |
1829 SOF_TIMESTAMPING_RAW_HARDWARE;
1830 if (fep->ptp_clock)
1831 info->phc_index = ptp_clock_index(fep->ptp_clock);
1832 else
1833 info->phc_index = -1;
1834
1835 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1836 (1 << HWTSTAMP_TX_ON);
1837
1838 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1839 (1 << HWTSTAMP_FILTER_ALL);
1840 return 0;
1841 } else {
1842 return ethtool_op_get_ts_info(ndev, info);
1843 }
1844}
1845
d1391930
GR		 1846#if !defined(CONFIG_M5272)
1847
baa70a5c
FL		 1848static void fec_enet_get_pauseparam(struct net_device *ndev,
1849 struct ethtool_pauseparam *pause)
1850{
1851 struct fec_enet_private *fep = netdev_priv(ndev);
1852
1853 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1854 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1855 pause->rx_pause = pause->tx_pause;
1856}
1857
1858static int fec_enet_set_pauseparam(struct net_device *ndev,
1859 struct ethtool_pauseparam *pause)
1860{
1861 struct fec_enet_private *fep = netdev_priv(ndev);
1862
0b146ca8
RK		 1863 if (!fep->phy_dev)
1864 return -ENODEV;
1865
baa70a5c
FL		 1866 if (pause->tx_pause != pause->rx_pause) {
1867 netdev_info(ndev,
1868 "hardware only support enable/disable both tx and rx");
1869 return -EINVAL;
1870 }
1871
1872 fep->pause_flag = 0;
1873
1874 /* tx pause must be same as rx pause */
1875 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1876 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1877
1878 if (pause->rx_pause || pause->autoneg) {
1879 fep->phy_dev->supported |= ADVERTISED_Pause;
1880 fep->phy_dev->advertising |= ADVERTISED_Pause;
1881 } else {
1882 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1883 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1884 }
1885
1886 if (pause->autoneg) {
1887 if (netif_running(ndev))
1888 fec_stop(ndev);
1889 phy_start_aneg(fep->phy_dev);
1890 }
dbc64a8e 1891 if (netif_running(ndev)) {
dbc64a8e 1892 napi_disable(&fep->napi);
dbc64a8e 1893 netif_tx_lock_bh(ndev);
ef83337d 1894 fec_restart(ndev);
dbc64a8e 1895 netif_wake_queue(ndev);
6af42d42 1896 netif_tx_unlock_bh(ndev);
dbc64a8e 1897 napi_enable(&fep->napi);
dbc64a8e 1898 }
baa70a5c
FL		 1899
1900 return 0;
1901}
1902
38ae92dc
CH		 1903static const struct fec_stat {
1904 char name[ETH_GSTRING_LEN];
1905 u16 offset;
1906} fec_stats[] = {
1907 /* RMON TX */
1908 { "tx_dropped", RMON_T_DROP },
1909 { "tx_packets", RMON_T_PACKETS },
1910 { "tx_broadcast", RMON_T_BC_PKT },
1911 { "tx_multicast", RMON_T_MC_PKT },
1912 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1913 { "tx_undersize", RMON_T_UNDERSIZE },
1914 { "tx_oversize", RMON_T_OVERSIZE },
1915 { "tx_fragment", RMON_T_FRAG },
1916 { "tx_jabber", RMON_T_JAB },
1917 { "tx_collision", RMON_T_COL },
1918 { "tx_64byte", RMON_T_P64 },
1919 { "tx_65to127byte", RMON_T_P65TO127 },
1920 { "tx_128to255byte", RMON_T_P128TO255 },
1921 { "tx_256to511byte", RMON_T_P256TO511 },
1922 { "tx_512to1023byte", RMON_T_P512TO1023 },
1923 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1924 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1925 { "tx_octets", RMON_T_OCTETS },
1926
1927 /* IEEE TX */
1928 { "IEEE_tx_drop", IEEE_T_DROP },
1929 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1930 { "IEEE_tx_1col", IEEE_T_1COL },
1931 { "IEEE_tx_mcol", IEEE_T_MCOL },
1932 { "IEEE_tx_def", IEEE_T_DEF },
1933 { "IEEE_tx_lcol", IEEE_T_LCOL },
1934 { "IEEE_tx_excol", IEEE_T_EXCOL },
1935 { "IEEE_tx_macerr", IEEE_T_MACERR },
1936 { "IEEE_tx_cserr", IEEE_T_CSERR },
1937 { "IEEE_tx_sqe", IEEE_T_SQE },
1938 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1939 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1940
1941 /* RMON RX */
1942 { "rx_packets", RMON_R_PACKETS },
1943 { "rx_broadcast", RMON_R_BC_PKT },
1944 { "rx_multicast", RMON_R_MC_PKT },
1945 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1946 { "rx_undersize", RMON_R_UNDERSIZE },
1947 { "rx_oversize", RMON_R_OVERSIZE },
1948 { "rx_fragment", RMON_R_FRAG },
1949 { "rx_jabber", RMON_R_JAB },
1950 { "rx_64byte", RMON_R_P64 },
1951 { "rx_65to127byte", RMON_R_P65TO127 },
1952 { "rx_128to255byte", RMON_R_P128TO255 },
1953 { "rx_256to511byte", RMON_R_P256TO511 },
1954 { "rx_512to1023byte", RMON_R_P512TO1023 },
1955 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1956 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1957 { "rx_octets", RMON_R_OCTETS },
1958
1959 /* IEEE RX */
1960 { "IEEE_rx_drop", IEEE_R_DROP },
1961 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1962 { "IEEE_rx_crc", IEEE_R_CRC },
1963 { "IEEE_rx_align", IEEE_R_ALIGN },
1964 { "IEEE_rx_macerr", IEEE_R_MACERR },
1965 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1966 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1967};
1968
1969static void fec_enet_get_ethtool_stats(struct net_device *dev,
1970 struct ethtool_stats *stats, u64 *data)
1971{
1972 struct fec_enet_private *fep = netdev_priv(dev);
1973 int i;
1974
1975 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1976 data[i] = readl(fep->hwp + fec_stats[i].offset);
1977}
1978
1979static void fec_enet_get_strings(struct net_device *netdev,
1980 u32 stringset, u8 *data)
1981{
1982 int i;
1983 switch (stringset) {
1984 case ETH_SS_STATS:
1985 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1986 memcpy(data + i * ETH_GSTRING_LEN,
1987 fec_stats[i].name, ETH_GSTRING_LEN);
1988 break;
1989 }
1990}
1991
1992static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1993{
1994 switch (sset) {
1995 case ETH_SS_STATS:
1996 return ARRAY_SIZE(fec_stats);
1997 default:
1998 return -EOPNOTSUPP;
1999 }
2000}
d1391930 2001#endif /* !defined(CONFIG_M5272) */
38ae92dc 2002
32bc9b46
CH		 2003static int fec_enet_nway_reset(struct net_device *dev)
2004{
2005 struct fec_enet_private *fep = netdev_priv(dev);
2006 struct phy_device *phydev = fep->phy_dev;
2007
2008 if (!phydev)
2009 return -ENODEV;
2010
2011 return genphy_restart_aneg(phydev);
2012}
2013
9b07be4b 2014static const struct ethtool_ops fec_enet_ethtool_ops = {
d1391930 2015#if !defined(CONFIG_M5272)
baa70a5c
FL		 2016 .get_pauseparam = fec_enet_get_pauseparam,
2017 .set_pauseparam = fec_enet_set_pauseparam,
d1391930 2018#endif
e6b043d5
BW		 2019 .get_settings = fec_enet_get_settings,
2020 .set_settings = fec_enet_set_settings,
2021 .get_drvinfo = fec_enet_get_drvinfo,
2022 .get_link = ethtool_op_get_link,
5ebae489 2023 .get_ts_info = fec_enet_get_ts_info,
32bc9b46 2024 .nway_reset = fec_enet_nway_reset,
38ae92dc
CH		 2025#ifndef CONFIG_M5272
2026 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2027 .get_strings = fec_enet_get_strings,
2028 .get_sset_count = fec_enet_get_sset_count,
2029#endif
e6b043d5 2030};
1da177e4 2031
c556167f 2032static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1da177e4 2033{
c556167f 2034 struct fec_enet_private *fep = netdev_priv(ndev);
e6b043d5 2035 struct phy_device *phydev = fep->phy_dev;
1da177e4 2036
c556167f 2037 if (!netif_running(ndev))
e6b043d5 2038 return -EINVAL;
1da177e4 2039
e6b043d5
BW		 2040 if (!phydev)
2041 return -ENODEV;
2042
1d5244d0
BH		 2043 if (fep->bufdesc_ex) {
2044 if (cmd == SIOCSHWTSTAMP)
2045 return fec_ptp_set(ndev, rq);
2046 if (cmd == SIOCGHWTSTAMP)
2047 return fec_ptp_get(ndev, rq);
2048 }
ff43da86 2049
28b04113 2050 return phy_mii_ioctl(phydev, rq, cmd);
1da177e4
LT		 2051}
2052
c556167f 2053static void fec_enet_free_buffers(struct net_device *ndev)
f0b3fbea 2054{
c556167f 2055 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2056 unsigned int i;
f0b3fbea
SH		 2057 struct sk_buff *skb;
2058 struct bufdesc *bdp;
2059
2060 bdp = fep->rx_bd_base;
36e24e2e 2061 for (i = 0; i < fep->rx_ring_size; i++) {
f0b3fbea 2062 skb = fep->rx_skbuff[i];
730ee360
RK		 2063 fep->rx_skbuff[i] = NULL;
2064 if (skb) {
d1ab1f54 2065 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
f0b3fbea 2066 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
f0b3fbea 2067 dev_kfree_skb(skb);
730ee360 2068 }
36e24e2e 2069 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2070 }
2071
2072 bdp = fep->tx_bd_base;
8b7c9efa 2073 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2074 kfree(fep->tx_bounce[i]);
8b7c9efa
RK		 2075 fep->tx_bounce[i] = NULL;
2076 skb = fep->tx_skbuff[i];
2077 fep->tx_skbuff[i] = NULL;
2078 dev_kfree_skb(skb);
2079 }
f0b3fbea
SH		 2080}
2081
c556167f 2082static int fec_enet_alloc_buffers(struct net_device *ndev)
f0b3fbea 2083{
c556167f 2084 struct fec_enet_private *fep = netdev_priv(ndev);
da2191e3 2085 unsigned int i;
f0b3fbea
SH		 2086 struct sk_buff *skb;
2087 struct bufdesc *bdp;
2088
2089 bdp = fep->rx_bd_base;
36e24e2e 2090 for (i = 0; i < fep->rx_ring_size; i++) {
730ee360
RK		 2091 dma_addr_t addr;
2092
b72061a3 2093 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
ffdce2cc
RK		 2094 if (!skb)
2095 goto err_alloc;
f0b3fbea 2096
730ee360 2097 addr = dma_map_single(&fep->pdev->dev, skb->data,
f0b3fbea 2098 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
730ee360
RK		 2099 if (dma_mapping_error(&fep->pdev->dev, addr)) {
2100 dev_kfree_skb(skb);
d842a31f
DFB		 2101 if (net_ratelimit())
2102 netdev_err(ndev, "Rx DMA memory map failed\n");
ffdce2cc 2103 goto err_alloc;
d842a31f 2104 }
730ee360
RK		 2105
2106 fep->rx_skbuff[i] = skb;
2107 bdp->cbd_bufaddr = addr;
f0b3fbea 2108 bdp->cbd_sc = BD_ENET_RX_EMPTY;
ff43da86
FL		 2109
2110 if (fep->bufdesc_ex) {
2111 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2112 ebdp->cbd_esc = BD_ENET_RX_INT;
2113 }
2114
36e24e2e 2115 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2116 }
2117
2118 /* Set the last buffer to wrap. */
36e24e2e 2119 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2120 bdp->cbd_sc |= BD_SC_WRAP;
2121
2122 bdp = fep->tx_bd_base;
36e24e2e 2123 for (i = 0; i < fep->tx_ring_size; i++) {
f0b3fbea 2124 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
ffdce2cc
RK		 2125 if (!fep->tx_bounce[i])
2126 goto err_alloc;
f0b3fbea
SH		 2127
2128 bdp->cbd_sc = 0;
2129 bdp->cbd_bufaddr = 0;
6605b730 2130
ff43da86
FL		 2131 if (fep->bufdesc_ex) {
2132 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
96d2222b 2133 ebdp->cbd_esc = BD_ENET_TX_INT;
ff43da86
FL		 2134 }
2135
36e24e2e 2136 bdp = fec_enet_get_nextdesc(bdp, fep);
f0b3fbea
SH		 2137 }
2138
2139 /* Set the last buffer to wrap. */
36e24e2e 2140 bdp = fec_enet_get_prevdesc(bdp, fep);
f0b3fbea
SH		 2141 bdp->cbd_sc |= BD_SC_WRAP;
2142
2143 return 0;
ffdce2cc
RK		 2144
2145 err_alloc:
2146 fec_enet_free_buffers(ndev);
2147 return -ENOMEM;
f0b3fbea
SH		 2148}
2149
1da177e4 2150static int
c556167f 2151fec_enet_open(struct net_device *ndev)
1da177e4 2152{
c556167f 2153 struct fec_enet_private *fep = netdev_priv(ndev);
f0b3fbea 2154 int ret;
1da177e4 2155
5bbde4d2 2156 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5
NA		 2157 ret = fec_enet_clk_enable(ndev, true);
2158 if (ret)
2159 return ret;
2160
1da177e4
LT		 2161 /* I should reset the ring buffers here, but I don't yet know
2162 * a simple way to do that.
2163 */
1da177e4 2164
c556167f 2165 ret = fec_enet_alloc_buffers(ndev);
f0b3fbea
SH		 2166 if (ret)
2167 return ret;
2168
418bd0d4 2169 /* Probe and connect to PHY when open the interface */
c556167f 2170 ret = fec_enet_mii_probe(ndev);
418bd0d4 2171 if (ret) {
c556167f 2172 fec_enet_free_buffers(ndev);
418bd0d4
BW		 2173 return ret;
2174 }
ce5eaf02 2175
ef83337d 2176 fec_restart(ndev);
ce5eaf02 2177 napi_enable(&fep->napi);
e6b043d5 2178 phy_start(fep->phy_dev);
c556167f 2179 netif_start_queue(ndev);
22f6b860 2180 return 0;
1da177e4
LT		 2181}
2182
2183static int
c556167f 2184fec_enet_close(struct net_device *ndev)
1da177e4 2185{
c556167f 2186 struct fec_enet_private *fep = netdev_priv(ndev);
1da177e4 2187
d76cfae9
RK		 2188 phy_stop(fep->phy_dev);
2189
31a6de34
RK		 2190 if (netif_device_present(ndev)) {
2191 napi_disable(&fep->napi);
2192 netif_tx_disable(ndev);
8bbbd3c1 2193 fec_stop(ndev);
31a6de34 2194 }
1da177e4 2195
635cf17c 2196 phy_disconnect(fep->phy_dev);
0b146ca8 2197 fep->phy_dev = NULL;
418bd0d4 2198
e8fcfcd5 2199 fec_enet_clk_enable(ndev, false);
5bbde4d2 2200 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
db8880bc 2201 fec_enet_free_buffers(ndev);
f0b3fbea 2202
1da177e4
LT		 2203 return 0;
2204}
2205
1da177e4
LT		 2206/* Set or clear the multicast filter for this adaptor.
2207 * Skeleton taken from sunlance driver.
2208 * The CPM Ethernet implementation allows Multicast as well as individual
2209 * MAC address filtering. Some of the drivers check to make sure it is
2210 * a group multicast address, and discard those that are not. I guess I
2211 * will do the same for now, but just remove the test if you want
2212 * individual filtering as well (do the upper net layers want or support
2213 * this kind of feature?).
2214 */
2215
2216#define HASH_BITS 6 /* #bits in hash */
2217#define CRC32_POLY 0xEDB88320
2218
c556167f 2219static void set_multicast_list(struct net_device *ndev)
1da177e4 2220{
c556167f 2221 struct fec_enet_private *fep = netdev_priv(ndev);
22bedad3 2222 struct netdev_hw_addr *ha;
48e2f183 2223 unsigned int i, bit, data, crc, tmp;
1da177e4
LT		 2224 unsigned char hash;
2225
c556167f 2226 if (ndev->flags & IFF_PROMISC) {
f44d6305
SH		 2227 tmp = readl(fep->hwp + FEC_R_CNTRL);
2228 tmp |= 0x8;
2229 writel(tmp, fep->hwp + FEC_R_CNTRL);
4e831836
SH		 2230 return;
2231 }
1da177e4 2232
4e831836
SH		 2233 tmp = readl(fep->hwp + FEC_R_CNTRL);
2234 tmp &= ~0x8;
2235 writel(tmp, fep->hwp + FEC_R_CNTRL);
2236
c556167f 2237 if (ndev->flags & IFF_ALLMULTI) {
4e831836
SH		 2238 /* Catch all multicast addresses, so set the
2239 * filter to all 1's
2240 */
2241 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2242 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2243
2244 return;
2245 }
2246
2247 /* Clear filter and add the addresses in hash register
2248 */
2249 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2250 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2251
c556167f 2252 netdev_for_each_mc_addr(ha, ndev) {
4e831836
SH		 2253 /* calculate crc32 value of mac address */
2254 crc = 0xffffffff;
2255
c556167f 2256 for (i = 0; i < ndev->addr_len; i++) {
22bedad3 2257 data = ha->addr[i];
4e831836
SH		 2258 for (bit = 0; bit < 8; bit++, data >>= 1) {
2259 crc = (crc >> 1) ^
2260 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1da177e4
LT		 2261 }
2262 }
4e831836
SH		 2263
2264 /* only upper 6 bits (HASH_BITS) are used
2265 * which point to specific bit in he hash registers
2266 */
2267 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2268
2269 if (hash > 31) {
2270 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2271 tmp |= 1 << (hash - 32);
2272 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2273 } else {
2274 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2275 tmp |= 1 << hash;
2276 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2277 }
1da177e4
LT		 2278 }
2279}
2280
22f6b860 2281/* Set a MAC change in hardware. */
009fda83 2282static int
c556167f 2283fec_set_mac_address(struct net_device *ndev, void *p)
1da177e4 2284{
c556167f 2285 struct fec_enet_private *fep = netdev_priv(ndev);
009fda83
SH		 2286 struct sockaddr *addr = p;
2287
44934fac
LS		 2288 if (addr) {
2289 if (!is_valid_ether_addr(addr->sa_data))
2290 return -EADDRNOTAVAIL;
2291 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2292 }
1da177e4 2293
c556167f
UKK		 2294 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2295 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
f44d6305 2296 fep->hwp + FEC_ADDR_LOW);
c556167f 2297 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
7cff0943 2298 fep->hwp + FEC_ADDR_HIGH);
009fda83 2299 return 0;
1da177e4
LT		 2300}
2301
7f5c6add 2302#ifdef CONFIG_NET_POLL_CONTROLLER
49ce9c2c
BH		 2303/**
2304 * fec_poll_controller - FEC Poll controller function
7f5c6add
XJ		 2305 * @dev: The FEC network adapter
2306 *
2307 * Polled functionality used by netconsole and others in non interrupt mode
2308 *
2309 */
47a5247f 2310static void fec_poll_controller(struct net_device *dev)
7f5c6add
XJ		 2311{
2312 int i;
2313 struct fec_enet_private *fep = netdev_priv(dev);
2314
2315 for (i = 0; i < FEC_IRQ_NUM; i++) {
2316 if (fep->irq[i] > 0) {
2317 disable_irq(fep->irq[i]);
2318 fec_enet_interrupt(fep->irq[i], dev);
2319 enable_irq(fep->irq[i]);
2320 }
2321 }
2322}
2323#endif
2324
8506fa1d
RK		 2325#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2326
4c09eed9
JB		 2327static int fec_set_features(struct net_device *netdev,
2328 netdev_features_t features)
2329{
2330 struct fec_enet_private *fep = netdev_priv(netdev);
2331 netdev_features_t changed = features ^ netdev->features;
2332
8506fa1d
RK		 2333 /* Quiesce the device if necessary */
2334 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2335 napi_disable(&fep->napi);
2336 netif_tx_lock_bh(netdev);
2337 fec_stop(netdev);
2338 }
2339
4c09eed9
JB		 2340 netdev->features = features;
2341
2342 /* Receive checksum has been changed */
2343 if (changed & NETIF_F_RXCSUM) {
2344 if (features & NETIF_F_RXCSUM)
2345 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2346 else
2347 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
8506fa1d 2348 }
4c09eed9 2349
8506fa1d
RK		 2350 /* Resume the device after updates */
2351 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
ef83337d 2352 fec_restart(netdev);
8506fa1d
RK		 2353 netif_wake_queue(netdev);
2354 netif_tx_unlock_bh(netdev);
2355 napi_enable(&fep->napi);
4c09eed9
JB		 2356 }
2357
2358 return 0;
2359}
2360
009fda83
SH		 2361static const struct net_device_ops fec_netdev_ops = {
2362 .ndo_open = fec_enet_open,
2363 .ndo_stop = fec_enet_close,
2364 .ndo_start_xmit = fec_enet_start_xmit,
afc4b13d 2365 .ndo_set_rx_mode = set_multicast_list,
635ecaa7 2366 .ndo_change_mtu = eth_change_mtu,
009fda83
SH		 2367 .ndo_validate_addr = eth_validate_addr,
2368 .ndo_tx_timeout = fec_timeout,
2369 .ndo_set_mac_address = fec_set_mac_address,
db8880bc 2370 .ndo_do_ioctl = fec_enet_ioctl,
7f5c6add
XJ		 2371#ifdef CONFIG_NET_POLL_CONTROLLER
2372 .ndo_poll_controller = fec_poll_controller,
2373#endif
4c09eed9 2374 .ndo_set_features = fec_set_features,
009fda83
SH		 2375};
2376
1da177e4
LT		 2377 /*
2378 * XXX: We need to clean up on failure exits here.
ead73183 2379 *
1da177e4 2380 */
c556167f 2381static int fec_enet_init(struct net_device *ndev)
1da177e4 2382{
c556167f 2383 struct fec_enet_private *fep = netdev_priv(ndev);
48496255
SG		 2384 const struct platform_device_id *id_entry =
2385 platform_get_device_id(fep->pdev);
f0b3fbea 2386 struct bufdesc *cbd_base;
55d0218a
NA		 2387 int bd_size;
2388
2389 /* init the tx & rx ring size */
2390 fep->tx_ring_size = TX_RING_SIZE;
2391 fep->rx_ring_size = RX_RING_SIZE;
2392
79f33912
NA		 2393 fep->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2394 fep->tx_wake_threshold = (fep->tx_ring_size - fep->tx_stop_threshold) / 2;
2395
55d0218a
NA		 2396 if (fep->bufdesc_ex)
2397 fep->bufdesc_size = sizeof(struct bufdesc_ex);
2398 else
2399 fep->bufdesc_size = sizeof(struct bufdesc);
2400 bd_size = (fep->tx_ring_size + fep->rx_ring_size) *
2401 fep->bufdesc_size;
1da177e4 2402
8d4dd5cf 2403 /* Allocate memory for buffer descriptors. */
55d0218a 2404 cbd_base = dma_alloc_coherent(NULL, bd_size, &fep->bd_dma,
d0320f75
JP		 2405 GFP_KERNEL);
2406 if (!cbd_base)
562d2f8c 2407 return -ENOMEM;
562d2f8c 2408
79f33912
NA		 2409 fep->tso_hdrs = dma_alloc_coherent(NULL, fep->tx_ring_size * TSO_HEADER_SIZE,
2410 &fep->tso_hdrs_dma, GFP_KERNEL);
2411 if (!fep->tso_hdrs) {
2412 dma_free_coherent(NULL, bd_size, cbd_base, fep->bd_dma);
2413 return -ENOMEM;
2414 }
2415
14109a59 2416 memset(cbd_base, 0, PAGE_SIZE);
3b2b74ca 2417
c556167f 2418 fep->netdev = ndev;
1da177e4 2419
49da97dc 2420 /* Get the Ethernet address */
c556167f 2421 fec_get_mac(ndev);
44934fac
LS		 2422 /* make sure MAC we just acquired is programmed into the hw */
2423 fec_set_mac_address(ndev, NULL);
1da177e4 2424
8d4dd5cf 2425 /* Set receive and transmit descriptor base. */
1da177e4 2426 fep->rx_bd_base = cbd_base;
55d0218a 2427 if (fep->bufdesc_ex)
ff43da86 2428 fep->tx_bd_base = (struct bufdesc *)
36e24e2e 2429 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
55d0218a 2430 else
36e24e2e 2431 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
1da177e4 2432
22f6b860 2433 /* The FEC Ethernet specific entries in the device structure */
c556167f
UKK		 2434 ndev->watchdog_timeo = TX_TIMEOUT;
2435 ndev->netdev_ops = &fec_netdev_ops;
2436 ndev->ethtool_ops = &fec_enet_ethtool_ops;
633e7533 2437
dc975382 2438 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
322555f5 2439 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
dc975382 2440
09d1e541 2441 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
cdffcf1b
JB		 2442 /* enable hw VLAN support */
2443 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
cdffcf1b 2444
48496255 2445 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
79f33912
NA		 2446 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
2447
48496255
SG		 2448 /* enable hw accelerator */
2449 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
79f33912 2450 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
48496255
SG		 2451 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2452 }
4c09eed9 2453
09d1e541
NA		 2454 ndev->hw_features = ndev->features;
2455
ef83337d 2456 fec_restart(ndev);
1da177e4 2457
1da177e4
LT		 2458 return 0;
2459}
2460
ca2cc333 2461#ifdef CONFIG_OF
33897cc8 2462static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2463{
2464 int err, phy_reset;
a3caad0a 2465 int msec = 1;
ca2cc333
SG		 2466 struct device_node *np = pdev->dev.of_node;
2467
2468 if (!np)
a9b2c8ef 2469 return;
ca2cc333 2470
a3caad0a
SG		 2471 of_property_read_u32(np, "phy-reset-duration", &msec);
2472 /* A sane reset duration should not be longer than 1s */
2473 if (msec > 1000)
2474 msec = 1;
2475
ca2cc333 2476 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
07dcf8e9
FE		 2477 if (!gpio_is_valid(phy_reset))
2478 return;
2479
119fc007
SG		 2480 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2481 GPIOF_OUT_INIT_LOW, "phy-reset");
ca2cc333 2482 if (err) {
07dcf8e9 2483 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
a9b2c8ef 2484 return;
ca2cc333 2485 }
a3caad0a 2486 msleep(msec);
ca2cc333 2487 gpio_set_value(phy_reset, 1);
ca2cc333
SG		 2488}
2489#else /* CONFIG_OF */
0c7768a0 2490static void fec_reset_phy(struct platform_device *pdev)
ca2cc333
SG		 2491{
2492 /*
2493 * In case of platform probe, the reset has been done
2494 * by machine code.
2495 */
ca2cc333
SG		 2496}
2497#endif /* CONFIG_OF */
2498
33897cc8 2499static int
ead73183
SH		 2500fec_probe(struct platform_device *pdev)
2501{
2502 struct fec_enet_private *fep;
5eb32bd0 2503 struct fec_platform_data *pdata;
ead73183
SH		 2504 struct net_device *ndev;
2505 int i, irq, ret = 0;
2506 struct resource *r;
ca2cc333 2507 const struct of_device_id *of_id;
43af940c 2508 static int dev_id;
ca2cc333
SG		 2509
2510 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2511 if (of_id)
2512 pdev->id_entry = of_id->data;
ead73183 2513
ead73183
SH		 2514 /* Init network device */
2515 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
83e519b6
FE		 2516 if (!ndev)
2517 return -ENOMEM;
ead73183
SH		 2518
2519 SET_NETDEV_DEV(ndev, &pdev->dev);
2520
2521 /* setup board info structure */
2522 fep = netdev_priv(ndev);
ead73183 2523
d1391930 2524#if !defined(CONFIG_M5272)
baa70a5c
FL		 2525 /* default enable pause frame auto negotiation */
2526 if (pdev->id_entry &&
2527 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2528 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
d1391930 2529#endif
baa70a5c 2530
5bbde4d2
NA		 2531 /* Select default pin state */
2532 pinctrl_pm_select_default_state(&pdev->dev);
2533
399db75b 2534 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
941e173a
TB		 2535 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2536 if (IS_ERR(fep->hwp)) {
2537 ret = PTR_ERR(fep->hwp);
2538 goto failed_ioremap;
2539 }
2540
e6b043d5 2541 fep->pdev = pdev;
43af940c 2542 fep->dev_id = dev_id++;
ead73183 2543
ff43da86
FL		 2544 fep->bufdesc_ex = 0;
2545
ead73183
SH		 2546 platform_set_drvdata(pdev, ndev);
2547
6c5f7808 2548 ret = of_get_phy_mode(pdev->dev.of_node);
ca2cc333 2549 if (ret < 0) {
94660ba0 2550 pdata = dev_get_platdata(&pdev->dev);
ca2cc333
SG		 2551 if (pdata)
2552 fep->phy_interface = pdata->phy;
2553 else
2554 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2555 } else {
2556 fep->phy_interface = ret;
2557 }
2558
f4d40de3
SH		 2559 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2560 if (IS_ERR(fep->clk_ipg)) {
2561 ret = PTR_ERR(fep->clk_ipg);
ead73183
SH		 2562 goto failed_clk;
2563 }
f4d40de3
SH		 2564
2565 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2566 if (IS_ERR(fep->clk_ahb)) {
2567 ret = PTR_ERR(fep->clk_ahb);
2568 goto failed_clk;
2569 }
2570
daa7d392
WS		 2571 /* enet_out is optional, depends on board */
2572 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2573 if (IS_ERR(fep->clk_enet_out))
2574 fep->clk_enet_out = NULL;
2575
6605b730 2576 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
e2f8d555
FE		 2577 fep->bufdesc_ex =
2578 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
6605b730 2579 if (IS_ERR(fep->clk_ptp)) {
c29dc2d7 2580 fep->clk_ptp = NULL;
ff43da86 2581 fep->bufdesc_ex = 0;
6605b730 2582 }
6605b730 2583
e8fcfcd5 2584 ret = fec_enet_clk_enable(ndev, true);
13a097bd
FE		 2585 if (ret)
2586 goto failed_clk;
2587
f4e9f3d2
FE		 2588 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2589 if (!IS_ERR(fep->reg_phy)) {
2590 ret = regulator_enable(fep->reg_phy);
5fa9c0fe
SG		 2591 if (ret) {
2592 dev_err(&pdev->dev,
2593 "Failed to enable phy regulator: %d\n", ret);
2594 goto failed_regulator;
2595 }
f6a4d607
FE		 2596 } else {
2597 fep->reg_phy = NULL;
5fa9c0fe
SG		 2598 }
2599
2ca9b2aa
SG		 2600 fec_reset_phy(pdev);
2601
e2f8d555 2602 if (fep->bufdesc_ex)
ca162a82 2603 fec_ptp_init(pdev);
e2f8d555
FE		 2604
2605 ret = fec_enet_init(ndev);
2606 if (ret)
2607 goto failed_init;
2608
2609 for (i = 0; i < FEC_IRQ_NUM; i++) {
2610 irq = platform_get_irq(pdev, i);
2611 if (irq < 0) {
2612 if (i)
2613 break;
2614 ret = irq;
2615 goto failed_irq;
2616 }
0d9b2ab1 2617 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
44a272dd 2618 0, pdev->name, ndev);
0d9b2ab1 2619 if (ret)
e2f8d555 2620 goto failed_irq;
e2f8d555
FE		 2621 }
2622
e6b043d5
BW		 2623 ret = fec_enet_mii_init(pdev);
2624 if (ret)
2625 goto failed_mii_init;
2626
03c698c9
OS		 2627 /* Carrier starts down, phylib will bring it up */
2628 netif_carrier_off(ndev);
e8fcfcd5 2629 fec_enet_clk_enable(ndev, false);
5bbde4d2 2630 pinctrl_pm_select_sleep_state(&pdev->dev);
03c698c9 2631
ead73183
SH		 2632 ret = register_netdev(ndev);
2633 if (ret)
2634 goto failed_register;
2635
eb1d0640
FE		 2636 if (fep->bufdesc_ex && fep->ptp_clock)
2637 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2638
36cdc743 2639 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
ead73183
SH		 2640 return 0;
2641
2642failed_register:
e6b043d5
BW		 2643 fec_enet_mii_remove(fep);
2644failed_mii_init:
7a2bbd8d 2645failed_irq:
7a2bbd8d 2646failed_init:
f6a4d607
FE		 2647 if (fep->reg_phy)
2648 regulator_disable(fep->reg_phy);
5fa9c0fe 2649failed_regulator:
e8fcfcd5 2650 fec_enet_clk_enable(ndev, false);
ead73183 2651failed_clk:
ead73183
SH		 2652failed_ioremap:
2653 free_netdev(ndev);
2654
2655 return ret;
2656}
2657
33897cc8 2658static int
ead73183
SH		 2659fec_drv_remove(struct platform_device *pdev)
2660{
2661 struct net_device *ndev = platform_get_drvdata(pdev);
2662 struct fec_enet_private *fep = netdev_priv(ndev);
2663
36cdc743 2664 cancel_work_sync(&fep->tx_timeout_work);
e163cc97 2665 unregister_netdev(ndev);
e6b043d5 2666 fec_enet_mii_remove(fep);
6605b730 2667 del_timer_sync(&fep->time_keep);
f6a4d607
FE		 2668 if (fep->reg_phy)
2669 regulator_disable(fep->reg_phy);
6605b730
FL		 2670 if (fep->ptp_clock)
2671 ptp_clock_unregister(fep->ptp_clock);
e8fcfcd5 2672 fec_enet_clk_enable(ndev, false);
ead73183 2673 free_netdev(ndev);
28e2188e 2674
ead73183
SH		 2675 return 0;
2676}
2677
bf7bfd7f 2678#ifdef CONFIG_PM_SLEEP
ead73183 2679static int
87cad5c3 2680fec_suspend(struct device *dev)
ead73183 2681{
87cad5c3 2682 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2683 struct fec_enet_private *fep = netdev_priv(ndev);
ead73183 2684
da1774e5 2685 rtnl_lock();
04e5216d 2686 if (netif_running(ndev)) {
d76cfae9 2687 phy_stop(fep->phy_dev);
31a6de34
RK		 2688 napi_disable(&fep->napi);
2689 netif_tx_lock_bh(ndev);
04e5216d 2690 netif_device_detach(ndev);
31a6de34
RK		 2691 netif_tx_unlock_bh(ndev);
2692 fec_stop(ndev);
ead73183 2693 }
da1774e5
RK		 2694 rtnl_unlock();
2695
e8fcfcd5 2696 fec_enet_clk_enable(ndev, false);
5bbde4d2 2697 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
04e5216d 2698
238f7bc7
FE		 2699 if (fep->reg_phy)
2700 regulator_disable(fep->reg_phy);
2701
ead73183
SH		 2702 return 0;
2703}
2704
2705static int
87cad5c3 2706fec_resume(struct device *dev)
ead73183 2707{
87cad5c3 2708 struct net_device *ndev = dev_get_drvdata(dev);
04e5216d 2709 struct fec_enet_private *fep = netdev_priv(ndev);
238f7bc7
FE		 2710 int ret;
2711
2712 if (fep->reg_phy) {
2713 ret = regulator_enable(fep->reg_phy);
2714 if (ret)
2715 return ret;
2716 }
ead73183 2717
5bbde4d2 2718 pinctrl_pm_select_default_state(&fep->pdev->dev);
e8fcfcd5 2719 ret = fec_enet_clk_enable(ndev, true);
13a097bd 2720 if (ret)
e8fcfcd5 2721 goto failed_clk;
13a097bd 2722
da1774e5 2723 rtnl_lock();
04e5216d 2724 if (netif_running(ndev)) {
ef83337d 2725 fec_restart(ndev);
31a6de34 2726 netif_tx_lock_bh(ndev);
6af42d42 2727 netif_device_attach(ndev);
dbc64a8e 2728 netif_tx_unlock_bh(ndev);
6af42d42 2729 napi_enable(&fep->napi);
d76cfae9 2730 phy_start(fep->phy_dev);
ead73183 2731 }
da1774e5 2732 rtnl_unlock();
04e5216d 2733
ead73183 2734 return 0;
13a097bd 2735
e8fcfcd5 2736failed_clk:
13a097bd
FE		 2737 if (fep->reg_phy)
2738 regulator_disable(fep->reg_phy);
2739 return ret;
ead73183 2740}
bf7bfd7f 2741#endif /* CONFIG_PM_SLEEP */
ead73183 2742
bf7bfd7f 2743static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
59d4289b 2744
ead73183
SH		 2745static struct platform_driver fec_driver = {
2746 .driver = {
b5680e0b 2747 .name = DRIVER_NAME,
87cad5c3 2748 .owner = THIS_MODULE,
87cad5c3 2749 .pm = &fec_pm_ops,
ca2cc333 2750 .of_match_table = fec_dt_ids,
ead73183 2751 },
b5680e0b 2752 .id_table = fec_devtype,
87cad5c3 2753 .probe = fec_probe,
33897cc8 2754 .remove = fec_drv_remove,
ead73183
SH		 2755};
2756
aaca2377 2757module_platform_driver(fec_driver);
1da177e4 2758
f8c0aca9 2759MODULE_ALIAS("platform:"DRIVER_NAME);
1da177e4 2760MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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