Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
7dd6a2aa | 5 | * Right now, I am very wasteful with the buffers. I allocate memory |
1da177e4 LT |
6 | * pages and then divide them into 2K frame buffers. This way I know I |
7 | * have buffers large enough to hold one frame within one buffer descriptor. | |
8 | * Once I get this working, I will use 64 or 128 byte CPM buffers, which | |
9 | * will be much more memory efficient and will easily handle lots of | |
10 | * small packets. | |
11 | * | |
12 | * Much better multiple PHY support by Magnus Damm. | |
13 | * Copyright (c) 2000 Ericsson Radio Systems AB. | |
14 | * | |
562d2f8c GU |
15 | * Support for FEC controller of ColdFire processors. |
16 | * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) | |
7dd6a2aa GU |
17 | * |
18 | * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) | |
677177c5 | 19 | * Copyright (c) 2004-2006 Macq Electronique SA. |
b5680e0b | 20 | * |
230dec61 | 21 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
1da177e4 LT |
22 | */ |
23 | ||
1da177e4 LT |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/errno.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/slab.h> | |
31 | #include <linux/interrupt.h> | |
1da177e4 LT |
32 | #include <linux/init.h> |
33 | #include <linux/delay.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/skbuff.h> | |
4c09eed9 JB |
37 | #include <linux/in.h> |
38 | #include <linux/ip.h> | |
39 | #include <net/ip.h> | |
40 | #include <linux/tcp.h> | |
41 | #include <linux/udp.h> | |
42 | #include <linux/icmp.h> | |
1da177e4 LT |
43 | #include <linux/spinlock.h> |
44 | #include <linux/workqueue.h> | |
45 | #include <linux/bitops.h> | |
6f501b17 SH |
46 | #include <linux/io.h> |
47 | #include <linux/irq.h> | |
196719ec | 48 | #include <linux/clk.h> |
ead73183 | 49 | #include <linux/platform_device.h> |
e6b043d5 | 50 | #include <linux/phy.h> |
5eb32bd0 | 51 | #include <linux/fec.h> |
ca2cc333 SG |
52 | #include <linux/of.h> |
53 | #include <linux/of_device.h> | |
54 | #include <linux/of_gpio.h> | |
55 | #include <linux/of_net.h> | |
5fa9c0fe | 56 | #include <linux/regulator/consumer.h> |
cdffcf1b | 57 | #include <linux/if_vlan.h> |
1da177e4 | 58 | |
080853af | 59 | #include <asm/cacheflush.h> |
196719ec | 60 | |
1da177e4 | 61 | #include "fec.h" |
1da177e4 | 62 | |
772e42b0 CM |
63 | static void set_multicast_list(struct net_device *ndev); |
64 | ||
085e79ed | 65 | #if defined(CONFIG_ARM) |
196719ec SH |
66 | #define FEC_ALIGNMENT 0xf |
67 | #else | |
68 | #define FEC_ALIGNMENT 0x3 | |
69 | #endif | |
70 | ||
b5680e0b | 71 | #define DRIVER_NAME "fec" |
dc975382 | 72 | #define FEC_NAPI_WEIGHT 64 |
b5680e0b | 73 | |
baa70a5c FL |
74 | /* Pause frame feild and FIFO threshold */ |
75 | #define FEC_ENET_FCE (1 << 5) | |
76 | #define FEC_ENET_RSEM_V 0x84 | |
77 | #define FEC_ENET_RSFL_V 16 | |
78 | #define FEC_ENET_RAEM_V 0x8 | |
79 | #define FEC_ENET_RAFL_V 0x8 | |
80 | #define FEC_ENET_OPD_V 0xFFF0 | |
81 | ||
b5680e0b SG |
82 | /* Controller is ENET-MAC */ |
83 | #define FEC_QUIRK_ENET_MAC (1 << 0) | |
84 | /* Controller needs driver to swap frame */ | |
85 | #define FEC_QUIRK_SWAP_FRAME (1 << 1) | |
0ca1e290 SG |
86 | /* Controller uses gasket */ |
87 | #define FEC_QUIRK_USE_GASKET (1 << 2) | |
230dec61 SG |
88 | /* Controller has GBIT support */ |
89 | #define FEC_QUIRK_HAS_GBIT (1 << 3) | |
ff43da86 FL |
90 | /* Controller has extend desc buffer */ |
91 | #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) | |
48496255 SG |
92 | /* Controller has hardware checksum support */ |
93 | #define FEC_QUIRK_HAS_CSUM (1 << 5) | |
cdffcf1b JB |
94 | /* Controller has hardware vlan support */ |
95 | #define FEC_QUIRK_HAS_VLAN (1 << 6) | |
03191656 FL |
96 | /* ENET IP errata ERR006358 |
97 | * | |
98 | * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously | |
99 | * detected as not set during a prior frame transmission, then the | |
100 | * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs | |
101 | * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in | |
102 | * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously | |
103 | * detected as not set during a prior frame transmission, then the | |
104 | * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs | |
105 | * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in | |
106 | * frames not being transmitted until there is a 0-to-1 transition on | |
107 | * ENET_TDAR[TDAR]. | |
108 | */ | |
109 | #define FEC_QUIRK_ERR006358 (1 << 7) | |
b5680e0b SG |
110 | |
111 | static struct platform_device_id fec_devtype[] = { | |
112 | { | |
0ca1e290 | 113 | /* keep it for coldfire */ |
b5680e0b SG |
114 | .name = DRIVER_NAME, |
115 | .driver_data = 0, | |
0ca1e290 SG |
116 | }, { |
117 | .name = "imx25-fec", | |
118 | .driver_data = FEC_QUIRK_USE_GASKET, | |
119 | }, { | |
120 | .name = "imx27-fec", | |
121 | .driver_data = 0, | |
b5680e0b SG |
122 | }, { |
123 | .name = "imx28-fec", | |
124 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, | |
230dec61 SG |
125 | }, { |
126 | .name = "imx6q-fec", | |
ff43da86 | 127 | .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | |
cdffcf1b | 128 | FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM | |
03191656 | 129 | FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358, |
ca7c4a45 | 130 | }, { |
36803542 | 131 | .name = "mvf600-fec", |
ca7c4a45 | 132 | .driver_data = FEC_QUIRK_ENET_MAC, |
0ca1e290 SG |
133 | }, { |
134 | /* sentinel */ | |
135 | } | |
b5680e0b | 136 | }; |
0ca1e290 | 137 | MODULE_DEVICE_TABLE(platform, fec_devtype); |
b5680e0b | 138 | |
ca2cc333 | 139 | enum imx_fec_type { |
a7dd3219 | 140 | IMX25_FEC = 1, /* runs on i.mx25/50/53 */ |
ca2cc333 SG |
141 | IMX27_FEC, /* runs on i.mx27/35/51 */ |
142 | IMX28_FEC, | |
230dec61 | 143 | IMX6Q_FEC, |
36803542 | 144 | MVF600_FEC, |
ca2cc333 SG |
145 | }; |
146 | ||
147 | static const struct of_device_id fec_dt_ids[] = { | |
148 | { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], }, | |
149 | { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], }, | |
150 | { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], }, | |
230dec61 | 151 | { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], }, |
36803542 | 152 | { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], }, |
ca2cc333 SG |
153 | { /* sentinel */ } |
154 | }; | |
155 | MODULE_DEVICE_TABLE(of, fec_dt_ids); | |
156 | ||
49da97dc SG |
157 | static unsigned char macaddr[ETH_ALEN]; |
158 | module_param_array(macaddr, byte, NULL, 0); | |
159 | MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); | |
1da177e4 | 160 | |
49da97dc | 161 | #if defined(CONFIG_M5272) |
1da177e4 LT |
162 | /* |
163 | * Some hardware gets it MAC address out of local flash memory. | |
164 | * if this is non-zero then assume it is the address to get MAC from. | |
165 | */ | |
166 | #if defined(CONFIG_NETtel) | |
167 | #define FEC_FLASHMAC 0xf0006006 | |
168 | #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) | |
169 | #define FEC_FLASHMAC 0xf0006000 | |
1da177e4 LT |
170 | #elif defined(CONFIG_CANCam) |
171 | #define FEC_FLASHMAC 0xf0020000 | |
7dd6a2aa GU |
172 | #elif defined (CONFIG_M5272C3) |
173 | #define FEC_FLASHMAC (0xffe04000 + 4) | |
174 | #elif defined(CONFIG_MOD5272) | |
a7dd3219 | 175 | #define FEC_FLASHMAC 0xffc0406b |
1da177e4 LT |
176 | #else |
177 | #define FEC_FLASHMAC 0 | |
178 | #endif | |
43be6366 | 179 | #endif /* CONFIG_M5272 */ |
ead73183 | 180 | |
ff43da86 | 181 | #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE) |
6b265293 | 182 | #error "FEC: descriptor ring size constants too large" |
562d2f8c GU |
183 | #endif |
184 | ||
22f6b860 | 185 | /* Interrupt events/masks. */ |
1da177e4 LT |
186 | #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ |
187 | #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ | |
188 | #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ | |
189 | #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ | |
190 | #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ | |
191 | #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ | |
192 | #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ | |
193 | #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ | |
194 | #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ | |
195 | #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ | |
196 | ||
4bee1f9a | 197 | #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) |
dc975382 | 198 | #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) |
4bee1f9a | 199 | |
cdffcf1b | 200 | /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets. |
1da177e4 | 201 | */ |
cdffcf1b | 202 | #define PKT_MAXBUF_SIZE 1522 |
1da177e4 | 203 | #define PKT_MINBUF_SIZE 64 |
cdffcf1b | 204 | #define PKT_MAXBLR_SIZE 1536 |
1da177e4 | 205 | |
4c09eed9 JB |
206 | /* FEC receive acceleration */ |
207 | #define FEC_RACC_IPDIS (1 << 1) | |
208 | #define FEC_RACC_PRODIS (1 << 2) | |
209 | #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS) | |
210 | ||
1da177e4 | 211 | /* |
6b265293 | 212 | * The 5270/5271/5280/5282/532x RX control register also contains maximum frame |
1da177e4 LT |
213 | * size bits. Other FEC hardware does not, so we need to take that into |
214 | * account when setting it. | |
215 | */ | |
562d2f8c | 216 | #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ |
085e79ed | 217 | defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) |
1da177e4 LT |
218 | #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) |
219 | #else | |
220 | #define OPT_FRAME_SIZE 0 | |
221 | #endif | |
222 | ||
e6b043d5 BW |
223 | /* FEC MII MMFR bits definition */ |
224 | #define FEC_MMFR_ST (1 << 30) | |
225 | #define FEC_MMFR_OP_READ (2 << 28) | |
226 | #define FEC_MMFR_OP_WRITE (1 << 28) | |
227 | #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) | |
228 | #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) | |
229 | #define FEC_MMFR_TA (2 << 16) | |
230 | #define FEC_MMFR_DATA(v) (v & 0xffff) | |
1da177e4 | 231 | |
c3b084c2 | 232 | #define FEC_MII_TIMEOUT 30000 /* us */ |
1da177e4 | 233 | |
22f6b860 SH |
234 | /* Transmitter timeout */ |
235 | #define TX_TIMEOUT (2 * HZ) | |
1da177e4 | 236 | |
baa70a5c FL |
237 | #define FEC_PAUSE_FLAG_AUTONEG 0x1 |
238 | #define FEC_PAUSE_FLAG_ENABLE 0x2 | |
239 | ||
e163cc97 LW |
240 | static int mii_cnt; |
241 | ||
ff43da86 FL |
242 | static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex) |
243 | { | |
244 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
245 | if (is_ex) | |
246 | return (struct bufdesc *)(ex + 1); | |
247 | else | |
248 | return bdp + 1; | |
249 | } | |
250 | ||
251 | static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex) | |
252 | { | |
253 | struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp; | |
254 | if (is_ex) | |
255 | return (struct bufdesc *)(ex - 1); | |
256 | else | |
257 | return bdp - 1; | |
258 | } | |
259 | ||
b5680e0b SG |
260 | static void *swap_buffer(void *bufaddr, int len) |
261 | { | |
262 | int i; | |
263 | unsigned int *buf = bufaddr; | |
264 | ||
ffed61e6 | 265 | for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++) |
b5680e0b SG |
266 | *buf = cpu_to_be32(*buf); |
267 | ||
268 | return bufaddr; | |
269 | } | |
270 | ||
4c09eed9 JB |
271 | static int |
272 | fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev) | |
273 | { | |
274 | /* Only run for packets requiring a checksum. */ | |
275 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
276 | return 0; | |
277 | ||
278 | if (unlikely(skb_cow_head(skb, 0))) | |
279 | return -1; | |
280 | ||
281 | *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0; | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
c7621cb3 | 286 | static netdev_tx_t |
c556167f | 287 | fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
1da177e4 | 288 | { |
c556167f | 289 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
290 | const struct platform_device_id *id_entry = |
291 | platform_get_device_id(fep->pdev); | |
03191656 | 292 | struct bufdesc *bdp, *bdp_pre; |
9555b31e | 293 | void *bufaddr; |
0e702ab3 | 294 | unsigned short status; |
de5fb0a0 | 295 | unsigned int index; |
1da177e4 | 296 | |
1da177e4 LT |
297 | /* Fill in a Tx ring entry */ |
298 | bdp = fep->cur_tx; | |
299 | ||
0e702ab3 | 300 | status = bdp->cbd_sc; |
22f6b860 | 301 | |
0e702ab3 | 302 | if (status & BD_ENET_TX_READY) { |
1da177e4 | 303 | /* Ooops. All transmit buffers are full. Bail out. |
c556167f | 304 | * This should not happen, since ndev->tbusy should be set. |
1da177e4 | 305 | */ |
31b7720c | 306 | netdev_err(ndev, "tx queue full!\n"); |
5b548140 | 307 | return NETDEV_TX_BUSY; |
1da177e4 | 308 | } |
1da177e4 | 309 | |
4c09eed9 JB |
310 | /* Protocol checksum off-load for TCP and UDP. */ |
311 | if (fec_enet_clear_csum(skb, ndev)) { | |
312 | kfree_skb(skb); | |
313 | return NETDEV_TX_OK; | |
314 | } | |
315 | ||
22f6b860 | 316 | /* Clear all of the status flags */ |
0e702ab3 | 317 | status &= ~BD_ENET_TX_STATS; |
1da177e4 | 318 | |
22f6b860 | 319 | /* Set buffer length and buffer pointer */ |
9555b31e | 320 | bufaddr = skb->data; |
1da177e4 LT |
321 | bdp->cbd_datlen = skb->len; |
322 | ||
323 | /* | |
22f6b860 SH |
324 | * On some FEC implementations data must be aligned on |
325 | * 4-byte boundaries. Use bounce buffers to copy data | |
326 | * and get it aligned. Ugh. | |
1da177e4 | 327 | */ |
de5fb0a0 FL |
328 | if (fep->bufdesc_ex) |
329 | index = (struct bufdesc_ex *)bdp - | |
330 | (struct bufdesc_ex *)fep->tx_bd_base; | |
331 | else | |
332 | index = bdp - fep->tx_bd_base; | |
333 | ||
9555b31e | 334 | if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { |
8a73b0bc | 335 | memcpy(fep->tx_bounce[index], skb->data, skb->len); |
9555b31e | 336 | bufaddr = fep->tx_bounce[index]; |
1da177e4 LT |
337 | } |
338 | ||
b5680e0b SG |
339 | /* |
340 | * Some design made an incorrect assumption on endian mode of | |
341 | * the system that it's running on. As the result, driver has to | |
342 | * swap every frame going to and coming from the controller. | |
343 | */ | |
344 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) | |
345 | swap_buffer(bufaddr, skb->len); | |
346 | ||
22f6b860 | 347 | /* Save skb pointer */ |
de5fb0a0 | 348 | fep->tx_skbuff[index] = skb; |
6aa20a22 | 349 | |
1da177e4 LT |
350 | /* Push the data cache so the CPM does not get stale memory |
351 | * data. | |
352 | */ | |
d1ab1f54 | 353 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr, |
f0b3fbea | 354 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); |
1da177e4 | 355 | |
0e702ab3 GU |
356 | /* Send it on its way. Tell FEC it's ready, interrupt when done, |
357 | * it's the last BD of the frame, and to put the CRC on the end. | |
1da177e4 | 358 | */ |
0e702ab3 | 359 | status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR |
1da177e4 | 360 | | BD_ENET_TX_LAST | BD_ENET_TX_TC); |
0e702ab3 | 361 | bdp->cbd_sc = status; |
1da177e4 | 362 | |
ff43da86 FL |
363 | if (fep->bufdesc_ex) { |
364 | ||
365 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
366 | ebdp->cbd_bdu = 0; | |
367 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && | |
6605b730 | 368 | fep->hwts_tx_en)) { |
ff43da86 | 369 | ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT); |
6605b730 | 370 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
ff43da86 | 371 | } else { |
ff43da86 | 372 | ebdp->cbd_esc = BD_ENET_TX_INT; |
4c09eed9 JB |
373 | |
374 | /* Enable protocol checksum flags | |
375 | * We do not bother with the IP Checksum bits as they | |
376 | * are done by the kernel | |
377 | */ | |
378 | if (skb->ip_summed == CHECKSUM_PARTIAL) | |
379 | ebdp->cbd_esc |= BD_ENET_TX_PINS; | |
ff43da86 | 380 | } |
6605b730 | 381 | } |
03191656 FL |
382 | |
383 | bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
384 | if ((id_entry->driver_data & FEC_QUIRK_ERR006358) && | |
385 | !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) { | |
386 | fep->delay_work.trig_tx = true; | |
387 | schedule_delayed_work(&(fep->delay_work.delay_work), | |
388 | msecs_to_jiffies(1)); | |
389 | } | |
390 | ||
22f6b860 SH |
391 | /* If this was the last BD in the ring, start at the beginning again. */ |
392 | if (status & BD_ENET_TX_WRAP) | |
1da177e4 | 393 | bdp = fep->tx_bd_base; |
22f6b860 | 394 | else |
ff43da86 | 395 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
1da177e4 | 396 | |
de5fb0a0 FL |
397 | fep->cur_tx = bdp; |
398 | ||
399 | if (fep->cur_tx == fep->dirty_tx) | |
c556167f | 400 | netif_stop_queue(ndev); |
1da177e4 | 401 | |
de5fb0a0 FL |
402 | /* Trigger transmission start */ |
403 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
1da177e4 | 404 | |
18a03b97 RC |
405 | skb_tx_timestamp(skb); |
406 | ||
6ed10654 | 407 | return NETDEV_TX_OK; |
1da177e4 LT |
408 | } |
409 | ||
14109a59 FL |
410 | /* Init RX & TX buffer descriptors |
411 | */ | |
412 | static void fec_enet_bd_init(struct net_device *dev) | |
413 | { | |
414 | struct fec_enet_private *fep = netdev_priv(dev); | |
415 | struct bufdesc *bdp; | |
416 | unsigned int i; | |
417 | ||
418 | /* Initialize the receive buffer descriptors. */ | |
419 | bdp = fep->rx_bd_base; | |
420 | for (i = 0; i < RX_RING_SIZE; i++) { | |
421 | ||
422 | /* Initialize the BD for every fragment in the page. */ | |
423 | if (bdp->cbd_bufaddr) | |
424 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
425 | else | |
426 | bdp->cbd_sc = 0; | |
427 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
428 | } | |
429 | ||
430 | /* Set the last buffer to wrap */ | |
431 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
432 | bdp->cbd_sc |= BD_SC_WRAP; | |
433 | ||
434 | fep->cur_rx = fep->rx_bd_base; | |
435 | ||
436 | /* ...and the same for transmit */ | |
437 | bdp = fep->tx_bd_base; | |
438 | fep->cur_tx = bdp; | |
439 | for (i = 0; i < TX_RING_SIZE; i++) { | |
440 | ||
441 | /* Initialize the BD for every fragment in the page. */ | |
442 | bdp->cbd_sc = 0; | |
443 | if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) { | |
444 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
445 | fep->tx_skbuff[i] = NULL; | |
446 | } | |
447 | bdp->cbd_bufaddr = 0; | |
448 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
449 | } | |
450 | ||
451 | /* Set the last buffer to wrap */ | |
452 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); | |
453 | bdp->cbd_sc |= BD_SC_WRAP; | |
454 | fep->dirty_tx = bdp; | |
455 | } | |
456 | ||
45993653 UKK |
457 | /* This function is called to start or restart the FEC during a link |
458 | * change. This only happens when switching between half and full | |
459 | * duplex. | |
460 | */ | |
1da177e4 | 461 | static void |
45993653 | 462 | fec_restart(struct net_device *ndev, int duplex) |
1da177e4 | 463 | { |
c556167f | 464 | struct fec_enet_private *fep = netdev_priv(ndev); |
45993653 UKK |
465 | const struct platform_device_id *id_entry = |
466 | platform_get_device_id(fep->pdev); | |
467 | int i; | |
4c09eed9 | 468 | u32 val; |
cd1f402c UKK |
469 | u32 temp_mac[2]; |
470 | u32 rcntl = OPT_FRAME_SIZE | 0x04; | |
230dec61 | 471 | u32 ecntl = 0x2; /* ETHEREN */ |
1da177e4 | 472 | |
54309fa6 FL |
473 | if (netif_running(ndev)) { |
474 | netif_device_detach(ndev); | |
475 | napi_disable(&fep->napi); | |
476 | netif_stop_queue(ndev); | |
31691344 | 477 | netif_tx_lock_bh(ndev); |
54309fa6 FL |
478 | } |
479 | ||
45993653 UKK |
480 | /* Whack a reset. We should wait for this. */ |
481 | writel(1, fep->hwp + FEC_ECNTRL); | |
482 | udelay(10); | |
1da177e4 | 483 | |
45993653 UKK |
484 | /* |
485 | * enet-mac reset will reset mac address registers too, | |
486 | * so need to reconfigure it. | |
487 | */ | |
488 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
489 | memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN); | |
490 | writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); | |
491 | writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); | |
492 | } | |
1da177e4 | 493 | |
45993653 UKK |
494 | /* Clear any outstanding interrupt. */ |
495 | writel(0xffc00000, fep->hwp + FEC_IEVENT); | |
1da177e4 | 496 | |
772e42b0 CM |
497 | /* Setup multicast filter. */ |
498 | set_multicast_list(ndev); | |
45993653 UKK |
499 | #ifndef CONFIG_M5272 |
500 | writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); | |
501 | writel(0, fep->hwp + FEC_HASH_TABLE_LOW); | |
502 | #endif | |
1da177e4 | 503 | |
45993653 UKK |
504 | /* Set maximum receive buffer size. */ |
505 | writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); | |
1da177e4 | 506 | |
14109a59 FL |
507 | fec_enet_bd_init(ndev); |
508 | ||
45993653 UKK |
509 | /* Set receive and transmit descriptor base. */ |
510 | writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); | |
ff43da86 FL |
511 | if (fep->bufdesc_ex) |
512 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex) | |
513 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
514 | else | |
515 | writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) | |
516 | * RX_RING_SIZE, fep->hwp + FEC_X_DES_START); | |
45993653 | 517 | |
45993653 | 518 | |
45993653 UKK |
519 | for (i = 0; i <= TX_RING_MOD_MASK; i++) { |
520 | if (fep->tx_skbuff[i]) { | |
521 | dev_kfree_skb_any(fep->tx_skbuff[i]); | |
522 | fep->tx_skbuff[i] = NULL; | |
1da177e4 | 523 | } |
45993653 | 524 | } |
97b72e43 | 525 | |
45993653 UKK |
526 | /* Enable MII mode */ |
527 | if (duplex) { | |
cd1f402c | 528 | /* FD enable */ |
45993653 UKK |
529 | writel(0x04, fep->hwp + FEC_X_CNTRL); |
530 | } else { | |
cd1f402c UKK |
531 | /* No Rcv on Xmit */ |
532 | rcntl |= 0x02; | |
45993653 UKK |
533 | writel(0x0, fep->hwp + FEC_X_CNTRL); |
534 | } | |
cd1f402c | 535 | |
45993653 UKK |
536 | fep->full_duplex = duplex; |
537 | ||
538 | /* Set MII speed */ | |
539 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
540 | ||
d1391930 | 541 | #if !defined(CONFIG_M5272) |
4c09eed9 JB |
542 | /* set RX checksum */ |
543 | val = readl(fep->hwp + FEC_RACC); | |
544 | if (fep->csum_flags & FLAG_RX_CSUM_ENABLED) | |
545 | val |= FEC_RACC_OPTIONS; | |
546 | else | |
547 | val &= ~FEC_RACC_OPTIONS; | |
548 | writel(val, fep->hwp + FEC_RACC); | |
d1391930 | 549 | #endif |
4c09eed9 | 550 | |
45993653 UKK |
551 | /* |
552 | * The phy interface and speed need to get configured | |
553 | * differently on enet-mac. | |
554 | */ | |
555 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { | |
cd1f402c UKK |
556 | /* Enable flow control and length check */ |
557 | rcntl |= 0x40000000 | 0x00000020; | |
45993653 | 558 | |
230dec61 SG |
559 | /* RGMII, RMII or MII */ |
560 | if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII) | |
561 | rcntl |= (1 << 6); | |
562 | else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) | |
cd1f402c | 563 | rcntl |= (1 << 8); |
45993653 | 564 | else |
cd1f402c | 565 | rcntl &= ~(1 << 8); |
45993653 | 566 | |
230dec61 SG |
567 | /* 1G, 100M or 10M */ |
568 | if (fep->phy_dev) { | |
569 | if (fep->phy_dev->speed == SPEED_1000) | |
570 | ecntl |= (1 << 5); | |
571 | else if (fep->phy_dev->speed == SPEED_100) | |
572 | rcntl &= ~(1 << 9); | |
573 | else | |
574 | rcntl |= (1 << 9); | |
575 | } | |
45993653 UKK |
576 | } else { |
577 | #ifdef FEC_MIIGSK_ENR | |
0ca1e290 | 578 | if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) { |
8d82f219 | 579 | u32 cfgr; |
45993653 UKK |
580 | /* disable the gasket and wait */ |
581 | writel(0, fep->hwp + FEC_MIIGSK_ENR); | |
582 | while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) | |
583 | udelay(1); | |
584 | ||
585 | /* | |
586 | * configure the gasket: | |
587 | * RMII, 50 MHz, no loopback, no echo | |
0ca1e290 | 588 | * MII, 25 MHz, no loopback, no echo |
45993653 | 589 | */ |
8d82f219 EB |
590 | cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) |
591 | ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; | |
592 | if (fep->phy_dev && fep->phy_dev->speed == SPEED_10) | |
593 | cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; | |
594 | writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); | |
45993653 UKK |
595 | |
596 | /* re-enable the gasket */ | |
597 | writel(2, fep->hwp + FEC_MIIGSK_ENR); | |
97b72e43 | 598 | } |
45993653 UKK |
599 | #endif |
600 | } | |
baa70a5c | 601 | |
d1391930 | 602 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
603 | /* enable pause frame*/ |
604 | if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) || | |
605 | ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) && | |
606 | fep->phy_dev && fep->phy_dev->pause)) { | |
607 | rcntl |= FEC_ENET_FCE; | |
608 | ||
4c09eed9 | 609 | /* set FIFO threshold parameter to reduce overrun */ |
baa70a5c FL |
610 | writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); |
611 | writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); | |
612 | writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); | |
613 | writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); | |
614 | ||
615 | /* OPD */ | |
616 | writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); | |
617 | } else { | |
618 | rcntl &= ~FEC_ENET_FCE; | |
619 | } | |
d1391930 | 620 | #endif /* !defined(CONFIG_M5272) */ |
baa70a5c | 621 | |
cd1f402c | 622 | writel(rcntl, fep->hwp + FEC_R_CNTRL); |
3b2b74ca | 623 | |
230dec61 SG |
624 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
625 | /* enable ENET endian swap */ | |
626 | ecntl |= (1 << 8); | |
627 | /* enable ENET store and forward mode */ | |
628 | writel(1 << 8, fep->hwp + FEC_X_WMRK); | |
629 | } | |
630 | ||
ff43da86 FL |
631 | if (fep->bufdesc_ex) |
632 | ecntl |= (1 << 4); | |
6605b730 | 633 | |
38ae92dc | 634 | #ifndef CONFIG_M5272 |
b9eef55c JB |
635 | /* Enable the MIB statistic event counters */ |
636 | writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); | |
38ae92dc CH |
637 | #endif |
638 | ||
45993653 | 639 | /* And last, enable the transmit and receive processing */ |
230dec61 | 640 | writel(ecntl, fep->hwp + FEC_ECNTRL); |
45993653 UKK |
641 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); |
642 | ||
ff43da86 FL |
643 | if (fep->bufdesc_ex) |
644 | fec_ptp_start_cyclecounter(ndev); | |
645 | ||
45993653 UKK |
646 | /* Enable interrupts we wish to service */ |
647 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
54309fa6 FL |
648 | |
649 | if (netif_running(ndev)) { | |
31691344 | 650 | netif_tx_unlock_bh(ndev); |
54309fa6 | 651 | netif_wake_queue(ndev); |
1ed0d56c FE |
652 | napi_enable(&fep->napi); |
653 | netif_device_attach(ndev); | |
54309fa6 | 654 | } |
45993653 UKK |
655 | } |
656 | ||
657 | static void | |
658 | fec_stop(struct net_device *ndev) | |
659 | { | |
660 | struct fec_enet_private *fep = netdev_priv(ndev); | |
230dec61 SG |
661 | const struct platform_device_id *id_entry = |
662 | platform_get_device_id(fep->pdev); | |
42431dc2 | 663 | u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8); |
45993653 UKK |
664 | |
665 | /* We cannot expect a graceful transmit stop without link !!! */ | |
666 | if (fep->link) { | |
667 | writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ | |
668 | udelay(10); | |
669 | if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) | |
31b7720c | 670 | netdev_err(ndev, "Graceful transmit stop did not complete!\n"); |
45993653 UKK |
671 | } |
672 | ||
673 | /* Whack a reset. We should wait for this. */ | |
674 | writel(1, fep->hwp + FEC_ECNTRL); | |
675 | udelay(10); | |
676 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); | |
677 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
230dec61 SG |
678 | |
679 | /* We have to keep ENET enabled to have MII interrupt stay working */ | |
42431dc2 | 680 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { |
230dec61 | 681 | writel(2, fep->hwp + FEC_ECNTRL); |
42431dc2 LW |
682 | writel(rmii_mode, fep->hwp + FEC_R_CNTRL); |
683 | } | |
1da177e4 LT |
684 | } |
685 | ||
686 | ||
45993653 UKK |
687 | static void |
688 | fec_timeout(struct net_device *ndev) | |
689 | { | |
690 | struct fec_enet_private *fep = netdev_priv(ndev); | |
691 | ||
692 | ndev->stats.tx_errors++; | |
693 | ||
54309fa6 FL |
694 | fep->delay_work.timeout = true; |
695 | schedule_delayed_work(&(fep->delay_work.delay_work), 0); | |
696 | } | |
697 | ||
698 | static void fec_enet_work(struct work_struct *work) | |
699 | { | |
700 | struct fec_enet_private *fep = | |
701 | container_of(work, | |
702 | struct fec_enet_private, | |
703 | delay_work.delay_work.work); | |
704 | ||
705 | if (fep->delay_work.timeout) { | |
706 | fep->delay_work.timeout = false; | |
707 | fec_restart(fep->netdev, fep->full_duplex); | |
708 | netif_wake_queue(fep->netdev); | |
709 | } | |
03191656 FL |
710 | |
711 | if (fep->delay_work.trig_tx) { | |
712 | fep->delay_work.trig_tx = false; | |
713 | writel(0, fep->hwp + FEC_X_DES_ACTIVE); | |
714 | } | |
45993653 UKK |
715 | } |
716 | ||
1da177e4 | 717 | static void |
c556167f | 718 | fec_enet_tx(struct net_device *ndev) |
1da177e4 LT |
719 | { |
720 | struct fec_enet_private *fep; | |
2e28532f | 721 | struct bufdesc *bdp; |
0e702ab3 | 722 | unsigned short status; |
1da177e4 | 723 | struct sk_buff *skb; |
de5fb0a0 | 724 | int index = 0; |
1da177e4 | 725 | |
c556167f | 726 | fep = netdev_priv(ndev); |
1da177e4 LT |
727 | bdp = fep->dirty_tx; |
728 | ||
de5fb0a0 FL |
729 | /* get next bdp of dirty_tx */ |
730 | if (bdp->cbd_sc & BD_ENET_TX_WRAP) | |
731 | bdp = fep->tx_bd_base; | |
732 | else | |
733 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
734 | ||
0e702ab3 | 735 | while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { |
de5fb0a0 FL |
736 | |
737 | /* current queue is empty */ | |
738 | if (bdp == fep->cur_tx) | |
f0b3fbea SH |
739 | break; |
740 | ||
de5fb0a0 FL |
741 | if (fep->bufdesc_ex) |
742 | index = (struct bufdesc_ex *)bdp - | |
743 | (struct bufdesc_ex *)fep->tx_bd_base; | |
744 | else | |
745 | index = bdp - fep->tx_bd_base; | |
746 | ||
d1ab1f54 UKK |
747 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
748 | FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); | |
f0b3fbea | 749 | bdp->cbd_bufaddr = 0; |
1da177e4 | 750 | |
de5fb0a0 FL |
751 | skb = fep->tx_skbuff[index]; |
752 | ||
1da177e4 | 753 | /* Check for errors. */ |
0e702ab3 | 754 | if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | |
1da177e4 LT |
755 | BD_ENET_TX_RL | BD_ENET_TX_UN | |
756 | BD_ENET_TX_CSL)) { | |
c556167f | 757 | ndev->stats.tx_errors++; |
0e702ab3 | 758 | if (status & BD_ENET_TX_HB) /* No heartbeat */ |
c556167f | 759 | ndev->stats.tx_heartbeat_errors++; |
0e702ab3 | 760 | if (status & BD_ENET_TX_LC) /* Late collision */ |
c556167f | 761 | ndev->stats.tx_window_errors++; |
0e702ab3 | 762 | if (status & BD_ENET_TX_RL) /* Retrans limit */ |
c556167f | 763 | ndev->stats.tx_aborted_errors++; |
0e702ab3 | 764 | if (status & BD_ENET_TX_UN) /* Underrun */ |
c556167f | 765 | ndev->stats.tx_fifo_errors++; |
0e702ab3 | 766 | if (status & BD_ENET_TX_CSL) /* Carrier lost */ |
c556167f | 767 | ndev->stats.tx_carrier_errors++; |
1da177e4 | 768 | } else { |
c556167f | 769 | ndev->stats.tx_packets++; |
06efce71 | 770 | ndev->stats.tx_bytes += bdp->cbd_datlen; |
1da177e4 LT |
771 | } |
772 | ||
ff43da86 FL |
773 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) && |
774 | fep->bufdesc_ex) { | |
6605b730 FL |
775 | struct skb_shared_hwtstamps shhwtstamps; |
776 | unsigned long flags; | |
ff43da86 | 777 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; |
6605b730 FL |
778 | |
779 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
780 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
781 | shhwtstamps.hwtstamp = ns_to_ktime( | |
ff43da86 | 782 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
783 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
784 | skb_tstamp_tx(skb, &shhwtstamps); | |
785 | } | |
ff43da86 | 786 | |
0e702ab3 | 787 | if (status & BD_ENET_TX_READY) |
31b7720c | 788 | netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n"); |
22f6b860 | 789 | |
1da177e4 LT |
790 | /* Deferred means some collisions occurred during transmit, |
791 | * but we eventually sent the packet OK. | |
792 | */ | |
0e702ab3 | 793 | if (status & BD_ENET_TX_DEF) |
c556167f | 794 | ndev->stats.collisions++; |
6aa20a22 | 795 | |
22f6b860 | 796 | /* Free the sk buffer associated with this last transmit */ |
1da177e4 | 797 | dev_kfree_skb_any(skb); |
de5fb0a0 FL |
798 | fep->tx_skbuff[index] = NULL; |
799 | ||
800 | fep->dirty_tx = bdp; | |
6aa20a22 | 801 | |
22f6b860 | 802 | /* Update pointer to next buffer descriptor to be transmitted */ |
0e702ab3 | 803 | if (status & BD_ENET_TX_WRAP) |
1da177e4 LT |
804 | bdp = fep->tx_bd_base; |
805 | else | |
ff43da86 | 806 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
6aa20a22 | 807 | |
22f6b860 | 808 | /* Since we have freed up a buffer, the ring is no longer full |
1da177e4 | 809 | */ |
de5fb0a0 | 810 | if (fep->dirty_tx != fep->cur_tx) { |
c556167f UKK |
811 | if (netif_queue_stopped(ndev)) |
812 | netif_wake_queue(ndev); | |
1da177e4 LT |
813 | } |
814 | } | |
de5fb0a0 | 815 | return; |
1da177e4 LT |
816 | } |
817 | ||
818 | ||
819 | /* During a receive, the cur_rx points to the current incoming buffer. | |
820 | * When we update through the ring, if the next incoming buffer has | |
821 | * not been given to the system, we just set the empty indicator, | |
822 | * effectively tossing the packet. | |
823 | */ | |
dc975382 FL |
824 | static int |
825 | fec_enet_rx(struct net_device *ndev, int budget) | |
1da177e4 | 826 | { |
c556167f | 827 | struct fec_enet_private *fep = netdev_priv(ndev); |
b5680e0b SG |
828 | const struct platform_device_id *id_entry = |
829 | platform_get_device_id(fep->pdev); | |
2e28532f | 830 | struct bufdesc *bdp; |
0e702ab3 | 831 | unsigned short status; |
1da177e4 LT |
832 | struct sk_buff *skb; |
833 | ushort pkt_len; | |
834 | __u8 *data; | |
dc975382 | 835 | int pkt_received = 0; |
cdffcf1b JB |
836 | struct bufdesc_ex *ebdp = NULL; |
837 | bool vlan_packet_rcvd = false; | |
838 | u16 vlan_tag; | |
6aa20a22 | 839 | |
0e702ab3 GU |
840 | #ifdef CONFIG_M532x |
841 | flush_cache_all(); | |
6aa20a22 | 842 | #endif |
1da177e4 | 843 | |
1da177e4 LT |
844 | /* First, grab all of the stats for the incoming packet. |
845 | * These get messed up if we get called due to a busy condition. | |
846 | */ | |
847 | bdp = fep->cur_rx; | |
848 | ||
22f6b860 | 849 | while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { |
1da177e4 | 850 | |
dc975382 FL |
851 | if (pkt_received >= budget) |
852 | break; | |
853 | pkt_received++; | |
854 | ||
22f6b860 SH |
855 | /* Since we have allocated space to hold a complete frame, |
856 | * the last indicator should be set. | |
857 | */ | |
858 | if ((status & BD_ENET_RX_LAST) == 0) | |
31b7720c | 859 | netdev_err(ndev, "rcv is not +last\n"); |
1da177e4 | 860 | |
22f6b860 SH |
861 | if (!fep->opened) |
862 | goto rx_processing_done; | |
1da177e4 | 863 | |
22f6b860 SH |
864 | /* Check for errors. */ |
865 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | | |
1da177e4 | 866 | BD_ENET_RX_CR | BD_ENET_RX_OV)) { |
c556167f | 867 | ndev->stats.rx_errors++; |
22f6b860 SH |
868 | if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { |
869 | /* Frame too long or too short. */ | |
c556167f | 870 | ndev->stats.rx_length_errors++; |
22f6b860 SH |
871 | } |
872 | if (status & BD_ENET_RX_NO) /* Frame alignment */ | |
c556167f | 873 | ndev->stats.rx_frame_errors++; |
22f6b860 | 874 | if (status & BD_ENET_RX_CR) /* CRC Error */ |
c556167f | 875 | ndev->stats.rx_crc_errors++; |
22f6b860 | 876 | if (status & BD_ENET_RX_OV) /* FIFO overrun */ |
c556167f | 877 | ndev->stats.rx_fifo_errors++; |
1da177e4 | 878 | } |
1da177e4 | 879 | |
22f6b860 SH |
880 | /* Report late collisions as a frame error. |
881 | * On this error, the BD is closed, but we don't know what we | |
882 | * have in the buffer. So, just drop this frame on the floor. | |
883 | */ | |
884 | if (status & BD_ENET_RX_CL) { | |
c556167f UKK |
885 | ndev->stats.rx_errors++; |
886 | ndev->stats.rx_frame_errors++; | |
22f6b860 SH |
887 | goto rx_processing_done; |
888 | } | |
1da177e4 | 889 | |
22f6b860 | 890 | /* Process the incoming frame. */ |
c556167f | 891 | ndev->stats.rx_packets++; |
22f6b860 | 892 | pkt_len = bdp->cbd_datlen; |
c556167f | 893 | ndev->stats.rx_bytes += pkt_len; |
22f6b860 | 894 | data = (__u8*)__va(bdp->cbd_bufaddr); |
1da177e4 | 895 | |
d1ab1f54 UKK |
896 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
897 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
ccdc4f19 | 898 | |
b5680e0b SG |
899 | if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) |
900 | swap_buffer(data, pkt_len); | |
901 | ||
cdffcf1b JB |
902 | /* Extract the enhanced buffer descriptor */ |
903 | ebdp = NULL; | |
904 | if (fep->bufdesc_ex) | |
905 | ebdp = (struct bufdesc_ex *)bdp; | |
906 | ||
907 | /* If this is a VLAN packet remove the VLAN Tag */ | |
908 | vlan_packet_rcvd = false; | |
909 | if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
910 | fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) { | |
911 | /* Push and remove the vlan tag */ | |
912 | struct vlan_hdr *vlan_header = | |
913 | (struct vlan_hdr *) (data + ETH_HLEN); | |
914 | vlan_tag = ntohs(vlan_header->h_vlan_TCI); | |
915 | pkt_len -= VLAN_HLEN; | |
916 | ||
917 | vlan_packet_rcvd = true; | |
918 | } | |
919 | ||
22f6b860 SH |
920 | /* This does 16 byte alignment, exactly what we need. |
921 | * The packet length includes FCS, but we don't want to | |
922 | * include that when passing upstream as it messes up | |
923 | * bridging applications. | |
924 | */ | |
b72061a3 | 925 | skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN); |
1da177e4 | 926 | |
8549889c | 927 | if (unlikely(!skb)) { |
c556167f | 928 | ndev->stats.rx_dropped++; |
22f6b860 | 929 | } else { |
cdffcf1b | 930 | int payload_offset = (2 * ETH_ALEN); |
8549889c | 931 | skb_reserve(skb, NET_IP_ALIGN); |
22f6b860 | 932 | skb_put(skb, pkt_len - 4); /* Make room */ |
cdffcf1b JB |
933 | |
934 | /* Extract the frame data without the VLAN header. */ | |
935 | skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN)); | |
936 | if (vlan_packet_rcvd) | |
937 | payload_offset = (2 * ETH_ALEN) + VLAN_HLEN; | |
938 | skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN), | |
939 | data + payload_offset, | |
940 | pkt_len - 4 - (2 * ETH_ALEN)); | |
941 | ||
c556167f | 942 | skb->protocol = eth_type_trans(skb, ndev); |
ff43da86 | 943 | |
6605b730 | 944 | /* Get receive timestamp from the skb */ |
ff43da86 | 945 | if (fep->hwts_rx_en && fep->bufdesc_ex) { |
6605b730 FL |
946 | struct skb_shared_hwtstamps *shhwtstamps = |
947 | skb_hwtstamps(skb); | |
948 | unsigned long flags; | |
949 | ||
950 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | |
951 | ||
952 | spin_lock_irqsave(&fep->tmreg_lock, flags); | |
953 | shhwtstamps->hwtstamp = ns_to_ktime( | |
ff43da86 | 954 | timecounter_cyc2time(&fep->tc, ebdp->ts)); |
6605b730 FL |
955 | spin_unlock_irqrestore(&fep->tmreg_lock, flags); |
956 | } | |
ff43da86 | 957 | |
4c09eed9 | 958 | if (fep->bufdesc_ex && |
cdffcf1b | 959 | (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) { |
4c09eed9 JB |
960 | if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) { |
961 | /* don't check it */ | |
962 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
963 | } else { | |
964 | skb_checksum_none_assert(skb); | |
965 | } | |
966 | } | |
967 | ||
cdffcf1b JB |
968 | /* Handle received VLAN packets */ |
969 | if (vlan_packet_rcvd) | |
970 | __vlan_hwaccel_put_tag(skb, | |
971 | htons(ETH_P_8021Q), | |
972 | vlan_tag); | |
973 | ||
18a03b97 | 974 | if (!skb_defer_rx_timestamp(skb)) |
dc975382 | 975 | napi_gro_receive(&fep->napi, skb); |
22f6b860 | 976 | } |
f0b3fbea | 977 | |
d1ab1f54 UKK |
978 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data, |
979 | FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE); | |
22f6b860 SH |
980 | rx_processing_done: |
981 | /* Clear the status flags for this buffer */ | |
982 | status &= ~BD_ENET_RX_STATS; | |
1da177e4 | 983 | |
22f6b860 SH |
984 | /* Mark the buffer empty */ |
985 | status |= BD_ENET_RX_EMPTY; | |
986 | bdp->cbd_sc = status; | |
6aa20a22 | 987 | |
ff43da86 FL |
988 | if (fep->bufdesc_ex) { |
989 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
990 | ||
991 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
992 | ebdp->cbd_prot = 0; | |
993 | ebdp->cbd_bdu = 0; | |
994 | } | |
6605b730 | 995 | |
22f6b860 SH |
996 | /* Update BD pointer to next entry */ |
997 | if (status & BD_ENET_RX_WRAP) | |
998 | bdp = fep->rx_bd_base; | |
999 | else | |
ff43da86 | 1000 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
22f6b860 SH |
1001 | /* Doing this here will keep the FEC running while we process |
1002 | * incoming frames. On a heavily loaded network, we should be | |
1003 | * able to keep up at the expense of system resources. | |
1004 | */ | |
1005 | writel(0, fep->hwp + FEC_R_DES_ACTIVE); | |
1006 | } | |
2e28532f | 1007 | fep->cur_rx = bdp; |
1da177e4 | 1008 | |
dc975382 | 1009 | return pkt_received; |
1da177e4 LT |
1010 | } |
1011 | ||
45993653 UKK |
1012 | static irqreturn_t |
1013 | fec_enet_interrupt(int irq, void *dev_id) | |
1014 | { | |
1015 | struct net_device *ndev = dev_id; | |
1016 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1017 | uint int_events; | |
1018 | irqreturn_t ret = IRQ_NONE; | |
1019 | ||
1020 | do { | |
1021 | int_events = readl(fep->hwp + FEC_IEVENT); | |
1022 | writel(int_events, fep->hwp + FEC_IEVENT); | |
1023 | ||
de5fb0a0 | 1024 | if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) { |
45993653 | 1025 | ret = IRQ_HANDLED; |
dc975382 FL |
1026 | |
1027 | /* Disable the RX interrupt */ | |
1028 | if (napi_schedule_prep(&fep->napi)) { | |
1029 | writel(FEC_RX_DISABLED_IMASK, | |
1030 | fep->hwp + FEC_IMASK); | |
1031 | __napi_schedule(&fep->napi); | |
1032 | } | |
45993653 UKK |
1033 | } |
1034 | ||
45993653 UKK |
1035 | if (int_events & FEC_ENET_MII) { |
1036 | ret = IRQ_HANDLED; | |
1037 | complete(&fep->mdio_done); | |
1038 | } | |
1039 | } while (int_events); | |
1040 | ||
1041 | return ret; | |
1042 | } | |
1043 | ||
dc975382 FL |
1044 | static int fec_enet_rx_napi(struct napi_struct *napi, int budget) |
1045 | { | |
1046 | struct net_device *ndev = napi->dev; | |
1047 | int pkts = fec_enet_rx(ndev, budget); | |
1048 | struct fec_enet_private *fep = netdev_priv(ndev); | |
45993653 | 1049 | |
de5fb0a0 FL |
1050 | fec_enet_tx(ndev); |
1051 | ||
dc975382 FL |
1052 | if (pkts < budget) { |
1053 | napi_complete(napi); | |
1054 | writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); | |
1055 | } | |
1056 | return pkts; | |
1057 | } | |
45993653 | 1058 | |
e6b043d5 | 1059 | /* ------------------------------------------------------------------------- */ |
0c7768a0 | 1060 | static void fec_get_mac(struct net_device *ndev) |
1da177e4 | 1061 | { |
c556167f | 1062 | struct fec_enet_private *fep = netdev_priv(ndev); |
49da97dc | 1063 | struct fec_platform_data *pdata = fep->pdev->dev.platform_data; |
e6b043d5 | 1064 | unsigned char *iap, tmpaddr[ETH_ALEN]; |
1da177e4 | 1065 | |
49da97dc SG |
1066 | /* |
1067 | * try to get mac address in following order: | |
1068 | * | |
1069 | * 1) module parameter via kernel command line in form | |
1070 | * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0 | |
1071 | */ | |
1072 | iap = macaddr; | |
1073 | ||
ca2cc333 SG |
1074 | /* |
1075 | * 2) from device tree data | |
1076 | */ | |
1077 | if (!is_valid_ether_addr(iap)) { | |
1078 | struct device_node *np = fep->pdev->dev.of_node; | |
1079 | if (np) { | |
1080 | const char *mac = of_get_mac_address(np); | |
1081 | if (mac) | |
1082 | iap = (unsigned char *) mac; | |
1083 | } | |
1084 | } | |
ca2cc333 | 1085 | |
49da97dc | 1086 | /* |
ca2cc333 | 1087 | * 3) from flash or fuse (via platform data) |
49da97dc SG |
1088 | */ |
1089 | if (!is_valid_ether_addr(iap)) { | |
1090 | #ifdef CONFIG_M5272 | |
1091 | if (FEC_FLASHMAC) | |
1092 | iap = (unsigned char *)FEC_FLASHMAC; | |
1093 | #else | |
1094 | if (pdata) | |
589efdc7 | 1095 | iap = (unsigned char *)&pdata->mac; |
49da97dc SG |
1096 | #endif |
1097 | } | |
1098 | ||
1099 | /* | |
ca2cc333 | 1100 | * 4) FEC mac registers set by bootloader |
49da97dc SG |
1101 | */ |
1102 | if (!is_valid_ether_addr(iap)) { | |
1103 | *((unsigned long *) &tmpaddr[0]) = | |
1104 | be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW)); | |
1105 | *((unsigned short *) &tmpaddr[4]) = | |
1106 | be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); | |
e6b043d5 | 1107 | iap = &tmpaddr[0]; |
1da177e4 LT |
1108 | } |
1109 | ||
ff5b2fab LS |
1110 | /* |
1111 | * 5) random mac address | |
1112 | */ | |
1113 | if (!is_valid_ether_addr(iap)) { | |
1114 | /* Report it and use a random ethernet address instead */ | |
1115 | netdev_err(ndev, "Invalid MAC address: %pM\n", iap); | |
1116 | eth_hw_addr_random(ndev); | |
1117 | netdev_info(ndev, "Using random MAC address: %pM\n", | |
1118 | ndev->dev_addr); | |
1119 | return; | |
1120 | } | |
1121 | ||
c556167f | 1122 | memcpy(ndev->dev_addr, iap, ETH_ALEN); |
1da177e4 | 1123 | |
49da97dc SG |
1124 | /* Adjust MAC if using macaddr */ |
1125 | if (iap == macaddr) | |
43af940c | 1126 | ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id; |
1da177e4 LT |
1127 | } |
1128 | ||
e6b043d5 | 1129 | /* ------------------------------------------------------------------------- */ |
1da177e4 | 1130 | |
e6b043d5 BW |
1131 | /* |
1132 | * Phy section | |
1133 | */ | |
c556167f | 1134 | static void fec_enet_adjust_link(struct net_device *ndev) |
1da177e4 | 1135 | { |
c556167f | 1136 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1137 | struct phy_device *phy_dev = fep->phy_dev; |
e6b043d5 | 1138 | int status_change = 0; |
1da177e4 | 1139 | |
e6b043d5 BW |
1140 | /* Prevent a state halted on mii error */ |
1141 | if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { | |
1142 | phy_dev->state = PHY_RESUMING; | |
54309fa6 | 1143 | return; |
e6b043d5 | 1144 | } |
1da177e4 | 1145 | |
e6b043d5 | 1146 | if (phy_dev->link) { |
d97e7497 | 1147 | if (!fep->link) { |
6ea0722f | 1148 | fep->link = phy_dev->link; |
e6b043d5 BW |
1149 | status_change = 1; |
1150 | } | |
1da177e4 | 1151 | |
d97e7497 LS |
1152 | if (fep->full_duplex != phy_dev->duplex) |
1153 | status_change = 1; | |
1154 | ||
1155 | if (phy_dev->speed != fep->speed) { | |
1156 | fep->speed = phy_dev->speed; | |
1157 | status_change = 1; | |
1158 | } | |
1159 | ||
1160 | /* if any of the above changed restart the FEC */ | |
1161 | if (status_change) | |
c556167f | 1162 | fec_restart(ndev, phy_dev->duplex); |
d97e7497 LS |
1163 | } else { |
1164 | if (fep->link) { | |
c556167f | 1165 | fec_stop(ndev); |
8d7ed0f0 | 1166 | fep->link = phy_dev->link; |
d97e7497 LS |
1167 | status_change = 1; |
1168 | } | |
1da177e4 | 1169 | } |
6aa20a22 | 1170 | |
e6b043d5 BW |
1171 | if (status_change) |
1172 | phy_print_status(phy_dev); | |
1173 | } | |
1da177e4 | 1174 | |
e6b043d5 | 1175 | static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) |
1da177e4 | 1176 | { |
e6b043d5 | 1177 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1178 | unsigned long time_left; |
1da177e4 | 1179 | |
e6b043d5 | 1180 | fep->mii_timeout = 0; |
97b72e43 | 1181 | init_completion(&fep->mdio_done); |
e6b043d5 BW |
1182 | |
1183 | /* start a read op */ | |
1184 | writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | | |
1185 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | | |
1186 | FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); | |
1187 | ||
1188 | /* wait for end of transfer */ | |
97b72e43 BS |
1189 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1190 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1191 | if (time_left == 0) { | |
1192 | fep->mii_timeout = 1; | |
31b7720c | 1193 | netdev_err(fep->netdev, "MDIO read timeout\n"); |
97b72e43 | 1194 | return -ETIMEDOUT; |
1da177e4 | 1195 | } |
1da177e4 | 1196 | |
e6b043d5 BW |
1197 | /* return value */ |
1198 | return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); | |
7dd6a2aa | 1199 | } |
6aa20a22 | 1200 | |
e6b043d5 BW |
1201 | static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, |
1202 | u16 value) | |
1da177e4 | 1203 | { |
e6b043d5 | 1204 | struct fec_enet_private *fep = bus->priv; |
97b72e43 | 1205 | unsigned long time_left; |
1da177e4 | 1206 | |
e6b043d5 | 1207 | fep->mii_timeout = 0; |
97b72e43 | 1208 | init_completion(&fep->mdio_done); |
1da177e4 | 1209 | |
862f0982 SG |
1210 | /* start a write op */ |
1211 | writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | | |
e6b043d5 BW |
1212 | FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | |
1213 | FEC_MMFR_TA | FEC_MMFR_DATA(value), | |
1214 | fep->hwp + FEC_MII_DATA); | |
1215 | ||
1216 | /* wait for end of transfer */ | |
97b72e43 BS |
1217 | time_left = wait_for_completion_timeout(&fep->mdio_done, |
1218 | usecs_to_jiffies(FEC_MII_TIMEOUT)); | |
1219 | if (time_left == 0) { | |
1220 | fep->mii_timeout = 1; | |
31b7720c | 1221 | netdev_err(fep->netdev, "MDIO write timeout\n"); |
97b72e43 | 1222 | return -ETIMEDOUT; |
e6b043d5 | 1223 | } |
1da177e4 | 1224 | |
e6b043d5 BW |
1225 | return 0; |
1226 | } | |
1da177e4 | 1227 | |
e6b043d5 | 1228 | static int fec_enet_mdio_reset(struct mii_bus *bus) |
1da177e4 | 1229 | { |
e6b043d5 | 1230 | return 0; |
1da177e4 LT |
1231 | } |
1232 | ||
c556167f | 1233 | static int fec_enet_mii_probe(struct net_device *ndev) |
562d2f8c | 1234 | { |
c556167f | 1235 | struct fec_enet_private *fep = netdev_priv(ndev); |
230dec61 SG |
1236 | const struct platform_device_id *id_entry = |
1237 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1238 | struct phy_device *phy_dev = NULL; |
6fcc040f GU |
1239 | char mdio_bus_id[MII_BUS_ID_SIZE]; |
1240 | char phy_name[MII_BUS_ID_SIZE + 3]; | |
1241 | int phy_id; | |
43af940c | 1242 | int dev_id = fep->dev_id; |
562d2f8c | 1243 | |
418bd0d4 BW |
1244 | fep->phy_dev = NULL; |
1245 | ||
6fcc040f GU |
1246 | /* check for attached phy */ |
1247 | for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { | |
1248 | if ((fep->mii_bus->phy_mask & (1 << phy_id))) | |
1249 | continue; | |
1250 | if (fep->mii_bus->phy_map[phy_id] == NULL) | |
1251 | continue; | |
1252 | if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) | |
1253 | continue; | |
b5680e0b SG |
1254 | if (dev_id--) |
1255 | continue; | |
6fcc040f GU |
1256 | strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); |
1257 | break; | |
e6b043d5 | 1258 | } |
1da177e4 | 1259 | |
6fcc040f | 1260 | if (phy_id >= PHY_MAX_ADDR) { |
31b7720c | 1261 | netdev_info(ndev, "no PHY, assuming direct connection to switch\n"); |
ea51ade9 | 1262 | strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); |
6fcc040f GU |
1263 | phy_id = 0; |
1264 | } | |
1265 | ||
a7ed07d5 | 1266 | snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id); |
f9a8f83b | 1267 | phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, |
230dec61 | 1268 | fep->phy_interface); |
6fcc040f | 1269 | if (IS_ERR(phy_dev)) { |
31b7720c | 1270 | netdev_err(ndev, "could not attach to PHY\n"); |
6fcc040f | 1271 | return PTR_ERR(phy_dev); |
e6b043d5 | 1272 | } |
1da177e4 | 1273 | |
e6b043d5 | 1274 | /* mask with MAC supported features */ |
baa70a5c | 1275 | if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) { |
230dec61 | 1276 | phy_dev->supported &= PHY_GBIT_FEATURES; |
d1391930 | 1277 | #if !defined(CONFIG_M5272) |
baa70a5c | 1278 | phy_dev->supported |= SUPPORTED_Pause; |
d1391930 | 1279 | #endif |
baa70a5c | 1280 | } |
230dec61 SG |
1281 | else |
1282 | phy_dev->supported &= PHY_BASIC_FEATURES; | |
1283 | ||
e6b043d5 | 1284 | phy_dev->advertising = phy_dev->supported; |
1da177e4 | 1285 | |
e6b043d5 BW |
1286 | fep->phy_dev = phy_dev; |
1287 | fep->link = 0; | |
1288 | fep->full_duplex = 0; | |
1da177e4 | 1289 | |
31b7720c JP |
1290 | netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
1291 | fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), | |
1292 | fep->phy_dev->irq); | |
418bd0d4 | 1293 | |
e6b043d5 | 1294 | return 0; |
1da177e4 LT |
1295 | } |
1296 | ||
e6b043d5 | 1297 | static int fec_enet_mii_init(struct platform_device *pdev) |
562d2f8c | 1298 | { |
b5680e0b | 1299 | static struct mii_bus *fec0_mii_bus; |
c556167f UKK |
1300 | struct net_device *ndev = platform_get_drvdata(pdev); |
1301 | struct fec_enet_private *fep = netdev_priv(ndev); | |
b5680e0b SG |
1302 | const struct platform_device_id *id_entry = |
1303 | platform_get_device_id(fep->pdev); | |
e6b043d5 | 1304 | int err = -ENXIO, i; |
6b265293 | 1305 | |
b5680e0b SG |
1306 | /* |
1307 | * The dual fec interfaces are not equivalent with enet-mac. | |
1308 | * Here are the differences: | |
1309 | * | |
1310 | * - fec0 supports MII & RMII modes while fec1 only supports RMII | |
1311 | * - fec0 acts as the 1588 time master while fec1 is slave | |
1312 | * - external phys can only be configured by fec0 | |
1313 | * | |
1314 | * That is to say fec1 can not work independently. It only works | |
1315 | * when fec0 is working. The reason behind this design is that the | |
1316 | * second interface is added primarily for Switch mode. | |
1317 | * | |
1318 | * Because of the last point above, both phys are attached on fec0 | |
1319 | * mdio interface in board design, and need to be configured by | |
1320 | * fec0 mii_bus. | |
1321 | */ | |
43af940c | 1322 | if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) { |
b5680e0b | 1323 | /* fec1 uses fec0 mii_bus */ |
e163cc97 LW |
1324 | if (mii_cnt && fec0_mii_bus) { |
1325 | fep->mii_bus = fec0_mii_bus; | |
1326 | mii_cnt++; | |
1327 | return 0; | |
1328 | } | |
1329 | return -ENOENT; | |
b5680e0b SG |
1330 | } |
1331 | ||
e6b043d5 | 1332 | fep->mii_timeout = 0; |
1da177e4 | 1333 | |
e6b043d5 BW |
1334 | /* |
1335 | * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) | |
230dec61 SG |
1336 | * |
1337 | * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while | |
1338 | * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28 | |
1339 | * Reference Manual has an error on this, and gets fixed on i.MX6Q | |
1340 | * document. | |
e6b043d5 | 1341 | */ |
f4d40de3 | 1342 | fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000); |
230dec61 SG |
1343 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) |
1344 | fep->phy_speed--; | |
1345 | fep->phy_speed <<= 1; | |
e6b043d5 | 1346 | writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); |
1da177e4 | 1347 | |
e6b043d5 BW |
1348 | fep->mii_bus = mdiobus_alloc(); |
1349 | if (fep->mii_bus == NULL) { | |
1350 | err = -ENOMEM; | |
1351 | goto err_out; | |
1da177e4 LT |
1352 | } |
1353 | ||
e6b043d5 BW |
1354 | fep->mii_bus->name = "fec_enet_mii_bus"; |
1355 | fep->mii_bus->read = fec_enet_mdio_read; | |
1356 | fep->mii_bus->write = fec_enet_mdio_write; | |
1357 | fep->mii_bus->reset = fec_enet_mdio_reset; | |
391420f7 FF |
1358 | snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1359 | pdev->name, fep->dev_id + 1); | |
e6b043d5 BW |
1360 | fep->mii_bus->priv = fep; |
1361 | fep->mii_bus->parent = &pdev->dev; | |
1362 | ||
1363 | fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | |
1364 | if (!fep->mii_bus->irq) { | |
1365 | err = -ENOMEM; | |
1366 | goto err_out_free_mdiobus; | |
1da177e4 LT |
1367 | } |
1368 | ||
e6b043d5 BW |
1369 | for (i = 0; i < PHY_MAX_ADDR; i++) |
1370 | fep->mii_bus->irq[i] = PHY_POLL; | |
1da177e4 | 1371 | |
e6b043d5 BW |
1372 | if (mdiobus_register(fep->mii_bus)) |
1373 | goto err_out_free_mdio_irq; | |
1da177e4 | 1374 | |
e163cc97 LW |
1375 | mii_cnt++; |
1376 | ||
b5680e0b SG |
1377 | /* save fec0 mii_bus */ |
1378 | if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) | |
1379 | fec0_mii_bus = fep->mii_bus; | |
1380 | ||
e6b043d5 | 1381 | return 0; |
1da177e4 | 1382 | |
e6b043d5 BW |
1383 | err_out_free_mdio_irq: |
1384 | kfree(fep->mii_bus->irq); | |
1385 | err_out_free_mdiobus: | |
1386 | mdiobus_free(fep->mii_bus); | |
1387 | err_out: | |
1388 | return err; | |
1da177e4 LT |
1389 | } |
1390 | ||
e6b043d5 | 1391 | static void fec_enet_mii_remove(struct fec_enet_private *fep) |
1da177e4 | 1392 | { |
e163cc97 LW |
1393 | if (--mii_cnt == 0) { |
1394 | mdiobus_unregister(fep->mii_bus); | |
1395 | kfree(fep->mii_bus->irq); | |
1396 | mdiobus_free(fep->mii_bus); | |
1397 | } | |
1da177e4 LT |
1398 | } |
1399 | ||
c556167f | 1400 | static int fec_enet_get_settings(struct net_device *ndev, |
e6b043d5 | 1401 | struct ethtool_cmd *cmd) |
1da177e4 | 1402 | { |
c556167f | 1403 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1404 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1405 | |
e6b043d5 BW |
1406 | if (!phydev) |
1407 | return -ENODEV; | |
1da177e4 | 1408 | |
e6b043d5 | 1409 | return phy_ethtool_gset(phydev, cmd); |
1da177e4 LT |
1410 | } |
1411 | ||
c556167f | 1412 | static int fec_enet_set_settings(struct net_device *ndev, |
e6b043d5 | 1413 | struct ethtool_cmd *cmd) |
1da177e4 | 1414 | { |
c556167f | 1415 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1416 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1417 | |
e6b043d5 BW |
1418 | if (!phydev) |
1419 | return -ENODEV; | |
1da177e4 | 1420 | |
e6b043d5 | 1421 | return phy_ethtool_sset(phydev, cmd); |
1da177e4 LT |
1422 | } |
1423 | ||
c556167f | 1424 | static void fec_enet_get_drvinfo(struct net_device *ndev, |
e6b043d5 | 1425 | struct ethtool_drvinfo *info) |
1da177e4 | 1426 | { |
c556167f | 1427 | struct fec_enet_private *fep = netdev_priv(ndev); |
6aa20a22 | 1428 | |
7826d43f JP |
1429 | strlcpy(info->driver, fep->pdev->dev.driver->name, |
1430 | sizeof(info->driver)); | |
1431 | strlcpy(info->version, "Revision: 1.0", sizeof(info->version)); | |
1432 | strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info)); | |
1da177e4 LT |
1433 | } |
1434 | ||
5ebae489 FL |
1435 | static int fec_enet_get_ts_info(struct net_device *ndev, |
1436 | struct ethtool_ts_info *info) | |
1437 | { | |
1438 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1439 | ||
1440 | if (fep->bufdesc_ex) { | |
1441 | ||
1442 | info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | | |
1443 | SOF_TIMESTAMPING_RX_SOFTWARE | | |
1444 | SOF_TIMESTAMPING_SOFTWARE | | |
1445 | SOF_TIMESTAMPING_TX_HARDWARE | | |
1446 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1447 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1448 | if (fep->ptp_clock) | |
1449 | info->phc_index = ptp_clock_index(fep->ptp_clock); | |
1450 | else | |
1451 | info->phc_index = -1; | |
1452 | ||
1453 | info->tx_types = (1 << HWTSTAMP_TX_OFF) | | |
1454 | (1 << HWTSTAMP_TX_ON); | |
1455 | ||
1456 | info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | | |
1457 | (1 << HWTSTAMP_FILTER_ALL); | |
1458 | return 0; | |
1459 | } else { | |
1460 | return ethtool_op_get_ts_info(ndev, info); | |
1461 | } | |
1462 | } | |
1463 | ||
d1391930 GR |
1464 | #if !defined(CONFIG_M5272) |
1465 | ||
baa70a5c FL |
1466 | static void fec_enet_get_pauseparam(struct net_device *ndev, |
1467 | struct ethtool_pauseparam *pause) | |
1468 | { | |
1469 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1470 | ||
1471 | pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0; | |
1472 | pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0; | |
1473 | pause->rx_pause = pause->tx_pause; | |
1474 | } | |
1475 | ||
1476 | static int fec_enet_set_pauseparam(struct net_device *ndev, | |
1477 | struct ethtool_pauseparam *pause) | |
1478 | { | |
1479 | struct fec_enet_private *fep = netdev_priv(ndev); | |
1480 | ||
1481 | if (pause->tx_pause != pause->rx_pause) { | |
1482 | netdev_info(ndev, | |
1483 | "hardware only support enable/disable both tx and rx"); | |
1484 | return -EINVAL; | |
1485 | } | |
1486 | ||
1487 | fep->pause_flag = 0; | |
1488 | ||
1489 | /* tx pause must be same as rx pause */ | |
1490 | fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0; | |
1491 | fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0; | |
1492 | ||
1493 | if (pause->rx_pause || pause->autoneg) { | |
1494 | fep->phy_dev->supported |= ADVERTISED_Pause; | |
1495 | fep->phy_dev->advertising |= ADVERTISED_Pause; | |
1496 | } else { | |
1497 | fep->phy_dev->supported &= ~ADVERTISED_Pause; | |
1498 | fep->phy_dev->advertising &= ~ADVERTISED_Pause; | |
1499 | } | |
1500 | ||
1501 | if (pause->autoneg) { | |
1502 | if (netif_running(ndev)) | |
1503 | fec_stop(ndev); | |
1504 | phy_start_aneg(fep->phy_dev); | |
1505 | } | |
1506 | if (netif_running(ndev)) | |
1507 | fec_restart(ndev, 0); | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
38ae92dc CH |
1512 | static const struct fec_stat { |
1513 | char name[ETH_GSTRING_LEN]; | |
1514 | u16 offset; | |
1515 | } fec_stats[] = { | |
1516 | /* RMON TX */ | |
1517 | { "tx_dropped", RMON_T_DROP }, | |
1518 | { "tx_packets", RMON_T_PACKETS }, | |
1519 | { "tx_broadcast", RMON_T_BC_PKT }, | |
1520 | { "tx_multicast", RMON_T_MC_PKT }, | |
1521 | { "tx_crc_errors", RMON_T_CRC_ALIGN }, | |
1522 | { "tx_undersize", RMON_T_UNDERSIZE }, | |
1523 | { "tx_oversize", RMON_T_OVERSIZE }, | |
1524 | { "tx_fragment", RMON_T_FRAG }, | |
1525 | { "tx_jabber", RMON_T_JAB }, | |
1526 | { "tx_collision", RMON_T_COL }, | |
1527 | { "tx_64byte", RMON_T_P64 }, | |
1528 | { "tx_65to127byte", RMON_T_P65TO127 }, | |
1529 | { "tx_128to255byte", RMON_T_P128TO255 }, | |
1530 | { "tx_256to511byte", RMON_T_P256TO511 }, | |
1531 | { "tx_512to1023byte", RMON_T_P512TO1023 }, | |
1532 | { "tx_1024to2047byte", RMON_T_P1024TO2047 }, | |
1533 | { "tx_GTE2048byte", RMON_T_P_GTE2048 }, | |
1534 | { "tx_octets", RMON_T_OCTETS }, | |
1535 | ||
1536 | /* IEEE TX */ | |
1537 | { "IEEE_tx_drop", IEEE_T_DROP }, | |
1538 | { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK }, | |
1539 | { "IEEE_tx_1col", IEEE_T_1COL }, | |
1540 | { "IEEE_tx_mcol", IEEE_T_MCOL }, | |
1541 | { "IEEE_tx_def", IEEE_T_DEF }, | |
1542 | { "IEEE_tx_lcol", IEEE_T_LCOL }, | |
1543 | { "IEEE_tx_excol", IEEE_T_EXCOL }, | |
1544 | { "IEEE_tx_macerr", IEEE_T_MACERR }, | |
1545 | { "IEEE_tx_cserr", IEEE_T_CSERR }, | |
1546 | { "IEEE_tx_sqe", IEEE_T_SQE }, | |
1547 | { "IEEE_tx_fdxfc", IEEE_T_FDXFC }, | |
1548 | { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK }, | |
1549 | ||
1550 | /* RMON RX */ | |
1551 | { "rx_packets", RMON_R_PACKETS }, | |
1552 | { "rx_broadcast", RMON_R_BC_PKT }, | |
1553 | { "rx_multicast", RMON_R_MC_PKT }, | |
1554 | { "rx_crc_errors", RMON_R_CRC_ALIGN }, | |
1555 | { "rx_undersize", RMON_R_UNDERSIZE }, | |
1556 | { "rx_oversize", RMON_R_OVERSIZE }, | |
1557 | { "rx_fragment", RMON_R_FRAG }, | |
1558 | { "rx_jabber", RMON_R_JAB }, | |
1559 | { "rx_64byte", RMON_R_P64 }, | |
1560 | { "rx_65to127byte", RMON_R_P65TO127 }, | |
1561 | { "rx_128to255byte", RMON_R_P128TO255 }, | |
1562 | { "rx_256to511byte", RMON_R_P256TO511 }, | |
1563 | { "rx_512to1023byte", RMON_R_P512TO1023 }, | |
1564 | { "rx_1024to2047byte", RMON_R_P1024TO2047 }, | |
1565 | { "rx_GTE2048byte", RMON_R_P_GTE2048 }, | |
1566 | { "rx_octets", RMON_R_OCTETS }, | |
1567 | ||
1568 | /* IEEE RX */ | |
1569 | { "IEEE_rx_drop", IEEE_R_DROP }, | |
1570 | { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK }, | |
1571 | { "IEEE_rx_crc", IEEE_R_CRC }, | |
1572 | { "IEEE_rx_align", IEEE_R_ALIGN }, | |
1573 | { "IEEE_rx_macerr", IEEE_R_MACERR }, | |
1574 | { "IEEE_rx_fdxfc", IEEE_R_FDXFC }, | |
1575 | { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK }, | |
1576 | }; | |
1577 | ||
1578 | static void fec_enet_get_ethtool_stats(struct net_device *dev, | |
1579 | struct ethtool_stats *stats, u64 *data) | |
1580 | { | |
1581 | struct fec_enet_private *fep = netdev_priv(dev); | |
1582 | int i; | |
1583 | ||
1584 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1585 | data[i] = readl(fep->hwp + fec_stats[i].offset); | |
1586 | } | |
1587 | ||
1588 | static void fec_enet_get_strings(struct net_device *netdev, | |
1589 | u32 stringset, u8 *data) | |
1590 | { | |
1591 | int i; | |
1592 | switch (stringset) { | |
1593 | case ETH_SS_STATS: | |
1594 | for (i = 0; i < ARRAY_SIZE(fec_stats); i++) | |
1595 | memcpy(data + i * ETH_GSTRING_LEN, | |
1596 | fec_stats[i].name, ETH_GSTRING_LEN); | |
1597 | break; | |
1598 | } | |
1599 | } | |
1600 | ||
1601 | static int fec_enet_get_sset_count(struct net_device *dev, int sset) | |
1602 | { | |
1603 | switch (sset) { | |
1604 | case ETH_SS_STATS: | |
1605 | return ARRAY_SIZE(fec_stats); | |
1606 | default: | |
1607 | return -EOPNOTSUPP; | |
1608 | } | |
1609 | } | |
d1391930 | 1610 | #endif /* !defined(CONFIG_M5272) */ |
38ae92dc | 1611 | |
32bc9b46 CH |
1612 | static int fec_enet_nway_reset(struct net_device *dev) |
1613 | { | |
1614 | struct fec_enet_private *fep = netdev_priv(dev); | |
1615 | struct phy_device *phydev = fep->phy_dev; | |
1616 | ||
1617 | if (!phydev) | |
1618 | return -ENODEV; | |
1619 | ||
1620 | return genphy_restart_aneg(phydev); | |
1621 | } | |
1622 | ||
9b07be4b | 1623 | static const struct ethtool_ops fec_enet_ethtool_ops = { |
d1391930 | 1624 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
1625 | .get_pauseparam = fec_enet_get_pauseparam, |
1626 | .set_pauseparam = fec_enet_set_pauseparam, | |
d1391930 | 1627 | #endif |
e6b043d5 BW |
1628 | .get_settings = fec_enet_get_settings, |
1629 | .set_settings = fec_enet_set_settings, | |
1630 | .get_drvinfo = fec_enet_get_drvinfo, | |
1631 | .get_link = ethtool_op_get_link, | |
5ebae489 | 1632 | .get_ts_info = fec_enet_get_ts_info, |
32bc9b46 | 1633 | .nway_reset = fec_enet_nway_reset, |
38ae92dc CH |
1634 | #ifndef CONFIG_M5272 |
1635 | .get_ethtool_stats = fec_enet_get_ethtool_stats, | |
1636 | .get_strings = fec_enet_get_strings, | |
1637 | .get_sset_count = fec_enet_get_sset_count, | |
1638 | #endif | |
e6b043d5 | 1639 | }; |
1da177e4 | 1640 | |
c556167f | 1641 | static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) |
1da177e4 | 1642 | { |
c556167f | 1643 | struct fec_enet_private *fep = netdev_priv(ndev); |
e6b043d5 | 1644 | struct phy_device *phydev = fep->phy_dev; |
1da177e4 | 1645 | |
c556167f | 1646 | if (!netif_running(ndev)) |
e6b043d5 | 1647 | return -EINVAL; |
1da177e4 | 1648 | |
e6b043d5 BW |
1649 | if (!phydev) |
1650 | return -ENODEV; | |
1651 | ||
ff43da86 | 1652 | if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex) |
6605b730 | 1653 | return fec_ptp_ioctl(ndev, rq, cmd); |
ff43da86 | 1654 | |
28b04113 | 1655 | return phy_mii_ioctl(phydev, rq, cmd); |
1da177e4 LT |
1656 | } |
1657 | ||
c556167f | 1658 | static void fec_enet_free_buffers(struct net_device *ndev) |
f0b3fbea | 1659 | { |
c556167f | 1660 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1661 | unsigned int i; |
f0b3fbea SH |
1662 | struct sk_buff *skb; |
1663 | struct bufdesc *bdp; | |
1664 | ||
1665 | bdp = fep->rx_bd_base; | |
1666 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1667 | skb = fep->rx_skbuff[i]; | |
1668 | ||
1669 | if (bdp->cbd_bufaddr) | |
d1ab1f54 | 1670 | dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, |
f0b3fbea SH |
1671 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1672 | if (skb) | |
1673 | dev_kfree_skb(skb); | |
ff43da86 | 1674 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1675 | } |
1676 | ||
1677 | bdp = fep->tx_bd_base; | |
1678 | for (i = 0; i < TX_RING_SIZE; i++) | |
1679 | kfree(fep->tx_bounce[i]); | |
1680 | } | |
1681 | ||
c556167f | 1682 | static int fec_enet_alloc_buffers(struct net_device *ndev) |
f0b3fbea | 1683 | { |
c556167f | 1684 | struct fec_enet_private *fep = netdev_priv(ndev); |
da2191e3 | 1685 | unsigned int i; |
f0b3fbea SH |
1686 | struct sk_buff *skb; |
1687 | struct bufdesc *bdp; | |
1688 | ||
1689 | bdp = fep->rx_bd_base; | |
1690 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b72061a3 | 1691 | skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE); |
f0b3fbea | 1692 | if (!skb) { |
c556167f | 1693 | fec_enet_free_buffers(ndev); |
f0b3fbea SH |
1694 | return -ENOMEM; |
1695 | } | |
1696 | fep->rx_skbuff[i] = skb; | |
1697 | ||
d1ab1f54 | 1698 | bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data, |
f0b3fbea SH |
1699 | FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); |
1700 | bdp->cbd_sc = BD_ENET_RX_EMPTY; | |
ff43da86 FL |
1701 | |
1702 | if (fep->bufdesc_ex) { | |
1703 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
1704 | ebdp->cbd_esc = BD_ENET_RX_INT; | |
1705 | } | |
1706 | ||
1707 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1708 | } |
1709 | ||
1710 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1711 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1712 | bdp->cbd_sc |= BD_SC_WRAP; |
1713 | ||
1714 | bdp = fep->tx_bd_base; | |
1715 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1716 | fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); | |
1717 | ||
1718 | bdp->cbd_sc = 0; | |
1719 | bdp->cbd_bufaddr = 0; | |
6605b730 | 1720 | |
ff43da86 FL |
1721 | if (fep->bufdesc_ex) { |
1722 | struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp; | |
96d2222b | 1723 | ebdp->cbd_esc = BD_ENET_TX_INT; |
ff43da86 FL |
1724 | } |
1725 | ||
1726 | bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex); | |
f0b3fbea SH |
1727 | } |
1728 | ||
1729 | /* Set the last buffer to wrap. */ | |
ff43da86 | 1730 | bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex); |
f0b3fbea SH |
1731 | bdp->cbd_sc |= BD_SC_WRAP; |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1da177e4 | 1736 | static int |
c556167f | 1737 | fec_enet_open(struct net_device *ndev) |
1da177e4 | 1738 | { |
c556167f | 1739 | struct fec_enet_private *fep = netdev_priv(ndev); |
f0b3fbea | 1740 | int ret; |
1da177e4 | 1741 | |
dc975382 FL |
1742 | napi_enable(&fep->napi); |
1743 | ||
1da177e4 LT |
1744 | /* I should reset the ring buffers here, but I don't yet know |
1745 | * a simple way to do that. | |
1746 | */ | |
1da177e4 | 1747 | |
c556167f | 1748 | ret = fec_enet_alloc_buffers(ndev); |
f0b3fbea SH |
1749 | if (ret) |
1750 | return ret; | |
1751 | ||
418bd0d4 | 1752 | /* Probe and connect to PHY when open the interface */ |
c556167f | 1753 | ret = fec_enet_mii_probe(ndev); |
418bd0d4 | 1754 | if (ret) { |
c556167f | 1755 | fec_enet_free_buffers(ndev); |
418bd0d4 BW |
1756 | return ret; |
1757 | } | |
e6b043d5 | 1758 | phy_start(fep->phy_dev); |
c556167f | 1759 | netif_start_queue(ndev); |
1da177e4 | 1760 | fep->opened = 1; |
22f6b860 | 1761 | return 0; |
1da177e4 LT |
1762 | } |
1763 | ||
1764 | static int | |
c556167f | 1765 | fec_enet_close(struct net_device *ndev) |
1da177e4 | 1766 | { |
c556167f | 1767 | struct fec_enet_private *fep = netdev_priv(ndev); |
1da177e4 | 1768 | |
22f6b860 | 1769 | /* Don't know what to do yet. */ |
3f104c38 | 1770 | napi_disable(&fep->napi); |
1da177e4 | 1771 | fep->opened = 0; |
c556167f UKK |
1772 | netif_stop_queue(ndev); |
1773 | fec_stop(ndev); | |
1da177e4 | 1774 | |
e497ba82 UKK |
1775 | if (fep->phy_dev) { |
1776 | phy_stop(fep->phy_dev); | |
418bd0d4 | 1777 | phy_disconnect(fep->phy_dev); |
e497ba82 | 1778 | } |
418bd0d4 | 1779 | |
db8880bc | 1780 | fec_enet_free_buffers(ndev); |
f0b3fbea | 1781 | |
1da177e4 LT |
1782 | return 0; |
1783 | } | |
1784 | ||
1da177e4 LT |
1785 | /* Set or clear the multicast filter for this adaptor. |
1786 | * Skeleton taken from sunlance driver. | |
1787 | * The CPM Ethernet implementation allows Multicast as well as individual | |
1788 | * MAC address filtering. Some of the drivers check to make sure it is | |
1789 | * a group multicast address, and discard those that are not. I guess I | |
1790 | * will do the same for now, but just remove the test if you want | |
1791 | * individual filtering as well (do the upper net layers want or support | |
1792 | * this kind of feature?). | |
1793 | */ | |
1794 | ||
1795 | #define HASH_BITS 6 /* #bits in hash */ | |
1796 | #define CRC32_POLY 0xEDB88320 | |
1797 | ||
c556167f | 1798 | static void set_multicast_list(struct net_device *ndev) |
1da177e4 | 1799 | { |
c556167f | 1800 | struct fec_enet_private *fep = netdev_priv(ndev); |
22bedad3 | 1801 | struct netdev_hw_addr *ha; |
48e2f183 | 1802 | unsigned int i, bit, data, crc, tmp; |
1da177e4 LT |
1803 | unsigned char hash; |
1804 | ||
c556167f | 1805 | if (ndev->flags & IFF_PROMISC) { |
f44d6305 SH |
1806 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1807 | tmp |= 0x8; | |
1808 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
4e831836 SH |
1809 | return; |
1810 | } | |
1da177e4 | 1811 | |
4e831836 SH |
1812 | tmp = readl(fep->hwp + FEC_R_CNTRL); |
1813 | tmp &= ~0x8; | |
1814 | writel(tmp, fep->hwp + FEC_R_CNTRL); | |
1815 | ||
c556167f | 1816 | if (ndev->flags & IFF_ALLMULTI) { |
4e831836 SH |
1817 | /* Catch all multicast addresses, so set the |
1818 | * filter to all 1's | |
1819 | */ | |
1820 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1821 | writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1822 | ||
1823 | return; | |
1824 | } | |
1825 | ||
1826 | /* Clear filter and add the addresses in hash register | |
1827 | */ | |
1828 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1829 | writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1830 | ||
c556167f | 1831 | netdev_for_each_mc_addr(ha, ndev) { |
4e831836 SH |
1832 | /* calculate crc32 value of mac address */ |
1833 | crc = 0xffffffff; | |
1834 | ||
c556167f | 1835 | for (i = 0; i < ndev->addr_len; i++) { |
22bedad3 | 1836 | data = ha->addr[i]; |
4e831836 SH |
1837 | for (bit = 0; bit < 8; bit++, data >>= 1) { |
1838 | crc = (crc >> 1) ^ | |
1839 | (((crc ^ data) & 1) ? CRC32_POLY : 0); | |
1da177e4 LT |
1840 | } |
1841 | } | |
4e831836 SH |
1842 | |
1843 | /* only upper 6 bits (HASH_BITS) are used | |
1844 | * which point to specific bit in he hash registers | |
1845 | */ | |
1846 | hash = (crc >> (32 - HASH_BITS)) & 0x3f; | |
1847 | ||
1848 | if (hash > 31) { | |
1849 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1850 | tmp |= 1 << (hash - 32); | |
1851 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); | |
1852 | } else { | |
1853 | tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1854 | tmp |= 1 << hash; | |
1855 | writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); | |
1856 | } | |
1da177e4 LT |
1857 | } |
1858 | } | |
1859 | ||
22f6b860 | 1860 | /* Set a MAC change in hardware. */ |
009fda83 | 1861 | static int |
c556167f | 1862 | fec_set_mac_address(struct net_device *ndev, void *p) |
1da177e4 | 1863 | { |
c556167f | 1864 | struct fec_enet_private *fep = netdev_priv(ndev); |
009fda83 SH |
1865 | struct sockaddr *addr = p; |
1866 | ||
1867 | if (!is_valid_ether_addr(addr->sa_data)) | |
1868 | return -EADDRNOTAVAIL; | |
1869 | ||
c556167f | 1870 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); |
1da177e4 | 1871 | |
c556167f UKK |
1872 | writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | |
1873 | (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), | |
f44d6305 | 1874 | fep->hwp + FEC_ADDR_LOW); |
c556167f | 1875 | writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), |
7cff0943 | 1876 | fep->hwp + FEC_ADDR_HIGH); |
009fda83 | 1877 | return 0; |
1da177e4 LT |
1878 | } |
1879 | ||
7f5c6add | 1880 | #ifdef CONFIG_NET_POLL_CONTROLLER |
49ce9c2c BH |
1881 | /** |
1882 | * fec_poll_controller - FEC Poll controller function | |
7f5c6add XJ |
1883 | * @dev: The FEC network adapter |
1884 | * | |
1885 | * Polled functionality used by netconsole and others in non interrupt mode | |
1886 | * | |
1887 | */ | |
47a5247f | 1888 | static void fec_poll_controller(struct net_device *dev) |
7f5c6add XJ |
1889 | { |
1890 | int i; | |
1891 | struct fec_enet_private *fep = netdev_priv(dev); | |
1892 | ||
1893 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
1894 | if (fep->irq[i] > 0) { | |
1895 | disable_irq(fep->irq[i]); | |
1896 | fec_enet_interrupt(fep->irq[i], dev); | |
1897 | enable_irq(fep->irq[i]); | |
1898 | } | |
1899 | } | |
1900 | } | |
1901 | #endif | |
1902 | ||
4c09eed9 JB |
1903 | static int fec_set_features(struct net_device *netdev, |
1904 | netdev_features_t features) | |
1905 | { | |
1906 | struct fec_enet_private *fep = netdev_priv(netdev); | |
1907 | netdev_features_t changed = features ^ netdev->features; | |
1908 | ||
1909 | netdev->features = features; | |
1910 | ||
1911 | /* Receive checksum has been changed */ | |
1912 | if (changed & NETIF_F_RXCSUM) { | |
1913 | if (features & NETIF_F_RXCSUM) | |
1914 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1915 | else | |
1916 | fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED; | |
1917 | ||
1918 | if (netif_running(netdev)) { | |
1919 | fec_stop(netdev); | |
1920 | fec_restart(netdev, fep->phy_dev->duplex); | |
1921 | netif_wake_queue(netdev); | |
1922 | } else { | |
1923 | fec_restart(netdev, fep->phy_dev->duplex); | |
1924 | } | |
1925 | } | |
1926 | ||
1927 | return 0; | |
1928 | } | |
1929 | ||
009fda83 SH |
1930 | static const struct net_device_ops fec_netdev_ops = { |
1931 | .ndo_open = fec_enet_open, | |
1932 | .ndo_stop = fec_enet_close, | |
1933 | .ndo_start_xmit = fec_enet_start_xmit, | |
afc4b13d | 1934 | .ndo_set_rx_mode = set_multicast_list, |
635ecaa7 | 1935 | .ndo_change_mtu = eth_change_mtu, |
009fda83 SH |
1936 | .ndo_validate_addr = eth_validate_addr, |
1937 | .ndo_tx_timeout = fec_timeout, | |
1938 | .ndo_set_mac_address = fec_set_mac_address, | |
db8880bc | 1939 | .ndo_do_ioctl = fec_enet_ioctl, |
7f5c6add XJ |
1940 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1941 | .ndo_poll_controller = fec_poll_controller, | |
1942 | #endif | |
4c09eed9 | 1943 | .ndo_set_features = fec_set_features, |
009fda83 SH |
1944 | }; |
1945 | ||
1da177e4 LT |
1946 | /* |
1947 | * XXX: We need to clean up on failure exits here. | |
ead73183 | 1948 | * |
1da177e4 | 1949 | */ |
c556167f | 1950 | static int fec_enet_init(struct net_device *ndev) |
1da177e4 | 1951 | { |
c556167f | 1952 | struct fec_enet_private *fep = netdev_priv(ndev); |
48496255 SG |
1953 | const struct platform_device_id *id_entry = |
1954 | platform_get_device_id(fep->pdev); | |
f0b3fbea | 1955 | struct bufdesc *cbd_base; |
1da177e4 | 1956 | |
8d4dd5cf SH |
1957 | /* Allocate memory for buffer descriptors. */ |
1958 | cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, | |
d0320f75 JP |
1959 | GFP_KERNEL); |
1960 | if (!cbd_base) | |
562d2f8c | 1961 | return -ENOMEM; |
562d2f8c | 1962 | |
14109a59 | 1963 | memset(cbd_base, 0, PAGE_SIZE); |
3b2b74ca | 1964 | |
c556167f | 1965 | fep->netdev = ndev; |
1da177e4 | 1966 | |
49da97dc | 1967 | /* Get the Ethernet address */ |
c556167f | 1968 | fec_get_mac(ndev); |
1da177e4 | 1969 | |
8d4dd5cf | 1970 | /* Set receive and transmit descriptor base. */ |
1da177e4 | 1971 | fep->rx_bd_base = cbd_base; |
ff43da86 FL |
1972 | if (fep->bufdesc_ex) |
1973 | fep->tx_bd_base = (struct bufdesc *) | |
1974 | (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE); | |
1975 | else | |
1976 | fep->tx_bd_base = cbd_base + RX_RING_SIZE; | |
1da177e4 | 1977 | |
22f6b860 | 1978 | /* The FEC Ethernet specific entries in the device structure */ |
c556167f UKK |
1979 | ndev->watchdog_timeo = TX_TIMEOUT; |
1980 | ndev->netdev_ops = &fec_netdev_ops; | |
1981 | ndev->ethtool_ops = &fec_enet_ethtool_ops; | |
633e7533 | 1982 | |
dc975382 FL |
1983 | writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); |
1984 | netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT); | |
1985 | ||
cdffcf1b JB |
1986 | if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) { |
1987 | /* enable hw VLAN support */ | |
1988 | ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
1989 | ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; | |
1990 | } | |
1991 | ||
48496255 SG |
1992 | if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) { |
1993 | /* enable hw accelerator */ | |
1994 | ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1995 | | NETIF_F_RXCSUM); | |
1996 | ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
1997 | | NETIF_F_RXCSUM); | |
1998 | fep->csum_flags |= FLAG_RX_CSUM_ENABLED; | |
1999 | } | |
4c09eed9 | 2000 | |
c556167f | 2001 | fec_restart(ndev, 0); |
1da177e4 | 2002 | |
1da177e4 LT |
2003 | return 0; |
2004 | } | |
2005 | ||
ca2cc333 | 2006 | #ifdef CONFIG_OF |
33897cc8 | 2007 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2008 | { |
2009 | int err, phy_reset; | |
a3caad0a | 2010 | int msec = 1; |
ca2cc333 SG |
2011 | struct device_node *np = pdev->dev.of_node; |
2012 | ||
2013 | if (!np) | |
a9b2c8ef | 2014 | return; |
ca2cc333 | 2015 | |
a3caad0a SG |
2016 | of_property_read_u32(np, "phy-reset-duration", &msec); |
2017 | /* A sane reset duration should not be longer than 1s */ | |
2018 | if (msec > 1000) | |
2019 | msec = 1; | |
2020 | ||
ca2cc333 | 2021 | phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0); |
07dcf8e9 FE |
2022 | if (!gpio_is_valid(phy_reset)) |
2023 | return; | |
2024 | ||
119fc007 SG |
2025 | err = devm_gpio_request_one(&pdev->dev, phy_reset, |
2026 | GPIOF_OUT_INIT_LOW, "phy-reset"); | |
ca2cc333 | 2027 | if (err) { |
07dcf8e9 | 2028 | dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err); |
a9b2c8ef | 2029 | return; |
ca2cc333 | 2030 | } |
a3caad0a | 2031 | msleep(msec); |
ca2cc333 | 2032 | gpio_set_value(phy_reset, 1); |
ca2cc333 SG |
2033 | } |
2034 | #else /* CONFIG_OF */ | |
0c7768a0 | 2035 | static void fec_reset_phy(struct platform_device *pdev) |
ca2cc333 SG |
2036 | { |
2037 | /* | |
2038 | * In case of platform probe, the reset has been done | |
2039 | * by machine code. | |
2040 | */ | |
ca2cc333 SG |
2041 | } |
2042 | #endif /* CONFIG_OF */ | |
2043 | ||
33897cc8 | 2044 | static int |
ead73183 SH |
2045 | fec_probe(struct platform_device *pdev) |
2046 | { | |
2047 | struct fec_enet_private *fep; | |
5eb32bd0 | 2048 | struct fec_platform_data *pdata; |
ead73183 SH |
2049 | struct net_device *ndev; |
2050 | int i, irq, ret = 0; | |
2051 | struct resource *r; | |
ca2cc333 | 2052 | const struct of_device_id *of_id; |
43af940c | 2053 | static int dev_id; |
ca2cc333 SG |
2054 | |
2055 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | |
2056 | if (of_id) | |
2057 | pdev->id_entry = of_id->data; | |
ead73183 SH |
2058 | |
2059 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2060 | if (!r) | |
2061 | return -ENXIO; | |
2062 | ||
ead73183 SH |
2063 | /* Init network device */ |
2064 | ndev = alloc_etherdev(sizeof(struct fec_enet_private)); | |
83e519b6 FE |
2065 | if (!ndev) |
2066 | return -ENOMEM; | |
ead73183 SH |
2067 | |
2068 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
2069 | ||
2070 | /* setup board info structure */ | |
2071 | fep = netdev_priv(ndev); | |
ead73183 | 2072 | |
d1391930 | 2073 | #if !defined(CONFIG_M5272) |
baa70a5c FL |
2074 | /* default enable pause frame auto negotiation */ |
2075 | if (pdev->id_entry && | |
2076 | (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT)) | |
2077 | fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG; | |
d1391930 | 2078 | #endif |
baa70a5c | 2079 | |
941e173a TB |
2080 | fep->hwp = devm_ioremap_resource(&pdev->dev, r); |
2081 | if (IS_ERR(fep->hwp)) { | |
2082 | ret = PTR_ERR(fep->hwp); | |
2083 | goto failed_ioremap; | |
2084 | } | |
2085 | ||
e6b043d5 | 2086 | fep->pdev = pdev; |
43af940c | 2087 | fep->dev_id = dev_id++; |
ead73183 | 2088 | |
ff43da86 FL |
2089 | fep->bufdesc_ex = 0; |
2090 | ||
ead73183 SH |
2091 | platform_set_drvdata(pdev, ndev); |
2092 | ||
6c5f7808 | 2093 | ret = of_get_phy_mode(pdev->dev.of_node); |
ca2cc333 SG |
2094 | if (ret < 0) { |
2095 | pdata = pdev->dev.platform_data; | |
2096 | if (pdata) | |
2097 | fep->phy_interface = pdata->phy; | |
2098 | else | |
2099 | fep->phy_interface = PHY_INTERFACE_MODE_MII; | |
2100 | } else { | |
2101 | fep->phy_interface = ret; | |
2102 | } | |
2103 | ||
f4d40de3 SH |
2104 | fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
2105 | if (IS_ERR(fep->clk_ipg)) { | |
2106 | ret = PTR_ERR(fep->clk_ipg); | |
ead73183 SH |
2107 | goto failed_clk; |
2108 | } | |
f4d40de3 SH |
2109 | |
2110 | fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
2111 | if (IS_ERR(fep->clk_ahb)) { | |
2112 | ret = PTR_ERR(fep->clk_ahb); | |
2113 | goto failed_clk; | |
2114 | } | |
2115 | ||
daa7d392 WS |
2116 | /* enet_out is optional, depends on board */ |
2117 | fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out"); | |
2118 | if (IS_ERR(fep->clk_enet_out)) | |
2119 | fep->clk_enet_out = NULL; | |
2120 | ||
6605b730 | 2121 | fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp"); |
e2f8d555 FE |
2122 | fep->bufdesc_ex = |
2123 | pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX; | |
6605b730 | 2124 | if (IS_ERR(fep->clk_ptp)) { |
c29dc2d7 | 2125 | fep->clk_ptp = NULL; |
ff43da86 | 2126 | fep->bufdesc_ex = 0; |
6605b730 | 2127 | } |
6605b730 | 2128 | |
f4d40de3 SH |
2129 | clk_prepare_enable(fep->clk_ahb); |
2130 | clk_prepare_enable(fep->clk_ipg); | |
daa7d392 | 2131 | clk_prepare_enable(fep->clk_enet_out); |
c29dc2d7 | 2132 | clk_prepare_enable(fep->clk_ptp); |
ff43da86 | 2133 | |
f4e9f3d2 FE |
2134 | fep->reg_phy = devm_regulator_get(&pdev->dev, "phy"); |
2135 | if (!IS_ERR(fep->reg_phy)) { | |
2136 | ret = regulator_enable(fep->reg_phy); | |
5fa9c0fe SG |
2137 | if (ret) { |
2138 | dev_err(&pdev->dev, | |
2139 | "Failed to enable phy regulator: %d\n", ret); | |
2140 | goto failed_regulator; | |
2141 | } | |
f6a4d607 FE |
2142 | } else { |
2143 | fep->reg_phy = NULL; | |
5fa9c0fe SG |
2144 | } |
2145 | ||
2ca9b2aa SG |
2146 | fec_reset_phy(pdev); |
2147 | ||
e2f8d555 | 2148 | if (fep->bufdesc_ex) |
ca162a82 | 2149 | fec_ptp_init(pdev); |
e2f8d555 FE |
2150 | |
2151 | ret = fec_enet_init(ndev); | |
2152 | if (ret) | |
2153 | goto failed_init; | |
2154 | ||
2155 | for (i = 0; i < FEC_IRQ_NUM; i++) { | |
2156 | irq = platform_get_irq(pdev, i); | |
2157 | if (irq < 0) { | |
2158 | if (i) | |
2159 | break; | |
2160 | ret = irq; | |
2161 | goto failed_irq; | |
2162 | } | |
2163 | ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); | |
2164 | if (ret) { | |
2165 | while (--i >= 0) { | |
2166 | irq = platform_get_irq(pdev, i); | |
2167 | free_irq(irq, ndev); | |
2168 | } | |
2169 | goto failed_irq; | |
2170 | } | |
2171 | } | |
2172 | ||
e6b043d5 BW |
2173 | ret = fec_enet_mii_init(pdev); |
2174 | if (ret) | |
2175 | goto failed_mii_init; | |
2176 | ||
03c698c9 OS |
2177 | /* Carrier starts down, phylib will bring it up */ |
2178 | netif_carrier_off(ndev); | |
2179 | ||
ead73183 SH |
2180 | ret = register_netdev(ndev); |
2181 | if (ret) | |
2182 | goto failed_register; | |
2183 | ||
eb1d0640 FE |
2184 | if (fep->bufdesc_ex && fep->ptp_clock) |
2185 | netdev_info(ndev, "registered PHC device %d\n", fep->dev_id); | |
2186 | ||
54309fa6 | 2187 | INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work); |
ead73183 SH |
2188 | return 0; |
2189 | ||
2190 | failed_register: | |
e6b043d5 BW |
2191 | fec_enet_mii_remove(fep); |
2192 | failed_mii_init: | |
7a2bbd8d | 2193 | failed_irq: |
e2f8d555 FE |
2194 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
2195 | irq = platform_get_irq(pdev, i); | |
2196 | if (irq > 0) | |
2197 | free_irq(irq, ndev); | |
2198 | } | |
7a2bbd8d | 2199 | failed_init: |
f6a4d607 FE |
2200 | if (fep->reg_phy) |
2201 | regulator_disable(fep->reg_phy); | |
5fa9c0fe | 2202 | failed_regulator: |
f4d40de3 SH |
2203 | clk_disable_unprepare(fep->clk_ahb); |
2204 | clk_disable_unprepare(fep->clk_ipg); | |
daa7d392 | 2205 | clk_disable_unprepare(fep->clk_enet_out); |
c29dc2d7 | 2206 | clk_disable_unprepare(fep->clk_ptp); |
ead73183 | 2207 | failed_clk: |
ead73183 SH |
2208 | failed_ioremap: |
2209 | free_netdev(ndev); | |
2210 | ||
2211 | return ret; | |
2212 | } | |
2213 | ||
33897cc8 | 2214 | static int |
ead73183 SH |
2215 | fec_drv_remove(struct platform_device *pdev) |
2216 | { | |
2217 | struct net_device *ndev = platform_get_drvdata(pdev); | |
2218 | struct fec_enet_private *fep = netdev_priv(ndev); | |
e163cc97 | 2219 | int i; |
ead73183 | 2220 | |
54309fa6 | 2221 | cancel_delayed_work_sync(&(fep->delay_work.delay_work)); |
e163cc97 | 2222 | unregister_netdev(ndev); |
e6b043d5 | 2223 | fec_enet_mii_remove(fep); |
6605b730 | 2224 | del_timer_sync(&fep->time_keep); |
c55284e4 FE |
2225 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
2226 | int irq = platform_get_irq(pdev, i); | |
2227 | if (irq > 0) | |
2228 | free_irq(irq, ndev); | |
2229 | } | |
f6a4d607 FE |
2230 | if (fep->reg_phy) |
2231 | regulator_disable(fep->reg_phy); | |
6605b730 FL |
2232 | clk_disable_unprepare(fep->clk_ptp); |
2233 | if (fep->ptp_clock) | |
2234 | ptp_clock_unregister(fep->ptp_clock); | |
daa7d392 | 2235 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2236 | clk_disable_unprepare(fep->clk_ahb); |
2237 | clk_disable_unprepare(fep->clk_ipg); | |
ead73183 | 2238 | free_netdev(ndev); |
28e2188e | 2239 | |
ead73183 SH |
2240 | return 0; |
2241 | } | |
2242 | ||
bf7bfd7f | 2243 | #ifdef CONFIG_PM_SLEEP |
ead73183 | 2244 | static int |
87cad5c3 | 2245 | fec_suspend(struct device *dev) |
ead73183 | 2246 | { |
87cad5c3 | 2247 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2248 | struct fec_enet_private *fep = netdev_priv(ndev); |
ead73183 | 2249 | |
04e5216d UKK |
2250 | if (netif_running(ndev)) { |
2251 | fec_stop(ndev); | |
2252 | netif_device_detach(ndev); | |
ead73183 | 2253 | } |
daa7d392 | 2254 | clk_disable_unprepare(fep->clk_enet_out); |
f4d40de3 SH |
2255 | clk_disable_unprepare(fep->clk_ahb); |
2256 | clk_disable_unprepare(fep->clk_ipg); | |
04e5216d | 2257 | |
238f7bc7 FE |
2258 | if (fep->reg_phy) |
2259 | regulator_disable(fep->reg_phy); | |
2260 | ||
ead73183 SH |
2261 | return 0; |
2262 | } | |
2263 | ||
2264 | static int | |
87cad5c3 | 2265 | fec_resume(struct device *dev) |
ead73183 | 2266 | { |
87cad5c3 | 2267 | struct net_device *ndev = dev_get_drvdata(dev); |
04e5216d | 2268 | struct fec_enet_private *fep = netdev_priv(ndev); |
238f7bc7 FE |
2269 | int ret; |
2270 | ||
2271 | if (fep->reg_phy) { | |
2272 | ret = regulator_enable(fep->reg_phy); | |
2273 | if (ret) | |
2274 | return ret; | |
2275 | } | |
ead73183 | 2276 | |
daa7d392 | 2277 | clk_prepare_enable(fep->clk_enet_out); |
f4d40de3 SH |
2278 | clk_prepare_enable(fep->clk_ahb); |
2279 | clk_prepare_enable(fep->clk_ipg); | |
04e5216d UKK |
2280 | if (netif_running(ndev)) { |
2281 | fec_restart(ndev, fep->full_duplex); | |
2282 | netif_device_attach(ndev); | |
ead73183 | 2283 | } |
04e5216d | 2284 | |
ead73183 SH |
2285 | return 0; |
2286 | } | |
bf7bfd7f | 2287 | #endif /* CONFIG_PM_SLEEP */ |
ead73183 | 2288 | |
bf7bfd7f | 2289 | static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume); |
59d4289b | 2290 | |
ead73183 SH |
2291 | static struct platform_driver fec_driver = { |
2292 | .driver = { | |
b5680e0b | 2293 | .name = DRIVER_NAME, |
87cad5c3 | 2294 | .owner = THIS_MODULE, |
87cad5c3 | 2295 | .pm = &fec_pm_ops, |
ca2cc333 | 2296 | .of_match_table = fec_dt_ids, |
ead73183 | 2297 | }, |
b5680e0b | 2298 | .id_table = fec_devtype, |
87cad5c3 | 2299 | .probe = fec_probe, |
33897cc8 | 2300 | .remove = fec_drv_remove, |
ead73183 SH |
2301 | }; |
2302 | ||
aaca2377 | 2303 | module_platform_driver(fec_driver); |
1da177e4 | 2304 | |
f8c0aca9 | 2305 | MODULE_ALIAS("platform:"DRIVER_NAME); |
1da177e4 | 2306 | MODULE_LICENSE("GPL"); |