[deliverable/linux.git] / drivers / net / ethernet / freescale / fsl_pq_mdio.c

/*
 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
 * Provides Bus interface for MIIM regs
 *
 * Author: Andy Fleming <afleming@freescale.com>
 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
 *
 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
 *
 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mii.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>

#include <asm/io.h>
#include <asm/ucc.h>	/* for ucc_set_qe_mux_mii_mng() */

#include "gianfar.h"

#define MIIMIND_BUSY		0x00000001
#define MIIMIND_NOTVALID	0x00000004
#define MIIMCFG_INIT_VALUE	0x00000007
#define MIIMCFG_RESET		0x80000000

#define MII_READ_COMMAND	0x00000001

struct fsl_pq_mdio {
	u8 res1[16];
	u32 ieventm;	/* MDIO Interrupt event register (for etsec2)*/
	u32 imaskm;	/* MDIO Interrupt mask register (for etsec2)*/
	u8 res2[4];
	u32 emapm;	/* MDIO Event mapping register (for etsec2)*/
	u8 res3[1280];
	u32 miimcfg;	/* MII management configuration reg */
	u32 miimcom;	/* MII management command reg */
	u32 miimadd;	/* MII management address reg */
	u32 miimcon;	/* MII management control reg */
	u32 miimstat;	/* MII management status reg */
	u32 miimind;	/* MII management indication reg */
	u8 res4[28];
	u32 utbipar;	/* TBI phy address reg (only on UCC) */
	u8 res5[2728];
} __packed;

/* Number of microseconds to wait for an MII register to respond */
#define MII_TIMEOUT	1000

struct fsl_pq_mdio_priv {
	void __iomem *map;
	struct fsl_pq_mdio __iomem *regs;
};

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus attached to the local interface, which may be different from the
 * generic mdio bus (tied to a single interface), waiting until the write is
 * done before returning. This is helpful in programming interfaces like
 * the TBI which control interfaces like onchip SERDES and are always tied to
 * the local mdio pins, which may not be the same as system mdio bus, used for
 * controlling the external PHYs, for example.
 */
static int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
		int regnum, u16 value)
{
	u32 status;

	/* Set the PHY address and the register address we want to write */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Write out the value we want */
	out_be32(&regs->miimcon, value);

	/* Wait for the transaction to finish */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &	MIIMIND_BUSY),
				    MII_TIMEOUT, 0);

	return status ? 0 : -ETIMEDOUT;
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.  All PHY operation
 * done on the bus attached to the local interface,
 * which may be different from the generic mdio bus
 * This is helpful in programming interfaces like
 * the TBI which, in turn, control interfaces like onchip SERDES
 * and are always tied to the local mdio pins, which may not be the
 * same as system mdio bus, used for controlling the external PHYs, for eg.
 */
static int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
		int mii_id, int regnum)
{
	u16 value;
	u32 status;

	/* Set the PHY address and the register address we want to read */
	out_be32(&regs->miimadd, (mii_id << 8) | regnum);

	/* Clear miimcom, and then initiate a read */
	out_be32(&regs->miimcom, 0);
	out_be32(&regs->miimcom, MII_READ_COMMAND);

	/* Wait for the transaction to finish, normally less than 100us */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &
				    (MIIMIND_NOTVALID | MIIMIND_BUSY)),
				    MII_TIMEOUT, 0);
	if (!status)
		return -ETIMEDOUT;

	/* Grab the value of the register from miimstat */
	value = in_be32(&regs->miimstat);

	return value;
}

static struct fsl_pq_mdio __iomem *fsl_pq_mdio_get_regs(struct mii_bus *bus)
{
	struct fsl_pq_mdio_priv *priv = bus->priv;

	return priv->regs;
}

/*
 * Write value to the PHY at mii_id at register regnum,
 * on the bus, waiting until the write is done before returning.
 */
static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
		u16 value)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Write to the local MII regs */
	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
}

/*
 * Read the bus for PHY at addr mii_id, register regnum, and
 * return the value.  Clears miimcom first.
 */
static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);

	/* Read the local MII regs */
	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
}

/* Reset the MIIM registers, and wait for the bus to free */
static int fsl_pq_mdio_reset(struct mii_bus *bus)
{
	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
	u32 status;

	mutex_lock(&bus->mdio_lock);

	/* Reset the management interface */
	out_be32(&regs->miimcfg, MIIMCFG_RESET);

	/* Setup the MII Mgmt clock speed */
	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);

	/* Wait until the bus is free */
	status = spin_event_timeout(!(in_be32(&regs->miimind) &	MIIMIND_BUSY),
				    MII_TIMEOUT, 0);

	mutex_unlock(&bus->mdio_lock);

	if (!status) {
		printk(KERN_ERR "%s: The MII Bus is stuck!\n",
				bus->name);
		return -EBUSY;
	}

	return 0;
}

static void fsl_pq_mdio_bus_name(char *name, struct device_node *np)
{
	const u32 *addr;
	u64 taddr = OF_BAD_ADDR;

	addr = of_get_address(np, 0, NULL, NULL);
	if (addr)
		taddr = of_translate_address(np, addr);

	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
		(unsigned long long)taddr);
}


static u32 __iomem *get_gfar_tbipa(struct fsl_pq_mdio __iomem *regs, struct device_node *np)
{
#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
	struct gfar __iomem *enet_regs;

	/*
	 * This is mildly evil, but so is our hardware for doing this.
	 * Also, we have to cast back to struct gfar because of
	 * definition weirdness done in gianfar.h.
	 */
	if(of_device_is_compatible(np, "fsl,gianfar-mdio") ||
		of_device_is_compatible(np, "fsl,gianfar-tbi") ||
		of_device_is_compatible(np, "gianfar")) {
		enet_regs = (struct gfar __iomem *)regs;
		return &enet_regs->tbipa;
	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi")) {
		return of_iomap(np, 1);
	}
#endif
	return NULL;
}


static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
{
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
	struct device_node *np = NULL;
	int err = 0;

	for_each_compatible_node(np, NULL, "ucc_geth") {
		struct resource tempres;

		err = of_address_to_resource(np, 0, &tempres);
		if (err)
			continue;

		/* if our mdio regs fall within this UCC regs range */
		if ((start >= tempres.start) && (end <= tempres.end)) {
			/* Find the id of the UCC */
			const u32 *id;

			id = of_get_property(np, "cell-index", NULL);
			if (!id) {
				id = of_get_property(np, "device-id", NULL);
				if (!id)
					continue;
			}

			*ucc_id = *id;

			return 0;
		}
	}

	if (err)
		return err;
	else
		return -EINVAL;
#else
	return -ENODEV;
#endif
}

static int fsl_pq_mdio_probe(struct platform_device *ofdev)
{
	struct device_node *np = ofdev->dev.of_node;
	struct device_node *tbi;
	struct fsl_pq_mdio_priv *priv;
	struct fsl_pq_mdio __iomem *regs = NULL;
	void __iomem *map;
	u32 __iomem *tbipa;
	struct mii_bus *new_bus;
	int tbiaddr = -1;
	const u32 *addrp;
	u64 addr = 0, size = 0;
	int err;

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	new_bus = mdiobus_alloc();
	if (!new_bus) {
		err = -ENOMEM;
		goto err_free_priv;
	}

	new_bus->name = "Freescale PowerQUICC MII Bus",
	new_bus->read = &fsl_pq_mdio_read,
	new_bus->write = &fsl_pq_mdio_write,
	new_bus->reset = &fsl_pq_mdio_reset,
	new_bus->priv = priv;
	fsl_pq_mdio_bus_name(new_bus->id, np);

	addrp = of_get_address(np, 0, &size, NULL);
	if (!addrp) {
		err = -EINVAL;
		goto err_free_bus;
	}

	/* Set the PHY base address */
	addr = of_translate_address(np, addrp);
	if (addr == OF_BAD_ADDR) {
		err = -EINVAL;
		goto err_free_bus;
	}

	map = ioremap(addr, size);
	if (!map) {
		err = -ENOMEM;
		goto err_free_bus;
	}
	priv->map = map;

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy"))
		map -= offsetof(struct fsl_pq_mdio, miimcfg);
	regs = map;
	priv->regs = regs;

	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);

	if (NULL == new_bus->irq) {
		err = -ENOMEM;
		goto err_unmap_regs;
	}

	new_bus->parent = &ofdev->dev;
	dev_set_drvdata(&ofdev->dev, new_bus);

	if (of_device_is_compatible(np, "fsl,gianfar-mdio") ||
			of_device_is_compatible(np, "fsl,gianfar-tbi") ||
			of_device_is_compatible(np, "fsl,etsec2-mdio") ||
			of_device_is_compatible(np, "fsl,etsec2-tbi") ||
			of_device_is_compatible(np, "gianfar")) {
		tbipa = get_gfar_tbipa(regs, np);
		if (!tbipa) {
			err = -EINVAL;
			goto err_free_irqs;
		}
	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") ||
			of_device_is_compatible(np, "ucc_geth_phy")) {
		u32 id;
		static u32 mii_mng_master;

		tbipa = &regs->utbipar;

		if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
			goto err_free_irqs;

		if (!mii_mng_master) {
			mii_mng_master = id;
			ucc_set_qe_mux_mii_mng(id - 1);
		}
	} else {
		err = -ENODEV;
		goto err_free_irqs;
	}

	for_each_child_of_node(np, tbi) {
		if (!strncmp(tbi->type, "tbi-phy", 8))
			break;
	}

	if (tbi) {
		const u32 *prop = of_get_property(tbi, "reg", NULL);

		if (prop)
			tbiaddr = *prop;

		if (tbiaddr == -1) {
			err = -EBUSY;
			goto err_free_irqs;
		} else {
			out_be32(tbipa, tbiaddr);
		}
	}

	err = of_mdiobus_register(new_bus, np);
	if (err) {
		printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
				new_bus->name);
		goto err_free_irqs;
	}

	return 0;

err_free_irqs:
	kfree(new_bus->irq);
err_unmap_regs:
	iounmap(priv->map);
err_free_bus:
	kfree(new_bus);
err_free_priv:
	kfree(priv);
	return err;
}


static int fsl_pq_mdio_remove(struct platform_device *ofdev)
{
	struct device *device = &ofdev->dev;
	struct mii_bus *bus = dev_get_drvdata(device);
	struct fsl_pq_mdio_priv *priv = bus->priv;

	mdiobus_unregister(bus);

	dev_set_drvdata(device, NULL);

	iounmap(priv->map);
	bus->priv = NULL;
	mdiobus_free(bus);
	kfree(priv);

	return 0;
}

static struct of_device_id fsl_pq_mdio_match[] = {
	{
		.type = "mdio",
		.compatible = "ucc_geth_phy",
	},
	{
		.type = "mdio",
		.compatible = "gianfar",
	},
	{
		.compatible = "fsl,ucc-mdio",
	},
	{
		.compatible = "fsl,gianfar-tbi",
	},
	{
		.compatible = "fsl,gianfar-mdio",
	},
	{
		.compatible = "fsl,etsec2-tbi",
	},
	{
		.compatible = "fsl,etsec2-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);

static struct platform_driver fsl_pq_mdio_driver = {
	.driver = {
		.name = "fsl-pq_mdio",
		.owner = THIS_MODULE,
		.of_match_table = fsl_pq_mdio_match,
	},
	.probe = fsl_pq_mdio_probe,
	.remove = fsl_pq_mdio_remove,
};

module_platform_driver(fsl_pq_mdio_driver);

MODULE_LICENSE("GPL");
Commit	Line	Data
1577ecef AF	1	/*
	2	* Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
	3	* Provides Bus interface for MIIM regs
	4	*
	5	* Author: Andy Fleming <afleming@freescale.com>
1d2397d7	6	* Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1577ecef	7	*
1d2397d7	8	* Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
1577ecef AF	9	*
	10	* Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/string.h>
	21	#include <linux/errno.h>
1577ecef	22	#include <linux/slab.h>
1577ecef AF	23	#include <linux/init.h>
1577ecef AF	24	#include <linux/delay.h>
1577ecef AF	25	#include <linux/module.h>
1577ecef AF	26	#include <linux/platform_device.h>
1577ecef	27	#include <linux/mii.h>
22ae782f	28	#include <linux/of_address.h>
324931ba	29	#include <linux/of_mdio.h>
1577ecef AF	30	#include <linux/of_platform.h>
	31
	32	#include <asm/io.h>
1aa06d42	33	#include <asm/ucc.h> /* for ucc_set_qe_mux_mii_mng() */
1577ecef AF	34
1577ecef AF	35	#include "gianfar.h"
19bcd6c6 TT	36
	37	#define MIIMIND_BUSY 0x00000001
	38	#define MIIMIND_NOTVALID 0x00000004
	39	#define MIIMCFG_INIT_VALUE 0x00000007
	40	#define MIIMCFG_RESET 0x80000000
	41
	42	#define MII_READ_COMMAND 0x00000001
	43
	44	struct fsl_pq_mdio {
	45	u8 res1[16];
	46	u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
	47	u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
	48	u8 res2[4];
	49	u32 emapm; /* MDIO Event mapping register (for etsec2)*/
	50	u8 res3[1280];
	51	u32 miimcfg; /* MII management configuration reg */
	52	u32 miimcom; /* MII management command reg */
	53	u32 miimadd; /* MII management address reg */
	54	u32 miimcon; /* MII management control reg */
	55	u32 miimstat; /* MII management status reg */
	56	u32 miimind; /* MII management indication reg */
	57	u8 res4[28];
	58	u32 utbipar; /* TBI phy address reg (only on UCC) */
	59	u8 res5[2728];
	60	} __packed;
1577ecef	61
59399c59 TT	62	/* Number of microseconds to wait for an MII register to respond */
	63	#define MII_TIMEOUT 1000
	64
b3319b10 AV	65	struct fsl_pq_mdio_priv {
	66	void __iomem *map;
	67	struct fsl_pq_mdio __iomem *regs;
	68	};
	69
1577ecef AF	70	/*
	71	* Write value to the PHY at mii_id at register regnum,
	72	* on the bus attached to the local interface, which may be different from the
	73	* generic mdio bus (tied to a single interface), waiting until the write is
	74	* done before returning. This is helpful in programming interfaces like
	75	* the TBI which control interfaces like onchip SERDES and are always tied to
	76	* the local mdio pins, which may not be the same as system mdio bus, used for
	77	* controlling the external PHYs, for example.
	78	*/
19bcd6c6	79	static int fsl_pq_local_mdio_write(struct fsl_pq_mdio __iomem *regs, int mii_id,
1577ecef AF	80	int regnum, u16 value)
1577ecef AF	81	{
59399c59 TT	82	u32 status;
59399c59 TT	83
1577ecef AF	84	/* Set the PHY address and the register address we want to write */
	85	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	86
	87	/* Write out the value we want */
	88	out_be32(&regs->miimcon, value);
	89
	90	/* Wait for the transaction to finish */
59399c59 TT	91	status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
59399c59 TT	92	MII_TIMEOUT, 0);
1577ecef	93
59399c59	94	return status ? 0 : -ETIMEDOUT;
1577ecef AF	95	}
	96
	97	/*
	98	* Read the bus for PHY at addr mii_id, register regnum, and
	99	* return the value. Clears miimcom first. All PHY operation
	100	* done on the bus attached to the local interface,
	101	* which may be different from the generic mdio bus
	102	* This is helpful in programming interfaces like
	103	* the TBI which, in turn, control interfaces like onchip SERDES
	104	* and are always tied to the local mdio pins, which may not be the
	105	* same as system mdio bus, used for controlling the external PHYs, for eg.
	106	*/
19bcd6c6	107	static int fsl_pq_local_mdio_read(struct fsl_pq_mdio __iomem *regs,
1577ecef AF	108	int mii_id, int regnum)
	109	{
	110	u16 value;
59399c59	111	u32 status;
1577ecef AF	112
	113	/* Set the PHY address and the register address we want to read */
	114	out_be32(&regs->miimadd, (mii_id << 8) \| regnum);
	115
	116	/* Clear miimcom, and then initiate a read */
	117	out_be32(&regs->miimcom, 0);
	118	out_be32(&regs->miimcom, MII_READ_COMMAND);
	119
59399c59 TT	120	/* Wait for the transaction to finish, normally less than 100us */
	121	status = spin_event_timeout(!(in_be32(&regs->miimind) &
	122	(MIIMIND_NOTVALID \| MIIMIND_BUSY)),
	123	MII_TIMEOUT, 0);
	124	if (!status)
	125	return -ETIMEDOUT;
1577ecef AF	126
	127	/* Grab the value of the register from miimstat */
	128	value = in_be32(&regs->miimstat);
	129
	130	return value;
	131	}
	132
6748f60b AV	133	static struct fsl_pq_mdio __iomem fsl_pq_mdio_get_regs(struct mii_bus bus)
6748f60b AV	134	{
b3319b10 AV	135	struct fsl_pq_mdio_priv *priv = bus->priv;
	136
	137	return priv->regs;
6748f60b AV	138	}
6748f60b AV	139
1577ecef AF	140	/*
	141	* Write value to the PHY at mii_id at register regnum,
	142	* on the bus, waiting until the write is done before returning.
	143	*/
19bcd6c6 TT	144	static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
19bcd6c6 TT	145	u16 value)
1577ecef	146	{
6748f60b	147	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	148
1577ecef AF	149	/* Write to the local MII regs */
807540ba	150	return fsl_pq_local_mdio_write(regs, mii_id, regnum, value);
1577ecef AF	151	}
	152
	153	/*
	154	* Read the bus for PHY at addr mii_id, register regnum, and
	155	* return the value. Clears miimcom first.
	156	*/
19bcd6c6	157	static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1577ecef	158	{
6748f60b	159	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
1577ecef AF	160
1577ecef AF	161	/* Read the local MII regs */
807540ba	162	return fsl_pq_local_mdio_read(regs, mii_id, regnum);
1577ecef AF	163	}
	164
	165	/* Reset the MIIM registers, and wait for the bus to free */
	166	static int fsl_pq_mdio_reset(struct mii_bus *bus)
	167	{
6748f60b	168	struct fsl_pq_mdio __iomem *regs = fsl_pq_mdio_get_regs(bus);
59399c59	169	u32 status;
1577ecef AF	170
	171	mutex_lock(&bus->mdio_lock);
	172
	173	/* Reset the management interface */
	174	out_be32(&regs->miimcfg, MIIMCFG_RESET);
	175
	176	/* Setup the MII Mgmt clock speed */
	177	out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
	178
	179	/* Wait until the bus is free */
59399c59 TT	180	status = spin_event_timeout(!(in_be32(&regs->miimind) & MIIMIND_BUSY),
59399c59 TT	181	MII_TIMEOUT, 0);
1577ecef AF	182
	183	mutex_unlock(&bus->mdio_lock);
	184
59399c59	185	if (!status) {
1577ecef AF	186	printk(KERN_ERR "%s: The MII Bus is stuck!\n",
	187	bus->name);
	188	return -EBUSY;
	189	}
	190
	191	return 0;
	192	}
	193
19bcd6c6	194	static void fsl_pq_mdio_bus_name(char name, struct device_node np)
1577ecef	195	{
18f27383 AV	196	const u32 *addr;
18f27383 AV	197	u64 taddr = OF_BAD_ADDR;
1577ecef	198
18f27383 AV	199	addr = of_get_address(np, 0, NULL, NULL);
	200	if (addr)
	201	taddr = of_translate_address(np, addr);
1577ecef	202
18f27383 AV	203	snprintf(name, MII_BUS_ID_SIZE, "%s@%llx", np->name,
18f27383 AV	204	(unsigned long long)taddr);
1577ecef AF	205	}
1577ecef AF	206
1577ecef	207
1d2397d7	208	static u32 __iomem get_gfar_tbipa(struct fsl_pq_mdio __iomem regs, struct device_node *np)
1577ecef	209	{
952c5ca1	210	#if defined(CONFIG_GIANFAR) \|\| defined(CONFIG_GIANFAR_MODULE)
1577ecef AF	211	struct gfar __iomem *enet_regs;
	212
	213	/*
	214	* This is mildly evil, but so is our hardware for doing this.
	215	* Also, we have to cast back to struct gfar because of
	216	* definition weirdness done in gianfar.h.
	217	*/
1d2397d7 SG	218	if(of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	219	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	220	of_device_is_compatible(np, "gianfar")) {
	221	enet_regs = (struct gfar __iomem *)regs;
	222	return &enet_regs->tbipa;
	223	} else if (of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
	224	of_device_is_compatible(np, "fsl,etsec2-tbi")) {
3b1fd3e5	225	return of_iomap(np, 1);
952c5ca1	226	}
1577ecef	227	#endif
952c5ca1 AF	228	return NULL;
952c5ca1 AF	229	}
1577ecef AF	230
1577ecef AF	231
1577ecef AF	232	static int get_ucc_id_for_range(u64 start, u64 end, u32 *ucc_id)
1577ecef AF	233	{
952c5ca1	234	#if defined(CONFIG_UCC_GETH) \|\| defined(CONFIG_UCC_GETH_MODULE)
1577ecef AF	235	struct device_node *np = NULL;
	236	int err = 0;
	237
	238	for_each_compatible_node(np, NULL, "ucc_geth") {
	239	struct resource tempres;
	240
	241	err = of_address_to_resource(np, 0, &tempres);
	242	if (err)
	243	continue;
	244
	245	/* if our mdio regs fall within this UCC regs range */
	246	if ((start >= tempres.start) && (end <= tempres.end)) {
	247	/* Find the id of the UCC */
	248	const u32 *id;
	249
	250	id = of_get_property(np, "cell-index", NULL);
	251	if (!id) {
	252	id = of_get_property(np, "device-id", NULL);
	253	if (!id)
	254	continue;
	255	}
	256
	257	ucc_id = id;
	258
	259	return 0;
	260	}
	261	}
	262
	263	if (err)
	264	return err;
	265	else
	266	return -EINVAL;
952c5ca1 AF	267	#else
952c5ca1 AF	268	return -ENODEV;
1577ecef	269	#endif
952c5ca1	270	}
1577ecef	271
74888760	272	static int fsl_pq_mdio_probe(struct platform_device *ofdev)
1577ecef	273	{
61c7a080	274	struct device_node *np = ofdev->dev.of_node;
1577ecef	275	struct device_node *tbi;
b3319b10	276	struct fsl_pq_mdio_priv *priv;
1d2397d7	277	struct fsl_pq_mdio __iomem *regs = NULL;
2951d64e	278	void __iomem *map;
1577ecef AF	279	u32 __iomem *tbipa;
	280	struct mii_bus *new_bus;
	281	int tbiaddr = -1;
3b1fd3e5	282	const u32 *addrp;
2951d64e	283	u64 addr = 0, size = 0;
08d18f3b	284	int err;
1577ecef	285
b3319b10 AV	286	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	287	if (!priv)
	288	return -ENOMEM;
	289
1577ecef	290	new_bus = mdiobus_alloc();
08d18f3b AV	291	if (!new_bus) {
08d18f3b AV	292	err = -ENOMEM;
b3319b10	293	goto err_free_priv;
08d18f3b	294	}
1577ecef AF	295
	296	new_bus->name = "Freescale PowerQUICC MII Bus",
	297	new_bus->read = &fsl_pq_mdio_read,
	298	new_bus->write = &fsl_pq_mdio_write,
	299	new_bus->reset = &fsl_pq_mdio_reset,
b3319b10	300	new_bus->priv = priv;
1577ecef AF	301	fsl_pq_mdio_bus_name(new_bus->id, np);
1577ecef AF	302
3b1fd3e5 AV	303	addrp = of_get_address(np, 0, &size, NULL);
	304	if (!addrp) {
	305	err = -EINVAL;
	306	goto err_free_bus;
	307	}
	308
1577ecef	309	/* Set the PHY base address */
3b1fd3e5 AV	310	addr = of_translate_address(np, addrp);
	311	if (addr == OF_BAD_ADDR) {
	312	err = -EINVAL;
	313	goto err_free_bus;
	314	}
	315
2951d64e AV	316	map = ioremap(addr, size);
2951d64e AV	317	if (!map) {
1577ecef AF	318	err = -ENOMEM;
	319	goto err_free_bus;
	320	}
b3319b10	321	priv->map = map;
1577ecef	322
2951d64e AV	323	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
	324	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
	325	of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
	326	of_device_is_compatible(np, "ucc_geth_phy"))
	327	map -= offsetof(struct fsl_pq_mdio, miimcfg);
	328	regs = map;
b3319b10	329	priv->regs = regs;
1577ecef	330
324931ba	331	new_bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1577ecef AF	332
	333	if (NULL == new_bus->irq) {
	334	err = -ENOMEM;
	335	goto err_unmap_regs;
	336	}
	337
	338	new_bus->parent = &ofdev->dev;
	339	dev_set_drvdata(&ofdev->dev, new_bus);
	340
	341	if (of_device_is_compatible(np, "fsl,gianfar-mdio") \|\|
30196845	342	of_device_is_compatible(np, "fsl,gianfar-tbi") \|\|
1d2397d7 SG	343	of_device_is_compatible(np, "fsl,etsec2-mdio") \|\|
1d2397d7 SG	344	of_device_is_compatible(np, "fsl,etsec2-tbi") \|\|
1577ecef	345	of_device_is_compatible(np, "gianfar")) {
1d2397d7 SG	346	tbipa = get_gfar_tbipa(regs, np);
	347	if (!tbipa) {
	348	err = -EINVAL;
	349	goto err_free_irqs;
	350	}
1577ecef AF	351	} else if (of_device_is_compatible(np, "fsl,ucc-mdio") \|\|
1577ecef AF	352	of_device_is_compatible(np, "ucc_geth_phy")) {
1577ecef	353	u32 id;
fbcc0e2c	354	static u32 mii_mng_master;
1577ecef AF	355
	356	tbipa = &regs->utbipar;
	357
	358	if ((err = get_ucc_id_for_range(addr, addr + size, &id)))
	359	goto err_free_irqs;
	360
fbcc0e2c HW	361	if (!mii_mng_master) {
	362	mii_mng_master = id;
	363	ucc_set_qe_mux_mii_mng(id - 1);
	364	}
1577ecef AF	365	} else {
	366	err = -ENODEV;
	367	goto err_free_irqs;
	368	}
	369
	370	for_each_child_of_node(np, tbi) {
	371	if (!strncmp(tbi->type, "tbi-phy", 8))
	372	break;
	373	}
	374
	375	if (tbi) {
	376	const u32 *prop = of_get_property(tbi, "reg", NULL);
	377
	378	if (prop)
	379	tbiaddr = *prop;
1577ecef	380
464b57da KE	381	if (tbiaddr == -1) {
	382	err = -EBUSY;
	383	goto err_free_irqs;
	384	} else {
	385	out_be32(tbipa, tbiaddr);
	386	}
1577ecef AF	387	}
1577ecef AF	388
324931ba	389	err = of_mdiobus_register(new_bus, np);
1577ecef AF	390	if (err) {
	391	printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
	392	new_bus->name);
	393	goto err_free_irqs;
	394	}
	395
	396	return 0;
	397
	398	err_free_irqs:
	399	kfree(new_bus->irq);
	400	err_unmap_regs:
b3319b10	401	iounmap(priv->map);
1577ecef AF	402	err_free_bus:
1577ecef AF	403	kfree(new_bus);
b3319b10 AV	404	err_free_priv:
b3319b10 AV	405	kfree(priv);
1577ecef AF	406	return err;
	407	}
	408
	409
2dc11581	410	static int fsl_pq_mdio_remove(struct platform_device *ofdev)
1577ecef AF	411	{
	412	struct device *device = &ofdev->dev;
	413	struct mii_bus *bus = dev_get_drvdata(device);
b3319b10	414	struct fsl_pq_mdio_priv *priv = bus->priv;
1577ecef AF	415
	416	mdiobus_unregister(bus);
	417
	418	dev_set_drvdata(device, NULL);
	419
b3319b10	420	iounmap(priv->map);
1577ecef AF	421	bus->priv = NULL;
1577ecef AF	422	mdiobus_free(bus);
b3319b10	423	kfree(priv);
1577ecef AF	424
	425	return 0;
	426	}
	427
	428	static struct of_device_id fsl_pq_mdio_match[] = {
	429	{
	430	.type = "mdio",
	431	.compatible = "ucc_geth_phy",
	432	},
	433	{
	434	.type = "mdio",
	435	.compatible = "gianfar",
	436	},
	437	{
	438	.compatible = "fsl,ucc-mdio",
	439	},
	440	{
	441	.compatible = "fsl,gianfar-tbi",
	442	},
	443	{
	444	.compatible = "fsl,gianfar-mdio",
	445	},
1d2397d7 SG	446	{
	447	.compatible = "fsl,etsec2-tbi",
	448	},
	449	{
	450	.compatible = "fsl,etsec2-mdio",
	451	},
1577ecef AF	452	{},
1577ecef AF	453	};
e72701ac	454	MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
1577ecef	455
74888760	456	static struct platform_driver fsl_pq_mdio_driver = {
4018294b GL	457	.driver = {
	458	.name = "fsl-pq_mdio",
	459	.owner = THIS_MODULE,
	460	.of_match_table = fsl_pq_mdio_match,
	461	},
1577ecef AF	462	.probe = fsl_pq_mdio_probe,
1577ecef AF	463	.remove = fsl_pq_mdio_remove,
1577ecef AF	464	};
1577ecef AF	465
db62f684	466	module_platform_driver(fsl_pq_mdio_driver);
1577ecef	467
26062897	468	MODULE_LICENSE("GPL");