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Merge tag 'linux-can-next-for-4.2-20150506' of git://git.kernel.org/pub/scm/linux...
[deliverable/linux.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0977f817 1/* drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 2 *
3 * Gianfar Ethernet Driver
7f7f5316
AF		 4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
20862788 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
a12f801d 13 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Gianfar: AKA Lambda Draconis, "Dragon"
21 * RA 11 31 24.2
22 * Dec +69 19 52
23 * V 3.84
24 * B-V +1.62
25 *
26 * Theory of operation
0bbaf069 27 *
b31a1d8b
AF		 28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 30 *
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 35 * last descriptor of the ring.
36 *
37 * When a packet is received, the RXF bit in the
0bbaf069 38 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
bb40dcbb 42 * of frames or amount of time have passed). In NAPI, the
1da177e4 43 * interrupt handler will signal there is work to be done, and
0aa1538f 44 * exit. This method will start at the last known empty
0bbaf069 45 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
52 * skb.
53 *
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
62 */
63
59deab26
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65#define DEBUG
66
1da177e4 67#include <linux/kernel.h>
1da177e4
LT		 68#include <linux/string.h>
69#include <linux/errno.h>
bb40dcbb 70#include <linux/unistd.h>
1da177e4
LT		 71#include <linux/slab.h>
72#include <linux/interrupt.h>
1da177e4
LT		 73#include <linux/delay.h>
74#include <linux/netdevice.h>
75#include <linux/etherdevice.h>
76#include <linux/skbuff.h>
0bbaf069 77#include <linux/if_vlan.h>
1da177e4
LT		 78#include <linux/spinlock.h>
79#include <linux/mm.h>
5af50730
RH		 80#include <linux/of_address.h>
81#include <linux/of_irq.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
d6ef0bcc 91#ifdef CONFIG_PPC
7d350977 92#include <asm/reg.h>
2969b1f7 93#include <asm/mpc85xx.h>
d6ef0bcc 94#endif
1da177e4
LT		 95#include <asm/irq.h>
96#include <asm/uaccess.h>
97#include <linux/module.h>
1da177e4
LT		 98#include <linux/dma-mapping.h>
99#include <linux/crc32.h>
bb40dcbb
AF		 100#include <linux/mii.h>
101#include <linux/phy.h>
b31a1d8b
AF		 102#include <linux/phy_fixed.h>
103#include <linux/of.h>
4b6ba8aa 104#include <linux/of_net.h>
fd31a952
CM		 105#include <linux/of_address.h>
106#include <linux/of_irq.h>
1da177e4
LT		 107
108#include "gianfar.h"
1da177e4
LT		 109
110#define TX_TIMEOUT (1*HZ)
1da177e4 111
7f7f5316 112const char gfar_driver_version[] = "1.3";
1da177e4 113
1da177e4
LT		 114static int gfar_enet_open(struct net_device *dev);
115static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 116static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 117static void gfar_timeout(struct net_device *dev);
118static int gfar_close(struct net_device *dev);
91c53f76
KH		 119static struct sk_buff *gfar_new_skb(struct net_device *dev,
120 dma_addr_t *bufaddr);
1da177e4
LT		 121static int gfar_set_mac_address(struct net_device *dev);
122static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 123static irqreturn_t gfar_error(int irq, void *dev_id);
124static irqreturn_t gfar_transmit(int irq, void *dev_id);
125static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4 126static void adjust_link(struct net_device *dev);
6ce29b0e 127static noinline void gfar_update_link_state(struct gfar_private *priv);
1da177e4 128static int init_phy(struct net_device *dev);
74888760 129static int gfar_probe(struct platform_device *ofdev);
2dc11581 130static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 131static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 132static void gfar_set_multi(struct net_device *dev);
133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 134static void gfar_configure_serdes(struct net_device *dev);
aeb12c5e
CM		 135static int gfar_poll_rx(struct napi_struct *napi, int budget);
136static int gfar_poll_tx(struct napi_struct *napi, int budget);
137static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
f2d71c2d
VW		 139#ifdef CONFIG_NET_POLL_CONTROLLER
140static void gfar_netpoll(struct net_device *dev);
141#endif
a12f801d 142int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
c233cf40 143static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
61db26c6
CM		 144static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
145 int amount_pull, struct napi_struct *napi);
c10650b6 146static void gfar_halt_nodisable(struct gfar_private *priv);
7f7f5316 147static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 148static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 const u8 *addr);
26ccfc37 150static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 151
1da177e4
LT		 152MODULE_AUTHOR("Freescale Semiconductor, Inc");
153MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154MODULE_LICENSE("GPL");
155
a12f801d 156static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 157 dma_addr_t buf)
158{
8a102fe0
AV		 159 u32 lstatus;
160
a7312d58 161 bdp->bufPtr = cpu_to_be32(buf);
8a102fe0
AV		 162
163 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 164 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 165 lstatus |= BD_LFLAG(RXBD_WRAP);
166
d55398ba 167 gfar_wmb();
8a102fe0 168
a7312d58 169 bdp->lstatus = cpu_to_be32(lstatus);
8a102fe0
AV		 170}
171
8728327e 172static int gfar_init_bds(struct net_device *ndev)
826aa4a0 173{
8728327e 174 struct gfar_private *priv = netdev_priv(ndev);
45b679c9 175 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a12f801d
SG		 176 struct gfar_priv_tx_q *tx_queue = NULL;
177 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 178 struct txbd8 *txbdp;
179 struct rxbd8 *rxbdp;
03366a33 180 u32 __iomem *rfbptr;
fba4ed03 181 int i, j;
0a4b5a24 182 dma_addr_t bufaddr;
a12f801d 183
fba4ed03
SG		 184 for (i = 0; i < priv->num_tx_queues; i++) {
185 tx_queue = priv->tx_queue[i];
186 /* Initialize some variables in our dev structure */
187 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
188 tx_queue->dirty_tx = tx_queue->tx_bd_base;
189 tx_queue->cur_tx = tx_queue->tx_bd_base;
190 tx_queue->skb_curtx = 0;
191 tx_queue->skb_dirtytx = 0;
192
193 /* Initialize Transmit Descriptor Ring */
194 txbdp = tx_queue->tx_bd_base;
195 for (j = 0; j < tx_queue->tx_ring_size; j++) {
196 txbdp->lstatus = 0;
197 txbdp->bufPtr = 0;
198 txbdp++;
199 }
8728327e 200
fba4ed03
SG		 201 /* Set the last descriptor in the ring to indicate wrap */
202 txbdp--;
a7312d58
CM		 203 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 TXBD_WRAP);
8728327e
AV		 205 }
206
45b679c9 207 rfbptr = &regs->rfbptr0;
fba4ed03
SG		 208 for (i = 0; i < priv->num_rx_queues; i++) {
209 rx_queue = priv->rx_queue[i];
210 rx_queue->cur_rx = rx_queue->rx_bd_base;
211 rx_queue->skb_currx = 0;
212 rxbdp = rx_queue->rx_bd_base;
8728327e 213
fba4ed03
SG		 214 for (j = 0; j < rx_queue->rx_ring_size; j++) {
215 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 216
fba4ed03 217 if (skb) {
a7312d58 218 bufaddr = be32_to_cpu(rxbdp->bufPtr);
fba4ed03 219 } else {
0a4b5a24 220 skb = gfar_new_skb(ndev, &bufaddr);
fba4ed03 221 if (!skb) {
59deab26 222 netdev_err(ndev, "Can't allocate RX buffers\n");
1eb8f7a7 223 return -ENOMEM;
fba4ed03
SG		 224 }
225 rx_queue->rx_skbuff[j] = skb;
8728327e 226 }
8728327e 227
0a4b5a24 228 gfar_init_rxbdp(rx_queue, rxbdp, bufaddr);
fba4ed03 229 rxbdp++;
8728327e
AV		 230 }
231
45b679c9
MP		 232 rx_queue->rfbptr = rfbptr;
233 rfbptr += 2;
8728327e
AV		 234 }
235
236 return 0;
237}
238
239static int gfar_alloc_skb_resources(struct net_device *ndev)
240{
826aa4a0 241 void *vaddr;
fba4ed03
SG		 242 dma_addr_t addr;
243 int i, j, k;
826aa4a0 244 struct gfar_private *priv = netdev_priv(ndev);
369ec162 245 struct device *dev = priv->dev;
a12f801d
SG		 246 struct gfar_priv_tx_q *tx_queue = NULL;
247 struct gfar_priv_rx_q *rx_queue = NULL;
248
fba4ed03
SG		 249 priv->total_tx_ring_size = 0;
250 for (i = 0; i < priv->num_tx_queues; i++)
251 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
252
253 priv->total_rx_ring_size = 0;
254 for (i = 0; i < priv->num_rx_queues; i++)
255 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 256
257 /* Allocate memory for the buffer descriptors */
8728327e 258 vaddr = dma_alloc_coherent(dev,
d0320f75
JP		 259 (priv->total_tx_ring_size *
260 sizeof(struct txbd8)) +
261 (priv->total_rx_ring_size *
262 sizeof(struct rxbd8)),
263 &addr, GFP_KERNEL);
264 if (!vaddr)
826aa4a0 265 return -ENOMEM;
826aa4a0 266
fba4ed03
SG		 267 for (i = 0; i < priv->num_tx_queues; i++) {
268 tx_queue = priv->tx_queue[i];
43d620c8 269 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 270 tx_queue->tx_bd_dma_base = addr;
271 tx_queue->dev = ndev;
272 /* enet DMA only understands physical addresses */
bc4598bc
JC		 273 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
274 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
fba4ed03 275 }
826aa4a0 276
826aa4a0 277 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 278 for (i = 0; i < priv->num_rx_queues; i++) {
279 rx_queue = priv->rx_queue[i];
43d620c8 280 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 281 rx_queue->rx_bd_dma_base = addr;
282 rx_queue->dev = ndev;
bc4598bc
JC		 283 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
284 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
fba4ed03 285 }
826aa4a0
AV		 286
287 /* Setup the skbuff rings */
fba4ed03
SG		 288 for (i = 0; i < priv->num_tx_queues; i++) {
289 tx_queue = priv->tx_queue[i];
14f8dc49
JP		 290 tx_queue->tx_skbuff =
291 kmalloc_array(tx_queue->tx_ring_size,
292 sizeof(*tx_queue->tx_skbuff),
293 GFP_KERNEL);
294 if (!tx_queue->tx_skbuff)
fba4ed03 295 goto cleanup;
826aa4a0 296
fba4ed03
SG		 297 for (k = 0; k < tx_queue->tx_ring_size; k++)
298 tx_queue->tx_skbuff[k] = NULL;
299 }
826aa4a0 300
fba4ed03
SG		 301 for (i = 0; i < priv->num_rx_queues; i++) {
302 rx_queue = priv->rx_queue[i];
14f8dc49
JP		 303 rx_queue->rx_skbuff =
304 kmalloc_array(rx_queue->rx_ring_size,
305 sizeof(*rx_queue->rx_skbuff),
306 GFP_KERNEL);
307 if (!rx_queue->rx_skbuff)
fba4ed03 308 goto cleanup;
fba4ed03
SG		 309
310 for (j = 0; j < rx_queue->rx_ring_size; j++)
311 rx_queue->rx_skbuff[j] = NULL;
312 }
826aa4a0 313
8728327e
AV		 314 if (gfar_init_bds(ndev))
315 goto cleanup;
826aa4a0
AV		 316
317 return 0;
318
319cleanup:
320 free_skb_resources(priv);
321 return -ENOMEM;
322}
323
fba4ed03
SG		 324static void gfar_init_tx_rx_base(struct gfar_private *priv)
325{
46ceb60c 326 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 327 u32 __iomem *baddr;
fba4ed03
SG		 328 int i;
329
330 baddr = &regs->tbase0;
bc4598bc 331 for (i = 0; i < priv->num_tx_queues; i++) {
fba4ed03 332 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
bc4598bc 333 baddr += 2;
fba4ed03
SG		 334 }
335
336 baddr = &regs->rbase0;
bc4598bc 337 for (i = 0; i < priv->num_rx_queues; i++) {
fba4ed03 338 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
bc4598bc 339 baddr += 2;
fba4ed03
SG		 340 }
341}
342
45b679c9
MP		 343static void gfar_init_rqprm(struct gfar_private *priv)
344{
345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
346 u32 __iomem *baddr;
347 int i;
348
349 baddr = &regs->rqprm0;
350 for (i = 0; i < priv->num_rx_queues; i++) {
351 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
352 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
353 baddr++;
354 }
355}
356
88302648 357static void gfar_rx_buff_size_config(struct gfar_private *priv)
826aa4a0 358{
f5b720b8 359 int frame_size = priv->ndev->mtu + ETH_HLEN + ETH_FCS_LEN;
fba4ed03 360
ba779711
CM		 361 /* set this when rx hw offload (TOE) functions are being used */
362 priv->uses_rxfcb = 0;
363
88302648
CM		 364 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
365 priv->uses_rxfcb = 1;
366
367 if (priv->hwts_rx_en)
368 priv->uses_rxfcb = 1;
369
370 if (priv->uses_rxfcb)
371 frame_size += GMAC_FCB_LEN;
372
373 frame_size += priv->padding;
374
375 frame_size = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
376 INCREMENTAL_BUFFER_SIZE;
377
378 priv->rx_buffer_size = frame_size;
379}
380
381static void gfar_mac_rx_config(struct gfar_private *priv)
382{
383 struct gfar __iomem *regs = priv->gfargrp[0].regs;
384 u32 rctrl = 0;
385
1ccb8389 386 if (priv->rx_filer_enable) {
fba4ed03 387 rctrl |= RCTRL_FILREN;
1ccb8389 388 /* Program the RIR0 reg with the required distribution */
71ff9e3d
CM		 389 if (priv->poll_mode == GFAR_SQ_POLLING)
390 gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
391 else /* GFAR_MQ_POLLING */
392 gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
1ccb8389 393 }
826aa4a0 394
f5ae6279 395 /* Restore PROMISC mode */
a328ac92 396 if (priv->ndev->flags & IFF_PROMISC)
f5ae6279
CM		 397 rctrl |= RCTRL_PROM;
398
88302648 399 if (priv->ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 400 rctrl |= RCTRL_CHECKSUMMING;
401
88302648
CM		 402 if (priv->extended_hash)
403 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
826aa4a0
AV		 404
405 if (priv->padding) {
406 rctrl &= ~RCTRL_PAL_MASK;
407 rctrl |= RCTRL_PADDING(priv->padding);
408 }
409
97553f7f 410 /* Enable HW time stamping if requested from user space */
88302648 411 if (priv->hwts_rx_en)
97553f7f
MR		 412 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
413
88302648 414 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
b852b720 415 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0 416
45b679c9
MP		 417 /* Clear the LFC bit */
418 gfar_write(&regs->rctrl, rctrl);
419 /* Init flow control threshold values */
420 gfar_init_rqprm(priv);
421 gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
422 rctrl |= RCTRL_LFC;
423
826aa4a0
AV		 424 /* Init rctrl based on our settings */
425 gfar_write(&regs->rctrl, rctrl);
a328ac92 426}
826aa4a0 427
a328ac92
CM		 428static void gfar_mac_tx_config(struct gfar_private *priv)
429{
430 struct gfar __iomem *regs = priv->gfargrp[0].regs;
431 u32 tctrl = 0;
432
433 if (priv->ndev->features & NETIF_F_IP_CSUM)
826aa4a0
AV		 434 tctrl |= TCTRL_INIT_CSUM;
435
b98b8bab
CM		 436 if (priv->prio_sched_en)
437 tctrl |= TCTRL_TXSCHED_PRIO;
438 else {
439 tctrl |= TCTRL_TXSCHED_WRRS;
440 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
441 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
442 }
fba4ed03 443
88302648
CM		 444 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
445 tctrl |= TCTRL_VLINS;
446
826aa4a0 447 gfar_write(&regs->tctrl, tctrl);
826aa4a0
AV		 448}
449
f19015ba
CM		 450static void gfar_configure_coalescing(struct gfar_private *priv,
451 unsigned long tx_mask, unsigned long rx_mask)
452{
453 struct gfar __iomem *regs = priv->gfargrp[0].regs;
454 u32 __iomem *baddr;
455
456 if (priv->mode == MQ_MG_MODE) {
457 int i = 0;
458
459 baddr = &regs->txic0;
460 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
461 gfar_write(baddr + i, 0);
462 if (likely(priv->tx_queue[i]->txcoalescing))
463 gfar_write(baddr + i, priv->tx_queue[i]->txic);
464 }
465
466 baddr = &regs->rxic0;
467 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
468 gfar_write(baddr + i, 0);
469 if (likely(priv->rx_queue[i]->rxcoalescing))
470 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
471 }
472 } else {
473 /* Backward compatible case -- even if we enable
474 * multiple queues, there's only single reg to program
475 */
476 gfar_write(&regs->txic, 0);
477 if (likely(priv->tx_queue[0]->txcoalescing))
478 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
479
480 gfar_write(&regs->rxic, 0);
481 if (unlikely(priv->rx_queue[0]->rxcoalescing))
482 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
483 }
484}
485
486void gfar_configure_coalescing_all(struct gfar_private *priv)
487{
488 gfar_configure_coalescing(priv, 0xFF, 0xFF);
489}
490
a7f38041
SG		 491static struct net_device_stats *gfar_get_stats(struct net_device *dev)
492{
493 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 494 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
495 unsigned long tx_packets = 0, tx_bytes = 0;
3a2e16c8 496 int i;
a7f38041
SG		 497
498 for (i = 0; i < priv->num_rx_queues; i++) {
499 rx_packets += priv->rx_queue[i]->stats.rx_packets;
bc4598bc 500 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
a7f38041
SG		 501 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
502 }
503
504 dev->stats.rx_packets = rx_packets;
bc4598bc 505 dev->stats.rx_bytes = rx_bytes;
a7f38041
SG		 506 dev->stats.rx_dropped = rx_dropped;
507
508 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 509 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
510 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 511 }
512
bc4598bc 513 dev->stats.tx_bytes = tx_bytes;
a7f38041
SG		 514 dev->stats.tx_packets = tx_packets;
515
516 return &dev->stats;
517}
518
3d23a05c
CM		 519static int gfar_set_mac_addr(struct net_device *dev, void *p)
520{
521 eth_mac_addr(dev, p);
522
523 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
524
525 return 0;
526}
527
26ccfc37
AF		 528static const struct net_device_ops gfar_netdev_ops = {
529 .ndo_open = gfar_enet_open,
530 .ndo_start_xmit = gfar_start_xmit,
531 .ndo_stop = gfar_close,
532 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 533 .ndo_set_features = gfar_set_features,
afc4b13d 534 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 535 .ndo_tx_timeout = gfar_timeout,
536 .ndo_do_ioctl = gfar_ioctl,
a7f38041 537 .ndo_get_stats = gfar_get_stats,
3d23a05c 538 .ndo_set_mac_address = gfar_set_mac_addr,
240c102d 539 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 540#ifdef CONFIG_NET_POLL_CONTROLLER
541 .ndo_poll_controller = gfar_netpoll,
542#endif
543};
544
efeddce7
CM		 545static void gfar_ints_disable(struct gfar_private *priv)
546{
547 int i;
548 for (i = 0; i < priv->num_grps; i++) {
549 struct gfar __iomem *regs = priv->gfargrp[i].regs;
550 /* Clear IEVENT */
551 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
552
553 /* Initialize IMASK */
554 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
555 }
556}
557
558static void gfar_ints_enable(struct gfar_private *priv)
559{
560 int i;
561 for (i = 0; i < priv->num_grps; i++) {
562 struct gfar __iomem *regs = priv->gfargrp[i].regs;
563 /* Unmask the interrupts we look for */
564 gfar_write(&regs->imask, IMASK_DEFAULT);
565 }
566}
567
91c53f76 568static void lock_tx_qs(struct gfar_private *priv)
fba4ed03 569{
3a2e16c8 570 int i;
fba4ed03
SG		 571
572 for (i = 0; i < priv->num_tx_queues; i++)
573 spin_lock(&priv->tx_queue[i]->txlock);
574}
575
91c53f76 576static void unlock_tx_qs(struct gfar_private *priv)
fba4ed03 577{
3a2e16c8 578 int i;
fba4ed03
SG		 579
580 for (i = 0; i < priv->num_tx_queues; i++)
581 spin_unlock(&priv->tx_queue[i]->txlock);
582}
583
20862788
CM		 584static int gfar_alloc_tx_queues(struct gfar_private *priv)
585{
586 int i;
587
588 for (i = 0; i < priv->num_tx_queues; i++) {
589 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
590 GFP_KERNEL);
591 if (!priv->tx_queue[i])
592 return -ENOMEM;
593
594 priv->tx_queue[i]->tx_skbuff = NULL;
595 priv->tx_queue[i]->qindex = i;
596 priv->tx_queue[i]->dev = priv->ndev;
597 spin_lock_init(&(priv->tx_queue[i]->txlock));
598 }
599 return 0;
600}
601
602static int gfar_alloc_rx_queues(struct gfar_private *priv)
603{
604 int i;
605
606 for (i = 0; i < priv->num_rx_queues; i++) {
607 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
608 GFP_KERNEL);
609 if (!priv->rx_queue[i])
610 return -ENOMEM;
611
612 priv->rx_queue[i]->rx_skbuff = NULL;
613 priv->rx_queue[i]->qindex = i;
614 priv->rx_queue[i]->dev = priv->ndev;
20862788
CM		 615 }
616 return 0;
617}
618
619static void gfar_free_tx_queues(struct gfar_private *priv)
fba4ed03 620{
3a2e16c8 621 int i;
fba4ed03
SG		 622
623 for (i = 0; i < priv->num_tx_queues; i++)
624 kfree(priv->tx_queue[i]);
625}
626
20862788 627static void gfar_free_rx_queues(struct gfar_private *priv)
fba4ed03 628{
3a2e16c8 629 int i;
fba4ed03
SG		 630
631 for (i = 0; i < priv->num_rx_queues; i++)
632 kfree(priv->rx_queue[i]);
633}
634
46ceb60c
SG		 635static void unmap_group_regs(struct gfar_private *priv)
636{
3a2e16c8 637 int i;
46ceb60c
SG		 638
639 for (i = 0; i < MAXGROUPS; i++)
640 if (priv->gfargrp[i].regs)
641 iounmap(priv->gfargrp[i].regs);
642}
643
ee873fda
CM		 644static void free_gfar_dev(struct gfar_private *priv)
645{
646 int i, j;
647
648 for (i = 0; i < priv->num_grps; i++)
649 for (j = 0; j < GFAR_NUM_IRQS; j++) {
650 kfree(priv->gfargrp[i].irqinfo[j]);
651 priv->gfargrp[i].irqinfo[j] = NULL;
652 }
653
654 free_netdev(priv->ndev);
655}
656
46ceb60c
SG		 657static void disable_napi(struct gfar_private *priv)
658{
3a2e16c8 659 int i;
46ceb60c 660
aeb12c5e
CM		 661 for (i = 0; i < priv->num_grps; i++) {
662 napi_disable(&priv->gfargrp[i].napi_rx);
663 napi_disable(&priv->gfargrp[i].napi_tx);
664 }
46ceb60c
SG		 665}
666
667static void enable_napi(struct gfar_private *priv)
668{
3a2e16c8 669 int i;
46ceb60c 670
aeb12c5e
CM		 671 for (i = 0; i < priv->num_grps; i++) {
672 napi_enable(&priv->gfargrp[i].napi_rx);
673 napi_enable(&priv->gfargrp[i].napi_tx);
674 }
46ceb60c
SG		 675}
676
677static int gfar_parse_group(struct device_node *np,
bc4598bc 678 struct gfar_private *priv, const char *model)
46ceb60c 679{
5fedcc14 680 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
ee873fda
CM		 681 int i;
682
7c1e7e99
PG		 683 for (i = 0; i < GFAR_NUM_IRQS; i++) {
684 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
685 GFP_KERNEL);
686 if (!grp->irqinfo[i])
ee873fda 687 return -ENOMEM;
ee873fda 688 }
46ceb60c 689
5fedcc14
CM		 690 grp->regs = of_iomap(np, 0);
691 if (!grp->regs)
46ceb60c
SG		 692 return -ENOMEM;
693
ee873fda 694 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
46ceb60c
SG		 695
696 /* If we aren't the FEC we have multiple interrupts */
697 if (model && strcasecmp(model, "FEC")) {
ee873fda
CM		 698 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
699 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
700 if (gfar_irq(grp, TX)->irq == NO_IRQ ||
701 gfar_irq(grp, RX)->irq == NO_IRQ ||
702 gfar_irq(grp, ER)->irq == NO_IRQ)
46ceb60c 703 return -EINVAL;
46ceb60c
SG		 704 }
705
5fedcc14
CM		 706 grp->priv = priv;
707 spin_lock_init(&grp->grplock);
bc4598bc 708 if (priv->mode == MQ_MG_MODE) {
55917641
JL		 709 u32 rxq_mask, txq_mask;
710 int ret;
711
712 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
713 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
714
715 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
716 if (!ret) {
717 grp->rx_bit_map = rxq_mask ?
718 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
719 }
720
721 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
722 if (!ret) {
723 grp->tx_bit_map = txq_mask ?
724 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
725 }
71ff9e3d
CM		 726
727 if (priv->poll_mode == GFAR_SQ_POLLING) {
728 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
729 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
730 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
71ff9e3d 731 }
46ceb60c 732 } else {
5fedcc14
CM		 733 grp->rx_bit_map = 0xFF;
734 grp->tx_bit_map = 0xFF;
46ceb60c 735 }
20862788
CM		 736
737 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
738 * right to left, so we need to revert the 8 bits to get the q index
739 */
740 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
741 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
742
743 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
744 * also assign queues to groups
745 */
746 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
71ff9e3d
CM		 747 if (!grp->rx_queue)
748 grp->rx_queue = priv->rx_queue[i];
20862788
CM		 749 grp->num_rx_queues++;
750 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
751 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
752 priv->rx_queue[i]->grp = grp;
753 }
754
755 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
71ff9e3d
CM		 756 if (!grp->tx_queue)
757 grp->tx_queue = priv->tx_queue[i];
20862788
CM		 758 grp->num_tx_queues++;
759 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
760 priv->tqueue |= (TQUEUE_EN0 >> i);
761 priv->tx_queue[i]->grp = grp;
762 }
763
46ceb60c
SG		 764 priv->num_grps++;
765
766 return 0;
767}
768
f50724cd
TW		 769static int gfar_of_group_count(struct device_node *np)
770{
771 struct device_node *child;
772 int num = 0;
773
774 for_each_available_child_of_node(np, child)
775 if (!of_node_cmp(child->name, "queue-group"))
776 num++;
777
778 return num;
779}
780
2dc11581 781static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 782{
b31a1d8b
AF		 783 const char *model;
784 const char *ctype;
785 const void *mac_addr;
fba4ed03
SG		 786 int err = 0, i;
787 struct net_device *dev = NULL;
788 struct gfar_private *priv = NULL;
61c7a080 789 struct device_node *np = ofdev->dev.of_node;
46ceb60c 790 struct device_node *child = NULL;
55917641
JL		 791 struct property *stash;
792 u32 stash_len = 0;
793 u32 stash_idx = 0;
fba4ed03 794 unsigned int num_tx_qs, num_rx_qs;
b338ce27 795 unsigned short mode, poll_mode;
b31a1d8b 796
4b222ca6 797 if (!np)
b31a1d8b
AF		 798 return -ENODEV;
799
b338ce27
CM		 800 if (of_device_is_compatible(np, "fsl,etsec2")) {
801 mode = MQ_MG_MODE;
802 poll_mode = GFAR_SQ_POLLING;
803 } else {
804 mode = SQ_SG_MODE;
805 poll_mode = GFAR_SQ_POLLING;
806 }
807
b338ce27 808 if (mode == SQ_SG_MODE) {
71ff9e3d
CM		 809 num_tx_qs = 1;
810 num_rx_qs = 1;
811 } else { /* MQ_MG_MODE */
c65d7533 812 /* get the actual number of supported groups */
f50724cd 813 unsigned int num_grps = gfar_of_group_count(np);
c65d7533
CM		 814
815 if (num_grps == 0 || num_grps > MAXGROUPS) {
816 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
817 num_grps);
818 pr_err("Cannot do alloc_etherdev, aborting\n");
819 return -EINVAL;
820 }
821
b338ce27 822 if (poll_mode == GFAR_SQ_POLLING) {
c65d7533
CM		 823 num_tx_qs = num_grps; /* one txq per int group */
824 num_rx_qs = num_grps; /* one rxq per int group */
71ff9e3d 825 } else { /* GFAR_MQ_POLLING */
55917641
JL		 826 u32 tx_queues, rx_queues;
827 int ret;
828
829 /* parse the num of HW tx and rx queues */
830 ret = of_property_read_u32(np, "fsl,num_tx_queues",
831 &tx_queues);
832 num_tx_qs = ret ? 1 : tx_queues;
833
834 ret = of_property_read_u32(np, "fsl,num_rx_queues",
835 &rx_queues);
836 num_rx_qs = ret ? 1 : rx_queues;
71ff9e3d
CM		 837 }
838 }
fba4ed03
SG		 839
840 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 841 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
842 num_tx_qs, MAX_TX_QS);
843 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 844 return -EINVAL;
845 }
846
fba4ed03 847 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 848 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
849 num_rx_qs, MAX_RX_QS);
850 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 851 return -EINVAL;
852 }
853
854 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
855 dev = *pdev;
856 if (NULL == dev)
857 return -ENOMEM;
858
859 priv = netdev_priv(dev);
fba4ed03
SG		 860 priv->ndev = dev;
861
b338ce27
CM		 862 priv->mode = mode;
863 priv->poll_mode = poll_mode;
864
fba4ed03 865 priv->num_tx_queues = num_tx_qs;
fe069123 866 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 867 priv->num_rx_queues = num_rx_qs;
20862788
CM		 868
869 err = gfar_alloc_tx_queues(priv);
870 if (err)
871 goto tx_alloc_failed;
872
873 err = gfar_alloc_rx_queues(priv);
874 if (err)
875 goto rx_alloc_failed;
b31a1d8b 876
55917641
JL		 877 err = of_property_read_string(np, "model", &model);
878 if (err) {
879 pr_err("Device model property missing, aborting\n");
880 goto rx_alloc_failed;
881 }
882
0977f817 883 /* Init Rx queue filer rule set linked list */
4aa3a715
SP		 884 INIT_LIST_HEAD(&priv->rx_list.list);
885 priv->rx_list.count = 0;
886 mutex_init(&priv->rx_queue_access);
887
46ceb60c
SG		 888 for (i = 0; i < MAXGROUPS; i++)
889 priv->gfargrp[i].regs = NULL;
b31a1d8b 890
46ceb60c 891 /* Parse and initialize group specific information */
b338ce27 892 if (priv->mode == MQ_MG_MODE) {
f50724cd
TW		 893 for_each_available_child_of_node(np, child) {
894 if (of_node_cmp(child->name, "queue-group"))
895 continue;
896
46ceb60c
SG		 897 err = gfar_parse_group(child, priv, model);
898 if (err)
899 goto err_grp_init;
b31a1d8b 900 }
b338ce27 901 } else { /* SQ_SG_MODE */
46ceb60c 902 err = gfar_parse_group(np, priv, model);
bc4598bc 903 if (err)
46ceb60c 904 goto err_grp_init;
b31a1d8b
AF		 905 }
906
55917641 907 stash = of_find_property(np, "bd-stash", NULL);
4d7902f2 908
a12f801d 909 if (stash) {
4d7902f2
AF		 910 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
911 priv->bd_stash_en = 1;
912 }
913
55917641 914 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
4d7902f2 915
55917641
JL		 916 if (err == 0)
917 priv->rx_stash_size = stash_len;
4d7902f2 918
55917641 919 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
4d7902f2 920
55917641
JL		 921 if (err == 0)
922 priv->rx_stash_index = stash_idx;
4d7902f2
AF		 923
924 if (stash_len || stash_idx)
925 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
926
b31a1d8b 927 mac_addr = of_get_mac_address(np);
bc4598bc 928
b31a1d8b 929 if (mac_addr)
6a3c910c 930 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 931
932 if (model && !strcasecmp(model, "TSEC"))
34018fd4 933 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 934 FSL_GIANFAR_DEV_HAS_COALESCE |
935 FSL_GIANFAR_DEV_HAS_RMON |
936 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
937
b31a1d8b 938 if (model && !strcasecmp(model, "eTSEC"))
34018fd4 939 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
bc4598bc
JC		 940 FSL_GIANFAR_DEV_HAS_COALESCE |
941 FSL_GIANFAR_DEV_HAS_RMON |
942 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
bc4598bc
JC		 943 FSL_GIANFAR_DEV_HAS_CSUM |
944 FSL_GIANFAR_DEV_HAS_VLAN |
945 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
946 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
947 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b 948
55917641 949 err = of_property_read_string(np, "phy-connection-type", &ctype);
b31a1d8b
AF		 950
951 /* We only care about rgmii-id. The rest are autodetected */
55917641 952 if (err == 0 && !strcmp(ctype, "rgmii-id"))
b31a1d8b
AF		 953 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
954 else
955 priv->interface = PHY_INTERFACE_MODE_MII;
956
55917641 957 if (of_find_property(np, "fsl,magic-packet", NULL))
b31a1d8b
AF		 958 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
959
fe192a49 960 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b 961
be403645
FF		 962 /* In the case of a fixed PHY, the DT node associated
963 * to the PHY is the Ethernet MAC DT node.
964 */
6f2c9bd8 965 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
be403645
FF		 966 err = of_phy_register_fixed_link(np);
967 if (err)
968 goto err_grp_init;
969
6f2c9bd8 970 priv->phy_node = of_node_get(np);
be403645
FF		 971 }
972
b31a1d8b 973 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 974 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 975
976 return 0;
977
46ceb60c
SG		 978err_grp_init:
979 unmap_group_regs(priv);
20862788
CM		 980rx_alloc_failed:
981 gfar_free_rx_queues(priv);
982tx_alloc_failed:
983 gfar_free_tx_queues(priv);
ee873fda 984 free_gfar_dev(priv);
b31a1d8b
AF		 985 return err;
986}
987
ca0c88c2 988static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
cc772ab7
MR		 989{
990 struct hwtstamp_config config;
991 struct gfar_private *priv = netdev_priv(netdev);
992
993 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
994 return -EFAULT;
995
996 /* reserved for future extensions */
997 if (config.flags)
998 return -EINVAL;
999
f0ee7acf
MR		 1000 switch (config.tx_type) {
1001 case HWTSTAMP_TX_OFF:
1002 priv->hwts_tx_en = 0;
1003 break;
1004 case HWTSTAMP_TX_ON:
1005 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1006 return -ERANGE;
1007 priv->hwts_tx_en = 1;
1008 break;
1009 default:
cc772ab7 1010 return -ERANGE;
f0ee7acf 1011 }
cc772ab7
MR		 1012
1013 switch (config.rx_filter) {
1014 case HWTSTAMP_FILTER_NONE:
97553f7f 1015 if (priv->hwts_rx_en) {
97553f7f 1016 priv->hwts_rx_en = 0;
0851133b 1017 reset_gfar(netdev);
97553f7f 1018 }
cc772ab7
MR		 1019 break;
1020 default:
1021 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
1022 return -ERANGE;
97553f7f 1023 if (!priv->hwts_rx_en) {
97553f7f 1024 priv->hwts_rx_en = 1;
0851133b 1025 reset_gfar(netdev);
97553f7f 1026 }
cc772ab7
MR		 1027 config.rx_filter = HWTSTAMP_FILTER_ALL;
1028 break;
1029 }
1030
1031 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1032 -EFAULT : 0;
1033}
1034
ca0c88c2
BH		 1035static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
1036{
1037 struct hwtstamp_config config;
1038 struct gfar_private *priv = netdev_priv(netdev);
1039
1040 config.flags = 0;
1041 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1042 config.rx_filter = (priv->hwts_rx_en ?
1043 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1044
1045 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1046 -EFAULT : 0;
1047}
1048
0faac9f7
CW		 1049static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1050{
1051 struct gfar_private *priv = netdev_priv(dev);
1052
1053 if (!netif_running(dev))
1054 return -EINVAL;
1055
cc772ab7 1056 if (cmd == SIOCSHWTSTAMP)
ca0c88c2
BH		 1057 return gfar_hwtstamp_set(dev, rq);
1058 if (cmd == SIOCGHWTSTAMP)
1059 return gfar_hwtstamp_get(dev, rq);
cc772ab7 1060
0faac9f7
CW		 1061 if (!priv->phydev)
1062 return -ENODEV;
1063
28b04113 1064 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 1065}
1066
18294ad1
AV		 1067static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1068 u32 class)
7a8b3372
SG		 1069{
1070 u32 rqfpr = FPR_FILER_MASK;
1071 u32 rqfcr = 0x0;
1072
1073 rqfar--;
1074 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 1075 priv->ftp_rqfpr[rqfar] = rqfpr;
1076 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1077 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1078
1079 rqfar--;
1080 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 1081 priv->ftp_rqfpr[rqfar] = rqfpr;
1082 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 1083 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1084
1085 rqfar--;
1086 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1087 rqfpr = class;
6c43e046
WJB		 1088 priv->ftp_rqfcr[rqfar] = rqfcr;
1089 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1090 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1091
1092 rqfar--;
1093 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1094 rqfpr = class;
6c43e046
WJB		 1095 priv->ftp_rqfcr[rqfar] = rqfcr;
1096 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1097 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1098
1099 return rqfar;
1100}
1101
1102static void gfar_init_filer_table(struct gfar_private *priv)
1103{
1104 int i = 0x0;
1105 u32 rqfar = MAX_FILER_IDX;
1106 u32 rqfcr = 0x0;
1107 u32 rqfpr = FPR_FILER_MASK;
1108
1109 /* Default rule */
1110 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 1111 priv->ftp_rqfcr[rqfar] = rqfcr;
1112 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 1113 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1114
1115 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1116 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1117 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1118 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1119 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1120 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1121
85dd08eb 1122 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 1123 priv->cur_filer_idx = rqfar;
1124
1125 /* Rest are masked rules */
1126 rqfcr = RQFCR_CMP_NOMATCH;
1127 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 1128 priv->ftp_rqfcr[i] = rqfcr;
1129 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 1130 gfar_write_filer(priv, i, rqfcr, rqfpr);
1131 }
1132}
1133
d6ef0bcc 1134#ifdef CONFIG_PPC
2969b1f7 1135static void __gfar_detect_errata_83xx(struct gfar_private *priv)
7d350977 1136{
7d350977
AV		 1137 unsigned int pvr = mfspr(SPRN_PVR);
1138 unsigned int svr = mfspr(SPRN_SVR);
1139 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1140 unsigned int rev = svr & 0xffff;
1141
1142 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1143 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
bc4598bc 1144 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
7d350977
AV		 1145 priv->errata |= GFAR_ERRATA_74;
1146
deb90eac
AV		 1147 /* MPC8313 and MPC837x all rev */
1148 if ((pvr == 0x80850010 && mod == 0x80b0) ||
bc4598bc 1149 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
deb90eac
AV		 1150 priv->errata |= GFAR_ERRATA_76;
1151
2969b1f7
CM		 1152 /* MPC8313 Rev < 2.0 */
1153 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1154 priv->errata |= GFAR_ERRATA_12;
1155}
1156
1157static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1158{
1159 unsigned int svr = mfspr(SPRN_SVR);
1160
1161 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
4363c2fd 1162 priv->errata |= GFAR_ERRATA_12;
53fad773
CM		 1163 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1164 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1165 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
2969b1f7 1166}
d6ef0bcc 1167#endif
2969b1f7
CM		 1168
1169static void gfar_detect_errata(struct gfar_private *priv)
1170{
1171 struct device *dev = &priv->ofdev->dev;
1172
1173 /* no plans to fix */
1174 priv->errata |= GFAR_ERRATA_A002;
1175
d6ef0bcc 1176#ifdef CONFIG_PPC
2969b1f7
CM		 1177 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1178 __gfar_detect_errata_85xx(priv);
1179 else /* non-mpc85xx parts, i.e. e300 core based */
1180 __gfar_detect_errata_83xx(priv);
d6ef0bcc 1181#endif
4363c2fd 1182
7d350977
AV		 1183 if (priv->errata)
1184 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1185 priv->errata);
1186}
1187
0851133b 1188void gfar_mac_reset(struct gfar_private *priv)
20862788
CM		 1189{
1190 struct gfar __iomem *regs = priv->gfargrp[0].regs;
a328ac92 1191 u32 tempval;
20862788
CM		 1192
1193 /* Reset MAC layer */
1194 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1195
1196 /* We need to delay at least 3 TX clocks */
a328ac92 1197 udelay(3);
20862788
CM		 1198
1199 /* the soft reset bit is not self-resetting, so we need to
1200 * clear it before resuming normal operation
1201 */
1202 gfar_write(&regs->maccfg1, 0);
1203
a328ac92
CM		 1204 udelay(3);
1205
88302648
CM		 1206 /* Compute rx_buff_size based on config flags */
1207 gfar_rx_buff_size_config(priv);
1208
1209 /* Initialize the max receive frame/buffer lengths */
1210 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
a328ac92
CM		 1211 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1212
1213 /* Initialize the Minimum Frame Length Register */
1214 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1215
20862788
CM		 1216 /* Initialize MACCFG2. */
1217 tempval = MACCFG2_INIT_SETTINGS;
88302648
CM		 1218
1219 /* If the mtu is larger than the max size for standard
1220 * ethernet frames (ie, a jumbo frame), then set maccfg2
1221 * to allow huge frames, and to check the length
1222 */
1223 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
1224 gfar_has_errata(priv, GFAR_ERRATA_74))
20862788 1225 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
88302648 1226
20862788
CM		 1227 gfar_write(&regs->maccfg2, tempval);
1228
a328ac92
CM		 1229 /* Clear mac addr hash registers */
1230 gfar_write(&regs->igaddr0, 0);
1231 gfar_write(&regs->igaddr1, 0);
1232 gfar_write(&regs->igaddr2, 0);
1233 gfar_write(&regs->igaddr3, 0);
1234 gfar_write(&regs->igaddr4, 0);
1235 gfar_write(&regs->igaddr5, 0);
1236 gfar_write(&regs->igaddr6, 0);
1237 gfar_write(&regs->igaddr7, 0);
1238
1239 gfar_write(&regs->gaddr0, 0);
1240 gfar_write(&regs->gaddr1, 0);
1241 gfar_write(&regs->gaddr2, 0);
1242 gfar_write(&regs->gaddr3, 0);
1243 gfar_write(&regs->gaddr4, 0);
1244 gfar_write(&regs->gaddr5, 0);
1245 gfar_write(&regs->gaddr6, 0);
1246 gfar_write(&regs->gaddr7, 0);
1247
1248 if (priv->extended_hash)
1249 gfar_clear_exact_match(priv->ndev);
1250
1251 gfar_mac_rx_config(priv);
1252
1253 gfar_mac_tx_config(priv);
1254
1255 gfar_set_mac_address(priv->ndev);
1256
1257 gfar_set_multi(priv->ndev);
1258
1259 /* clear ievent and imask before configuring coalescing */
1260 gfar_ints_disable(priv);
1261
1262 /* Configure the coalescing support */
1263 gfar_configure_coalescing_all(priv);
1264}
1265
1266static void gfar_hw_init(struct gfar_private *priv)
1267{
1268 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1269 u32 attrs;
1270
1271 /* Stop the DMA engine now, in case it was running before
1272 * (The firmware could have used it, and left it running).
1273 */
1274 gfar_halt(priv);
1275
1276 gfar_mac_reset(priv);
1277
1278 /* Zero out the rmon mib registers if it has them */
1279 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1280 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1281
1282 /* Mask off the CAM interrupts */
1283 gfar_write(&regs->rmon.cam1, 0xffffffff);
1284 gfar_write(&regs->rmon.cam2, 0xffffffff);
1285 }
1286
20862788
CM		 1287 /* Initialize ECNTRL */
1288 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1289
34018fd4
CM		 1290 /* Set the extraction length and index */
1291 attrs = ATTRELI_EL(priv->rx_stash_size) |
1292 ATTRELI_EI(priv->rx_stash_index);
1293
1294 gfar_write(&regs->attreli, attrs);
1295
1296 /* Start with defaults, and add stashing
1297 * depending on driver parameters
1298 */
1299 attrs = ATTR_INIT_SETTINGS;
1300
1301 if (priv->bd_stash_en)
1302 attrs |= ATTR_BDSTASH;
1303
1304 if (priv->rx_stash_size != 0)
1305 attrs |= ATTR_BUFSTASH;
1306
1307 gfar_write(&regs->attr, attrs);
1308
1309 /* FIFO configs */
1310 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1311 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1312 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1313
20862788
CM		 1314 /* Program the interrupt steering regs, only for MG devices */
1315 if (priv->num_grps > 1)
1316 gfar_write_isrg(priv);
20862788
CM		 1317}
1318
898157ed 1319static void gfar_init_addr_hash_table(struct gfar_private *priv)
20862788
CM		 1320{
1321 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1322
1323 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1324 priv->extended_hash = 1;
1325 priv->hash_width = 9;
1326
1327 priv->hash_regs[0] = &regs->igaddr0;
1328 priv->hash_regs[1] = &regs->igaddr1;
1329 priv->hash_regs[2] = &regs->igaddr2;
1330 priv->hash_regs[3] = &regs->igaddr3;
1331 priv->hash_regs[4] = &regs->igaddr4;
1332 priv->hash_regs[5] = &regs->igaddr5;
1333 priv->hash_regs[6] = &regs->igaddr6;
1334 priv->hash_regs[7] = &regs->igaddr7;
1335 priv->hash_regs[8] = &regs->gaddr0;
1336 priv->hash_regs[9] = &regs->gaddr1;
1337 priv->hash_regs[10] = &regs->gaddr2;
1338 priv->hash_regs[11] = &regs->gaddr3;
1339 priv->hash_regs[12] = &regs->gaddr4;
1340 priv->hash_regs[13] = &regs->gaddr5;
1341 priv->hash_regs[14] = &regs->gaddr6;
1342 priv->hash_regs[15] = &regs->gaddr7;
1343
1344 } else {
1345 priv->extended_hash = 0;
1346 priv->hash_width = 8;
1347
1348 priv->hash_regs[0] = &regs->gaddr0;
1349 priv->hash_regs[1] = &regs->gaddr1;
1350 priv->hash_regs[2] = &regs->gaddr2;
1351 priv->hash_regs[3] = &regs->gaddr3;
1352 priv->hash_regs[4] = &regs->gaddr4;
1353 priv->hash_regs[5] = &regs->gaddr5;
1354 priv->hash_regs[6] = &regs->gaddr6;
1355 priv->hash_regs[7] = &regs->gaddr7;
1356 }
1357}
1358
bb40dcbb 1359/* Set up the ethernet device structure, private data,
0977f817
JC		 1360 * and anything else we need before we start
1361 */
74888760 1362static int gfar_probe(struct platform_device *ofdev)
1da177e4 1363{
1da177e4
LT		 1364 struct net_device *dev = NULL;
1365 struct gfar_private *priv = NULL;
20862788 1366 int err = 0, i;
1da177e4 1367
fba4ed03 1368 err = gfar_of_init(ofdev, &dev);
1da177e4 1369
fba4ed03
SG		 1370 if (err)
1371 return err;
1da177e4
LT		 1372
1373 priv = netdev_priv(dev);
4826857f
KG		 1374 priv->ndev = dev;
1375 priv->ofdev = ofdev;
369ec162 1376 priv->dev = &ofdev->dev;
4826857f 1377 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 1378
d87eb127 1379 spin_lock_init(&priv->bflock);
ab939905 1380 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 1381
8513fbd8 1382 platform_set_drvdata(ofdev, priv);
1da177e4 1383
7d350977
AV		 1384 gfar_detect_errata(priv);
1385
1da177e4 1386 /* Set the dev->base_addr to the gfar reg region */
20862788 1387 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1da177e4 1388
1da177e4 1389 /* Fill in the dev structure */
1da177e4 1390 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1391 dev->mtu = 1500;
26ccfc37 1392 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1393 dev->ethtool_ops = &gfar_ethtool_ops;
1394
fba4ed03 1395 /* Register for napi ...We are registering NAPI for each grp */
71ff9e3d
CM		 1396 for (i = 0; i < priv->num_grps; i++) {
1397 if (priv->poll_mode == GFAR_SQ_POLLING) {
1398 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1399 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1400 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1401 gfar_poll_tx_sq, 2);
1402 } else {
aeb12c5e
CM		 1403 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1404 gfar_poll_rx, GFAR_DEV_WEIGHT);
1405 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1406 gfar_poll_tx, 2);
1407 }
1408 }
a12f801d 1409
b31a1d8b 1410 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95 1411 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1412 NETIF_F_RXCSUM;
8b3afe95 1413 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
bc4598bc 1414 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
8b3afe95 1415 }
0bbaf069 1416
87c288c6 1417 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
f646968f
PM		 1418 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1419 NETIF_F_HW_VLAN_CTAG_RX;
1420 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
87c288c6 1421 }
0bbaf069 1422
3d23a05c
CM		 1423 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1424
20862788 1425 gfar_init_addr_hash_table(priv);
0bbaf069 1426
532c37bc
CM		 1427 /* Insert receive time stamps into padding alignment bytes */
1428 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1429 priv->padding = 8;
0bbaf069 1430
cc772ab7 1431 if (dev->features & NETIF_F_IP_CSUM ||
bc4598bc 1432 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1433 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4
LT		 1434
1435 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1436
a12f801d 1437 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1438 for (i = 0; i < priv->num_tx_queues; i++) {
1439 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1440 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1441 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1442 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1443 }
a12f801d 1444
fba4ed03
SG		 1445 for (i = 0; i < priv->num_rx_queues; i++) {
1446 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1447 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1448 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1449 }
1da177e4 1450
0977f817 1451 /* always enable rx filer */
4aa3a715 1452 priv->rx_filer_enable = 1;
0bbaf069
KG		 1453 /* Enable most messages by default */
1454 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
b98b8bab
CM		 1455 /* use pritority h/w tx queue scheduling for single queue devices */
1456 if (priv->num_tx_queues == 1)
1457 priv->prio_sched_en = 1;
0bbaf069 1458
0851133b
CM		 1459 set_bit(GFAR_DOWN, &priv->state);
1460
a328ac92 1461 gfar_hw_init(priv);
d3eab82b 1462
d4c642ea
FE		 1463 /* Carrier starts down, phylib will bring it up */
1464 netif_carrier_off(dev);
1465
1da177e4
LT		 1466 err = register_netdev(dev);
1467
1468 if (err) {
59deab26 1469 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1470 goto register_fail;
1471 }
1472
2884e5cc 1473 device_init_wakeup(&dev->dev,
bc4598bc
JC		 1474 priv->device_flags &
1475 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
2884e5cc 1476
c50a5d9a 1477 /* fill out IRQ number and name fields */
46ceb60c 1478 for (i = 0; i < priv->num_grps; i++) {
ee873fda 1479 struct gfar_priv_grp *grp = &priv->gfargrp[i];
46ceb60c 1480 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
ee873fda 1481 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
0015e551 1482 dev->name, "_g", '0' + i, "_tx");
ee873fda 1483 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
0015e551 1484 dev->name, "_g", '0' + i, "_rx");
ee873fda 1485 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
0015e551 1486 dev->name, "_g", '0' + i, "_er");
46ceb60c 1487 } else
ee873fda 1488 strcpy(gfar_irq(grp, TX)->name, dev->name);
46ceb60c 1489 }
c50a5d9a 1490
7a8b3372
SG		 1491 /* Initialize the filer table */
1492 gfar_init_filer_table(priv);
1493
1da177e4 1494 /* Print out the device info */
59deab26 1495 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4 1496
0977f817
JC		 1497 /* Even more device info helps when determining which kernel
1498 * provided which set of benchmarks.
1499 */
59deab26 1500 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1501 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1502 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1503 i, priv->rx_queue[i]->rx_ring_size);
bc4598bc 1504 for (i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1505 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1506 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1507
1508 return 0;
1509
1510register_fail:
46ceb60c 1511 unmap_group_regs(priv);
20862788
CM		 1512 gfar_free_rx_queues(priv);
1513 gfar_free_tx_queues(priv);
888c88b8
UKK		 1514 of_node_put(priv->phy_node);
1515 of_node_put(priv->tbi_node);
ee873fda 1516 free_gfar_dev(priv);
bb40dcbb 1517 return err;
1da177e4
LT		 1518}
1519
2dc11581 1520static int gfar_remove(struct platform_device *ofdev)
1da177e4 1521{
8513fbd8 1522 struct gfar_private *priv = platform_get_drvdata(ofdev);
1da177e4 1523
888c88b8
UKK		 1524 of_node_put(priv->phy_node);
1525 of_node_put(priv->tbi_node);
fe192a49 1526
d9d8e041 1527 unregister_netdev(priv->ndev);
46ceb60c 1528 unmap_group_regs(priv);
20862788
CM		 1529 gfar_free_rx_queues(priv);
1530 gfar_free_tx_queues(priv);
ee873fda 1531 free_gfar_dev(priv);
1da177e4
LT		 1532
1533 return 0;
1534}
1535
d87eb127 1536#ifdef CONFIG_PM
be926fc4
AV		 1537
1538static int gfar_suspend(struct device *dev)
d87eb127 1539{
be926fc4
AV		 1540 struct gfar_private *priv = dev_get_drvdata(dev);
1541 struct net_device *ndev = priv->ndev;
46ceb60c 1542 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1543 unsigned long flags;
1544 u32 tempval;
1545
1546 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1547 (priv->device_flags &
1548 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1549
be926fc4 1550 netif_device_detach(ndev);
d87eb127 1551
be926fc4 1552 if (netif_running(ndev)) {
fba4ed03
SG		 1553
1554 local_irq_save(flags);
1555 lock_tx_qs(priv);
d87eb127 1556
c10650b6 1557 gfar_halt_nodisable(priv);
d87eb127
SW		 1558
1559 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1560 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1561
1562 tempval &= ~MACCFG1_TX_EN;
1563
1564 if (!magic_packet)
1565 tempval &= ~MACCFG1_RX_EN;
1566
f4983704 1567 gfar_write(&regs->maccfg1, tempval);
d87eb127 1568
fba4ed03
SG		 1569 unlock_tx_qs(priv);
1570 local_irq_restore(flags);
d87eb127 1571
46ceb60c 1572 disable_napi(priv);
d87eb127
SW		 1573
1574 if (magic_packet) {
1575 /* Enable interrupt on Magic Packet */
f4983704 1576 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1577
1578 /* Enable Magic Packet mode */
f4983704 1579 tempval = gfar_read(&regs->maccfg2);
d87eb127 1580 tempval |= MACCFG2_MPEN;
f4983704 1581 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1582 } else {
1583 phy_stop(priv->phydev);
1584 }
1585 }
1586
1587 return 0;
1588}
1589
be926fc4 1590static int gfar_resume(struct device *dev)
d87eb127 1591{
be926fc4
AV		 1592 struct gfar_private *priv = dev_get_drvdata(dev);
1593 struct net_device *ndev = priv->ndev;
46ceb60c 1594 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1595 unsigned long flags;
1596 u32 tempval;
1597 int magic_packet = priv->wol_en &&
bc4598bc
JC		 1598 (priv->device_flags &
1599 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1600
be926fc4
AV		 1601 if (!netif_running(ndev)) {
1602 netif_device_attach(ndev);
d87eb127
SW		 1603 return 0;
1604 }
1605
1606 if (!magic_packet && priv->phydev)
1607 phy_start(priv->phydev);
1608
1609 /* Disable Magic Packet mode, in case something
1610 * else woke us up.
1611 */
fba4ed03
SG		 1612 local_irq_save(flags);
1613 lock_tx_qs(priv);
d87eb127 1614
f4983704 1615 tempval = gfar_read(&regs->maccfg2);
d87eb127 1616 tempval &= ~MACCFG2_MPEN;
f4983704 1617 gfar_write(&regs->maccfg2, tempval);
d87eb127 1618
c10650b6 1619 gfar_start(priv);
d87eb127 1620
fba4ed03
SG		 1621 unlock_tx_qs(priv);
1622 local_irq_restore(flags);
d87eb127 1623
be926fc4
AV		 1624 netif_device_attach(ndev);
1625
46ceb60c 1626 enable_napi(priv);
be926fc4
AV		 1627
1628 return 0;
1629}
1630
1631static int gfar_restore(struct device *dev)
1632{
1633 struct gfar_private *priv = dev_get_drvdata(dev);
1634 struct net_device *ndev = priv->ndev;
1635
103cdd1d
WD		 1636 if (!netif_running(ndev)) {
1637 netif_device_attach(ndev);
1638
be926fc4 1639 return 0;
103cdd1d 1640 }
be926fc4 1641
1eb8f7a7
CM		 1642 if (gfar_init_bds(ndev)) {
1643 free_skb_resources(priv);
1644 return -ENOMEM;
1645 }
1646
a328ac92
CM		 1647 gfar_mac_reset(priv);
1648
1649 gfar_init_tx_rx_base(priv);
1650
c10650b6 1651 gfar_start(priv);
be926fc4
AV		 1652
1653 priv->oldlink = 0;
1654 priv->oldspeed = 0;
1655 priv->oldduplex = -1;
1656
1657 if (priv->phydev)
1658 phy_start(priv->phydev);
d87eb127 1659
be926fc4 1660 netif_device_attach(ndev);
5ea681d4 1661 enable_napi(priv);
d87eb127
SW		 1662
1663 return 0;
1664}
be926fc4
AV		 1665
1666static struct dev_pm_ops gfar_pm_ops = {
1667 .suspend = gfar_suspend,
1668 .resume = gfar_resume,
1669 .freeze = gfar_suspend,
1670 .thaw = gfar_resume,
1671 .restore = gfar_restore,
1672};
1673
1674#define GFAR_PM_OPS (&gfar_pm_ops)
1675
d87eb127 1676#else
be926fc4
AV		 1677
1678#define GFAR_PM_OPS NULL
be926fc4 1679
d87eb127 1680#endif
1da177e4 1681
e8a2b6a4
AF		 1682/* Reads the controller's registers to determine what interface
1683 * connects it to the PHY.
1684 */
1685static phy_interface_t gfar_get_interface(struct net_device *dev)
1686{
1687 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1688 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1689 u32 ecntrl;
1690
f4983704 1691 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1692
1693 if (ecntrl & ECNTRL_SGMII_MODE)
1694 return PHY_INTERFACE_MODE_SGMII;
1695
1696 if (ecntrl & ECNTRL_TBI_MODE) {
1697 if (ecntrl & ECNTRL_REDUCED_MODE)
1698 return PHY_INTERFACE_MODE_RTBI;
1699 else
1700 return PHY_INTERFACE_MODE_TBI;
1701 }
1702
1703 if (ecntrl & ECNTRL_REDUCED_MODE) {
bc4598bc 1704 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
e8a2b6a4 1705 return PHY_INTERFACE_MODE_RMII;
bc4598bc 1706 }
7132ab7f 1707 else {
b31a1d8b 1708 phy_interface_t interface = priv->interface;
7132ab7f 1709
0977f817 1710 /* This isn't autodetected right now, so it must
7132ab7f
AF		 1711 * be set by the device tree or platform code.
1712 */
1713 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1714 return PHY_INTERFACE_MODE_RGMII_ID;
1715
e8a2b6a4 1716 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1717 }
e8a2b6a4
AF		 1718 }
1719
b31a1d8b 1720 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1721 return PHY_INTERFACE_MODE_GMII;
1722
1723 return PHY_INTERFACE_MODE_MII;
1724}
1725
1726
bb40dcbb
AF		 1727/* Initializes driver's PHY state, and attaches to the PHY.
1728 * Returns 0 on success.
1da177e4
LT		 1729 */
1730static int init_phy(struct net_device *dev)
1731{
1732 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1733 uint gigabit_support =
b31a1d8b 1734 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
23402bdd 1735 GFAR_SUPPORTED_GBIT : 0;
e8a2b6a4 1736 phy_interface_t interface;
1da177e4
LT		 1737
1738 priv->oldlink = 0;
1739 priv->oldspeed = 0;
1740 priv->oldduplex = -1;
1741
e8a2b6a4
AF		 1742 interface = gfar_get_interface(dev);
1743
1db780f8
AV		 1744 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1745 interface);
1db780f8
AV		 1746 if (!priv->phydev) {
1747 dev_err(&dev->dev, "could not attach to PHY\n");
1748 return -ENODEV;
fe192a49 1749 }
1da177e4 1750
d3c12873
KJ		 1751 if (interface == PHY_INTERFACE_MODE_SGMII)
1752 gfar_configure_serdes(dev);
1753
bb40dcbb 1754 /* Remove any features not supported by the controller */
fe192a49
GL		 1755 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1756 priv->phydev->advertising = priv->phydev->supported;
1da177e4 1757
cf987afc
PMB		 1758 /* Add support for flow control, but don't advertise it by default */
1759 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1760
1da177e4 1761 return 0;
1da177e4
LT		 1762}
1763
0977f817 1764/* Initialize TBI PHY interface for communicating with the
d0313587
PG		 1765 * SERDES lynx PHY on the chip. We communicate with this PHY
1766 * through the MDIO bus on each controller, treating it as a
1767 * "normal" PHY at the address found in the TBIPA register. We assume
1768 * that the TBIPA register is valid. Either the MDIO bus code will set
1769 * it to a value that doesn't conflict with other PHYs on the bus, or the
1770 * value doesn't matter, as there are no other PHYs on the bus.
1771 */
d3c12873
KJ		 1772static void gfar_configure_serdes(struct net_device *dev)
1773{
1774 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1775 struct phy_device *tbiphy;
1776
1777 if (!priv->tbi_node) {
1778 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1779 "device tree specify a tbi-handle\n");
1780 return;
1781 }
c132419e 1782
fe192a49
GL		 1783 tbiphy = of_phy_find_device(priv->tbi_node);
1784 if (!tbiphy) {
1785 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1786 return;
1787 }
d3c12873 1788
0977f817 1789 /* If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1790 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1791 * everything for us? Resetting it takes the link down and requires
1792 * several seconds for it to come back.
1793 */
fe192a49 1794 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1795 return;
d3c12873 1796
d0313587 1797 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1798 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1799
fe192a49 1800 phy_write(tbiphy, MII_ADVERTISE,
bc4598bc
JC		 1801 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1802 ADVERTISE_1000XPSE_ASYM);
d3c12873 1803
bc4598bc
JC		 1804 phy_write(tbiphy, MII_BMCR,
1805 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1806 BMCR_SPEED1000);
d3c12873
KJ		 1807}
1808
511d934f
AV		 1809static int __gfar_is_rx_idle(struct gfar_private *priv)
1810{
1811 u32 res;
1812
0977f817 1813 /* Normaly TSEC should not hang on GRS commands, so we should
511d934f
AV		 1814 * actually wait for IEVENT_GRSC flag.
1815 */
ad3660c2 1816 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
511d934f
AV		 1817 return 0;
1818
0977f817 1819 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
511d934f
AV		 1820 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1821 * and the Rx can be safely reset.
1822 */
1823 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1824 res &= 0x7f807f80;
1825 if ((res & 0xffff) == (res >> 16))
1826 return 1;
1827
1828 return 0;
1829}
0bbaf069
KG		 1830
1831/* Halt the receive and transmit queues */
c10650b6 1832static void gfar_halt_nodisable(struct gfar_private *priv)
1da177e4 1833{
efeddce7 1834 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 1835 u32 tempval;
a4feee89
CM		 1836 unsigned int timeout;
1837 int stopped;
1da177e4 1838
efeddce7 1839 gfar_ints_disable(priv);
1da177e4 1840
a4feee89
CM		 1841 if (gfar_is_dma_stopped(priv))
1842 return;
1843
1da177e4 1844 /* Stop the DMA, and wait for it to stop */
f4983704 1845 tempval = gfar_read(&regs->dmactrl);
a4feee89
CM		 1846 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1847 gfar_write(&regs->dmactrl, tempval);
1848
1849retry:
1850 timeout = 1000;
1851 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1852 cpu_relax();
1853 timeout--;
1da177e4 1854 }
a4feee89
CM		 1855
1856 if (!timeout)
1857 stopped = gfar_is_dma_stopped(priv);
1858
1859 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1860 !__gfar_is_rx_idle(priv))
1861 goto retry;
d87eb127 1862}
d87eb127
SW		 1863
1864/* Halt the receive and transmit queues */
c10650b6 1865void gfar_halt(struct gfar_private *priv)
d87eb127 1866{
46ceb60c 1867 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1868 u32 tempval;
1da177e4 1869
c10650b6
CM		 1870 /* Dissable the Rx/Tx hw queues */
1871 gfar_write(&regs->rqueue, 0);
1872 gfar_write(&regs->tqueue, 0);
2a54adc3 1873
c10650b6
CM		 1874 mdelay(10);
1875
1876 gfar_halt_nodisable(priv);
1877
1878 /* Disable Rx/Tx DMA */
1da177e4
LT		 1879 tempval = gfar_read(&regs->maccfg1);
1880 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1881 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1882}
1883
1884void stop_gfar(struct net_device *dev)
1885{
1886 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1887
0851133b 1888 netif_tx_stop_all_queues(dev);
bb40dcbb 1889
4e857c58 1890 smp_mb__before_atomic();
0851133b 1891 set_bit(GFAR_DOWN, &priv->state);
4e857c58 1892 smp_mb__after_atomic();
a12f801d 1893
0851133b 1894 disable_napi(priv);
0bbaf069 1895
0851133b 1896 /* disable ints and gracefully shut down Rx/Tx DMA */
c10650b6 1897 gfar_halt(priv);
1da177e4 1898
0851133b 1899 phy_stop(priv->phydev);
1da177e4 1900
1da177e4 1901 free_skb_resources(priv);
1da177e4
LT		 1902}
1903
fba4ed03 1904static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1905{
1da177e4 1906 struct txbd8 *txbdp;
fba4ed03 1907 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1908 int i, j;
1da177e4 1909
a12f801d 1910 txbdp = tx_queue->tx_bd_base;
1da177e4 1911
a12f801d
SG		 1912 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1913 if (!tx_queue->tx_skbuff[i])
4669bc90 1914 continue;
1da177e4 1915
a7312d58
CM		 1916 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1917 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
4669bc90 1918 txbdp->lstatus = 0;
fba4ed03 1919 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
bc4598bc 1920 j++) {
4669bc90 1921 txbdp++;
a7312d58
CM		 1922 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1923 be16_to_cpu(txbdp->length),
1924 DMA_TO_DEVICE);
1da177e4 1925 }
ad5da7ab 1926 txbdp++;
a12f801d
SG		 1927 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1928 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1929 }
a12f801d 1930 kfree(tx_queue->tx_skbuff);
1eb8f7a7 1931 tx_queue->tx_skbuff = NULL;
fba4ed03 1932}
1da177e4 1933
fba4ed03
SG		 1934static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1935{
1936 struct rxbd8 *rxbdp;
1937 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1938 int i;
1da177e4 1939
fba4ed03 1940 rxbdp = rx_queue->rx_bd_base;
1da177e4 1941
a12f801d
SG		 1942 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1943 if (rx_queue->rx_skbuff[i]) {
a7312d58 1944 dma_unmap_single(priv->dev, be32_to_cpu(rxbdp->bufPtr),
369ec162 1945 priv->rx_buffer_size,
bc4598bc 1946 DMA_FROM_DEVICE);
a12f801d
SG		 1947 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1948 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1949 }
e69edd21
AV		 1950 rxbdp->lstatus = 0;
1951 rxbdp->bufPtr = 0;
1952 rxbdp++;
1da177e4 1953 }
a12f801d 1954 kfree(rx_queue->rx_skbuff);
1eb8f7a7 1955 rx_queue->rx_skbuff = NULL;
fba4ed03 1956}
e69edd21 1957
fba4ed03 1958/* If there are any tx skbs or rx skbs still around, free them.
0977f817
JC		 1959 * Then free tx_skbuff and rx_skbuff
1960 */
fba4ed03
SG		 1961static void free_skb_resources(struct gfar_private *priv)
1962{
1963 struct gfar_priv_tx_q *tx_queue = NULL;
1964 struct gfar_priv_rx_q *rx_queue = NULL;
1965 int i;
1966
1967 /* Go through all the buffer descriptors and free their data buffers */
1968 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1969 struct netdev_queue *txq;
bc4598bc 1970
fba4ed03 1971 tx_queue = priv->tx_queue[i];
d8a0f1b0 1972 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
bc4598bc 1973 if (tx_queue->tx_skbuff)
fba4ed03 1974 free_skb_tx_queue(tx_queue);
d8a0f1b0 1975 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1976 }
1977
1978 for (i = 0; i < priv->num_rx_queues; i++) {
1979 rx_queue = priv->rx_queue[i];
bc4598bc 1980 if (rx_queue->rx_skbuff)
fba4ed03
SG		 1981 free_skb_rx_queue(rx_queue);
1982 }
1983
369ec162 1984 dma_free_coherent(priv->dev,
bc4598bc
JC		 1985 sizeof(struct txbd8) * priv->total_tx_ring_size +
1986 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1987 priv->tx_queue[0]->tx_bd_base,
1988 priv->tx_queue[0]->tx_bd_dma_base);
1da177e4
LT		 1989}
1990
c10650b6 1991void gfar_start(struct gfar_private *priv)
0bbaf069 1992{
46ceb60c 1993 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1994 u32 tempval;
46ceb60c 1995 int i = 0;
0bbaf069 1996
c10650b6
CM		 1997 /* Enable Rx/Tx hw queues */
1998 gfar_write(&regs->rqueue, priv->rqueue);
1999 gfar_write(&regs->tqueue, priv->tqueue);
0bbaf069
KG		 2000
2001 /* Initialize DMACTRL to have WWR and WOP */
f4983704 2002 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2003 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 2004 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2005
0bbaf069 2006 /* Make sure we aren't stopped */
f4983704 2007 tempval = gfar_read(&regs->dmactrl);
0bbaf069 2008 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 2009 gfar_write(&regs->dmactrl, tempval);
0bbaf069 2010
46ceb60c
SG		 2011 for (i = 0; i < priv->num_grps; i++) {
2012 regs = priv->gfargrp[i].regs;
2013 /* Clear THLT/RHLT, so that the DMA starts polling now */
2014 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2015 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
46ceb60c 2016 }
12dea57b 2017
c10650b6
CM		 2018 /* Enable Rx/Tx DMA */
2019 tempval = gfar_read(&regs->maccfg1);
2020 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2021 gfar_write(&regs->maccfg1, tempval);
2022
efeddce7
CM		 2023 gfar_ints_enable(priv);
2024
c10650b6 2025 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 2026}
2027
80ec396c
CM		 2028static void free_grp_irqs(struct gfar_priv_grp *grp)
2029{
2030 free_irq(gfar_irq(grp, TX)->irq, grp);
2031 free_irq(gfar_irq(grp, RX)->irq, grp);
2032 free_irq(gfar_irq(grp, ER)->irq, grp);
2033}
2034
46ceb60c
SG		 2035static int register_grp_irqs(struct gfar_priv_grp *grp)
2036{
2037 struct gfar_private *priv = grp->priv;
2038 struct net_device *dev = priv->ndev;
2039 int err;
1da177e4 2040
1da177e4 2041 /* If the device has multiple interrupts, register for
0977f817
JC		 2042 * them. Otherwise, only register for the one
2043 */
b31a1d8b 2044 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 2045 /* Install our interrupt handlers for Error,
0977f817
JC		 2046 * Transmit, and Receive
2047 */
ee873fda
CM		 2048 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2049 gfar_irq(grp, ER)->name, grp);
2050 if (err < 0) {
59deab26 2051 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2052 gfar_irq(grp, ER)->irq);
46ceb60c 2053
2145f1af 2054 goto err_irq_fail;
1da177e4 2055 }
ee873fda
CM		 2056 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2057 gfar_irq(grp, TX)->name, grp);
2058 if (err < 0) {
59deab26 2059 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2060 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2061 goto tx_irq_fail;
2062 }
ee873fda
CM		 2063 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2064 gfar_irq(grp, RX)->name, grp);
2065 if (err < 0) {
59deab26 2066 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2067 gfar_irq(grp, RX)->irq);
1da177e4
LT		 2068 goto rx_irq_fail;
2069 }
2070 } else {
ee873fda
CM		 2071 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2072 gfar_irq(grp, TX)->name, grp);
2073 if (err < 0) {
59deab26 2074 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
ee873fda 2075 gfar_irq(grp, TX)->irq);
1da177e4
LT		 2076 goto err_irq_fail;
2077 }
2078 }
2079
46ceb60c
SG		 2080 return 0;
2081
2082rx_irq_fail:
ee873fda 2083 free_irq(gfar_irq(grp, TX)->irq, grp);
46ceb60c 2084tx_irq_fail:
ee873fda 2085 free_irq(gfar_irq(grp, ER)->irq, grp);
46ceb60c
SG		 2086err_irq_fail:
2087 return err;
2088
2089}
2090
80ec396c
CM		 2091static void gfar_free_irq(struct gfar_private *priv)
2092{
2093 int i;
2094
2095 /* Free the IRQs */
2096 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2097 for (i = 0; i < priv->num_grps; i++)
2098 free_grp_irqs(&priv->gfargrp[i]);
2099 } else {
2100 for (i = 0; i < priv->num_grps; i++)
2101 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2102 &priv->gfargrp[i]);
2103 }
2104}
2105
2106static int gfar_request_irq(struct gfar_private *priv)
2107{
2108 int err, i, j;
2109
2110 for (i = 0; i < priv->num_grps; i++) {
2111 err = register_grp_irqs(&priv->gfargrp[i]);
2112 if (err) {
2113 for (j = 0; j < i; j++)
2114 free_grp_irqs(&priv->gfargrp[j]);
2115 return err;
2116 }
2117 }
2118
2119 return 0;
2120}
2121
46ceb60c
SG		 2122/* Bring the controller up and running */
2123int startup_gfar(struct net_device *ndev)
2124{
2125 struct gfar_private *priv = netdev_priv(ndev);
80ec396c 2126 int err;
46ceb60c 2127
a328ac92 2128 gfar_mac_reset(priv);
46ceb60c 2129
46ceb60c
SG		 2130 err = gfar_alloc_skb_resources(ndev);
2131 if (err)
2132 return err;
2133
a328ac92 2134 gfar_init_tx_rx_base(priv);
46ceb60c 2135
4e857c58 2136 smp_mb__before_atomic();
0851133b 2137 clear_bit(GFAR_DOWN, &priv->state);
4e857c58 2138 smp_mb__after_atomic();
0851133b
CM		 2139
2140 /* Start Rx/Tx DMA and enable the interrupts */
c10650b6 2141 gfar_start(priv);
1da177e4 2142
826aa4a0
AV		 2143 phy_start(priv->phydev);
2144
0851133b
CM		 2145 enable_napi(priv);
2146
2147 netif_tx_wake_all_queues(ndev);
2148
1da177e4 2149 return 0;
1da177e4
LT		 2150}
2151
0977f817
JC		 2152/* Called when something needs to use the ethernet device
2153 * Returns 0 for success.
2154 */
1da177e4
LT		 2155static int gfar_enet_open(struct net_device *dev)
2156{
94e8cc35 2157 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 2158 int err;
2159
1da177e4 2160 err = init_phy(dev);
0851133b 2161 if (err)
1da177e4
LT		 2162 return err;
2163
80ec396c
CM		 2164 err = gfar_request_irq(priv);
2165 if (err)
2166 return err;
2167
1da177e4 2168 err = startup_gfar(dev);
0851133b 2169 if (err)
db0e8e3f 2170 return err;
1da177e4 2171
2884e5cc
AV		 2172 device_set_wakeup_enable(&dev->dev, priv->wol_en);
2173
1da177e4
LT		 2174 return err;
2175}
2176
54dc79fe 2177static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 2178{
54dc79fe 2179 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 2180
2181 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 2182
0bbaf069
KG		 2183 return fcb;
2184}
2185
9c4886e5 2186static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
bc4598bc 2187 int fcb_length)
0bbaf069 2188{
0bbaf069
KG		 2189 /* If we're here, it's a IP packet with a TCP or UDP
2190 * payload. We set it to checksum, using a pseudo-header
2191 * we provide
2192 */
3a2e16c8 2193 u8 flags = TXFCB_DEFAULT;
0bbaf069 2194
0977f817
JC		 2195 /* Tell the controller what the protocol is
2196 * And provide the already calculated phcs
2197 */
eddc9ec5 2198 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 2199 flags |= TXFCB_UDP;
26eb9374 2200 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
7f7f5316 2201 } else
26eb9374 2202 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
0bbaf069
KG		 2203
2204 /* l3os is the distance between the start of the
2205 * frame (skb->data) and the start of the IP hdr.
2206 * l4os is the distance between the start of the
0977f817
JC		 2207 * l3 hdr and the l4 hdr
2208 */
26eb9374 2209 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
cfe1fc77 2210 fcb->l4os = skb_network_header_len(skb);
0bbaf069 2211
7f7f5316 2212 fcb->flags = flags;
0bbaf069
KG		 2213}
2214
7f7f5316 2215void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 2216{
7f7f5316 2217 fcb->flags |= TXFCB_VLN;
26eb9374 2218 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
0bbaf069
KG		 2219}
2220
4669bc90 2221static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
bc4598bc 2222 struct txbd8 *base, int ring_size)
4669bc90
DH		 2223{
2224 struct txbd8 *new_bd = bdp + stride;
2225
2226 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2227}
2228
2229static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
bc4598bc 2230 int ring_size)
4669bc90
DH		 2231{
2232 return skip_txbd(bdp, 1, base, ring_size);
2233}
2234
02d88fb4
CM		 2235/* eTSEC12: csum generation not supported for some fcb offsets */
2236static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2237 unsigned long fcb_addr)
2238{
2239 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2240 (fcb_addr % 0x20) > 0x18);
2241}
2242
2243/* eTSEC76: csum generation for frames larger than 2500 may
2244 * cause excess delays before start of transmission
2245 */
2246static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2247 unsigned int len)
2248{
2249 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2250 (len > 2500));
2251}
2252
0977f817
JC		 2253/* This is called by the kernel when a frame is ready for transmission.
2254 * It is pointed to by the dev->hard_start_xmit function pointer
2255 */
1da177e4
LT		 2256static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2257{
2258 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2259 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2260 struct netdev_queue *txq;
f4983704 2261 struct gfar __iomem *regs = NULL;
0bbaf069 2262 struct txfcb *fcb = NULL;
f0ee7acf 2263 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2264 u32 lstatus;
0d0cffdc
CM		 2265 int i, rq = 0;
2266 int do_tstamp, do_csum, do_vlan;
4669bc90 2267 u32 bufaddr;
50ad076b 2268 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
fba4ed03
SG		 2269
2270 rq = skb->queue_mapping;
2271 tx_queue = priv->tx_queue[rq];
2272 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2273 base = tx_queue->tx_bd_base;
46ceb60c 2274 regs = tx_queue->grp->regs;
f0ee7acf 2275
0d0cffdc 2276 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
df8a39de 2277 do_vlan = skb_vlan_tag_present(skb);
0d0cffdc
CM		 2278 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2279 priv->hwts_tx_en;
2280
2281 if (do_csum || do_vlan)
2282 fcb_len = GMAC_FCB_LEN;
2283
f0ee7acf 2284 /* check if time stamp should be generated */
0d0cffdc
CM		 2285 if (unlikely(do_tstamp))
2286 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
4669bc90 2287
5b28beaf 2288 /* make space for additional header when fcb is needed */
0d0cffdc 2289 if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
54dc79fe
SH		 2290 struct sk_buff *skb_new;
2291
0d0cffdc 2292 skb_new = skb_realloc_headroom(skb, fcb_len);
54dc79fe
SH		 2293 if (!skb_new) {
2294 dev->stats.tx_errors++;
c9974ad4 2295 dev_kfree_skb_any(skb);
54dc79fe
SH		 2296 return NETDEV_TX_OK;
2297 }
db83d136 2298
313b037c
ED		 2299 if (skb->sk)
2300 skb_set_owner_w(skb_new, skb->sk);
c9974ad4 2301 dev_consume_skb_any(skb);
54dc79fe
SH		 2302 skb = skb_new;
2303 }
2304
4669bc90
DH		 2305 /* total number of fragments in the SKB */
2306 nr_frags = skb_shinfo(skb)->nr_frags;
2307
f0ee7acf
MR		 2308 /* calculate the required number of TxBDs for this skb */
2309 if (unlikely(do_tstamp))
2310 nr_txbds = nr_frags + 2;
2311 else
2312 nr_txbds = nr_frags + 1;
2313
4669bc90 2314 /* check if there is space to queue this packet */
f0ee7acf 2315 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2316 /* no space, stop the queue */
fba4ed03 2317 netif_tx_stop_queue(txq);
4669bc90 2318 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2319 return NETDEV_TX_BUSY;
2320 }
1da177e4
LT		 2321
2322 /* Update transmit stats */
50ad076b
CM		 2323 bytes_sent = skb->len;
2324 tx_queue->stats.tx_bytes += bytes_sent;
2325 /* keep Tx bytes on wire for BQL accounting */
2326 GFAR_CB(skb)->bytes_sent = bytes_sent;
1ac9ad13 2327 tx_queue->stats.tx_packets++;
1da177e4 2328
a12f801d 2329 txbdp = txbdp_start = tx_queue->cur_tx;
a7312d58 2330 lstatus = be32_to_cpu(txbdp->lstatus);
f0ee7acf
MR		 2331
2332 /* Time stamp insertion requires one additional TxBD */
2333 if (unlikely(do_tstamp))
2334 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
bc4598bc 2335 tx_queue->tx_ring_size);
1da177e4 2336
4669bc90 2337 if (nr_frags == 0) {
a7312d58
CM		 2338 if (unlikely(do_tstamp)) {
2339 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2340
2341 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2342 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2343 } else {
f0ee7acf 2344 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
a7312d58 2345 }
4669bc90
DH		 2346 } else {
2347 /* Place the fragment addresses and lengths into the TxBDs */
2348 for (i = 0; i < nr_frags; i++) {
50ad076b 2349 unsigned int frag_len;
4669bc90 2350 /* Point at the next BD, wrapping as needed */
a12f801d 2351 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2352
50ad076b 2353 frag_len = skb_shinfo(skb)->frags[i].size;
4669bc90 2354
a7312d58 2355 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
bc4598bc 2356 BD_LFLAG(TXBD_READY);
4669bc90
DH		 2357
2358 /* Handle the last BD specially */
2359 if (i == nr_frags - 1)
2360 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2361
369ec162 2362 bufaddr = skb_frag_dma_map(priv->dev,
2234a722
IC		 2363 &skb_shinfo(skb)->frags[i],
2364 0,
50ad076b 2365 frag_len,
2234a722 2366 DMA_TO_DEVICE);
0a4b5a24
KH		 2367 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2368 goto dma_map_err;
4669bc90
DH		 2369
2370 /* set the TxBD length and buffer pointer */
a7312d58
CM		 2371 txbdp->bufPtr = cpu_to_be32(bufaddr);
2372 txbdp->lstatus = cpu_to_be32(lstatus);
4669bc90
DH		 2373 }
2374
a7312d58 2375 lstatus = be32_to_cpu(txbdp_start->lstatus);
4669bc90 2376 }
1da177e4 2377
9c4886e5
MR		 2378 /* Add TxPAL between FCB and frame if required */
2379 if (unlikely(do_tstamp)) {
2380 skb_push(skb, GMAC_TXPAL_LEN);
2381 memset(skb->data, 0, GMAC_TXPAL_LEN);
2382 }
2383
0d0cffdc
CM		 2384 /* Add TxFCB if required */
2385 if (fcb_len) {
54dc79fe 2386 fcb = gfar_add_fcb(skb);
02d88fb4 2387 lstatus |= BD_LFLAG(TXBD_TOE);
0d0cffdc
CM		 2388 }
2389
2390 /* Set up checksumming */
2391 if (do_csum) {
2392 gfar_tx_checksum(skb, fcb, fcb_len);
02d88fb4
CM		 2393
2394 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2395 unlikely(gfar_csum_errata_76(priv, skb->len))) {
4363c2fd
AD		 2396 __skb_pull(skb, GMAC_FCB_LEN);
2397 skb_checksum_help(skb);
0d0cffdc
CM		 2398 if (do_vlan || do_tstamp) {
2399 /* put back a new fcb for vlan/tstamp TOE */
2400 fcb = gfar_add_fcb(skb);
2401 } else {
2402 /* Tx TOE not used */
2403 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2404 fcb = NULL;
2405 }
4363c2fd 2406 }
0bbaf069
KG		 2407 }
2408
0d0cffdc 2409 if (do_vlan)
54dc79fe 2410 gfar_tx_vlan(skb, fcb);
0bbaf069 2411
f0ee7acf
MR		 2412 /* Setup tx hardware time stamping if requested */
2413 if (unlikely(do_tstamp)) {
2244d07b 2414 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf 2415 fcb->ptp = 1;
f0ee7acf
MR		 2416 }
2417
0a4b5a24
KH		 2418 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2419 DMA_TO_DEVICE);
2420 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2421 goto dma_map_err;
2422
a7312d58 2423 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1da177e4 2424
0977f817 2425 /* If time stamping is requested one additional TxBD must be set up. The
f0ee7acf
MR		 2426 * first TxBD points to the FCB and must have a data length of
2427 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2428 * the full frame length.
2429 */
2430 if (unlikely(do_tstamp)) {
a7312d58
CM		 2431 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2432
2433 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2434 bufaddr += fcb_len;
2435 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2436 (skb_headlen(skb) - fcb_len);
2437
2438 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2439 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
f0ee7acf
MR		 2440 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2441 } else {
2442 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2443 }
1da177e4 2444
50ad076b 2445 netdev_tx_sent_queue(txq, bytes_sent);
d8a0f1b0 2446
d55398ba 2447 gfar_wmb();
7f7f5316 2448
a7312d58 2449 txbdp_start->lstatus = cpu_to_be32(lstatus);
4669bc90 2450
d55398ba 2451 gfar_wmb(); /* force lstatus write before tx_skbuff */
0eddba52
AV		 2452
2453 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2454
4669bc90 2455 /* Update the current skb pointer to the next entry we will use
0977f817
JC		 2456 * (wrapping if necessary)
2457 */
a12f801d 2458 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
bc4598bc 2459 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2460
a12f801d 2461 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90 2462
bc602280
CM		 2463 /* We can work in parallel with gfar_clean_tx_ring(), except
2464 * when modifying num_txbdfree. Note that we didn't grab the lock
2465 * when we were reading the num_txbdfree and checking for available
2466 * space, that's because outside of this function it can only grow.
2467 */
2468 spin_lock_bh(&tx_queue->txlock);
4669bc90 2469 /* reduce TxBD free count */
f0ee7acf 2470 tx_queue->num_txbdfree -= (nr_txbds);
bc602280 2471 spin_unlock_bh(&tx_queue->txlock);
1da177e4
LT		 2472
2473 /* If the next BD still needs to be cleaned up, then the bds
0977f817
JC		 2474 * are full. We need to tell the kernel to stop sending us stuff.
2475 */
a12f801d 2476 if (!tx_queue->num_txbdfree) {
fba4ed03 2477 netif_tx_stop_queue(txq);
1da177e4 2478
09f75cd7 2479 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2480 }
2481
1da177e4 2482 /* Tell the DMA to go go go */
fba4ed03 2483 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4 2484
54dc79fe 2485 return NETDEV_TX_OK;
0a4b5a24
KH		 2486
2487dma_map_err:
2488 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2489 if (do_tstamp)
2490 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2491 for (i = 0; i < nr_frags; i++) {
a7312d58 2492 lstatus = be32_to_cpu(txbdp->lstatus);
0a4b5a24
KH		 2493 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2494 break;
2495
a7312d58
CM		 2496 lstatus &= ~BD_LFLAG(TXBD_READY);
2497 txbdp->lstatus = cpu_to_be32(lstatus);
2498 bufaddr = be32_to_cpu(txbdp->bufPtr);
2499 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
0a4b5a24
KH		 2500 DMA_TO_DEVICE);
2501 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2502 }
2503 gfar_wmb();
2504 dev_kfree_skb_any(skb);
2505 return NETDEV_TX_OK;
1da177e4
LT		 2506}
2507
2508/* Stops the kernel queue, and halts the controller */
2509static int gfar_close(struct net_device *dev)
2510{
2511 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2512
ab939905 2513 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2514 stop_gfar(dev);
2515
bb40dcbb
AF		 2516 /* Disconnect from the PHY */
2517 phy_disconnect(priv->phydev);
2518 priv->phydev = NULL;
1da177e4 2519
80ec396c
CM		 2520 gfar_free_irq(priv);
2521
1da177e4
LT		 2522 return 0;
2523}
2524
1da177e4 2525/* Changes the mac address if the controller is not running. */
f162b9d5 2526static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2527{
7f7f5316 2528 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2529
2530 return 0;
2531}
2532
1da177e4
LT		 2533static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2534{
1da177e4 2535 struct gfar_private *priv = netdev_priv(dev);
0bbaf069
KG		 2536 int frame_size = new_mtu + ETH_HLEN;
2537
1da177e4 2538 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2539 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2540 return -EINVAL;
2541 }
2542
0851133b
CM		 2543 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2544 cpu_relax();
2545
88302648 2546 if (dev->flags & IFF_UP)
1da177e4
LT		 2547 stop_gfar(dev);
2548
1da177e4
LT		 2549 dev->mtu = new_mtu;
2550
88302648 2551 if (dev->flags & IFF_UP)
1da177e4
LT		 2552 startup_gfar(dev);
2553
0851133b
CM		 2554 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2555
1da177e4
LT		 2556 return 0;
2557}
2558
0851133b
CM		 2559void reset_gfar(struct net_device *ndev)
2560{
2561 struct gfar_private *priv = netdev_priv(ndev);
2562
2563 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2564 cpu_relax();
2565
2566 stop_gfar(ndev);
2567 startup_gfar(ndev);
2568
2569 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2570}
2571
ab939905 2572/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2573 * transmitted after a set amount of time.
2574 * For now, assume that clearing out all the structures, and
ab939905
SS		 2575 * starting over will fix the problem.
2576 */
2577static void gfar_reset_task(struct work_struct *work)
1da177e4 2578{
ab939905 2579 struct gfar_private *priv = container_of(work, struct gfar_private,
bc4598bc 2580 reset_task);
0851133b 2581 reset_gfar(priv->ndev);
1da177e4
LT		 2582}
2583
ab939905
SS		 2584static void gfar_timeout(struct net_device *dev)
2585{
2586 struct gfar_private *priv = netdev_priv(dev);
2587
2588 dev->stats.tx_errors++;
2589 schedule_work(&priv->reset_task);
2590}
2591
acbc0f03
EL		 2592static void gfar_align_skb(struct sk_buff *skb)
2593{
2594 /* We need the data buffer to be aligned properly. We will reserve
2595 * as many bytes as needed to align the data properly
2596 */
2597 skb_reserve(skb, RXBUF_ALIGNMENT -
bc4598bc 2598 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
acbc0f03
EL		 2599}
2600
1da177e4 2601/* Interrupt Handler for Transmit complete */
c233cf40 2602static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2603{
a12f801d 2604 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2605 struct netdev_queue *txq;
d080cd63 2606 struct gfar_private *priv = netdev_priv(dev);
f0ee7acf 2607 struct txbd8 *bdp, *next = NULL;
4669bc90 2608 struct txbd8 *lbdp = NULL;
a12f801d 2609 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2610 struct sk_buff *skb;
2611 int skb_dirtytx;
a12f801d 2612 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2613 int frags = 0, nr_txbds = 0;
4669bc90 2614 int i;
d080cd63 2615 int howmany = 0;
d8a0f1b0
PG		 2616 int tqi = tx_queue->qindex;
2617 unsigned int bytes_sent = 0;
4669bc90 2618 u32 lstatus;
f0ee7acf 2619 size_t buflen;
1da177e4 2620
d8a0f1b0 2621 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2622 bdp = tx_queue->dirty_tx;
2623 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2624
a12f801d 2625 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11 2626
4669bc90 2627 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf 2628
0977f817 2629 /* When time stamping, one additional TxBD must be freed.
f0ee7acf
MR		 2630 * Also, we need to dma_unmap_single() the TxPAL.
2631 */
2244d07b 2632 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2633 nr_txbds = frags + 2;
2634 else
2635 nr_txbds = frags + 1;
2636
2637 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2638
a7312d58 2639 lstatus = be32_to_cpu(lbdp->lstatus);
1da177e4 2640
4669bc90
DH		 2641 /* Only clean completed frames */
2642 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
bc4598bc 2643 (lstatus & BD_LENGTH_MASK))
4669bc90
DH		 2644 break;
2645
2244d07b 2646 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2647 next = next_txbd(bdp, base, tx_ring_size);
a7312d58
CM		 2648 buflen = be16_to_cpu(next->length) +
2649 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf 2650 } else
a7312d58 2651 buflen = be16_to_cpu(bdp->length);
f0ee7acf 2652
a7312d58 2653 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
bc4598bc 2654 buflen, DMA_TO_DEVICE);
f0ee7acf 2655
2244d07b 2656 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2657 struct skb_shared_hwtstamps shhwtstamps;
2658 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
bc4598bc 2659
f0ee7acf
MR		 2660 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2661 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2662 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf 2663 skb_tstamp_tx(skb, &shhwtstamps);
a7312d58 2664 gfar_clear_txbd_status(bdp);
f0ee7acf
MR		 2665 bdp = next;
2666 }
81183059 2667
a7312d58 2668 gfar_clear_txbd_status(bdp);
4669bc90 2669 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2670
4669bc90 2671 for (i = 0; i < frags; i++) {
a7312d58
CM		 2672 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2673 be16_to_cpu(bdp->length),
2674 DMA_TO_DEVICE);
2675 gfar_clear_txbd_status(bdp);
4669bc90
DH		 2676 bdp = next_txbd(bdp, base, tx_ring_size);
2677 }
1da177e4 2678
50ad076b 2679 bytes_sent += GFAR_CB(skb)->bytes_sent;
d8a0f1b0 2680
acb600de 2681 dev_kfree_skb_any(skb);
0fd56bb5 2682
a12f801d 2683 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2684
4669bc90 2685 skb_dirtytx = (skb_dirtytx + 1) &
bc4598bc 2686 TX_RING_MOD_MASK(tx_ring_size);
4669bc90
DH		 2687
2688 howmany++;
bc602280 2689 spin_lock(&tx_queue->txlock);
f0ee7acf 2690 tx_queue->num_txbdfree += nr_txbds;
bc602280 2691 spin_unlock(&tx_queue->txlock);
4669bc90 2692 }
1da177e4 2693
4669bc90 2694 /* If we freed a buffer, we can restart transmission, if necessary */
0851133b
CM		 2695 if (tx_queue->num_txbdfree &&
2696 netif_tx_queue_stopped(txq) &&
2697 !(test_bit(GFAR_DOWN, &priv->state)))
2698 netif_wake_subqueue(priv->ndev, tqi);
1da177e4 2699
4669bc90 2700 /* Update dirty indicators */
a12f801d
SG		 2701 tx_queue->skb_dirtytx = skb_dirtytx;
2702 tx_queue->dirty_tx = bdp;
1da177e4 2703
d8a0f1b0 2704 netdev_tx_completed_queue(txq, howmany, bytes_sent);
d080cd63
DH		 2705}
2706
2281a0f3 2707static struct sk_buff *gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2708{
2709 struct gfar_private *priv = netdev_priv(dev);
acb600de 2710 struct sk_buff *skb;
1da177e4 2711
acbc0f03 2712 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2713 if (!skb)
1da177e4
LT		 2714 return NULL;
2715
acbc0f03 2716 gfar_align_skb(skb);
7f7f5316 2717
acbc0f03
EL		 2718 return skb;
2719}
2720
91c53f76 2721static struct sk_buff *gfar_new_skb(struct net_device *dev, dma_addr_t *bufaddr)
acbc0f03 2722{
0a4b5a24
KH		 2723 struct gfar_private *priv = netdev_priv(dev);
2724 struct sk_buff *skb;
2725 dma_addr_t addr;
2726
2727 skb = gfar_alloc_skb(dev);
2728 if (!skb)
2729 return NULL;
2730
2731 addr = dma_map_single(priv->dev, skb->data,
2732 priv->rx_buffer_size, DMA_FROM_DEVICE);
2733 if (unlikely(dma_mapping_error(priv->dev, addr))) {
2734 dev_kfree_skb_any(skb);
2735 return NULL;
2736 }
2737
2738 *bufaddr = addr;
2739 return skb;
1da177e4
LT		 2740}
2741
298e1a9e 2742static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2743{
298e1a9e 2744 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2745 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2746 struct gfar_extra_stats *estats = &priv->extra_stats;
2747
0977f817 2748 /* If the packet was truncated, none of the other errors matter */
1da177e4
LT		 2749 if (status & RXBD_TRUNCATED) {
2750 stats->rx_length_errors++;
2751
212079df 2752 atomic64_inc(&estats->rx_trunc);
1da177e4
LT		 2753
2754 return;
2755 }
2756 /* Count the errors, if there were any */
2757 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2758 stats->rx_length_errors++;
2759
2760 if (status & RXBD_LARGE)
212079df 2761 atomic64_inc(&estats->rx_large);
1da177e4 2762 else
212079df 2763 atomic64_inc(&estats->rx_short);
1da177e4
LT		 2764 }
2765 if (status & RXBD_NONOCTET) {
2766 stats->rx_frame_errors++;
212079df 2767 atomic64_inc(&estats->rx_nonoctet);
1da177e4
LT		 2768 }
2769 if (status & RXBD_CRCERR) {
212079df 2770 atomic64_inc(&estats->rx_crcerr);
1da177e4
LT		 2771 stats->rx_crc_errors++;
2772 }
2773 if (status & RXBD_OVERRUN) {
212079df 2774 atomic64_inc(&estats->rx_overrun);
1da177e4
LT		 2775 stats->rx_crc_errors++;
2776 }
2777}
2778
f4983704 2779irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2780{
aeb12c5e
CM		 2781 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2782 unsigned long flags;
2783 u32 imask;
2784
2785 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2786 spin_lock_irqsave(&grp->grplock, flags);
2787 imask = gfar_read(&grp->regs->imask);
2788 imask &= IMASK_RX_DISABLED;
2789 gfar_write(&grp->regs->imask, imask);
2790 spin_unlock_irqrestore(&grp->grplock, flags);
2791 __napi_schedule(&grp->napi_rx);
2792 } else {
2793 /* Clear IEVENT, so interrupts aren't called again
2794 * because of the packets that have already arrived.
2795 */
2796 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2797 }
2798
2799 return IRQ_HANDLED;
2800}
2801
2802/* Interrupt Handler for Transmit complete */
2803static irqreturn_t gfar_transmit(int irq, void *grp_id)
2804{
2805 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2806 unsigned long flags;
2807 u32 imask;
2808
2809 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2810 spin_lock_irqsave(&grp->grplock, flags);
2811 imask = gfar_read(&grp->regs->imask);
2812 imask &= IMASK_TX_DISABLED;
2813 gfar_write(&grp->regs->imask, imask);
2814 spin_unlock_irqrestore(&grp->grplock, flags);
2815 __napi_schedule(&grp->napi_tx);
2816 } else {
2817 /* Clear IEVENT, so interrupts aren't called again
2818 * because of the packets that have already arrived.
2819 */
2820 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2821 }
2822
1da177e4
LT		 2823 return IRQ_HANDLED;
2824}
2825
0bbaf069
KG		 2826static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2827{
2828 /* If valid headers were found, and valid sums
2829 * were verified, then we tell the kernel that no
0977f817
JC		 2830 * checksumming is necessary. Otherwise, it is [FIXME]
2831 */
26eb9374
CM		 2832 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2833 (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2834 skb->ip_summed = CHECKSUM_UNNECESSARY;
2835 else
bc8acf2c 2836 skb_checksum_none_assert(skb);
0bbaf069
KG		 2837}
2838
0977f817 2839/* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
61db26c6
CM		 2840static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2841 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2842{
2843 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2844 struct rxfcb *fcb = NULL;
1da177e4 2845
2c2db48a
DH		 2846 /* fcb is at the beginning if exists */
2847 fcb = (struct rxfcb *)skb->data;
0bbaf069 2848
0977f817
JC		 2849 /* Remove the FCB from the skb
2850 * Remove the padded bytes, if there are any
2851 */
f74dac08
SG		 2852 if (amount_pull) {
2853 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2854 skb_pull(skb, amount_pull);
f74dac08 2855 }
0bbaf069 2856
cc772ab7
MR		 2857 /* Get receive timestamp from the skb */
2858 if (priv->hwts_rx_en) {
2859 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2860 u64 *ns = (u64 *) skb->data;
bc4598bc 2861
cc772ab7
MR		 2862 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2863 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2864 }
2865
2866 if (priv->padding)
2867 skb_pull(skb, priv->padding);
2868
8b3afe95 2869 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2870 gfar_rx_checksum(skb, fcb);
0bbaf069 2871
2c2db48a
DH		 2872 /* Tell the skb what kind of packet this is */
2873 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2874
f646968f 2875 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
32f7fd44
JP		 2876 * Even if vlan rx accel is disabled, on some chips
2877 * RXFCB_VLN is pseudo randomly set.
2878 */
f646968f 2879 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
26eb9374
CM		 2880 be16_to_cpu(fcb->flags) & RXFCB_VLN)
2881 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2882 be16_to_cpu(fcb->vlctl));
87c288c6 2883
2c2db48a 2884 /* Send the packet up the stack */
953d2768 2885 napi_gro_receive(napi, skb);
0bbaf069 2886
1da177e4
LT		 2887}
2888
2889/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2281a0f3
JC		 2890 * until the budget/quota has been reached. Returns the number
2891 * of frames handled
1da177e4 2892 */
a12f801d 2893int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2894{
a12f801d 2895 struct net_device *dev = rx_queue->dev;
31de198b 2896 struct rxbd8 *bdp, *base;
1da177e4 2897 struct sk_buff *skb;
2c2db48a
DH		 2898 int pkt_len;
2899 int amount_pull;
1da177e4
LT		 2900 int howmany = 0;
2901 struct gfar_private *priv = netdev_priv(dev);
2902
2903 /* Get the first full descriptor */
a12f801d
SG		 2904 bdp = rx_queue->cur_rx;
2905 base = rx_queue->rx_bd_base;
1da177e4 2906
ba779711 2907 amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0;
2c2db48a 2908
a7312d58 2909 while (!(be16_to_cpu(bdp->status) & RXBD_EMPTY) && rx_work_limit--) {
815b97c6 2910 struct sk_buff *newskb;
0a4b5a24 2911 dma_addr_t bufaddr;
bc4598bc 2912
3b6330ce 2913 rmb();
815b97c6
AF		 2914
2915 /* Add another skb for the future */
0a4b5a24 2916 newskb = gfar_new_skb(dev, &bufaddr);
815b97c6 2917
a12f801d 2918 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2919
a7312d58 2920 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
bc4598bc 2921 priv->rx_buffer_size, DMA_FROM_DEVICE);
81183059 2922
a7312d58
CM		 2923 if (unlikely(!(be16_to_cpu(bdp->status) & RXBD_ERR) &&
2924 be16_to_cpu(bdp->length) > priv->rx_buffer_size))
2925 bdp->status = cpu_to_be16(RXBD_LARGE);
63b88b90 2926
815b97c6 2927 /* We drop the frame if we failed to allocate a new buffer */
a7312d58
CM		 2928 if (unlikely(!newskb ||
2929 !(be16_to_cpu(bdp->status) & RXBD_LAST) ||
2930 be16_to_cpu(bdp->status) & RXBD_ERR)) {
2931 count_errors(be16_to_cpu(bdp->status), dev);
815b97c6 2932
0a4b5a24 2933 if (unlikely(!newskb)) {
815b97c6 2934 newskb = skb;
a7312d58 2935 bufaddr = be32_to_cpu(bdp->bufPtr);
0a4b5a24 2936 } else if (skb)
acb600de 2937 dev_kfree_skb(skb);
815b97c6 2938 } else {
1da177e4 2939 /* Increment the number of packets */
a7f38041 2940 rx_queue->stats.rx_packets++;
1da177e4
LT		 2941 howmany++;
2942
2c2db48a 2943 if (likely(skb)) {
a7312d58
CM		 2944 pkt_len = be16_to_cpu(bdp->length) -
2945 ETH_FCS_LEN;
2c2db48a
DH		 2946 /* Remove the FCS from the packet length */
2947 skb_put(skb, pkt_len);
a7f38041 2948 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2949 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57 2950 gfar_process_frame(dev, skb, amount_pull,
aeb12c5e 2951 &rx_queue->grp->napi_rx);
2c2db48a
DH		 2952
2953 } else {
59deab26 2954 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2955 rx_queue->stats.rx_dropped++;
212079df 2956 atomic64_inc(&priv->extra_stats.rx_skbmissing);
2c2db48a 2957 }
1da177e4 2958
1da177e4
LT		 2959 }
2960
a12f801d 2961 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2962
815b97c6 2963 /* Setup the new bdp */
0a4b5a24 2964 gfar_init_rxbdp(rx_queue, bdp, bufaddr);
1da177e4 2965
45b679c9
MP		 2966 /* Update Last Free RxBD pointer for LFC */
2967 if (unlikely(rx_queue->rfbptr && priv->tx_actual_en))
2968 gfar_write(rx_queue->rfbptr, (u32)bdp);
2969
1da177e4 2970 /* Update to the next pointer */
a12f801d 2971 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2972
2973 /* update to point at the next skb */
bc4598bc
JC		 2974 rx_queue->skb_currx = (rx_queue->skb_currx + 1) &
2975 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2976 }
2977
2978 /* Update the current rxbd pointer to be the next one */
a12f801d 2979 rx_queue->cur_rx = bdp;
1da177e4 2980
1da177e4
LT		 2981 return howmany;
2982}
2983
aeb12c5e 2984static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
5eaedf31
CM		 2985{
2986 struct gfar_priv_grp *gfargrp =
aeb12c5e 2987 container_of(napi, struct gfar_priv_grp, napi_rx);
5eaedf31 2988 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 2989 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
5eaedf31
CM		 2990 int work_done = 0;
2991
2992 /* Clear IEVENT, so interrupts aren't called again
2993 * because of the packets that have already arrived
2994 */
aeb12c5e 2995 gfar_write(&regs->ievent, IEVENT_RX_MASK);
5eaedf31
CM		 2996
2997 work_done = gfar_clean_rx_ring(rx_queue, budget);
2998
2999 if (work_done < budget) {
aeb12c5e 3000 u32 imask;
5eaedf31
CM		 3001 napi_complete(napi);
3002 /* Clear the halt bit in RSTAT */
3003 gfar_write(&regs->rstat, gfargrp->rstat);
3004
aeb12c5e
CM		 3005 spin_lock_irq(&gfargrp->grplock);
3006 imask = gfar_read(&regs->imask);
3007 imask |= IMASK_RX_DEFAULT;
3008 gfar_write(&regs->imask, imask);
3009 spin_unlock_irq(&gfargrp->grplock);
5eaedf31
CM		 3010 }
3011
3012 return work_done;
3013}
3014
aeb12c5e 3015static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
1da177e4 3016{
bc4598bc 3017 struct gfar_priv_grp *gfargrp =
aeb12c5e
CM		 3018 container_of(napi, struct gfar_priv_grp, napi_tx);
3019 struct gfar __iomem *regs = gfargrp->regs;
71ff9e3d 3020 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
aeb12c5e
CM		 3021 u32 imask;
3022
3023 /* Clear IEVENT, so interrupts aren't called again
3024 * because of the packets that have already arrived
3025 */
3026 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3027
3028 /* run Tx cleanup to completion */
3029 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3030 gfar_clean_tx_ring(tx_queue);
3031
3032 napi_complete(napi);
3033
3034 spin_lock_irq(&gfargrp->grplock);
3035 imask = gfar_read(&regs->imask);
3036 imask |= IMASK_TX_DEFAULT;
3037 gfar_write(&regs->imask, imask);
3038 spin_unlock_irq(&gfargrp->grplock);
3039
3040 return 0;
3041}
3042
3043static int gfar_poll_rx(struct napi_struct *napi, int budget)
3044{
3045 struct gfar_priv_grp *gfargrp =
3046 container_of(napi, struct gfar_priv_grp, napi_rx);
fba4ed03 3047 struct gfar_private *priv = gfargrp->priv;
46ceb60c 3048 struct gfar __iomem *regs = gfargrp->regs;
fba4ed03 3049 struct gfar_priv_rx_q *rx_queue = NULL;
c233cf40 3050 int work_done = 0, work_done_per_q = 0;
39c0a0d5 3051 int i, budget_per_q = 0;
6be5ed3f
CM		 3052 unsigned long rstat_rxf;
3053 int num_act_queues;
fba4ed03 3054
8c7396ae 3055 /* Clear IEVENT, so interrupts aren't called again
0977f817
JC		 3056 * because of the packets that have already arrived
3057 */
aeb12c5e 3058 gfar_write(&regs->ievent, IEVENT_RX_MASK);
8c7396ae 3059
6be5ed3f
CM		 3060 rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3061
3062 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3063 if (num_act_queues)
3064 budget_per_q = budget/num_act_queues;
3065
3ba405db
CM		 3066 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3067 /* skip queue if not active */
3068 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3069 continue;
1da177e4 3070
3ba405db
CM		 3071 rx_queue = priv->rx_queue[i];
3072 work_done_per_q =
3073 gfar_clean_rx_ring(rx_queue, budget_per_q);
3074 work_done += work_done_per_q;
3075
3076 /* finished processing this queue */
3077 if (work_done_per_q < budget_per_q) {
3078 /* clear active queue hw indication */
3079 gfar_write(&regs->rstat,
3080 RSTAT_CLEAR_RXF0 >> i);
3081 num_act_queues--;
3082
3083 if (!num_act_queues)
3084 break;
3085 }
3086 }
42199884 3087
aeb12c5e
CM		 3088 if (!num_act_queues) {
3089 u32 imask;
3ba405db 3090 napi_complete(napi);
1da177e4 3091
3ba405db
CM		 3092 /* Clear the halt bit in RSTAT */
3093 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 3094
aeb12c5e
CM		 3095 spin_lock_irq(&gfargrp->grplock);
3096 imask = gfar_read(&regs->imask);
3097 imask |= IMASK_RX_DEFAULT;
3098 gfar_write(&regs->imask, imask);
3099 spin_unlock_irq(&gfargrp->grplock);
1da177e4
LT		 3100 }
3101
c233cf40 3102 return work_done;
1da177e4 3103}
1da177e4 3104
aeb12c5e
CM		 3105static int gfar_poll_tx(struct napi_struct *napi, int budget)
3106{
3107 struct gfar_priv_grp *gfargrp =
3108 container_of(napi, struct gfar_priv_grp, napi_tx);
3109 struct gfar_private *priv = gfargrp->priv;
3110 struct gfar __iomem *regs = gfargrp->regs;
3111 struct gfar_priv_tx_q *tx_queue = NULL;
3112 int has_tx_work = 0;
3113 int i;
3114
3115 /* Clear IEVENT, so interrupts aren't called again
3116 * because of the packets that have already arrived
3117 */
3118 gfar_write(&regs->ievent, IEVENT_TX_MASK);
3119
3120 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3121 tx_queue = priv->tx_queue[i];
3122 /* run Tx cleanup to completion */
3123 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3124 gfar_clean_tx_ring(tx_queue);
3125 has_tx_work = 1;
3126 }
3127 }
3128
3129 if (!has_tx_work) {
3130 u32 imask;
3131 napi_complete(napi);
3132
3133 spin_lock_irq(&gfargrp->grplock);
3134 imask = gfar_read(&regs->imask);
3135 imask |= IMASK_TX_DEFAULT;
3136 gfar_write(&regs->imask, imask);
3137 spin_unlock_irq(&gfargrp->grplock);
3138 }
3139
3140 return 0;
3141}
3142
3143
f2d71c2d 3144#ifdef CONFIG_NET_POLL_CONTROLLER
0977f817 3145/* Polling 'interrupt' - used by things like netconsole to send skbs
f2d71c2d
VW		 3146 * without having to re-enable interrupts. It's not called while
3147 * the interrupt routine is executing.
3148 */
3149static void gfar_netpoll(struct net_device *dev)
3150{
3151 struct gfar_private *priv = netdev_priv(dev);
3a2e16c8 3152 int i;
f2d71c2d
VW		 3153
3154 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 3155 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c 3156 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3157 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3158
3159 disable_irq(gfar_irq(grp, TX)->irq);
3160 disable_irq(gfar_irq(grp, RX)->irq);
3161 disable_irq(gfar_irq(grp, ER)->irq);
3162 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3163 enable_irq(gfar_irq(grp, ER)->irq);
3164 enable_irq(gfar_irq(grp, RX)->irq);
3165 enable_irq(gfar_irq(grp, TX)->irq);
46ceb60c 3166 }
f2d71c2d 3167 } else {
46ceb60c 3168 for (i = 0; i < priv->num_grps; i++) {
62ed839d
PG		 3169 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3170
3171 disable_irq(gfar_irq(grp, TX)->irq);
3172 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3173 enable_irq(gfar_irq(grp, TX)->irq);
43de004b 3174 }
f2d71c2d
VW		 3175 }
3176}
3177#endif
3178
1da177e4 3179/* The interrupt handler for devices with one interrupt */
f4983704 3180static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 3181{
f4983704 3182 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 3183
3184 /* Save ievent for future reference */
f4983704 3185 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 3186
1da177e4 3187 /* Check for reception */
538cc7ee 3188 if (events & IEVENT_RX_MASK)
f4983704 3189 gfar_receive(irq, grp_id);
1da177e4
LT		 3190
3191 /* Check for transmit completion */
538cc7ee 3192 if (events & IEVENT_TX_MASK)
f4983704 3193 gfar_transmit(irq, grp_id);
1da177e4 3194
538cc7ee
SS		 3195 /* Check for errors */
3196 if (events & IEVENT_ERR_MASK)
f4983704 3197 gfar_error(irq, grp_id);
1da177e4
LT		 3198
3199 return IRQ_HANDLED;
3200}
3201
1da177e4
LT		 3202/* Called every time the controller might need to be made
3203 * aware of new link state. The PHY code conveys this
bb40dcbb 3204 * information through variables in the phydev structure, and this
1da177e4
LT		 3205 * function converts those variables into the appropriate
3206 * register values, and can bring down the device if needed.
3207 */
3208static void adjust_link(struct net_device *dev)
3209{
3210 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 3211 struct phy_device *phydev = priv->phydev;
bb40dcbb 3212
6ce29b0e 3213 if (unlikely(phydev->link != priv->oldlink ||
0ae93b2c
GR		 3214 (phydev->link && (phydev->duplex != priv->oldduplex ||
3215 phydev->speed != priv->oldspeed))))
6ce29b0e 3216 gfar_update_link_state(priv);
bb40dcbb 3217}
1da177e4
LT		 3218
3219/* Update the hash table based on the current list of multicast
3220 * addresses we subscribe to. Also, change the promiscuity of
3221 * the device based on the flags (this function is called
0977f817
JC		 3222 * whenever dev->flags is changed
3223 */
1da177e4
LT		 3224static void gfar_set_multi(struct net_device *dev)
3225{
22bedad3 3226 struct netdev_hw_addr *ha;
1da177e4 3227 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3228 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3229 u32 tempval;
3230
a12f801d 3231 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3232 /* Set RCTRL to PROM */
3233 tempval = gfar_read(&regs->rctrl);
3234 tempval |= RCTRL_PROM;
3235 gfar_write(&regs->rctrl, tempval);
3236 } else {
3237 /* Set RCTRL to not PROM */
3238 tempval = gfar_read(&regs->rctrl);
3239 tempval &= ~(RCTRL_PROM);
3240 gfar_write(&regs->rctrl, tempval);
3241 }
6aa20a22 3242
a12f801d 3243 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3244 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3245 gfar_write(&regs->igaddr0, 0xffffffff);
3246 gfar_write(&regs->igaddr1, 0xffffffff);
3247 gfar_write(&regs->igaddr2, 0xffffffff);
3248 gfar_write(&regs->igaddr3, 0xffffffff);
3249 gfar_write(&regs->igaddr4, 0xffffffff);
3250 gfar_write(&regs->igaddr5, 0xffffffff);
3251 gfar_write(&regs->igaddr6, 0xffffffff);
3252 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3253 gfar_write(&regs->gaddr0, 0xffffffff);
3254 gfar_write(&regs->gaddr1, 0xffffffff);
3255 gfar_write(&regs->gaddr2, 0xffffffff);
3256 gfar_write(&regs->gaddr3, 0xffffffff);
3257 gfar_write(&regs->gaddr4, 0xffffffff);
3258 gfar_write(&regs->gaddr5, 0xffffffff);
3259 gfar_write(&regs->gaddr6, 0xffffffff);
3260 gfar_write(&regs->gaddr7, 0xffffffff);
3261 } else {
7f7f5316
AF		 3262 int em_num;
3263 int idx;
3264
1da177e4 3265 /* zero out the hash */
0bbaf069
KG		 3266 gfar_write(&regs->igaddr0, 0x0);
3267 gfar_write(&regs->igaddr1, 0x0);
3268 gfar_write(&regs->igaddr2, 0x0);
3269 gfar_write(&regs->igaddr3, 0x0);
3270 gfar_write(&regs->igaddr4, 0x0);
3271 gfar_write(&regs->igaddr5, 0x0);
3272 gfar_write(&regs->igaddr6, 0x0);
3273 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3274 gfar_write(&regs->gaddr0, 0x0);
3275 gfar_write(&regs->gaddr1, 0x0);
3276 gfar_write(&regs->gaddr2, 0x0);
3277 gfar_write(&regs->gaddr3, 0x0);
3278 gfar_write(&regs->gaddr4, 0x0);
3279 gfar_write(&regs->gaddr5, 0x0);
3280 gfar_write(&regs->gaddr6, 0x0);
3281 gfar_write(&regs->gaddr7, 0x0);
3282
7f7f5316
AF		 3283 /* If we have extended hash tables, we need to
3284 * clear the exact match registers to prepare for
0977f817
JC		 3285 * setting them
3286 */
7f7f5316
AF		 3287 if (priv->extended_hash) {
3288 em_num = GFAR_EM_NUM + 1;
3289 gfar_clear_exact_match(dev);
3290 idx = 1;
3291 } else {
3292 idx = 0;
3293 em_num = 0;
3294 }
3295
4cd24eaf 3296 if (netdev_mc_empty(dev))
1da177e4
LT		 3297 return;
3298
3299 /* Parse the list, and set the appropriate bits */
22bedad3 3300 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3301 if (idx < em_num) {
22bedad3 3302 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3303 idx++;
3304 } else
22bedad3 3305 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3306 }
3307 }
1da177e4
LT		 3308}
3309
7f7f5316
AF		 3310
3311/* Clears each of the exact match registers to zero, so they
0977f817
JC		 3312 * don't interfere with normal reception
3313 */
7f7f5316
AF		 3314static void gfar_clear_exact_match(struct net_device *dev)
3315{
3316 int idx;
6a3c910c 3317 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316 3318
bc4598bc 3319 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
b6bc7650 3320 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3321}
3322
1da177e4
LT		 3323/* Set the appropriate hash bit for the given addr */
3324/* The algorithm works like so:
3325 * 1) Take the Destination Address (ie the multicast address), and
3326 * do a CRC on it (little endian), and reverse the bits of the
3327 * result.
3328 * 2) Use the 8 most significant bits as a hash into a 256-entry
3329 * table. The table is controlled through 8 32-bit registers:
3330 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3331 * gaddr7. This means that the 3 most significant bits in the
3332 * hash index which gaddr register to use, and the 5 other bits
3333 * indicate which bit (assuming an IBM numbering scheme, which
3334 * for PowerPC (tm) is usually the case) in the register holds
0977f817
JC		 3335 * the entry.
3336 */
1da177e4
LT		 3337static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3338{
3339 u32 tempval;
3340 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3341 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3342 int width = priv->hash_width;
3343 u8 whichbit = (result >> (32 - width)) & 0x1f;
3344 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3345 u32 value = (1 << (31-whichbit));
3346
0bbaf069 3347 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3348 tempval |= value;
0bbaf069 3349 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3350}
3351
7f7f5316
AF		 3352
3353/* There are multiple MAC Address register pairs on some controllers
3354 * This function sets the numth pair to a given address
3355 */
b6bc7650
JP		 3356static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3357 const u8 *addr)
7f7f5316
AF		 3358{
3359 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3360 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3361 u32 tempval;
f4983704 3362 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3363
3364 macptr += num*2;
3365
83bfc3c4
CM		 3366 /* For a station address of 0x12345678ABCD in transmission
3367 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3368 * MACnADDR2 is set to 0x34120000.
0977f817 3369 */
83bfc3c4
CM		 3370 tempval = (addr[5] << 24) | (addr[4] << 16) |
3371 (addr[3] << 8) | addr[2];
7f7f5316 3372
83bfc3c4 3373 gfar_write(macptr, tempval);
7f7f5316 3374
83bfc3c4 3375 tempval = (addr[1] << 24) | (addr[0] << 16);
7f7f5316
AF		 3376
3377 gfar_write(macptr+1, tempval);
3378}
3379
1da177e4 3380/* GFAR error interrupt handler */
f4983704 3381static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3382{
f4983704
SG		 3383 struct gfar_priv_grp *gfargrp = grp_id;
3384 struct gfar __iomem *regs = gfargrp->regs;
3385 struct gfar_private *priv= gfargrp->priv;
3386 struct net_device *dev = priv->ndev;
1da177e4
LT		 3387
3388 /* Save ievent for future reference */
f4983704 3389 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3390
3391 /* Clear IEVENT */
f4983704 3392 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3393
3394 /* Magic Packet is not an error. */
b31a1d8b 3395 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3396 (events & IEVENT_MAG))
3397 events &= ~IEVENT_MAG;
1da177e4
LT		 3398
3399 /* Hmm... */
0bbaf069 3400 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
bc4598bc
JC		 3401 netdev_dbg(dev,
3402 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
59deab26 3403 events, gfar_read(&regs->imask));
1da177e4
LT		 3404
3405 /* Update the error counters */
3406 if (events & IEVENT_TXE) {
09f75cd7 3407 dev->stats.tx_errors++;
1da177e4
LT		 3408
3409 if (events & IEVENT_LC)
09f75cd7 3410 dev->stats.tx_window_errors++;
1da177e4 3411 if (events & IEVENT_CRL)
09f75cd7 3412 dev->stats.tx_aborted_errors++;
1da177e4 3413 if (events & IEVENT_XFUN) {
59deab26
JP		 3414 netif_dbg(priv, tx_err, dev,
3415 "TX FIFO underrun, packet dropped\n");
09f75cd7 3416 dev->stats.tx_dropped++;
212079df 3417 atomic64_inc(&priv->extra_stats.tx_underrun);
1da177e4 3418
bc602280 3419 schedule_work(&priv->reset_task);
1da177e4 3420 }
59deab26 3421 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3422 }
3423 if (events & IEVENT_BSY) {
09f75cd7 3424 dev->stats.rx_errors++;
212079df 3425 atomic64_inc(&priv->extra_stats.rx_bsy);
1da177e4 3426
f4983704 3427 gfar_receive(irq, grp_id);
1da177e4 3428
59deab26
JP		 3429 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3430 gfar_read(&regs->rstat));
1da177e4
LT		 3431 }
3432 if (events & IEVENT_BABR) {
09f75cd7 3433 dev->stats.rx_errors++;
212079df 3434 atomic64_inc(&priv->extra_stats.rx_babr);
1da177e4 3435
59deab26 3436 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3437 }
3438 if (events & IEVENT_EBERR) {
212079df 3439 atomic64_inc(&priv->extra_stats.eberr);
59deab26 3440 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3441 }
59deab26
JP		 3442 if (events & IEVENT_RXC)
3443 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3444
3445 if (events & IEVENT_BABT) {
212079df 3446 atomic64_inc(&priv->extra_stats.tx_babt);
59deab26 3447 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3448 }
3449 return IRQ_HANDLED;
3450}
3451
6ce29b0e
CM		 3452static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3453{
3454 struct phy_device *phydev = priv->phydev;
3455 u32 val = 0;
3456
3457 if (!phydev->duplex)
3458 return val;
3459
3460 if (!priv->pause_aneg_en) {
3461 if (priv->tx_pause_en)
3462 val |= MACCFG1_TX_FLOW;
3463 if (priv->rx_pause_en)
3464 val |= MACCFG1_RX_FLOW;
3465 } else {
3466 u16 lcl_adv, rmt_adv;
3467 u8 flowctrl;
3468 /* get link partner capabilities */
3469 rmt_adv = 0;
3470 if (phydev->pause)
3471 rmt_adv = LPA_PAUSE_CAP;
3472 if (phydev->asym_pause)
3473 rmt_adv |= LPA_PAUSE_ASYM;
3474
43ef8d29
PMB		 3475 lcl_adv = 0;
3476 if (phydev->advertising & ADVERTISED_Pause)
3477 lcl_adv |= ADVERTISE_PAUSE_CAP;
3478 if (phydev->advertising & ADVERTISED_Asym_Pause)
3479 lcl_adv |= ADVERTISE_PAUSE_ASYM;
6ce29b0e
CM		 3480
3481 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3482 if (flowctrl & FLOW_CTRL_TX)
3483 val |= MACCFG1_TX_FLOW;
3484 if (flowctrl & FLOW_CTRL_RX)
3485 val |= MACCFG1_RX_FLOW;
3486 }
3487
3488 return val;
3489}
3490
3491static noinline void gfar_update_link_state(struct gfar_private *priv)
3492{
3493 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3494 struct phy_device *phydev = priv->phydev;
45b679c9
MP		 3495 struct gfar_priv_rx_q *rx_queue = NULL;
3496 int i;
3497 struct rxbd8 *bdp;
6ce29b0e
CM		 3498
3499 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3500 return;
3501
3502 if (phydev->link) {
3503 u32 tempval1 = gfar_read(&regs->maccfg1);
3504 u32 tempval = gfar_read(&regs->maccfg2);
3505 u32 ecntrl = gfar_read(&regs->ecntrl);
45b679c9 3506 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
6ce29b0e
CM		 3507
3508 if (phydev->duplex != priv->oldduplex) {
3509 if (!(phydev->duplex))
3510 tempval &= ~(MACCFG2_FULL_DUPLEX);
3511 else
3512 tempval |= MACCFG2_FULL_DUPLEX;
3513
3514 priv->oldduplex = phydev->duplex;
3515 }
3516
3517 if (phydev->speed != priv->oldspeed) {
3518 switch (phydev->speed) {
3519 case 1000:
3520 tempval =
3521 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3522
3523 ecntrl &= ~(ECNTRL_R100);
3524 break;
3525 case 100:
3526 case 10:
3527 tempval =
3528 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3529
3530 /* Reduced mode distinguishes
3531 * between 10 and 100
3532 */
3533 if (phydev->speed == SPEED_100)
3534 ecntrl |= ECNTRL_R100;
3535 else
3536 ecntrl &= ~(ECNTRL_R100);
3537 break;
3538 default:
3539 netif_warn(priv, link, priv->ndev,
3540 "Ack! Speed (%d) is not 10/100/1000!\n",
3541 phydev->speed);
3542 break;
3543 }
3544
3545 priv->oldspeed = phydev->speed;
3546 }
3547
3548 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3549 tempval1 |= gfar_get_flowctrl_cfg(priv);
3550
45b679c9
MP		 3551 /* Turn last free buffer recording on */
3552 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3553 for (i = 0; i < priv->num_rx_queues; i++) {
3554 rx_queue = priv->rx_queue[i];
3555 bdp = rx_queue->cur_rx;
3556 /* skip to previous bd */
3557 bdp = skip_bd(bdp, rx_queue->rx_ring_size - 1,
3558 rx_queue->rx_bd_base,
3559 rx_queue->rx_ring_size);
3560
3561 if (rx_queue->rfbptr)
3562 gfar_write(rx_queue->rfbptr, (u32)bdp);
3563 }
3564
3565 priv->tx_actual_en = 1;
3566 }
3567
3568 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3569 priv->tx_actual_en = 0;
3570
6ce29b0e
CM		 3571 gfar_write(&regs->maccfg1, tempval1);
3572 gfar_write(&regs->maccfg2, tempval);
3573 gfar_write(&regs->ecntrl, ecntrl);
3574
3575 if (!priv->oldlink)
3576 priv->oldlink = 1;
3577
3578 } else if (priv->oldlink) {
3579 priv->oldlink = 0;
3580 priv->oldspeed = 0;
3581 priv->oldduplex = -1;
3582 }
3583
3584 if (netif_msg_link(priv))
3585 phy_print_status(phydev);
3586}
3587
94e5a2a8 3588static const struct of_device_id gfar_match[] =
b31a1d8b
AF		 3589{
3590 {
3591 .type = "network",
3592 .compatible = "gianfar",
3593 },
46ceb60c
SG		 3594 {
3595 .compatible = "fsl,etsec2",
3596 },
b31a1d8b
AF		 3597 {},
3598};
e72701ac 3599MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3600
1da177e4 3601/* Structure for a device driver */
74888760 3602static struct platform_driver gfar_driver = {
4018294b
GL		 3603 .driver = {
3604 .name = "fsl-gianfar",
4018294b
GL		 3605 .pm = GFAR_PM_OPS,
3606 .of_match_table = gfar_match,
3607 },
1da177e4
LT		 3608 .probe = gfar_probe,
3609 .remove = gfar_remove,
3610};
3611
db62f684 3612module_platform_driver(gfar_driver);
Linux kernel - Deliverables
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