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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / drivers / net / ethernet / freescale / gianfar.c
CommitLineData
0bbaf069 1/*
3396c782 2 * drivers/net/ethernet/freescale/gianfar.c
1da177e4
LT		 3 *
4 * Gianfar Ethernet Driver
7f7f5316
AF		 5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
1da177e4
LT		 7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
4c8d3d99 10 * Maintainer: Kumar Gala
a12f801d 11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 12 *
6c43e046 13 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
a12f801d 14 * Copyright 2007 MontaVista Software, Inc.
1da177e4
LT		 15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
0bbaf069 28 *
b31a1d8b
AF		 29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
1da177e4
LT		 31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
0bbaf069
KG		 34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
1da177e4
LT		 36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
0bbaf069 39 * IEVENT register is set, triggering an interrupt when the
1da177e4
LT		 40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
bb40dcbb 43 * of frames or amount of time have passed). In NAPI, the
1da177e4 44 * interrupt handler will signal there is work to be done, and
0aa1538f 45 * exit. This method will start at the last known empty
0bbaf069 46 * descriptor, and process every subsequent descriptor until there
1da177e4
LT		 47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
59deab26
JP		 65#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
66#define DEBUG
67
1da177e4 68#include <linux/kernel.h>
1da177e4
LT		 69#include <linux/string.h>
70#include <linux/errno.h>
bb40dcbb 71#include <linux/unistd.h>
1da177e4
LT		 72#include <linux/slab.h>
73#include <linux/interrupt.h>
74#include <linux/init.h>
75#include <linux/delay.h>
76#include <linux/netdevice.h>
77#include <linux/etherdevice.h>
78#include <linux/skbuff.h>
0bbaf069 79#include <linux/if_vlan.h>
1da177e4
LT		 80#include <linux/spinlock.h>
81#include <linux/mm.h>
fe192a49 82#include <linux/of_mdio.h>
b31a1d8b 83#include <linux/of_platform.h>
0bbaf069
KG		 84#include <linux/ip.h>
85#include <linux/tcp.h>
86#include <linux/udp.h>
9c07b884 87#include <linux/in.h>
cc772ab7 88#include <linux/net_tstamp.h>
1da177e4
LT		 89
90#include <asm/io.h>
7d350977 91#include <asm/reg.h>
1da177e4
LT		 92#include <asm/irq.h>
93#include <asm/uaccess.h>
94#include <linux/module.h>
1da177e4
LT		 95#include <linux/dma-mapping.h>
96#include <linux/crc32.h>
bb40dcbb
AF		 97#include <linux/mii.h>
98#include <linux/phy.h>
b31a1d8b
AF		 99#include <linux/phy_fixed.h>
100#include <linux/of.h>
4b6ba8aa 101#include <linux/of_net.h>
1da177e4
LT		 102
103#include "gianfar.h"
1577ecef 104#include "fsl_pq_mdio.h"
1da177e4
LT		 105
106#define TX_TIMEOUT (1*HZ)
1da177e4 107
7f7f5316 108const char gfar_driver_version[] = "1.3";
1da177e4 109
1da177e4
LT		 110static int gfar_enet_open(struct net_device *dev);
111static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
ab939905 112static void gfar_reset_task(struct work_struct *work);
1da177e4
LT		 113static void gfar_timeout(struct net_device *dev);
114static int gfar_close(struct net_device *dev);
815b97c6 115struct sk_buff *gfar_new_skb(struct net_device *dev);
a12f801d 116static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6 117 struct sk_buff *skb);
1da177e4
LT		 118static int gfar_set_mac_address(struct net_device *dev);
119static int gfar_change_mtu(struct net_device *dev, int new_mtu);
7d12e780
DH		 120static irqreturn_t gfar_error(int irq, void *dev_id);
121static irqreturn_t gfar_transmit(int irq, void *dev_id);
122static irqreturn_t gfar_interrupt(int irq, void *dev_id);
1da177e4
LT		 123static void adjust_link(struct net_device *dev);
124static void init_registers(struct net_device *dev);
125static int init_phy(struct net_device *dev);
74888760 126static int gfar_probe(struct platform_device *ofdev);
2dc11581 127static int gfar_remove(struct platform_device *ofdev);
bb40dcbb 128static void free_skb_resources(struct gfar_private *priv);
1da177e4
LT		 129static void gfar_set_multi(struct net_device *dev);
130static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
d3c12873 131static void gfar_configure_serdes(struct net_device *dev);
bea3348e 132static int gfar_poll(struct napi_struct *napi, int budget);
f2d71c2d
VW		 133#ifdef CONFIG_NET_POLL_CONTROLLER
134static void gfar_netpoll(struct net_device *dev);
135#endif
a12f801d
SG		 136int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
2c2db48a 138static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
cd754a57 139 int amount_pull, struct napi_struct *napi);
7f7f5316 140void gfar_halt(struct net_device *dev);
d87eb127 141static void gfar_halt_nodisable(struct net_device *dev);
7f7f5316
AF		 142void gfar_start(struct net_device *dev);
143static void gfar_clear_exact_match(struct net_device *dev);
b6bc7650
JP		 144static void gfar_set_mac_for_addr(struct net_device *dev, int num,
145 const u8 *addr);
26ccfc37 146static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
1da177e4 147
1da177e4
LT		 148MODULE_AUTHOR("Freescale Semiconductor, Inc");
149MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150MODULE_LICENSE("GPL");
151
a12f801d 152static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
8a102fe0
AV		 153 dma_addr_t buf)
154{
8a102fe0
AV		 155 u32 lstatus;
156
157 bdp->bufPtr = buf;
158
159 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
a12f801d 160 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
8a102fe0
AV		 161 lstatus |= BD_LFLAG(RXBD_WRAP);
162
163 eieio();
164
165 bdp->lstatus = lstatus;
166}
167
8728327e 168static int gfar_init_bds(struct net_device *ndev)
826aa4a0 169{
8728327e 170 struct gfar_private *priv = netdev_priv(ndev);
a12f801d
SG		 171 struct gfar_priv_tx_q *tx_queue = NULL;
172 struct gfar_priv_rx_q *rx_queue = NULL;
826aa4a0
AV		 173 struct txbd8 *txbdp;
174 struct rxbd8 *rxbdp;
fba4ed03 175 int i, j;
a12f801d 176
fba4ed03
SG		 177 for (i = 0; i < priv->num_tx_queues; i++) {
178 tx_queue = priv->tx_queue[i];
179 /* Initialize some variables in our dev structure */
180 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
181 tx_queue->dirty_tx = tx_queue->tx_bd_base;
182 tx_queue->cur_tx = tx_queue->tx_bd_base;
183 tx_queue->skb_curtx = 0;
184 tx_queue->skb_dirtytx = 0;
185
186 /* Initialize Transmit Descriptor Ring */
187 txbdp = tx_queue->tx_bd_base;
188 for (j = 0; j < tx_queue->tx_ring_size; j++) {
189 txbdp->lstatus = 0;
190 txbdp->bufPtr = 0;
191 txbdp++;
192 }
8728327e 193
fba4ed03
SG		 194 /* Set the last descriptor in the ring to indicate wrap */
195 txbdp--;
196 txbdp->status |= TXBD_WRAP;
8728327e
AV		 197 }
198
fba4ed03
SG		 199 for (i = 0; i < priv->num_rx_queues; i++) {
200 rx_queue = priv->rx_queue[i];
201 rx_queue->cur_rx = rx_queue->rx_bd_base;
202 rx_queue->skb_currx = 0;
203 rxbdp = rx_queue->rx_bd_base;
8728327e 204
fba4ed03
SG		 205 for (j = 0; j < rx_queue->rx_ring_size; j++) {
206 struct sk_buff *skb = rx_queue->rx_skbuff[j];
8728327e 207
fba4ed03
SG		 208 if (skb) {
209 gfar_init_rxbdp(rx_queue, rxbdp,
210 rxbdp->bufPtr);
211 } else {
212 skb = gfar_new_skb(ndev);
213 if (!skb) {
59deab26 214 netdev_err(ndev, "Can't allocate RX buffers\n");
fba4ed03
SG		 215 goto err_rxalloc_fail;
216 }
217 rx_queue->rx_skbuff[j] = skb;
218
219 gfar_new_rxbdp(rx_queue, rxbdp, skb);
8728327e 220 }
8728327e 221
fba4ed03 222 rxbdp++;
8728327e
AV		 223 }
224
8728327e
AV		 225 }
226
227 return 0;
fba4ed03
SG		 228
229err_rxalloc_fail:
230 free_skb_resources(priv);
231 return -ENOMEM;
8728327e
AV		 232}
233
234static int gfar_alloc_skb_resources(struct net_device *ndev)
235{
826aa4a0 236 void *vaddr;
fba4ed03
SG		 237 dma_addr_t addr;
238 int i, j, k;
826aa4a0
AV		 239 struct gfar_private *priv = netdev_priv(ndev);
240 struct device *dev = &priv->ofdev->dev;
a12f801d
SG		 241 struct gfar_priv_tx_q *tx_queue = NULL;
242 struct gfar_priv_rx_q *rx_queue = NULL;
243
fba4ed03
SG		 244 priv->total_tx_ring_size = 0;
245 for (i = 0; i < priv->num_tx_queues; i++)
246 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
247
248 priv->total_rx_ring_size = 0;
249 for (i = 0; i < priv->num_rx_queues; i++)
250 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
826aa4a0
AV		 251
252 /* Allocate memory for the buffer descriptors */
8728327e 253 vaddr = dma_alloc_coherent(dev,
fba4ed03
SG		 254 sizeof(struct txbd8) * priv->total_tx_ring_size +
255 sizeof(struct rxbd8) * priv->total_rx_ring_size,
256 &addr, GFP_KERNEL);
826aa4a0 257 if (!vaddr) {
59deab26
JP		 258 netif_err(priv, ifup, ndev,
259 "Could not allocate buffer descriptors!\n");
826aa4a0
AV		 260 return -ENOMEM;
261 }
262
fba4ed03
SG		 263 for (i = 0; i < priv->num_tx_queues; i++) {
264 tx_queue = priv->tx_queue[i];
43d620c8 265 tx_queue->tx_bd_base = vaddr;
fba4ed03
SG		 266 tx_queue->tx_bd_dma_base = addr;
267 tx_queue->dev = ndev;
268 /* enet DMA only understands physical addresses */
269 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
270 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
271 }
826aa4a0 272
826aa4a0 273 /* Start the rx descriptor ring where the tx ring leaves off */
fba4ed03
SG		 274 for (i = 0; i < priv->num_rx_queues; i++) {
275 rx_queue = priv->rx_queue[i];
43d620c8 276 rx_queue->rx_bd_base = vaddr;
fba4ed03
SG		 277 rx_queue->rx_bd_dma_base = addr;
278 rx_queue->dev = ndev;
279 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
280 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
281 }
826aa4a0
AV		 282
283 /* Setup the skbuff rings */
fba4ed03
SG		 284 for (i = 0; i < priv->num_tx_queues; i++) {
285 tx_queue = priv->tx_queue[i];
286 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
a12f801d 287 tx_queue->tx_ring_size, GFP_KERNEL);
fba4ed03 288 if (!tx_queue->tx_skbuff) {
59deab26
JP		 289 netif_err(priv, ifup, ndev,
290 "Could not allocate tx_skbuff\n");
fba4ed03
SG		 291 goto cleanup;
292 }
826aa4a0 293
fba4ed03
SG		 294 for (k = 0; k < tx_queue->tx_ring_size; k++)
295 tx_queue->tx_skbuff[k] = NULL;
296 }
826aa4a0 297
fba4ed03
SG		 298 for (i = 0; i < priv->num_rx_queues; i++) {
299 rx_queue = priv->rx_queue[i];
300 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
a12f801d 301 rx_queue->rx_ring_size, GFP_KERNEL);
826aa4a0 302
fba4ed03 303 if (!rx_queue->rx_skbuff) {
59deab26
JP		 304 netif_err(priv, ifup, ndev,
305 "Could not allocate rx_skbuff\n");
fba4ed03
SG		 306 goto cleanup;
307 }
308
309 for (j = 0; j < rx_queue->rx_ring_size; j++)
310 rx_queue->rx_skbuff[j] = NULL;
311 }
826aa4a0 312
8728327e
AV		 313 if (gfar_init_bds(ndev))
314 goto cleanup;
826aa4a0
AV		 315
316 return 0;
317
318cleanup:
319 free_skb_resources(priv);
320 return -ENOMEM;
321}
322
fba4ed03
SG		 323static void gfar_init_tx_rx_base(struct gfar_private *priv)
324{
46ceb60c 325 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 326 u32 __iomem *baddr;
fba4ed03
SG		 327 int i;
328
329 baddr = &regs->tbase0;
330 for(i = 0; i < priv->num_tx_queues; i++) {
331 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
332 baddr += 2;
333 }
334
335 baddr = &regs->rbase0;
336 for(i = 0; i < priv->num_rx_queues; i++) {
337 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
338 baddr += 2;
339 }
340}
341
826aa4a0
AV		 342static void gfar_init_mac(struct net_device *ndev)
343{
344 struct gfar_private *priv = netdev_priv(ndev);
46ceb60c 345 struct gfar __iomem *regs = priv->gfargrp[0].regs;
826aa4a0
AV		 346 u32 rctrl = 0;
347 u32 tctrl = 0;
348 u32 attrs = 0;
349
fba4ed03
SG		 350 /* write the tx/rx base registers */
351 gfar_init_tx_rx_base(priv);
32c513bc 352
826aa4a0 353 /* Configure the coalescing support */
46ceb60c 354 gfar_configure_coalescing(priv, 0xFF, 0xFF);
fba4ed03 355
1ccb8389 356 if (priv->rx_filer_enable) {
fba4ed03 357 rctrl |= RCTRL_FILREN;
1ccb8389
SG		 358 /* Program the RIR0 reg with the required distribution */
359 gfar_write(&regs->rir0, DEFAULT_RIR0);
360 }
826aa4a0 361
8b3afe95 362 if (ndev->features & NETIF_F_RXCSUM)
826aa4a0
AV		 363 rctrl |= RCTRL_CHECKSUMMING;
364
365 if (priv->extended_hash) {
366 rctrl |= RCTRL_EXTHASH;
367
368 gfar_clear_exact_match(ndev);
369 rctrl |= RCTRL_EMEN;
370 }
371
372 if (priv->padding) {
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
375 }
376
cc772ab7
MR		 377 /* Insert receive time stamps into padding alignment bytes */
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
379 rctrl &= ~RCTRL_PAL_MASK;
97553f7f 380 rctrl |= RCTRL_PADDING(8);
cc772ab7
MR		 381 priv->padding = 8;
382 }
383
97553f7f
MR		 384 /* Enable HW time stamping if requested from user space */
385 if (priv->hwts_rx_en)
386 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
387
87c288c6 388 if (ndev->features & NETIF_F_HW_VLAN_RX)
b852b720 389 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
826aa4a0
AV		 390
391 /* Init rctrl based on our settings */
392 gfar_write(&regs->rctrl, rctrl);
393
394 if (ndev->features & NETIF_F_IP_CSUM)
395 tctrl |= TCTRL_INIT_CSUM;
396
fba4ed03
SG		 397 tctrl |= TCTRL_TXSCHED_PRIO;
398
826aa4a0
AV		 399 gfar_write(&regs->tctrl, tctrl);
400
401 /* Set the extraction length and index */
402 attrs = ATTRELI_EL(priv->rx_stash_size) |
403 ATTRELI_EI(priv->rx_stash_index);
404
405 gfar_write(&regs->attreli, attrs);
406
407 /* Start with defaults, and add stashing or locking
408 * depending on the approprate variables */
409 attrs = ATTR_INIT_SETTINGS;
410
411 if (priv->bd_stash_en)
412 attrs |= ATTR_BDSTASH;
413
414 if (priv->rx_stash_size != 0)
415 attrs |= ATTR_BUFSTASH;
416
417 gfar_write(&regs->attr, attrs);
418
419 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
420 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
421 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
422}
423
a7f38041
SG		 424static struct net_device_stats *gfar_get_stats(struct net_device *dev)
425{
426 struct gfar_private *priv = netdev_priv(dev);
a7f38041
SG		 427 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
428 unsigned long tx_packets = 0, tx_bytes = 0;
429 int i = 0;
430
431 for (i = 0; i < priv->num_rx_queues; i++) {
432 rx_packets += priv->rx_queue[i]->stats.rx_packets;
433 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
434 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
435 }
436
437 dev->stats.rx_packets = rx_packets;
438 dev->stats.rx_bytes = rx_bytes;
439 dev->stats.rx_dropped = rx_dropped;
440
441 for (i = 0; i < priv->num_tx_queues; i++) {
1ac9ad13
ED		 442 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
443 tx_packets += priv->tx_queue[i]->stats.tx_packets;
a7f38041
SG		 444 }
445
446 dev->stats.tx_bytes = tx_bytes;
447 dev->stats.tx_packets = tx_packets;
448
449 return &dev->stats;
450}
451
26ccfc37
AF		 452static const struct net_device_ops gfar_netdev_ops = {
453 .ndo_open = gfar_enet_open,
454 .ndo_start_xmit = gfar_start_xmit,
455 .ndo_stop = gfar_close,
456 .ndo_change_mtu = gfar_change_mtu,
8b3afe95 457 .ndo_set_features = gfar_set_features,
afc4b13d 458 .ndo_set_rx_mode = gfar_set_multi,
26ccfc37
AF		 459 .ndo_tx_timeout = gfar_timeout,
460 .ndo_do_ioctl = gfar_ioctl,
a7f38041 461 .ndo_get_stats = gfar_get_stats,
240c102d
BH		 462 .ndo_set_mac_address = eth_mac_addr,
463 .ndo_validate_addr = eth_validate_addr,
26ccfc37
AF		 464#ifdef CONFIG_NET_POLL_CONTROLLER
465 .ndo_poll_controller = gfar_netpoll,
466#endif
467};
468
fba4ed03
SG		 469void lock_rx_qs(struct gfar_private *priv)
470{
471 int i = 0x0;
472
473 for (i = 0; i < priv->num_rx_queues; i++)
474 spin_lock(&priv->rx_queue[i]->rxlock);
475}
476
477void lock_tx_qs(struct gfar_private *priv)
478{
479 int i = 0x0;
480
481 for (i = 0; i < priv->num_tx_queues; i++)
482 spin_lock(&priv->tx_queue[i]->txlock);
483}
484
485void unlock_rx_qs(struct gfar_private *priv)
486{
487 int i = 0x0;
488
489 for (i = 0; i < priv->num_rx_queues; i++)
490 spin_unlock(&priv->rx_queue[i]->rxlock);
491}
492
493void unlock_tx_qs(struct gfar_private *priv)
494{
495 int i = 0x0;
496
497 for (i = 0; i < priv->num_tx_queues; i++)
498 spin_unlock(&priv->tx_queue[i]->txlock);
499}
500
87c288c6
JP		 501static bool gfar_is_vlan_on(struct gfar_private *priv)
502{
503 return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
504 (priv->ndev->features & NETIF_F_HW_VLAN_TX);
505}
506
7f7f5316
AF		 507/* Returns 1 if incoming frames use an FCB */
508static inline int gfar_uses_fcb(struct gfar_private *priv)
0bbaf069 509{
87c288c6
JP		 510 return gfar_is_vlan_on(priv) ||
511 (priv->ndev->features & NETIF_F_RXCSUM) ||
cc772ab7 512 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
0bbaf069 513}
bb40dcbb 514
fba4ed03
SG		 515static void free_tx_pointers(struct gfar_private *priv)
516{
517 int i = 0;
518
519 for (i = 0; i < priv->num_tx_queues; i++)
520 kfree(priv->tx_queue[i]);
521}
522
523static void free_rx_pointers(struct gfar_private *priv)
524{
525 int i = 0;
526
527 for (i = 0; i < priv->num_rx_queues; i++)
528 kfree(priv->rx_queue[i]);
529}
530
46ceb60c
SG		 531static void unmap_group_regs(struct gfar_private *priv)
532{
533 int i = 0;
534
535 for (i = 0; i < MAXGROUPS; i++)
536 if (priv->gfargrp[i].regs)
537 iounmap(priv->gfargrp[i].regs);
538}
539
540static void disable_napi(struct gfar_private *priv)
541{
542 int i = 0;
543
544 for (i = 0; i < priv->num_grps; i++)
545 napi_disable(&priv->gfargrp[i].napi);
546}
547
548static void enable_napi(struct gfar_private *priv)
549{
550 int i = 0;
551
552 for (i = 0; i < priv->num_grps; i++)
553 napi_enable(&priv->gfargrp[i].napi);
554}
555
556static int gfar_parse_group(struct device_node *np,
557 struct gfar_private *priv, const char *model)
558{
559 u32 *queue_mask;
46ceb60c 560
7ce97d4f 561 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
46ceb60c
SG		 562 if (!priv->gfargrp[priv->num_grps].regs)
563 return -ENOMEM;
564
565 priv->gfargrp[priv->num_grps].interruptTransmit =
566 irq_of_parse_and_map(np, 0);
567
568 /* If we aren't the FEC we have multiple interrupts */
569 if (model && strcasecmp(model, "FEC")) {
570 priv->gfargrp[priv->num_grps].interruptReceive =
571 irq_of_parse_and_map(np, 1);
572 priv->gfargrp[priv->num_grps].interruptError =
573 irq_of_parse_and_map(np,2);
28cb6ccd
NK		 574 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
575 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
576 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
46ceb60c 577 return -EINVAL;
46ceb60c
SG		 578 }
579
580 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
581 priv->gfargrp[priv->num_grps].priv = priv;
582 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
583 if(priv->mode == MQ_MG_MODE) {
584 queue_mask = (u32 *)of_get_property(np,
585 "fsl,rx-bit-map", NULL);
586 priv->gfargrp[priv->num_grps].rx_bit_map =
587 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
588 queue_mask = (u32 *)of_get_property(np,
589 "fsl,tx-bit-map", NULL);
590 priv->gfargrp[priv->num_grps].tx_bit_map =
591 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
592 } else {
593 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
594 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
595 }
596 priv->num_grps++;
597
598 return 0;
599}
600
2dc11581 601static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
b31a1d8b 602{
b31a1d8b
AF		 603 const char *model;
604 const char *ctype;
605 const void *mac_addr;
fba4ed03
SG		 606 int err = 0, i;
607 struct net_device *dev = NULL;
608 struct gfar_private *priv = NULL;
61c7a080 609 struct device_node *np = ofdev->dev.of_node;
46ceb60c 610 struct device_node *child = NULL;
4d7902f2
AF		 611 const u32 *stash;
612 const u32 *stash_len;
613 const u32 *stash_idx;
fba4ed03
SG		 614 unsigned int num_tx_qs, num_rx_qs;
615 u32 *tx_queues, *rx_queues;
b31a1d8b
AF		 616
617 if (!np || !of_device_is_available(np))
618 return -ENODEV;
619
fba4ed03
SG		 620 /* parse the num of tx and rx queues */
621 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
622 num_tx_qs = tx_queues ? *tx_queues : 1;
623
624 if (num_tx_qs > MAX_TX_QS) {
59deab26
JP		 625 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
626 num_tx_qs, MAX_TX_QS);
627 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 628 return -EINVAL;
629 }
630
631 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
632 num_rx_qs = rx_queues ? *rx_queues : 1;
633
634 if (num_rx_qs > MAX_RX_QS) {
59deab26
JP		 635 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
636 num_rx_qs, MAX_RX_QS);
637 pr_err("Cannot do alloc_etherdev, aborting\n");
fba4ed03
SG		 638 return -EINVAL;
639 }
640
641 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
642 dev = *pdev;
643 if (NULL == dev)
644 return -ENOMEM;
645
646 priv = netdev_priv(dev);
61c7a080 647 priv->node = ofdev->dev.of_node;
fba4ed03
SG		 648 priv->ndev = dev;
649
fba4ed03 650 priv->num_tx_queues = num_tx_qs;
fe069123 651 netif_set_real_num_rx_queues(dev, num_rx_qs);
fba4ed03 652 priv->num_rx_queues = num_rx_qs;
46ceb60c 653 priv->num_grps = 0x0;
b31a1d8b 654
4aa3a715
SP		 655 /* Init Rx queue filer rule set linked list*/
656 INIT_LIST_HEAD(&priv->rx_list.list);
657 priv->rx_list.count = 0;
658 mutex_init(&priv->rx_queue_access);
659
b31a1d8b
AF		 660 model = of_get_property(np, "model", NULL);
661
46ceb60c
SG		 662 for (i = 0; i < MAXGROUPS; i++)
663 priv->gfargrp[i].regs = NULL;
b31a1d8b 664
46ceb60c
SG		 665 /* Parse and initialize group specific information */
666 if (of_device_is_compatible(np, "fsl,etsec2")) {
667 priv->mode = MQ_MG_MODE;
668 for_each_child_of_node(np, child) {
669 err = gfar_parse_group(child, priv, model);
670 if (err)
671 goto err_grp_init;
b31a1d8b 672 }
46ceb60c
SG		 673 } else {
674 priv->mode = SQ_SG_MODE;
675 err = gfar_parse_group(np, priv, model);
676 if(err)
677 goto err_grp_init;
b31a1d8b
AF		 678 }
679
fba4ed03
SG		 680 for (i = 0; i < priv->num_tx_queues; i++)
681 priv->tx_queue[i] = NULL;
682 for (i = 0; i < priv->num_rx_queues; i++)
683 priv->rx_queue[i] = NULL;
684
685 for (i = 0; i < priv->num_tx_queues; i++) {
de47f072
JP		 686 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
687 GFP_KERNEL);
fba4ed03
SG		 688 if (!priv->tx_queue[i]) {
689 err = -ENOMEM;
690 goto tx_alloc_failed;
691 }
692 priv->tx_queue[i]->tx_skbuff = NULL;
693 priv->tx_queue[i]->qindex = i;
694 priv->tx_queue[i]->dev = dev;
695 spin_lock_init(&(priv->tx_queue[i]->txlock));
696 }
697
698 for (i = 0; i < priv->num_rx_queues; i++) {
de47f072
JP		 699 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
700 GFP_KERNEL);
fba4ed03
SG		 701 if (!priv->rx_queue[i]) {
702 err = -ENOMEM;
703 goto rx_alloc_failed;
704 }
705 priv->rx_queue[i]->rx_skbuff = NULL;
706 priv->rx_queue[i]->qindex = i;
707 priv->rx_queue[i]->dev = dev;
708 spin_lock_init(&(priv->rx_queue[i]->rxlock));
709 }
710
711
4d7902f2
AF		 712 stash = of_get_property(np, "bd-stash", NULL);
713
a12f801d 714 if (stash) {
4d7902f2
AF		 715 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
716 priv->bd_stash_en = 1;
717 }
718
719 stash_len = of_get_property(np, "rx-stash-len", NULL);
720
721 if (stash_len)
722 priv->rx_stash_size = *stash_len;
723
724 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
725
726 if (stash_idx)
727 priv->rx_stash_index = *stash_idx;
728
729 if (stash_len || stash_idx)
730 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
731
b31a1d8b
AF		 732 mac_addr = of_get_mac_address(np);
733 if (mac_addr)
6a3c910c 734 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
b31a1d8b
AF		 735
736 if (model && !strcasecmp(model, "TSEC"))
737 priv->device_flags =
738 FSL_GIANFAR_DEV_HAS_GIGABIT |
739 FSL_GIANFAR_DEV_HAS_COALESCE |
740 FSL_GIANFAR_DEV_HAS_RMON |
741 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
742 if (model && !strcasecmp(model, "eTSEC"))
743 priv->device_flags =
744 FSL_GIANFAR_DEV_HAS_GIGABIT |
745 FSL_GIANFAR_DEV_HAS_COALESCE |
746 FSL_GIANFAR_DEV_HAS_RMON |
747 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
2c2db48a 748 FSL_GIANFAR_DEV_HAS_PADDING |
b31a1d8b
AF		 749 FSL_GIANFAR_DEV_HAS_CSUM |
750 FSL_GIANFAR_DEV_HAS_VLAN |
751 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
97553f7f
MR		 752 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
753 FSL_GIANFAR_DEV_HAS_TIMER;
b31a1d8b
AF		 754
755 ctype = of_get_property(np, "phy-connection-type", NULL);
756
757 /* We only care about rgmii-id. The rest are autodetected */
758 if (ctype && !strcmp(ctype, "rgmii-id"))
759 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
760 else
761 priv->interface = PHY_INTERFACE_MODE_MII;
762
763 if (of_get_property(np, "fsl,magic-packet", NULL))
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
765
fe192a49 766 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
b31a1d8b
AF		 767
768 /* Find the TBI PHY. If it's not there, we don't support SGMII */
fe192a49 769 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
b31a1d8b
AF		 770
771 return 0;
772
fba4ed03
SG		 773rx_alloc_failed:
774 free_rx_pointers(priv);
775tx_alloc_failed:
776 free_tx_pointers(priv);
46ceb60c
SG		 777err_grp_init:
778 unmap_group_regs(priv);
fba4ed03 779 free_netdev(dev);
b31a1d8b
AF		 780 return err;
781}
782
cc772ab7
MR		 783static int gfar_hwtstamp_ioctl(struct net_device *netdev,
784 struct ifreq *ifr, int cmd)
785{
786 struct hwtstamp_config config;
787 struct gfar_private *priv = netdev_priv(netdev);
788
789 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
790 return -EFAULT;
791
792 /* reserved for future extensions */
793 if (config.flags)
794 return -EINVAL;
795
f0ee7acf
MR		 796 switch (config.tx_type) {
797 case HWTSTAMP_TX_OFF:
798 priv->hwts_tx_en = 0;
799 break;
800 case HWTSTAMP_TX_ON:
801 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
802 return -ERANGE;
803 priv->hwts_tx_en = 1;
804 break;
805 default:
cc772ab7 806 return -ERANGE;
f0ee7acf 807 }
cc772ab7
MR		 808
809 switch (config.rx_filter) {
810 case HWTSTAMP_FILTER_NONE:
97553f7f
MR		 811 if (priv->hwts_rx_en) {
812 stop_gfar(netdev);
813 priv->hwts_rx_en = 0;
814 startup_gfar(netdev);
815 }
cc772ab7
MR		 816 break;
817 default:
818 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
819 return -ERANGE;
97553f7f
MR		 820 if (!priv->hwts_rx_en) {
821 stop_gfar(netdev);
822 priv->hwts_rx_en = 1;
823 startup_gfar(netdev);
824 }
cc772ab7
MR		 825 config.rx_filter = HWTSTAMP_FILTER_ALL;
826 break;
827 }
828
829 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
830 -EFAULT : 0;
831}
832
0faac9f7
CW		 833/* Ioctl MII Interface */
834static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
835{
836 struct gfar_private *priv = netdev_priv(dev);
837
838 if (!netif_running(dev))
839 return -EINVAL;
840
cc772ab7
MR		 841 if (cmd == SIOCSHWTSTAMP)
842 return gfar_hwtstamp_ioctl(dev, rq, cmd);
843
0faac9f7
CW		 844 if (!priv->phydev)
845 return -ENODEV;
846
28b04113 847 return phy_mii_ioctl(priv->phydev, rq, cmd);
0faac9f7
CW		 848}
849
fba4ed03
SG		 850static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
851{
852 unsigned int new_bit_map = 0x0;
853 int mask = 0x1 << (max_qs - 1), i;
854 for (i = 0; i < max_qs; i++) {
855 if (bit_map & mask)
856 new_bit_map = new_bit_map + (1 << i);
857 mask = mask >> 0x1;
858 }
859 return new_bit_map;
860}
7a8b3372 861
18294ad1
AV		 862static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
863 u32 class)
7a8b3372
SG		 864{
865 u32 rqfpr = FPR_FILER_MASK;
866 u32 rqfcr = 0x0;
867
868 rqfar--;
869 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
6c43e046
WJB		 870 priv->ftp_rqfpr[rqfar] = rqfpr;
871 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
873
874 rqfar--;
875 rqfcr = RQFCR_CMP_NOMATCH;
6c43e046
WJB		 876 priv->ftp_rqfpr[rqfar] = rqfpr;
877 priv->ftp_rqfcr[rqfar] = rqfcr;
7a8b3372
SG		 878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
879
880 rqfar--;
881 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
882 rqfpr = class;
6c43e046
WJB		 883 priv->ftp_rqfcr[rqfar] = rqfcr;
884 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887 rqfar--;
888 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
889 rqfpr = class;
6c43e046
WJB		 890 priv->ftp_rqfcr[rqfar] = rqfcr;
891 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
893
894 return rqfar;
895}
896
897static void gfar_init_filer_table(struct gfar_private *priv)
898{
899 int i = 0x0;
900 u32 rqfar = MAX_FILER_IDX;
901 u32 rqfcr = 0x0;
902 u32 rqfpr = FPR_FILER_MASK;
903
904 /* Default rule */
905 rqfcr = RQFCR_CMP_MATCH;
6c43e046
WJB		 906 priv->ftp_rqfcr[rqfar] = rqfcr;
907 priv->ftp_rqfpr[rqfar] = rqfpr;
7a8b3372
SG		 908 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
909
910 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
911 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
916
85dd08eb 917 /* cur_filer_idx indicated the first non-masked rule */
7a8b3372
SG		 918 priv->cur_filer_idx = rqfar;
919
920 /* Rest are masked rules */
921 rqfcr = RQFCR_CMP_NOMATCH;
922 for (i = 0; i < rqfar; i++) {
6c43e046
WJB		 923 priv->ftp_rqfcr[i] = rqfcr;
924 priv->ftp_rqfpr[i] = rqfpr;
7a8b3372
SG		 925 gfar_write_filer(priv, i, rqfcr, rqfpr);
926 }
927}
928
7d350977
AV		 929static void gfar_detect_errata(struct gfar_private *priv)
930{
931 struct device *dev = &priv->ofdev->dev;
932 unsigned int pvr = mfspr(SPRN_PVR);
933 unsigned int svr = mfspr(SPRN_SVR);
934 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
935 unsigned int rev = svr & 0xffff;
936
937 /* MPC8313 Rev 2.0 and higher; All MPC837x */
938 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
939 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
940 priv->errata |= GFAR_ERRATA_74;
941
deb90eac
AV		 942 /* MPC8313 and MPC837x all rev */
943 if ((pvr == 0x80850010 && mod == 0x80b0) ||
944 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
945 priv->errata |= GFAR_ERRATA_76;
946
511d934f
AV		 947 /* MPC8313 and MPC837x all rev */
948 if ((pvr == 0x80850010 && mod == 0x80b0) ||
949 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
950 priv->errata |= GFAR_ERRATA_A002;
951
4363c2fd
AD		 952 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
953 if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
954 (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
955 priv->errata |= GFAR_ERRATA_12;
956
7d350977
AV		 957 if (priv->errata)
958 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
959 priv->errata);
960}
961
bb40dcbb
AF		 962/* Set up the ethernet device structure, private data,
963 * and anything else we need before we start */
74888760 964static int gfar_probe(struct platform_device *ofdev)
1da177e4
LT		 965{
966 u32 tempval;
967 struct net_device *dev = NULL;
968 struct gfar_private *priv = NULL;
f4983704 969 struct gfar __iomem *regs = NULL;
46ceb60c 970 int err = 0, i, grp_idx = 0;
fba4ed03 971 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
46ceb60c 972 u32 isrg = 0;
18294ad1 973 u32 __iomem *baddr;
1da177e4 974
fba4ed03 975 err = gfar_of_init(ofdev, &dev);
1da177e4 976
fba4ed03
SG		 977 if (err)
978 return err;
1da177e4
LT		 979
980 priv = netdev_priv(dev);
4826857f
KG		 981 priv->ndev = dev;
982 priv->ofdev = ofdev;
61c7a080 983 priv->node = ofdev->dev.of_node;
4826857f 984 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4 985
d87eb127 986 spin_lock_init(&priv->bflock);
ab939905 987 INIT_WORK(&priv->reset_task, gfar_reset_task);
1da177e4 988
b31a1d8b 989 dev_set_drvdata(&ofdev->dev, priv);
46ceb60c 990 regs = priv->gfargrp[0].regs;
1da177e4 991
7d350977
AV		 992 gfar_detect_errata(priv);
993
1da177e4
LT		 994 /* Stop the DMA engine now, in case it was running before */
995 /* (The firmware could have used it, and left it running). */
257d938a 996 gfar_halt(dev);
1da177e4
LT		 997
998 /* Reset MAC layer */
f4983704 999 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1da177e4 1000
b98ac702
AF		 1001 /* We need to delay at least 3 TX clocks */
1002 udelay(2);
1003
1da177e4 1004 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
f4983704 1005 gfar_write(&regs->maccfg1, tempval);
1da177e4
LT		 1006
1007 /* Initialize MACCFG2. */
7d350977
AV		 1008 tempval = MACCFG2_INIT_SETTINGS;
1009 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1010 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1011 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 1012
1013 /* Initialize ECNTRL */
f4983704 1014 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1da177e4 1015
1da177e4 1016 /* Set the dev->base_addr to the gfar reg region */
f4983704 1017 dev->base_addr = (unsigned long) regs;
1da177e4 1018
b31a1d8b 1019 SET_NETDEV_DEV(dev, &ofdev->dev);
1da177e4
LT		 1020
1021 /* Fill in the dev structure */
1da177e4 1022 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 1023 dev->mtu = 1500;
26ccfc37 1024 dev->netdev_ops = &gfar_netdev_ops;
0bbaf069
KG		 1025 dev->ethtool_ops = &gfar_ethtool_ops;
1026
fba4ed03 1027 /* Register for napi ...We are registering NAPI for each grp */
46ceb60c
SG		 1028 for (i = 0; i < priv->num_grps; i++)
1029 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
a12f801d 1030
b31a1d8b 1031 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
8b3afe95
MM		 1032 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1033 NETIF_F_RXCSUM;
1034 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1035 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1036 }
0bbaf069 1037
87c288c6
JP		 1038 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1039 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
0bbaf069 1040 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
87c288c6 1041 }
0bbaf069 1042
b31a1d8b 1043 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
0bbaf069
KG		 1044 priv->extended_hash = 1;
1045 priv->hash_width = 9;
1046
f4983704
SG		 1047 priv->hash_regs[0] = &regs->igaddr0;
1048 priv->hash_regs[1] = &regs->igaddr1;
1049 priv->hash_regs[2] = &regs->igaddr2;
1050 priv->hash_regs[3] = &regs->igaddr3;
1051 priv->hash_regs[4] = &regs->igaddr4;
1052 priv->hash_regs[5] = &regs->igaddr5;
1053 priv->hash_regs[6] = &regs->igaddr6;
1054 priv->hash_regs[7] = &regs->igaddr7;
1055 priv->hash_regs[8] = &regs->gaddr0;
1056 priv->hash_regs[9] = &regs->gaddr1;
1057 priv->hash_regs[10] = &regs->gaddr2;
1058 priv->hash_regs[11] = &regs->gaddr3;
1059 priv->hash_regs[12] = &regs->gaddr4;
1060 priv->hash_regs[13] = &regs->gaddr5;
1061 priv->hash_regs[14] = &regs->gaddr6;
1062 priv->hash_regs[15] = &regs->gaddr7;
0bbaf069
KG		 1063
1064 } else {
1065 priv->extended_hash = 0;
1066 priv->hash_width = 8;
1067
f4983704
SG		 1068 priv->hash_regs[0] = &regs->gaddr0;
1069 priv->hash_regs[1] = &regs->gaddr1;
1070 priv->hash_regs[2] = &regs->gaddr2;
1071 priv->hash_regs[3] = &regs->gaddr3;
1072 priv->hash_regs[4] = &regs->gaddr4;
1073 priv->hash_regs[5] = &regs->gaddr5;
1074 priv->hash_regs[6] = &regs->gaddr6;
1075 priv->hash_regs[7] = &regs->gaddr7;
0bbaf069
KG		 1076 }
1077
b31a1d8b 1078 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
0bbaf069
KG		 1079 priv->padding = DEFAULT_PADDING;
1080 else
1081 priv->padding = 0;
1082
cc772ab7
MR		 1083 if (dev->features & NETIF_F_IP_CSUM ||
1084 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
bee9e58c 1085 dev->needed_headroom = GMAC_FCB_LEN;
1da177e4 1086
46ceb60c
SG		 1087 /* Program the isrg regs only if number of grps > 1 */
1088 if (priv->num_grps > 1) {
1089 baddr = &regs->isrg0;
1090 for (i = 0; i < priv->num_grps; i++) {
1091 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1092 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1093 gfar_write(baddr, isrg);
1094 baddr++;
1095 isrg = 0x0;
1096 }
1097 }
1098
fba4ed03 1099 /* Need to reverse the bit maps as bit_map's MSB is q0
984b3f57 1100 * but, for_each_set_bit parses from right to left, which
fba4ed03 1101 * basically reverses the queue numbers */
46ceb60c
SG		 1102 for (i = 0; i< priv->num_grps; i++) {
1103 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1104 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1105 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1106 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1107 }
1108
1109 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1110 * also assign queues to groups */
1111 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1112 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
984b3f57 1113 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
46ceb60c
SG		 1114 priv->num_rx_queues) {
1115 priv->gfargrp[grp_idx].num_rx_queues++;
1116 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1117 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1118 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1119 }
1120 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
984b3f57 1121 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
46ceb60c
SG		 1122 priv->num_tx_queues) {
1123 priv->gfargrp[grp_idx].num_tx_queues++;
1124 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1125 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1126 tqueue = tqueue | (TQUEUE_EN0 >> i);
1127 }
1128 priv->gfargrp[grp_idx].rstat = rstat;
1129 priv->gfargrp[grp_idx].tstat = tstat;
1130 rstat = tstat =0;
fba4ed03 1131 }
fba4ed03
SG		 1132
1133 gfar_write(&regs->rqueue, rqueue);
1134 gfar_write(&regs->tqueue, tqueue);
1135
1da177e4 1136 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1da177e4 1137
a12f801d 1138 /* Initializing some of the rx/tx queue level parameters */
fba4ed03
SG		 1139 for (i = 0; i < priv->num_tx_queues; i++) {
1140 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1141 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1142 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1143 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1144 }
a12f801d 1145
fba4ed03
SG		 1146 for (i = 0; i < priv->num_rx_queues; i++) {
1147 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1148 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1149 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1150 }
1da177e4 1151
4aa3a715
SP		 1152 /* always enable rx filer*/
1153 priv->rx_filer_enable = 1;
0bbaf069
KG		 1154 /* Enable most messages by default */
1155 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1156
d3eab82b
TP		 1157 /* Carrier starts down, phylib will bring it up */
1158 netif_carrier_off(dev);
1159
1da177e4
LT		 1160 err = register_netdev(dev);
1161
1162 if (err) {
59deab26 1163 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1da177e4
LT		 1164 goto register_fail;
1165 }
1166
2884e5cc
AV		 1167 device_init_wakeup(&dev->dev,
1168 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1169
c50a5d9a 1170 /* fill out IRQ number and name fields */
46ceb60c 1171 for (i = 0; i < priv->num_grps; i++) {
46ceb60c 1172 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0015e551
JP		 1173 sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1174 dev->name, "_g", '0' + i, "_tx");
1175 sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1176 dev->name, "_g", '0' + i, "_rx");
1177 sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1178 dev->name, "_g", '0' + i, "_er");
46ceb60c 1179 } else
0015e551 1180 strcpy(priv->gfargrp[i].int_name_tx, dev->name);
46ceb60c 1181 }
c50a5d9a 1182
7a8b3372
SG		 1183 /* Initialize the filer table */
1184 gfar_init_filer_table(priv);
1185
7f7f5316
AF		 1186 /* Create all the sysfs files */
1187 gfar_init_sysfs(dev);
1188
1da177e4 1189 /* Print out the device info */
59deab26 1190 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1da177e4
LT		 1191
1192 /* Even more device info helps when determining which kernel */
7f7f5316 1193 /* provided which set of benchmarks. */
59deab26 1194 netdev_info(dev, "Running with NAPI enabled\n");
fba4ed03 1195 for (i = 0; i < priv->num_rx_queues; i++)
59deab26
JP		 1196 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1197 i, priv->rx_queue[i]->rx_ring_size);
fba4ed03 1198 for(i = 0; i < priv->num_tx_queues; i++)
59deab26
JP		 1199 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1200 i, priv->tx_queue[i]->tx_ring_size);
1da177e4
LT		 1201
1202 return 0;
1203
1204register_fail:
46ceb60c 1205 unmap_group_regs(priv);
fba4ed03
SG		 1206 free_tx_pointers(priv);
1207 free_rx_pointers(priv);
fe192a49
GL		 1208 if (priv->phy_node)
1209 of_node_put(priv->phy_node);
1210 if (priv->tbi_node)
1211 of_node_put(priv->tbi_node);
1da177e4 1212 free_netdev(dev);
bb40dcbb 1213 return err;
1da177e4
LT		 1214}
1215
2dc11581 1216static int gfar_remove(struct platform_device *ofdev)
1da177e4 1217{
b31a1d8b 1218 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1da177e4 1219
fe192a49
GL		 1220 if (priv->phy_node)
1221 of_node_put(priv->phy_node);
1222 if (priv->tbi_node)
1223 of_node_put(priv->tbi_node);
1224
b31a1d8b 1225 dev_set_drvdata(&ofdev->dev, NULL);
1da177e4 1226
d9d8e041 1227 unregister_netdev(priv->ndev);
46ceb60c 1228 unmap_group_regs(priv);
4826857f 1229 free_netdev(priv->ndev);
1da177e4
LT		 1230
1231 return 0;
1232}
1233
d87eb127 1234#ifdef CONFIG_PM
be926fc4
AV		 1235
1236static int gfar_suspend(struct device *dev)
d87eb127 1237{
be926fc4
AV		 1238 struct gfar_private *priv = dev_get_drvdata(dev);
1239 struct net_device *ndev = priv->ndev;
46ceb60c 1240 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1241 unsigned long flags;
1242 u32 tempval;
1243
1244 int magic_packet = priv->wol_en &&
b31a1d8b 1245 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1246
be926fc4 1247 netif_device_detach(ndev);
d87eb127 1248
be926fc4 1249 if (netif_running(ndev)) {
fba4ed03
SG		 1250
1251 local_irq_save(flags);
1252 lock_tx_qs(priv);
1253 lock_rx_qs(priv);
d87eb127 1254
be926fc4 1255 gfar_halt_nodisable(ndev);
d87eb127
SW		 1256
1257 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
f4983704 1258 tempval = gfar_read(&regs->maccfg1);
d87eb127
SW		 1259
1260 tempval &= ~MACCFG1_TX_EN;
1261
1262 if (!magic_packet)
1263 tempval &= ~MACCFG1_RX_EN;
1264
f4983704 1265 gfar_write(&regs->maccfg1, tempval);
d87eb127 1266
fba4ed03
SG		 1267 unlock_rx_qs(priv);
1268 unlock_tx_qs(priv);
1269 local_irq_restore(flags);
d87eb127 1270
46ceb60c 1271 disable_napi(priv);
d87eb127
SW		 1272
1273 if (magic_packet) {
1274 /* Enable interrupt on Magic Packet */
f4983704 1275 gfar_write(&regs->imask, IMASK_MAG);
d87eb127
SW		 1276
1277 /* Enable Magic Packet mode */
f4983704 1278 tempval = gfar_read(&regs->maccfg2);
d87eb127 1279 tempval |= MACCFG2_MPEN;
f4983704 1280 gfar_write(&regs->maccfg2, tempval);
d87eb127
SW		 1281 } else {
1282 phy_stop(priv->phydev);
1283 }
1284 }
1285
1286 return 0;
1287}
1288
be926fc4 1289static int gfar_resume(struct device *dev)
d87eb127 1290{
be926fc4
AV		 1291 struct gfar_private *priv = dev_get_drvdata(dev);
1292 struct net_device *ndev = priv->ndev;
46ceb60c 1293 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127
SW		 1294 unsigned long flags;
1295 u32 tempval;
1296 int magic_packet = priv->wol_en &&
b31a1d8b 1297 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
d87eb127 1298
be926fc4
AV		 1299 if (!netif_running(ndev)) {
1300 netif_device_attach(ndev);
d87eb127
SW		 1301 return 0;
1302 }
1303
1304 if (!magic_packet && priv->phydev)
1305 phy_start(priv->phydev);
1306
1307 /* Disable Magic Packet mode, in case something
1308 * else woke us up.
1309 */
fba4ed03
SG		 1310 local_irq_save(flags);
1311 lock_tx_qs(priv);
1312 lock_rx_qs(priv);
d87eb127 1313
f4983704 1314 tempval = gfar_read(&regs->maccfg2);
d87eb127 1315 tempval &= ~MACCFG2_MPEN;
f4983704 1316 gfar_write(&regs->maccfg2, tempval);
d87eb127 1317
be926fc4 1318 gfar_start(ndev);
d87eb127 1319
fba4ed03
SG		 1320 unlock_rx_qs(priv);
1321 unlock_tx_qs(priv);
1322 local_irq_restore(flags);
d87eb127 1323
be926fc4
AV		 1324 netif_device_attach(ndev);
1325
46ceb60c 1326 enable_napi(priv);
be926fc4
AV		 1327
1328 return 0;
1329}
1330
1331static int gfar_restore(struct device *dev)
1332{
1333 struct gfar_private *priv = dev_get_drvdata(dev);
1334 struct net_device *ndev = priv->ndev;
1335
1336 if (!netif_running(ndev))
1337 return 0;
1338
1339 gfar_init_bds(ndev);
1340 init_registers(ndev);
1341 gfar_set_mac_address(ndev);
1342 gfar_init_mac(ndev);
1343 gfar_start(ndev);
1344
1345 priv->oldlink = 0;
1346 priv->oldspeed = 0;
1347 priv->oldduplex = -1;
1348
1349 if (priv->phydev)
1350 phy_start(priv->phydev);
d87eb127 1351
be926fc4 1352 netif_device_attach(ndev);
5ea681d4 1353 enable_napi(priv);
d87eb127
SW		 1354
1355 return 0;
1356}
be926fc4
AV		 1357
1358static struct dev_pm_ops gfar_pm_ops = {
1359 .suspend = gfar_suspend,
1360 .resume = gfar_resume,
1361 .freeze = gfar_suspend,
1362 .thaw = gfar_resume,
1363 .restore = gfar_restore,
1364};
1365
1366#define GFAR_PM_OPS (&gfar_pm_ops)
1367
d87eb127 1368#else
be926fc4
AV		 1369
1370#define GFAR_PM_OPS NULL
be926fc4 1371
d87eb127 1372#endif
1da177e4 1373
e8a2b6a4
AF		 1374/* Reads the controller's registers to determine what interface
1375 * connects it to the PHY.
1376 */
1377static phy_interface_t gfar_get_interface(struct net_device *dev)
1378{
1379 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1380 struct gfar __iomem *regs = priv->gfargrp[0].regs;
f4983704
SG		 1381 u32 ecntrl;
1382
f4983704 1383 ecntrl = gfar_read(&regs->ecntrl);
e8a2b6a4
AF		 1384
1385 if (ecntrl & ECNTRL_SGMII_MODE)
1386 return PHY_INTERFACE_MODE_SGMII;
1387
1388 if (ecntrl & ECNTRL_TBI_MODE) {
1389 if (ecntrl & ECNTRL_REDUCED_MODE)
1390 return PHY_INTERFACE_MODE_RTBI;
1391 else
1392 return PHY_INTERFACE_MODE_TBI;
1393 }
1394
1395 if (ecntrl & ECNTRL_REDUCED_MODE) {
1396 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1397 return PHY_INTERFACE_MODE_RMII;
7132ab7f 1398 else {
b31a1d8b 1399 phy_interface_t interface = priv->interface;
7132ab7f
AF		 1400
1401 /*
1402 * This isn't autodetected right now, so it must
1403 * be set by the device tree or platform code.
1404 */
1405 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1406 return PHY_INTERFACE_MODE_RGMII_ID;
1407
e8a2b6a4 1408 return PHY_INTERFACE_MODE_RGMII;
7132ab7f 1409 }
e8a2b6a4
AF		 1410 }
1411
b31a1d8b 1412 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
e8a2b6a4
AF		 1413 return PHY_INTERFACE_MODE_GMII;
1414
1415 return PHY_INTERFACE_MODE_MII;
1416}
1417
1418
bb40dcbb
AF		 1419/* Initializes driver's PHY state, and attaches to the PHY.
1420 * Returns 0 on success.
1da177e4
LT		 1421 */
1422static int init_phy(struct net_device *dev)
1423{
1424 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 1425 uint gigabit_support =
b31a1d8b 1426 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
bb40dcbb 1427 SUPPORTED_1000baseT_Full : 0;
e8a2b6a4 1428 phy_interface_t interface;
1da177e4
LT		 1429
1430 priv->oldlink = 0;
1431 priv->oldspeed = 0;
1432 priv->oldduplex = -1;
1433
e8a2b6a4
AF		 1434 interface = gfar_get_interface(dev);
1435
1db780f8
AV		 1436 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1437 interface);
1438 if (!priv->phydev)
1439 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1440 interface);
1441 if (!priv->phydev) {
1442 dev_err(&dev->dev, "could not attach to PHY\n");
1443 return -ENODEV;
fe192a49 1444 }
1da177e4 1445
d3c12873
KJ		 1446 if (interface == PHY_INTERFACE_MODE_SGMII)
1447 gfar_configure_serdes(dev);
1448
bb40dcbb 1449 /* Remove any features not supported by the controller */
fe192a49
GL		 1450 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1451 priv->phydev->advertising = priv->phydev->supported;
1da177e4
LT		 1452
1453 return 0;
1da177e4
LT		 1454}
1455
d0313587
PG		 1456/*
1457 * Initialize TBI PHY interface for communicating with the
1458 * SERDES lynx PHY on the chip. We communicate with this PHY
1459 * through the MDIO bus on each controller, treating it as a
1460 * "normal" PHY at the address found in the TBIPA register. We assume
1461 * that the TBIPA register is valid. Either the MDIO bus code will set
1462 * it to a value that doesn't conflict with other PHYs on the bus, or the
1463 * value doesn't matter, as there are no other PHYs on the bus.
1464 */
d3c12873
KJ		 1465static void gfar_configure_serdes(struct net_device *dev)
1466{
1467 struct gfar_private *priv = netdev_priv(dev);
fe192a49
GL		 1468 struct phy_device *tbiphy;
1469
1470 if (!priv->tbi_node) {
1471 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1472 "device tree specify a tbi-handle\n");
1473 return;
1474 }
c132419e 1475
fe192a49
GL		 1476 tbiphy = of_phy_find_device(priv->tbi_node);
1477 if (!tbiphy) {
1478 dev_err(&dev->dev, "error: Could not get TBI device\n");
b31a1d8b
AF		 1479 return;
1480 }
d3c12873 1481
b31a1d8b
AF		 1482 /*
1483 * If the link is already up, we must already be ok, and don't need to
bdb59f94
TP		 1484 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1485 * everything for us? Resetting it takes the link down and requires
1486 * several seconds for it to come back.
1487 */
fe192a49 1488 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
b31a1d8b 1489 return;
d3c12873 1490
d0313587 1491 /* Single clk mode, mii mode off(for serdes communication) */
fe192a49 1492 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
d3c12873 1493
fe192a49 1494 phy_write(tbiphy, MII_ADVERTISE,
d3c12873
KJ		 1495 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1496 ADVERTISE_1000XPSE_ASYM);
1497
fe192a49 1498 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
d3c12873
KJ		 1499 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1500}
1501
1da177e4
LT		 1502static void init_registers(struct net_device *dev)
1503{
1504 struct gfar_private *priv = netdev_priv(dev);
f4983704 1505 struct gfar __iomem *regs = NULL;
46ceb60c 1506 int i = 0;
1da177e4 1507
46ceb60c
SG		 1508 for (i = 0; i < priv->num_grps; i++) {
1509 regs = priv->gfargrp[i].regs;
1510 /* Clear IEVENT */
1511 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1da177e4 1512
46ceb60c
SG		 1513 /* Initialize IMASK */
1514 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1515 }
1da177e4 1516
46ceb60c 1517 regs = priv->gfargrp[0].regs;
1da177e4 1518 /* Init hash registers to zero */
f4983704
SG		 1519 gfar_write(&regs->igaddr0, 0);
1520 gfar_write(&regs->igaddr1, 0);
1521 gfar_write(&regs->igaddr2, 0);
1522 gfar_write(&regs->igaddr3, 0);
1523 gfar_write(&regs->igaddr4, 0);
1524 gfar_write(&regs->igaddr5, 0);
1525 gfar_write(&regs->igaddr6, 0);
1526 gfar_write(&regs->igaddr7, 0);
1527
1528 gfar_write(&regs->gaddr0, 0);
1529 gfar_write(&regs->gaddr1, 0);
1530 gfar_write(&regs->gaddr2, 0);
1531 gfar_write(&regs->gaddr3, 0);
1532 gfar_write(&regs->gaddr4, 0);
1533 gfar_write(&regs->gaddr5, 0);
1534 gfar_write(&regs->gaddr6, 0);
1535 gfar_write(&regs->gaddr7, 0);
1da177e4 1536
1da177e4 1537 /* Zero out the rmon mib registers if it has them */
b31a1d8b 1538 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 1539 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1da177e4
LT		 1540
1541 /* Mask off the CAM interrupts */
f4983704
SG		 1542 gfar_write(&regs->rmon.cam1, 0xffffffff);
1543 gfar_write(&regs->rmon.cam2, 0xffffffff);
1da177e4
LT		 1544 }
1545
1546 /* Initialize the max receive buffer length */
f4983704 1547 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1da177e4 1548
1da177e4 1549 /* Initialize the Minimum Frame Length Register */
f4983704 1550 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1da177e4
LT		 1551}
1552
511d934f
AV		 1553static int __gfar_is_rx_idle(struct gfar_private *priv)
1554{
1555 u32 res;
1556
1557 /*
1558 * Normaly TSEC should not hang on GRS commands, so we should
1559 * actually wait for IEVENT_GRSC flag.
1560 */
1561 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1562 return 0;
1563
1564 /*
1565 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1566 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1567 * and the Rx can be safely reset.
1568 */
1569 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1570 res &= 0x7f807f80;
1571 if ((res & 0xffff) == (res >> 16))
1572 return 1;
1573
1574 return 0;
1575}
0bbaf069
KG		 1576
1577/* Halt the receive and transmit queues */
d87eb127 1578static void gfar_halt_nodisable(struct net_device *dev)
1da177e4
LT		 1579{
1580 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1581 struct gfar __iomem *regs = NULL;
1da177e4 1582 u32 tempval;
46ceb60c 1583 int i = 0;
1da177e4 1584
46ceb60c
SG		 1585 for (i = 0; i < priv->num_grps; i++) {
1586 regs = priv->gfargrp[i].regs;
1587 /* Mask all interrupts */
1588 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1da177e4 1589
46ceb60c
SG		 1590 /* Clear all interrupts */
1591 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1592 }
1da177e4 1593
46ceb60c 1594 regs = priv->gfargrp[0].regs;
1da177e4 1595 /* Stop the DMA, and wait for it to stop */
f4983704 1596 tempval = gfar_read(&regs->dmactrl);
1da177e4
LT		 1597 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1598 != (DMACTRL_GRS | DMACTRL_GTS)) {
511d934f
AV		 1599 int ret;
1600
1da177e4 1601 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
f4983704 1602 gfar_write(&regs->dmactrl, tempval);
1da177e4 1603
511d934f
AV		 1604 do {
1605 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1606 (IEVENT_GRSC | IEVENT_GTSC)) ==
1607 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1608 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1609 ret = __gfar_is_rx_idle(priv);
1610 } while (!ret);
1da177e4 1611 }
d87eb127 1612}
d87eb127
SW		 1613
1614/* Halt the receive and transmit queues */
1615void gfar_halt(struct net_device *dev)
1616{
1617 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1618 struct gfar __iomem *regs = priv->gfargrp[0].regs;
d87eb127 1619 u32 tempval;
1da177e4 1620
2a54adc3
SW		 1621 gfar_halt_nodisable(dev);
1622
1da177e4
LT		 1623 /* Disable Rx and Tx */
1624 tempval = gfar_read(&regs->maccfg1);
1625 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1626 gfar_write(&regs->maccfg1, tempval);
0bbaf069
KG		 1627}
1628
46ceb60c
SG		 1629static void free_grp_irqs(struct gfar_priv_grp *grp)
1630{
1631 free_irq(grp->interruptError, grp);
1632 free_irq(grp->interruptTransmit, grp);
1633 free_irq(grp->interruptReceive, grp);
1634}
1635
0bbaf069
KG		 1636void stop_gfar(struct net_device *dev)
1637{
1638 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 1639 unsigned long flags;
46ceb60c 1640 int i;
0bbaf069 1641
bb40dcbb
AF		 1642 phy_stop(priv->phydev);
1643
a12f801d 1644
0bbaf069 1645 /* Lock it down */
fba4ed03
SG		 1646 local_irq_save(flags);
1647 lock_tx_qs(priv);
1648 lock_rx_qs(priv);
0bbaf069 1649
0bbaf069 1650 gfar_halt(dev);
1da177e4 1651
fba4ed03
SG		 1652 unlock_rx_qs(priv);
1653 unlock_tx_qs(priv);
1654 local_irq_restore(flags);
1da177e4
LT		 1655
1656 /* Free the IRQs */
b31a1d8b 1657 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 1658 for (i = 0; i < priv->num_grps; i++)
1659 free_grp_irqs(&priv->gfargrp[i]);
1da177e4 1660 } else {
46ceb60c
SG		 1661 for (i = 0; i < priv->num_grps; i++)
1662 free_irq(priv->gfargrp[i].interruptTransmit,
1663 &priv->gfargrp[i]);
1da177e4
LT		 1664 }
1665
1666 free_skb_resources(priv);
1da177e4
LT		 1667}
1668
fba4ed03 1669static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1da177e4 1670{
1da177e4 1671 struct txbd8 *txbdp;
fba4ed03 1672 struct gfar_private *priv = netdev_priv(tx_queue->dev);
4669bc90 1673 int i, j;
1da177e4 1674
a12f801d 1675 txbdp = tx_queue->tx_bd_base;
1da177e4 1676
a12f801d
SG		 1677 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1678 if (!tx_queue->tx_skbuff[i])
4669bc90 1679 continue;
1da177e4 1680
4826857f 1681 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90
DH		 1682 txbdp->length, DMA_TO_DEVICE);
1683 txbdp->lstatus = 0;
fba4ed03
SG		 1684 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1685 j++) {
4669bc90 1686 txbdp++;
4826857f 1687 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
4669bc90 1688 txbdp->length, DMA_TO_DEVICE);
1da177e4 1689 }
ad5da7ab 1690 txbdp++;
a12f801d
SG		 1691 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1692 tx_queue->tx_skbuff[i] = NULL;
1da177e4 1693 }
a12f801d 1694 kfree(tx_queue->tx_skbuff);
fba4ed03 1695}
1da177e4 1696
fba4ed03
SG		 1697static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1698{
1699 struct rxbd8 *rxbdp;
1700 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1701 int i;
1da177e4 1702
fba4ed03 1703 rxbdp = rx_queue->rx_bd_base;
1da177e4 1704
a12f801d
SG		 1705 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1706 if (rx_queue->rx_skbuff[i]) {
fba4ed03
SG		 1707 dma_unmap_single(&priv->ofdev->dev,
1708 rxbdp->bufPtr, priv->rx_buffer_size,
e69edd21 1709 DMA_FROM_DEVICE);
a12f801d
SG		 1710 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1711 rx_queue->rx_skbuff[i] = NULL;
1da177e4 1712 }
e69edd21
AV		 1713 rxbdp->lstatus = 0;
1714 rxbdp->bufPtr = 0;
1715 rxbdp++;
1da177e4 1716 }
a12f801d 1717 kfree(rx_queue->rx_skbuff);
fba4ed03 1718}
e69edd21 1719
fba4ed03
SG		 1720/* If there are any tx skbs or rx skbs still around, free them.
1721 * Then free tx_skbuff and rx_skbuff */
1722static void free_skb_resources(struct gfar_private *priv)
1723{
1724 struct gfar_priv_tx_q *tx_queue = NULL;
1725 struct gfar_priv_rx_q *rx_queue = NULL;
1726 int i;
1727
1728 /* Go through all the buffer descriptors and free their data buffers */
1729 for (i = 0; i < priv->num_tx_queues; i++) {
d8a0f1b0 1730 struct netdev_queue *txq;
fba4ed03 1731 tx_queue = priv->tx_queue[i];
d8a0f1b0 1732 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
7c0d10d3 1733 if(tx_queue->tx_skbuff)
fba4ed03 1734 free_skb_tx_queue(tx_queue);
d8a0f1b0 1735 netdev_tx_reset_queue(txq);
fba4ed03
SG		 1736 }
1737
1738 for (i = 0; i < priv->num_rx_queues; i++) {
1739 rx_queue = priv->rx_queue[i];
7c0d10d3 1740 if(rx_queue->rx_skbuff)
fba4ed03
SG		 1741 free_skb_rx_queue(rx_queue);
1742 }
1743
1744 dma_free_coherent(&priv->ofdev->dev,
1745 sizeof(struct txbd8) * priv->total_tx_ring_size +
1746 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1747 priv->tx_queue[0]->tx_bd_base,
1748 priv->tx_queue[0]->tx_bd_dma_base);
7df9c43f 1749 skb_queue_purge(&priv->rx_recycle);
1da177e4
LT		 1750}
1751
0bbaf069
KG		 1752void gfar_start(struct net_device *dev)
1753{
1754 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 1755 struct gfar __iomem *regs = priv->gfargrp[0].regs;
0bbaf069 1756 u32 tempval;
46ceb60c 1757 int i = 0;
0bbaf069
KG		 1758
1759 /* Enable Rx and Tx in MACCFG1 */
1760 tempval = gfar_read(&regs->maccfg1);
1761 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1762 gfar_write(&regs->maccfg1, tempval);
1763
1764 /* Initialize DMACTRL to have WWR and WOP */
f4983704 1765 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1766 tempval |= DMACTRL_INIT_SETTINGS;
f4983704 1767 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1768
0bbaf069 1769 /* Make sure we aren't stopped */
f4983704 1770 tempval = gfar_read(&regs->dmactrl);
0bbaf069 1771 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
f4983704 1772 gfar_write(&regs->dmactrl, tempval);
0bbaf069 1773
46ceb60c
SG		 1774 for (i = 0; i < priv->num_grps; i++) {
1775 regs = priv->gfargrp[i].regs;
1776 /* Clear THLT/RHLT, so that the DMA starts polling now */
1777 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1778 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1779 /* Unmask the interrupts we look for */
1780 gfar_write(&regs->imask, IMASK_DEFAULT);
1781 }
12dea57b 1782
1ae5dc34 1783 dev->trans_start = jiffies; /* prevent tx timeout */
0bbaf069
KG		 1784}
1785
46ceb60c 1786void gfar_configure_coalescing(struct gfar_private *priv,
18294ad1 1787 unsigned long tx_mask, unsigned long rx_mask)
1da177e4 1788{
46ceb60c 1789 struct gfar __iomem *regs = priv->gfargrp[0].regs;
18294ad1 1790 u32 __iomem *baddr;
46ceb60c 1791 int i = 0;
1da177e4 1792
46ceb60c
SG		 1793 /* Backward compatible case ---- even if we enable
1794 * multiple queues, there's only single reg to program
1795 */
1796 gfar_write(&regs->txic, 0);
1797 if(likely(priv->tx_queue[0]->txcoalescing))
1798 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1da177e4 1799
46ceb60c
SG		 1800 gfar_write(&regs->rxic, 0);
1801 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1802 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
815b97c6 1803
46ceb60c
SG		 1804 if (priv->mode == MQ_MG_MODE) {
1805 baddr = &regs->txic0;
984b3f57 1806 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
9740e001
CM		 1807 gfar_write(baddr + i, 0);
1808 if (likely(priv->tx_queue[i]->txcoalescing))
46ceb60c 1809 gfar_write(baddr + i, priv->tx_queue[i]->txic);
46ceb60c
SG		 1810 }
1811
1812 baddr = &regs->rxic0;
984b3f57 1813 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
9740e001
CM		 1814 gfar_write(baddr + i, 0);
1815 if (likely(priv->rx_queue[i]->rxcoalescing))
46ceb60c 1816 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
46ceb60c
SG		 1817 }
1818 }
1819}
1820
1821static int register_grp_irqs(struct gfar_priv_grp *grp)
1822{
1823 struct gfar_private *priv = grp->priv;
1824 struct net_device *dev = priv->ndev;
1825 int err;
1da177e4 1826
1da177e4
LT		 1827 /* If the device has multiple interrupts, register for
1828 * them. Otherwise, only register for the one */
b31a1d8b 1829 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
0bbaf069 1830 /* Install our interrupt handlers for Error,
1da177e4 1831 * Transmit, and Receive */
46ceb60c
SG		 1832 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1833 grp->int_name_er,grp)) < 0) {
59deab26
JP		 1834 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1835 grp->interruptError);
46ceb60c 1836
2145f1af 1837 goto err_irq_fail;
1da177e4
LT		 1838 }
1839
46ceb60c
SG		 1840 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1841 0, grp->int_name_tx, grp)) < 0) {
59deab26
JP		 1842 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1843 grp->interruptTransmit);
1da177e4
LT		 1844 goto tx_irq_fail;
1845 }
1846
46ceb60c
SG		 1847 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1848 grp->int_name_rx, grp)) < 0) {
59deab26
JP		 1849 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1850 grp->interruptReceive);
1da177e4
LT		 1851 goto rx_irq_fail;
1852 }
1853 } else {
46ceb60c
SG		 1854 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1855 grp->int_name_tx, grp)) < 0) {
59deab26
JP		 1856 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1857 grp->interruptTransmit);
1da177e4
LT		 1858 goto err_irq_fail;
1859 }
1860 }
1861
46ceb60c
SG		 1862 return 0;
1863
1864rx_irq_fail:
1865 free_irq(grp->interruptTransmit, grp);
1866tx_irq_fail:
1867 free_irq(grp->interruptError, grp);
1868err_irq_fail:
1869 return err;
1870
1871}
1872
1873/* Bring the controller up and running */
1874int startup_gfar(struct net_device *ndev)
1875{
1876 struct gfar_private *priv = netdev_priv(ndev);
1877 struct gfar __iomem *regs = NULL;
1878 int err, i, j;
1879
1880 for (i = 0; i < priv->num_grps; i++) {
1881 regs= priv->gfargrp[i].regs;
1882 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1883 }
1884
1885 regs= priv->gfargrp[0].regs;
1886 err = gfar_alloc_skb_resources(ndev);
1887 if (err)
1888 return err;
1889
1890 gfar_init_mac(ndev);
1891
1892 for (i = 0; i < priv->num_grps; i++) {
1893 err = register_grp_irqs(&priv->gfargrp[i]);
1894 if (err) {
1895 for (j = 0; j < i; j++)
1896 free_grp_irqs(&priv->gfargrp[j]);
ff76015f 1897 goto irq_fail;
46ceb60c
SG		 1898 }
1899 }
1900
7f7f5316 1901 /* Start the controller */
ccc05c6e 1902 gfar_start(ndev);
1da177e4 1903
826aa4a0
AV		 1904 phy_start(priv->phydev);
1905
46ceb60c
SG		 1906 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1907
1da177e4
LT		 1908 return 0;
1909
46ceb60c 1910irq_fail:
e69edd21 1911 free_skb_resources(priv);
1da177e4
LT		 1912 return err;
1913}
1914
1915/* Called when something needs to use the ethernet device */
1916/* Returns 0 for success. */
1917static int gfar_enet_open(struct net_device *dev)
1918{
94e8cc35 1919 struct gfar_private *priv = netdev_priv(dev);
1da177e4
LT		 1920 int err;
1921
46ceb60c 1922 enable_napi(priv);
bea3348e 1923
0fd56bb5
AF		 1924 skb_queue_head_init(&priv->rx_recycle);
1925
1da177e4
LT		 1926 /* Initialize a bunch of registers */
1927 init_registers(dev);
1928
1929 gfar_set_mac_address(dev);
1930
1931 err = init_phy(dev);
1932
a12f801d 1933 if (err) {
46ceb60c 1934 disable_napi(priv);
1da177e4 1935 return err;
bea3348e 1936 }
1da177e4
LT		 1937
1938 err = startup_gfar(dev);
db0e8e3f 1939 if (err) {
46ceb60c 1940 disable_napi(priv);
db0e8e3f
AV		 1941 return err;
1942 }
1da177e4 1943
fba4ed03 1944 netif_tx_start_all_queues(dev);
1da177e4 1945
2884e5cc
AV		 1946 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1947
1da177e4
LT		 1948 return err;
1949}
1950
54dc79fe 1951static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
0bbaf069 1952{
54dc79fe 1953 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
6c31d55f
KG		 1954
1955 memset(fcb, 0, GMAC_FCB_LEN);
0bbaf069 1956
0bbaf069
KG		 1957 return fcb;
1958}
1959
9c4886e5
MR		 1960static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1961 int fcb_length)
0bbaf069 1962{
7f7f5316 1963 u8 flags = 0;
0bbaf069
KG		 1964
1965 /* If we're here, it's a IP packet with a TCP or UDP
1966 * payload. We set it to checksum, using a pseudo-header
1967 * we provide
1968 */
7f7f5316 1969 flags = TXFCB_DEFAULT;
0bbaf069 1970
7f7f5316
AF		 1971 /* Tell the controller what the protocol is */
1972 /* And provide the already calculated phcs */
eddc9ec5 1973 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
7f7f5316 1974 flags |= TXFCB_UDP;
4bedb452 1975 fcb->phcs = udp_hdr(skb)->check;
7f7f5316 1976 } else
8da32de5 1977 fcb->phcs = tcp_hdr(skb)->check;
0bbaf069
KG		 1978
1979 /* l3os is the distance between the start of the
1980 * frame (skb->data) and the start of the IP hdr.
1981 * l4os is the distance between the start of the
1982 * l3 hdr and the l4 hdr */
9c4886e5 1983 fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
cfe1fc77 1984 fcb->l4os = skb_network_header_len(skb);
0bbaf069 1985
7f7f5316 1986 fcb->flags = flags;
0bbaf069
KG		 1987}
1988
7f7f5316 1989void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
0bbaf069 1990{
7f7f5316 1991 fcb->flags |= TXFCB_VLN;
0bbaf069
KG		 1992 fcb->vlctl = vlan_tx_tag_get(skb);
1993}
1994
4669bc90
DH		 1995static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1996 struct txbd8 *base, int ring_size)
1997{
1998 struct txbd8 *new_bd = bdp + stride;
1999
2000 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2001}
2002
2003static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2004 int ring_size)
2005{
2006 return skip_txbd(bdp, 1, base, ring_size);
2007}
2008
1da177e4
LT		 2009/* This is called by the kernel when a frame is ready for transmission. */
2010/* It is pointed to by the dev->hard_start_xmit function pointer */
2011static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2012{
2013 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2014 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03 2015 struct netdev_queue *txq;
f4983704 2016 struct gfar __iomem *regs = NULL;
0bbaf069 2017 struct txfcb *fcb = NULL;
f0ee7acf 2018 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
5a5efed4 2019 u32 lstatus;
f0ee7acf 2020 int i, rq = 0, do_tstamp = 0;
4669bc90 2021 u32 bufaddr;
fef6108d 2022 unsigned long flags;
9c4886e5 2023 unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
fba4ed03 2024
deb90eac
AV		 2025 /*
2026 * TOE=1 frames larger than 2500 bytes may see excess delays
2027 * before start of transmission.
2028 */
2029 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2030 skb->ip_summed == CHECKSUM_PARTIAL &&
2031 skb->len > 2500)) {
2032 int ret;
2033
2034 ret = skb_checksum_help(skb);
2035 if (ret)
2036 return ret;
2037 }
2038
fba4ed03
SG		 2039 rq = skb->queue_mapping;
2040 tx_queue = priv->tx_queue[rq];
2041 txq = netdev_get_tx_queue(dev, rq);
a12f801d 2042 base = tx_queue->tx_bd_base;
46ceb60c 2043 regs = tx_queue->grp->regs;
f0ee7acf
MR		 2044
2045 /* check if time stamp should be generated */
2244d07b 2046 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
9c4886e5 2047 priv->hwts_tx_en)) {
f0ee7acf 2048 do_tstamp = 1;
9c4886e5
MR		 2049 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2050 }
4669bc90 2051
5b28beaf
LY		 2052 /* make space for additional header when fcb is needed */
2053 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
eab6d18d 2054 vlan_tx_tag_present(skb) ||
f0ee7acf 2055 unlikely(do_tstamp)) &&
9c4886e5 2056 (skb_headroom(skb) < fcb_length)) {
54dc79fe
SH		 2057 struct sk_buff *skb_new;
2058
9c4886e5 2059 skb_new = skb_realloc_headroom(skb, fcb_length);
54dc79fe
SH		 2060 if (!skb_new) {
2061 dev->stats.tx_errors++;
bd14ba84 2062 kfree_skb(skb);
54dc79fe
SH		 2063 return NETDEV_TX_OK;
2064 }
db83d136 2065
313b037c
ED		 2066 if (skb->sk)
2067 skb_set_owner_w(skb_new, skb->sk);
2068 consume_skb(skb);
54dc79fe
SH		 2069 skb = skb_new;
2070 }
2071
4669bc90
DH		 2072 /* total number of fragments in the SKB */
2073 nr_frags = skb_shinfo(skb)->nr_frags;
2074
f0ee7acf
MR		 2075 /* calculate the required number of TxBDs for this skb */
2076 if (unlikely(do_tstamp))
2077 nr_txbds = nr_frags + 2;
2078 else
2079 nr_txbds = nr_frags + 1;
2080
4669bc90 2081 /* check if there is space to queue this packet */
f0ee7acf 2082 if (nr_txbds > tx_queue->num_txbdfree) {
4669bc90 2083 /* no space, stop the queue */
fba4ed03 2084 netif_tx_stop_queue(txq);
4669bc90 2085 dev->stats.tx_fifo_errors++;
4669bc90
DH		 2086 return NETDEV_TX_BUSY;
2087 }
1da177e4
LT		 2088
2089 /* Update transmit stats */
1ac9ad13
ED		 2090 tx_queue->stats.tx_bytes += skb->len;
2091 tx_queue->stats.tx_packets++;
1da177e4 2092
a12f801d 2093 txbdp = txbdp_start = tx_queue->cur_tx;
f0ee7acf
MR		 2094 lstatus = txbdp->lstatus;
2095
2096 /* Time stamp insertion requires one additional TxBD */
2097 if (unlikely(do_tstamp))
2098 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2099 tx_queue->tx_ring_size);
1da177e4 2100
4669bc90 2101 if (nr_frags == 0) {
f0ee7acf
MR		 2102 if (unlikely(do_tstamp))
2103 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2104 TXBD_INTERRUPT);
2105 else
2106 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
4669bc90
DH		 2107 } else {
2108 /* Place the fragment addresses and lengths into the TxBDs */
2109 for (i = 0; i < nr_frags; i++) {
2110 /* Point at the next BD, wrapping as needed */
a12f801d 2111 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2112
2113 length = skb_shinfo(skb)->frags[i].size;
2114
2115 lstatus = txbdp->lstatus | length |
2116 BD_LFLAG(TXBD_READY);
2117
2118 /* Handle the last BD specially */
2119 if (i == nr_frags - 1)
2120 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1da177e4 2121
2234a722
IC		 2122 bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2123 &skb_shinfo(skb)->frags[i],
2124 0,
2125 length,
2126 DMA_TO_DEVICE);
4669bc90
DH		 2127
2128 /* set the TxBD length and buffer pointer */
2129 txbdp->bufPtr = bufaddr;
2130 txbdp->lstatus = lstatus;
2131 }
2132
2133 lstatus = txbdp_start->lstatus;
2134 }
1da177e4 2135
9c4886e5
MR		 2136 /* Add TxPAL between FCB and frame if required */
2137 if (unlikely(do_tstamp)) {
2138 skb_push(skb, GMAC_TXPAL_LEN);
2139 memset(skb->data, 0, GMAC_TXPAL_LEN);
2140 }
2141
0bbaf069 2142 /* Set up checksumming */
12dea57b 2143 if (CHECKSUM_PARTIAL == skb->ip_summed) {
54dc79fe 2144 fcb = gfar_add_fcb(skb);
4363c2fd
AD		 2145 /* as specified by errata */
2146 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2147 && ((unsigned long)fcb % 0x20) > 0x18)) {
2148 __skb_pull(skb, GMAC_FCB_LEN);
2149 skb_checksum_help(skb);
2150 } else {
2151 lstatus |= BD_LFLAG(TXBD_TOE);
9c4886e5 2152 gfar_tx_checksum(skb, fcb, fcb_length);
4363c2fd 2153 }
0bbaf069
KG		 2154 }
2155
eab6d18d 2156 if (vlan_tx_tag_present(skb)) {
54dc79fe
SH		 2157 if (unlikely(NULL == fcb)) {
2158 fcb = gfar_add_fcb(skb);
5a5efed4 2159 lstatus |= BD_LFLAG(TXBD_TOE);
7f7f5316 2160 }
54dc79fe
SH		 2161
2162 gfar_tx_vlan(skb, fcb);
0bbaf069
KG		 2163 }
2164
f0ee7acf
MR		 2165 /* Setup tx hardware time stamping if requested */
2166 if (unlikely(do_tstamp)) {
2244d07b 2167 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
f0ee7acf
MR		 2168 if (fcb == NULL)
2169 fcb = gfar_add_fcb(skb);
2170 fcb->ptp = 1;
2171 lstatus |= BD_LFLAG(TXBD_TOE);
2172 }
2173
4826857f 2174 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
4669bc90 2175 skb_headlen(skb), DMA_TO_DEVICE);
1da177e4 2176
f0ee7acf
MR		 2177 /*
2178 * If time stamping is requested one additional TxBD must be set up. The
2179 * first TxBD points to the FCB and must have a data length of
2180 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2181 * the full frame length.
2182 */
2183 if (unlikely(do_tstamp)) {
9c4886e5 2184 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
f0ee7acf 2185 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
9c4886e5 2186 (skb_headlen(skb) - fcb_length);
f0ee7acf
MR		 2187 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2188 } else {
2189 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2190 }
1da177e4 2191
d8a0f1b0
PG		 2192 netdev_tx_sent_queue(txq, skb->len);
2193
a3bc1f11
AV		 2194 /*
2195 * We can work in parallel with gfar_clean_tx_ring(), except
2196 * when modifying num_txbdfree. Note that we didn't grab the lock
2197 * when we were reading the num_txbdfree and checking for available
2198 * space, that's because outside of this function it can only grow,
2199 * and once we've got needed space, it cannot suddenly disappear.
2200 *
2201 * The lock also protects us from gfar_error(), which can modify
2202 * regs->tstat and thus retrigger the transfers, which is why we
2203 * also must grab the lock before setting ready bit for the first
2204 * to be transmitted BD.
2205 */
2206 spin_lock_irqsave(&tx_queue->txlock, flags);
2207
4669bc90
DH		 2208 /*
2209 * The powerpc-specific eieio() is used, as wmb() has too strong
3b6330ce
SW		 2210 * semantics (it requires synchronization between cacheable and
2211 * uncacheable mappings, which eieio doesn't provide and which we
2212 * don't need), thus requiring a more expensive sync instruction. At
2213 * some point, the set of architecture-independent barrier functions
2214 * should be expanded to include weaker barriers.
2215 */
3b6330ce 2216 eieio();
7f7f5316 2217
4669bc90
DH		 2218 txbdp_start->lstatus = lstatus;
2219
0eddba52
AV		 2220 eieio(); /* force lstatus write before tx_skbuff */
2221
2222 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2223
4669bc90
DH		 2224 /* Update the current skb pointer to the next entry we will use
2225 * (wrapping if necessary) */
a12f801d
SG		 2226 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2227 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
4669bc90 2228
a12f801d 2229 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
4669bc90
DH		 2230
2231 /* reduce TxBD free count */
f0ee7acf 2232 tx_queue->num_txbdfree -= (nr_txbds);
1da177e4
LT		 2233
2234 /* If the next BD still needs to be cleaned up, then the bds
2235 are full. We need to tell the kernel to stop sending us stuff. */
a12f801d 2236 if (!tx_queue->num_txbdfree) {
fba4ed03 2237 netif_tx_stop_queue(txq);
1da177e4 2238
09f75cd7 2239 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2240 }
2241
1da177e4 2242 /* Tell the DMA to go go go */
fba4ed03 2243 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
1da177e4
LT		 2244
2245 /* Unlock priv */
a12f801d 2246 spin_unlock_irqrestore(&tx_queue->txlock, flags);
1da177e4 2247
54dc79fe 2248 return NETDEV_TX_OK;
1da177e4
LT		 2249}
2250
2251/* Stops the kernel queue, and halts the controller */
2252static int gfar_close(struct net_device *dev)
2253{
2254 struct gfar_private *priv = netdev_priv(dev);
bea3348e 2255
46ceb60c 2256 disable_napi(priv);
bea3348e 2257
ab939905 2258 cancel_work_sync(&priv->reset_task);
1da177e4
LT		 2259 stop_gfar(dev);
2260
bb40dcbb
AF		 2261 /* Disconnect from the PHY */
2262 phy_disconnect(priv->phydev);
2263 priv->phydev = NULL;
1da177e4 2264
fba4ed03 2265 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2266
2267 return 0;
2268}
2269
1da177e4 2270/* Changes the mac address if the controller is not running. */
f162b9d5 2271static int gfar_set_mac_address(struct net_device *dev)
1da177e4 2272{
7f7f5316 2273 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1da177e4
LT		 2274
2275 return 0;
2276}
2277
f3dc1586
SP		 2278/* Check if rx parser should be activated */
2279void gfar_check_rx_parser_mode(struct gfar_private *priv)
2280{
2281 struct gfar __iomem *regs;
2282 u32 tempval;
2283
2284 regs = priv->gfargrp[0].regs;
2285
2286 tempval = gfar_read(&regs->rctrl);
2287 /* If parse is no longer required, then disable parser */
2288 if (tempval & RCTRL_REQ_PARSER)
2289 tempval |= RCTRL_PRSDEP_INIT;
2290 else
2291 tempval &= ~RCTRL_PRSDEP_INIT;
2292 gfar_write(&regs->rctrl, tempval);
2293}
2294
0bbaf069 2295/* Enables and disables VLAN insertion/extraction */
c8f44aff 2296void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
0bbaf069
KG		 2297{
2298 struct gfar_private *priv = netdev_priv(dev);
f4983704 2299 struct gfar __iomem *regs = NULL;
0bbaf069
KG		 2300 unsigned long flags;
2301 u32 tempval;
2302
46ceb60c 2303 regs = priv->gfargrp[0].regs;
fba4ed03
SG		 2304 local_irq_save(flags);
2305 lock_rx_qs(priv);
0bbaf069 2306
87c288c6 2307 if (features & NETIF_F_HW_VLAN_TX) {
0bbaf069 2308 /* Enable VLAN tag insertion */
f4983704 2309 tempval = gfar_read(&regs->tctrl);
0bbaf069 2310 tempval |= TCTRL_VLINS;
f4983704 2311 gfar_write(&regs->tctrl, tempval);
0bbaf069
KG		 2312 } else {
2313 /* Disable VLAN tag insertion */
f4983704 2314 tempval = gfar_read(&regs->tctrl);
0bbaf069 2315 tempval &= ~TCTRL_VLINS;
f4983704 2316 gfar_write(&regs->tctrl, tempval);
87c288c6 2317 }
0bbaf069 2318
87c288c6
JP		 2319 if (features & NETIF_F_HW_VLAN_RX) {
2320 /* Enable VLAN tag extraction */
2321 tempval = gfar_read(&regs->rctrl);
2322 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2323 gfar_write(&regs->rctrl, tempval);
2324 } else {
0bbaf069 2325 /* Disable VLAN tag extraction */
f4983704 2326 tempval = gfar_read(&regs->rctrl);
0bbaf069 2327 tempval &= ~RCTRL_VLEX;
f4983704 2328 gfar_write(&regs->rctrl, tempval);
f3dc1586
SP		 2329
2330 gfar_check_rx_parser_mode(priv);
0bbaf069
KG		 2331 }
2332
77ecaf2d
DH		 2333 gfar_change_mtu(dev, dev->mtu);
2334
fba4ed03
SG		 2335 unlock_rx_qs(priv);
2336 local_irq_restore(flags);
0bbaf069
KG		 2337}
2338
1da177e4
LT		 2339static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2340{
2341 int tempsize, tempval;
2342 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2343 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4 2344 int oldsize = priv->rx_buffer_size;
0bbaf069
KG		 2345 int frame_size = new_mtu + ETH_HLEN;
2346
87c288c6 2347 if (gfar_is_vlan_on(priv))
faa89577 2348 frame_size += VLAN_HLEN;
0bbaf069 2349
1da177e4 2350 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
59deab26 2351 netif_err(priv, drv, dev, "Invalid MTU setting\n");
1da177e4
LT		 2352 return -EINVAL;
2353 }
2354
77ecaf2d
DH		 2355 if (gfar_uses_fcb(priv))
2356 frame_size += GMAC_FCB_LEN;
2357
2358 frame_size += priv->padding;
2359
1da177e4
LT		 2360 tempsize =
2361 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2362 INCREMENTAL_BUFFER_SIZE;
2363
2364 /* Only stop and start the controller if it isn't already
7f7f5316 2365 * stopped, and we changed something */
1da177e4
LT		 2366 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2367 stop_gfar(dev);
2368
2369 priv->rx_buffer_size = tempsize;
2370
2371 dev->mtu = new_mtu;
2372
f4983704
SG		 2373 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2374 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
1da177e4
LT		 2375
2376 /* If the mtu is larger than the max size for standard
2377 * ethernet frames (ie, a jumbo frame), then set maccfg2
2378 * to allow huge frames, and to check the length */
f4983704 2379 tempval = gfar_read(&regs->maccfg2);
1da177e4 2380
7d350977
AV		 2381 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2382 gfar_has_errata(priv, GFAR_ERRATA_74))
1da177e4
LT		 2383 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2384 else
2385 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2386
f4983704 2387 gfar_write(&regs->maccfg2, tempval);
1da177e4
LT		 2388
2389 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2390 startup_gfar(dev);
2391
2392 return 0;
2393}
2394
ab939905 2395/* gfar_reset_task gets scheduled when a packet has not been
1da177e4
LT		 2396 * transmitted after a set amount of time.
2397 * For now, assume that clearing out all the structures, and
ab939905
SS		 2398 * starting over will fix the problem.
2399 */
2400static void gfar_reset_task(struct work_struct *work)
1da177e4 2401{
ab939905
SS		 2402 struct gfar_private *priv = container_of(work, struct gfar_private,
2403 reset_task);
4826857f 2404 struct net_device *dev = priv->ndev;
1da177e4
LT		 2405
2406 if (dev->flags & IFF_UP) {
fba4ed03 2407 netif_tx_stop_all_queues(dev);
1da177e4
LT		 2408 stop_gfar(dev);
2409 startup_gfar(dev);
fba4ed03 2410 netif_tx_start_all_queues(dev);
1da177e4
LT		 2411 }
2412
263ba320 2413 netif_tx_schedule_all(dev);
1da177e4
LT		 2414}
2415
ab939905
SS		 2416static void gfar_timeout(struct net_device *dev)
2417{
2418 struct gfar_private *priv = netdev_priv(dev);
2419
2420 dev->stats.tx_errors++;
2421 schedule_work(&priv->reset_task);
2422}
2423
acbc0f03
EL		 2424static void gfar_align_skb(struct sk_buff *skb)
2425{
2426 /* We need the data buffer to be aligned properly. We will reserve
2427 * as many bytes as needed to align the data properly
2428 */
2429 skb_reserve(skb, RXBUF_ALIGNMENT -
2430 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2431}
2432
1da177e4 2433/* Interrupt Handler for Transmit complete */
a12f801d 2434static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
1da177e4 2435{
a12f801d 2436 struct net_device *dev = tx_queue->dev;
d8a0f1b0 2437 struct netdev_queue *txq;
d080cd63 2438 struct gfar_private *priv = netdev_priv(dev);
a12f801d 2439 struct gfar_priv_rx_q *rx_queue = NULL;
f0ee7acf 2440 struct txbd8 *bdp, *next = NULL;
4669bc90 2441 struct txbd8 *lbdp = NULL;
a12f801d 2442 struct txbd8 *base = tx_queue->tx_bd_base;
4669bc90
DH		 2443 struct sk_buff *skb;
2444 int skb_dirtytx;
a12f801d 2445 int tx_ring_size = tx_queue->tx_ring_size;
f0ee7acf 2446 int frags = 0, nr_txbds = 0;
4669bc90 2447 int i;
d080cd63 2448 int howmany = 0;
d8a0f1b0
PG		 2449 int tqi = tx_queue->qindex;
2450 unsigned int bytes_sent = 0;
4669bc90 2451 u32 lstatus;
f0ee7acf 2452 size_t buflen;
1da177e4 2453
d8a0f1b0
PG		 2454 rx_queue = priv->rx_queue[tqi];
2455 txq = netdev_get_tx_queue(dev, tqi);
a12f801d
SG		 2456 bdp = tx_queue->dirty_tx;
2457 skb_dirtytx = tx_queue->skb_dirtytx;
1da177e4 2458
a12f801d 2459 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
a3bc1f11
AV		 2460 unsigned long flags;
2461
4669bc90 2462 frags = skb_shinfo(skb)->nr_frags;
f0ee7acf
MR		 2463
2464 /*
2465 * When time stamping, one additional TxBD must be freed.
2466 * Also, we need to dma_unmap_single() the TxPAL.
2467 */
2244d07b 2468 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
f0ee7acf
MR		 2469 nr_txbds = frags + 2;
2470 else
2471 nr_txbds = frags + 1;
2472
2473 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
1da177e4 2474
4669bc90 2475 lstatus = lbdp->lstatus;
1da177e4 2476
4669bc90
DH		 2477 /* Only clean completed frames */
2478 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2479 (lstatus & BD_LENGTH_MASK))
2480 break;
2481
2244d07b 2482 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf 2483 next = next_txbd(bdp, base, tx_ring_size);
9c4886e5 2484 buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
f0ee7acf
MR		 2485 } else
2486 buflen = bdp->length;
2487
2488 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2489 buflen, DMA_TO_DEVICE);
2490
2244d07b 2491 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
f0ee7acf
MR		 2492 struct skb_shared_hwtstamps shhwtstamps;
2493 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2494 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2495 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
9c4886e5 2496 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
f0ee7acf
MR		 2497 skb_tstamp_tx(skb, &shhwtstamps);
2498 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2499 bdp = next;
2500 }
81183059 2501
4669bc90
DH		 2502 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2503 bdp = next_txbd(bdp, base, tx_ring_size);
d080cd63 2504
4669bc90 2505 for (i = 0; i < frags; i++) {
4826857f 2506 dma_unmap_page(&priv->ofdev->dev,
4669bc90
DH		 2507 bdp->bufPtr,
2508 bdp->length,
2509 DMA_TO_DEVICE);
2510 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2511 bdp = next_txbd(bdp, base, tx_ring_size);
2512 }
1da177e4 2513
d8a0f1b0
PG		 2514 bytes_sent += skb->len;
2515
0fd56bb5
AF		 2516 /*
2517 * If there's room in the queue (limit it to rx_buffer_size)
2518 * we add this skb back into the pool, if it's the right size
2519 */
a12f801d 2520 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
0fd56bb5 2521 skb_recycle_check(skb, priv->rx_buffer_size +
acbc0f03
EL		 2522 RXBUF_ALIGNMENT)) {
2523 gfar_align_skb(skb);
cd0ea241 2524 skb_queue_head(&priv->rx_recycle, skb);
acbc0f03 2525 } else
0fd56bb5
AF		 2526 dev_kfree_skb_any(skb);
2527
a12f801d 2528 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
d080cd63 2529
4669bc90
DH		 2530 skb_dirtytx = (skb_dirtytx + 1) &
2531 TX_RING_MOD_MASK(tx_ring_size);
2532
2533 howmany++;
a3bc1f11 2534 spin_lock_irqsave(&tx_queue->txlock, flags);
f0ee7acf 2535 tx_queue->num_txbdfree += nr_txbds;
a3bc1f11 2536 spin_unlock_irqrestore(&tx_queue->txlock, flags);
4669bc90 2537 }
1da177e4 2538
4669bc90 2539 /* If we freed a buffer, we can restart transmission, if necessary */
5407b14c 2540 if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
d8a0f1b0 2541 netif_wake_subqueue(dev, tqi);
1da177e4 2542
4669bc90 2543 /* Update dirty indicators */
a12f801d
SG		 2544 tx_queue->skb_dirtytx = skb_dirtytx;
2545 tx_queue->dirty_tx = bdp;
1da177e4 2546
d8a0f1b0
PG		 2547 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2548
d080cd63
DH		 2549 return howmany;
2550}
2551
f4983704 2552static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
d080cd63 2553{
a6d0b91a
AV		 2554 unsigned long flags;
2555
fba4ed03
SG		 2556 spin_lock_irqsave(&gfargrp->grplock, flags);
2557 if (napi_schedule_prep(&gfargrp->napi)) {
f4983704 2558 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
fba4ed03 2559 __napi_schedule(&gfargrp->napi);
8707bdd4
JP		 2560 } else {
2561 /*
2562 * Clear IEVENT, so interrupts aren't called again
2563 * because of the packets that have already arrived.
2564 */
f4983704 2565 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2f448911 2566 }
fba4ed03 2567 spin_unlock_irqrestore(&gfargrp->grplock, flags);
a6d0b91a 2568
8c7396ae 2569}
1da177e4 2570
8c7396ae 2571/* Interrupt Handler for Transmit complete */
f4983704 2572static irqreturn_t gfar_transmit(int irq, void *grp_id)
8c7396ae 2573{
f4983704 2574 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2575 return IRQ_HANDLED;
2576}
2577
a12f801d 2578static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
815b97c6
AF		 2579 struct sk_buff *skb)
2580{
a12f801d 2581 struct net_device *dev = rx_queue->dev;
815b97c6 2582 struct gfar_private *priv = netdev_priv(dev);
8a102fe0 2583 dma_addr_t buf;
815b97c6 2584
8a102fe0
AV		 2585 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2586 priv->rx_buffer_size, DMA_FROM_DEVICE);
a12f801d 2587 gfar_init_rxbdp(rx_queue, bdp, buf);
815b97c6
AF		 2588}
2589
acbc0f03 2590static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
1da177e4
LT		 2591{
2592 struct gfar_private *priv = netdev_priv(dev);
2593 struct sk_buff *skb = NULL;
1da177e4 2594
acbc0f03 2595 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
815b97c6 2596 if (!skb)
1da177e4
LT		 2597 return NULL;
2598
acbc0f03 2599 gfar_align_skb(skb);
7f7f5316 2600
acbc0f03
EL		 2601 return skb;
2602}
2603
2604struct sk_buff * gfar_new_skb(struct net_device *dev)
2605{
2606 struct gfar_private *priv = netdev_priv(dev);
2607 struct sk_buff *skb = NULL;
2608
cd0ea241 2609 skb = skb_dequeue(&priv->rx_recycle);
acbc0f03
EL		 2610 if (!skb)
2611 skb = gfar_alloc_skb(dev);
1da177e4 2612
1da177e4
LT		 2613 return skb;
2614}
2615
298e1a9e 2616static inline void count_errors(unsigned short status, struct net_device *dev)
1da177e4 2617{
298e1a9e 2618 struct gfar_private *priv = netdev_priv(dev);
09f75cd7 2619 struct net_device_stats *stats = &dev->stats;
1da177e4
LT		 2620 struct gfar_extra_stats *estats = &priv->extra_stats;
2621
2622 /* If the packet was truncated, none of the other errors
2623 * matter */
2624 if (status & RXBD_TRUNCATED) {
2625 stats->rx_length_errors++;
2626
2627 estats->rx_trunc++;
2628
2629 return;
2630 }
2631 /* Count the errors, if there were any */
2632 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2633 stats->rx_length_errors++;
2634
2635 if (status & RXBD_LARGE)
2636 estats->rx_large++;
2637 else
2638 estats->rx_short++;
2639 }
2640 if (status & RXBD_NONOCTET) {
2641 stats->rx_frame_errors++;
2642 estats->rx_nonoctet++;
2643 }
2644 if (status & RXBD_CRCERR) {
2645 estats->rx_crcerr++;
2646 stats->rx_crc_errors++;
2647 }
2648 if (status & RXBD_OVERRUN) {
2649 estats->rx_overrun++;
2650 stats->rx_crc_errors++;
2651 }
2652}
2653
f4983704 2654irqreturn_t gfar_receive(int irq, void *grp_id)
1da177e4 2655{
f4983704 2656 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
1da177e4
LT		 2657 return IRQ_HANDLED;
2658}
2659
0bbaf069
KG		 2660static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2661{
2662 /* If valid headers were found, and valid sums
2663 * were verified, then we tell the kernel that no
2664 * checksumming is necessary. Otherwise, it is */
7f7f5316 2665 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
0bbaf069
KG		 2666 skb->ip_summed = CHECKSUM_UNNECESSARY;
2667 else
bc8acf2c 2668 skb_checksum_none_assert(skb);
0bbaf069
KG		 2669}
2670
2671
1da177e4
LT		 2672/* gfar_process_frame() -- handle one incoming packet if skb
2673 * isn't NULL. */
2674static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
cd754a57 2675 int amount_pull, struct napi_struct *napi)
1da177e4
LT		 2676{
2677 struct gfar_private *priv = netdev_priv(dev);
0bbaf069 2678 struct rxfcb *fcb = NULL;
1da177e4 2679
cd754a57 2680 gro_result_t ret;
1da177e4 2681
2c2db48a
DH		 2682 /* fcb is at the beginning if exists */
2683 fcb = (struct rxfcb *)skb->data;
0bbaf069 2684
2c2db48a
DH		 2685 /* Remove the FCB from the skb */
2686 /* Remove the padded bytes, if there are any */
f74dac08
SG		 2687 if (amount_pull) {
2688 skb_record_rx_queue(skb, fcb->rq);
2c2db48a 2689 skb_pull(skb, amount_pull);
f74dac08 2690 }
0bbaf069 2691
cc772ab7
MR		 2692 /* Get receive timestamp from the skb */
2693 if (priv->hwts_rx_en) {
2694 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2695 u64 *ns = (u64 *) skb->data;
2696 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2697 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2698 }
2699
2700 if (priv->padding)
2701 skb_pull(skb, priv->padding);
2702
8b3afe95 2703 if (dev->features & NETIF_F_RXCSUM)
2c2db48a 2704 gfar_rx_checksum(skb, fcb);
0bbaf069 2705
2c2db48a
DH		 2706 /* Tell the skb what kind of packet this is */
2707 skb->protocol = eth_type_trans(skb, dev);
1da177e4 2708
32f7fd44
JP		 2709 /*
2710 * There's need to check for NETIF_F_HW_VLAN_RX here.
2711 * Even if vlan rx accel is disabled, on some chips
2712 * RXFCB_VLN is pseudo randomly set.
2713 */
2714 if (dev->features & NETIF_F_HW_VLAN_RX &&
2715 fcb->flags & RXFCB_VLN)
87c288c6
JP		 2716 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2717
2c2db48a 2718 /* Send the packet up the stack */
cd754a57 2719 ret = napi_gro_receive(napi, skb);
0bbaf069 2720
cd754a57 2721 if (GRO_DROP == ret)
2c2db48a 2722 priv->extra_stats.kernel_dropped++;
1da177e4
LT		 2723
2724 return 0;
2725}
2726
2727/* gfar_clean_rx_ring() -- Processes each frame in the rx ring
0bbaf069 2728 * until the budget/quota has been reached. Returns the number
1da177e4
LT		 2729 * of frames handled
2730 */
a12f801d 2731int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
1da177e4 2732{
a12f801d 2733 struct net_device *dev = rx_queue->dev;
31de198b 2734 struct rxbd8 *bdp, *base;
1da177e4 2735 struct sk_buff *skb;
2c2db48a
DH		 2736 int pkt_len;
2737 int amount_pull;
1da177e4
LT		 2738 int howmany = 0;
2739 struct gfar_private *priv = netdev_priv(dev);
2740
2741 /* Get the first full descriptor */
a12f801d
SG		 2742 bdp = rx_queue->cur_rx;
2743 base = rx_queue->rx_bd_base;
1da177e4 2744
cc772ab7 2745 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2c2db48a 2746
1da177e4 2747 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
815b97c6 2748 struct sk_buff *newskb;
3b6330ce 2749 rmb();
815b97c6
AF		 2750
2751 /* Add another skb for the future */
2752 newskb = gfar_new_skb(dev);
2753
a12f801d 2754 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
1da177e4 2755
4826857f 2756 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
81183059
AF		 2757 priv->rx_buffer_size, DMA_FROM_DEVICE);
2758
63b88b90
AV		 2759 if (unlikely(!(bdp->status & RXBD_ERR) &&
2760 bdp->length > priv->rx_buffer_size))
2761 bdp->status = RXBD_LARGE;
2762
815b97c6
AF		 2763 /* We drop the frame if we failed to allocate a new buffer */
2764 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2765 bdp->status & RXBD_ERR)) {
2766 count_errors(bdp->status, dev);
2767
2768 if (unlikely(!newskb))
2769 newskb = skb;
acbc0f03 2770 else if (skb)
cd0ea241 2771 skb_queue_head(&priv->rx_recycle, skb);
815b97c6 2772 } else {
1da177e4 2773 /* Increment the number of packets */
a7f38041 2774 rx_queue->stats.rx_packets++;
1da177e4
LT		 2775 howmany++;
2776
2c2db48a
DH		 2777 if (likely(skb)) {
2778 pkt_len = bdp->length - ETH_FCS_LEN;
2779 /* Remove the FCS from the packet length */
2780 skb_put(skb, pkt_len);
a7f38041 2781 rx_queue->stats.rx_bytes += pkt_len;
f74dac08 2782 skb_record_rx_queue(skb, rx_queue->qindex);
cd754a57
WJB		 2783 gfar_process_frame(dev, skb, amount_pull,
2784 &rx_queue->grp->napi);
2c2db48a
DH		 2785
2786 } else {
59deab26 2787 netif_warn(priv, rx_err, dev, "Missing skb!\n");
a7f38041 2788 rx_queue->stats.rx_dropped++;
2c2db48a
DH		 2789 priv->extra_stats.rx_skbmissing++;
2790 }
1da177e4 2791
1da177e4
LT		 2792 }
2793
a12f801d 2794 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
1da177e4 2795
815b97c6 2796 /* Setup the new bdp */
a12f801d 2797 gfar_new_rxbdp(rx_queue, bdp, newskb);
1da177e4
LT		 2798
2799 /* Update to the next pointer */
a12f801d 2800 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
1da177e4
LT		 2801
2802 /* update to point at the next skb */
a12f801d
SG		 2803 rx_queue->skb_currx =
2804 (rx_queue->skb_currx + 1) &
2805 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
1da177e4
LT		 2806 }
2807
2808 /* Update the current rxbd pointer to be the next one */
a12f801d 2809 rx_queue->cur_rx = bdp;
1da177e4 2810
1da177e4
LT		 2811 return howmany;
2812}
2813
bea3348e 2814static int gfar_poll(struct napi_struct *napi, int budget)
1da177e4 2815{
fba4ed03
SG		 2816 struct gfar_priv_grp *gfargrp = container_of(napi,
2817 struct gfar_priv_grp, napi);
2818 struct gfar_private *priv = gfargrp->priv;
46ceb60c 2819 struct gfar __iomem *regs = gfargrp->regs;
a12f801d 2820 struct gfar_priv_tx_q *tx_queue = NULL;
fba4ed03
SG		 2821 struct gfar_priv_rx_q *rx_queue = NULL;
2822 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
18294ad1
AV		 2823 int tx_cleaned = 0, i, left_over_budget = budget;
2824 unsigned long serviced_queues = 0;
fba4ed03 2825 int num_queues = 0;
d080cd63 2826
fba4ed03
SG		 2827 num_queues = gfargrp->num_rx_queues;
2828 budget_per_queue = budget/num_queues;
2829
8c7396ae
DH		 2830 /* Clear IEVENT, so interrupts aren't called again
2831 * because of the packets that have already arrived */
f4983704 2832 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
8c7396ae 2833
fba4ed03 2834 while (num_queues && left_over_budget) {
1da177e4 2835
fba4ed03
SG		 2836 budget_per_queue = left_over_budget/num_queues;
2837 left_over_budget = 0;
2838
984b3f57 2839 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
fba4ed03
SG		 2840 if (test_bit(i, &serviced_queues))
2841 continue;
2842 rx_queue = priv->rx_queue[i];
2843 tx_queue = priv->tx_queue[rx_queue->qindex];
2844
a3bc1f11 2845 tx_cleaned += gfar_clean_tx_ring(tx_queue);
fba4ed03
SG		 2846 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2847 budget_per_queue);
2848 rx_cleaned += rx_cleaned_per_queue;
2849 if(rx_cleaned_per_queue < budget_per_queue) {
2850 left_over_budget = left_over_budget +
2851 (budget_per_queue - rx_cleaned_per_queue);
2852 set_bit(i, &serviced_queues);
2853 num_queues--;
2854 }
2855 }
2856 }
1da177e4 2857
42199884
AF		 2858 if (tx_cleaned)
2859 return budget;
2860
2861 if (rx_cleaned < budget) {
288379f0 2862 napi_complete(napi);
1da177e4
LT		 2863
2864 /* Clear the halt bit in RSTAT */
fba4ed03 2865 gfar_write(&regs->rstat, gfargrp->rstat);
1da177e4 2866
f4983704 2867 gfar_write(&regs->imask, IMASK_DEFAULT);
1da177e4
LT		 2868
2869 /* If we are coalescing interrupts, update the timer */
2870 /* Otherwise, clear it */
46ceb60c
SG		 2871 gfar_configure_coalescing(priv,
2872 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
1da177e4
LT		 2873 }
2874
42199884 2875 return rx_cleaned;
1da177e4 2876}
1da177e4 2877
f2d71c2d
VW		 2878#ifdef CONFIG_NET_POLL_CONTROLLER
2879/*
2880 * Polling 'interrupt' - used by things like netconsole to send skbs
2881 * without having to re-enable interrupts. It's not called while
2882 * the interrupt routine is executing.
2883 */
2884static void gfar_netpoll(struct net_device *dev)
2885{
2886 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2887 int i = 0;
f2d71c2d
VW		 2888
2889 /* If the device has multiple interrupts, run tx/rx */
b31a1d8b 2890 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
46ceb60c
SG		 2891 for (i = 0; i < priv->num_grps; i++) {
2892 disable_irq(priv->gfargrp[i].interruptTransmit);
2893 disable_irq(priv->gfargrp[i].interruptReceive);
2894 disable_irq(priv->gfargrp[i].interruptError);
2895 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2896 &priv->gfargrp[i]);
2897 enable_irq(priv->gfargrp[i].interruptError);
2898 enable_irq(priv->gfargrp[i].interruptReceive);
2899 enable_irq(priv->gfargrp[i].interruptTransmit);
2900 }
f2d71c2d 2901 } else {
46ceb60c
SG		 2902 for (i = 0; i < priv->num_grps; i++) {
2903 disable_irq(priv->gfargrp[i].interruptTransmit);
2904 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2905 &priv->gfargrp[i]);
2906 enable_irq(priv->gfargrp[i].interruptTransmit);
43de004b 2907 }
f2d71c2d
VW		 2908 }
2909}
2910#endif
2911
1da177e4 2912/* The interrupt handler for devices with one interrupt */
f4983704 2913static irqreturn_t gfar_interrupt(int irq, void *grp_id)
1da177e4 2914{
f4983704 2915 struct gfar_priv_grp *gfargrp = grp_id;
1da177e4
LT		 2916
2917 /* Save ievent for future reference */
f4983704 2918 u32 events = gfar_read(&gfargrp->regs->ievent);
1da177e4 2919
1da177e4 2920 /* Check for reception */
538cc7ee 2921 if (events & IEVENT_RX_MASK)
f4983704 2922 gfar_receive(irq, grp_id);
1da177e4
LT		 2923
2924 /* Check for transmit completion */
538cc7ee 2925 if (events & IEVENT_TX_MASK)
f4983704 2926 gfar_transmit(irq, grp_id);
1da177e4 2927
538cc7ee
SS		 2928 /* Check for errors */
2929 if (events & IEVENT_ERR_MASK)
f4983704 2930 gfar_error(irq, grp_id);
1da177e4
LT		 2931
2932 return IRQ_HANDLED;
2933}
2934
1da177e4
LT		 2935/* Called every time the controller might need to be made
2936 * aware of new link state. The PHY code conveys this
bb40dcbb 2937 * information through variables in the phydev structure, and this
1da177e4
LT		 2938 * function converts those variables into the appropriate
2939 * register values, and can bring down the device if needed.
2940 */
2941static void adjust_link(struct net_device *dev)
2942{
2943 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 2944 struct gfar __iomem *regs = priv->gfargrp[0].regs;
bb40dcbb
AF		 2945 unsigned long flags;
2946 struct phy_device *phydev = priv->phydev;
2947 int new_state = 0;
2948
fba4ed03
SG		 2949 local_irq_save(flags);
2950 lock_tx_qs(priv);
2951
bb40dcbb
AF		 2952 if (phydev->link) {
2953 u32 tempval = gfar_read(&regs->maccfg2);
7f7f5316 2954 u32 ecntrl = gfar_read(&regs->ecntrl);
1da177e4 2955
1da177e4
LT		 2956 /* Now we make sure that we can be in full duplex mode.
2957 * If not, we operate in half-duplex mode. */
bb40dcbb
AF		 2958 if (phydev->duplex != priv->oldduplex) {
2959 new_state = 1;
2960 if (!(phydev->duplex))
1da177e4 2961 tempval &= ~(MACCFG2_FULL_DUPLEX);
bb40dcbb 2962 else
1da177e4 2963 tempval |= MACCFG2_FULL_DUPLEX;
1da177e4 2964
bb40dcbb 2965 priv->oldduplex = phydev->duplex;
1da177e4
LT		 2966 }
2967
bb40dcbb
AF		 2968 if (phydev->speed != priv->oldspeed) {
2969 new_state = 1;
2970 switch (phydev->speed) {
1da177e4 2971 case 1000:
1da177e4
LT		 2972 tempval =
2973 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
f430e49e
LY		 2974
2975 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2976 break;
2977 case 100:
2978 case 10:
1da177e4
LT		 2979 tempval =
2980 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
7f7f5316
AF		 2981
2982 /* Reduced mode distinguishes
2983 * between 10 and 100 */
2984 if (phydev->speed == SPEED_100)
2985 ecntrl |= ECNTRL_R100;
2986 else
2987 ecntrl &= ~(ECNTRL_R100);
1da177e4
LT		 2988 break;
2989 default:
59deab26
JP		 2990 netif_warn(priv, link, dev,
2991 "Ack! Speed (%d) is not 10/100/1000!\n",
2992 phydev->speed);
1da177e4
LT		 2993 break;
2994 }
2995
bb40dcbb 2996 priv->oldspeed = phydev->speed;
1da177e4
LT		 2997 }
2998
bb40dcbb 2999 gfar_write(&regs->maccfg2, tempval);
7f7f5316 3000 gfar_write(&regs->ecntrl, ecntrl);
bb40dcbb 3001
1da177e4 3002 if (!priv->oldlink) {
bb40dcbb 3003 new_state = 1;
1da177e4 3004 priv->oldlink = 1;
1da177e4 3005 }
bb40dcbb
AF		 3006 } else if (priv->oldlink) {
3007 new_state = 1;
3008 priv->oldlink = 0;
3009 priv->oldspeed = 0;
3010 priv->oldduplex = -1;
1da177e4 3011 }
1da177e4 3012
bb40dcbb
AF		 3013 if (new_state && netif_msg_link(priv))
3014 phy_print_status(phydev);
fba4ed03
SG		 3015 unlock_tx_qs(priv);
3016 local_irq_restore(flags);
bb40dcbb 3017}
1da177e4
LT		 3018
3019/* Update the hash table based on the current list of multicast
3020 * addresses we subscribe to. Also, change the promiscuity of
3021 * the device based on the flags (this function is called
3022 * whenever dev->flags is changed */
3023static void gfar_set_multi(struct net_device *dev)
3024{
22bedad3 3025 struct netdev_hw_addr *ha;
1da177e4 3026 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3027 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1da177e4
LT		 3028 u32 tempval;
3029
a12f801d 3030 if (dev->flags & IFF_PROMISC) {
1da177e4
LT		 3031 /* Set RCTRL to PROM */
3032 tempval = gfar_read(&regs->rctrl);
3033 tempval |= RCTRL_PROM;
3034 gfar_write(&regs->rctrl, tempval);
3035 } else {
3036 /* Set RCTRL to not PROM */
3037 tempval = gfar_read(&regs->rctrl);
3038 tempval &= ~(RCTRL_PROM);
3039 gfar_write(&regs->rctrl, tempval);
3040 }
6aa20a22 3041
a12f801d 3042 if (dev->flags & IFF_ALLMULTI) {
1da177e4 3043 /* Set the hash to rx all multicast frames */
0bbaf069
KG		 3044 gfar_write(&regs->igaddr0, 0xffffffff);
3045 gfar_write(&regs->igaddr1, 0xffffffff);
3046 gfar_write(&regs->igaddr2, 0xffffffff);
3047 gfar_write(&regs->igaddr3, 0xffffffff);
3048 gfar_write(&regs->igaddr4, 0xffffffff);
3049 gfar_write(&regs->igaddr5, 0xffffffff);
3050 gfar_write(&regs->igaddr6, 0xffffffff);
3051 gfar_write(&regs->igaddr7, 0xffffffff);
1da177e4
LT		 3052 gfar_write(&regs->gaddr0, 0xffffffff);
3053 gfar_write(&regs->gaddr1, 0xffffffff);
3054 gfar_write(&regs->gaddr2, 0xffffffff);
3055 gfar_write(&regs->gaddr3, 0xffffffff);
3056 gfar_write(&regs->gaddr4, 0xffffffff);
3057 gfar_write(&regs->gaddr5, 0xffffffff);
3058 gfar_write(&regs->gaddr6, 0xffffffff);
3059 gfar_write(&regs->gaddr7, 0xffffffff);
3060 } else {
7f7f5316
AF		 3061 int em_num;
3062 int idx;
3063
1da177e4 3064 /* zero out the hash */
0bbaf069
KG		 3065 gfar_write(&regs->igaddr0, 0x0);
3066 gfar_write(&regs->igaddr1, 0x0);
3067 gfar_write(&regs->igaddr2, 0x0);
3068 gfar_write(&regs->igaddr3, 0x0);
3069 gfar_write(&regs->igaddr4, 0x0);
3070 gfar_write(&regs->igaddr5, 0x0);
3071 gfar_write(&regs->igaddr6, 0x0);
3072 gfar_write(&regs->igaddr7, 0x0);
1da177e4
LT		 3073 gfar_write(&regs->gaddr0, 0x0);
3074 gfar_write(&regs->gaddr1, 0x0);
3075 gfar_write(&regs->gaddr2, 0x0);
3076 gfar_write(&regs->gaddr3, 0x0);
3077 gfar_write(&regs->gaddr4, 0x0);
3078 gfar_write(&regs->gaddr5, 0x0);
3079 gfar_write(&regs->gaddr6, 0x0);
3080 gfar_write(&regs->gaddr7, 0x0);
3081
7f7f5316
AF		 3082 /* If we have extended hash tables, we need to
3083 * clear the exact match registers to prepare for
3084 * setting them */
3085 if (priv->extended_hash) {
3086 em_num = GFAR_EM_NUM + 1;
3087 gfar_clear_exact_match(dev);
3088 idx = 1;
3089 } else {
3090 idx = 0;
3091 em_num = 0;
3092 }
3093
4cd24eaf 3094 if (netdev_mc_empty(dev))
1da177e4
LT		 3095 return;
3096
3097 /* Parse the list, and set the appropriate bits */
22bedad3 3098 netdev_for_each_mc_addr(ha, dev) {
7f7f5316 3099 if (idx < em_num) {
22bedad3 3100 gfar_set_mac_for_addr(dev, idx, ha->addr);
7f7f5316
AF		 3101 idx++;
3102 } else
22bedad3 3103 gfar_set_hash_for_addr(dev, ha->addr);
1da177e4
LT		 3104 }
3105 }
1da177e4
LT		 3106}
3107
7f7f5316
AF		 3108
3109/* Clears each of the exact match registers to zero, so they
3110 * don't interfere with normal reception */
3111static void gfar_clear_exact_match(struct net_device *dev)
3112{
3113 int idx;
6a3c910c 3114 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
7f7f5316
AF		 3115
3116 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
b6bc7650 3117 gfar_set_mac_for_addr(dev, idx, zero_arr);
7f7f5316
AF		 3118}
3119
1da177e4
LT		 3120/* Set the appropriate hash bit for the given addr */
3121/* The algorithm works like so:
3122 * 1) Take the Destination Address (ie the multicast address), and
3123 * do a CRC on it (little endian), and reverse the bits of the
3124 * result.
3125 * 2) Use the 8 most significant bits as a hash into a 256-entry
3126 * table. The table is controlled through 8 32-bit registers:
3127 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3128 * gaddr7. This means that the 3 most significant bits in the
3129 * hash index which gaddr register to use, and the 5 other bits
3130 * indicate which bit (assuming an IBM numbering scheme, which
3131 * for PowerPC (tm) is usually the case) in the register holds
3132 * the entry. */
3133static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3134{
3135 u32 tempval;
3136 struct gfar_private *priv = netdev_priv(dev);
6a3c910c 3137 u32 result = ether_crc(ETH_ALEN, addr);
0bbaf069
KG		 3138 int width = priv->hash_width;
3139 u8 whichbit = (result >> (32 - width)) & 0x1f;
3140 u8 whichreg = result >> (32 - width + 5);
1da177e4
LT		 3141 u32 value = (1 << (31-whichbit));
3142
0bbaf069 3143 tempval = gfar_read(priv->hash_regs[whichreg]);
1da177e4 3144 tempval |= value;
0bbaf069 3145 gfar_write(priv->hash_regs[whichreg], tempval);
1da177e4
LT		 3146}
3147
7f7f5316
AF		 3148
3149/* There are multiple MAC Address register pairs on some controllers
3150 * This function sets the numth pair to a given address
3151 */
b6bc7650
JP		 3152static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3153 const u8 *addr)
7f7f5316
AF		 3154{
3155 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 3156 struct gfar __iomem *regs = priv->gfargrp[0].regs;
7f7f5316 3157 int idx;
6a3c910c 3158 char tmpbuf[ETH_ALEN];
7f7f5316 3159 u32 tempval;
f4983704 3160 u32 __iomem *macptr = &regs->macstnaddr1;
7f7f5316
AF		 3161
3162 macptr += num*2;
3163
3164 /* Now copy it into the mac registers backwards, cuz */
3165 /* little endian is silly */
6a3c910c
JP		 3166 for (idx = 0; idx < ETH_ALEN; idx++)
3167 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
7f7f5316
AF		 3168
3169 gfar_write(macptr, *((u32 *) (tmpbuf)));
3170
3171 tempval = *((u32 *) (tmpbuf + 4));
3172
3173 gfar_write(macptr+1, tempval);
3174}
3175
1da177e4 3176/* GFAR error interrupt handler */
f4983704 3177static irqreturn_t gfar_error(int irq, void *grp_id)
1da177e4 3178{
f4983704
SG		 3179 struct gfar_priv_grp *gfargrp = grp_id;
3180 struct gfar __iomem *regs = gfargrp->regs;
3181 struct gfar_private *priv= gfargrp->priv;
3182 struct net_device *dev = priv->ndev;
1da177e4
LT		 3183
3184 /* Save ievent for future reference */
f4983704 3185 u32 events = gfar_read(&regs->ievent);
1da177e4
LT		 3186
3187 /* Clear IEVENT */
f4983704 3188 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
d87eb127
SW		 3189
3190 /* Magic Packet is not an error. */
b31a1d8b 3191 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 3192 (events & IEVENT_MAG))
3193 events &= ~IEVENT_MAG;
1da177e4
LT		 3194
3195 /* Hmm... */
0bbaf069 3196 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
59deab26
JP		 3197 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3198 events, gfar_read(&regs->imask));
1da177e4
LT		 3199
3200 /* Update the error counters */
3201 if (events & IEVENT_TXE) {
09f75cd7 3202 dev->stats.tx_errors++;
1da177e4
LT		 3203
3204 if (events & IEVENT_LC)
09f75cd7 3205 dev->stats.tx_window_errors++;
1da177e4 3206 if (events & IEVENT_CRL)
09f75cd7 3207 dev->stats.tx_aborted_errors++;
1da177e4 3208 if (events & IEVENT_XFUN) {
836cf7fa
AV		 3209 unsigned long flags;
3210
59deab26
JP		 3211 netif_dbg(priv, tx_err, dev,
3212 "TX FIFO underrun, packet dropped\n");
09f75cd7 3213 dev->stats.tx_dropped++;
1da177e4
LT		 3214 priv->extra_stats.tx_underrun++;
3215
836cf7fa
AV		 3216 local_irq_save(flags);
3217 lock_tx_qs(priv);
3218
1da177e4 3219 /* Reactivate the Tx Queues */
fba4ed03 3220 gfar_write(&regs->tstat, gfargrp->tstat);
836cf7fa
AV		 3221
3222 unlock_tx_qs(priv);
3223 local_irq_restore(flags);
1da177e4 3224 }
59deab26 3225 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
1da177e4
LT		 3226 }
3227 if (events & IEVENT_BSY) {
09f75cd7 3228 dev->stats.rx_errors++;
1da177e4
LT		 3229 priv->extra_stats.rx_bsy++;
3230
f4983704 3231 gfar_receive(irq, grp_id);
1da177e4 3232
59deab26
JP		 3233 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3234 gfar_read(&regs->rstat));
1da177e4
LT		 3235 }
3236 if (events & IEVENT_BABR) {
09f75cd7 3237 dev->stats.rx_errors++;
1da177e4
LT		 3238 priv->extra_stats.rx_babr++;
3239
59deab26 3240 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
1da177e4
LT		 3241 }
3242 if (events & IEVENT_EBERR) {
3243 priv->extra_stats.eberr++;
59deab26 3244 netif_dbg(priv, rx_err, dev, "bus error\n");
1da177e4 3245 }
59deab26
JP		 3246 if (events & IEVENT_RXC)
3247 netif_dbg(priv, rx_status, dev, "control frame\n");
1da177e4
LT		 3248
3249 if (events & IEVENT_BABT) {
3250 priv->extra_stats.tx_babt++;
59deab26 3251 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
1da177e4
LT		 3252 }
3253 return IRQ_HANDLED;
3254}
3255
b31a1d8b
AF		 3256static struct of_device_id gfar_match[] =
3257{
3258 {
3259 .type = "network",
3260 .compatible = "gianfar",
3261 },
46ceb60c
SG		 3262 {
3263 .compatible = "fsl,etsec2",
3264 },
b31a1d8b
AF		 3265 {},
3266};
e72701ac 3267MODULE_DEVICE_TABLE(of, gfar_match);
b31a1d8b 3268
1da177e4 3269/* Structure for a device driver */
74888760 3270static struct platform_driver gfar_driver = {
4018294b
GL		 3271 .driver = {
3272 .name = "fsl-gianfar",
3273 .owner = THIS_MODULE,
3274 .pm = GFAR_PM_OPS,
3275 .of_match_table = gfar_match,
3276 },
1da177e4
LT		 3277 .probe = gfar_probe,
3278 .remove = gfar_remove,
3279};
3280
db62f684 3281module_platform_driver(gfar_driver);
Linux kernel - Deliverables
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