Commit | Line | Data |
---|---|---|
0977f817 | 1 | /* drivers/net/ethernet/freescale/gianfar.c |
1da177e4 LT |
2 | * |
3 | * Gianfar Ethernet Driver | |
7f7f5316 AF |
4 | * This driver is designed for the non-CPM ethernet controllers |
5 | * on the 85xx and 83xx family of integrated processors | |
1da177e4 LT |
6 | * Based on 8260_io/fcc_enet.c |
7 | * | |
8 | * Author: Andy Fleming | |
4c8d3d99 | 9 | * Maintainer: Kumar Gala |
a12f801d | 10 | * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> |
1da177e4 | 11 | * |
6c43e046 | 12 | * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. |
a12f801d | 13 | * Copyright 2007 MontaVista Software, Inc. |
1da177e4 LT |
14 | * |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * Gianfar: AKA Lambda Draconis, "Dragon" | |
21 | * RA 11 31 24.2 | |
22 | * Dec +69 19 52 | |
23 | * V 3.84 | |
24 | * B-V +1.62 | |
25 | * | |
26 | * Theory of operation | |
0bbaf069 | 27 | * |
b31a1d8b AF |
28 | * The driver is initialized through of_device. Configuration information |
29 | * is therefore conveyed through an OF-style device tree. | |
1da177e4 LT |
30 | * |
31 | * The Gianfar Ethernet Controller uses a ring of buffer | |
32 | * descriptors. The beginning is indicated by a register | |
0bbaf069 KG |
33 | * pointing to the physical address of the start of the ring. |
34 | * The end is determined by a "wrap" bit being set in the | |
1da177e4 LT |
35 | * last descriptor of the ring. |
36 | * | |
37 | * When a packet is received, the RXF bit in the | |
0bbaf069 | 38 | * IEVENT register is set, triggering an interrupt when the |
1da177e4 LT |
39 | * corresponding bit in the IMASK register is also set (if |
40 | * interrupt coalescing is active, then the interrupt may not | |
41 | * happen immediately, but will wait until either a set number | |
bb40dcbb | 42 | * of frames or amount of time have passed). In NAPI, the |
1da177e4 | 43 | * interrupt handler will signal there is work to be done, and |
0aa1538f | 44 | * exit. This method will start at the last known empty |
0bbaf069 | 45 | * descriptor, and process every subsequent descriptor until there |
1da177e4 LT |
46 | * are none left with data (NAPI will stop after a set number of |
47 | * packets to give time to other tasks, but will eventually | |
48 | * process all the packets). The data arrives inside a | |
49 | * pre-allocated skb, and so after the skb is passed up to the | |
50 | * stack, a new skb must be allocated, and the address field in | |
51 | * the buffer descriptor must be updated to indicate this new | |
52 | * skb. | |
53 | * | |
54 | * When the kernel requests that a packet be transmitted, the | |
55 | * driver starts where it left off last time, and points the | |
56 | * descriptor at the buffer which was passed in. The driver | |
57 | * then informs the DMA engine that there are packets ready to | |
58 | * be transmitted. Once the controller is finished transmitting | |
59 | * the packet, an interrupt may be triggered (under the same | |
60 | * conditions as for reception, but depending on the TXF bit). | |
61 | * The driver then cleans up the buffer. | |
62 | */ | |
63 | ||
59deab26 JP |
64 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
65 | #define DEBUG | |
66 | ||
1da177e4 | 67 | #include <linux/kernel.h> |
1da177e4 LT |
68 | #include <linux/string.h> |
69 | #include <linux/errno.h> | |
bb40dcbb | 70 | #include <linux/unistd.h> |
1da177e4 LT |
71 | #include <linux/slab.h> |
72 | #include <linux/interrupt.h> | |
73 | #include <linux/init.h> | |
74 | #include <linux/delay.h> | |
75 | #include <linux/netdevice.h> | |
76 | #include <linux/etherdevice.h> | |
77 | #include <linux/skbuff.h> | |
0bbaf069 | 78 | #include <linux/if_vlan.h> |
1da177e4 LT |
79 | #include <linux/spinlock.h> |
80 | #include <linux/mm.h> | |
5af50730 RH |
81 | #include <linux/of_address.h> |
82 | #include <linux/of_irq.h> | |
fe192a49 | 83 | #include <linux/of_mdio.h> |
b31a1d8b | 84 | #include <linux/of_platform.h> |
0bbaf069 KG |
85 | #include <linux/ip.h> |
86 | #include <linux/tcp.h> | |
87 | #include <linux/udp.h> | |
9c07b884 | 88 | #include <linux/in.h> |
cc772ab7 | 89 | #include <linux/net_tstamp.h> |
1da177e4 LT |
90 | |
91 | #include <asm/io.h> | |
7d350977 | 92 | #include <asm/reg.h> |
1da177e4 LT |
93 | #include <asm/irq.h> |
94 | #include <asm/uaccess.h> | |
95 | #include <linux/module.h> | |
1da177e4 LT |
96 | #include <linux/dma-mapping.h> |
97 | #include <linux/crc32.h> | |
bb40dcbb AF |
98 | #include <linux/mii.h> |
99 | #include <linux/phy.h> | |
b31a1d8b AF |
100 | #include <linux/phy_fixed.h> |
101 | #include <linux/of.h> | |
4b6ba8aa | 102 | #include <linux/of_net.h> |
1da177e4 LT |
103 | |
104 | #include "gianfar.h" | |
1da177e4 LT |
105 | |
106 | #define TX_TIMEOUT (1*HZ) | |
1da177e4 | 107 | |
7f7f5316 | 108 | const char gfar_driver_version[] = "1.3"; |
1da177e4 | 109 | |
1da177e4 LT |
110 | static int gfar_enet_open(struct net_device *dev); |
111 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
ab939905 | 112 | static void gfar_reset_task(struct work_struct *work); |
1da177e4 LT |
113 | static void gfar_timeout(struct net_device *dev); |
114 | static int gfar_close(struct net_device *dev); | |
815b97c6 | 115 | struct sk_buff *gfar_new_skb(struct net_device *dev); |
a12f801d | 116 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 117 | struct sk_buff *skb); |
1da177e4 LT |
118 | static int gfar_set_mac_address(struct net_device *dev); |
119 | static int gfar_change_mtu(struct net_device *dev, int new_mtu); | |
7d12e780 DH |
120 | static irqreturn_t gfar_error(int irq, void *dev_id); |
121 | static irqreturn_t gfar_transmit(int irq, void *dev_id); | |
122 | static irqreturn_t gfar_interrupt(int irq, void *dev_id); | |
1da177e4 LT |
123 | static void adjust_link(struct net_device *dev); |
124 | static void init_registers(struct net_device *dev); | |
125 | static int init_phy(struct net_device *dev); | |
74888760 | 126 | static int gfar_probe(struct platform_device *ofdev); |
2dc11581 | 127 | static int gfar_remove(struct platform_device *ofdev); |
bb40dcbb | 128 | static void free_skb_resources(struct gfar_private *priv); |
1da177e4 LT |
129 | static void gfar_set_multi(struct net_device *dev); |
130 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr); | |
d3c12873 | 131 | static void gfar_configure_serdes(struct net_device *dev); |
bea3348e | 132 | static int gfar_poll(struct napi_struct *napi, int budget); |
5eaedf31 | 133 | static int gfar_poll_sq(struct napi_struct *napi, int budget); |
f2d71c2d VW |
134 | #ifdef CONFIG_NET_POLL_CONTROLLER |
135 | static void gfar_netpoll(struct net_device *dev); | |
136 | #endif | |
a12f801d | 137 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit); |
c233cf40 | 138 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); |
61db26c6 CM |
139 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
140 | int amount_pull, struct napi_struct *napi); | |
7f7f5316 | 141 | void gfar_halt(struct net_device *dev); |
d87eb127 | 142 | static void gfar_halt_nodisable(struct net_device *dev); |
7f7f5316 AF |
143 | void gfar_start(struct net_device *dev); |
144 | static void gfar_clear_exact_match(struct net_device *dev); | |
b6bc7650 JP |
145 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
146 | const u8 *addr); | |
26ccfc37 | 147 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
1da177e4 | 148 | |
1da177e4 LT |
149 | MODULE_AUTHOR("Freescale Semiconductor, Inc"); |
150 | MODULE_DESCRIPTION("Gianfar Ethernet Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | ||
a12f801d | 153 | static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
8a102fe0 AV |
154 | dma_addr_t buf) |
155 | { | |
8a102fe0 AV |
156 | u32 lstatus; |
157 | ||
158 | bdp->bufPtr = buf; | |
159 | ||
160 | lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT); | |
a12f801d | 161 | if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1) |
8a102fe0 AV |
162 | lstatus |= BD_LFLAG(RXBD_WRAP); |
163 | ||
164 | eieio(); | |
165 | ||
166 | bdp->lstatus = lstatus; | |
167 | } | |
168 | ||
8728327e | 169 | static int gfar_init_bds(struct net_device *ndev) |
826aa4a0 | 170 | { |
8728327e | 171 | struct gfar_private *priv = netdev_priv(ndev); |
a12f801d SG |
172 | struct gfar_priv_tx_q *tx_queue = NULL; |
173 | struct gfar_priv_rx_q *rx_queue = NULL; | |
826aa4a0 AV |
174 | struct txbd8 *txbdp; |
175 | struct rxbd8 *rxbdp; | |
fba4ed03 | 176 | int i, j; |
a12f801d | 177 | |
fba4ed03 SG |
178 | for (i = 0; i < priv->num_tx_queues; i++) { |
179 | tx_queue = priv->tx_queue[i]; | |
180 | /* Initialize some variables in our dev structure */ | |
181 | tx_queue->num_txbdfree = tx_queue->tx_ring_size; | |
182 | tx_queue->dirty_tx = tx_queue->tx_bd_base; | |
183 | tx_queue->cur_tx = tx_queue->tx_bd_base; | |
184 | tx_queue->skb_curtx = 0; | |
185 | tx_queue->skb_dirtytx = 0; | |
186 | ||
187 | /* Initialize Transmit Descriptor Ring */ | |
188 | txbdp = tx_queue->tx_bd_base; | |
189 | for (j = 0; j < tx_queue->tx_ring_size; j++) { | |
190 | txbdp->lstatus = 0; | |
191 | txbdp->bufPtr = 0; | |
192 | txbdp++; | |
193 | } | |
8728327e | 194 | |
fba4ed03 SG |
195 | /* Set the last descriptor in the ring to indicate wrap */ |
196 | txbdp--; | |
197 | txbdp->status |= TXBD_WRAP; | |
8728327e AV |
198 | } |
199 | ||
fba4ed03 SG |
200 | for (i = 0; i < priv->num_rx_queues; i++) { |
201 | rx_queue = priv->rx_queue[i]; | |
202 | rx_queue->cur_rx = rx_queue->rx_bd_base; | |
203 | rx_queue->skb_currx = 0; | |
204 | rxbdp = rx_queue->rx_bd_base; | |
8728327e | 205 | |
fba4ed03 SG |
206 | for (j = 0; j < rx_queue->rx_ring_size; j++) { |
207 | struct sk_buff *skb = rx_queue->rx_skbuff[j]; | |
8728327e | 208 | |
fba4ed03 SG |
209 | if (skb) { |
210 | gfar_init_rxbdp(rx_queue, rxbdp, | |
211 | rxbdp->bufPtr); | |
212 | } else { | |
213 | skb = gfar_new_skb(ndev); | |
214 | if (!skb) { | |
59deab26 | 215 | netdev_err(ndev, "Can't allocate RX buffers\n"); |
1eb8f7a7 | 216 | return -ENOMEM; |
fba4ed03 SG |
217 | } |
218 | rx_queue->rx_skbuff[j] = skb; | |
219 | ||
220 | gfar_new_rxbdp(rx_queue, rxbdp, skb); | |
8728327e | 221 | } |
8728327e | 222 | |
fba4ed03 | 223 | rxbdp++; |
8728327e AV |
224 | } |
225 | ||
8728327e AV |
226 | } |
227 | ||
228 | return 0; | |
229 | } | |
230 | ||
231 | static int gfar_alloc_skb_resources(struct net_device *ndev) | |
232 | { | |
826aa4a0 | 233 | void *vaddr; |
fba4ed03 SG |
234 | dma_addr_t addr; |
235 | int i, j, k; | |
826aa4a0 | 236 | struct gfar_private *priv = netdev_priv(ndev); |
369ec162 | 237 | struct device *dev = priv->dev; |
a12f801d SG |
238 | struct gfar_priv_tx_q *tx_queue = NULL; |
239 | struct gfar_priv_rx_q *rx_queue = NULL; | |
240 | ||
fba4ed03 SG |
241 | priv->total_tx_ring_size = 0; |
242 | for (i = 0; i < priv->num_tx_queues; i++) | |
243 | priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size; | |
244 | ||
245 | priv->total_rx_ring_size = 0; | |
246 | for (i = 0; i < priv->num_rx_queues; i++) | |
247 | priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size; | |
826aa4a0 AV |
248 | |
249 | /* Allocate memory for the buffer descriptors */ | |
8728327e | 250 | vaddr = dma_alloc_coherent(dev, |
d0320f75 JP |
251 | (priv->total_tx_ring_size * |
252 | sizeof(struct txbd8)) + | |
253 | (priv->total_rx_ring_size * | |
254 | sizeof(struct rxbd8)), | |
255 | &addr, GFP_KERNEL); | |
256 | if (!vaddr) | |
826aa4a0 | 257 | return -ENOMEM; |
826aa4a0 | 258 | |
fba4ed03 SG |
259 | for (i = 0; i < priv->num_tx_queues; i++) { |
260 | tx_queue = priv->tx_queue[i]; | |
43d620c8 | 261 | tx_queue->tx_bd_base = vaddr; |
fba4ed03 SG |
262 | tx_queue->tx_bd_dma_base = addr; |
263 | tx_queue->dev = ndev; | |
264 | /* enet DMA only understands physical addresses */ | |
bc4598bc JC |
265 | addr += sizeof(struct txbd8) * tx_queue->tx_ring_size; |
266 | vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size; | |
fba4ed03 | 267 | } |
826aa4a0 | 268 | |
826aa4a0 | 269 | /* Start the rx descriptor ring where the tx ring leaves off */ |
fba4ed03 SG |
270 | for (i = 0; i < priv->num_rx_queues; i++) { |
271 | rx_queue = priv->rx_queue[i]; | |
43d620c8 | 272 | rx_queue->rx_bd_base = vaddr; |
fba4ed03 SG |
273 | rx_queue->rx_bd_dma_base = addr; |
274 | rx_queue->dev = ndev; | |
bc4598bc JC |
275 | addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; |
276 | vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size; | |
fba4ed03 | 277 | } |
826aa4a0 AV |
278 | |
279 | /* Setup the skbuff rings */ | |
fba4ed03 SG |
280 | for (i = 0; i < priv->num_tx_queues; i++) { |
281 | tx_queue = priv->tx_queue[i]; | |
14f8dc49 JP |
282 | tx_queue->tx_skbuff = |
283 | kmalloc_array(tx_queue->tx_ring_size, | |
284 | sizeof(*tx_queue->tx_skbuff), | |
285 | GFP_KERNEL); | |
286 | if (!tx_queue->tx_skbuff) | |
fba4ed03 | 287 | goto cleanup; |
826aa4a0 | 288 | |
fba4ed03 SG |
289 | for (k = 0; k < tx_queue->tx_ring_size; k++) |
290 | tx_queue->tx_skbuff[k] = NULL; | |
291 | } | |
826aa4a0 | 292 | |
fba4ed03 SG |
293 | for (i = 0; i < priv->num_rx_queues; i++) { |
294 | rx_queue = priv->rx_queue[i]; | |
14f8dc49 JP |
295 | rx_queue->rx_skbuff = |
296 | kmalloc_array(rx_queue->rx_ring_size, | |
297 | sizeof(*rx_queue->rx_skbuff), | |
298 | GFP_KERNEL); | |
299 | if (!rx_queue->rx_skbuff) | |
fba4ed03 | 300 | goto cleanup; |
fba4ed03 SG |
301 | |
302 | for (j = 0; j < rx_queue->rx_ring_size; j++) | |
303 | rx_queue->rx_skbuff[j] = NULL; | |
304 | } | |
826aa4a0 | 305 | |
8728327e AV |
306 | if (gfar_init_bds(ndev)) |
307 | goto cleanup; | |
826aa4a0 AV |
308 | |
309 | return 0; | |
310 | ||
311 | cleanup: | |
312 | free_skb_resources(priv); | |
313 | return -ENOMEM; | |
314 | } | |
315 | ||
fba4ed03 SG |
316 | static void gfar_init_tx_rx_base(struct gfar_private *priv) |
317 | { | |
46ceb60c | 318 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 319 | u32 __iomem *baddr; |
fba4ed03 SG |
320 | int i; |
321 | ||
322 | baddr = ®s->tbase0; | |
bc4598bc | 323 | for (i = 0; i < priv->num_tx_queues; i++) { |
fba4ed03 | 324 | gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base); |
bc4598bc | 325 | baddr += 2; |
fba4ed03 SG |
326 | } |
327 | ||
328 | baddr = ®s->rbase0; | |
bc4598bc | 329 | for (i = 0; i < priv->num_rx_queues; i++) { |
fba4ed03 | 330 | gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base); |
bc4598bc | 331 | baddr += 2; |
fba4ed03 SG |
332 | } |
333 | } | |
334 | ||
826aa4a0 AV |
335 | static void gfar_init_mac(struct net_device *ndev) |
336 | { | |
337 | struct gfar_private *priv = netdev_priv(ndev); | |
46ceb60c | 338 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
826aa4a0 AV |
339 | u32 rctrl = 0; |
340 | u32 tctrl = 0; | |
341 | u32 attrs = 0; | |
342 | ||
fba4ed03 SG |
343 | /* write the tx/rx base registers */ |
344 | gfar_init_tx_rx_base(priv); | |
32c513bc | 345 | |
826aa4a0 | 346 | /* Configure the coalescing support */ |
800c644b | 347 | gfar_configure_coalescing_all(priv); |
fba4ed03 | 348 | |
ba779711 CM |
349 | /* set this when rx hw offload (TOE) functions are being used */ |
350 | priv->uses_rxfcb = 0; | |
351 | ||
1ccb8389 | 352 | if (priv->rx_filer_enable) { |
fba4ed03 | 353 | rctrl |= RCTRL_FILREN; |
1ccb8389 SG |
354 | /* Program the RIR0 reg with the required distribution */ |
355 | gfar_write(®s->rir0, DEFAULT_RIR0); | |
356 | } | |
826aa4a0 | 357 | |
f5ae6279 CM |
358 | /* Restore PROMISC mode */ |
359 | if (ndev->flags & IFF_PROMISC) | |
360 | rctrl |= RCTRL_PROM; | |
361 | ||
ba779711 | 362 | if (ndev->features & NETIF_F_RXCSUM) { |
826aa4a0 | 363 | rctrl |= RCTRL_CHECKSUMMING; |
ba779711 CM |
364 | priv->uses_rxfcb = 1; |
365 | } | |
826aa4a0 AV |
366 | |
367 | if (priv->extended_hash) { | |
368 | rctrl |= RCTRL_EXTHASH; | |
369 | ||
370 | gfar_clear_exact_match(ndev); | |
371 | rctrl |= RCTRL_EMEN; | |
372 | } | |
373 | ||
374 | if (priv->padding) { | |
375 | rctrl &= ~RCTRL_PAL_MASK; | |
376 | rctrl |= RCTRL_PADDING(priv->padding); | |
377 | } | |
378 | ||
cc772ab7 MR |
379 | /* Insert receive time stamps into padding alignment bytes */ |
380 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) { | |
381 | rctrl &= ~RCTRL_PAL_MASK; | |
97553f7f | 382 | rctrl |= RCTRL_PADDING(8); |
cc772ab7 MR |
383 | priv->padding = 8; |
384 | } | |
385 | ||
97553f7f | 386 | /* Enable HW time stamping if requested from user space */ |
ba779711 | 387 | if (priv->hwts_rx_en) { |
97553f7f | 388 | rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; |
ba779711 CM |
389 | priv->uses_rxfcb = 1; |
390 | } | |
97553f7f | 391 | |
f646968f | 392 | if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX) { |
b852b720 | 393 | rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT; |
ba779711 CM |
394 | priv->uses_rxfcb = 1; |
395 | } | |
826aa4a0 AV |
396 | |
397 | /* Init rctrl based on our settings */ | |
398 | gfar_write(®s->rctrl, rctrl); | |
399 | ||
400 | if (ndev->features & NETIF_F_IP_CSUM) | |
401 | tctrl |= TCTRL_INIT_CSUM; | |
402 | ||
b98b8bab CM |
403 | if (priv->prio_sched_en) |
404 | tctrl |= TCTRL_TXSCHED_PRIO; | |
405 | else { | |
406 | tctrl |= TCTRL_TXSCHED_WRRS; | |
407 | gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT); | |
408 | gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT); | |
409 | } | |
fba4ed03 | 410 | |
826aa4a0 AV |
411 | gfar_write(®s->tctrl, tctrl); |
412 | ||
413 | /* Set the extraction length and index */ | |
414 | attrs = ATTRELI_EL(priv->rx_stash_size) | | |
415 | ATTRELI_EI(priv->rx_stash_index); | |
416 | ||
417 | gfar_write(®s->attreli, attrs); | |
418 | ||
419 | /* Start with defaults, and add stashing or locking | |
0977f817 JC |
420 | * depending on the approprate variables |
421 | */ | |
826aa4a0 AV |
422 | attrs = ATTR_INIT_SETTINGS; |
423 | ||
424 | if (priv->bd_stash_en) | |
425 | attrs |= ATTR_BDSTASH; | |
426 | ||
427 | if (priv->rx_stash_size != 0) | |
428 | attrs |= ATTR_BUFSTASH; | |
429 | ||
430 | gfar_write(®s->attr, attrs); | |
431 | ||
432 | gfar_write(®s->fifo_tx_thr, priv->fifo_threshold); | |
433 | gfar_write(®s->fifo_tx_starve, priv->fifo_starve); | |
434 | gfar_write(®s->fifo_tx_starve_shutoff, priv->fifo_starve_off); | |
435 | } | |
436 | ||
a7f38041 SG |
437 | static struct net_device_stats *gfar_get_stats(struct net_device *dev) |
438 | { | |
439 | struct gfar_private *priv = netdev_priv(dev); | |
a7f38041 SG |
440 | unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0; |
441 | unsigned long tx_packets = 0, tx_bytes = 0; | |
3a2e16c8 | 442 | int i; |
a7f38041 SG |
443 | |
444 | for (i = 0; i < priv->num_rx_queues; i++) { | |
445 | rx_packets += priv->rx_queue[i]->stats.rx_packets; | |
bc4598bc | 446 | rx_bytes += priv->rx_queue[i]->stats.rx_bytes; |
a7f38041 SG |
447 | rx_dropped += priv->rx_queue[i]->stats.rx_dropped; |
448 | } | |
449 | ||
450 | dev->stats.rx_packets = rx_packets; | |
bc4598bc | 451 | dev->stats.rx_bytes = rx_bytes; |
a7f38041 SG |
452 | dev->stats.rx_dropped = rx_dropped; |
453 | ||
454 | for (i = 0; i < priv->num_tx_queues; i++) { | |
1ac9ad13 ED |
455 | tx_bytes += priv->tx_queue[i]->stats.tx_bytes; |
456 | tx_packets += priv->tx_queue[i]->stats.tx_packets; | |
a7f38041 SG |
457 | } |
458 | ||
bc4598bc | 459 | dev->stats.tx_bytes = tx_bytes; |
a7f38041 SG |
460 | dev->stats.tx_packets = tx_packets; |
461 | ||
462 | return &dev->stats; | |
463 | } | |
464 | ||
26ccfc37 AF |
465 | static const struct net_device_ops gfar_netdev_ops = { |
466 | .ndo_open = gfar_enet_open, | |
467 | .ndo_start_xmit = gfar_start_xmit, | |
468 | .ndo_stop = gfar_close, | |
469 | .ndo_change_mtu = gfar_change_mtu, | |
8b3afe95 | 470 | .ndo_set_features = gfar_set_features, |
afc4b13d | 471 | .ndo_set_rx_mode = gfar_set_multi, |
26ccfc37 AF |
472 | .ndo_tx_timeout = gfar_timeout, |
473 | .ndo_do_ioctl = gfar_ioctl, | |
a7f38041 | 474 | .ndo_get_stats = gfar_get_stats, |
240c102d BH |
475 | .ndo_set_mac_address = eth_mac_addr, |
476 | .ndo_validate_addr = eth_validate_addr, | |
26ccfc37 AF |
477 | #ifdef CONFIG_NET_POLL_CONTROLLER |
478 | .ndo_poll_controller = gfar_netpoll, | |
479 | #endif | |
480 | }; | |
481 | ||
fba4ed03 SG |
482 | void lock_rx_qs(struct gfar_private *priv) |
483 | { | |
3a2e16c8 | 484 | int i; |
fba4ed03 SG |
485 | |
486 | for (i = 0; i < priv->num_rx_queues; i++) | |
487 | spin_lock(&priv->rx_queue[i]->rxlock); | |
488 | } | |
489 | ||
490 | void lock_tx_qs(struct gfar_private *priv) | |
491 | { | |
3a2e16c8 | 492 | int i; |
fba4ed03 SG |
493 | |
494 | for (i = 0; i < priv->num_tx_queues; i++) | |
495 | spin_lock(&priv->tx_queue[i]->txlock); | |
496 | } | |
497 | ||
498 | void unlock_rx_qs(struct gfar_private *priv) | |
499 | { | |
3a2e16c8 | 500 | int i; |
fba4ed03 SG |
501 | |
502 | for (i = 0; i < priv->num_rx_queues; i++) | |
503 | spin_unlock(&priv->rx_queue[i]->rxlock); | |
504 | } | |
505 | ||
506 | void unlock_tx_qs(struct gfar_private *priv) | |
507 | { | |
3a2e16c8 | 508 | int i; |
fba4ed03 SG |
509 | |
510 | for (i = 0; i < priv->num_tx_queues; i++) | |
511 | spin_unlock(&priv->tx_queue[i]->txlock); | |
512 | } | |
513 | ||
fba4ed03 SG |
514 | static void free_tx_pointers(struct gfar_private *priv) |
515 | { | |
3a2e16c8 | 516 | int i; |
fba4ed03 SG |
517 | |
518 | for (i = 0; i < priv->num_tx_queues; i++) | |
519 | kfree(priv->tx_queue[i]); | |
520 | } | |
521 | ||
522 | static void free_rx_pointers(struct gfar_private *priv) | |
523 | { | |
3a2e16c8 | 524 | int i; |
fba4ed03 SG |
525 | |
526 | for (i = 0; i < priv->num_rx_queues; i++) | |
527 | kfree(priv->rx_queue[i]); | |
528 | } | |
529 | ||
46ceb60c SG |
530 | static void unmap_group_regs(struct gfar_private *priv) |
531 | { | |
3a2e16c8 | 532 | int i; |
46ceb60c SG |
533 | |
534 | for (i = 0; i < MAXGROUPS; i++) | |
535 | if (priv->gfargrp[i].regs) | |
536 | iounmap(priv->gfargrp[i].regs); | |
537 | } | |
538 | ||
ee873fda CM |
539 | static void free_gfar_dev(struct gfar_private *priv) |
540 | { | |
541 | int i, j; | |
542 | ||
543 | for (i = 0; i < priv->num_grps; i++) | |
544 | for (j = 0; j < GFAR_NUM_IRQS; j++) { | |
545 | kfree(priv->gfargrp[i].irqinfo[j]); | |
546 | priv->gfargrp[i].irqinfo[j] = NULL; | |
547 | } | |
548 | ||
549 | free_netdev(priv->ndev); | |
550 | } | |
551 | ||
46ceb60c SG |
552 | static void disable_napi(struct gfar_private *priv) |
553 | { | |
3a2e16c8 | 554 | int i; |
46ceb60c SG |
555 | |
556 | for (i = 0; i < priv->num_grps; i++) | |
557 | napi_disable(&priv->gfargrp[i].napi); | |
558 | } | |
559 | ||
560 | static void enable_napi(struct gfar_private *priv) | |
561 | { | |
3a2e16c8 | 562 | int i; |
46ceb60c SG |
563 | |
564 | for (i = 0; i < priv->num_grps; i++) | |
565 | napi_enable(&priv->gfargrp[i].napi); | |
566 | } | |
567 | ||
568 | static int gfar_parse_group(struct device_node *np, | |
bc4598bc | 569 | struct gfar_private *priv, const char *model) |
46ceb60c | 570 | { |
5fedcc14 | 571 | struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps]; |
46ceb60c | 572 | u32 *queue_mask; |
ee873fda CM |
573 | int i; |
574 | ||
7c1e7e99 PG |
575 | for (i = 0; i < GFAR_NUM_IRQS; i++) { |
576 | grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo), | |
577 | GFP_KERNEL); | |
578 | if (!grp->irqinfo[i]) | |
ee873fda | 579 | return -ENOMEM; |
ee873fda | 580 | } |
46ceb60c | 581 | |
5fedcc14 CM |
582 | grp->regs = of_iomap(np, 0); |
583 | if (!grp->regs) | |
46ceb60c SG |
584 | return -ENOMEM; |
585 | ||
ee873fda | 586 | gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0); |
46ceb60c SG |
587 | |
588 | /* If we aren't the FEC we have multiple interrupts */ | |
589 | if (model && strcasecmp(model, "FEC")) { | |
ee873fda CM |
590 | gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1); |
591 | gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2); | |
592 | if (gfar_irq(grp, TX)->irq == NO_IRQ || | |
593 | gfar_irq(grp, RX)->irq == NO_IRQ || | |
594 | gfar_irq(grp, ER)->irq == NO_IRQ) | |
46ceb60c | 595 | return -EINVAL; |
46ceb60c SG |
596 | } |
597 | ||
5fedcc14 CM |
598 | grp->priv = priv; |
599 | spin_lock_init(&grp->grplock); | |
bc4598bc JC |
600 | if (priv->mode == MQ_MG_MODE) { |
601 | queue_mask = (u32 *)of_get_property(np, "fsl,rx-bit-map", NULL); | |
5fedcc14 | 602 | grp->rx_bit_map = queue_mask ? |
bc4598bc JC |
603 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
604 | queue_mask = (u32 *)of_get_property(np, "fsl,tx-bit-map", NULL); | |
5fedcc14 | 605 | grp->tx_bit_map = queue_mask ? |
bc4598bc | 606 | *queue_mask : (DEFAULT_MAPPING >> priv->num_grps); |
46ceb60c | 607 | } else { |
5fedcc14 CM |
608 | grp->rx_bit_map = 0xFF; |
609 | grp->tx_bit_map = 0xFF; | |
46ceb60c SG |
610 | } |
611 | priv->num_grps++; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
2dc11581 | 616 | static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev) |
b31a1d8b | 617 | { |
b31a1d8b AF |
618 | const char *model; |
619 | const char *ctype; | |
620 | const void *mac_addr; | |
fba4ed03 SG |
621 | int err = 0, i; |
622 | struct net_device *dev = NULL; | |
623 | struct gfar_private *priv = NULL; | |
61c7a080 | 624 | struct device_node *np = ofdev->dev.of_node; |
46ceb60c | 625 | struct device_node *child = NULL; |
4d7902f2 AF |
626 | const u32 *stash; |
627 | const u32 *stash_len; | |
628 | const u32 *stash_idx; | |
fba4ed03 SG |
629 | unsigned int num_tx_qs, num_rx_qs; |
630 | u32 *tx_queues, *rx_queues; | |
b31a1d8b AF |
631 | |
632 | if (!np || !of_device_is_available(np)) | |
633 | return -ENODEV; | |
634 | ||
fba4ed03 SG |
635 | /* parse the num of tx and rx queues */ |
636 | tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL); | |
637 | num_tx_qs = tx_queues ? *tx_queues : 1; | |
638 | ||
639 | if (num_tx_qs > MAX_TX_QS) { | |
59deab26 JP |
640 | pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n", |
641 | num_tx_qs, MAX_TX_QS); | |
642 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
643 | return -EINVAL; |
644 | } | |
645 | ||
646 | rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL); | |
647 | num_rx_qs = rx_queues ? *rx_queues : 1; | |
648 | ||
649 | if (num_rx_qs > MAX_RX_QS) { | |
59deab26 JP |
650 | pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n", |
651 | num_rx_qs, MAX_RX_QS); | |
652 | pr_err("Cannot do alloc_etherdev, aborting\n"); | |
fba4ed03 SG |
653 | return -EINVAL; |
654 | } | |
655 | ||
656 | *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs); | |
657 | dev = *pdev; | |
658 | if (NULL == dev) | |
659 | return -ENOMEM; | |
660 | ||
661 | priv = netdev_priv(dev); | |
fba4ed03 SG |
662 | priv->ndev = dev; |
663 | ||
fba4ed03 | 664 | priv->num_tx_queues = num_tx_qs; |
fe069123 | 665 | netif_set_real_num_rx_queues(dev, num_rx_qs); |
fba4ed03 | 666 | priv->num_rx_queues = num_rx_qs; |
46ceb60c | 667 | priv->num_grps = 0x0; |
b31a1d8b | 668 | |
0977f817 | 669 | /* Init Rx queue filer rule set linked list */ |
4aa3a715 SP |
670 | INIT_LIST_HEAD(&priv->rx_list.list); |
671 | priv->rx_list.count = 0; | |
672 | mutex_init(&priv->rx_queue_access); | |
673 | ||
b31a1d8b AF |
674 | model = of_get_property(np, "model", NULL); |
675 | ||
46ceb60c SG |
676 | for (i = 0; i < MAXGROUPS; i++) |
677 | priv->gfargrp[i].regs = NULL; | |
b31a1d8b | 678 | |
46ceb60c SG |
679 | /* Parse and initialize group specific information */ |
680 | if (of_device_is_compatible(np, "fsl,etsec2")) { | |
681 | priv->mode = MQ_MG_MODE; | |
682 | for_each_child_of_node(np, child) { | |
683 | err = gfar_parse_group(child, priv, model); | |
684 | if (err) | |
685 | goto err_grp_init; | |
b31a1d8b | 686 | } |
46ceb60c SG |
687 | } else { |
688 | priv->mode = SQ_SG_MODE; | |
689 | err = gfar_parse_group(np, priv, model); | |
bc4598bc | 690 | if (err) |
46ceb60c | 691 | goto err_grp_init; |
b31a1d8b AF |
692 | } |
693 | ||
fba4ed03 | 694 | for (i = 0; i < priv->num_tx_queues; i++) |
c6e1160e | 695 | priv->tx_queue[i] = NULL; |
fba4ed03 SG |
696 | for (i = 0; i < priv->num_rx_queues; i++) |
697 | priv->rx_queue[i] = NULL; | |
698 | ||
699 | for (i = 0; i < priv->num_tx_queues; i++) { | |
de47f072 JP |
700 | priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q), |
701 | GFP_KERNEL); | |
fba4ed03 SG |
702 | if (!priv->tx_queue[i]) { |
703 | err = -ENOMEM; | |
704 | goto tx_alloc_failed; | |
705 | } | |
706 | priv->tx_queue[i]->tx_skbuff = NULL; | |
707 | priv->tx_queue[i]->qindex = i; | |
708 | priv->tx_queue[i]->dev = dev; | |
709 | spin_lock_init(&(priv->tx_queue[i]->txlock)); | |
710 | } | |
711 | ||
712 | for (i = 0; i < priv->num_rx_queues; i++) { | |
de47f072 JP |
713 | priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q), |
714 | GFP_KERNEL); | |
fba4ed03 SG |
715 | if (!priv->rx_queue[i]) { |
716 | err = -ENOMEM; | |
717 | goto rx_alloc_failed; | |
718 | } | |
719 | priv->rx_queue[i]->rx_skbuff = NULL; | |
720 | priv->rx_queue[i]->qindex = i; | |
721 | priv->rx_queue[i]->dev = dev; | |
722 | spin_lock_init(&(priv->rx_queue[i]->rxlock)); | |
723 | } | |
724 | ||
725 | ||
4d7902f2 AF |
726 | stash = of_get_property(np, "bd-stash", NULL); |
727 | ||
a12f801d | 728 | if (stash) { |
4d7902f2 AF |
729 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING; |
730 | priv->bd_stash_en = 1; | |
731 | } | |
732 | ||
733 | stash_len = of_get_property(np, "rx-stash-len", NULL); | |
734 | ||
735 | if (stash_len) | |
736 | priv->rx_stash_size = *stash_len; | |
737 | ||
738 | stash_idx = of_get_property(np, "rx-stash-idx", NULL); | |
739 | ||
740 | if (stash_idx) | |
741 | priv->rx_stash_index = *stash_idx; | |
742 | ||
743 | if (stash_len || stash_idx) | |
744 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING; | |
745 | ||
b31a1d8b | 746 | mac_addr = of_get_mac_address(np); |
bc4598bc | 747 | |
b31a1d8b | 748 | if (mac_addr) |
6a3c910c | 749 | memcpy(dev->dev_addr, mac_addr, ETH_ALEN); |
b31a1d8b AF |
750 | |
751 | if (model && !strcasecmp(model, "TSEC")) | |
bc4598bc JC |
752 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
753 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
754 | FSL_GIANFAR_DEV_HAS_RMON | | |
755 | FSL_GIANFAR_DEV_HAS_MULTI_INTR; | |
756 | ||
b31a1d8b | 757 | if (model && !strcasecmp(model, "eTSEC")) |
bc4598bc JC |
758 | priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | |
759 | FSL_GIANFAR_DEV_HAS_COALESCE | | |
760 | FSL_GIANFAR_DEV_HAS_RMON | | |
761 | FSL_GIANFAR_DEV_HAS_MULTI_INTR | | |
762 | FSL_GIANFAR_DEV_HAS_PADDING | | |
763 | FSL_GIANFAR_DEV_HAS_CSUM | | |
764 | FSL_GIANFAR_DEV_HAS_VLAN | | |
765 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | | |
766 | FSL_GIANFAR_DEV_HAS_EXTENDED_HASH | | |
767 | FSL_GIANFAR_DEV_HAS_TIMER; | |
b31a1d8b AF |
768 | |
769 | ctype = of_get_property(np, "phy-connection-type", NULL); | |
770 | ||
771 | /* We only care about rgmii-id. The rest are autodetected */ | |
772 | if (ctype && !strcmp(ctype, "rgmii-id")) | |
773 | priv->interface = PHY_INTERFACE_MODE_RGMII_ID; | |
774 | else | |
775 | priv->interface = PHY_INTERFACE_MODE_MII; | |
776 | ||
777 | if (of_get_property(np, "fsl,magic-packet", NULL)) | |
778 | priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET; | |
779 | ||
fe192a49 | 780 | priv->phy_node = of_parse_phandle(np, "phy-handle", 0); |
b31a1d8b AF |
781 | |
782 | /* Find the TBI PHY. If it's not there, we don't support SGMII */ | |
fe192a49 | 783 | priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0); |
b31a1d8b AF |
784 | |
785 | return 0; | |
786 | ||
fba4ed03 SG |
787 | rx_alloc_failed: |
788 | free_rx_pointers(priv); | |
789 | tx_alloc_failed: | |
790 | free_tx_pointers(priv); | |
46ceb60c SG |
791 | err_grp_init: |
792 | unmap_group_regs(priv); | |
ee873fda | 793 | free_gfar_dev(priv); |
b31a1d8b AF |
794 | return err; |
795 | } | |
796 | ||
cc772ab7 | 797 | static int gfar_hwtstamp_ioctl(struct net_device *netdev, |
bc4598bc | 798 | struct ifreq *ifr, int cmd) |
cc772ab7 MR |
799 | { |
800 | struct hwtstamp_config config; | |
801 | struct gfar_private *priv = netdev_priv(netdev); | |
802 | ||
803 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
804 | return -EFAULT; | |
805 | ||
806 | /* reserved for future extensions */ | |
807 | if (config.flags) | |
808 | return -EINVAL; | |
809 | ||
f0ee7acf MR |
810 | switch (config.tx_type) { |
811 | case HWTSTAMP_TX_OFF: | |
812 | priv->hwts_tx_en = 0; | |
813 | break; | |
814 | case HWTSTAMP_TX_ON: | |
815 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
816 | return -ERANGE; | |
817 | priv->hwts_tx_en = 1; | |
818 | break; | |
819 | default: | |
cc772ab7 | 820 | return -ERANGE; |
f0ee7acf | 821 | } |
cc772ab7 MR |
822 | |
823 | switch (config.rx_filter) { | |
824 | case HWTSTAMP_FILTER_NONE: | |
97553f7f MR |
825 | if (priv->hwts_rx_en) { |
826 | stop_gfar(netdev); | |
827 | priv->hwts_rx_en = 0; | |
828 | startup_gfar(netdev); | |
829 | } | |
cc772ab7 MR |
830 | break; |
831 | default: | |
832 | if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) | |
833 | return -ERANGE; | |
97553f7f MR |
834 | if (!priv->hwts_rx_en) { |
835 | stop_gfar(netdev); | |
836 | priv->hwts_rx_en = 1; | |
837 | startup_gfar(netdev); | |
838 | } | |
cc772ab7 MR |
839 | config.rx_filter = HWTSTAMP_FILTER_ALL; |
840 | break; | |
841 | } | |
842 | ||
843 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
844 | -EFAULT : 0; | |
845 | } | |
846 | ||
0faac9f7 CW |
847 | /* Ioctl MII Interface */ |
848 | static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
849 | { | |
850 | struct gfar_private *priv = netdev_priv(dev); | |
851 | ||
852 | if (!netif_running(dev)) | |
853 | return -EINVAL; | |
854 | ||
cc772ab7 MR |
855 | if (cmd == SIOCSHWTSTAMP) |
856 | return gfar_hwtstamp_ioctl(dev, rq, cmd); | |
857 | ||
0faac9f7 CW |
858 | if (!priv->phydev) |
859 | return -ENODEV; | |
860 | ||
28b04113 | 861 | return phy_mii_ioctl(priv->phydev, rq, cmd); |
0faac9f7 CW |
862 | } |
863 | ||
fba4ed03 SG |
864 | static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs) |
865 | { | |
866 | unsigned int new_bit_map = 0x0; | |
867 | int mask = 0x1 << (max_qs - 1), i; | |
bc4598bc | 868 | |
fba4ed03 SG |
869 | for (i = 0; i < max_qs; i++) { |
870 | if (bit_map & mask) | |
871 | new_bit_map = new_bit_map + (1 << i); | |
872 | mask = mask >> 0x1; | |
873 | } | |
874 | return new_bit_map; | |
875 | } | |
7a8b3372 | 876 | |
18294ad1 AV |
877 | static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, |
878 | u32 class) | |
7a8b3372 SG |
879 | { |
880 | u32 rqfpr = FPR_FILER_MASK; | |
881 | u32 rqfcr = 0x0; | |
882 | ||
883 | rqfar--; | |
884 | rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT; | |
6c43e046 WJB |
885 | priv->ftp_rqfpr[rqfar] = rqfpr; |
886 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
887 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
888 | ||
889 | rqfar--; | |
890 | rqfcr = RQFCR_CMP_NOMATCH; | |
6c43e046 WJB |
891 | priv->ftp_rqfpr[rqfar] = rqfpr; |
892 | priv->ftp_rqfcr[rqfar] = rqfcr; | |
7a8b3372 SG |
893 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
894 | ||
895 | rqfar--; | |
896 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND; | |
897 | rqfpr = class; | |
6c43e046 WJB |
898 | priv->ftp_rqfcr[rqfar] = rqfcr; |
899 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
900 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
901 | ||
902 | rqfar--; | |
903 | rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND; | |
904 | rqfpr = class; | |
6c43e046 WJB |
905 | priv->ftp_rqfcr[rqfar] = rqfcr; |
906 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
907 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
908 | ||
909 | return rqfar; | |
910 | } | |
911 | ||
912 | static void gfar_init_filer_table(struct gfar_private *priv) | |
913 | { | |
914 | int i = 0x0; | |
915 | u32 rqfar = MAX_FILER_IDX; | |
916 | u32 rqfcr = 0x0; | |
917 | u32 rqfpr = FPR_FILER_MASK; | |
918 | ||
919 | /* Default rule */ | |
920 | rqfcr = RQFCR_CMP_MATCH; | |
6c43e046 WJB |
921 | priv->ftp_rqfcr[rqfar] = rqfcr; |
922 | priv->ftp_rqfpr[rqfar] = rqfpr; | |
7a8b3372 SG |
923 | gfar_write_filer(priv, rqfar, rqfcr, rqfpr); |
924 | ||
925 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6); | |
926 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP); | |
927 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP); | |
928 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4); | |
929 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP); | |
930 | rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP); | |
931 | ||
85dd08eb | 932 | /* cur_filer_idx indicated the first non-masked rule */ |
7a8b3372 SG |
933 | priv->cur_filer_idx = rqfar; |
934 | ||
935 | /* Rest are masked rules */ | |
936 | rqfcr = RQFCR_CMP_NOMATCH; | |
937 | for (i = 0; i < rqfar; i++) { | |
6c43e046 WJB |
938 | priv->ftp_rqfcr[i] = rqfcr; |
939 | priv->ftp_rqfpr[i] = rqfpr; | |
7a8b3372 SG |
940 | gfar_write_filer(priv, i, rqfcr, rqfpr); |
941 | } | |
942 | } | |
943 | ||
7d350977 AV |
944 | static void gfar_detect_errata(struct gfar_private *priv) |
945 | { | |
946 | struct device *dev = &priv->ofdev->dev; | |
947 | unsigned int pvr = mfspr(SPRN_PVR); | |
948 | unsigned int svr = mfspr(SPRN_SVR); | |
949 | unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */ | |
950 | unsigned int rev = svr & 0xffff; | |
951 | ||
952 | /* MPC8313 Rev 2.0 and higher; All MPC837x */ | |
953 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) || | |
bc4598bc | 954 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
7d350977 AV |
955 | priv->errata |= GFAR_ERRATA_74; |
956 | ||
deb90eac AV |
957 | /* MPC8313 and MPC837x all rev */ |
958 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 959 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
deb90eac AV |
960 | priv->errata |= GFAR_ERRATA_76; |
961 | ||
511d934f AV |
962 | /* MPC8313 and MPC837x all rev */ |
963 | if ((pvr == 0x80850010 && mod == 0x80b0) || | |
bc4598bc | 964 | (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0)) |
511d934f AV |
965 | priv->errata |= GFAR_ERRATA_A002; |
966 | ||
4363c2fd AD |
967 | /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */ |
968 | if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) || | |
bc4598bc | 969 | (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)) |
4363c2fd AD |
970 | priv->errata |= GFAR_ERRATA_12; |
971 | ||
7d350977 AV |
972 | if (priv->errata) |
973 | dev_info(dev, "enabled errata workarounds, flags: 0x%x\n", | |
974 | priv->errata); | |
975 | } | |
976 | ||
bb40dcbb | 977 | /* Set up the ethernet device structure, private data, |
0977f817 JC |
978 | * and anything else we need before we start |
979 | */ | |
74888760 | 980 | static int gfar_probe(struct platform_device *ofdev) |
1da177e4 LT |
981 | { |
982 | u32 tempval; | |
983 | struct net_device *dev = NULL; | |
984 | struct gfar_private *priv = NULL; | |
f4983704 | 985 | struct gfar __iomem *regs = NULL; |
46ceb60c | 986 | int err = 0, i, grp_idx = 0; |
fba4ed03 | 987 | u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0; |
46ceb60c | 988 | u32 isrg = 0; |
18294ad1 | 989 | u32 __iomem *baddr; |
1da177e4 | 990 | |
fba4ed03 | 991 | err = gfar_of_init(ofdev, &dev); |
1da177e4 | 992 | |
fba4ed03 SG |
993 | if (err) |
994 | return err; | |
1da177e4 LT |
995 | |
996 | priv = netdev_priv(dev); | |
4826857f KG |
997 | priv->ndev = dev; |
998 | priv->ofdev = ofdev; | |
369ec162 | 999 | priv->dev = &ofdev->dev; |
4826857f | 1000 | SET_NETDEV_DEV(dev, &ofdev->dev); |
1da177e4 | 1001 | |
d87eb127 | 1002 | spin_lock_init(&priv->bflock); |
ab939905 | 1003 | INIT_WORK(&priv->reset_task, gfar_reset_task); |
1da177e4 | 1004 | |
8513fbd8 | 1005 | platform_set_drvdata(ofdev, priv); |
46ceb60c | 1006 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1007 | |
7d350977 AV |
1008 | gfar_detect_errata(priv); |
1009 | ||
0977f817 JC |
1010 | /* Stop the DMA engine now, in case it was running before |
1011 | * (The firmware could have used it, and left it running). | |
1012 | */ | |
257d938a | 1013 | gfar_halt(dev); |
1da177e4 LT |
1014 | |
1015 | /* Reset MAC layer */ | |
f4983704 | 1016 | gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET); |
1da177e4 | 1017 | |
b98ac702 AF |
1018 | /* We need to delay at least 3 TX clocks */ |
1019 | udelay(2); | |
1020 | ||
23402bdd CM |
1021 | tempval = 0; |
1022 | if (!priv->pause_aneg_en && priv->tx_pause_en) | |
1023 | tempval |= MACCFG1_TX_FLOW; | |
1024 | if (!priv->pause_aneg_en && priv->rx_pause_en) | |
1025 | tempval |= MACCFG1_RX_FLOW; | |
1026 | /* the soft reset bit is not self-resetting, so we need to | |
1027 | * clear it before resuming normal operation | |
1028 | */ | |
f4983704 | 1029 | gfar_write(®s->maccfg1, tempval); |
1da177e4 LT |
1030 | |
1031 | /* Initialize MACCFG2. */ | |
7d350977 AV |
1032 | tempval = MACCFG2_INIT_SETTINGS; |
1033 | if (gfar_has_errata(priv, GFAR_ERRATA_74)) | |
1034 | tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK; | |
1035 | gfar_write(®s->maccfg2, tempval); | |
1da177e4 LT |
1036 | |
1037 | /* Initialize ECNTRL */ | |
f4983704 | 1038 | gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS); |
1da177e4 | 1039 | |
1da177e4 | 1040 | /* Set the dev->base_addr to the gfar reg region */ |
f4983704 | 1041 | dev->base_addr = (unsigned long) regs; |
1da177e4 | 1042 | |
1da177e4 | 1043 | /* Fill in the dev structure */ |
1da177e4 | 1044 | dev->watchdog_timeo = TX_TIMEOUT; |
1da177e4 | 1045 | dev->mtu = 1500; |
26ccfc37 | 1046 | dev->netdev_ops = &gfar_netdev_ops; |
0bbaf069 KG |
1047 | dev->ethtool_ops = &gfar_ethtool_ops; |
1048 | ||
fba4ed03 | 1049 | /* Register for napi ...We are registering NAPI for each grp */ |
5eaedf31 CM |
1050 | if (priv->mode == SQ_SG_MODE) |
1051 | netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, | |
bc4598bc | 1052 | GFAR_DEV_WEIGHT); |
5eaedf31 CM |
1053 | else |
1054 | for (i = 0; i < priv->num_grps; i++) | |
1055 | netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, | |
1056 | GFAR_DEV_WEIGHT); | |
a12f801d | 1057 | |
b31a1d8b | 1058 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { |
8b3afe95 | 1059 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1060 | NETIF_F_RXCSUM; |
8b3afe95 | 1061 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
bc4598bc | 1062 | NETIF_F_RXCSUM | NETIF_F_HIGHDMA; |
8b3afe95 | 1063 | } |
0bbaf069 | 1064 | |
87c288c6 | 1065 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { |
f646968f PM |
1066 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | |
1067 | NETIF_F_HW_VLAN_CTAG_RX; | |
1068 | dev->features |= NETIF_F_HW_VLAN_CTAG_RX; | |
87c288c6 | 1069 | } |
0bbaf069 | 1070 | |
b31a1d8b | 1071 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { |
0bbaf069 KG |
1072 | priv->extended_hash = 1; |
1073 | priv->hash_width = 9; | |
1074 | ||
f4983704 SG |
1075 | priv->hash_regs[0] = ®s->igaddr0; |
1076 | priv->hash_regs[1] = ®s->igaddr1; | |
1077 | priv->hash_regs[2] = ®s->igaddr2; | |
1078 | priv->hash_regs[3] = ®s->igaddr3; | |
1079 | priv->hash_regs[4] = ®s->igaddr4; | |
1080 | priv->hash_regs[5] = ®s->igaddr5; | |
1081 | priv->hash_regs[6] = ®s->igaddr6; | |
1082 | priv->hash_regs[7] = ®s->igaddr7; | |
1083 | priv->hash_regs[8] = ®s->gaddr0; | |
1084 | priv->hash_regs[9] = ®s->gaddr1; | |
1085 | priv->hash_regs[10] = ®s->gaddr2; | |
1086 | priv->hash_regs[11] = ®s->gaddr3; | |
1087 | priv->hash_regs[12] = ®s->gaddr4; | |
1088 | priv->hash_regs[13] = ®s->gaddr5; | |
1089 | priv->hash_regs[14] = ®s->gaddr6; | |
1090 | priv->hash_regs[15] = ®s->gaddr7; | |
0bbaf069 KG |
1091 | |
1092 | } else { | |
1093 | priv->extended_hash = 0; | |
1094 | priv->hash_width = 8; | |
1095 | ||
f4983704 SG |
1096 | priv->hash_regs[0] = ®s->gaddr0; |
1097 | priv->hash_regs[1] = ®s->gaddr1; | |
1098 | priv->hash_regs[2] = ®s->gaddr2; | |
1099 | priv->hash_regs[3] = ®s->gaddr3; | |
1100 | priv->hash_regs[4] = ®s->gaddr4; | |
1101 | priv->hash_regs[5] = ®s->gaddr5; | |
1102 | priv->hash_regs[6] = ®s->gaddr6; | |
1103 | priv->hash_regs[7] = ®s->gaddr7; | |
0bbaf069 KG |
1104 | } |
1105 | ||
b31a1d8b | 1106 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) |
0bbaf069 KG |
1107 | priv->padding = DEFAULT_PADDING; |
1108 | else | |
1109 | priv->padding = 0; | |
1110 | ||
cc772ab7 | 1111 | if (dev->features & NETIF_F_IP_CSUM || |
bc4598bc | 1112 | priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) |
bee9e58c | 1113 | dev->needed_headroom = GMAC_FCB_LEN; |
1da177e4 | 1114 | |
46ceb60c SG |
1115 | /* Program the isrg regs only if number of grps > 1 */ |
1116 | if (priv->num_grps > 1) { | |
1117 | baddr = ®s->isrg0; | |
1118 | for (i = 0; i < priv->num_grps; i++) { | |
1119 | isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX); | |
1120 | isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX); | |
1121 | gfar_write(baddr, isrg); | |
1122 | baddr++; | |
1123 | isrg = 0x0; | |
1124 | } | |
1125 | } | |
1126 | ||
fba4ed03 | 1127 | /* Need to reverse the bit maps as bit_map's MSB is q0 |
984b3f57 | 1128 | * but, for_each_set_bit parses from right to left, which |
0977f817 JC |
1129 | * basically reverses the queue numbers |
1130 | */ | |
46ceb60c | 1131 | for (i = 0; i< priv->num_grps; i++) { |
bc4598bc JC |
1132 | priv->gfargrp[i].tx_bit_map = |
1133 | reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); | |
1134 | priv->gfargrp[i].rx_bit_map = | |
1135 | reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); | |
46ceb60c SG |
1136 | } |
1137 | ||
1138 | /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, | |
0977f817 JC |
1139 | * also assign queues to groups |
1140 | */ | |
46ceb60c SG |
1141 | for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { |
1142 | priv->gfargrp[grp_idx].num_rx_queues = 0x0; | |
bc4598bc | 1143 | |
984b3f57 | 1144 | for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map, |
bc4598bc | 1145 | priv->num_rx_queues) { |
46ceb60c SG |
1146 | priv->gfargrp[grp_idx].num_rx_queues++; |
1147 | priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1148 | rstat = rstat | (RSTAT_CLEAR_RHALT >> i); | |
1149 | rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i); | |
1150 | } | |
1151 | priv->gfargrp[grp_idx].num_tx_queues = 0x0; | |
bc4598bc | 1152 | |
984b3f57 | 1153 | for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map, |
bc4598bc | 1154 | priv->num_tx_queues) { |
46ceb60c SG |
1155 | priv->gfargrp[grp_idx].num_tx_queues++; |
1156 | priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx]; | |
1157 | tstat = tstat | (TSTAT_CLEAR_THALT >> i); | |
1158 | tqueue = tqueue | (TQUEUE_EN0 >> i); | |
1159 | } | |
1160 | priv->gfargrp[grp_idx].rstat = rstat; | |
1161 | priv->gfargrp[grp_idx].tstat = tstat; | |
1162 | rstat = tstat =0; | |
fba4ed03 | 1163 | } |
fba4ed03 SG |
1164 | |
1165 | gfar_write(®s->rqueue, rqueue); | |
1166 | gfar_write(®s->tqueue, tqueue); | |
1167 | ||
1da177e4 | 1168 | priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; |
1da177e4 | 1169 | |
a12f801d | 1170 | /* Initializing some of the rx/tx queue level parameters */ |
fba4ed03 SG |
1171 | for (i = 0; i < priv->num_tx_queues; i++) { |
1172 | priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE; | |
1173 | priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE; | |
1174 | priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE; | |
1175 | priv->tx_queue[i]->txic = DEFAULT_TXIC; | |
1176 | } | |
a12f801d | 1177 | |
fba4ed03 SG |
1178 | for (i = 0; i < priv->num_rx_queues; i++) { |
1179 | priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE; | |
1180 | priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE; | |
1181 | priv->rx_queue[i]->rxic = DEFAULT_RXIC; | |
1182 | } | |
1da177e4 | 1183 | |
0977f817 | 1184 | /* always enable rx filer */ |
4aa3a715 | 1185 | priv->rx_filer_enable = 1; |
0bbaf069 KG |
1186 | /* Enable most messages by default */ |
1187 | priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
b98b8bab CM |
1188 | /* use pritority h/w tx queue scheduling for single queue devices */ |
1189 | if (priv->num_tx_queues == 1) | |
1190 | priv->prio_sched_en = 1; | |
0bbaf069 | 1191 | |
d3eab82b TP |
1192 | /* Carrier starts down, phylib will bring it up */ |
1193 | netif_carrier_off(dev); | |
1194 | ||
1da177e4 LT |
1195 | err = register_netdev(dev); |
1196 | ||
1197 | if (err) { | |
59deab26 | 1198 | pr_err("%s: Cannot register net device, aborting\n", dev->name); |
1da177e4 LT |
1199 | goto register_fail; |
1200 | } | |
1201 | ||
2884e5cc | 1202 | device_init_wakeup(&dev->dev, |
bc4598bc JC |
1203 | priv->device_flags & |
1204 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
2884e5cc | 1205 | |
c50a5d9a | 1206 | /* fill out IRQ number and name fields */ |
46ceb60c | 1207 | for (i = 0; i < priv->num_grps; i++) { |
ee873fda | 1208 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
46ceb60c | 1209 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
ee873fda | 1210 | sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s", |
0015e551 | 1211 | dev->name, "_g", '0' + i, "_tx"); |
ee873fda | 1212 | sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s", |
0015e551 | 1213 | dev->name, "_g", '0' + i, "_rx"); |
ee873fda | 1214 | sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s", |
0015e551 | 1215 | dev->name, "_g", '0' + i, "_er"); |
46ceb60c | 1216 | } else |
ee873fda | 1217 | strcpy(gfar_irq(grp, TX)->name, dev->name); |
46ceb60c | 1218 | } |
c50a5d9a | 1219 | |
7a8b3372 SG |
1220 | /* Initialize the filer table */ |
1221 | gfar_init_filer_table(priv); | |
1222 | ||
7f7f5316 AF |
1223 | /* Create all the sysfs files */ |
1224 | gfar_init_sysfs(dev); | |
1225 | ||
1da177e4 | 1226 | /* Print out the device info */ |
59deab26 | 1227 | netdev_info(dev, "mac: %pM\n", dev->dev_addr); |
1da177e4 | 1228 | |
0977f817 JC |
1229 | /* Even more device info helps when determining which kernel |
1230 | * provided which set of benchmarks. | |
1231 | */ | |
59deab26 | 1232 | netdev_info(dev, "Running with NAPI enabled\n"); |
fba4ed03 | 1233 | for (i = 0; i < priv->num_rx_queues; i++) |
59deab26 JP |
1234 | netdev_info(dev, "RX BD ring size for Q[%d]: %d\n", |
1235 | i, priv->rx_queue[i]->rx_ring_size); | |
bc4598bc | 1236 | for (i = 0; i < priv->num_tx_queues; i++) |
59deab26 JP |
1237 | netdev_info(dev, "TX BD ring size for Q[%d]: %d\n", |
1238 | i, priv->tx_queue[i]->tx_ring_size); | |
1da177e4 LT |
1239 | |
1240 | return 0; | |
1241 | ||
1242 | register_fail: | |
46ceb60c | 1243 | unmap_group_regs(priv); |
fba4ed03 SG |
1244 | free_tx_pointers(priv); |
1245 | free_rx_pointers(priv); | |
fe192a49 GL |
1246 | if (priv->phy_node) |
1247 | of_node_put(priv->phy_node); | |
1248 | if (priv->tbi_node) | |
1249 | of_node_put(priv->tbi_node); | |
ee873fda | 1250 | free_gfar_dev(priv); |
bb40dcbb | 1251 | return err; |
1da177e4 LT |
1252 | } |
1253 | ||
2dc11581 | 1254 | static int gfar_remove(struct platform_device *ofdev) |
1da177e4 | 1255 | { |
8513fbd8 | 1256 | struct gfar_private *priv = platform_get_drvdata(ofdev); |
1da177e4 | 1257 | |
fe192a49 GL |
1258 | if (priv->phy_node) |
1259 | of_node_put(priv->phy_node); | |
1260 | if (priv->tbi_node) | |
1261 | of_node_put(priv->tbi_node); | |
1262 | ||
d9d8e041 | 1263 | unregister_netdev(priv->ndev); |
46ceb60c | 1264 | unmap_group_regs(priv); |
ee873fda | 1265 | free_gfar_dev(priv); |
1da177e4 LT |
1266 | |
1267 | return 0; | |
1268 | } | |
1269 | ||
d87eb127 | 1270 | #ifdef CONFIG_PM |
be926fc4 AV |
1271 | |
1272 | static int gfar_suspend(struct device *dev) | |
d87eb127 | 1273 | { |
be926fc4 AV |
1274 | struct gfar_private *priv = dev_get_drvdata(dev); |
1275 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1276 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1277 | unsigned long flags; |
1278 | u32 tempval; | |
1279 | ||
1280 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1281 | (priv->device_flags & |
1282 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1283 | |
be926fc4 | 1284 | netif_device_detach(ndev); |
d87eb127 | 1285 | |
be926fc4 | 1286 | if (netif_running(ndev)) { |
fba4ed03 SG |
1287 | |
1288 | local_irq_save(flags); | |
1289 | lock_tx_qs(priv); | |
1290 | lock_rx_qs(priv); | |
d87eb127 | 1291 | |
be926fc4 | 1292 | gfar_halt_nodisable(ndev); |
d87eb127 SW |
1293 | |
1294 | /* Disable Tx, and Rx if wake-on-LAN is disabled. */ | |
f4983704 | 1295 | tempval = gfar_read(®s->maccfg1); |
d87eb127 SW |
1296 | |
1297 | tempval &= ~MACCFG1_TX_EN; | |
1298 | ||
1299 | if (!magic_packet) | |
1300 | tempval &= ~MACCFG1_RX_EN; | |
1301 | ||
f4983704 | 1302 | gfar_write(®s->maccfg1, tempval); |
d87eb127 | 1303 | |
fba4ed03 SG |
1304 | unlock_rx_qs(priv); |
1305 | unlock_tx_qs(priv); | |
1306 | local_irq_restore(flags); | |
d87eb127 | 1307 | |
46ceb60c | 1308 | disable_napi(priv); |
d87eb127 SW |
1309 | |
1310 | if (magic_packet) { | |
1311 | /* Enable interrupt on Magic Packet */ | |
f4983704 | 1312 | gfar_write(®s->imask, IMASK_MAG); |
d87eb127 SW |
1313 | |
1314 | /* Enable Magic Packet mode */ | |
f4983704 | 1315 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1316 | tempval |= MACCFG2_MPEN; |
f4983704 | 1317 | gfar_write(®s->maccfg2, tempval); |
d87eb127 SW |
1318 | } else { |
1319 | phy_stop(priv->phydev); | |
1320 | } | |
1321 | } | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
be926fc4 | 1326 | static int gfar_resume(struct device *dev) |
d87eb127 | 1327 | { |
be926fc4 AV |
1328 | struct gfar_private *priv = dev_get_drvdata(dev); |
1329 | struct net_device *ndev = priv->ndev; | |
46ceb60c | 1330 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 SW |
1331 | unsigned long flags; |
1332 | u32 tempval; | |
1333 | int magic_packet = priv->wol_en && | |
bc4598bc JC |
1334 | (priv->device_flags & |
1335 | FSL_GIANFAR_DEV_HAS_MAGIC_PACKET); | |
d87eb127 | 1336 | |
be926fc4 AV |
1337 | if (!netif_running(ndev)) { |
1338 | netif_device_attach(ndev); | |
d87eb127 SW |
1339 | return 0; |
1340 | } | |
1341 | ||
1342 | if (!magic_packet && priv->phydev) | |
1343 | phy_start(priv->phydev); | |
1344 | ||
1345 | /* Disable Magic Packet mode, in case something | |
1346 | * else woke us up. | |
1347 | */ | |
fba4ed03 SG |
1348 | local_irq_save(flags); |
1349 | lock_tx_qs(priv); | |
1350 | lock_rx_qs(priv); | |
d87eb127 | 1351 | |
f4983704 | 1352 | tempval = gfar_read(®s->maccfg2); |
d87eb127 | 1353 | tempval &= ~MACCFG2_MPEN; |
f4983704 | 1354 | gfar_write(®s->maccfg2, tempval); |
d87eb127 | 1355 | |
be926fc4 | 1356 | gfar_start(ndev); |
d87eb127 | 1357 | |
fba4ed03 SG |
1358 | unlock_rx_qs(priv); |
1359 | unlock_tx_qs(priv); | |
1360 | local_irq_restore(flags); | |
d87eb127 | 1361 | |
be926fc4 AV |
1362 | netif_device_attach(ndev); |
1363 | ||
46ceb60c | 1364 | enable_napi(priv); |
be926fc4 AV |
1365 | |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static int gfar_restore(struct device *dev) | |
1370 | { | |
1371 | struct gfar_private *priv = dev_get_drvdata(dev); | |
1372 | struct net_device *ndev = priv->ndev; | |
1373 | ||
103cdd1d WD |
1374 | if (!netif_running(ndev)) { |
1375 | netif_device_attach(ndev); | |
1376 | ||
be926fc4 | 1377 | return 0; |
103cdd1d | 1378 | } |
be926fc4 | 1379 | |
1eb8f7a7 CM |
1380 | if (gfar_init_bds(ndev)) { |
1381 | free_skb_resources(priv); | |
1382 | return -ENOMEM; | |
1383 | } | |
1384 | ||
be926fc4 AV |
1385 | init_registers(ndev); |
1386 | gfar_set_mac_address(ndev); | |
1387 | gfar_init_mac(ndev); | |
1388 | gfar_start(ndev); | |
1389 | ||
1390 | priv->oldlink = 0; | |
1391 | priv->oldspeed = 0; | |
1392 | priv->oldduplex = -1; | |
1393 | ||
1394 | if (priv->phydev) | |
1395 | phy_start(priv->phydev); | |
d87eb127 | 1396 | |
be926fc4 | 1397 | netif_device_attach(ndev); |
5ea681d4 | 1398 | enable_napi(priv); |
d87eb127 SW |
1399 | |
1400 | return 0; | |
1401 | } | |
be926fc4 AV |
1402 | |
1403 | static struct dev_pm_ops gfar_pm_ops = { | |
1404 | .suspend = gfar_suspend, | |
1405 | .resume = gfar_resume, | |
1406 | .freeze = gfar_suspend, | |
1407 | .thaw = gfar_resume, | |
1408 | .restore = gfar_restore, | |
1409 | }; | |
1410 | ||
1411 | #define GFAR_PM_OPS (&gfar_pm_ops) | |
1412 | ||
d87eb127 | 1413 | #else |
be926fc4 AV |
1414 | |
1415 | #define GFAR_PM_OPS NULL | |
be926fc4 | 1416 | |
d87eb127 | 1417 | #endif |
1da177e4 | 1418 | |
e8a2b6a4 AF |
1419 | /* Reads the controller's registers to determine what interface |
1420 | * connects it to the PHY. | |
1421 | */ | |
1422 | static phy_interface_t gfar_get_interface(struct net_device *dev) | |
1423 | { | |
1424 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1425 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
f4983704 SG |
1426 | u32 ecntrl; |
1427 | ||
f4983704 | 1428 | ecntrl = gfar_read(®s->ecntrl); |
e8a2b6a4 AF |
1429 | |
1430 | if (ecntrl & ECNTRL_SGMII_MODE) | |
1431 | return PHY_INTERFACE_MODE_SGMII; | |
1432 | ||
1433 | if (ecntrl & ECNTRL_TBI_MODE) { | |
1434 | if (ecntrl & ECNTRL_REDUCED_MODE) | |
1435 | return PHY_INTERFACE_MODE_RTBI; | |
1436 | else | |
1437 | return PHY_INTERFACE_MODE_TBI; | |
1438 | } | |
1439 | ||
1440 | if (ecntrl & ECNTRL_REDUCED_MODE) { | |
bc4598bc | 1441 | if (ecntrl & ECNTRL_REDUCED_MII_MODE) { |
e8a2b6a4 | 1442 | return PHY_INTERFACE_MODE_RMII; |
bc4598bc | 1443 | } |
7132ab7f | 1444 | else { |
b31a1d8b | 1445 | phy_interface_t interface = priv->interface; |
7132ab7f | 1446 | |
0977f817 | 1447 | /* This isn't autodetected right now, so it must |
7132ab7f AF |
1448 | * be set by the device tree or platform code. |
1449 | */ | |
1450 | if (interface == PHY_INTERFACE_MODE_RGMII_ID) | |
1451 | return PHY_INTERFACE_MODE_RGMII_ID; | |
1452 | ||
e8a2b6a4 | 1453 | return PHY_INTERFACE_MODE_RGMII; |
7132ab7f | 1454 | } |
e8a2b6a4 AF |
1455 | } |
1456 | ||
b31a1d8b | 1457 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT) |
e8a2b6a4 AF |
1458 | return PHY_INTERFACE_MODE_GMII; |
1459 | ||
1460 | return PHY_INTERFACE_MODE_MII; | |
1461 | } | |
1462 | ||
1463 | ||
bb40dcbb AF |
1464 | /* Initializes driver's PHY state, and attaches to the PHY. |
1465 | * Returns 0 on success. | |
1da177e4 LT |
1466 | */ |
1467 | static int init_phy(struct net_device *dev) | |
1468 | { | |
1469 | struct gfar_private *priv = netdev_priv(dev); | |
bb40dcbb | 1470 | uint gigabit_support = |
b31a1d8b | 1471 | priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ? |
23402bdd | 1472 | GFAR_SUPPORTED_GBIT : 0; |
e8a2b6a4 | 1473 | phy_interface_t interface; |
1da177e4 LT |
1474 | |
1475 | priv->oldlink = 0; | |
1476 | priv->oldspeed = 0; | |
1477 | priv->oldduplex = -1; | |
1478 | ||
e8a2b6a4 AF |
1479 | interface = gfar_get_interface(dev); |
1480 | ||
1db780f8 AV |
1481 | priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0, |
1482 | interface); | |
1483 | if (!priv->phydev) | |
1484 | priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link, | |
1485 | interface); | |
1486 | if (!priv->phydev) { | |
1487 | dev_err(&dev->dev, "could not attach to PHY\n"); | |
1488 | return -ENODEV; | |
fe192a49 | 1489 | } |
1da177e4 | 1490 | |
d3c12873 KJ |
1491 | if (interface == PHY_INTERFACE_MODE_SGMII) |
1492 | gfar_configure_serdes(dev); | |
1493 | ||
bb40dcbb | 1494 | /* Remove any features not supported by the controller */ |
fe192a49 GL |
1495 | priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support); |
1496 | priv->phydev->advertising = priv->phydev->supported; | |
1da177e4 LT |
1497 | |
1498 | return 0; | |
1da177e4 LT |
1499 | } |
1500 | ||
0977f817 | 1501 | /* Initialize TBI PHY interface for communicating with the |
d0313587 PG |
1502 | * SERDES lynx PHY on the chip. We communicate with this PHY |
1503 | * through the MDIO bus on each controller, treating it as a | |
1504 | * "normal" PHY at the address found in the TBIPA register. We assume | |
1505 | * that the TBIPA register is valid. Either the MDIO bus code will set | |
1506 | * it to a value that doesn't conflict with other PHYs on the bus, or the | |
1507 | * value doesn't matter, as there are no other PHYs on the bus. | |
1508 | */ | |
d3c12873 KJ |
1509 | static void gfar_configure_serdes(struct net_device *dev) |
1510 | { | |
1511 | struct gfar_private *priv = netdev_priv(dev); | |
fe192a49 GL |
1512 | struct phy_device *tbiphy; |
1513 | ||
1514 | if (!priv->tbi_node) { | |
1515 | dev_warn(&dev->dev, "error: SGMII mode requires that the " | |
1516 | "device tree specify a tbi-handle\n"); | |
1517 | return; | |
1518 | } | |
c132419e | 1519 | |
fe192a49 GL |
1520 | tbiphy = of_phy_find_device(priv->tbi_node); |
1521 | if (!tbiphy) { | |
1522 | dev_err(&dev->dev, "error: Could not get TBI device\n"); | |
b31a1d8b AF |
1523 | return; |
1524 | } | |
d3c12873 | 1525 | |
0977f817 | 1526 | /* If the link is already up, we must already be ok, and don't need to |
bdb59f94 TP |
1527 | * configure and reset the TBI<->SerDes link. Maybe U-Boot configured |
1528 | * everything for us? Resetting it takes the link down and requires | |
1529 | * several seconds for it to come back. | |
1530 | */ | |
fe192a49 | 1531 | if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) |
b31a1d8b | 1532 | return; |
d3c12873 | 1533 | |
d0313587 | 1534 | /* Single clk mode, mii mode off(for serdes communication) */ |
fe192a49 | 1535 | phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); |
d3c12873 | 1536 | |
fe192a49 | 1537 | phy_write(tbiphy, MII_ADVERTISE, |
bc4598bc JC |
1538 | ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE | |
1539 | ADVERTISE_1000XPSE_ASYM); | |
d3c12873 | 1540 | |
bc4598bc JC |
1541 | phy_write(tbiphy, MII_BMCR, |
1542 | BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX | | |
1543 | BMCR_SPEED1000); | |
d3c12873 KJ |
1544 | } |
1545 | ||
1da177e4 LT |
1546 | static void init_registers(struct net_device *dev) |
1547 | { | |
1548 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 1549 | struct gfar __iomem *regs = NULL; |
3a2e16c8 | 1550 | int i; |
1da177e4 | 1551 | |
46ceb60c SG |
1552 | for (i = 0; i < priv->num_grps; i++) { |
1553 | regs = priv->gfargrp[i].regs; | |
1554 | /* Clear IEVENT */ | |
1555 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1da177e4 | 1556 | |
46ceb60c SG |
1557 | /* Initialize IMASK */ |
1558 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1559 | } | |
1da177e4 | 1560 | |
46ceb60c | 1561 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1562 | /* Init hash registers to zero */ |
f4983704 SG |
1563 | gfar_write(®s->igaddr0, 0); |
1564 | gfar_write(®s->igaddr1, 0); | |
1565 | gfar_write(®s->igaddr2, 0); | |
1566 | gfar_write(®s->igaddr3, 0); | |
1567 | gfar_write(®s->igaddr4, 0); | |
1568 | gfar_write(®s->igaddr5, 0); | |
1569 | gfar_write(®s->igaddr6, 0); | |
1570 | gfar_write(®s->igaddr7, 0); | |
1571 | ||
1572 | gfar_write(®s->gaddr0, 0); | |
1573 | gfar_write(®s->gaddr1, 0); | |
1574 | gfar_write(®s->gaddr2, 0); | |
1575 | gfar_write(®s->gaddr3, 0); | |
1576 | gfar_write(®s->gaddr4, 0); | |
1577 | gfar_write(®s->gaddr5, 0); | |
1578 | gfar_write(®s->gaddr6, 0); | |
1579 | gfar_write(®s->gaddr7, 0); | |
1da177e4 | 1580 | |
1da177e4 | 1581 | /* Zero out the rmon mib registers if it has them */ |
b31a1d8b | 1582 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) { |
f4983704 | 1583 | memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib)); |
1da177e4 LT |
1584 | |
1585 | /* Mask off the CAM interrupts */ | |
f4983704 SG |
1586 | gfar_write(®s->rmon.cam1, 0xffffffff); |
1587 | gfar_write(®s->rmon.cam2, 0xffffffff); | |
1da177e4 LT |
1588 | } |
1589 | ||
1590 | /* Initialize the max receive buffer length */ | |
f4983704 | 1591 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
1da177e4 | 1592 | |
1da177e4 | 1593 | /* Initialize the Minimum Frame Length Register */ |
f4983704 | 1594 | gfar_write(®s->minflr, MINFLR_INIT_SETTINGS); |
1da177e4 LT |
1595 | } |
1596 | ||
511d934f AV |
1597 | static int __gfar_is_rx_idle(struct gfar_private *priv) |
1598 | { | |
1599 | u32 res; | |
1600 | ||
0977f817 | 1601 | /* Normaly TSEC should not hang on GRS commands, so we should |
511d934f AV |
1602 | * actually wait for IEVENT_GRSC flag. |
1603 | */ | |
1604 | if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002))) | |
1605 | return 0; | |
1606 | ||
0977f817 | 1607 | /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are |
511d934f AV |
1608 | * the same as bits 23-30, the eTSEC Rx is assumed to be idle |
1609 | * and the Rx can be safely reset. | |
1610 | */ | |
1611 | res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c); | |
1612 | res &= 0x7f807f80; | |
1613 | if ((res & 0xffff) == (res >> 16)) | |
1614 | return 1; | |
1615 | ||
1616 | return 0; | |
1617 | } | |
0bbaf069 KG |
1618 | |
1619 | /* Halt the receive and transmit queues */ | |
d87eb127 | 1620 | static void gfar_halt_nodisable(struct net_device *dev) |
1da177e4 LT |
1621 | { |
1622 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1623 | struct gfar __iomem *regs = NULL; |
1da177e4 | 1624 | u32 tempval; |
3a2e16c8 | 1625 | int i; |
1da177e4 | 1626 | |
46ceb60c SG |
1627 | for (i = 0; i < priv->num_grps; i++) { |
1628 | regs = priv->gfargrp[i].regs; | |
1629 | /* Mask all interrupts */ | |
1630 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1da177e4 | 1631 | |
46ceb60c SG |
1632 | /* Clear all interrupts */ |
1633 | gfar_write(®s->ievent, IEVENT_INIT_CLEAR); | |
1634 | } | |
1da177e4 | 1635 | |
46ceb60c | 1636 | regs = priv->gfargrp[0].regs; |
1da177e4 | 1637 | /* Stop the DMA, and wait for it to stop */ |
f4983704 | 1638 | tempval = gfar_read(®s->dmactrl); |
bc4598bc JC |
1639 | if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != |
1640 | (DMACTRL_GRS | DMACTRL_GTS)) { | |
511d934f AV |
1641 | int ret; |
1642 | ||
1da177e4 | 1643 | tempval |= (DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1644 | gfar_write(®s->dmactrl, tempval); |
1da177e4 | 1645 | |
511d934f AV |
1646 | do { |
1647 | ret = spin_event_timeout(((gfar_read(®s->ievent) & | |
1648 | (IEVENT_GRSC | IEVENT_GTSC)) == | |
1649 | (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0); | |
1650 | if (!ret && !(gfar_read(®s->ievent) & IEVENT_GRSC)) | |
1651 | ret = __gfar_is_rx_idle(priv); | |
1652 | } while (!ret); | |
1da177e4 | 1653 | } |
d87eb127 | 1654 | } |
d87eb127 SW |
1655 | |
1656 | /* Halt the receive and transmit queues */ | |
1657 | void gfar_halt(struct net_device *dev) | |
1658 | { | |
1659 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1660 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
d87eb127 | 1661 | u32 tempval; |
1da177e4 | 1662 | |
2a54adc3 SW |
1663 | gfar_halt_nodisable(dev); |
1664 | ||
1da177e4 LT |
1665 | /* Disable Rx and Tx */ |
1666 | tempval = gfar_read(®s->maccfg1); | |
1667 | tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1668 | gfar_write(®s->maccfg1, tempval); | |
0bbaf069 KG |
1669 | } |
1670 | ||
46ceb60c SG |
1671 | static void free_grp_irqs(struct gfar_priv_grp *grp) |
1672 | { | |
ee873fda CM |
1673 | free_irq(gfar_irq(grp, TX)->irq, grp); |
1674 | free_irq(gfar_irq(grp, RX)->irq, grp); | |
1675 | free_irq(gfar_irq(grp, ER)->irq, grp); | |
46ceb60c SG |
1676 | } |
1677 | ||
0bbaf069 KG |
1678 | void stop_gfar(struct net_device *dev) |
1679 | { | |
1680 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 1681 | unsigned long flags; |
46ceb60c | 1682 | int i; |
0bbaf069 | 1683 | |
bb40dcbb AF |
1684 | phy_stop(priv->phydev); |
1685 | ||
a12f801d | 1686 | |
0bbaf069 | 1687 | /* Lock it down */ |
fba4ed03 SG |
1688 | local_irq_save(flags); |
1689 | lock_tx_qs(priv); | |
1690 | lock_rx_qs(priv); | |
0bbaf069 | 1691 | |
0bbaf069 | 1692 | gfar_halt(dev); |
1da177e4 | 1693 | |
fba4ed03 SG |
1694 | unlock_rx_qs(priv); |
1695 | unlock_tx_qs(priv); | |
1696 | local_irq_restore(flags); | |
1da177e4 LT |
1697 | |
1698 | /* Free the IRQs */ | |
b31a1d8b | 1699 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c SG |
1700 | for (i = 0; i < priv->num_grps; i++) |
1701 | free_grp_irqs(&priv->gfargrp[i]); | |
1da177e4 | 1702 | } else { |
46ceb60c | 1703 | for (i = 0; i < priv->num_grps; i++) |
ee873fda | 1704 | free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq, |
bc4598bc | 1705 | &priv->gfargrp[i]); |
1da177e4 LT |
1706 | } |
1707 | ||
1708 | free_skb_resources(priv); | |
1da177e4 LT |
1709 | } |
1710 | ||
fba4ed03 | 1711 | static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 1712 | { |
1da177e4 | 1713 | struct txbd8 *txbdp; |
fba4ed03 | 1714 | struct gfar_private *priv = netdev_priv(tx_queue->dev); |
4669bc90 | 1715 | int i, j; |
1da177e4 | 1716 | |
a12f801d | 1717 | txbdp = tx_queue->tx_bd_base; |
1da177e4 | 1718 | |
a12f801d SG |
1719 | for (i = 0; i < tx_queue->tx_ring_size; i++) { |
1720 | if (!tx_queue->tx_skbuff[i]) | |
4669bc90 | 1721 | continue; |
1da177e4 | 1722 | |
369ec162 | 1723 | dma_unmap_single(priv->dev, txbdp->bufPtr, |
bc4598bc | 1724 | txbdp->length, DMA_TO_DEVICE); |
4669bc90 | 1725 | txbdp->lstatus = 0; |
fba4ed03 | 1726 | for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags; |
bc4598bc | 1727 | j++) { |
4669bc90 | 1728 | txbdp++; |
369ec162 | 1729 | dma_unmap_page(priv->dev, txbdp->bufPtr, |
bc4598bc | 1730 | txbdp->length, DMA_TO_DEVICE); |
1da177e4 | 1731 | } |
ad5da7ab | 1732 | txbdp++; |
a12f801d SG |
1733 | dev_kfree_skb_any(tx_queue->tx_skbuff[i]); |
1734 | tx_queue->tx_skbuff[i] = NULL; | |
1da177e4 | 1735 | } |
a12f801d | 1736 | kfree(tx_queue->tx_skbuff); |
1eb8f7a7 | 1737 | tx_queue->tx_skbuff = NULL; |
fba4ed03 | 1738 | } |
1da177e4 | 1739 | |
fba4ed03 SG |
1740 | static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue) |
1741 | { | |
1742 | struct rxbd8 *rxbdp; | |
1743 | struct gfar_private *priv = netdev_priv(rx_queue->dev); | |
1744 | int i; | |
1da177e4 | 1745 | |
fba4ed03 | 1746 | rxbdp = rx_queue->rx_bd_base; |
1da177e4 | 1747 | |
a12f801d SG |
1748 | for (i = 0; i < rx_queue->rx_ring_size; i++) { |
1749 | if (rx_queue->rx_skbuff[i]) { | |
369ec162 CM |
1750 | dma_unmap_single(priv->dev, rxbdp->bufPtr, |
1751 | priv->rx_buffer_size, | |
bc4598bc | 1752 | DMA_FROM_DEVICE); |
a12f801d SG |
1753 | dev_kfree_skb_any(rx_queue->rx_skbuff[i]); |
1754 | rx_queue->rx_skbuff[i] = NULL; | |
1da177e4 | 1755 | } |
e69edd21 AV |
1756 | rxbdp->lstatus = 0; |
1757 | rxbdp->bufPtr = 0; | |
1758 | rxbdp++; | |
1da177e4 | 1759 | } |
a12f801d | 1760 | kfree(rx_queue->rx_skbuff); |
1eb8f7a7 | 1761 | rx_queue->rx_skbuff = NULL; |
fba4ed03 | 1762 | } |
e69edd21 | 1763 | |
fba4ed03 | 1764 | /* If there are any tx skbs or rx skbs still around, free them. |
0977f817 JC |
1765 | * Then free tx_skbuff and rx_skbuff |
1766 | */ | |
fba4ed03 SG |
1767 | static void free_skb_resources(struct gfar_private *priv) |
1768 | { | |
1769 | struct gfar_priv_tx_q *tx_queue = NULL; | |
1770 | struct gfar_priv_rx_q *rx_queue = NULL; | |
1771 | int i; | |
1772 | ||
1773 | /* Go through all the buffer descriptors and free their data buffers */ | |
1774 | for (i = 0; i < priv->num_tx_queues; i++) { | |
d8a0f1b0 | 1775 | struct netdev_queue *txq; |
bc4598bc | 1776 | |
fba4ed03 | 1777 | tx_queue = priv->tx_queue[i]; |
d8a0f1b0 | 1778 | txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex); |
bc4598bc | 1779 | if (tx_queue->tx_skbuff) |
fba4ed03 | 1780 | free_skb_tx_queue(tx_queue); |
d8a0f1b0 | 1781 | netdev_tx_reset_queue(txq); |
fba4ed03 SG |
1782 | } |
1783 | ||
1784 | for (i = 0; i < priv->num_rx_queues; i++) { | |
1785 | rx_queue = priv->rx_queue[i]; | |
bc4598bc | 1786 | if (rx_queue->rx_skbuff) |
fba4ed03 SG |
1787 | free_skb_rx_queue(rx_queue); |
1788 | } | |
1789 | ||
369ec162 | 1790 | dma_free_coherent(priv->dev, |
bc4598bc JC |
1791 | sizeof(struct txbd8) * priv->total_tx_ring_size + |
1792 | sizeof(struct rxbd8) * priv->total_rx_ring_size, | |
1793 | priv->tx_queue[0]->tx_bd_base, | |
1794 | priv->tx_queue[0]->tx_bd_dma_base); | |
1da177e4 LT |
1795 | } |
1796 | ||
0bbaf069 KG |
1797 | void gfar_start(struct net_device *dev) |
1798 | { | |
1799 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 1800 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
0bbaf069 | 1801 | u32 tempval; |
46ceb60c | 1802 | int i = 0; |
0bbaf069 KG |
1803 | |
1804 | /* Enable Rx and Tx in MACCFG1 */ | |
1805 | tempval = gfar_read(®s->maccfg1); | |
1806 | tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); | |
1807 | gfar_write(®s->maccfg1, tempval); | |
1808 | ||
1809 | /* Initialize DMACTRL to have WWR and WOP */ | |
f4983704 | 1810 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1811 | tempval |= DMACTRL_INIT_SETTINGS; |
f4983704 | 1812 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1813 | |
0bbaf069 | 1814 | /* Make sure we aren't stopped */ |
f4983704 | 1815 | tempval = gfar_read(®s->dmactrl); |
0bbaf069 | 1816 | tempval &= ~(DMACTRL_GRS | DMACTRL_GTS); |
f4983704 | 1817 | gfar_write(®s->dmactrl, tempval); |
0bbaf069 | 1818 | |
46ceb60c SG |
1819 | for (i = 0; i < priv->num_grps; i++) { |
1820 | regs = priv->gfargrp[i].regs; | |
1821 | /* Clear THLT/RHLT, so that the DMA starts polling now */ | |
1822 | gfar_write(®s->tstat, priv->gfargrp[i].tstat); | |
1823 | gfar_write(®s->rstat, priv->gfargrp[i].rstat); | |
1824 | /* Unmask the interrupts we look for */ | |
1825 | gfar_write(®s->imask, IMASK_DEFAULT); | |
1826 | } | |
12dea57b | 1827 | |
1ae5dc34 | 1828 | dev->trans_start = jiffies; /* prevent tx timeout */ |
0bbaf069 KG |
1829 | } |
1830 | ||
800c644b | 1831 | static void gfar_configure_coalescing(struct gfar_private *priv, |
bc4598bc | 1832 | unsigned long tx_mask, unsigned long rx_mask) |
1da177e4 | 1833 | { |
46ceb60c | 1834 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
18294ad1 | 1835 | u32 __iomem *baddr; |
815b97c6 | 1836 | |
46ceb60c | 1837 | if (priv->mode == MQ_MG_MODE) { |
5d9657d8 | 1838 | int i = 0; |
c6e1160e | 1839 | |
46ceb60c | 1840 | baddr = ®s->txic0; |
984b3f57 | 1841 | for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { |
9740e001 CM |
1842 | gfar_write(baddr + i, 0); |
1843 | if (likely(priv->tx_queue[i]->txcoalescing)) | |
46ceb60c | 1844 | gfar_write(baddr + i, priv->tx_queue[i]->txic); |
46ceb60c SG |
1845 | } |
1846 | ||
1847 | baddr = ®s->rxic0; | |
984b3f57 | 1848 | for_each_set_bit(i, &rx_mask, priv->num_rx_queues) { |
9740e001 CM |
1849 | gfar_write(baddr + i, 0); |
1850 | if (likely(priv->rx_queue[i]->rxcoalescing)) | |
46ceb60c | 1851 | gfar_write(baddr + i, priv->rx_queue[i]->rxic); |
46ceb60c | 1852 | } |
5d9657d8 | 1853 | } else { |
c6e1160e | 1854 | /* Backward compatible case -- even if we enable |
5d9657d8 CM |
1855 | * multiple queues, there's only single reg to program |
1856 | */ | |
1857 | gfar_write(®s->txic, 0); | |
1858 | if (likely(priv->tx_queue[0]->txcoalescing)) | |
1859 | gfar_write(®s->txic, priv->tx_queue[0]->txic); | |
1860 | ||
1861 | gfar_write(®s->rxic, 0); | |
1862 | if (unlikely(priv->rx_queue[0]->rxcoalescing)) | |
1863 | gfar_write(®s->rxic, priv->rx_queue[0]->rxic); | |
46ceb60c SG |
1864 | } |
1865 | } | |
1866 | ||
800c644b CM |
1867 | void gfar_configure_coalescing_all(struct gfar_private *priv) |
1868 | { | |
1869 | gfar_configure_coalescing(priv, 0xFF, 0xFF); | |
1870 | } | |
1871 | ||
46ceb60c SG |
1872 | static int register_grp_irqs(struct gfar_priv_grp *grp) |
1873 | { | |
1874 | struct gfar_private *priv = grp->priv; | |
1875 | struct net_device *dev = priv->ndev; | |
1876 | int err; | |
1da177e4 | 1877 | |
1da177e4 | 1878 | /* If the device has multiple interrupts, register for |
0977f817 JC |
1879 | * them. Otherwise, only register for the one |
1880 | */ | |
b31a1d8b | 1881 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
0bbaf069 | 1882 | /* Install our interrupt handlers for Error, |
0977f817 JC |
1883 | * Transmit, and Receive |
1884 | */ | |
ee873fda CM |
1885 | err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0, |
1886 | gfar_irq(grp, ER)->name, grp); | |
1887 | if (err < 0) { | |
59deab26 | 1888 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1889 | gfar_irq(grp, ER)->irq); |
46ceb60c | 1890 | |
2145f1af | 1891 | goto err_irq_fail; |
1da177e4 | 1892 | } |
ee873fda CM |
1893 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0, |
1894 | gfar_irq(grp, TX)->name, grp); | |
1895 | if (err < 0) { | |
59deab26 | 1896 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1897 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1898 | goto tx_irq_fail; |
1899 | } | |
ee873fda CM |
1900 | err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0, |
1901 | gfar_irq(grp, RX)->name, grp); | |
1902 | if (err < 0) { | |
59deab26 | 1903 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1904 | gfar_irq(grp, RX)->irq); |
1da177e4 LT |
1905 | goto rx_irq_fail; |
1906 | } | |
1907 | } else { | |
ee873fda CM |
1908 | err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0, |
1909 | gfar_irq(grp, TX)->name, grp); | |
1910 | if (err < 0) { | |
59deab26 | 1911 | netif_err(priv, intr, dev, "Can't get IRQ %d\n", |
ee873fda | 1912 | gfar_irq(grp, TX)->irq); |
1da177e4 LT |
1913 | goto err_irq_fail; |
1914 | } | |
1915 | } | |
1916 | ||
46ceb60c SG |
1917 | return 0; |
1918 | ||
1919 | rx_irq_fail: | |
ee873fda | 1920 | free_irq(gfar_irq(grp, TX)->irq, grp); |
46ceb60c | 1921 | tx_irq_fail: |
ee873fda | 1922 | free_irq(gfar_irq(grp, ER)->irq, grp); |
46ceb60c SG |
1923 | err_irq_fail: |
1924 | return err; | |
1925 | ||
1926 | } | |
1927 | ||
1928 | /* Bring the controller up and running */ | |
1929 | int startup_gfar(struct net_device *ndev) | |
1930 | { | |
1931 | struct gfar_private *priv = netdev_priv(ndev); | |
1932 | struct gfar __iomem *regs = NULL; | |
1933 | int err, i, j; | |
1934 | ||
1935 | for (i = 0; i < priv->num_grps; i++) { | |
1936 | regs= priv->gfargrp[i].regs; | |
1937 | gfar_write(®s->imask, IMASK_INIT_CLEAR); | |
1938 | } | |
1939 | ||
1940 | regs= priv->gfargrp[0].regs; | |
1941 | err = gfar_alloc_skb_resources(ndev); | |
1942 | if (err) | |
1943 | return err; | |
1944 | ||
1945 | gfar_init_mac(ndev); | |
1946 | ||
1947 | for (i = 0; i < priv->num_grps; i++) { | |
1948 | err = register_grp_irqs(&priv->gfargrp[i]); | |
1949 | if (err) { | |
1950 | for (j = 0; j < i; j++) | |
1951 | free_grp_irqs(&priv->gfargrp[j]); | |
ff76015f | 1952 | goto irq_fail; |
46ceb60c SG |
1953 | } |
1954 | } | |
1955 | ||
7f7f5316 | 1956 | /* Start the controller */ |
ccc05c6e | 1957 | gfar_start(ndev); |
1da177e4 | 1958 | |
826aa4a0 AV |
1959 | phy_start(priv->phydev); |
1960 | ||
800c644b | 1961 | gfar_configure_coalescing_all(priv); |
46ceb60c | 1962 | |
1da177e4 LT |
1963 | return 0; |
1964 | ||
46ceb60c | 1965 | irq_fail: |
e69edd21 | 1966 | free_skb_resources(priv); |
1da177e4 LT |
1967 | return err; |
1968 | } | |
1969 | ||
0977f817 JC |
1970 | /* Called when something needs to use the ethernet device |
1971 | * Returns 0 for success. | |
1972 | */ | |
1da177e4 LT |
1973 | static int gfar_enet_open(struct net_device *dev) |
1974 | { | |
94e8cc35 | 1975 | struct gfar_private *priv = netdev_priv(dev); |
1da177e4 LT |
1976 | int err; |
1977 | ||
46ceb60c | 1978 | enable_napi(priv); |
bea3348e | 1979 | |
1da177e4 LT |
1980 | /* Initialize a bunch of registers */ |
1981 | init_registers(dev); | |
1982 | ||
1983 | gfar_set_mac_address(dev); | |
1984 | ||
1985 | err = init_phy(dev); | |
1986 | ||
a12f801d | 1987 | if (err) { |
46ceb60c | 1988 | disable_napi(priv); |
1da177e4 | 1989 | return err; |
bea3348e | 1990 | } |
1da177e4 LT |
1991 | |
1992 | err = startup_gfar(dev); | |
db0e8e3f | 1993 | if (err) { |
46ceb60c | 1994 | disable_napi(priv); |
db0e8e3f AV |
1995 | return err; |
1996 | } | |
1da177e4 | 1997 | |
fba4ed03 | 1998 | netif_tx_start_all_queues(dev); |
1da177e4 | 1999 | |
2884e5cc AV |
2000 | device_set_wakeup_enable(&dev->dev, priv->wol_en); |
2001 | ||
1da177e4 LT |
2002 | return err; |
2003 | } | |
2004 | ||
54dc79fe | 2005 | static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb) |
0bbaf069 | 2006 | { |
54dc79fe | 2007 | struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN); |
6c31d55f KG |
2008 | |
2009 | memset(fcb, 0, GMAC_FCB_LEN); | |
0bbaf069 | 2010 | |
0bbaf069 KG |
2011 | return fcb; |
2012 | } | |
2013 | ||
9c4886e5 | 2014 | static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb, |
bc4598bc | 2015 | int fcb_length) |
0bbaf069 | 2016 | { |
0bbaf069 KG |
2017 | /* If we're here, it's a IP packet with a TCP or UDP |
2018 | * payload. We set it to checksum, using a pseudo-header | |
2019 | * we provide | |
2020 | */ | |
3a2e16c8 | 2021 | u8 flags = TXFCB_DEFAULT; |
0bbaf069 | 2022 | |
0977f817 JC |
2023 | /* Tell the controller what the protocol is |
2024 | * And provide the already calculated phcs | |
2025 | */ | |
eddc9ec5 | 2026 | if (ip_hdr(skb)->protocol == IPPROTO_UDP) { |
7f7f5316 | 2027 | flags |= TXFCB_UDP; |
4bedb452 | 2028 | fcb->phcs = udp_hdr(skb)->check; |
7f7f5316 | 2029 | } else |
8da32de5 | 2030 | fcb->phcs = tcp_hdr(skb)->check; |
0bbaf069 KG |
2031 | |
2032 | /* l3os is the distance between the start of the | |
2033 | * frame (skb->data) and the start of the IP hdr. | |
2034 | * l4os is the distance between the start of the | |
0977f817 JC |
2035 | * l3 hdr and the l4 hdr |
2036 | */ | |
9c4886e5 | 2037 | fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length); |
cfe1fc77 | 2038 | fcb->l4os = skb_network_header_len(skb); |
0bbaf069 | 2039 | |
7f7f5316 | 2040 | fcb->flags = flags; |
0bbaf069 KG |
2041 | } |
2042 | ||
7f7f5316 | 2043 | void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb) |
0bbaf069 | 2044 | { |
7f7f5316 | 2045 | fcb->flags |= TXFCB_VLN; |
0bbaf069 KG |
2046 | fcb->vlctl = vlan_tx_tag_get(skb); |
2047 | } | |
2048 | ||
4669bc90 | 2049 | static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride, |
bc4598bc | 2050 | struct txbd8 *base, int ring_size) |
4669bc90 DH |
2051 | { |
2052 | struct txbd8 *new_bd = bdp + stride; | |
2053 | ||
2054 | return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd; | |
2055 | } | |
2056 | ||
2057 | static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base, | |
bc4598bc | 2058 | int ring_size) |
4669bc90 DH |
2059 | { |
2060 | return skip_txbd(bdp, 1, base, ring_size); | |
2061 | } | |
2062 | ||
02d88fb4 CM |
2063 | /* eTSEC12: csum generation not supported for some fcb offsets */ |
2064 | static inline bool gfar_csum_errata_12(struct gfar_private *priv, | |
2065 | unsigned long fcb_addr) | |
2066 | { | |
2067 | return (gfar_has_errata(priv, GFAR_ERRATA_12) && | |
2068 | (fcb_addr % 0x20) > 0x18); | |
2069 | } | |
2070 | ||
2071 | /* eTSEC76: csum generation for frames larger than 2500 may | |
2072 | * cause excess delays before start of transmission | |
2073 | */ | |
2074 | static inline bool gfar_csum_errata_76(struct gfar_private *priv, | |
2075 | unsigned int len) | |
2076 | { | |
2077 | return (gfar_has_errata(priv, GFAR_ERRATA_76) && | |
2078 | (len > 2500)); | |
2079 | } | |
2080 | ||
0977f817 JC |
2081 | /* This is called by the kernel when a frame is ready for transmission. |
2082 | * It is pointed to by the dev->hard_start_xmit function pointer | |
2083 | */ | |
1da177e4 LT |
2084 | static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2085 | { | |
2086 | struct gfar_private *priv = netdev_priv(dev); | |
a12f801d | 2087 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2088 | struct netdev_queue *txq; |
f4983704 | 2089 | struct gfar __iomem *regs = NULL; |
0bbaf069 | 2090 | struct txfcb *fcb = NULL; |
f0ee7acf | 2091 | struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL; |
5a5efed4 | 2092 | u32 lstatus; |
0d0cffdc CM |
2093 | int i, rq = 0; |
2094 | int do_tstamp, do_csum, do_vlan; | |
4669bc90 | 2095 | u32 bufaddr; |
fef6108d | 2096 | unsigned long flags; |
50ad076b | 2097 | unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0; |
fba4ed03 SG |
2098 | |
2099 | rq = skb->queue_mapping; | |
2100 | tx_queue = priv->tx_queue[rq]; | |
2101 | txq = netdev_get_tx_queue(dev, rq); | |
a12f801d | 2102 | base = tx_queue->tx_bd_base; |
46ceb60c | 2103 | regs = tx_queue->grp->regs; |
f0ee7acf | 2104 | |
0d0cffdc CM |
2105 | do_csum = (CHECKSUM_PARTIAL == skb->ip_summed); |
2106 | do_vlan = vlan_tx_tag_present(skb); | |
2107 | do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && | |
2108 | priv->hwts_tx_en; | |
2109 | ||
2110 | if (do_csum || do_vlan) | |
2111 | fcb_len = GMAC_FCB_LEN; | |
2112 | ||
f0ee7acf | 2113 | /* check if time stamp should be generated */ |
0d0cffdc CM |
2114 | if (unlikely(do_tstamp)) |
2115 | fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN; | |
4669bc90 | 2116 | |
5b28beaf | 2117 | /* make space for additional header when fcb is needed */ |
0d0cffdc | 2118 | if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) { |
54dc79fe SH |
2119 | struct sk_buff *skb_new; |
2120 | ||
0d0cffdc | 2121 | skb_new = skb_realloc_headroom(skb, fcb_len); |
54dc79fe SH |
2122 | if (!skb_new) { |
2123 | dev->stats.tx_errors++; | |
bd14ba84 | 2124 | kfree_skb(skb); |
54dc79fe SH |
2125 | return NETDEV_TX_OK; |
2126 | } | |
db83d136 | 2127 | |
313b037c ED |
2128 | if (skb->sk) |
2129 | skb_set_owner_w(skb_new, skb->sk); | |
2130 | consume_skb(skb); | |
54dc79fe SH |
2131 | skb = skb_new; |
2132 | } | |
2133 | ||
4669bc90 DH |
2134 | /* total number of fragments in the SKB */ |
2135 | nr_frags = skb_shinfo(skb)->nr_frags; | |
2136 | ||
f0ee7acf MR |
2137 | /* calculate the required number of TxBDs for this skb */ |
2138 | if (unlikely(do_tstamp)) | |
2139 | nr_txbds = nr_frags + 2; | |
2140 | else | |
2141 | nr_txbds = nr_frags + 1; | |
2142 | ||
4669bc90 | 2143 | /* check if there is space to queue this packet */ |
f0ee7acf | 2144 | if (nr_txbds > tx_queue->num_txbdfree) { |
4669bc90 | 2145 | /* no space, stop the queue */ |
fba4ed03 | 2146 | netif_tx_stop_queue(txq); |
4669bc90 | 2147 | dev->stats.tx_fifo_errors++; |
4669bc90 DH |
2148 | return NETDEV_TX_BUSY; |
2149 | } | |
1da177e4 LT |
2150 | |
2151 | /* Update transmit stats */ | |
50ad076b CM |
2152 | bytes_sent = skb->len; |
2153 | tx_queue->stats.tx_bytes += bytes_sent; | |
2154 | /* keep Tx bytes on wire for BQL accounting */ | |
2155 | GFAR_CB(skb)->bytes_sent = bytes_sent; | |
1ac9ad13 | 2156 | tx_queue->stats.tx_packets++; |
1da177e4 | 2157 | |
a12f801d | 2158 | txbdp = txbdp_start = tx_queue->cur_tx; |
f0ee7acf MR |
2159 | lstatus = txbdp->lstatus; |
2160 | ||
2161 | /* Time stamp insertion requires one additional TxBD */ | |
2162 | if (unlikely(do_tstamp)) | |
2163 | txbdp_tstamp = txbdp = next_txbd(txbdp, base, | |
bc4598bc | 2164 | tx_queue->tx_ring_size); |
1da177e4 | 2165 | |
4669bc90 | 2166 | if (nr_frags == 0) { |
f0ee7acf MR |
2167 | if (unlikely(do_tstamp)) |
2168 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST | | |
bc4598bc | 2169 | TXBD_INTERRUPT); |
f0ee7acf MR |
2170 | else |
2171 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
4669bc90 DH |
2172 | } else { |
2173 | /* Place the fragment addresses and lengths into the TxBDs */ | |
2174 | for (i = 0; i < nr_frags; i++) { | |
50ad076b | 2175 | unsigned int frag_len; |
4669bc90 | 2176 | /* Point at the next BD, wrapping as needed */ |
a12f801d | 2177 | txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 | 2178 | |
50ad076b | 2179 | frag_len = skb_shinfo(skb)->frags[i].size; |
4669bc90 | 2180 | |
50ad076b | 2181 | lstatus = txbdp->lstatus | frag_len | |
bc4598bc | 2182 | BD_LFLAG(TXBD_READY); |
4669bc90 DH |
2183 | |
2184 | /* Handle the last BD specially */ | |
2185 | if (i == nr_frags - 1) | |
2186 | lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT); | |
1da177e4 | 2187 | |
369ec162 | 2188 | bufaddr = skb_frag_dma_map(priv->dev, |
2234a722 IC |
2189 | &skb_shinfo(skb)->frags[i], |
2190 | 0, | |
50ad076b | 2191 | frag_len, |
2234a722 | 2192 | DMA_TO_DEVICE); |
4669bc90 DH |
2193 | |
2194 | /* set the TxBD length and buffer pointer */ | |
2195 | txbdp->bufPtr = bufaddr; | |
2196 | txbdp->lstatus = lstatus; | |
2197 | } | |
2198 | ||
2199 | lstatus = txbdp_start->lstatus; | |
2200 | } | |
1da177e4 | 2201 | |
9c4886e5 MR |
2202 | /* Add TxPAL between FCB and frame if required */ |
2203 | if (unlikely(do_tstamp)) { | |
2204 | skb_push(skb, GMAC_TXPAL_LEN); | |
2205 | memset(skb->data, 0, GMAC_TXPAL_LEN); | |
2206 | } | |
2207 | ||
0d0cffdc CM |
2208 | /* Add TxFCB if required */ |
2209 | if (fcb_len) { | |
54dc79fe | 2210 | fcb = gfar_add_fcb(skb); |
02d88fb4 | 2211 | lstatus |= BD_LFLAG(TXBD_TOE); |
0d0cffdc CM |
2212 | } |
2213 | ||
2214 | /* Set up checksumming */ | |
2215 | if (do_csum) { | |
2216 | gfar_tx_checksum(skb, fcb, fcb_len); | |
02d88fb4 CM |
2217 | |
2218 | if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) || | |
2219 | unlikely(gfar_csum_errata_76(priv, skb->len))) { | |
4363c2fd AD |
2220 | __skb_pull(skb, GMAC_FCB_LEN); |
2221 | skb_checksum_help(skb); | |
0d0cffdc CM |
2222 | if (do_vlan || do_tstamp) { |
2223 | /* put back a new fcb for vlan/tstamp TOE */ | |
2224 | fcb = gfar_add_fcb(skb); | |
2225 | } else { | |
2226 | /* Tx TOE not used */ | |
2227 | lstatus &= ~(BD_LFLAG(TXBD_TOE)); | |
2228 | fcb = NULL; | |
2229 | } | |
4363c2fd | 2230 | } |
0bbaf069 KG |
2231 | } |
2232 | ||
0d0cffdc | 2233 | if (do_vlan) |
54dc79fe | 2234 | gfar_tx_vlan(skb, fcb); |
0bbaf069 | 2235 | |
f0ee7acf MR |
2236 | /* Setup tx hardware time stamping if requested */ |
2237 | if (unlikely(do_tstamp)) { | |
2244d07b | 2238 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
f0ee7acf | 2239 | fcb->ptp = 1; |
f0ee7acf MR |
2240 | } |
2241 | ||
369ec162 | 2242 | txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data, |
bc4598bc | 2243 | skb_headlen(skb), DMA_TO_DEVICE); |
1da177e4 | 2244 | |
0977f817 | 2245 | /* If time stamping is requested one additional TxBD must be set up. The |
f0ee7acf MR |
2246 | * first TxBD points to the FCB and must have a data length of |
2247 | * GMAC_FCB_LEN. The second TxBD points to the actual frame data with | |
2248 | * the full frame length. | |
2249 | */ | |
2250 | if (unlikely(do_tstamp)) { | |
0d0cffdc | 2251 | txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len; |
f0ee7acf | 2252 | txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) | |
0d0cffdc | 2253 | (skb_headlen(skb) - fcb_len); |
f0ee7acf MR |
2254 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN; |
2255 | } else { | |
2256 | lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb); | |
2257 | } | |
1da177e4 | 2258 | |
50ad076b | 2259 | netdev_tx_sent_queue(txq, bytes_sent); |
d8a0f1b0 | 2260 | |
0977f817 | 2261 | /* We can work in parallel with gfar_clean_tx_ring(), except |
a3bc1f11 AV |
2262 | * when modifying num_txbdfree. Note that we didn't grab the lock |
2263 | * when we were reading the num_txbdfree and checking for available | |
2264 | * space, that's because outside of this function it can only grow, | |
2265 | * and once we've got needed space, it cannot suddenly disappear. | |
2266 | * | |
2267 | * The lock also protects us from gfar_error(), which can modify | |
2268 | * regs->tstat and thus retrigger the transfers, which is why we | |
2269 | * also must grab the lock before setting ready bit for the first | |
2270 | * to be transmitted BD. | |
2271 | */ | |
2272 | spin_lock_irqsave(&tx_queue->txlock, flags); | |
2273 | ||
0977f817 | 2274 | /* The powerpc-specific eieio() is used, as wmb() has too strong |
3b6330ce SW |
2275 | * semantics (it requires synchronization between cacheable and |
2276 | * uncacheable mappings, which eieio doesn't provide and which we | |
2277 | * don't need), thus requiring a more expensive sync instruction. At | |
2278 | * some point, the set of architecture-independent barrier functions | |
2279 | * should be expanded to include weaker barriers. | |
2280 | */ | |
3b6330ce | 2281 | eieio(); |
7f7f5316 | 2282 | |
4669bc90 DH |
2283 | txbdp_start->lstatus = lstatus; |
2284 | ||
0eddba52 AV |
2285 | eieio(); /* force lstatus write before tx_skbuff */ |
2286 | ||
2287 | tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb; | |
2288 | ||
4669bc90 | 2289 | /* Update the current skb pointer to the next entry we will use |
0977f817 JC |
2290 | * (wrapping if necessary) |
2291 | */ | |
a12f801d | 2292 | tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) & |
bc4598bc | 2293 | TX_RING_MOD_MASK(tx_queue->tx_ring_size); |
4669bc90 | 2294 | |
a12f801d | 2295 | tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size); |
4669bc90 DH |
2296 | |
2297 | /* reduce TxBD free count */ | |
f0ee7acf | 2298 | tx_queue->num_txbdfree -= (nr_txbds); |
1da177e4 LT |
2299 | |
2300 | /* If the next BD still needs to be cleaned up, then the bds | |
0977f817 JC |
2301 | * are full. We need to tell the kernel to stop sending us stuff. |
2302 | */ | |
a12f801d | 2303 | if (!tx_queue->num_txbdfree) { |
fba4ed03 | 2304 | netif_tx_stop_queue(txq); |
1da177e4 | 2305 | |
09f75cd7 | 2306 | dev->stats.tx_fifo_errors++; |
1da177e4 LT |
2307 | } |
2308 | ||
1da177e4 | 2309 | /* Tell the DMA to go go go */ |
fba4ed03 | 2310 | gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex); |
1da177e4 LT |
2311 | |
2312 | /* Unlock priv */ | |
a12f801d | 2313 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
1da177e4 | 2314 | |
54dc79fe | 2315 | return NETDEV_TX_OK; |
1da177e4 LT |
2316 | } |
2317 | ||
2318 | /* Stops the kernel queue, and halts the controller */ | |
2319 | static int gfar_close(struct net_device *dev) | |
2320 | { | |
2321 | struct gfar_private *priv = netdev_priv(dev); | |
bea3348e | 2322 | |
46ceb60c | 2323 | disable_napi(priv); |
bea3348e | 2324 | |
ab939905 | 2325 | cancel_work_sync(&priv->reset_task); |
1da177e4 LT |
2326 | stop_gfar(dev); |
2327 | ||
bb40dcbb AF |
2328 | /* Disconnect from the PHY */ |
2329 | phy_disconnect(priv->phydev); | |
2330 | priv->phydev = NULL; | |
1da177e4 | 2331 | |
fba4ed03 | 2332 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2333 | |
2334 | return 0; | |
2335 | } | |
2336 | ||
1da177e4 | 2337 | /* Changes the mac address if the controller is not running. */ |
f162b9d5 | 2338 | static int gfar_set_mac_address(struct net_device *dev) |
1da177e4 | 2339 | { |
7f7f5316 | 2340 | gfar_set_mac_for_addr(dev, 0, dev->dev_addr); |
1da177e4 LT |
2341 | |
2342 | return 0; | |
2343 | } | |
2344 | ||
f3dc1586 SP |
2345 | /* Check if rx parser should be activated */ |
2346 | void gfar_check_rx_parser_mode(struct gfar_private *priv) | |
2347 | { | |
2348 | struct gfar __iomem *regs; | |
2349 | u32 tempval; | |
2350 | ||
2351 | regs = priv->gfargrp[0].regs; | |
2352 | ||
2353 | tempval = gfar_read(®s->rctrl); | |
2354 | /* If parse is no longer required, then disable parser */ | |
ba779711 | 2355 | if (tempval & RCTRL_REQ_PARSER) { |
f3dc1586 | 2356 | tempval |= RCTRL_PRSDEP_INIT; |
ba779711 CM |
2357 | priv->uses_rxfcb = 1; |
2358 | } else { | |
f3dc1586 | 2359 | tempval &= ~RCTRL_PRSDEP_INIT; |
ba779711 CM |
2360 | priv->uses_rxfcb = 0; |
2361 | } | |
f3dc1586 SP |
2362 | gfar_write(®s->rctrl, tempval); |
2363 | } | |
2364 | ||
0bbaf069 | 2365 | /* Enables and disables VLAN insertion/extraction */ |
c8f44aff | 2366 | void gfar_vlan_mode(struct net_device *dev, netdev_features_t features) |
0bbaf069 KG |
2367 | { |
2368 | struct gfar_private *priv = netdev_priv(dev); | |
f4983704 | 2369 | struct gfar __iomem *regs = NULL; |
0bbaf069 KG |
2370 | unsigned long flags; |
2371 | u32 tempval; | |
2372 | ||
46ceb60c | 2373 | regs = priv->gfargrp[0].regs; |
fba4ed03 SG |
2374 | local_irq_save(flags); |
2375 | lock_rx_qs(priv); | |
0bbaf069 | 2376 | |
f646968f | 2377 | if (features & NETIF_F_HW_VLAN_CTAG_TX) { |
0bbaf069 | 2378 | /* Enable VLAN tag insertion */ |
f4983704 | 2379 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2380 | tempval |= TCTRL_VLINS; |
f4983704 | 2381 | gfar_write(®s->tctrl, tempval); |
0bbaf069 KG |
2382 | } else { |
2383 | /* Disable VLAN tag insertion */ | |
f4983704 | 2384 | tempval = gfar_read(®s->tctrl); |
0bbaf069 | 2385 | tempval &= ~TCTRL_VLINS; |
f4983704 | 2386 | gfar_write(®s->tctrl, tempval); |
87c288c6 | 2387 | } |
0bbaf069 | 2388 | |
f646968f | 2389 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
87c288c6 JP |
2390 | /* Enable VLAN tag extraction */ |
2391 | tempval = gfar_read(®s->rctrl); | |
2392 | tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT); | |
2393 | gfar_write(®s->rctrl, tempval); | |
ba779711 | 2394 | priv->uses_rxfcb = 1; |
87c288c6 | 2395 | } else { |
0bbaf069 | 2396 | /* Disable VLAN tag extraction */ |
f4983704 | 2397 | tempval = gfar_read(®s->rctrl); |
0bbaf069 | 2398 | tempval &= ~RCTRL_VLEX; |
f4983704 | 2399 | gfar_write(®s->rctrl, tempval); |
f3dc1586 SP |
2400 | |
2401 | gfar_check_rx_parser_mode(priv); | |
0bbaf069 KG |
2402 | } |
2403 | ||
77ecaf2d DH |
2404 | gfar_change_mtu(dev, dev->mtu); |
2405 | ||
fba4ed03 SG |
2406 | unlock_rx_qs(priv); |
2407 | local_irq_restore(flags); | |
0bbaf069 KG |
2408 | } |
2409 | ||
1da177e4 LT |
2410 | static int gfar_change_mtu(struct net_device *dev, int new_mtu) |
2411 | { | |
2412 | int tempsize, tempval; | |
2413 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 2414 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 | 2415 | int oldsize = priv->rx_buffer_size; |
0bbaf069 KG |
2416 | int frame_size = new_mtu + ETH_HLEN; |
2417 | ||
1da177e4 | 2418 | if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) { |
59deab26 | 2419 | netif_err(priv, drv, dev, "Invalid MTU setting\n"); |
1da177e4 LT |
2420 | return -EINVAL; |
2421 | } | |
2422 | ||
ba779711 | 2423 | if (priv->uses_rxfcb) |
77ecaf2d DH |
2424 | frame_size += GMAC_FCB_LEN; |
2425 | ||
2426 | frame_size += priv->padding; | |
2427 | ||
bc4598bc JC |
2428 | tempsize = (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) + |
2429 | INCREMENTAL_BUFFER_SIZE; | |
1da177e4 LT |
2430 | |
2431 | /* Only stop and start the controller if it isn't already | |
0977f817 JC |
2432 | * stopped, and we changed something |
2433 | */ | |
1da177e4 LT |
2434 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) |
2435 | stop_gfar(dev); | |
2436 | ||
2437 | priv->rx_buffer_size = tempsize; | |
2438 | ||
2439 | dev->mtu = new_mtu; | |
2440 | ||
f4983704 SG |
2441 | gfar_write(®s->mrblr, priv->rx_buffer_size); |
2442 | gfar_write(®s->maxfrm, priv->rx_buffer_size); | |
1da177e4 LT |
2443 | |
2444 | /* If the mtu is larger than the max size for standard | |
2445 | * ethernet frames (ie, a jumbo frame), then set maccfg2 | |
0977f817 JC |
2446 | * to allow huge frames, and to check the length |
2447 | */ | |
f4983704 | 2448 | tempval = gfar_read(®s->maccfg2); |
1da177e4 | 2449 | |
7d350977 | 2450 | if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE || |
bc4598bc | 2451 | gfar_has_errata(priv, GFAR_ERRATA_74)) |
1da177e4 LT |
2452 | tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); |
2453 | else | |
2454 | tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK); | |
2455 | ||
f4983704 | 2456 | gfar_write(®s->maccfg2, tempval); |
1da177e4 LT |
2457 | |
2458 | if ((oldsize != tempsize) && (dev->flags & IFF_UP)) | |
2459 | startup_gfar(dev); | |
2460 | ||
2461 | return 0; | |
2462 | } | |
2463 | ||
ab939905 | 2464 | /* gfar_reset_task gets scheduled when a packet has not been |
1da177e4 LT |
2465 | * transmitted after a set amount of time. |
2466 | * For now, assume that clearing out all the structures, and | |
ab939905 SS |
2467 | * starting over will fix the problem. |
2468 | */ | |
2469 | static void gfar_reset_task(struct work_struct *work) | |
1da177e4 | 2470 | { |
ab939905 | 2471 | struct gfar_private *priv = container_of(work, struct gfar_private, |
bc4598bc | 2472 | reset_task); |
4826857f | 2473 | struct net_device *dev = priv->ndev; |
1da177e4 LT |
2474 | |
2475 | if (dev->flags & IFF_UP) { | |
fba4ed03 | 2476 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
2477 | stop_gfar(dev); |
2478 | startup_gfar(dev); | |
fba4ed03 | 2479 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
2480 | } |
2481 | ||
263ba320 | 2482 | netif_tx_schedule_all(dev); |
1da177e4 LT |
2483 | } |
2484 | ||
ab939905 SS |
2485 | static void gfar_timeout(struct net_device *dev) |
2486 | { | |
2487 | struct gfar_private *priv = netdev_priv(dev); | |
2488 | ||
2489 | dev->stats.tx_errors++; | |
2490 | schedule_work(&priv->reset_task); | |
2491 | } | |
2492 | ||
acbc0f03 EL |
2493 | static void gfar_align_skb(struct sk_buff *skb) |
2494 | { | |
2495 | /* We need the data buffer to be aligned properly. We will reserve | |
2496 | * as many bytes as needed to align the data properly | |
2497 | */ | |
2498 | skb_reserve(skb, RXBUF_ALIGNMENT - | |
bc4598bc | 2499 | (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1))); |
acbc0f03 EL |
2500 | } |
2501 | ||
1da177e4 | 2502 | /* Interrupt Handler for Transmit complete */ |
c233cf40 | 2503 | static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue) |
1da177e4 | 2504 | { |
a12f801d | 2505 | struct net_device *dev = tx_queue->dev; |
d8a0f1b0 | 2506 | struct netdev_queue *txq; |
d080cd63 | 2507 | struct gfar_private *priv = netdev_priv(dev); |
f0ee7acf | 2508 | struct txbd8 *bdp, *next = NULL; |
4669bc90 | 2509 | struct txbd8 *lbdp = NULL; |
a12f801d | 2510 | struct txbd8 *base = tx_queue->tx_bd_base; |
4669bc90 DH |
2511 | struct sk_buff *skb; |
2512 | int skb_dirtytx; | |
a12f801d | 2513 | int tx_ring_size = tx_queue->tx_ring_size; |
f0ee7acf | 2514 | int frags = 0, nr_txbds = 0; |
4669bc90 | 2515 | int i; |
d080cd63 | 2516 | int howmany = 0; |
d8a0f1b0 PG |
2517 | int tqi = tx_queue->qindex; |
2518 | unsigned int bytes_sent = 0; | |
4669bc90 | 2519 | u32 lstatus; |
f0ee7acf | 2520 | size_t buflen; |
1da177e4 | 2521 | |
d8a0f1b0 | 2522 | txq = netdev_get_tx_queue(dev, tqi); |
a12f801d SG |
2523 | bdp = tx_queue->dirty_tx; |
2524 | skb_dirtytx = tx_queue->skb_dirtytx; | |
1da177e4 | 2525 | |
a12f801d | 2526 | while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) { |
a3bc1f11 AV |
2527 | unsigned long flags; |
2528 | ||
4669bc90 | 2529 | frags = skb_shinfo(skb)->nr_frags; |
f0ee7acf | 2530 | |
0977f817 | 2531 | /* When time stamping, one additional TxBD must be freed. |
f0ee7acf MR |
2532 | * Also, we need to dma_unmap_single() the TxPAL. |
2533 | */ | |
2244d07b | 2534 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) |
f0ee7acf MR |
2535 | nr_txbds = frags + 2; |
2536 | else | |
2537 | nr_txbds = frags + 1; | |
2538 | ||
2539 | lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size); | |
1da177e4 | 2540 | |
4669bc90 | 2541 | lstatus = lbdp->lstatus; |
1da177e4 | 2542 | |
4669bc90 DH |
2543 | /* Only clean completed frames */ |
2544 | if ((lstatus & BD_LFLAG(TXBD_READY)) && | |
bc4598bc | 2545 | (lstatus & BD_LENGTH_MASK)) |
4669bc90 DH |
2546 | break; |
2547 | ||
2244d07b | 2548 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf | 2549 | next = next_txbd(bdp, base, tx_ring_size); |
9c4886e5 | 2550 | buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN; |
f0ee7acf MR |
2551 | } else |
2552 | buflen = bdp->length; | |
2553 | ||
369ec162 | 2554 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2555 | buflen, DMA_TO_DEVICE); |
f0ee7acf | 2556 | |
2244d07b | 2557 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) { |
f0ee7acf MR |
2558 | struct skb_shared_hwtstamps shhwtstamps; |
2559 | u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7); | |
bc4598bc | 2560 | |
f0ee7acf MR |
2561 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
2562 | shhwtstamps.hwtstamp = ns_to_ktime(*ns); | |
9c4886e5 | 2563 | skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN); |
f0ee7acf MR |
2564 | skb_tstamp_tx(skb, &shhwtstamps); |
2565 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); | |
2566 | bdp = next; | |
2567 | } | |
81183059 | 2568 | |
4669bc90 DH |
2569 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2570 | bdp = next_txbd(bdp, base, tx_ring_size); | |
d080cd63 | 2571 | |
4669bc90 | 2572 | for (i = 0; i < frags; i++) { |
369ec162 | 2573 | dma_unmap_page(priv->dev, bdp->bufPtr, |
bc4598bc | 2574 | bdp->length, DMA_TO_DEVICE); |
4669bc90 DH |
2575 | bdp->lstatus &= BD_LFLAG(TXBD_WRAP); |
2576 | bdp = next_txbd(bdp, base, tx_ring_size); | |
2577 | } | |
1da177e4 | 2578 | |
50ad076b | 2579 | bytes_sent += GFAR_CB(skb)->bytes_sent; |
d8a0f1b0 | 2580 | |
acb600de | 2581 | dev_kfree_skb_any(skb); |
0fd56bb5 | 2582 | |
a12f801d | 2583 | tx_queue->tx_skbuff[skb_dirtytx] = NULL; |
d080cd63 | 2584 | |
4669bc90 | 2585 | skb_dirtytx = (skb_dirtytx + 1) & |
bc4598bc | 2586 | TX_RING_MOD_MASK(tx_ring_size); |
4669bc90 DH |
2587 | |
2588 | howmany++; | |
a3bc1f11 | 2589 | spin_lock_irqsave(&tx_queue->txlock, flags); |
f0ee7acf | 2590 | tx_queue->num_txbdfree += nr_txbds; |
a3bc1f11 | 2591 | spin_unlock_irqrestore(&tx_queue->txlock, flags); |
4669bc90 | 2592 | } |
1da177e4 | 2593 | |
4669bc90 | 2594 | /* If we freed a buffer, we can restart transmission, if necessary */ |
5407b14c | 2595 | if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree) |
d8a0f1b0 | 2596 | netif_wake_subqueue(dev, tqi); |
1da177e4 | 2597 | |
4669bc90 | 2598 | /* Update dirty indicators */ |
a12f801d SG |
2599 | tx_queue->skb_dirtytx = skb_dirtytx; |
2600 | tx_queue->dirty_tx = bdp; | |
1da177e4 | 2601 | |
d8a0f1b0 | 2602 | netdev_tx_completed_queue(txq, howmany, bytes_sent); |
d080cd63 DH |
2603 | } |
2604 | ||
f4983704 | 2605 | static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp) |
d080cd63 | 2606 | { |
a6d0b91a AV |
2607 | unsigned long flags; |
2608 | ||
fba4ed03 SG |
2609 | spin_lock_irqsave(&gfargrp->grplock, flags); |
2610 | if (napi_schedule_prep(&gfargrp->napi)) { | |
f4983704 | 2611 | gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED); |
fba4ed03 | 2612 | __napi_schedule(&gfargrp->napi); |
8707bdd4 | 2613 | } else { |
0977f817 | 2614 | /* Clear IEVENT, so interrupts aren't called again |
8707bdd4 JP |
2615 | * because of the packets that have already arrived. |
2616 | */ | |
f4983704 | 2617 | gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK); |
2f448911 | 2618 | } |
fba4ed03 | 2619 | spin_unlock_irqrestore(&gfargrp->grplock, flags); |
a6d0b91a | 2620 | |
8c7396ae | 2621 | } |
1da177e4 | 2622 | |
8c7396ae | 2623 | /* Interrupt Handler for Transmit complete */ |
f4983704 | 2624 | static irqreturn_t gfar_transmit(int irq, void *grp_id) |
8c7396ae | 2625 | { |
f4983704 | 2626 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2627 | return IRQ_HANDLED; |
2628 | } | |
2629 | ||
a12f801d | 2630 | static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp, |
bc4598bc | 2631 | struct sk_buff *skb) |
815b97c6 | 2632 | { |
a12f801d | 2633 | struct net_device *dev = rx_queue->dev; |
815b97c6 | 2634 | struct gfar_private *priv = netdev_priv(dev); |
8a102fe0 | 2635 | dma_addr_t buf; |
815b97c6 | 2636 | |
369ec162 | 2637 | buf = dma_map_single(priv->dev, skb->data, |
8a102fe0 | 2638 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
a12f801d | 2639 | gfar_init_rxbdp(rx_queue, bdp, buf); |
815b97c6 AF |
2640 | } |
2641 | ||
2281a0f3 | 2642 | static struct sk_buff *gfar_alloc_skb(struct net_device *dev) |
1da177e4 LT |
2643 | { |
2644 | struct gfar_private *priv = netdev_priv(dev); | |
acb600de | 2645 | struct sk_buff *skb; |
1da177e4 | 2646 | |
acbc0f03 | 2647 | skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT); |
815b97c6 | 2648 | if (!skb) |
1da177e4 LT |
2649 | return NULL; |
2650 | ||
acbc0f03 | 2651 | gfar_align_skb(skb); |
7f7f5316 | 2652 | |
acbc0f03 EL |
2653 | return skb; |
2654 | } | |
2655 | ||
2281a0f3 | 2656 | struct sk_buff *gfar_new_skb(struct net_device *dev) |
acbc0f03 | 2657 | { |
acb600de | 2658 | return gfar_alloc_skb(dev); |
1da177e4 LT |
2659 | } |
2660 | ||
298e1a9e | 2661 | static inline void count_errors(unsigned short status, struct net_device *dev) |
1da177e4 | 2662 | { |
298e1a9e | 2663 | struct gfar_private *priv = netdev_priv(dev); |
09f75cd7 | 2664 | struct net_device_stats *stats = &dev->stats; |
1da177e4 LT |
2665 | struct gfar_extra_stats *estats = &priv->extra_stats; |
2666 | ||
0977f817 | 2667 | /* If the packet was truncated, none of the other errors matter */ |
1da177e4 LT |
2668 | if (status & RXBD_TRUNCATED) { |
2669 | stats->rx_length_errors++; | |
2670 | ||
212079df | 2671 | atomic64_inc(&estats->rx_trunc); |
1da177e4 LT |
2672 | |
2673 | return; | |
2674 | } | |
2675 | /* Count the errors, if there were any */ | |
2676 | if (status & (RXBD_LARGE | RXBD_SHORT)) { | |
2677 | stats->rx_length_errors++; | |
2678 | ||
2679 | if (status & RXBD_LARGE) | |
212079df | 2680 | atomic64_inc(&estats->rx_large); |
1da177e4 | 2681 | else |
212079df | 2682 | atomic64_inc(&estats->rx_short); |
1da177e4 LT |
2683 | } |
2684 | if (status & RXBD_NONOCTET) { | |
2685 | stats->rx_frame_errors++; | |
212079df | 2686 | atomic64_inc(&estats->rx_nonoctet); |
1da177e4 LT |
2687 | } |
2688 | if (status & RXBD_CRCERR) { | |
212079df | 2689 | atomic64_inc(&estats->rx_crcerr); |
1da177e4 LT |
2690 | stats->rx_crc_errors++; |
2691 | } | |
2692 | if (status & RXBD_OVERRUN) { | |
212079df | 2693 | atomic64_inc(&estats->rx_overrun); |
1da177e4 LT |
2694 | stats->rx_crc_errors++; |
2695 | } | |
2696 | } | |
2697 | ||
f4983704 | 2698 | irqreturn_t gfar_receive(int irq, void *grp_id) |
1da177e4 | 2699 | { |
f4983704 | 2700 | gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id); |
1da177e4 LT |
2701 | return IRQ_HANDLED; |
2702 | } | |
2703 | ||
0bbaf069 KG |
2704 | static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb) |
2705 | { | |
2706 | /* If valid headers were found, and valid sums | |
2707 | * were verified, then we tell the kernel that no | |
0977f817 JC |
2708 | * checksumming is necessary. Otherwise, it is [FIXME] |
2709 | */ | |
7f7f5316 | 2710 | if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU)) |
0bbaf069 KG |
2711 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
2712 | else | |
bc8acf2c | 2713 | skb_checksum_none_assert(skb); |
0bbaf069 KG |
2714 | } |
2715 | ||
2716 | ||
0977f817 | 2717 | /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */ |
61db26c6 CM |
2718 | static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, |
2719 | int amount_pull, struct napi_struct *napi) | |
1da177e4 LT |
2720 | { |
2721 | struct gfar_private *priv = netdev_priv(dev); | |
0bbaf069 | 2722 | struct rxfcb *fcb = NULL; |
1da177e4 | 2723 | |
2c2db48a DH |
2724 | /* fcb is at the beginning if exists */ |
2725 | fcb = (struct rxfcb *)skb->data; | |
0bbaf069 | 2726 | |
0977f817 JC |
2727 | /* Remove the FCB from the skb |
2728 | * Remove the padded bytes, if there are any | |
2729 | */ | |
f74dac08 SG |
2730 | if (amount_pull) { |
2731 | skb_record_rx_queue(skb, fcb->rq); | |
2c2db48a | 2732 | skb_pull(skb, amount_pull); |
f74dac08 | 2733 | } |
0bbaf069 | 2734 | |
cc772ab7 MR |
2735 | /* Get receive timestamp from the skb */ |
2736 | if (priv->hwts_rx_en) { | |
2737 | struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb); | |
2738 | u64 *ns = (u64 *) skb->data; | |
bc4598bc | 2739 | |
cc772ab7 MR |
2740 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
2741 | shhwtstamps->hwtstamp = ns_to_ktime(*ns); | |
2742 | } | |
2743 | ||
2744 | if (priv->padding) | |
2745 | skb_pull(skb, priv->padding); | |
2746 | ||
8b3afe95 | 2747 | if (dev->features & NETIF_F_RXCSUM) |
2c2db48a | 2748 | gfar_rx_checksum(skb, fcb); |
0bbaf069 | 2749 | |
2c2db48a DH |
2750 | /* Tell the skb what kind of packet this is */ |
2751 | skb->protocol = eth_type_trans(skb, dev); | |
1da177e4 | 2752 | |
f646968f | 2753 | /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here. |
32f7fd44 JP |
2754 | * Even if vlan rx accel is disabled, on some chips |
2755 | * RXFCB_VLN is pseudo randomly set. | |
2756 | */ | |
f646968f | 2757 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
32f7fd44 | 2758 | fcb->flags & RXFCB_VLN) |
e5905c83 | 2759 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), fcb->vlctl); |
87c288c6 | 2760 | |
2c2db48a | 2761 | /* Send the packet up the stack */ |
953d2768 | 2762 | napi_gro_receive(napi, skb); |
0bbaf069 | 2763 | |
1da177e4 LT |
2764 | } |
2765 | ||
2766 | /* gfar_clean_rx_ring() -- Processes each frame in the rx ring | |
2281a0f3 JC |
2767 | * until the budget/quota has been reached. Returns the number |
2768 | * of frames handled | |
1da177e4 | 2769 | */ |
a12f801d | 2770 | int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit) |
1da177e4 | 2771 | { |
a12f801d | 2772 | struct net_device *dev = rx_queue->dev; |
31de198b | 2773 | struct rxbd8 *bdp, *base; |
1da177e4 | 2774 | struct sk_buff *skb; |
2c2db48a DH |
2775 | int pkt_len; |
2776 | int amount_pull; | |
1da177e4 LT |
2777 | int howmany = 0; |
2778 | struct gfar_private *priv = netdev_priv(dev); | |
2779 | ||
2780 | /* Get the first full descriptor */ | |
a12f801d SG |
2781 | bdp = rx_queue->cur_rx; |
2782 | base = rx_queue->rx_bd_base; | |
1da177e4 | 2783 | |
ba779711 | 2784 | amount_pull = priv->uses_rxfcb ? GMAC_FCB_LEN : 0; |
2c2db48a | 2785 | |
1da177e4 | 2786 | while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) { |
815b97c6 | 2787 | struct sk_buff *newskb; |
bc4598bc | 2788 | |
3b6330ce | 2789 | rmb(); |
815b97c6 AF |
2790 | |
2791 | /* Add another skb for the future */ | |
2792 | newskb = gfar_new_skb(dev); | |
2793 | ||
a12f801d | 2794 | skb = rx_queue->rx_skbuff[rx_queue->skb_currx]; |
1da177e4 | 2795 | |
369ec162 | 2796 | dma_unmap_single(priv->dev, bdp->bufPtr, |
bc4598bc | 2797 | priv->rx_buffer_size, DMA_FROM_DEVICE); |
81183059 | 2798 | |
63b88b90 | 2799 | if (unlikely(!(bdp->status & RXBD_ERR) && |
bc4598bc | 2800 | bdp->length > priv->rx_buffer_size)) |
63b88b90 AV |
2801 | bdp->status = RXBD_LARGE; |
2802 | ||
815b97c6 AF |
2803 | /* We drop the frame if we failed to allocate a new buffer */ |
2804 | if (unlikely(!newskb || !(bdp->status & RXBD_LAST) || | |
bc4598bc | 2805 | bdp->status & RXBD_ERR)) { |
815b97c6 AF |
2806 | count_errors(bdp->status, dev); |
2807 | ||
2808 | if (unlikely(!newskb)) | |
2809 | newskb = skb; | |
acbc0f03 | 2810 | else if (skb) |
acb600de | 2811 | dev_kfree_skb(skb); |
815b97c6 | 2812 | } else { |
1da177e4 | 2813 | /* Increment the number of packets */ |
a7f38041 | 2814 | rx_queue->stats.rx_packets++; |
1da177e4 LT |
2815 | howmany++; |
2816 | ||
2c2db48a DH |
2817 | if (likely(skb)) { |
2818 | pkt_len = bdp->length - ETH_FCS_LEN; | |
2819 | /* Remove the FCS from the packet length */ | |
2820 | skb_put(skb, pkt_len); | |
a7f38041 | 2821 | rx_queue->stats.rx_bytes += pkt_len; |
f74dac08 | 2822 | skb_record_rx_queue(skb, rx_queue->qindex); |
cd754a57 | 2823 | gfar_process_frame(dev, skb, amount_pull, |
bc4598bc | 2824 | &rx_queue->grp->napi); |
2c2db48a DH |
2825 | |
2826 | } else { | |
59deab26 | 2827 | netif_warn(priv, rx_err, dev, "Missing skb!\n"); |
a7f38041 | 2828 | rx_queue->stats.rx_dropped++; |
212079df | 2829 | atomic64_inc(&priv->extra_stats.rx_skbmissing); |
2c2db48a | 2830 | } |
1da177e4 | 2831 | |
1da177e4 LT |
2832 | } |
2833 | ||
a12f801d | 2834 | rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb; |
1da177e4 | 2835 | |
815b97c6 | 2836 | /* Setup the new bdp */ |
a12f801d | 2837 | gfar_new_rxbdp(rx_queue, bdp, newskb); |
1da177e4 LT |
2838 | |
2839 | /* Update to the next pointer */ | |
a12f801d | 2840 | bdp = next_bd(bdp, base, rx_queue->rx_ring_size); |
1da177e4 LT |
2841 | |
2842 | /* update to point at the next skb */ | |
bc4598bc JC |
2843 | rx_queue->skb_currx = (rx_queue->skb_currx + 1) & |
2844 | RX_RING_MOD_MASK(rx_queue->rx_ring_size); | |
1da177e4 LT |
2845 | } |
2846 | ||
2847 | /* Update the current rxbd pointer to be the next one */ | |
a12f801d | 2848 | rx_queue->cur_rx = bdp; |
1da177e4 | 2849 | |
1da177e4 LT |
2850 | return howmany; |
2851 | } | |
2852 | ||
5eaedf31 CM |
2853 | static int gfar_poll_sq(struct napi_struct *napi, int budget) |
2854 | { | |
2855 | struct gfar_priv_grp *gfargrp = | |
2856 | container_of(napi, struct gfar_priv_grp, napi); | |
2857 | struct gfar __iomem *regs = gfargrp->regs; | |
2858 | struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0]; | |
2859 | struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0]; | |
2860 | int work_done = 0; | |
2861 | ||
2862 | /* Clear IEVENT, so interrupts aren't called again | |
2863 | * because of the packets that have already arrived | |
2864 | */ | |
2865 | gfar_write(®s->ievent, IEVENT_RTX_MASK); | |
2866 | ||
2867 | /* run Tx cleanup to completion */ | |
2868 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) | |
2869 | gfar_clean_tx_ring(tx_queue); | |
2870 | ||
2871 | work_done = gfar_clean_rx_ring(rx_queue, budget); | |
2872 | ||
2873 | if (work_done < budget) { | |
2874 | napi_complete(napi); | |
2875 | /* Clear the halt bit in RSTAT */ | |
2876 | gfar_write(®s->rstat, gfargrp->rstat); | |
2877 | ||
2878 | gfar_write(®s->imask, IMASK_DEFAULT); | |
2879 | ||
2880 | /* If we are coalescing interrupts, update the timer | |
2881 | * Otherwise, clear it | |
2882 | */ | |
2883 | gfar_write(®s->txic, 0); | |
2884 | if (likely(tx_queue->txcoalescing)) | |
2885 | gfar_write(®s->txic, tx_queue->txic); | |
2886 | ||
2887 | gfar_write(®s->rxic, 0); | |
2888 | if (unlikely(rx_queue->rxcoalescing)) | |
2889 | gfar_write(®s->rxic, rx_queue->rxic); | |
2890 | } | |
2891 | ||
2892 | return work_done; | |
2893 | } | |
2894 | ||
bea3348e | 2895 | static int gfar_poll(struct napi_struct *napi, int budget) |
1da177e4 | 2896 | { |
bc4598bc JC |
2897 | struct gfar_priv_grp *gfargrp = |
2898 | container_of(napi, struct gfar_priv_grp, napi); | |
fba4ed03 | 2899 | struct gfar_private *priv = gfargrp->priv; |
46ceb60c | 2900 | struct gfar __iomem *regs = gfargrp->regs; |
a12f801d | 2901 | struct gfar_priv_tx_q *tx_queue = NULL; |
fba4ed03 | 2902 | struct gfar_priv_rx_q *rx_queue = NULL; |
c233cf40 | 2903 | int work_done = 0, work_done_per_q = 0; |
39c0a0d5 | 2904 | int i, budget_per_q = 0; |
c233cf40 | 2905 | int has_tx_work; |
6be5ed3f CM |
2906 | unsigned long rstat_rxf; |
2907 | int num_act_queues; | |
fba4ed03 | 2908 | |
8c7396ae | 2909 | /* Clear IEVENT, so interrupts aren't called again |
0977f817 JC |
2910 | * because of the packets that have already arrived |
2911 | */ | |
f4983704 | 2912 | gfar_write(®s->ievent, IEVENT_RTX_MASK); |
8c7396ae | 2913 | |
6be5ed3f CM |
2914 | rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK; |
2915 | ||
2916 | num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS); | |
2917 | if (num_act_queues) | |
2918 | budget_per_q = budget/num_act_queues; | |
2919 | ||
c233cf40 CM |
2920 | while (1) { |
2921 | has_tx_work = 0; | |
2922 | for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) { | |
2923 | tx_queue = priv->tx_queue[i]; | |
2924 | /* run Tx cleanup to completion */ | |
2925 | if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) { | |
2926 | gfar_clean_tx_ring(tx_queue); | |
2927 | has_tx_work = 1; | |
2928 | } | |
2929 | } | |
fba4ed03 | 2930 | |
984b3f57 | 2931 | for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) { |
6be5ed3f CM |
2932 | /* skip queue if not active */ |
2933 | if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i))) | |
fba4ed03 | 2934 | continue; |
c233cf40 | 2935 | |
fba4ed03 | 2936 | rx_queue = priv->rx_queue[i]; |
c233cf40 CM |
2937 | work_done_per_q = |
2938 | gfar_clean_rx_ring(rx_queue, budget_per_q); | |
2939 | work_done += work_done_per_q; | |
2940 | ||
2941 | /* finished processing this queue */ | |
2942 | if (work_done_per_q < budget_per_q) { | |
6be5ed3f CM |
2943 | /* clear active queue hw indication */ |
2944 | gfar_write(®s->rstat, | |
2945 | RSTAT_CLEAR_RXF0 >> i); | |
2946 | rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i); | |
2947 | num_act_queues--; | |
2948 | ||
2949 | if (!num_act_queues) | |
c233cf40 CM |
2950 | break; |
2951 | /* recompute budget per Rx queue */ | |
2952 | budget_per_q = | |
6be5ed3f | 2953 | (budget - work_done) / num_act_queues; |
fba4ed03 SG |
2954 | } |
2955 | } | |
1da177e4 | 2956 | |
c233cf40 CM |
2957 | if (work_done >= budget) |
2958 | break; | |
42199884 | 2959 | |
6be5ed3f | 2960 | if (!num_act_queues && !has_tx_work) { |
1da177e4 | 2961 | |
c233cf40 | 2962 | napi_complete(napi); |
1da177e4 | 2963 | |
c233cf40 CM |
2964 | /* Clear the halt bit in RSTAT */ |
2965 | gfar_write(®s->rstat, gfargrp->rstat); | |
1da177e4 | 2966 | |
c233cf40 CM |
2967 | gfar_write(®s->imask, IMASK_DEFAULT); |
2968 | ||
2969 | /* If we are coalescing interrupts, update the timer | |
2970 | * Otherwise, clear it | |
2971 | */ | |
2972 | gfar_configure_coalescing(priv, gfargrp->rx_bit_map, | |
2973 | gfargrp->tx_bit_map); | |
2974 | break; | |
2975 | } | |
1da177e4 LT |
2976 | } |
2977 | ||
c233cf40 | 2978 | return work_done; |
1da177e4 | 2979 | } |
1da177e4 | 2980 | |
f2d71c2d | 2981 | #ifdef CONFIG_NET_POLL_CONTROLLER |
0977f817 | 2982 | /* Polling 'interrupt' - used by things like netconsole to send skbs |
f2d71c2d VW |
2983 | * without having to re-enable interrupts. It's not called while |
2984 | * the interrupt routine is executing. | |
2985 | */ | |
2986 | static void gfar_netpoll(struct net_device *dev) | |
2987 | { | |
2988 | struct gfar_private *priv = netdev_priv(dev); | |
3a2e16c8 | 2989 | int i; |
f2d71c2d VW |
2990 | |
2991 | /* If the device has multiple interrupts, run tx/rx */ | |
b31a1d8b | 2992 | if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) { |
46ceb60c | 2993 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
2994 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
2995 | ||
2996 | disable_irq(gfar_irq(grp, TX)->irq); | |
2997 | disable_irq(gfar_irq(grp, RX)->irq); | |
2998 | disable_irq(gfar_irq(grp, ER)->irq); | |
2999 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
3000 | enable_irq(gfar_irq(grp, ER)->irq); | |
3001 | enable_irq(gfar_irq(grp, RX)->irq); | |
3002 | enable_irq(gfar_irq(grp, TX)->irq); | |
46ceb60c | 3003 | } |
f2d71c2d | 3004 | } else { |
46ceb60c | 3005 | for (i = 0; i < priv->num_grps; i++) { |
62ed839d PG |
3006 | struct gfar_priv_grp *grp = &priv->gfargrp[i]; |
3007 | ||
3008 | disable_irq(gfar_irq(grp, TX)->irq); | |
3009 | gfar_interrupt(gfar_irq(grp, TX)->irq, grp); | |
3010 | enable_irq(gfar_irq(grp, TX)->irq); | |
43de004b | 3011 | } |
f2d71c2d VW |
3012 | } |
3013 | } | |
3014 | #endif | |
3015 | ||
1da177e4 | 3016 | /* The interrupt handler for devices with one interrupt */ |
f4983704 | 3017 | static irqreturn_t gfar_interrupt(int irq, void *grp_id) |
1da177e4 | 3018 | { |
f4983704 | 3019 | struct gfar_priv_grp *gfargrp = grp_id; |
1da177e4 LT |
3020 | |
3021 | /* Save ievent for future reference */ | |
f4983704 | 3022 | u32 events = gfar_read(&gfargrp->regs->ievent); |
1da177e4 | 3023 | |
1da177e4 | 3024 | /* Check for reception */ |
538cc7ee | 3025 | if (events & IEVENT_RX_MASK) |
f4983704 | 3026 | gfar_receive(irq, grp_id); |
1da177e4 LT |
3027 | |
3028 | /* Check for transmit completion */ | |
538cc7ee | 3029 | if (events & IEVENT_TX_MASK) |
f4983704 | 3030 | gfar_transmit(irq, grp_id); |
1da177e4 | 3031 | |
538cc7ee SS |
3032 | /* Check for errors */ |
3033 | if (events & IEVENT_ERR_MASK) | |
f4983704 | 3034 | gfar_error(irq, grp_id); |
1da177e4 LT |
3035 | |
3036 | return IRQ_HANDLED; | |
3037 | } | |
3038 | ||
23402bdd CM |
3039 | static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv) |
3040 | { | |
3041 | struct phy_device *phydev = priv->phydev; | |
3042 | u32 val = 0; | |
3043 | ||
3044 | if (!phydev->duplex) | |
3045 | return val; | |
3046 | ||
3047 | if (!priv->pause_aneg_en) { | |
3048 | if (priv->tx_pause_en) | |
3049 | val |= MACCFG1_TX_FLOW; | |
3050 | if (priv->rx_pause_en) | |
3051 | val |= MACCFG1_RX_FLOW; | |
3052 | } else { | |
3053 | u16 lcl_adv, rmt_adv; | |
3054 | u8 flowctrl; | |
3055 | /* get link partner capabilities */ | |
3056 | rmt_adv = 0; | |
3057 | if (phydev->pause) | |
3058 | rmt_adv = LPA_PAUSE_CAP; | |
3059 | if (phydev->asym_pause) | |
3060 | rmt_adv |= LPA_PAUSE_ASYM; | |
3061 | ||
3062 | lcl_adv = mii_advertise_flowctrl(phydev->advertising); | |
3063 | ||
3064 | flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); | |
3065 | if (flowctrl & FLOW_CTRL_TX) | |
3066 | val |= MACCFG1_TX_FLOW; | |
3067 | if (flowctrl & FLOW_CTRL_RX) | |
3068 | val |= MACCFG1_RX_FLOW; | |
3069 | } | |
3070 | ||
3071 | return val; | |
3072 | } | |
3073 | ||
1da177e4 LT |
3074 | /* Called every time the controller might need to be made |
3075 | * aware of new link state. The PHY code conveys this | |
bb40dcbb | 3076 | * information through variables in the phydev structure, and this |
1da177e4 LT |
3077 | * function converts those variables into the appropriate |
3078 | * register values, and can bring down the device if needed. | |
3079 | */ | |
3080 | static void adjust_link(struct net_device *dev) | |
3081 | { | |
3082 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3083 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
bb40dcbb AF |
3084 | unsigned long flags; |
3085 | struct phy_device *phydev = priv->phydev; | |
3086 | int new_state = 0; | |
3087 | ||
fba4ed03 SG |
3088 | local_irq_save(flags); |
3089 | lock_tx_qs(priv); | |
3090 | ||
bb40dcbb | 3091 | if (phydev->link) { |
23402bdd | 3092 | u32 tempval1 = gfar_read(®s->maccfg1); |
bb40dcbb | 3093 | u32 tempval = gfar_read(®s->maccfg2); |
7f7f5316 | 3094 | u32 ecntrl = gfar_read(®s->ecntrl); |
1da177e4 | 3095 | |
1da177e4 | 3096 | /* Now we make sure that we can be in full duplex mode. |
0977f817 JC |
3097 | * If not, we operate in half-duplex mode. |
3098 | */ | |
bb40dcbb AF |
3099 | if (phydev->duplex != priv->oldduplex) { |
3100 | new_state = 1; | |
3101 | if (!(phydev->duplex)) | |
1da177e4 | 3102 | tempval &= ~(MACCFG2_FULL_DUPLEX); |
bb40dcbb | 3103 | else |
1da177e4 | 3104 | tempval |= MACCFG2_FULL_DUPLEX; |
1da177e4 | 3105 | |
bb40dcbb | 3106 | priv->oldduplex = phydev->duplex; |
1da177e4 LT |
3107 | } |
3108 | ||
bb40dcbb AF |
3109 | if (phydev->speed != priv->oldspeed) { |
3110 | new_state = 1; | |
3111 | switch (phydev->speed) { | |
1da177e4 | 3112 | case 1000: |
1da177e4 LT |
3113 | tempval = |
3114 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII); | |
f430e49e LY |
3115 | |
3116 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3117 | break; |
3118 | case 100: | |
3119 | case 10: | |
1da177e4 LT |
3120 | tempval = |
3121 | ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII); | |
7f7f5316 AF |
3122 | |
3123 | /* Reduced mode distinguishes | |
0977f817 JC |
3124 | * between 10 and 100 |
3125 | */ | |
7f7f5316 AF |
3126 | if (phydev->speed == SPEED_100) |
3127 | ecntrl |= ECNTRL_R100; | |
3128 | else | |
3129 | ecntrl &= ~(ECNTRL_R100); | |
1da177e4 LT |
3130 | break; |
3131 | default: | |
59deab26 JP |
3132 | netif_warn(priv, link, dev, |
3133 | "Ack! Speed (%d) is not 10/100/1000!\n", | |
3134 | phydev->speed); | |
1da177e4 LT |
3135 | break; |
3136 | } | |
3137 | ||
bb40dcbb | 3138 | priv->oldspeed = phydev->speed; |
1da177e4 LT |
3139 | } |
3140 | ||
23402bdd CM |
3141 | tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW); |
3142 | tempval1 |= gfar_get_flowctrl_cfg(priv); | |
3143 | ||
3144 | gfar_write(®s->maccfg1, tempval1); | |
bb40dcbb | 3145 | gfar_write(®s->maccfg2, tempval); |
7f7f5316 | 3146 | gfar_write(®s->ecntrl, ecntrl); |
bb40dcbb | 3147 | |
1da177e4 | 3148 | if (!priv->oldlink) { |
bb40dcbb | 3149 | new_state = 1; |
1da177e4 | 3150 | priv->oldlink = 1; |
1da177e4 | 3151 | } |
bb40dcbb AF |
3152 | } else if (priv->oldlink) { |
3153 | new_state = 1; | |
3154 | priv->oldlink = 0; | |
3155 | priv->oldspeed = 0; | |
3156 | priv->oldduplex = -1; | |
1da177e4 | 3157 | } |
1da177e4 | 3158 | |
bb40dcbb AF |
3159 | if (new_state && netif_msg_link(priv)) |
3160 | phy_print_status(phydev); | |
fba4ed03 SG |
3161 | unlock_tx_qs(priv); |
3162 | local_irq_restore(flags); | |
bb40dcbb | 3163 | } |
1da177e4 LT |
3164 | |
3165 | /* Update the hash table based on the current list of multicast | |
3166 | * addresses we subscribe to. Also, change the promiscuity of | |
3167 | * the device based on the flags (this function is called | |
0977f817 JC |
3168 | * whenever dev->flags is changed |
3169 | */ | |
1da177e4 LT |
3170 | static void gfar_set_multi(struct net_device *dev) |
3171 | { | |
22bedad3 | 3172 | struct netdev_hw_addr *ha; |
1da177e4 | 3173 | struct gfar_private *priv = netdev_priv(dev); |
46ceb60c | 3174 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
1da177e4 LT |
3175 | u32 tempval; |
3176 | ||
a12f801d | 3177 | if (dev->flags & IFF_PROMISC) { |
1da177e4 LT |
3178 | /* Set RCTRL to PROM */ |
3179 | tempval = gfar_read(®s->rctrl); | |
3180 | tempval |= RCTRL_PROM; | |
3181 | gfar_write(®s->rctrl, tempval); | |
3182 | } else { | |
3183 | /* Set RCTRL to not PROM */ | |
3184 | tempval = gfar_read(®s->rctrl); | |
3185 | tempval &= ~(RCTRL_PROM); | |
3186 | gfar_write(®s->rctrl, tempval); | |
3187 | } | |
6aa20a22 | 3188 | |
a12f801d | 3189 | if (dev->flags & IFF_ALLMULTI) { |
1da177e4 | 3190 | /* Set the hash to rx all multicast frames */ |
0bbaf069 KG |
3191 | gfar_write(®s->igaddr0, 0xffffffff); |
3192 | gfar_write(®s->igaddr1, 0xffffffff); | |
3193 | gfar_write(®s->igaddr2, 0xffffffff); | |
3194 | gfar_write(®s->igaddr3, 0xffffffff); | |
3195 | gfar_write(®s->igaddr4, 0xffffffff); | |
3196 | gfar_write(®s->igaddr5, 0xffffffff); | |
3197 | gfar_write(®s->igaddr6, 0xffffffff); | |
3198 | gfar_write(®s->igaddr7, 0xffffffff); | |
1da177e4 LT |
3199 | gfar_write(®s->gaddr0, 0xffffffff); |
3200 | gfar_write(®s->gaddr1, 0xffffffff); | |
3201 | gfar_write(®s->gaddr2, 0xffffffff); | |
3202 | gfar_write(®s->gaddr3, 0xffffffff); | |
3203 | gfar_write(®s->gaddr4, 0xffffffff); | |
3204 | gfar_write(®s->gaddr5, 0xffffffff); | |
3205 | gfar_write(®s->gaddr6, 0xffffffff); | |
3206 | gfar_write(®s->gaddr7, 0xffffffff); | |
3207 | } else { | |
7f7f5316 AF |
3208 | int em_num; |
3209 | int idx; | |
3210 | ||
1da177e4 | 3211 | /* zero out the hash */ |
0bbaf069 KG |
3212 | gfar_write(®s->igaddr0, 0x0); |
3213 | gfar_write(®s->igaddr1, 0x0); | |
3214 | gfar_write(®s->igaddr2, 0x0); | |
3215 | gfar_write(®s->igaddr3, 0x0); | |
3216 | gfar_write(®s->igaddr4, 0x0); | |
3217 | gfar_write(®s->igaddr5, 0x0); | |
3218 | gfar_write(®s->igaddr6, 0x0); | |
3219 | gfar_write(®s->igaddr7, 0x0); | |
1da177e4 LT |
3220 | gfar_write(®s->gaddr0, 0x0); |
3221 | gfar_write(®s->gaddr1, 0x0); | |
3222 | gfar_write(®s->gaddr2, 0x0); | |
3223 | gfar_write(®s->gaddr3, 0x0); | |
3224 | gfar_write(®s->gaddr4, 0x0); | |
3225 | gfar_write(®s->gaddr5, 0x0); | |
3226 | gfar_write(®s->gaddr6, 0x0); | |
3227 | gfar_write(®s->gaddr7, 0x0); | |
3228 | ||
7f7f5316 AF |
3229 | /* If we have extended hash tables, we need to |
3230 | * clear the exact match registers to prepare for | |
0977f817 JC |
3231 | * setting them |
3232 | */ | |
7f7f5316 AF |
3233 | if (priv->extended_hash) { |
3234 | em_num = GFAR_EM_NUM + 1; | |
3235 | gfar_clear_exact_match(dev); | |
3236 | idx = 1; | |
3237 | } else { | |
3238 | idx = 0; | |
3239 | em_num = 0; | |
3240 | } | |
3241 | ||
4cd24eaf | 3242 | if (netdev_mc_empty(dev)) |
1da177e4 LT |
3243 | return; |
3244 | ||
3245 | /* Parse the list, and set the appropriate bits */ | |
22bedad3 | 3246 | netdev_for_each_mc_addr(ha, dev) { |
7f7f5316 | 3247 | if (idx < em_num) { |
22bedad3 | 3248 | gfar_set_mac_for_addr(dev, idx, ha->addr); |
7f7f5316 AF |
3249 | idx++; |
3250 | } else | |
22bedad3 | 3251 | gfar_set_hash_for_addr(dev, ha->addr); |
1da177e4 LT |
3252 | } |
3253 | } | |
1da177e4 LT |
3254 | } |
3255 | ||
7f7f5316 AF |
3256 | |
3257 | /* Clears each of the exact match registers to zero, so they | |
0977f817 JC |
3258 | * don't interfere with normal reception |
3259 | */ | |
7f7f5316 AF |
3260 | static void gfar_clear_exact_match(struct net_device *dev) |
3261 | { | |
3262 | int idx; | |
6a3c910c | 3263 | static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; |
7f7f5316 | 3264 | |
bc4598bc | 3265 | for (idx = 1; idx < GFAR_EM_NUM + 1; idx++) |
b6bc7650 | 3266 | gfar_set_mac_for_addr(dev, idx, zero_arr); |
7f7f5316 AF |
3267 | } |
3268 | ||
1da177e4 LT |
3269 | /* Set the appropriate hash bit for the given addr */ |
3270 | /* The algorithm works like so: | |
3271 | * 1) Take the Destination Address (ie the multicast address), and | |
3272 | * do a CRC on it (little endian), and reverse the bits of the | |
3273 | * result. | |
3274 | * 2) Use the 8 most significant bits as a hash into a 256-entry | |
3275 | * table. The table is controlled through 8 32-bit registers: | |
3276 | * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is | |
3277 | * gaddr7. This means that the 3 most significant bits in the | |
3278 | * hash index which gaddr register to use, and the 5 other bits | |
3279 | * indicate which bit (assuming an IBM numbering scheme, which | |
3280 | * for PowerPC (tm) is usually the case) in the register holds | |
0977f817 JC |
3281 | * the entry. |
3282 | */ | |
1da177e4 LT |
3283 | static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr) |
3284 | { | |
3285 | u32 tempval; | |
3286 | struct gfar_private *priv = netdev_priv(dev); | |
6a3c910c | 3287 | u32 result = ether_crc(ETH_ALEN, addr); |
0bbaf069 KG |
3288 | int width = priv->hash_width; |
3289 | u8 whichbit = (result >> (32 - width)) & 0x1f; | |
3290 | u8 whichreg = result >> (32 - width + 5); | |
1da177e4 LT |
3291 | u32 value = (1 << (31-whichbit)); |
3292 | ||
0bbaf069 | 3293 | tempval = gfar_read(priv->hash_regs[whichreg]); |
1da177e4 | 3294 | tempval |= value; |
0bbaf069 | 3295 | gfar_write(priv->hash_regs[whichreg], tempval); |
1da177e4 LT |
3296 | } |
3297 | ||
7f7f5316 AF |
3298 | |
3299 | /* There are multiple MAC Address register pairs on some controllers | |
3300 | * This function sets the numth pair to a given address | |
3301 | */ | |
b6bc7650 JP |
3302 | static void gfar_set_mac_for_addr(struct net_device *dev, int num, |
3303 | const u8 *addr) | |
7f7f5316 AF |
3304 | { |
3305 | struct gfar_private *priv = netdev_priv(dev); | |
46ceb60c | 3306 | struct gfar __iomem *regs = priv->gfargrp[0].regs; |
7f7f5316 | 3307 | int idx; |
6a3c910c | 3308 | char tmpbuf[ETH_ALEN]; |
7f7f5316 | 3309 | u32 tempval; |
f4983704 | 3310 | u32 __iomem *macptr = ®s->macstnaddr1; |
7f7f5316 AF |
3311 | |
3312 | macptr += num*2; | |
3313 | ||
0977f817 JC |
3314 | /* Now copy it into the mac registers backwards, cuz |
3315 | * little endian is silly | |
3316 | */ | |
6a3c910c JP |
3317 | for (idx = 0; idx < ETH_ALEN; idx++) |
3318 | tmpbuf[ETH_ALEN - 1 - idx] = addr[idx]; | |
7f7f5316 AF |
3319 | |
3320 | gfar_write(macptr, *((u32 *) (tmpbuf))); | |
3321 | ||
3322 | tempval = *((u32 *) (tmpbuf + 4)); | |
3323 | ||
3324 | gfar_write(macptr+1, tempval); | |
3325 | } | |
3326 | ||
1da177e4 | 3327 | /* GFAR error interrupt handler */ |
f4983704 | 3328 | static irqreturn_t gfar_error(int irq, void *grp_id) |
1da177e4 | 3329 | { |
f4983704 SG |
3330 | struct gfar_priv_grp *gfargrp = grp_id; |
3331 | struct gfar __iomem *regs = gfargrp->regs; | |
3332 | struct gfar_private *priv= gfargrp->priv; | |
3333 | struct net_device *dev = priv->ndev; | |
1da177e4 LT |
3334 | |
3335 | /* Save ievent for future reference */ | |
f4983704 | 3336 | u32 events = gfar_read(®s->ievent); |
1da177e4 LT |
3337 | |
3338 | /* Clear IEVENT */ | |
f4983704 | 3339 | gfar_write(®s->ievent, events & IEVENT_ERR_MASK); |
d87eb127 SW |
3340 | |
3341 | /* Magic Packet is not an error. */ | |
b31a1d8b | 3342 | if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) && |
d87eb127 SW |
3343 | (events & IEVENT_MAG)) |
3344 | events &= ~IEVENT_MAG; | |
1da177e4 LT |
3345 | |
3346 | /* Hmm... */ | |
0bbaf069 | 3347 | if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv)) |
bc4598bc JC |
3348 | netdev_dbg(dev, |
3349 | "error interrupt (ievent=0x%08x imask=0x%08x)\n", | |
59deab26 | 3350 | events, gfar_read(®s->imask)); |
1da177e4 LT |
3351 | |
3352 | /* Update the error counters */ | |
3353 | if (events & IEVENT_TXE) { | |
09f75cd7 | 3354 | dev->stats.tx_errors++; |
1da177e4 LT |
3355 | |
3356 | if (events & IEVENT_LC) | |
09f75cd7 | 3357 | dev->stats.tx_window_errors++; |
1da177e4 | 3358 | if (events & IEVENT_CRL) |
09f75cd7 | 3359 | dev->stats.tx_aborted_errors++; |
1da177e4 | 3360 | if (events & IEVENT_XFUN) { |
836cf7fa AV |
3361 | unsigned long flags; |
3362 | ||
59deab26 JP |
3363 | netif_dbg(priv, tx_err, dev, |
3364 | "TX FIFO underrun, packet dropped\n"); | |
09f75cd7 | 3365 | dev->stats.tx_dropped++; |
212079df | 3366 | atomic64_inc(&priv->extra_stats.tx_underrun); |
1da177e4 | 3367 | |
836cf7fa AV |
3368 | local_irq_save(flags); |
3369 | lock_tx_qs(priv); | |
3370 | ||
1da177e4 | 3371 | /* Reactivate the Tx Queues */ |
fba4ed03 | 3372 | gfar_write(®s->tstat, gfargrp->tstat); |
836cf7fa AV |
3373 | |
3374 | unlock_tx_qs(priv); | |
3375 | local_irq_restore(flags); | |
1da177e4 | 3376 | } |
59deab26 | 3377 | netif_dbg(priv, tx_err, dev, "Transmit Error\n"); |
1da177e4 LT |
3378 | } |
3379 | if (events & IEVENT_BSY) { | |
09f75cd7 | 3380 | dev->stats.rx_errors++; |
212079df | 3381 | atomic64_inc(&priv->extra_stats.rx_bsy); |
1da177e4 | 3382 | |
f4983704 | 3383 | gfar_receive(irq, grp_id); |
1da177e4 | 3384 | |
59deab26 JP |
3385 | netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n", |
3386 | gfar_read(®s->rstat)); | |
1da177e4 LT |
3387 | } |
3388 | if (events & IEVENT_BABR) { | |
09f75cd7 | 3389 | dev->stats.rx_errors++; |
212079df | 3390 | atomic64_inc(&priv->extra_stats.rx_babr); |
1da177e4 | 3391 | |
59deab26 | 3392 | netif_dbg(priv, rx_err, dev, "babbling RX error\n"); |
1da177e4 LT |
3393 | } |
3394 | if (events & IEVENT_EBERR) { | |
212079df | 3395 | atomic64_inc(&priv->extra_stats.eberr); |
59deab26 | 3396 | netif_dbg(priv, rx_err, dev, "bus error\n"); |
1da177e4 | 3397 | } |
59deab26 JP |
3398 | if (events & IEVENT_RXC) |
3399 | netif_dbg(priv, rx_status, dev, "control frame\n"); | |
1da177e4 LT |
3400 | |
3401 | if (events & IEVENT_BABT) { | |
212079df | 3402 | atomic64_inc(&priv->extra_stats.tx_babt); |
59deab26 | 3403 | netif_dbg(priv, tx_err, dev, "babbling TX error\n"); |
1da177e4 LT |
3404 | } |
3405 | return IRQ_HANDLED; | |
3406 | } | |
3407 | ||
b31a1d8b AF |
3408 | static struct of_device_id gfar_match[] = |
3409 | { | |
3410 | { | |
3411 | .type = "network", | |
3412 | .compatible = "gianfar", | |
3413 | }, | |
46ceb60c SG |
3414 | { |
3415 | .compatible = "fsl,etsec2", | |
3416 | }, | |
b31a1d8b AF |
3417 | {}, |
3418 | }; | |
e72701ac | 3419 | MODULE_DEVICE_TABLE(of, gfar_match); |
b31a1d8b | 3420 | |
1da177e4 | 3421 | /* Structure for a device driver */ |
74888760 | 3422 | static struct platform_driver gfar_driver = { |
4018294b GL |
3423 | .driver = { |
3424 | .name = "fsl-gianfar", | |
3425 | .owner = THIS_MODULE, | |
3426 | .pm = GFAR_PM_OPS, | |
3427 | .of_match_table = gfar_match, | |
3428 | }, | |
1da177e4 LT |
3429 | .probe = gfar_probe, |
3430 | .remove = gfar_remove, | |
3431 | }; | |
3432 | ||
db62f684 | 3433 | module_platform_driver(gfar_driver); |