projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / net / ethernet / freescale / gianfar_ethtool.c
CommitLineData
1da177e4 1/*
3396c782 2 * drivers/net/ethernet/freescale/gianfar_ethtool.c
1da177e4
LT		 3 *
4 * Gianfar Ethernet Driver
5 * Ethtool support for Gianfar Enet
6 * Based on e1000 ethtool support
7 *
8 * Author: Andy Fleming
4c8d3d99 9 * Maintainer: Kumar Gala
a12f801d 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
1da177e4 11 *
6c43e046 12 * Copyright 2003-2006, 2008-2009, 2011 Freescale Semiconductor, Inc.
1da177e4 13 *
6aa20a22
JG		 14 * This software may be used and distributed according to
15 * the terms of the GNU Public License, Version 2, incorporated herein
1da177e4
LT		 16 * by reference.
17 */
18
59deab26
JP		 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
1da177e4 21#include <linux/kernel.h>
1da177e4
LT		 22#include <linux/string.h>
23#include <linux/errno.h>
1da177e4 24#include <linux/interrupt.h>
1da177e4
LT		 25#include <linux/delay.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
65a85a8d 28#include <linux/net_tstamp.h>
1da177e4
LT		 29#include <linux/skbuff.h>
30#include <linux/spinlock.h>
31#include <linux/mm.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/uaccess.h>
36#include <linux/module.h>
1da177e4
LT		 37#include <linux/crc32.h>
38#include <asm/types.h>
1da177e4 39#include <linux/ethtool.h>
bb40dcbb
AF		 40#include <linux/mii.h>
41#include <linux/phy.h>
4aa3a715 42#include <linux/sort.h>
380b153c 43#include <linux/if_vlan.h>
1da177e4
LT		 44
45#include "gianfar.h"
46
bb40dcbb
AF		 47#define GFAR_MAX_COAL_USECS 0xffff
48#define GFAR_MAX_COAL_FRAMES 0xff
0bbaf069 49static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
cbfc6071 50 u64 *buf);
0bbaf069 51static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf);
cbfc6071
JC		 52static int gfar_gcoalesce(struct net_device *dev,
53 struct ethtool_coalesce *cvals);
54static int gfar_scoalesce(struct net_device *dev,
55 struct ethtool_coalesce *cvals);
56static void gfar_gringparam(struct net_device *dev,
57 struct ethtool_ringparam *rvals);
58static int gfar_sringparam(struct net_device *dev,
59 struct ethtool_ringparam *rvals);
60static void gfar_gdrvinfo(struct net_device *dev,
61 struct ethtool_drvinfo *drvinfo);
1da177e4 62
30f7e310 63static const char stat_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 64 "rx-large-frame-errors",
65 "rx-short-frame-errors",
66 "rx-non-octet-errors",
67 "rx-crc-errors",
68 "rx-overrun-errors",
69 "rx-busy-errors",
70 "rx-babbling-errors",
71 "rx-truncated-frames",
72 "ethernet-bus-error",
73 "tx-babbling-errors",
74 "tx-underrun-errors",
75 "rx-skb-missing-errors",
76 "tx-timeout-errors",
77 "tx-rx-64-frames",
78 "tx-rx-65-127-frames",
79 "tx-rx-128-255-frames",
80 "tx-rx-256-511-frames",
81 "tx-rx-512-1023-frames",
82 "tx-rx-1024-1518-frames",
83 "tx-rx-1519-1522-good-vlan",
84 "rx-bytes",
85 "rx-packets",
86 "rx-fcs-errors",
87 "receive-multicast-packet",
88 "receive-broadcast-packet",
89 "rx-control-frame-packets",
90 "rx-pause-frame-packets",
91 "rx-unknown-op-code",
92 "rx-alignment-error",
93 "rx-frame-length-error",
94 "rx-code-error",
95 "rx-carrier-sense-error",
96 "rx-undersize-packets",
97 "rx-oversize-packets",
98 "rx-fragmented-frames",
99 "rx-jabber-frames",
100 "rx-dropped-frames",
101 "tx-byte-counter",
102 "tx-packets",
103 "tx-multicast-packets",
104 "tx-broadcast-packets",
105 "tx-pause-control-frames",
106 "tx-deferral-packets",
107 "tx-excessive-deferral-packets",
108 "tx-single-collision-packets",
109 "tx-multiple-collision-packets",
110 "tx-late-collision-packets",
111 "tx-excessive-collision-packets",
112 "tx-total-collision",
113 "reserved",
114 "tx-dropped-frames",
115 "tx-jabber-frames",
116 "tx-fcs-errors",
117 "tx-control-frames",
118 "tx-oversize-frames",
119 "tx-undersize-frames",
120 "tx-fragmented-frames",
121};
122
0bbaf069
KG		 123/* Fill in a buffer with the strings which correspond to the
124 * stats */
125static void gfar_gstrings(struct net_device *dev, u32 stringset, u8 * buf)
126{
127 struct gfar_private *priv = netdev_priv(dev);
7f7f5316 128
b31a1d8b 129 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
0bbaf069
KG		 130 memcpy(buf, stat_gstrings, GFAR_STATS_LEN * ETH_GSTRING_LEN);
131 else
132 memcpy(buf, stat_gstrings,
cbfc6071 133 GFAR_EXTRA_STATS_LEN * ETH_GSTRING_LEN);
0bbaf069
KG		 134}
135
1da177e4
LT		 136/* Fill in an array of 64-bit statistics from various sources.
137 * This array will be appended to the end of the ethtool_stats
138 * structure, and returned to user space
139 */
cbfc6071
JC		 140static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
141 u64 *buf)
1da177e4
LT		 142{
143 int i;
144 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 145 struct gfar __iomem *regs = priv->gfargrp[0].regs;
212079df 146 atomic64_t *extra = (atomic64_t *)&priv->extra_stats;
1da177e4 147
68719786 148 for (i = 0; i < GFAR_EXTRA_STATS_LEN; i++)
212079df 149 buf[i] = atomic64_read(&extra[i]);
68719786 150
b31a1d8b 151 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
f4983704 152 u32 __iomem *rmon = (u32 __iomem *) &regs->rmon;
1da177e4 153
68719786
PG		 154 for (; i < GFAR_STATS_LEN; i++, rmon++)
155 buf[i] = (u64) gfar_read(rmon);
156 }
1da177e4
LT		 157}
158
b9f2c044 159static int gfar_sset_count(struct net_device *dev, int sset)
1da177e4 160{
1da177e4 161 struct gfar_private *priv = netdev_priv(dev);
1da177e4 162
b9f2c044
JG		 163 switch (sset) {
164 case ETH_SS_STATS:
b31a1d8b 165 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON)
b9f2c044
JG		 166 return GFAR_STATS_LEN;
167 else
168 return GFAR_EXTRA_STATS_LEN;
169 default:
170 return -EOPNOTSUPP;
171 }
1da177e4
LT		 172}
173
1da177e4 174/* Fills in the drvinfo structure with some basic info */
cbfc6071
JC		 175static void gfar_gdrvinfo(struct net_device *dev,
176 struct ethtool_drvinfo *drvinfo)
1da177e4 177{
7826d43f
JP		 178 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
179 strlcpy(drvinfo->version, gfar_driver_version,
180 sizeof(drvinfo->version));
181 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
182 strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info));
1da177e4
LT		 183 drvinfo->regdump_len = 0;
184 drvinfo->eedump_len = 0;
185}
186
bb40dcbb
AF		 187
188static int gfar_ssettings(struct net_device *dev, struct ethtool_cmd *cmd)
189{
190 struct gfar_private *priv = netdev_priv(dev);
191 struct phy_device *phydev = priv->phydev;
192
193 if (NULL == phydev)
194 return -ENODEV;
195
196 return phy_ethtool_sset(phydev, cmd);
197}
198
199
1da177e4 200/* Return the current settings in the ethtool_cmd structure */
0bbaf069 201static int gfar_gsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 202{
203 struct gfar_private *priv = netdev_priv(dev);
bb40dcbb 204 struct phy_device *phydev = priv->phydev;
a12f801d
SG		 205 struct gfar_priv_rx_q *rx_queue = NULL;
206 struct gfar_priv_tx_q *tx_queue = NULL;
bb40dcbb
AF		 207
208 if (NULL == phydev)
209 return -ENODEV;
fba4ed03
SG		 210 tx_queue = priv->tx_queue[0];
211 rx_queue = priv->rx_queue[0];
6aa20a22 212
fba4ed03
SG		 213 /* etsec-1.7 and older versions have only one txic
214 * and rxic regs although they support multiple queues */
a12f801d
SG		 215 cmd->maxtxpkt = get_icft_value(tx_queue->txic);
216 cmd->maxrxpkt = get_icft_value(rx_queue->rxic);
1da177e4 217
bb40dcbb 218 return phy_ethtool_gset(phydev, cmd);
1da177e4
LT		 219}
220
221/* Return the length of the register structure */
0bbaf069 222static int gfar_reglen(struct net_device *dev)
1da177e4
LT		 223{
224 return sizeof (struct gfar);
225}
226
227/* Return a dump of the GFAR register space */
cbfc6071
JC		 228static void gfar_get_regs(struct net_device *dev, struct ethtool_regs *regs,
229 void *regbuf)
1da177e4
LT		 230{
231 int i;
232 struct gfar_private *priv = netdev_priv(dev);
46ceb60c 233 u32 __iomem *theregs = (u32 __iomem *) priv->gfargrp[0].regs;
1da177e4
LT		 234 u32 *buf = (u32 *) regbuf;
235
236 for (i = 0; i < sizeof (struct gfar) / sizeof (u32); i++)
cc8c6e37 237 buf[i] = gfar_read(&theregs[i]);
1da177e4
LT		 238}
239
1da177e4
LT		 240/* Convert microseconds to ethernet clock ticks, which changes
241 * depending on what speed the controller is running at */
cbfc6071
JC		 242static unsigned int gfar_usecs2ticks(struct gfar_private *priv,
243 unsigned int usecs)
1da177e4
LT		 244{
245 unsigned int count;
246
247 /* The timer is different, depending on the interface speed */
bb40dcbb
AF		 248 switch (priv->phydev->speed) {
249 case SPEED_1000:
1da177e4
LT		 250 count = GFAR_GBIT_TIME;
251 break;
bb40dcbb 252 case SPEED_100:
1da177e4
LT		 253 count = GFAR_100_TIME;
254 break;
bb40dcbb 255 case SPEED_10:
1da177e4
LT		 256 default:
257 count = GFAR_10_TIME;
258 break;
259 }
260
261 /* Make sure we return a number greater than 0
262 * if usecs > 0 */
807540ba 263 return (usecs * 1000 + count - 1) / count;
1da177e4
LT		 264}
265
266/* Convert ethernet clock ticks to microseconds */
cbfc6071
JC		 267static unsigned int gfar_ticks2usecs(struct gfar_private *priv,
268 unsigned int ticks)
1da177e4
LT		 269{
270 unsigned int count;
271
272 /* The timer is different, depending on the interface speed */
bb40dcbb
AF		 273 switch (priv->phydev->speed) {
274 case SPEED_1000:
1da177e4
LT		 275 count = GFAR_GBIT_TIME;
276 break;
bb40dcbb 277 case SPEED_100:
1da177e4
LT		 278 count = GFAR_100_TIME;
279 break;
bb40dcbb 280 case SPEED_10:
1da177e4
LT		 281 default:
282 count = GFAR_10_TIME;
283 break;
284 }
285
286 /* Make sure we return a number greater than 0 */
287 /* if ticks is > 0 */
807540ba 288 return (ticks * count) / 1000;
1da177e4
LT		 289}
290
291/* Get the coalescing parameters, and put them in the cvals
292 * structure. */
cbfc6071
JC		 293static int gfar_gcoalesce(struct net_device *dev,
294 struct ethtool_coalesce *cvals)
1da177e4
LT		 295{
296 struct gfar_private *priv = netdev_priv(dev);
a12f801d
SG		 297 struct gfar_priv_rx_q *rx_queue = NULL;
298 struct gfar_priv_tx_q *tx_queue = NULL;
b46a8454
DH		 299 unsigned long rxtime;
300 unsigned long rxcount;
301 unsigned long txtime;
302 unsigned long txcount;
6aa20a22 303
b31a1d8b 304 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
0bbaf069 305 return -EOPNOTSUPP;
1da177e4 306
bb40dcbb
AF		 307 if (NULL == priv->phydev)
308 return -ENODEV;
309
fba4ed03
SG		 310 rx_queue = priv->rx_queue[0];
311 tx_queue = priv->tx_queue[0];
a12f801d
SG		 312
313 rxtime = get_ictt_value(rx_queue->rxic);
314 rxcount = get_icft_value(rx_queue->rxic);
315 txtime = get_ictt_value(tx_queue->txic);
316 txcount = get_icft_value(tx_queue->txic);
b46a8454
DH		 317 cvals->rx_coalesce_usecs = gfar_ticks2usecs(priv, rxtime);
318 cvals->rx_max_coalesced_frames = rxcount;
1da177e4 319
b46a8454
DH		 320 cvals->tx_coalesce_usecs = gfar_ticks2usecs(priv, txtime);
321 cvals->tx_max_coalesced_frames = txcount;
1da177e4
LT		 322
323 cvals->use_adaptive_rx_coalesce = 0;
324 cvals->use_adaptive_tx_coalesce = 0;
325
326 cvals->pkt_rate_low = 0;
327 cvals->rx_coalesce_usecs_low = 0;
328 cvals->rx_max_coalesced_frames_low = 0;
329 cvals->tx_coalesce_usecs_low = 0;
330 cvals->tx_max_coalesced_frames_low = 0;
331
332 /* When the packet rate is below pkt_rate_high but above
333 * pkt_rate_low (both measured in packets per second) the
334 * normal {rx,tx}_* coalescing parameters are used.
335 */
336
337 /* When the packet rate is (measured in packets per second)
338 * is above pkt_rate_high, the {rx,tx}_*_high parameters are
339 * used.
340 */
341 cvals->pkt_rate_high = 0;
342 cvals->rx_coalesce_usecs_high = 0;
343 cvals->rx_max_coalesced_frames_high = 0;
344 cvals->tx_coalesce_usecs_high = 0;
345 cvals->tx_max_coalesced_frames_high = 0;
346
347 /* How often to do adaptive coalescing packet rate sampling,
348 * measured in seconds. Must not be zero.
349 */
350 cvals->rate_sample_interval = 0;
351
352 return 0;
353}
354
355/* Change the coalescing values.
356 * Both cvals->*_usecs and cvals->*_frames have to be > 0
357 * in order for coalescing to be active
358 */
cbfc6071
JC		 359static int gfar_scoalesce(struct net_device *dev,
360 struct ethtool_coalesce *cvals)
1da177e4
LT		 361{
362 struct gfar_private *priv = netdev_priv(dev);
f19015ba 363 int i, err = 0;
1da177e4 364
b31a1d8b 365 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_COALESCE))
0bbaf069
KG		 366 return -EOPNOTSUPP;
367
bb40dcbb
AF		 368 if (NULL == priv->phydev)
369 return -ENODEV;
370
371 /* Check the bounds of the values */
372 if (cvals->rx_coalesce_usecs > GFAR_MAX_COAL_USECS) {
375d6a1b
JP		 373 netdev_info(dev, "Coalescing is limited to %d microseconds\n",
374 GFAR_MAX_COAL_USECS);
bb40dcbb
AF		 375 return -EINVAL;
376 }
377
378 if (cvals->rx_max_coalesced_frames > GFAR_MAX_COAL_FRAMES) {
375d6a1b
JP		 379 netdev_info(dev, "Coalescing is limited to %d frames\n",
380 GFAR_MAX_COAL_FRAMES);
bb40dcbb
AF		 381 return -EINVAL;
382 }
383
f19015ba
CM		 384 /* Check the bounds of the values */
385 if (cvals->tx_coalesce_usecs > GFAR_MAX_COAL_USECS) {
386 netdev_info(dev, "Coalescing is limited to %d microseconds\n",
387 GFAR_MAX_COAL_USECS);
388 return -EINVAL;
389 }
390
391 if (cvals->tx_max_coalesced_frames > GFAR_MAX_COAL_FRAMES) {
392 netdev_info(dev, "Coalescing is limited to %d frames\n",
393 GFAR_MAX_COAL_FRAMES);
394 return -EINVAL;
395 }
396
397 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
398 cpu_relax();
399
400 /* Set up rx coalescing */
401 if ((cvals->rx_coalesce_usecs == 0) ||
402 (cvals->rx_max_coalesced_frames == 0)) {
403 for (i = 0; i < priv->num_rx_queues; i++)
404 priv->rx_queue[i]->rxcoalescing = 0;
405 } else {
406 for (i = 0; i < priv->num_rx_queues; i++)
407 priv->rx_queue[i]->rxcoalescing = 1;
408 }
409
46ceb60c
SG		 410 for (i = 0; i < priv->num_rx_queues; i++) {
411 priv->rx_queue[i]->rxic = mk_ic_value(
412 cvals->rx_max_coalesced_frames,
413 gfar_usecs2ticks(priv, cvals->rx_coalesce_usecs));
414 }
1da177e4
LT		 415
416 /* Set up tx coalescing */
417 if ((cvals->tx_coalesce_usecs == 0) ||
46ceb60c
SG		 418 (cvals->tx_max_coalesced_frames == 0)) {
419 for (i = 0; i < priv->num_tx_queues; i++)
420 priv->tx_queue[i]->txcoalescing = 0;
421 } else {
422 for (i = 0; i < priv->num_tx_queues; i++)
423 priv->tx_queue[i]->txcoalescing = 1;
424 }
1da177e4 425
46ceb60c
SG		 426 for (i = 0; i < priv->num_tx_queues; i++) {
427 priv->tx_queue[i]->txic = mk_ic_value(
428 cvals->tx_max_coalesced_frames,
429 gfar_usecs2ticks(priv, cvals->tx_coalesce_usecs));
430 }
1da177e4 431
f19015ba
CM		 432 if (dev->flags & IFF_UP) {
433 stop_gfar(dev);
434 err = startup_gfar(dev);
435 } else {
436 gfar_mac_reset(priv);
437 }
438
439 clear_bit_unlock(GFAR_RESETTING, &priv->state);
1da177e4 440
f19015ba 441 return err;
1da177e4
LT		 442}
443
444/* Fills in rvals with the current ring parameters. Currently,
445 * rx, rx_mini, and rx_jumbo rings are the same size, as mini and
446 * jumbo are ignored by the driver */
cbfc6071
JC		 447static void gfar_gringparam(struct net_device *dev,
448 struct ethtool_ringparam *rvals)
1da177e4
LT		 449{
450 struct gfar_private *priv = netdev_priv(dev);
a12f801d
SG		 451 struct gfar_priv_tx_q *tx_queue = NULL;
452 struct gfar_priv_rx_q *rx_queue = NULL;
453
fba4ed03
SG		 454 tx_queue = priv->tx_queue[0];
455 rx_queue = priv->rx_queue[0];
1da177e4
LT		 456
457 rvals->rx_max_pending = GFAR_RX_MAX_RING_SIZE;
458 rvals->rx_mini_max_pending = GFAR_RX_MAX_RING_SIZE;
459 rvals->rx_jumbo_max_pending = GFAR_RX_MAX_RING_SIZE;
460 rvals->tx_max_pending = GFAR_TX_MAX_RING_SIZE;
461
462 /* Values changeable by the user. The valid values are
463 * in the range 1 to the "*_max_pending" counterpart above.
464 */
a12f801d
SG		 465 rvals->rx_pending = rx_queue->rx_ring_size;
466 rvals->rx_mini_pending = rx_queue->rx_ring_size;
467 rvals->rx_jumbo_pending = rx_queue->rx_ring_size;
468 rvals->tx_pending = tx_queue->tx_ring_size;
1da177e4
LT		 469}
470
471/* Change the current ring parameters, stopping the controller if
7cca336a 472 * necessary so that we don't mess things up while we're in motion.
cbfc6071
JC		 473 */
474static int gfar_sringparam(struct net_device *dev,
475 struct ethtool_ringparam *rvals)
1da177e4 476{
1da177e4 477 struct gfar_private *priv = netdev_priv(dev);
7cca336a 478 int err = 0, i;
1da177e4
LT		 479
480 if (rvals->rx_pending > GFAR_RX_MAX_RING_SIZE)
481 return -EINVAL;
482
483 if (!is_power_of_2(rvals->rx_pending)) {
59deab26 484 netdev_err(dev, "Ring sizes must be a power of 2\n");
1da177e4
LT		 485 return -EINVAL;
486 }
487
488 if (rvals->tx_pending > GFAR_TX_MAX_RING_SIZE)
489 return -EINVAL;
490
491 if (!is_power_of_2(rvals->tx_pending)) {
59deab26 492 netdev_err(dev, "Ring sizes must be a power of 2\n");
1da177e4
LT		 493 return -EINVAL;
494 }
495
0851133b
CM		 496 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
497 cpu_relax();
498
7cca336a 499 if (dev->flags & IFF_UP)
0bbaf069 500 stop_gfar(dev);
1da177e4 501
7cca336a
CM		 502 /* Change the sizes */
503 for (i = 0; i < priv->num_rx_queues; i++)
fba4ed03 504 priv->rx_queue[i]->rx_ring_size = rvals->rx_pending;
7cca336a
CM		 505
506 for (i = 0; i < priv->num_tx_queues; i++)
fba4ed03 507 priv->tx_queue[i]->tx_ring_size = rvals->tx_pending;
1da177e4 508
0bbaf069 509 /* Rebuild the rings with the new size */
0851133b 510 if (dev->flags & IFF_UP)
0bbaf069 511 err = startup_gfar(dev);
0851133b
CM		 512
513 clear_bit_unlock(GFAR_RESETTING, &priv->state);
514
0bbaf069
KG		 515 return err;
516}
1da177e4 517
23402bdd
CM		 518static void gfar_gpauseparam(struct net_device *dev,
519 struct ethtool_pauseparam *epause)
520{
521 struct gfar_private *priv = netdev_priv(dev);
522
523 epause->autoneg = !!priv->pause_aneg_en;
524 epause->rx_pause = !!priv->rx_pause_en;
525 epause->tx_pause = !!priv->tx_pause_en;
526}
527
528static int gfar_spauseparam(struct net_device *dev,
529 struct ethtool_pauseparam *epause)
530{
531 struct gfar_private *priv = netdev_priv(dev);
532 struct phy_device *phydev = priv->phydev;
533 struct gfar __iomem *regs = priv->gfargrp[0].regs;
534 u32 oldadv, newadv;
535
98a46d46
CM		 536 if (!phydev)
537 return -ENODEV;
538
23402bdd
CM		 539 if (!(phydev->supported & SUPPORTED_Pause) ||
540 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
541 (epause->rx_pause != epause->tx_pause)))
542 return -EINVAL;
543
544 priv->rx_pause_en = priv->tx_pause_en = 0;
545 if (epause->rx_pause) {
546 priv->rx_pause_en = 1;
547
548 if (epause->tx_pause) {
549 priv->tx_pause_en = 1;
550 /* FLOW_CTRL_RX & TX */
551 newadv = ADVERTISED_Pause;
552 } else /* FLOW_CTLR_RX */
553 newadv = ADVERTISED_Pause | ADVERTISED_Asym_Pause;
554 } else if (epause->tx_pause) {
555 priv->tx_pause_en = 1;
556 /* FLOW_CTLR_TX */
557 newadv = ADVERTISED_Asym_Pause;
558 } else
559 newadv = 0;
560
561 if (epause->autoneg)
562 priv->pause_aneg_en = 1;
563 else
564 priv->pause_aneg_en = 0;
565
566 oldadv = phydev->advertising &
567 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
568 if (oldadv != newadv) {
569 phydev->advertising &=
570 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
571 phydev->advertising |= newadv;
572 if (phydev->autoneg)
573 /* inform link partner of our
574 * new flow ctrl settings
575 */
576 return phy_start_aneg(phydev);
577
578 if (!epause->autoneg) {
579 u32 tempval;
580 tempval = gfar_read(&regs->maccfg1);
581 tempval &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
45b679c9
MP		 582
583 priv->tx_actual_en = 0;
584 if (priv->tx_pause_en) {
585 priv->tx_actual_en = 1;
23402bdd 586 tempval |= MACCFG1_TX_FLOW;
45b679c9
MP		 587 }
588
23402bdd
CM		 589 if (priv->rx_pause_en)
590 tempval |= MACCFG1_RX_FLOW;
591 gfar_write(&regs->maccfg1, tempval);
592 }
593 }
594
595 return 0;
596}
597
c8f44aff 598int gfar_set_features(struct net_device *dev, netdev_features_t features)
0bbaf069 599{
c8f44aff 600 netdev_features_t changed = dev->features ^ features;
0851133b 601 struct gfar_private *priv = netdev_priv(dev);
7cca336a 602 int err = 0;
1da177e4 603
88302648
CM		 604 if (!(changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
605 NETIF_F_RXCSUM)))
8b3afe95 606 return 0;
a12f801d 607
0851133b
CM		 608 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
609 cpu_relax();
610
88302648
CM		 611 dev->features = features;
612
0bbaf069 613 if (dev->flags & IFF_UP) {
0bbaf069 614 /* Now we take down the rings to rebuild them */
1da177e4 615 stop_gfar(dev);
1da177e4 616 err = startup_gfar(dev);
0851133b
CM		 617 } else {
618 gfar_mac_reset(priv);
12dea57b 619 }
0851133b
CM		 620
621 clear_bit_unlock(GFAR_RESETTING, &priv->state);
622
1da177e4
LT		 623 return err;
624}
625
0bbaf069 626static uint32_t gfar_get_msglevel(struct net_device *dev)
6aa20a22 627{
0bbaf069 628 struct gfar_private *priv = netdev_priv(dev);
cbfc6071 629
0bbaf069 630 return priv->msg_enable;
6aa20a22
JG		 631}
632
0bbaf069 633static void gfar_set_msglevel(struct net_device *dev, uint32_t data)
6aa20a22 634{
0bbaf069 635 struct gfar_private *priv = netdev_priv(dev);
cbfc6071 636
0bbaf069
KG		 637 priv->msg_enable = data;
638}
639
d87eb127
SW		 640#ifdef CONFIG_PM
641static void gfar_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
642{
643 struct gfar_private *priv = netdev_priv(dev);
644
b31a1d8b 645 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) {
d87eb127
SW		 646 wol->supported = WAKE_MAGIC;
647 wol->wolopts = priv->wol_en ? WAKE_MAGIC : 0;
648 } else {
649 wol->supported = wol->wolopts = 0;
650 }
651}
652
653static int gfar_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
654{
655 struct gfar_private *priv = netdev_priv(dev);
656 unsigned long flags;
657
b31a1d8b 658 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
d87eb127
SW		 659 wol->wolopts != 0)
660 return -EINVAL;
661
662 if (wol->wolopts & ~WAKE_MAGIC)
663 return -EINVAL;
664
6c4f1994
RW		 665 device_set_wakeup_enable(&dev->dev, wol->wolopts & WAKE_MAGIC);
666
d87eb127 667 spin_lock_irqsave(&priv->bflock, flags);
6c4f1994 668 priv->wol_en = !!device_may_wakeup(&dev->dev);
d87eb127
SW		 669 spin_unlock_irqrestore(&priv->bflock, flags);
670
671 return 0;
672}
673#endif
0bbaf069 674
7a8b3372
SG		 675static void ethflow_to_filer_rules (struct gfar_private *priv, u64 ethflow)
676{
677 u32 fcr = 0x0, fpr = FPR_FILER_MASK;
678
679 if (ethflow & RXH_L2DA) {
680 fcr = RQFCR_PID_DAH |RQFCR_CMP_NOMATCH |
cbfc6071 681 RQFCR_HASH | RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 682 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
683 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 684 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
685 priv->cur_filer_idx = priv->cur_filer_idx - 1;
686
687 fcr = RQFCR_PID_DAL | RQFCR_AND | RQFCR_CMP_NOMATCH |
cbfc6071 688 RQFCR_HASH | RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 689 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
690 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 691 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
692 priv->cur_filer_idx = priv->cur_filer_idx - 1;
693 }
694
695 if (ethflow & RXH_VLAN) {
696 fcr = RQFCR_PID_VID | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 697 RQFCR_AND | RQFCR_HASHTBL_0;
7a8b3372 698 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
6c43e046
WJB		 699 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
700 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 701 priv->cur_filer_idx = priv->cur_filer_idx - 1;
702 }
703
704 if (ethflow & RXH_IP_SRC) {
705 fcr = RQFCR_PID_SIA | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 706 RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 707 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
708 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 709 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
710 priv->cur_filer_idx = priv->cur_filer_idx - 1;
711 }
712
713 if (ethflow & (RXH_IP_DST)) {
714 fcr = RQFCR_PID_DIA | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 715 RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 716 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
717 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 718 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
719 priv->cur_filer_idx = priv->cur_filer_idx - 1;
720 }
721
722 if (ethflow & RXH_L3_PROTO) {
723 fcr = RQFCR_PID_L4P | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 724 RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 725 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
726 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 727 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
728 priv->cur_filer_idx = priv->cur_filer_idx - 1;
729 }
730
731 if (ethflow & RXH_L4_B_0_1) {
732 fcr = RQFCR_PID_SPT | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 733 RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 734 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
735 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 736 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
737 priv->cur_filer_idx = priv->cur_filer_idx - 1;
738 }
739
740 if (ethflow & RXH_L4_B_2_3) {
741 fcr = RQFCR_PID_DPT | RQFCR_CMP_NOMATCH | RQFCR_HASH |
cbfc6071 742 RQFCR_AND | RQFCR_HASHTBL_0;
6c43e046
WJB		 743 priv->ftp_rqfpr[priv->cur_filer_idx] = fpr;
744 priv->ftp_rqfcr[priv->cur_filer_idx] = fcr;
7a8b3372
SG		 745 gfar_write_filer(priv, priv->cur_filer_idx, fcr, fpr);
746 priv->cur_filer_idx = priv->cur_filer_idx - 1;
747 }
748}
749
cbfc6071
JC		 750static int gfar_ethflow_to_filer_table(struct gfar_private *priv, u64 ethflow,
751 u64 class)
7a8b3372
SG		 752{
753 unsigned int last_rule_idx = priv->cur_filer_idx;
754 unsigned int cmp_rqfpr;
588dc911
WS		 755 unsigned int *local_rqfpr;
756 unsigned int *local_rqfcr;
7a8b3372
SG		 757 int i = 0x0, k = 0x0;
758 int j = MAX_FILER_IDX, l = 0x0;
588dc911
WS		 759 int ret = 1;
760
b2adaca9
JP		 761 local_rqfpr = kmalloc_array(MAX_FILER_IDX + 1, sizeof(unsigned int),
762 GFP_KERNEL);
763 local_rqfcr = kmalloc_array(MAX_FILER_IDX + 1, sizeof(unsigned int),
764 GFP_KERNEL);
588dc911 765 if (!local_rqfpr || !local_rqfcr) {
588dc911
WS		 766 ret = 0;
767 goto err;
768 }
7a8b3372
SG		 769
770 switch (class) {
771 case TCP_V4_FLOW:
772 cmp_rqfpr = RQFPR_IPV4 |RQFPR_TCP;
773 break;
774 case UDP_V4_FLOW:
775 cmp_rqfpr = RQFPR_IPV4 |RQFPR_UDP;
776 break;
777 case TCP_V6_FLOW:
778 cmp_rqfpr = RQFPR_IPV6 |RQFPR_TCP;
779 break;
780 case UDP_V6_FLOW:
781 cmp_rqfpr = RQFPR_IPV6 |RQFPR_UDP;
782 break;
7a8b3372 783 default:
375d6a1b
JP		 784 netdev_err(priv->ndev,
785 "Right now this class is not supported\n");
588dc911
WS		 786 ret = 0;
787 goto err;
7a8b3372
SG		 788 }
789
790 for (i = 0; i < MAX_FILER_IDX + 1; i++) {
6c43e046
WJB		 791 local_rqfpr[j] = priv->ftp_rqfpr[i];
792 local_rqfcr[j] = priv->ftp_rqfcr[i];
7a8b3372 793 j--;
cbfc6071
JC		 794 if ((priv->ftp_rqfcr[i] ==
795 (RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND)) &&
796 (priv->ftp_rqfpr[i] == cmp_rqfpr))
7a8b3372
SG		 797 break;
798 }
799
800 if (i == MAX_FILER_IDX + 1) {
375d6a1b
JP		 801 netdev_err(priv->ndev,
802 "No parse rule found, can't create hash rules\n");
588dc911
WS		 803 ret = 0;
804 goto err;
7a8b3372
SG		 805 }
806
807 /* If a match was found, then it begins the starting of a cluster rule
808 * if it was already programmed, we need to overwrite these rules
809 */
810 for (l = i+1; l < MAX_FILER_IDX; l++) {
6c43e046 811 if ((priv->ftp_rqfcr[l] & RQFCR_CLE) &&
cbfc6071 812 !(priv->ftp_rqfcr[l] & RQFCR_AND)) {
6c43e046 813 priv->ftp_rqfcr[l] = RQFCR_CLE | RQFCR_CMP_EXACT |
cbfc6071 814 RQFCR_HASHTBL_0 | RQFCR_PID_MASK;
6c43e046
WJB		 815 priv->ftp_rqfpr[l] = FPR_FILER_MASK;
816 gfar_write_filer(priv, l, priv->ftp_rqfcr[l],
cbfc6071 817 priv->ftp_rqfpr[l]);
7a8b3372
SG		 818 break;
819 }
820
6c43e046
WJB		 821 if (!(priv->ftp_rqfcr[l] & RQFCR_CLE) &&
822 (priv->ftp_rqfcr[l] & RQFCR_AND))
7a8b3372
SG		 823 continue;
824 else {
6c43e046
WJB		 825 local_rqfpr[j] = priv->ftp_rqfpr[l];
826 local_rqfcr[j] = priv->ftp_rqfcr[l];
7a8b3372
SG		 827 j--;
828 }
829 }
830
831 priv->cur_filer_idx = l - 1;
832 last_rule_idx = l;
833
834 /* hash rules */
835 ethflow_to_filer_rules(priv, ethflow);
836
837 /* Write back the popped out rules again */
838 for (k = j+1; k < MAX_FILER_IDX; k++) {
6c43e046
WJB		 839 priv->ftp_rqfpr[priv->cur_filer_idx] = local_rqfpr[k];
840 priv->ftp_rqfcr[priv->cur_filer_idx] = local_rqfcr[k];
7a8b3372 841 gfar_write_filer(priv, priv->cur_filer_idx,
cbfc6071 842 local_rqfcr[k], local_rqfpr[k]);
7a8b3372
SG		 843 if (!priv->cur_filer_idx)
844 break;
845 priv->cur_filer_idx = priv->cur_filer_idx - 1;
846 }
847
588dc911
WS		 848err:
849 kfree(local_rqfcr);
850 kfree(local_rqfpr);
851 return ret;
7a8b3372
SG		 852}
853
cbfc6071
JC		 854static int gfar_set_hash_opts(struct gfar_private *priv,
855 struct ethtool_rxnfc *cmd)
7a8b3372 856{
7a8b3372
SG		 857 /* write the filer rules here */
858 if (!gfar_ethflow_to_filer_table(priv, cmd->data, cmd->flow_type))
bde3528f 859 return -EINVAL;
7a8b3372
SG		 860
861 return 0;
862}
863
4aa3a715
SP		 864static int gfar_check_filer_hardware(struct gfar_private *priv)
865{
42851e88 866 struct gfar __iomem *regs = priv->gfargrp[0].regs;
4aa3a715
SP		 867 u32 i;
868
4aa3a715
SP		 869 /* Check if we are in FIFO mode */
870 i = gfar_read(&regs->ecntrl);
871 i &= ECNTRL_FIFM;
872 if (i == ECNTRL_FIFM) {
873 netdev_notice(priv->ndev, "Interface in FIFO mode\n");
874 i = gfar_read(&regs->rctrl);
875 i &= RCTRL_PRSDEP_MASK | RCTRL_PRSFM;
876 if (i == (RCTRL_PRSDEP_MASK | RCTRL_PRSFM)) {
877 netdev_info(priv->ndev,
cbfc6071 878 "Receive Queue Filtering enabled\n");
4aa3a715
SP		 879 } else {
880 netdev_warn(priv->ndev,
cbfc6071 881 "Receive Queue Filtering disabled\n");
4aa3a715
SP		 882 return -EOPNOTSUPP;
883 }
884 }
885 /* Or in standard mode */
886 else {
887 i = gfar_read(&regs->rctrl);
888 i &= RCTRL_PRSDEP_MASK;
889 if (i == RCTRL_PRSDEP_MASK) {
890 netdev_info(priv->ndev,
cbfc6071 891 "Receive Queue Filtering enabled\n");
4aa3a715
SP		 892 } else {
893 netdev_warn(priv->ndev,
cbfc6071 894 "Receive Queue Filtering disabled\n");
4aa3a715
SP		 895 return -EOPNOTSUPP;
896 }
897 }
898
899 /* Sets the properties for arbitrary filer rule
cbfc6071
JC		 900 * to the first 4 Layer 4 Bytes
901 */
42851e88 902 gfar_write(&regs->rbifx, 0xC0C1C2C3);
4aa3a715
SP		 903 return 0;
904}
905
906static int gfar_comp_asc(const void *a, const void *b)
907{
908 return memcmp(a, b, 4);
909}
910
911static int gfar_comp_desc(const void *a, const void *b)
912{
913 return -memcmp(a, b, 4);
914}
915
916static void gfar_swap(void *a, void *b, int size)
917{
918 u32 *_a = a;
919 u32 *_b = b;
920
921 swap(_a[0], _b[0]);
922 swap(_a[1], _b[1]);
923 swap(_a[2], _b[2]);
924 swap(_a[3], _b[3]);
925}
926
927/* Write a mask to filer cache */
928static void gfar_set_mask(u32 mask, struct filer_table *tab)
929{
930 tab->fe[tab->index].ctrl = RQFCR_AND | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
931 tab->fe[tab->index].prop = mask;
932 tab->index++;
933}
934
935/* Sets parse bits (e.g. IP or TCP) */
936static void gfar_set_parse_bits(u32 value, u32 mask, struct filer_table *tab)
937{
938 gfar_set_mask(mask, tab);
cbfc6071
JC		 939 tab->fe[tab->index].ctrl = RQFCR_CMP_EXACT | RQFCR_PID_PARSE |
940 RQFCR_AND;
4aa3a715
SP		 941 tab->fe[tab->index].prop = value;
942 tab->index++;
943}
944
945static void gfar_set_general_attribute(u32 value, u32 mask, u32 flag,
cbfc6071 946 struct filer_table *tab)
4aa3a715
SP		 947{
948 gfar_set_mask(mask, tab);
949 tab->fe[tab->index].ctrl = RQFCR_CMP_EXACT | RQFCR_AND | flag;
950 tab->fe[tab->index].prop = value;
951 tab->index++;
952}
953
cbfc6071 954/* For setting a tuple of value and mask of type flag
4aa3a715
SP		 955 * Example:
956 * IP-Src = 10.0.0.0/255.0.0.0
957 * value: 0x0A000000 mask: FF000000 flag: RQFPR_IPV4
958 *
959 * Ethtool gives us a value=0 and mask=~0 for don't care a tuple
960 * For a don't care mask it gives us a 0
961 *
962 * The check if don't care and the mask adjustment if mask=0 is done for VLAN
963 * and MAC stuff on an upper level (due to missing information on this level).
964 * For these guys we can discard them if they are value=0 and mask=0.
965 *
966 * Further the all masks are one-padded for better hardware efficiency.
967 */
968static void gfar_set_attribute(u32 value, u32 mask, u32 flag,
cbfc6071 969 struct filer_table *tab)
4aa3a715
SP		 970{
971 switch (flag) {
380b153c 972 /* 3bit */
4aa3a715
SP		 973 case RQFCR_PID_PRI:
974 if (!(value | mask))
975 return;
976 mask |= RQFCR_PID_PRI_MASK;
977 break;
978 /* 8bit */
979 case RQFCR_PID_L4P:
980 case RQFCR_PID_TOS:
981 if (!~(mask | RQFCR_PID_L4P_MASK))
982 return;
983 if (!mask)
984 mask = ~0;
985 else
986 mask |= RQFCR_PID_L4P_MASK;
987 break;
988 /* 12bit */
989 case RQFCR_PID_VID:
990 if (!(value | mask))
991 return;
992 mask |= RQFCR_PID_VID_MASK;
993 break;
994 /* 16bit */
995 case RQFCR_PID_DPT:
996 case RQFCR_PID_SPT:
997 case RQFCR_PID_ETY:
998 if (!~(mask | RQFCR_PID_PORT_MASK))
999 return;
1000 if (!mask)
1001 mask = ~0;
1002 else
1003 mask |= RQFCR_PID_PORT_MASK;
1004 break;
1005 /* 24bit */
1006 case RQFCR_PID_DAH:
1007 case RQFCR_PID_DAL:
1008 case RQFCR_PID_SAH:
1009 case RQFCR_PID_SAL:
1010 if (!(value | mask))
1011 return;
1012 mask |= RQFCR_PID_MAC_MASK;
1013 break;
1014 /* for all real 32bit masks */
1015 default:
1016 if (!~mask)
1017 return;
1018 if (!mask)
1019 mask = ~0;
1020 break;
1021 }
1022 gfar_set_general_attribute(value, mask, flag, tab);
1023}
1024
1025/* Translates value and mask for UDP, TCP or SCTP */
1026static void gfar_set_basic_ip(struct ethtool_tcpip4_spec *value,
cbfc6071
JC		 1027 struct ethtool_tcpip4_spec *mask,
1028 struct filer_table *tab)
4aa3a715 1029{
42851e88
CM		 1030 gfar_set_attribute(be32_to_cpu(value->ip4src),
1031 be32_to_cpu(mask->ip4src),
1032 RQFCR_PID_SIA, tab);
1033 gfar_set_attribute(be32_to_cpu(value->ip4dst),
1034 be32_to_cpu(mask->ip4dst),
1035 RQFCR_PID_DIA, tab);
1036 gfar_set_attribute(be16_to_cpu(value->pdst),
1037 be16_to_cpu(mask->pdst),
1038 RQFCR_PID_DPT, tab);
1039 gfar_set_attribute(be16_to_cpu(value->psrc),
1040 be16_to_cpu(mask->psrc),
1041 RQFCR_PID_SPT, tab);
4aa3a715
SP		 1042 gfar_set_attribute(value->tos, mask->tos, RQFCR_PID_TOS, tab);
1043}
1044
1045/* Translates value and mask for RAW-IP4 */
1046static void gfar_set_user_ip(struct ethtool_usrip4_spec *value,
cbfc6071
JC		 1047 struct ethtool_usrip4_spec *mask,
1048 struct filer_table *tab)
4aa3a715 1049{
42851e88
CM		 1050 gfar_set_attribute(be32_to_cpu(value->ip4src),
1051 be32_to_cpu(mask->ip4src),
1052 RQFCR_PID_SIA, tab);
1053 gfar_set_attribute(be32_to_cpu(value->ip4dst),
1054 be32_to_cpu(mask->ip4dst),
1055 RQFCR_PID_DIA, tab);
4aa3a715
SP		 1056 gfar_set_attribute(value->tos, mask->tos, RQFCR_PID_TOS, tab);
1057 gfar_set_attribute(value->proto, mask->proto, RQFCR_PID_L4P, tab);
42851e88
CM		 1058 gfar_set_attribute(be32_to_cpu(value->l4_4_bytes),
1059 be32_to_cpu(mask->l4_4_bytes),
1060 RQFCR_PID_ARB, tab);
4aa3a715
SP		 1061
1062}
1063
1064/* Translates value and mask for ETHER spec */
1065static void gfar_set_ether(struct ethhdr *value, struct ethhdr *mask,
cbfc6071 1066 struct filer_table *tab)
4aa3a715
SP		 1067{
1068 u32 upper_temp_mask = 0;
1069 u32 lower_temp_mask = 0;
cbfc6071 1070
4aa3a715
SP		 1071 /* Source address */
1072 if (!is_broadcast_ether_addr(mask->h_source)) {
4aa3a715
SP		 1073 if (is_zero_ether_addr(mask->h_source)) {
1074 upper_temp_mask = 0xFFFFFFFF;
1075 lower_temp_mask = 0xFFFFFFFF;
1076 } else {
cbfc6071
JC		 1077 upper_temp_mask = mask->h_source[0] << 16 |
1078 mask->h_source[1] << 8 |
1079 mask->h_source[2];
1080 lower_temp_mask = mask->h_source[3] << 16 |
1081 mask->h_source[4] << 8 |
1082 mask->h_source[5];
4aa3a715
SP		 1083 }
1084 /* Upper 24bit */
cbfc6071
JC		 1085 gfar_set_attribute(value->h_source[0] << 16 |
1086 value->h_source[1] << 8 |
1087 value->h_source[2],
1088 upper_temp_mask, RQFCR_PID_SAH, tab);
4aa3a715 1089 /* And the same for the lower part */
cbfc6071
JC		 1090 gfar_set_attribute(value->h_source[3] << 16 |
1091 value->h_source[4] << 8 |
1092 value->h_source[5],
1093 lower_temp_mask, RQFCR_PID_SAL, tab);
4aa3a715
SP		 1094 }
1095 /* Destination address */
1096 if (!is_broadcast_ether_addr(mask->h_dest)) {
4aa3a715 1097 /* Special for destination is limited broadcast */
cbfc6071
JC		 1098 if ((is_broadcast_ether_addr(value->h_dest) &&
1099 is_zero_ether_addr(mask->h_dest))) {
4aa3a715
SP		 1100 gfar_set_parse_bits(RQFPR_EBC, RQFPR_EBC, tab);
1101 } else {
4aa3a715
SP		 1102 if (is_zero_ether_addr(mask->h_dest)) {
1103 upper_temp_mask = 0xFFFFFFFF;
1104 lower_temp_mask = 0xFFFFFFFF;
1105 } else {
cbfc6071
JC		 1106 upper_temp_mask = mask->h_dest[0] << 16 |
1107 mask->h_dest[1] << 8 |
1108 mask->h_dest[2];
1109 lower_temp_mask = mask->h_dest[3] << 16 |
1110 mask->h_dest[4] << 8 |
1111 mask->h_dest[5];
4aa3a715
SP		 1112 }
1113
1114 /* Upper 24bit */
cbfc6071
JC		 1115 gfar_set_attribute(value->h_dest[0] << 16 |
1116 value->h_dest[1] << 8 |
1117 value->h_dest[2],
1118 upper_temp_mask, RQFCR_PID_DAH, tab);
4aa3a715 1119 /* And the same for the lower part */
cbfc6071
JC		 1120 gfar_set_attribute(value->h_dest[3] << 16 |
1121 value->h_dest[4] << 8 |
1122 value->h_dest[5],
1123 lower_temp_mask, RQFCR_PID_DAL, tab);
4aa3a715
SP		 1124 }
1125 }
1126
42851e88
CM		 1127 gfar_set_attribute(be16_to_cpu(value->h_proto),
1128 be16_to_cpu(mask->h_proto),
1129 RQFCR_PID_ETY, tab);
1130}
1131
1132static inline u32 vlan_tci_vid(struct ethtool_rx_flow_spec *rule)
1133{
1134 return be16_to_cpu(rule->h_ext.vlan_tci) & VLAN_VID_MASK;
1135}
1136
1137static inline u32 vlan_tci_vidm(struct ethtool_rx_flow_spec *rule)
1138{
1139 return be16_to_cpu(rule->m_ext.vlan_tci) & VLAN_VID_MASK;
1140}
1141
1142static inline u32 vlan_tci_cfi(struct ethtool_rx_flow_spec *rule)
1143{
1144 return be16_to_cpu(rule->h_ext.vlan_tci) & VLAN_CFI_MASK;
1145}
1146
1147static inline u32 vlan_tci_cfim(struct ethtool_rx_flow_spec *rule)
1148{
1149 return be16_to_cpu(rule->m_ext.vlan_tci) & VLAN_CFI_MASK;
1150}
1151
1152static inline u32 vlan_tci_prio(struct ethtool_rx_flow_spec *rule)
1153{
1154 return (be16_to_cpu(rule->h_ext.vlan_tci) & VLAN_PRIO_MASK) >>
1155 VLAN_PRIO_SHIFT;
1156}
1157
1158static inline u32 vlan_tci_priom(struct ethtool_rx_flow_spec *rule)
1159{
1160 return (be16_to_cpu(rule->m_ext.vlan_tci) & VLAN_PRIO_MASK) >>
1161 VLAN_PRIO_SHIFT;
4aa3a715
SP		 1162}
1163
1164/* Convert a rule to binary filter format of gianfar */
1165static int gfar_convert_to_filer(struct ethtool_rx_flow_spec *rule,
cbfc6071 1166 struct filer_table *tab)
4aa3a715
SP		 1167{
1168 u32 vlan = 0, vlan_mask = 0;
1169 u32 id = 0, id_mask = 0;
1170 u32 cfi = 0, cfi_mask = 0;
1171 u32 prio = 0, prio_mask = 0;
4aa3a715
SP		 1172 u32 old_index = tab->index;
1173
1174 /* Check if vlan is wanted */
42851e88
CM		 1175 if ((rule->flow_type & FLOW_EXT) &&
1176 (rule->m_ext.vlan_tci != cpu_to_be16(0xFFFF))) {
4aa3a715 1177 if (!rule->m_ext.vlan_tci)
42851e88 1178 rule->m_ext.vlan_tci = cpu_to_be16(0xFFFF);
4aa3a715
SP		 1179
1180 vlan = RQFPR_VLN;
1181 vlan_mask = RQFPR_VLN;
1182
1183 /* Separate the fields */
42851e88
CM		 1184 id = vlan_tci_vid(rule);
1185 id_mask = vlan_tci_vidm(rule);
1186 cfi = vlan_tci_cfi(rule);
1187 cfi_mask = vlan_tci_cfim(rule);
1188 prio = vlan_tci_prio(rule);
1189 prio_mask = vlan_tci_priom(rule);
380b153c
SP		 1190
1191 if (cfi == VLAN_TAG_PRESENT && cfi_mask == VLAN_TAG_PRESENT) {
4aa3a715
SP		 1192 vlan |= RQFPR_CFI;
1193 vlan_mask |= RQFPR_CFI;
cbfc6071
JC		 1194 } else if (cfi != VLAN_TAG_PRESENT &&
1195 cfi_mask == VLAN_TAG_PRESENT) {
4aa3a715
SP		 1196 vlan_mask |= RQFPR_CFI;
1197 }
1198 }
1199
1200 switch (rule->flow_type & ~FLOW_EXT) {
1201 case TCP_V4_FLOW:
1202 gfar_set_parse_bits(RQFPR_IPV4 | RQFPR_TCP | vlan,
cbfc6071 1203 RQFPR_IPV4 | RQFPR_TCP | vlan_mask, tab);
4aa3a715 1204 gfar_set_basic_ip(&rule->h_u.tcp_ip4_spec,
cbfc6071 1205 &rule->m_u.tcp_ip4_spec, tab);
4aa3a715
SP		 1206 break;
1207 case UDP_V4_FLOW:
1208 gfar_set_parse_bits(RQFPR_IPV4 | RQFPR_UDP | vlan,
cbfc6071 1209 RQFPR_IPV4 | RQFPR_UDP | vlan_mask, tab);
4aa3a715 1210 gfar_set_basic_ip(&rule->h_u.udp_ip4_spec,
cbfc6071 1211 &rule->m_u.udp_ip4_spec, tab);
4aa3a715
SP		 1212 break;
1213 case SCTP_V4_FLOW:
1214 gfar_set_parse_bits(RQFPR_IPV4 | vlan, RQFPR_IPV4 | vlan_mask,
cbfc6071 1215 tab);
4aa3a715 1216 gfar_set_attribute(132, 0, RQFCR_PID_L4P, tab);
cbfc6071
JC		 1217 gfar_set_basic_ip((struct ethtool_tcpip4_spec *)&rule->h_u,
1218 (struct ethtool_tcpip4_spec *)&rule->m_u,
1219 tab);
4aa3a715
SP		 1220 break;
1221 case IP_USER_FLOW:
1222 gfar_set_parse_bits(RQFPR_IPV4 | vlan, RQFPR_IPV4 | vlan_mask,
cbfc6071 1223 tab);
4aa3a715 1224 gfar_set_user_ip((struct ethtool_usrip4_spec *) &rule->h_u,
cbfc6071
JC		 1225 (struct ethtool_usrip4_spec *) &rule->m_u,
1226 tab);
4aa3a715
SP		 1227 break;
1228 case ETHER_FLOW:
1229 if (vlan)
1230 gfar_set_parse_bits(vlan, vlan_mask, tab);
1231 gfar_set_ether((struct ethhdr *) &rule->h_u,
cbfc6071 1232 (struct ethhdr *) &rule->m_u, tab);
4aa3a715
SP		 1233 break;
1234 default:
1235 return -1;
1236 }
1237
1238 /* Set the vlan attributes in the end */
1239 if (vlan) {
1240 gfar_set_attribute(id, id_mask, RQFCR_PID_VID, tab);
1241 gfar_set_attribute(prio, prio_mask, RQFCR_PID_PRI, tab);
1242 }
1243
1244 /* If there has been nothing written till now, it must be a default */
1245 if (tab->index == old_index) {
1246 gfar_set_mask(0xFFFFFFFF, tab);
1247 tab->fe[tab->index].ctrl = 0x20;
1248 tab->fe[tab->index].prop = 0x0;
1249 tab->index++;
1250 }
1251
1252 /* Remove last AND */
1253 tab->fe[tab->index - 1].ctrl &= (~RQFCR_AND);
1254
1255 /* Specify which queue to use or to drop */
1256 if (rule->ring_cookie == RX_CLS_FLOW_DISC)
1257 tab->fe[tab->index - 1].ctrl |= RQFCR_RJE;
1258 else
1259 tab->fe[tab->index - 1].ctrl |= (rule->ring_cookie << 10);
1260
1261 /* Only big enough entries can be clustered */
1262 if (tab->index > (old_index + 2)) {
1263 tab->fe[old_index + 1].ctrl |= RQFCR_CLE;
1264 tab->fe[tab->index - 1].ctrl |= RQFCR_CLE;
1265 }
1266
cbfc6071
JC		 1267 /* In rare cases the cache can be full while there is
1268 * free space in hw
1269 */
4aa3a715
SP		 1270 if (tab->index > MAX_FILER_CACHE_IDX - 1)
1271 return -EBUSY;
1272
1273 return 0;
1274}
1275
1276/* Copy size filer entries */
1277static void gfar_copy_filer_entries(struct gfar_filer_entry dst[0],
cbfc6071 1278 struct gfar_filer_entry src[0], s32 size)
4aa3a715
SP		 1279{
1280 while (size > 0) {
1281 size--;
1282 dst[size].ctrl = src[size].ctrl;
1283 dst[size].prop = src[size].prop;
1284 }
1285}
1286
1287/* Delete the contents of the filer-table between start and end
cbfc6071
JC		 1288 * and collapse them
1289 */
4aa3a715
SP		 1290static int gfar_trim_filer_entries(u32 begin, u32 end, struct filer_table *tab)
1291{
1292 int length;
cbfc6071 1293
4aa3a715
SP		 1294 if (end > MAX_FILER_CACHE_IDX || end < begin)
1295 return -EINVAL;
1296
1297 end++;
1298 length = end - begin;
1299
1300 /* Copy */
1301 while (end < tab->index) {
1302 tab->fe[begin].ctrl = tab->fe[end].ctrl;
1303 tab->fe[begin++].prop = tab->fe[end++].prop;
1304
1305 }
1306 /* Fill up with don't cares */
1307 while (begin < tab->index) {
1308 tab->fe[begin].ctrl = 0x60;
1309 tab->fe[begin].prop = 0xFFFFFFFF;
1310 begin++;
1311 }
1312
1313 tab->index -= length;
1314 return 0;
1315}
1316
1317/* Make space on the wanted location */
1318static int gfar_expand_filer_entries(u32 begin, u32 length,
cbfc6071 1319 struct filer_table *tab)
4aa3a715 1320{
cbfc6071
JC		 1321 if (length == 0 || length + tab->index > MAX_FILER_CACHE_IDX ||
1322 begin > MAX_FILER_CACHE_IDX)
4aa3a715
SP		 1323 return -EINVAL;
1324
1325 gfar_copy_filer_entries(&(tab->fe[begin + length]), &(tab->fe[begin]),
cbfc6071 1326 tab->index - length + 1);
4aa3a715
SP		 1327
1328 tab->index += length;
1329 return 0;
1330}
1331
1332static int gfar_get_next_cluster_start(int start, struct filer_table *tab)
1333{
cbfc6071
JC		 1334 for (; (start < tab->index) && (start < MAX_FILER_CACHE_IDX - 1);
1335 start++) {
1336 if ((tab->fe[start].ctrl & (RQFCR_AND | RQFCR_CLE)) ==
1337 (RQFCR_AND | RQFCR_CLE))
4aa3a715
SP		 1338 return start;
1339 }
1340 return -1;
1341}
1342
1343static int gfar_get_next_cluster_end(int start, struct filer_table *tab)
1344{
cbfc6071
JC		 1345 for (; (start < tab->index) && (start < MAX_FILER_CACHE_IDX - 1);
1346 start++) {
1347 if ((tab->fe[start].ctrl & (RQFCR_AND | RQFCR_CLE)) ==
1348 (RQFCR_CLE))
4aa3a715
SP		 1349 return start;
1350 }
1351 return -1;
1352}
1353
cbfc6071 1354/* Uses hardwares clustering option to reduce
4aa3a715
SP		 1355 * the number of filer table entries
1356 */
1357static void gfar_cluster_filer(struct filer_table *tab)
1358{
1359 s32 i = -1, j, iend, jend;
1360
1361 while ((i = gfar_get_next_cluster_start(++i, tab)) != -1) {
1362 j = i;
1363 while ((j = gfar_get_next_cluster_start(++j, tab)) != -1) {
cbfc6071 1364 /* The cluster entries self and the previous one
4aa3a715
SP		 1365 * (a mask) must be identical!
1366 */
1367 if (tab->fe[i].ctrl != tab->fe[j].ctrl)
1368 break;
1369 if (tab->fe[i].prop != tab->fe[j].prop)
1370 break;
1371 if (tab->fe[i - 1].ctrl != tab->fe[j - 1].ctrl)
1372 break;
1373 if (tab->fe[i - 1].prop != tab->fe[j - 1].prop)
1374 break;
1375 iend = gfar_get_next_cluster_end(i, tab);
1376 jend = gfar_get_next_cluster_end(j, tab);
1377 if (jend == -1 || iend == -1)
1378 break;
cbfc6071
JC		 1379
1380 /* First we make some free space, where our cluster
4aa3a715
SP		 1381 * element should be. Then we copy it there and finally
1382 * delete in from its old location.
1383 */
cbfc6071
JC		 1384 if (gfar_expand_filer_entries(iend, (jend - j), tab) ==
1385 -EINVAL)
4aa3a715
SP		 1386 break;
1387
1388 gfar_copy_filer_entries(&(tab->fe[iend + 1]),
cbfc6071 1389 &(tab->fe[jend + 1]), jend - j);
4aa3a715
SP		 1390
1391 if (gfar_trim_filer_entries(jend - 1,
cbfc6071
JC		 1392 jend + (jend - j),
1393 tab) == -EINVAL)
4aa3a715
SP		 1394 return;
1395
1396 /* Mask out cluster bit */
1397 tab->fe[iend].ctrl &= ~(RQFCR_CLE);
1398 }
1399 }
1400}
1401
380b153c
SP		 1402/* Swaps the masked bits of a1<>a2 and b1<>b2 */
1403static void gfar_swap_bits(struct gfar_filer_entry *a1,
cbfc6071
JC		 1404 struct gfar_filer_entry *a2,
1405 struct gfar_filer_entry *b1,
1406 struct gfar_filer_entry *b2, u32 mask)
4aa3a715
SP		 1407{
1408 u32 temp[4];
380b153c
SP		 1409 temp[0] = a1->ctrl & mask;
1410 temp[1] = a2->ctrl & mask;
1411 temp[2] = b1->ctrl & mask;
1412 temp[3] = b2->ctrl & mask;
4aa3a715 1413
380b153c
SP		 1414 a1->ctrl &= ~mask;
1415 a2->ctrl &= ~mask;
1416 b1->ctrl &= ~mask;
1417 b2->ctrl &= ~mask;
4aa3a715
SP		 1418
1419 a1->ctrl |= temp[1];
1420 a2->ctrl |= temp[0];
1421 b1->ctrl |= temp[3];
1422 b2->ctrl |= temp[2];
1423}
1424
cbfc6071 1425/* Generate a list consisting of masks values with their start and
4aa3a715
SP		 1426 * end of validity and block as indicator for parts belonging
1427 * together (glued by ANDs) in mask_table
1428 */
1429static u32 gfar_generate_mask_table(struct gfar_mask_entry *mask_table,
cbfc6071 1430 struct filer_table *tab)
4aa3a715
SP		 1431{
1432 u32 i, and_index = 0, block_index = 1;
1433
1434 for (i = 0; i < tab->index; i++) {
1435
1436 /* LSByte of control = 0 sets a mask */
1437 if (!(tab->fe[i].ctrl & 0xF)) {
1438 mask_table[and_index].mask = tab->fe[i].prop;
1439 mask_table[and_index].start = i;
1440 mask_table[and_index].block = block_index;
1441 if (and_index >= 1)
1442 mask_table[and_index - 1].end = i - 1;
1443 and_index++;
1444 }
380b153c 1445 /* cluster starts and ends will be separated because they should
cbfc6071
JC		 1446 * hold their position
1447 */
4aa3a715
SP		 1448 if (tab->fe[i].ctrl & RQFCR_CLE)
1449 block_index++;
1450 /* A not set AND indicates the end of a depended block */
1451 if (!(tab->fe[i].ctrl & RQFCR_AND))
1452 block_index++;
4aa3a715
SP		 1453 }
1454
1455 mask_table[and_index - 1].end = i - 1;
1456
1457 return and_index;
1458}
1459
cbfc6071 1460/* Sorts the entries of mask_table by the values of the masks.
4aa3a715
SP		 1461 * Important: The 0xFF80 flags of the first and last entry of a
1462 * block must hold their position (which queue, CLusterEnable, ReJEct,
1463 * AND)
1464 */
1465static void gfar_sort_mask_table(struct gfar_mask_entry *mask_table,
cbfc6071 1466 struct filer_table *temp_table, u32 and_index)
4aa3a715
SP		 1467{
1468 /* Pointer to compare function (_asc or _desc) */
1469 int (*gfar_comp)(const void *, const void *);
1470
1471 u32 i, size = 0, start = 0, prev = 1;
1472 u32 old_first, old_last, new_first, new_last;
1473
1474 gfar_comp = &gfar_comp_desc;
1475
1476 for (i = 0; i < and_index; i++) {
4aa3a715
SP		 1477 if (prev != mask_table[i].block) {
1478 old_first = mask_table[start].start + 1;
1479 old_last = mask_table[i - 1].end;
1480 sort(mask_table + start, size,
cbfc6071
JC		 1481 sizeof(struct gfar_mask_entry),
1482 gfar_comp, &gfar_swap);
4aa3a715
SP		 1483
1484 /* Toggle order for every block. This makes the
cbfc6071
JC		 1485 * thing more efficient!
1486 */
4aa3a715
SP		 1487 if (gfar_comp == gfar_comp_desc)
1488 gfar_comp = &gfar_comp_asc;
1489 else
1490 gfar_comp = &gfar_comp_desc;
1491
1492 new_first = mask_table[start].start + 1;
1493 new_last = mask_table[i - 1].end;
1494
380b153c 1495 gfar_swap_bits(&temp_table->fe[new_first],
cbfc6071
JC		 1496 &temp_table->fe[old_first],
1497 &temp_table->fe[new_last],
1498 &temp_table->fe[old_last],
1499 RQFCR_QUEUE | RQFCR_CLE |
1500 RQFCR_RJE | RQFCR_AND);
4aa3a715
SP		 1501
1502 start = i;
1503 size = 0;
1504 }
1505 size++;
1506 prev = mask_table[i].block;
1507 }
4aa3a715
SP		 1508}
1509
cbfc6071 1510/* Reduces the number of masks needed in the filer table to save entries
4aa3a715
SP		 1511 * This is done by sorting the masks of a depended block. A depended block is
1512 * identified by gluing ANDs or CLE. The sorting order toggles after every
1513 * block. Of course entries in scope of a mask must change their location with
1514 * it.
1515 */
1516static int gfar_optimize_filer_masks(struct filer_table *tab)
1517{
1518 struct filer_table *temp_table;
1519 struct gfar_mask_entry *mask_table;
1520
1521 u32 and_index = 0, previous_mask = 0, i = 0, j = 0, size = 0;
1522 s32 ret = 0;
1523
1524 /* We need a copy of the filer table because
cbfc6071
JC		 1525 * we want to change its order
1526 */
b8ffdbd0 1527 temp_table = kmemdup(tab, sizeof(*temp_table), GFP_KERNEL);
4aa3a715
SP		 1528 if (temp_table == NULL)
1529 return -ENOMEM;
4aa3a715
SP		 1530
1531 mask_table = kcalloc(MAX_FILER_CACHE_IDX / 2 + 1,
cbfc6071 1532 sizeof(struct gfar_mask_entry), GFP_KERNEL);
4aa3a715
SP		 1533
1534 if (mask_table == NULL) {
1535 ret = -ENOMEM;
1536 goto end;
1537 }
1538
1539 and_index = gfar_generate_mask_table(mask_table, tab);
1540
1541 gfar_sort_mask_table(mask_table, temp_table, and_index);
1542
1543 /* Now we can copy the data from our duplicated filer table to
cbfc6071
JC		 1544 * the real one in the order the mask table says
1545 */
4aa3a715
SP		 1546 for (i = 0; i < and_index; i++) {
1547 size = mask_table[i].end - mask_table[i].start + 1;
1548 gfar_copy_filer_entries(&(tab->fe[j]),
1549 &(temp_table->fe[mask_table[i].start]), size);
1550 j += size;
1551 }
1552
1553 /* And finally we just have to check for duplicated masks and drop the
cbfc6071
JC		 1554 * second ones
1555 */
4aa3a715
SP		 1556 for (i = 0; i < tab->index && i < MAX_FILER_CACHE_IDX; i++) {
1557 if (tab->fe[i].ctrl == 0x80) {
1558 previous_mask = i++;
1559 break;
1560 }
1561 }
1562 for (; i < tab->index && i < MAX_FILER_CACHE_IDX; i++) {
1563 if (tab->fe[i].ctrl == 0x80) {
1564 if (tab->fe[i].prop == tab->fe[previous_mask].prop) {
1565 /* Two identical ones found!
cbfc6071
JC		 1566 * So drop the second one!
1567 */
4aa3a715
SP		 1568 gfar_trim_filer_entries(i, i, tab);
1569 } else
1570 /* Not identical! */
1571 previous_mask = i;
1572 }
1573 }
1574
1575 kfree(mask_table);
1576end: kfree(temp_table);
1577 return ret;
1578}
1579
1580/* Write the bit-pattern from software's buffer to hardware registers */
1581static int gfar_write_filer_table(struct gfar_private *priv,
cbfc6071 1582 struct filer_table *tab)
4aa3a715
SP		 1583{
1584 u32 i = 0;
1585 if (tab->index > MAX_FILER_IDX - 1)
1586 return -EBUSY;
1587
4aa3a715 1588 /* Fill regular entries */
75300ad2 1589 for (; i < MAX_FILER_IDX - 1 && (tab->fe[i].ctrl | tab->fe[i].prop);
cbfc6071 1590 i++)
4aa3a715
SP		 1591 gfar_write_filer(priv, i, tab->fe[i].ctrl, tab->fe[i].prop);
1592 /* Fill the rest with fall-troughs */
1593 for (; i < MAX_FILER_IDX - 1; i++)
1594 gfar_write_filer(priv, i, 0x60, 0xFFFFFFFF);
1595 /* Last entry must be default accept
cbfc6071
JC		 1596 * because that's what people expect
1597 */
4aa3a715
SP		 1598 gfar_write_filer(priv, i, 0x20, 0x0);
1599
4aa3a715
SP		 1600 return 0;
1601}
1602
1603static int gfar_check_capability(struct ethtool_rx_flow_spec *flow,
cbfc6071 1604 struct gfar_private *priv)
4aa3a715
SP		 1605{
1606
1607 if (flow->flow_type & FLOW_EXT) {
1608 if (~flow->m_ext.data[0] || ~flow->m_ext.data[1])
1609 netdev_warn(priv->ndev,
cbfc6071 1610 "User-specific data not supported!\n");
4aa3a715
SP		 1611 if (~flow->m_ext.vlan_etype)
1612 netdev_warn(priv->ndev,
cbfc6071 1613 "VLAN-etype not supported!\n");
4aa3a715
SP		 1614 }
1615 if (flow->flow_type == IP_USER_FLOW)
1616 if (flow->h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4)
1617 netdev_warn(priv->ndev,
cbfc6071 1618 "IP-Version differing from IPv4 not supported!\n");
4aa3a715
SP		 1619
1620 return 0;
1621}
1622
1623static int gfar_process_filer_changes(struct gfar_private *priv)
1624{
1625 struct ethtool_flow_spec_container *j;
1626 struct filer_table *tab;
1627 s32 i = 0;
1628 s32 ret = 0;
1629
1630 /* So index is set to zero, too! */
1631 tab = kzalloc(sizeof(*tab), GFP_KERNEL);
1632 if (tab == NULL)
1633 return -ENOMEM;
1634
1635 /* Now convert the existing filer data from flow_spec into
cbfc6071
JC		 1636 * filer tables binary format
1637 */
4aa3a715
SP		 1638 list_for_each_entry(j, &priv->rx_list.list, list) {
1639 ret = gfar_convert_to_filer(&j->fs, tab);
1640 if (ret == -EBUSY) {
cbfc6071
JC		 1641 netdev_err(priv->ndev,
1642 "Rule not added: No free space!\n");
4aa3a715
SP		 1643 goto end;
1644 }
1645 if (ret == -1) {
cbfc6071
JC		 1646 netdev_err(priv->ndev,
1647 "Rule not added: Unsupported Flow-type!\n");
4aa3a715
SP		 1648 goto end;
1649 }
1650 }
1651
1652 i = tab->index;
1653
1654 /* Optimizations to save entries */
1655 gfar_cluster_filer(tab);
1656 gfar_optimize_filer_masks(tab);
1657
375d6a1b 1658 pr_debug("\tSummary:\n"
cbfc6071
JC		 1659 "\tData on hardware: %d\n"
1660 "\tCompression rate: %d%%\n",
1661 tab->index, 100 - (100 * tab->index) / i);
4aa3a715
SP		 1662
1663 /* Write everything to hardware */
1664 ret = gfar_write_filer_table(priv, tab);
1665 if (ret == -EBUSY) {
1666 netdev_err(priv->ndev, "Rule not added: No free space!\n");
1667 goto end;
1668 }
1669
cbfc6071
JC		 1670end:
1671 kfree(tab);
4aa3a715
SP		 1672 return ret;
1673}
1674
1675static void gfar_invert_masks(struct ethtool_rx_flow_spec *flow)
1676{
1677 u32 i = 0;
1678
1679 for (i = 0; i < sizeof(flow->m_u); i++)
1680 flow->m_u.hdata[i] ^= 0xFF;
1681
42851e88
CM		 1682 flow->m_ext.vlan_etype ^= cpu_to_be16(0xFFFF);
1683 flow->m_ext.vlan_tci ^= cpu_to_be16(0xFFFF);
1684 flow->m_ext.data[0] ^= cpu_to_be32(~0);
1685 flow->m_ext.data[1] ^= cpu_to_be32(~0);
4aa3a715
SP		 1686}
1687
1688static int gfar_add_cls(struct gfar_private *priv,
cbfc6071 1689 struct ethtool_rx_flow_spec *flow)
4aa3a715
SP		 1690{
1691 struct ethtool_flow_spec_container *temp, *comp;
1692 int ret = 0;
1693
1694 temp = kmalloc(sizeof(*temp), GFP_KERNEL);
1695 if (temp == NULL)
1696 return -ENOMEM;
1697 memcpy(&temp->fs, flow, sizeof(temp->fs));
1698
1699 gfar_invert_masks(&temp->fs);
1700 ret = gfar_check_capability(&temp->fs, priv);
1701 if (ret)
1702 goto clean_mem;
1703 /* Link in the new element at the right @location */
1704 if (list_empty(&priv->rx_list.list)) {
1705 ret = gfar_check_filer_hardware(priv);
1706 if (ret != 0)
1707 goto clean_mem;
1708 list_add(&temp->list, &priv->rx_list.list);
1709 goto process;
1710 } else {
4aa3a715
SP		 1711 list_for_each_entry(comp, &priv->rx_list.list, list) {
1712 if (comp->fs.location > flow->location) {
1713 list_add_tail(&temp->list, &comp->list);
1714 goto process;
1715 }
1716 if (comp->fs.location == flow->location) {
1717 netdev_err(priv->ndev,
cbfc6071
JC		 1718 "Rule not added: ID %d not free!\n",
1719 flow->location);
4aa3a715
SP		 1720 ret = -EBUSY;
1721 goto clean_mem;
1722 }
1723 }
1724 list_add_tail(&temp->list, &priv->rx_list.list);
1725 }
1726
1727process:
1728 ret = gfar_process_filer_changes(priv);
1729 if (ret)
1730 goto clean_list;
1731 priv->rx_list.count++;
1732 return ret;
1733
1734clean_list:
1735 list_del(&temp->list);
1736clean_mem:
1737 kfree(temp);
1738 return ret;
1739}
1740
1741static int gfar_del_cls(struct gfar_private *priv, u32 loc)
1742{
1743 struct ethtool_flow_spec_container *comp;
1744 u32 ret = -EINVAL;
1745
1746 if (list_empty(&priv->rx_list.list))
1747 return ret;
1748
1749 list_for_each_entry(comp, &priv->rx_list.list, list) {
1750 if (comp->fs.location == loc) {
1751 list_del(&comp->list);
1752 kfree(comp);
1753 priv->rx_list.count--;
1754 gfar_process_filer_changes(priv);
1755 ret = 0;
1756 break;
1757 }
1758 }
1759
1760 return ret;
4aa3a715
SP		 1761}
1762
1763static int gfar_get_cls(struct gfar_private *priv, struct ethtool_rxnfc *cmd)
1764{
1765 struct ethtool_flow_spec_container *comp;
1766 u32 ret = -EINVAL;
1767
1768 list_for_each_entry(comp, &priv->rx_list.list, list) {
1769 if (comp->fs.location == cmd->fs.location) {
1770 memcpy(&cmd->fs, &comp->fs, sizeof(cmd->fs));
1771 gfar_invert_masks(&cmd->fs);
1772 ret = 0;
1773 break;
1774 }
1775 }
1776
1777 return ret;
1778}
1779
1780static int gfar_get_cls_all(struct gfar_private *priv,
cbfc6071 1781 struct ethtool_rxnfc *cmd, u32 *rule_locs)
4aa3a715
SP		 1782{
1783 struct ethtool_flow_spec_container *comp;
1784 u32 i = 0;
1785
1786 list_for_each_entry(comp, &priv->rx_list.list, list) {
710778ff
BH		 1787 if (i == cmd->rule_cnt)
1788 return -EMSGSIZE;
1789 rule_locs[i] = comp->fs.location;
1790 i++;
4aa3a715
SP		 1791 }
1792
1793 cmd->data = MAX_FILER_IDX;
473e64ee 1794 cmd->rule_cnt = i;
4aa3a715
SP		 1795
1796 return 0;
1797}
1798
7a8b3372
SG		 1799static int gfar_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1800{
1801 struct gfar_private *priv = netdev_priv(dev);
1802 int ret = 0;
1803
0851133b
CM		 1804 if (test_bit(GFAR_RESETTING, &priv->state))
1805 return -EBUSY;
1806
4aa3a715
SP		 1807 mutex_lock(&priv->rx_queue_access);
1808
1809 switch (cmd->cmd) {
7a8b3372
SG		 1810 case ETHTOOL_SRXFH:
1811 ret = gfar_set_hash_opts(priv, cmd);
1812 break;
4aa3a715 1813 case ETHTOOL_SRXCLSRLINS:
3a73e49c
BH		 1814 if ((cmd->fs.ring_cookie != RX_CLS_FLOW_DISC &&
1815 cmd->fs.ring_cookie >= priv->num_rx_queues) ||
1816 cmd->fs.location >= MAX_FILER_IDX) {
4aa3a715
SP		 1817 ret = -EINVAL;
1818 break;
1819 }
1820 ret = gfar_add_cls(priv, &cmd->fs);
1821 break;
1822 case ETHTOOL_SRXCLSRLDEL:
1823 ret = gfar_del_cls(priv, cmd->fs.location);
1824 break;
7a8b3372
SG		 1825 default:
1826 ret = -EINVAL;
1827 }
1828
4aa3a715
SP		 1829 mutex_unlock(&priv->rx_queue_access);
1830
1831 return ret;
1832}
1833
1834static int gfar_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
cbfc6071 1835 u32 *rule_locs)
4aa3a715
SP		 1836{
1837 struct gfar_private *priv = netdev_priv(dev);
1838 int ret = 0;
1839
1840 switch (cmd->cmd) {
1841 case ETHTOOL_GRXRINGS:
1842 cmd->data = priv->num_rx_queues;
1843 break;
1844 case ETHTOOL_GRXCLSRLCNT:
1845 cmd->rule_cnt = priv->rx_list.count;
1846 break;
1847 case ETHTOOL_GRXCLSRULE:
1848 ret = gfar_get_cls(priv, cmd);
1849 break;
1850 case ETHTOOL_GRXCLSRLALL:
815c7db5 1851 ret = gfar_get_cls_all(priv, cmd, rule_locs);
4aa3a715
SP		 1852 break;
1853 default:
1854 ret = -EINVAL;
1855 break;
1856 }
1857
7a8b3372
SG		 1858 return ret;
1859}
1860
66636287 1861int gfar_phc_index = -1;
28889b7e 1862EXPORT_SYMBOL(gfar_phc_index);
66636287
RC		 1863
1864static int gfar_get_ts_info(struct net_device *dev,
1865 struct ethtool_ts_info *info)
1866{
1867 struct gfar_private *priv = netdev_priv(dev);
1868
1869 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)) {
cbfc6071
JC		 1870 info->so_timestamping = SOF_TIMESTAMPING_RX_SOFTWARE |
1871 SOF_TIMESTAMPING_SOFTWARE;
66636287
RC		 1872 info->phc_index = -1;
1873 return 0;
1874 }
cbfc6071
JC		 1875 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1876 SOF_TIMESTAMPING_RX_HARDWARE |
1877 SOF_TIMESTAMPING_RAW_HARDWARE;
66636287 1878 info->phc_index = gfar_phc_index;
cbfc6071
JC		 1879 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1880 (1 << HWTSTAMP_TX_ON);
1881 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1882 (1 << HWTSTAMP_FILTER_ALL);
66636287
RC		 1883 return 0;
1884}
1885
7282d491 1886const struct ethtool_ops gfar_ethtool_ops = {
1da177e4 1887 .get_settings = gfar_gsettings,
bb40dcbb 1888 .set_settings = gfar_ssettings,
1da177e4
LT		 1889 .get_drvinfo = gfar_gdrvinfo,
1890 .get_regs_len = gfar_reglen,
1891 .get_regs = gfar_get_regs,
1892 .get_link = ethtool_op_get_link,
1893 .get_coalesce = gfar_gcoalesce,
1894 .set_coalesce = gfar_scoalesce,
1895 .get_ringparam = gfar_gringparam,
1896 .set_ringparam = gfar_sringparam,
23402bdd
CM		 1897 .get_pauseparam = gfar_gpauseparam,
1898 .set_pauseparam = gfar_spauseparam,
1da177e4 1899 .get_strings = gfar_gstrings,
b9f2c044 1900 .get_sset_count = gfar_sset_count,
1da177e4 1901 .get_ethtool_stats = gfar_fill_stats,
0bbaf069
KG		 1902 .get_msglevel = gfar_get_msglevel,
1903 .set_msglevel = gfar_set_msglevel,
d87eb127
SW		 1904#ifdef CONFIG_PM
1905 .get_wol = gfar_get_wol,
1906 .set_wol = gfar_set_wol,
1907#endif
7a8b3372 1908 .set_rxnfc = gfar_set_nfc,
4aa3a715 1909 .get_rxnfc = gfar_get_nfc,
66636287 1910 .get_ts_info = gfar_get_ts_info,
1da177e4 1911};
Linux kernel - Deliverables
This page took 1.467626 seconds and 5 git commands to generate.