[deliverable/linux.git] / drivers / net / ethernet / freescale / gianfar_ptp.c

/*
 * PTP 1588 clock using the eTSEC
 *
 * Copyright (C) 2010 OMICRON electronics GmbH
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/device.h>
#include <linux/hrtimer.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/timex.h>
#include <linux/io.h>

#include <linux/ptp_clock_kernel.h>

#include "gianfar.h"

/*
 * gianfar ptp registers
 * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
 */
struct gianfar_ptp_registers {
	u32 tmr_ctrl;     /* Timer control register */
	u32 tmr_tevent;   /* Timestamp event register */
	u32 tmr_temask;   /* Timer event mask register */
	u32 tmr_pevent;   /* Timestamp event register */
	u32 tmr_pemask;   /* Timer event mask register */
	u32 tmr_stat;     /* Timestamp status register */
	u32 tmr_cnt_h;    /* Timer counter high register */
	u32 tmr_cnt_l;    /* Timer counter low register */
	u32 tmr_add;      /* Timer drift compensation addend register */
	u32 tmr_acc;      /* Timer accumulator register */
	u32 tmr_prsc;     /* Timer prescale */
	u8  res1[4];
	u32 tmroff_h;     /* Timer offset high */
	u32 tmroff_l;     /* Timer offset low */
	u8  res2[8];
	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
	u8  res3[48];
	u32 tmr_fiper1;   /* Timer fixed period interval */
	u32 tmr_fiper2;   /* Timer fixed period interval */
	u32 tmr_fiper3;   /* Timer fixed period interval */
	u8  res4[20];
	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
};

/* Bit definitions for the TMR_CTRL register */
#define ALM1P                 (1<<31) /* Alarm1 output polarity */
#define ALM2P                 (1<<30) /* Alarm2 output polarity */
#define FS                    (1<<28) /* FIPER start indication */
#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
#define TCLK_PERIOD_MASK      (0x3ff)
#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
#define FRD                   (1<<14) /* FIPER Realignment Disable */
#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
#define COPH                  (1<<7) /* Generated clock output phase. */
#define CIPH                  (1<<6) /* External oscillator input clock phase */
#define TMSR                  (1<<5) /* Timer soft reset. */
#define BYP                   (1<<3) /* Bypass drift compensated clock */
#define TE                    (1<<2) /* 1588 timer enable. */
#define CKSEL_SHIFT           (0)    /* 1588 Timer reference clock source */
#define CKSEL_MASK            (0x3)

/* Bit definitions for the TMR_TEVENT register */
#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
#define ALM2                  (1<<17) /* Current time = alarm time register 2 */
#define ALM1                  (1<<16) /* Current time = alarm time register 1 */
#define PP1                   (1<<7)  /* periodic pulse generated on FIPER1 */
#define PP2                   (1<<6)  /* periodic pulse generated on FIPER2 */
#define PP3                   (1<<5)  /* periodic pulse generated on FIPER3 */

/* Bit definitions for the TMR_TEMASK register */
#define ETS2EN                (1<<25) /* External trigger 2 timestamp enable */
#define ETS1EN                (1<<24) /* External trigger 1 timestamp enable */
#define ALM2EN                (1<<17) /* Timer ALM2 event enable */
#define ALM1EN                (1<<16) /* Timer ALM1 event enable */
#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */

/* Bit definitions for the TMR_PEVENT register */
#define TXP2                  (1<<9) /* PTP transmitted timestamp im TXTS2 */
#define TXP1                  (1<<8) /* PTP transmitted timestamp in TXTS1 */
#define RXP                   (1<<0) /* PTP frame has been received */

/* Bit definitions for the TMR_PEMASK register */
#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
#define RXPEN                 (1<<0) /* Receive PTP packet event enable */

/* Bit definitions for the TMR_STAT register */
#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
#define STAT_VEC_MASK         (0x3f)

/* Bit definitions for the TMR_PRSC register */
#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
#define PRSC_OCK_MASK         (0xffff)


#define DRIVER		"gianfar_ptp"
#define DEFAULT_CKSEL	1
#define N_EXT_TS	2
#define REG_SIZE	sizeof(struct gianfar_ptp_registers)

struct etsects {
	struct gianfar_ptp_registers __iomem *regs;
	spinlock_t lock; /* protects regs */
	struct ptp_clock *clock;
	struct ptp_clock_info caps;
	struct resource *rsrc;
	int irq;
	u64 alarm_interval; /* for periodic alarm */
	u64 alarm_value;
	u32 tclk_period;  /* nanoseconds */
	u32 tmr_prsc;
	u32 tmr_add;
	u32 cksel;
	u32 tmr_fiper1;
	u32 tmr_fiper2;
};

/*
 * Register access functions
 */

/* Caller must hold etsects->lock. */
static u64 tmr_cnt_read(struct etsects *etsects)
{
	u64 ns;
	u32 lo, hi;

	lo = gfar_read(&etsects->regs->tmr_cnt_l);
	hi = gfar_read(&etsects->regs->tmr_cnt_h);
	ns = ((u64) hi) << 32;
	ns |= lo;
	return ns;
}

/* Caller must hold etsects->lock. */
static void tmr_cnt_write(struct etsects *etsects, u64 ns)
{
	u32 hi = ns >> 32;
	u32 lo = ns & 0xffffffff;

	gfar_write(&etsects->regs->tmr_cnt_l, lo);
	gfar_write(&etsects->regs->tmr_cnt_h, hi);
}

/* Caller must hold etsects->lock. */
static void set_alarm(struct etsects *etsects)
{
	u64 ns;
	u32 lo, hi;

	ns = tmr_cnt_read(etsects) + 1500000000ULL;
	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
	ns -= etsects->tclk_period;
	hi = ns >> 32;
	lo = ns & 0xffffffff;
	gfar_write(&etsects->regs->tmr_alarm1_l, lo);
	gfar_write(&etsects->regs->tmr_alarm1_h, hi);
}

/* Caller must hold etsects->lock. */
static void set_fipers(struct etsects *etsects)
{
	set_alarm(etsects);
	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
}

/*
 * Interrupt service routine
 */

static irqreturn_t isr(int irq, void *priv)
{
	struct etsects *etsects = priv;
	struct ptp_clock_event event;
	u64 ns;
	u32 ack = 0, lo, hi, mask, val;

	val = gfar_read(&etsects->regs->tmr_tevent);

	if (val & ETS1) {
		ack |= ETS1;
		hi = gfar_read(&etsects->regs->tmr_etts1_h);
		lo = gfar_read(&etsects->regs->tmr_etts1_l);
		event.type = PTP_CLOCK_EXTTS;
		event.index = 0;
		event.timestamp = ((u64) hi) << 32;
		event.timestamp |= lo;
		ptp_clock_event(etsects->clock, &event);
	}

	if (val & ETS2) {
		ack |= ETS2;
		hi = gfar_read(&etsects->regs->tmr_etts2_h);
		lo = gfar_read(&etsects->regs->tmr_etts2_l);
		event.type = PTP_CLOCK_EXTTS;
		event.index = 1;
		event.timestamp = ((u64) hi) << 32;
		event.timestamp |= lo;
		ptp_clock_event(etsects->clock, &event);
	}

	if (val & ALM2) {
		ack |= ALM2;
		if (etsects->alarm_value) {
			event.type = PTP_CLOCK_ALARM;
			event.index = 0;
			event.timestamp = etsects->alarm_value;
			ptp_clock_event(etsects->clock, &event);
		}
		if (etsects->alarm_interval) {
			ns = etsects->alarm_value + etsects->alarm_interval;
			hi = ns >> 32;
			lo = ns & 0xffffffff;
			spin_lock(&etsects->lock);
			gfar_write(&etsects->regs->tmr_alarm2_l, lo);
			gfar_write(&etsects->regs->tmr_alarm2_h, hi);
			spin_unlock(&etsects->lock);
			etsects->alarm_value = ns;
		} else {
			gfar_write(&etsects->regs->tmr_tevent, ALM2);
			spin_lock(&etsects->lock);
			mask = gfar_read(&etsects->regs->tmr_temask);
			mask &= ~ALM2EN;
			gfar_write(&etsects->regs->tmr_temask, mask);
			spin_unlock(&etsects->lock);
			etsects->alarm_value = 0;
			etsects->alarm_interval = 0;
		}
	}

	if (val & PP1) {
		ack |= PP1;
		event.type = PTP_CLOCK_PPS;
		ptp_clock_event(etsects->clock, &event);
	}

	if (ack) {
		gfar_write(&etsects->regs->tmr_tevent, ack);
		return IRQ_HANDLED;
	} else
		return IRQ_NONE;
}

/*
 * PTP clock operations
 */

static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 adj;
	u32 diff, tmr_add;
	int neg_adj = 0;
	struct etsects *etsects = container_of(ptp, struct etsects, caps);

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	tmr_add = etsects->tmr_add;
	adj = tmr_add;
	adj *= ppb;
	diff = div_u64(adj, 1000000000ULL);

	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;

	gfar_write(&etsects->regs->tmr_add, tmr_add);

	return 0;
}

static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	s64 now;
	unsigned long flags;
	struct etsects *etsects = container_of(ptp, struct etsects, caps);

	spin_lock_irqsave(&etsects->lock, flags);

	now = tmr_cnt_read(etsects);
	now += delta;
	tmr_cnt_write(etsects, now);

	spin_unlock_irqrestore(&etsects->lock, flags);

	set_fipers(etsects);

	return 0;
}

static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
			       struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct etsects *etsects = container_of(ptp, struct etsects, caps);

	spin_lock_irqsave(&etsects->lock, flags);

	ns = tmr_cnt_read(etsects);

	spin_unlock_irqrestore(&etsects->lock, flags);

	*ts = ns_to_timespec64(ns);

	return 0;
}

static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
			       const struct timespec64 *ts)
{
	u64 ns;
	unsigned long flags;
	struct etsects *etsects = container_of(ptp, struct etsects, caps);

	ns = timespec64_to_ns(ts);

	spin_lock_irqsave(&etsects->lock, flags);

	tmr_cnt_write(etsects, ns);
	set_fipers(etsects);

	spin_unlock_irqrestore(&etsects->lock, flags);

	return 0;
}

static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
			      struct ptp_clock_request *rq, int on)
{
	struct etsects *etsects = container_of(ptp, struct etsects, caps);
	unsigned long flags;
	u32 bit, mask;

	switch (rq->type) {
	case PTP_CLK_REQ_EXTTS:
		switch (rq->extts.index) {
		case 0:
			bit = ETS1EN;
			break;
		case 1:
			bit = ETS2EN;
			break;
		default:
			return -EINVAL;
		}
		spin_lock_irqsave(&etsects->lock, flags);
		mask = gfar_read(&etsects->regs->tmr_temask);
		if (on)
			mask |= bit;
		else
			mask &= ~bit;
		gfar_write(&etsects->regs->tmr_temask, mask);
		spin_unlock_irqrestore(&etsects->lock, flags);
		return 0;

	case PTP_CLK_REQ_PPS:
		spin_lock_irqsave(&etsects->lock, flags);
		mask = gfar_read(&etsects->regs->tmr_temask);
		if (on)
			mask |= PP1EN;
		else
			mask &= ~PP1EN;
		gfar_write(&etsects->regs->tmr_temask, mask);
		spin_unlock_irqrestore(&etsects->lock, flags);
		return 0;

	default:
		break;
	}

	return -EOPNOTSUPP;
}

static struct ptp_clock_info ptp_gianfar_caps = {
	.owner		= THIS_MODULE,
	.name		= "gianfar clock",
	.max_adj	= 512000,
	.n_alarm	= 0,
	.n_ext_ts	= N_EXT_TS,
	.n_per_out	= 0,
	.n_pins		= 0,
	.pps		= 1,
	.adjfreq	= ptp_gianfar_adjfreq,
	.adjtime	= ptp_gianfar_adjtime,
	.gettime64	= ptp_gianfar_gettime,
	.settime64	= ptp_gianfar_settime,
	.enable		= ptp_gianfar_enable,
};

static int gianfar_ptp_probe(struct platform_device *dev)
{
	struct device_node *node = dev->dev.of_node;
	struct etsects *etsects;
	struct timespec64 now;
	int err = -ENOMEM;
	u32 tmr_ctrl;
	unsigned long flags;

	etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
	if (!etsects)
		goto no_memory;

	err = -ENODEV;

	etsects->caps = ptp_gianfar_caps;

	if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
		etsects->cksel = DEFAULT_CKSEL;

	if (of_property_read_u32(node,
				 "fsl,tclk-period", &etsects->tclk_period) ||
	    of_property_read_u32(node,
				 "fsl,tmr-prsc", &etsects->tmr_prsc) ||
	    of_property_read_u32(node,
				 "fsl,tmr-add", &etsects->tmr_add) ||
	    of_property_read_u32(node,
				 "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
	    of_property_read_u32(node,
				 "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
	    of_property_read_u32(node,
				 "fsl,max-adj", &etsects->caps.max_adj)) {
		pr_err("device tree node missing required elements\n");
		goto no_node;
	}

	etsects->irq = platform_get_irq(dev, 0);

	if (etsects->irq < 0) {
		pr_err("irq not in device tree\n");
		goto no_node;
	}
	if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
		pr_err("request_irq failed\n");
		goto no_node;
	}

	etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!etsects->rsrc) {
		pr_err("no resource\n");
		goto no_resource;
	}
	if (request_resource(&iomem_resource, etsects->rsrc)) {
		pr_err("resource busy\n");
		goto no_resource;
	}

	spin_lock_init(&etsects->lock);

	etsects->regs = ioremap(etsects->rsrc->start,
				resource_size(etsects->rsrc));
	if (!etsects->regs) {
		pr_err("ioremap ptp registers failed\n");
		goto no_ioremap;
	}
	getnstimeofday64(&now);
	ptp_gianfar_settime(&etsects->caps, &now);

	tmr_ctrl =
	  (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
	  (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;

	spin_lock_irqsave(&etsects->lock, flags);

	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
	gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
	gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
	set_alarm(etsects);
	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FS|RTPE|TE|FRD);

	spin_unlock_irqrestore(&etsects->lock, flags);

	etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
	if (IS_ERR(etsects->clock)) {
		err = PTR_ERR(etsects->clock);
		goto no_clock;
	}
	gfar_phc_index = ptp_clock_index(etsects->clock);

	platform_set_drvdata(dev, etsects);

	return 0;

no_clock:
	iounmap(etsects->regs);
no_ioremap:
	release_resource(etsects->rsrc);
no_resource:
	free_irq(etsects->irq, etsects);
no_node:
	kfree(etsects);
no_memory:
	return err;
}

static int gianfar_ptp_remove(struct platform_device *dev)
{
	struct etsects *etsects = platform_get_drvdata(dev);

	gfar_write(&etsects->regs->tmr_temask, 0);
	gfar_write(&etsects->regs->tmr_ctrl,   0);

	gfar_phc_index = -1;
	ptp_clock_unregister(etsects->clock);
	iounmap(etsects->regs);
	release_resource(etsects->rsrc);
	free_irq(etsects->irq, etsects);
	kfree(etsects);

	return 0;
}

static const struct of_device_id match_table[] = {
	{ .compatible = "fsl,etsec-ptp" },
	{},
};
MODULE_DEVICE_TABLE(of, match_table);

static struct platform_driver gianfar_ptp_driver = {
	.driver = {
		.name		= "gianfar_ptp",
		.of_match_table	= match_table,
	},
	.probe       = gianfar_ptp_probe,
	.remove      = gianfar_ptp_remove,
};

module_platform_driver(gianfar_ptp_driver);

MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
MODULE_DESCRIPTION("PTP clock using the eTSEC");
MODULE_LICENSE("GPL");
Commit	Line	Data
c78275f3 RC	1	/*
	2	* PTP 1588 clock using the eTSEC
	3	*
	4	* Copyright (C) 2010 OMICRON electronics GmbH
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
375d6a1b JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
c78275f3 RC	23	#include <linux/device.h>
c78275f3 RC	24	#include <linux/hrtimer.h>
c78275f3 RC	25	#include <linux/interrupt.h>
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/of.h>
	29	#include <linux/of_platform.h>
	30	#include <linux/timex.h>
	31	#include <linux/io.h>
	32
	33	#include <linux/ptp_clock_kernel.h>
	34
	35	#include "gianfar.h"
	36
	37	/*
	38	* gianfar ptp registers
	39	* Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
	40	*/
	41	struct gianfar_ptp_registers {
	42	u32 tmr_ctrl; /* Timer control register */
	43	u32 tmr_tevent; /* Timestamp event register */
	44	u32 tmr_temask; /* Timer event mask register */
	45	u32 tmr_pevent; /* Timestamp event register */
	46	u32 tmr_pemask; /* Timer event mask register */
	47	u32 tmr_stat; /* Timestamp status register */
	48	u32 tmr_cnt_h; /* Timer counter high register */
	49	u32 tmr_cnt_l; /* Timer counter low register */
	50	u32 tmr_add; /* Timer drift compensation addend register */
	51	u32 tmr_acc; /* Timer accumulator register */
	52	u32 tmr_prsc; /* Timer prescale */
	53	u8 res1[4];
	54	u32 tmroff_h; /* Timer offset high */
	55	u32 tmroff_l; /* Timer offset low */
	56	u8 res2[8];
	57	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
	58	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
	59	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
	60	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
	61	u8 res3[48];
	62	u32 tmr_fiper1; /* Timer fixed period interval */
	63	u32 tmr_fiper2; /* Timer fixed period interval */
	64	u32 tmr_fiper3; /* Timer fixed period interval */
	65	u8 res4[20];
	66	u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
	67	u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
	68	u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
	69	u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
	70	};
	71
	72	/* Bit definitions for the TMR_CTRL register */
	73	#define ALM1P (1<<31) /* Alarm1 output polarity */
	74	#define ALM2P (1<<30) /* Alarm2 output polarity */
	75	#define FS (1<<28) /* FIPER start indication */
	76	#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
	77	#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
	78	#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
	79	#define TCLK_PERIOD_MASK (0x3ff)
	80	#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
	81	#define FRD (1<<14) /* FIPER Realignment Disable */
	82	#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
	83	#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
	84	#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
	85	#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
	86	#define COPH (1<<7) /* Generated clock output phase. */
	87	#define CIPH (1<<6) /* External oscillator input clock phase */
	88	#define TMSR (1<<5) /* Timer soft reset. */
89	#define BYP (1<<3) /* Bypass drift compensated clock */
90	#define TE (1<<2) /* 1588 timer enable. */
91	#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
92	#define CKSEL_MASK (0x3)
93
94	/* Bit definitions for the TMR_TEVENT register */
95	#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
96	#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
97	#define ALM2 (1<<17) /* Current time = alarm time register 2 */
98	#define ALM1 (1<<16) /* Current time = alarm time register 1 */
99	#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
100	#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
101	#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
102
103	/* Bit definitions for the TMR_TEMASK register */
104	#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
105	#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
106	#define ALM2EN (1<<17) /* Timer ALM2 event enable */
107	#define ALM1EN (1<<16) /* Timer ALM1 event enable */
108	#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
109	#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
110
111	/* Bit definitions for the TMR_PEVENT register */
112	#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
113	#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
114	#define RXP (1<<0) /* PTP frame has been received */
115
116	/* Bit definitions for the TMR_PEMASK register */
117	#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
118	#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
119	#define RXPEN (1<<0) /* Receive PTP packet event enable */
120
121	/* Bit definitions for the TMR_STAT register */
122	#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
123	#define STAT_VEC_MASK (0x3f)
124
125	/* Bit definitions for the TMR_PRSC register */
126	#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
127	#define PRSC_OCK_MASK (0xffff)
128
129
130	#define DRIVER "gianfar_ptp"
131	#define DEFAULT_CKSEL 1
c78275f3 RC	132	#define N_EXT_TS 2
	133	#define REG_SIZE sizeof(struct gianfar_ptp_registers)
	134
	135	struct etsects {
42851e88	136	struct gianfar_ptp_registers __iomem *regs;
c78275f3 RC	137	spinlock_t lock; /* protects regs */
	138	struct ptp_clock *clock;
	139	struct ptp_clock_info caps;
	140	struct resource *rsrc;
	141	int irq;
	142	u64 alarm_interval; /* for periodic alarm */
	143	u64 alarm_value;
	144	u32 tclk_period; /* nanoseconds */
	145	u32 tmr_prsc;
	146	u32 tmr_add;
	147	u32 cksel;
	148	u32 tmr_fiper1;
	149	u32 tmr_fiper2;
	150	};
	151
	152	/*
	153	* Register access functions
	154	*/
	155
	156	/* Caller must hold etsects->lock. */
	157	static u64 tmr_cnt_read(struct etsects *etsects)
	158	{
	159	u64 ns;
	160	u32 lo, hi;
	161
	162	lo = gfar_read(&etsects->regs->tmr_cnt_l);
	163	hi = gfar_read(&etsects->regs->tmr_cnt_h);
	164	ns = ((u64) hi) << 32;
	165	ns \|= lo;
	166	return ns;
	167	}
	168
	169	/* Caller must hold etsects->lock. */
	170	static void tmr_cnt_write(struct etsects *etsects, u64 ns)
	171	{
	172	u32 hi = ns >> 32;
	173	u32 lo = ns & 0xffffffff;
	174
	175	gfar_write(&etsects->regs->tmr_cnt_l, lo);
	176	gfar_write(&etsects->regs->tmr_cnt_h, hi);
	177	}
	178
	179	/* Caller must hold etsects->lock. */
	180	static void set_alarm(struct etsects *etsects)
	181	{
	182	u64 ns;
	183	u32 lo, hi;
	184
	185	ns = tmr_cnt_read(etsects) + 1500000000ULL;
	186	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
	187	ns -= etsects->tclk_period;
	188	hi = ns >> 32;
	189	lo = ns & 0xffffffff;
	190	gfar_write(&etsects->regs->tmr_alarm1_l, lo);
	191	gfar_write(&etsects->regs->tmr_alarm1_h, hi);
	192	}
	193
	194	/* Caller must hold etsects->lock. */
	195	static void set_fipers(struct etsects *etsects)
	196	{
cbc05660	197	set_alarm(etsects);
c78275f3 RC	198	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
c78275f3 RC	199	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
c78275f3 RC	200	}
	201
	202	/*
	203	* Interrupt service routine
	204	*/
	205
	206	static irqreturn_t isr(int irq, void *priv)
	207	{
	208	struct etsects *etsects = priv;
	209	struct ptp_clock_event event;
	210	u64 ns;
	211	u32 ack = 0, lo, hi, mask, val;
	212
	213	val = gfar_read(&etsects->regs->tmr_tevent);
	214
	215	if (val & ETS1) {
	216	ack \|= ETS1;
	217	hi = gfar_read(&etsects->regs->tmr_etts1_h);
	218	lo = gfar_read(&etsects->regs->tmr_etts1_l);
	219	event.type = PTP_CLOCK_EXTTS;
	220	event.index = 0;
	221	event.timestamp = ((u64) hi) << 32;
	222	event.timestamp \|= lo;
	223	ptp_clock_event(etsects->clock, &event);
	224	}
	225
	226	if (val & ETS2) {
	227	ack \|= ETS2;
	228	hi = gfar_read(&etsects->regs->tmr_etts2_h);
	229	lo = gfar_read(&etsects->regs->tmr_etts2_l);
	230	event.type = PTP_CLOCK_EXTTS;
	231	event.index = 1;
	232	event.timestamp = ((u64) hi) << 32;
	233	event.timestamp \|= lo;
	234	ptp_clock_event(etsects->clock, &event);
	235	}
	236
	237	if (val & ALM2) {
	238	ack \|= ALM2;
	239	if (etsects->alarm_value) {
	240	event.type = PTP_CLOCK_ALARM;
	241	event.index = 0;
	242	event.timestamp = etsects->alarm_value;
	243	ptp_clock_event(etsects->clock, &event);
	244	}
	245	if (etsects->alarm_interval) {
	246	ns = etsects->alarm_value + etsects->alarm_interval;
	247	hi = ns >> 32;
	248	lo = ns & 0xffffffff;
	249	spin_lock(&etsects->lock);
	250	gfar_write(&etsects->regs->tmr_alarm2_l, lo);
	251	gfar_write(&etsects->regs->tmr_alarm2_h, hi);
	252	spin_unlock(&etsects->lock);
	253	etsects->alarm_value = ns;
	254	} else {
	255	gfar_write(&etsects->regs->tmr_tevent, ALM2);
	256	spin_lock(&etsects->lock);
	257	mask = gfar_read(&etsects->regs->tmr_temask);
	258	mask &= ~ALM2EN;
	259	gfar_write(&etsects->regs->tmr_temask, mask);
	260	spin_unlock(&etsects->lock);
	261	etsects->alarm_value = 0;
	262	etsects->alarm_interval = 0;
	263	}
264	}
265
266	if (val & PP1) {
267	ack \|= PP1;
268	event.type = PTP_CLOCK_PPS;
269	ptp_clock_event(etsects->clock, &event);
270	}
271
272	if (ack) {
273	gfar_write(&etsects->regs->tmr_tevent, ack);
274	return IRQ_HANDLED;
275	} else
276	return IRQ_NONE;
277	}
278
279	/*
280	* PTP clock operations
281	*/
282
283	static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
284	{
285	u64 adj;
286	u32 diff, tmr_add;
287	int neg_adj = 0;
288	struct etsects *etsects = container_of(ptp, struct etsects, caps);
289
290	if (ppb < 0) {
291	neg_adj = 1;
292	ppb = -ppb;
293	}
294	tmr_add = etsects->tmr_add;
295	adj = tmr_add;
296	adj *= ppb;
297	diff = div_u64(adj, 1000000000ULL);
298
299	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
300
301	gfar_write(&etsects->regs->tmr_add, tmr_add);
302
303	return 0;
304	}
305
306	static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
307	{
308	s64 now;
309	unsigned long flags;
310	struct etsects *etsects = container_of(ptp, struct etsects, caps);
311
312	spin_lock_irqsave(&etsects->lock, flags);
313
314	now = tmr_cnt_read(etsects);
315	now += delta;
316	tmr_cnt_write(etsects, now);
317
318	spin_unlock_irqrestore(&etsects->lock, flags);
319
320	set_fipers(etsects);
321
322	return 0;
323	}
324
d28fdf0f RC	325	static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
d28fdf0f RC	326	struct timespec64 *ts)
c78275f3 RC	327	{
c78275f3 RC	328	u64 ns;
c78275f3 RC	329	unsigned long flags;
	330	struct etsects *etsects = container_of(ptp, struct etsects, caps);
	331
	332	spin_lock_irqsave(&etsects->lock, flags);
	333
	334	ns = tmr_cnt_read(etsects);
	335
	336	spin_unlock_irqrestore(&etsects->lock, flags);
	337
3359e7c2 RC	338	*ts = ns_to_timespec64(ns);
3359e7c2 RC	339
c78275f3 RC	340	return 0;
	341	}
	342
	343	static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
d28fdf0f	344	const struct timespec64 *ts)
c78275f3 RC	345	{
	346	u64 ns;
	347	unsigned long flags;
	348	struct etsects *etsects = container_of(ptp, struct etsects, caps);
	349
3359e7c2	350	ns = timespec64_to_ns(ts);
c78275f3 RC	351
	352	spin_lock_irqsave(&etsects->lock, flags);
	353
	354	tmr_cnt_write(etsects, ns);
	355	set_fipers(etsects);
	356
	357	spin_unlock_irqrestore(&etsects->lock, flags);
	358
	359	return 0;
	360	}
	361
	362	static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
	363	struct ptp_clock_request *rq, int on)
	364	{
	365	struct etsects *etsects = container_of(ptp, struct etsects, caps);
	366	unsigned long flags;
	367	u32 bit, mask;
	368
	369	switch (rq->type) {
	370	case PTP_CLK_REQ_EXTTS:
	371	switch (rq->extts.index) {
	372	case 0:
	373	bit = ETS1EN;
	374	break;
	375	case 1:
	376	bit = ETS2EN;
	377	break;
	378	default:
	379	return -EINVAL;
	380	}
	381	spin_lock_irqsave(&etsects->lock, flags);
	382	mask = gfar_read(&etsects->regs->tmr_temask);
	383	if (on)
	384	mask \|= bit;
	385	else
	386	mask &= ~bit;
	387	gfar_write(&etsects->regs->tmr_temask, mask);
	388	spin_unlock_irqrestore(&etsects->lock, flags);
	389	return 0;
	390
	391	case PTP_CLK_REQ_PPS:
	392	spin_lock_irqsave(&etsects->lock, flags);
	393	mask = gfar_read(&etsects->regs->tmr_temask);
	394	if (on)
	395	mask \|= PP1EN;
	396	else
	397	mask &= ~PP1EN;
	398	gfar_write(&etsects->regs->tmr_temask, mask);
	399	spin_unlock_irqrestore(&etsects->lock, flags);
	400	return 0;
	401
	402	default:
	403	break;
	404	}
	405
	406	return -EOPNOTSUPP;
	407	}
	408
	409	static struct ptp_clock_info ptp_gianfar_caps = {
	410	.owner = THIS_MODULE,
	411	.name = "gianfar clock",
	412	.max_adj = 512000,
cd4baaaa	413	.n_alarm = 0,
c78275f3 RC	414	.n_ext_ts = N_EXT_TS,
c78275f3 RC	415	.n_per_out = 0,
4986b4f0	416	.n_pins = 0,
c78275f3 RC	417	.pps = 1,
	418	.adjfreq = ptp_gianfar_adjfreq,
	419	.adjtime = ptp_gianfar_adjtime,
d28fdf0f RC	420	.gettime64 = ptp_gianfar_gettime,
d28fdf0f RC	421	.settime64 = ptp_gianfar_settime,
c78275f3 RC	422	.enable = ptp_gianfar_enable,
	423	};
	424
c78275f3 RC	425	static int gianfar_ptp_probe(struct platform_device *dev)
	426	{
	427	struct device_node *node = dev->dev.of_node;
	428	struct etsects *etsects;
d28fdf0f	429	struct timespec64 now;
c78275f3 RC	430	int err = -ENOMEM;
	431	u32 tmr_ctrl;
	432	unsigned long flags;
	433
	434	etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
	435	if (!etsects)
	436	goto no_memory;
	437
	438	err = -ENODEV;
	439
	440	etsects->caps = ptp_gianfar_caps;
e58f6f4f	441
c35ec779	442	if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
e58f6f4f	443	etsects->cksel = DEFAULT_CKSEL;
c78275f3	444
c35ec779 YL	445	if (of_property_read_u32(node,
	446	"fsl,tclk-period", &etsects->tclk_period) \|\|
	447	of_property_read_u32(node,
	448	"fsl,tmr-prsc", &etsects->tmr_prsc) \|\|
	449	of_property_read_u32(node,
	450	"fsl,tmr-add", &etsects->tmr_add) \|\|
	451	of_property_read_u32(node,
	452	"fsl,tmr-fiper1", &etsects->tmr_fiper1) \|\|
	453	of_property_read_u32(node,
	454	"fsl,tmr-fiper2", &etsects->tmr_fiper2) \|\|
	455	of_property_read_u32(node,
	456	"fsl,max-adj", &etsects->caps.max_adj)) {
c78275f3 RC	457	pr_err("device tree node missing required elements\n");
	458	goto no_node;
	459	}
	460
	461	etsects->irq = platform_get_irq(dev, 0);
	462
0f2c0d32	463	if (etsects->irq < 0) {
c78275f3 RC	464	pr_err("irq not in device tree\n");
	465	goto no_node;
	466	}
	467	if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
	468	pr_err("request_irq failed\n");
	469	goto no_node;
	470	}
	471
	472	etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
	473	if (!etsects->rsrc) {
	474	pr_err("no resource\n");
	475	goto no_resource;
	476	}
2b9c128e	477	if (request_resource(&iomem_resource, etsects->rsrc)) {
c78275f3 RC	478	pr_err("resource busy\n");
	479	goto no_resource;
	480	}
	481
	482	spin_lock_init(&etsects->lock);
	483
	484	etsects->regs = ioremap(etsects->rsrc->start,
28f65c11	485	resource_size(etsects->rsrc));
c78275f3 RC	486	if (!etsects->regs) {
	487	pr_err("ioremap ptp registers failed\n");
	488	goto no_ioremap;
	489	}
d28fdf0f	490	getnstimeofday64(&now);
c78275f3 RC	491	ptp_gianfar_settime(&etsects->caps, &now);
	492
	493	tmr_ctrl =
	494	(etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT \|
	495	(etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
	496
	497	spin_lock_irqsave(&etsects->lock, flags);
	498
	499	gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
	500	gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
	501	gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
	502	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
	503	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
	504	set_alarm(etsects);
cbc05660	505	gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl\|FS\|RTPE\|TE\|FRD);
c78275f3 RC	506
	507	spin_unlock_irqrestore(&etsects->lock, flags);
	508
1ef76158	509	etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
c78275f3 RC	510	if (IS_ERR(etsects->clock)) {
	511	err = PTR_ERR(etsects->clock);
	512	goto no_clock;
	513	}
28889b7e	514	gfar_phc_index = ptp_clock_index(etsects->clock);
c78275f3	515
8513fbd8	516	platform_set_drvdata(dev, etsects);
c78275f3 RC	517
	518	return 0;
	519
	520	no_clock:
e5f5e380	521	iounmap(etsects->regs);
c78275f3 RC	522	no_ioremap:
	523	release_resource(etsects->rsrc);
	524	no_resource:
	525	free_irq(etsects->irq, etsects);
	526	no_node:
	527	kfree(etsects);
	528	no_memory:
	529	return err;
	530	}
	531
	532	static int gianfar_ptp_remove(struct platform_device *dev)
	533	{
8513fbd8	534	struct etsects *etsects = platform_get_drvdata(dev);
c78275f3 RC	535
	536	gfar_write(&etsects->regs->tmr_temask, 0);
	537	gfar_write(&etsects->regs->tmr_ctrl, 0);
	538
28889b7e	539	gfar_phc_index = -1;
c78275f3 RC	540	ptp_clock_unregister(etsects->clock);
	541	iounmap(etsects->regs);
	542	release_resource(etsects->rsrc);
	543	free_irq(etsects->irq, etsects);
	544	kfree(etsects);
	545
	546	return 0;
	547	}
	548
94e5a2a8	549	static const struct of_device_id match_table[] = {
c78275f3 RC	550	{ .compatible = "fsl,etsec-ptp" },
	551	{},
	552	};
23860063	553	MODULE_DEVICE_TABLE(of, match_table);
c78275f3 RC	554
	555	static struct platform_driver gianfar_ptp_driver = {
	556	.driver = {
	557	.name = "gianfar_ptp",
	558	.of_match_table = match_table,
c78275f3 RC	559	},
	560	.probe = gianfar_ptp_probe,
	561	.remove = gianfar_ptp_remove,
	562	};
	563
db62f684	564	module_platform_driver(gianfar_ptp_driver);
c78275f3	565
c2ec3ff6	566	MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
c78275f3 RC	567	MODULE_DESCRIPTION("PTP clock using the eTSEC");
c78275f3 RC	568	MODULE_LICENSE("GPL");