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9f35a734 TT |
1 | /* |
2 | * QorIQ 10G MDIO Controller | |
3 | * | |
4 | * Copyright 2012 Freescale Semiconductor, Inc. | |
5 | * | |
6 | * Authors: Andy Fleming <afleming@freescale.com> | |
7 | * Timur Tabi <timur@freescale.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public License | |
10 | * version 2. This program is licensed "as is" without any warranty of any | |
11 | * kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/phy.h> | |
19 | #include <linux/mdio.h> | |
5af50730 | 20 | #include <linux/of_address.h> |
9f35a734 TT |
21 | #include <linux/of_platform.h> |
22 | #include <linux/of_mdio.h> | |
23 | ||
24 | /* Number of microseconds to wait for a register to respond */ | |
25 | #define TIMEOUT 1000 | |
26 | ||
27 | struct tgec_mdio_controller { | |
28 | __be32 reserved[12]; | |
29 | __be32 mdio_stat; /* MDIO configuration and status */ | |
30 | __be32 mdio_ctl; /* MDIO control */ | |
31 | __be32 mdio_data; /* MDIO data */ | |
32 | __be32 mdio_addr; /* MDIO address */ | |
33 | } __packed; | |
34 | ||
35 | #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8) | |
36 | #define MDIO_STAT_BSY (1 << 0) | |
37 | #define MDIO_STAT_RD_ER (1 << 1) | |
38 | #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f) | |
39 | #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5) | |
40 | #define MDIO_CTL_PRE_DIS (1 << 10) | |
41 | #define MDIO_CTL_SCAN_EN (1 << 11) | |
42 | #define MDIO_CTL_POST_INC (1 << 14) | |
43 | #define MDIO_CTL_READ (1 << 15) | |
44 | ||
45 | #define MDIO_DATA(x) (x & 0xffff) | |
46 | #define MDIO_DATA_BSY (1 << 31) | |
47 | ||
48 | /* | |
c1543d37 | 49 | * Wait until the MDIO bus is free |
9f35a734 TT |
50 | */ |
51 | static int xgmac_wait_until_free(struct device *dev, | |
52 | struct tgec_mdio_controller __iomem *regs) | |
53 | { | |
54 | uint32_t status; | |
55 | ||
56 | /* Wait till the bus is free */ | |
57 | status = spin_event_timeout( | |
58 | !((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0); | |
59 | if (!status) { | |
60 | dev_err(dev, "timeout waiting for bus to be free\n"); | |
61 | return -ETIMEDOUT; | |
62 | } | |
63 | ||
64 | return 0; | |
65 | } | |
66 | ||
67 | /* | |
68 | * Wait till the MDIO read or write operation is complete | |
69 | */ | |
70 | static int xgmac_wait_until_done(struct device *dev, | |
71 | struct tgec_mdio_controller __iomem *regs) | |
72 | { | |
73 | uint32_t status; | |
74 | ||
75 | /* Wait till the MDIO write is complete */ | |
76 | status = spin_event_timeout( | |
77 | !((in_be32(®s->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0); | |
78 | if (!status) { | |
79 | dev_err(dev, "timeout waiting for operation to complete\n"); | |
80 | return -ETIMEDOUT; | |
81 | } | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
86 | /* | |
87 | * Write value to the PHY for this device to the register at regnum,waiting | |
88 | * until the write is done before it returns. All PHY configuration has to be | |
89 | * done through the TSEC1 MIIM regs. | |
90 | */ | |
91 | static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value) | |
92 | { | |
93 | struct tgec_mdio_controller __iomem *regs = bus->priv; | |
94 | uint16_t dev_addr = regnum >> 16; | |
95 | int ret; | |
96 | ||
9f35a734 TT |
97 | /* Set the port and dev addr */ |
98 | out_be32(®s->mdio_ctl, | |
99 | MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr)); | |
100 | ||
101 | /* Set the register address */ | |
102 | out_be32(®s->mdio_addr, regnum & 0xffff); | |
103 | ||
104 | ret = xgmac_wait_until_free(&bus->dev, regs); | |
105 | if (ret) | |
106 | return ret; | |
107 | ||
108 | /* Write the value to the register */ | |
109 | out_be32(®s->mdio_data, MDIO_DATA(value)); | |
110 | ||
111 | ret = xgmac_wait_until_done(&bus->dev, regs); | |
112 | if (ret) | |
113 | return ret; | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | /* | |
119 | * Reads from register regnum in the PHY for device dev, returning the value. | |
120 | * Clears miimcom first. All PHY configuration has to be done through the | |
121 | * TSEC1 MIIM regs. | |
122 | */ | |
123 | static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum) | |
124 | { | |
125 | struct tgec_mdio_controller __iomem *regs = bus->priv; | |
126 | uint16_t dev_addr = regnum >> 16; | |
127 | uint32_t mdio_ctl; | |
128 | uint16_t value; | |
129 | int ret; | |
130 | ||
9f35a734 TT |
131 | /* Set the Port and Device Addrs */ |
132 | mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr); | |
133 | out_be32(®s->mdio_ctl, mdio_ctl); | |
134 | ||
135 | /* Set the register address */ | |
136 | out_be32(®s->mdio_addr, regnum & 0xffff); | |
137 | ||
138 | ret = xgmac_wait_until_free(&bus->dev, regs); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
142 | /* Initiate the read */ | |
143 | out_be32(®s->mdio_ctl, mdio_ctl | MDIO_CTL_READ); | |
144 | ||
145 | ret = xgmac_wait_until_done(&bus->dev, regs); | |
146 | if (ret) | |
147 | return ret; | |
148 | ||
149 | /* Return all Fs if nothing was there */ | |
150 | if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER) { | |
55fd3641 | 151 | dev_err(&bus->dev, |
9e6492ec | 152 | "Error while reading PHY%d reg at %d.%hhu\n", |
55fd3641 | 153 | phy_id, dev_addr, regnum); |
9f35a734 TT |
154 | return 0xffff; |
155 | } | |
156 | ||
157 | value = in_be32(®s->mdio_data) & 0xffff; | |
158 | dev_dbg(&bus->dev, "read %04x\n", value); | |
159 | ||
160 | return value; | |
161 | } | |
162 | ||
33897cc8 | 163 | static int xgmac_mdio_probe(struct platform_device *pdev) |
9f35a734 TT |
164 | { |
165 | struct device_node *np = pdev->dev.of_node; | |
166 | struct mii_bus *bus; | |
167 | struct resource res; | |
168 | int ret; | |
169 | ||
170 | ret = of_address_to_resource(np, 0, &res); | |
171 | if (ret) { | |
172 | dev_err(&pdev->dev, "could not obtain address\n"); | |
173 | return ret; | |
174 | } | |
175 | ||
aa842478 | 176 | bus = mdiobus_alloc(); |
9f35a734 TT |
177 | if (!bus) |
178 | return -ENOMEM; | |
179 | ||
180 | bus->name = "Freescale XGMAC MDIO Bus"; | |
181 | bus->read = xgmac_mdio_read; | |
182 | bus->write = xgmac_mdio_write; | |
9f35a734 TT |
183 | bus->parent = &pdev->dev; |
184 | snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start); | |
185 | ||
186 | /* Set the PHY base address */ | |
187 | bus->priv = of_iomap(np, 0); | |
188 | if (!bus->priv) { | |
189 | ret = -ENOMEM; | |
190 | goto err_ioremap; | |
191 | } | |
192 | ||
193 | ret = of_mdiobus_register(bus, np); | |
194 | if (ret) { | |
195 | dev_err(&pdev->dev, "cannot register MDIO bus\n"); | |
196 | goto err_registration; | |
197 | } | |
198 | ||
8513fbd8 | 199 | platform_set_drvdata(pdev, bus); |
9f35a734 TT |
200 | |
201 | return 0; | |
202 | ||
203 | err_registration: | |
204 | iounmap(bus->priv); | |
205 | ||
206 | err_ioremap: | |
207 | mdiobus_free(bus); | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
33897cc8 | 212 | static int xgmac_mdio_remove(struct platform_device *pdev) |
9f35a734 | 213 | { |
8513fbd8 | 214 | struct mii_bus *bus = platform_get_drvdata(pdev); |
9f35a734 TT |
215 | |
216 | mdiobus_unregister(bus); | |
217 | iounmap(bus->priv); | |
218 | mdiobus_free(bus); | |
219 | ||
220 | return 0; | |
221 | } | |
222 | ||
223 | static struct of_device_id xgmac_mdio_match[] = { | |
224 | { | |
225 | .compatible = "fsl,fman-xmdio", | |
226 | }, | |
227 | {}, | |
228 | }; | |
229 | MODULE_DEVICE_TABLE(of, xgmac_mdio_match); | |
230 | ||
231 | static struct platform_driver xgmac_mdio_driver = { | |
232 | .driver = { | |
233 | .name = "fsl-fman_xmdio", | |
234 | .of_match_table = xgmac_mdio_match, | |
235 | }, | |
236 | .probe = xgmac_mdio_probe, | |
237 | .remove = xgmac_mdio_remove, | |
238 | }; | |
239 | ||
240 | module_platform_driver(xgmac_mdio_driver); | |
241 | ||
242 | MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller"); | |
243 | MODULE_LICENSE("GPL v2"); |