[deliverable/linux.git] / drivers / net / ethernet / freescale / xgmac_mdio.c

/*
 * QorIQ 10G MDIO Controller
 *
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * Authors: Andy Fleming <afleming@freescale.com>
 *          Timur Tabi <timur@freescale.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/mdio.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/of_mdio.h>

/* Number of microseconds to wait for a register to respond */
#define TIMEOUT	1000

struct tgec_mdio_controller {
	__be32	reserved[12];
	__be32	mdio_stat;	/* MDIO configuration and status */
	__be32	mdio_ctl;	/* MDIO control */
	__be32	mdio_data;	/* MDIO data */
	__be32	mdio_addr;	/* MDIO address */
} __packed;

#define MDIO_STAT_ENC		BIT(6)
#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
#define MDIO_STAT_BSY		BIT(0)
#define MDIO_STAT_RD_ER		BIT(1)
#define MDIO_CTL_DEV_ADDR(x) 	(x & 0x1f)
#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
#define MDIO_CTL_PRE_DIS	BIT(10)
#define MDIO_CTL_SCAN_EN	BIT(11)
#define MDIO_CTL_POST_INC	BIT(14)
#define MDIO_CTL_READ		BIT(15)

#define MDIO_DATA(x)		(x & 0xffff)
#define MDIO_DATA_BSY		BIT(31)

/*
 * Wait until the MDIO bus is free
 */
static int xgmac_wait_until_free(struct device *dev,
				 struct tgec_mdio_controller __iomem *regs)
{
	uint32_t status;

	/* Wait till the bus is free */
	status = spin_event_timeout(
		!((ioread32be(&regs->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0);
	if (!status) {
		dev_err(dev, "timeout waiting for bus to be free\n");
		return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Wait till the MDIO read or write operation is complete
 */
static int xgmac_wait_until_done(struct device *dev,
				 struct tgec_mdio_controller __iomem *regs)
{
	uint32_t status;

	/* Wait till the MDIO write is complete */
	status = spin_event_timeout(
		!((ioread32be(&regs->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0);
	if (!status) {
		dev_err(dev, "timeout waiting for operation to complete\n");
		return -ETIMEDOUT;
	}

	return 0;
}

/*
 * Write value to the PHY for this device to the register at regnum,waiting
 * until the write is done before it returns.  All PHY configuration has to be
 * done through the TSEC1 MIIM regs.
 */
static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
{
	struct tgec_mdio_controller __iomem *regs = bus->priv;
	uint16_t dev_addr;
	u32 mdio_ctl, mdio_stat;
	int ret;

	mdio_stat = ioread32be(&regs->mdio_stat);
	if (regnum & MII_ADDR_C45) {
		/* Clause 45 (ie 10G) */
		dev_addr = (regnum >> 16) & 0x1f;
		mdio_stat |= MDIO_STAT_ENC;
	} else {
		/* Clause 22 (ie 1G) */
		dev_addr = regnum & 0x1f;
		mdio_stat &= ~MDIO_STAT_ENC;
	}

	iowrite32be(mdio_stat, &regs->mdio_stat);

	ret = xgmac_wait_until_free(&bus->dev, regs);
	if (ret)
		return ret;

	/* Set the port and dev addr */
	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
	iowrite32be(mdio_ctl, &regs->mdio_ctl);

	/* Set the register address */
	if (regnum & MII_ADDR_C45) {
		iowrite32be(regnum & 0xffff, &regs->mdio_addr);

		ret = xgmac_wait_until_free(&bus->dev, regs);
		if (ret)
			return ret;
	}

	/* Write the value to the register */
	iowrite32be(MDIO_DATA(value), &regs->mdio_data);

	ret = xgmac_wait_until_done(&bus->dev, regs);
	if (ret)
		return ret;

	return 0;
}

/*
 * Reads from register regnum in the PHY for device dev, returning the value.
 * Clears miimcom first.  All PHY configuration has to be done through the
 * TSEC1 MIIM regs.
 */
static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
	struct tgec_mdio_controller __iomem *regs = bus->priv;
	uint16_t dev_addr;
	uint32_t mdio_stat;
	uint32_t mdio_ctl;
	uint16_t value;
	int ret;

	mdio_stat = ioread32be(&regs->mdio_stat);
	if (regnum & MII_ADDR_C45) {
		dev_addr = (regnum >> 16) & 0x1f;
		mdio_stat |= MDIO_STAT_ENC;
	} else {
		dev_addr = regnum & 0x1f;
		mdio_stat &= ~MDIO_STAT_ENC;
	}

	iowrite32be(mdio_stat, &regs->mdio_stat);

	ret = xgmac_wait_until_free(&bus->dev, regs);
	if (ret)
		return ret;

	/* Set the Port and Device Addrs */
	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
	iowrite32be(mdio_ctl, &regs->mdio_ctl);

	/* Set the register address */
	if (regnum & MII_ADDR_C45) {
		iowrite32be(regnum & 0xffff, &regs->mdio_addr);

		ret = xgmac_wait_until_free(&bus->dev, regs);
		if (ret)
			return ret;
	}

	/* Initiate the read */
	iowrite32be(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl);

	ret = xgmac_wait_until_done(&bus->dev, regs);
	if (ret)
		return ret;

	/* Return all Fs if nothing was there */
	if (ioread32be(&regs->mdio_stat) & MDIO_STAT_RD_ER) {
		dev_err(&bus->dev,
			"Error while reading PHY%d reg at %d.%hhu\n",
			phy_id, dev_addr, regnum);
		return 0xffff;
	}

	value = ioread32be(&regs->mdio_data) & 0xffff;
	dev_dbg(&bus->dev, "read %04x\n", value);

	return value;
}

static int xgmac_mdio_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct mii_bus *bus;
	struct resource res;
	int ret;

	ret = of_address_to_resource(np, 0, &res);
	if (ret) {
		dev_err(&pdev->dev, "could not obtain address\n");
		return ret;
	}

	bus = mdiobus_alloc();
	if (!bus)
		return -ENOMEM;

	bus->name = "Freescale XGMAC MDIO Bus";
	bus->read = xgmac_mdio_read;
	bus->write = xgmac_mdio_write;
	bus->parent = &pdev->dev;
	snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);

	/* Set the PHY base address */
	bus->priv = of_iomap(np, 0);
	if (!bus->priv) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	ret = of_mdiobus_register(bus, np);
	if (ret) {
		dev_err(&pdev->dev, "cannot register MDIO bus\n");
		goto err_registration;
	}

	platform_set_drvdata(pdev, bus);

	return 0;

err_registration:
	iounmap(bus->priv);

err_ioremap:
	mdiobus_free(bus);

	return ret;
}

static int xgmac_mdio_remove(struct platform_device *pdev)
{
	struct mii_bus *bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus);
	iounmap(bus->priv);
	mdiobus_free(bus);

	return 0;
}

static struct of_device_id xgmac_mdio_match[] = {
	{
		.compatible = "fsl,fman-xmdio",
	},
	{
		.compatible = "fsl,fman-memac-mdio",
	},
	{},
};
MODULE_DEVICE_TABLE(of, xgmac_mdio_match);

static struct platform_driver xgmac_mdio_driver = {
	.driver = {
		.name = "fsl-fman_xmdio",
		.of_match_table = xgmac_mdio_match,
	},
	.probe = xgmac_mdio_probe,
	.remove = xgmac_mdio_remove,
};

module_platform_driver(xgmac_mdio_driver);

MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9f35a734 TT	1	/*
	2	* QorIQ 10G MDIO Controller
	3	*
	4	* Copyright 2012 Freescale Semiconductor, Inc.
	5	*
	6	* Authors: Andy Fleming <afleming@freescale.com>
	7	* Timur Tabi <timur@freescale.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public License
	10	* version 2. This program is licensed "as is" without any warranty of any
	11	* kind, whether express or implied.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/slab.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/module.h>
	18	#include <linux/phy.h>
	19	#include <linux/mdio.h>
5af50730	20	#include <linux/of_address.h>
9f35a734 TT	21	#include <linux/of_platform.h>
	22	#include <linux/of_mdio.h>
	23
	24	/* Number of microseconds to wait for a register to respond */
	25	#define TIMEOUT 1000
	26
	27	struct tgec_mdio_controller {
	28	__be32 reserved[12];
	29	__be32 mdio_stat; /* MDIO configuration and status */
	30	__be32 mdio_ctl; /* MDIO control */
	31	__be32 mdio_data; /* MDIO data */
	32	__be32 mdio_addr; /* MDIO address */
	33	} __packed;
	34
1fcf77c8	35	#define MDIO_STAT_ENC BIT(6)
9f35a734	36	#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
49ff2d3f SX	37	#define MDIO_STAT_BSY BIT(0)
49ff2d3f SX	38	#define MDIO_STAT_RD_ER BIT(1)
9f35a734 TT	39	#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
9f35a734 TT	40	#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
49ff2d3f SX	41	#define MDIO_CTL_PRE_DIS BIT(10)
	42	#define MDIO_CTL_SCAN_EN BIT(11)
	43	#define MDIO_CTL_POST_INC BIT(14)
	44	#define MDIO_CTL_READ BIT(15)
9f35a734 TT	45
9f35a734 TT	46	#define MDIO_DATA(x) (x & 0xffff)
49ff2d3f	47	#define MDIO_DATA_BSY BIT(31)
9f35a734 TT	48
9f35a734 TT	49	/*
c1543d37	50	* Wait until the MDIO bus is free
9f35a734 TT	51	*/
	52	static int xgmac_wait_until_free(struct device *dev,
	53	struct tgec_mdio_controller __iomem *regs)
	54	{
	55	uint32_t status;
	56
	57	/* Wait till the bus is free */
	58	status = spin_event_timeout(
ca43e58c	59	!((ioread32be(&regs->mdio_stat)) & MDIO_STAT_BSY), TIMEOUT, 0);
9f35a734 TT	60	if (!status) {
	61	dev_err(dev, "timeout waiting for bus to be free\n");
	62	return -ETIMEDOUT;
	63	}
	64
	65	return 0;
	66	}
	67
	68	/*
	69	* Wait till the MDIO read or write operation is complete
	70	*/
	71	static int xgmac_wait_until_done(struct device *dev,
	72	struct tgec_mdio_controller __iomem *regs)
	73	{
	74	uint32_t status;
	75
	76	/* Wait till the MDIO write is complete */
	77	status = spin_event_timeout(
ca43e58c	78	!((ioread32be(&regs->mdio_data)) & MDIO_DATA_BSY), TIMEOUT, 0);
9f35a734 TT	79	if (!status) {
	80	dev_err(dev, "timeout waiting for operation to complete\n");
	81	return -ETIMEDOUT;
	82	}
	83
	84	return 0;
	85	}
	86
	87	/*
	88	* Write value to the PHY for this device to the register at regnum,waiting
	89	* until the write is done before it returns. All PHY configuration has to be
	90	* done through the TSEC1 MIIM regs.
	91	*/
	92	static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
	93	{
	94	struct tgec_mdio_controller __iomem *regs = bus->priv;
1fcf77c8 AF	95	uint16_t dev_addr;
1fcf77c8 AF	96	u32 mdio_ctl, mdio_stat;
9f35a734 TT	97	int ret;
9f35a734 TT	98
ca43e58c	99	mdio_stat = ioread32be(&regs->mdio_stat);
1fcf77c8 AF	100	if (regnum & MII_ADDR_C45) {
	101	/* Clause 45 (ie 10G) */
	102	dev_addr = (regnum >> 16) & 0x1f;
	103	mdio_stat \|= MDIO_STAT_ENC;
	104	} else {
	105	/* Clause 22 (ie 1G) */
	106	dev_addr = regnum & 0x1f;
	107	mdio_stat &= ~MDIO_STAT_ENC;
	108	}
9f35a734	109
ca43e58c	110	iowrite32be(mdio_stat, &regs->mdio_stat);
9f35a734 TT	111
	112	ret = xgmac_wait_until_free(&bus->dev, regs);
	113	if (ret)
	114	return ret;
	115
1fcf77c8 AF	116	/* Set the port and dev addr */
1fcf77c8 AF	117	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) \| MDIO_CTL_DEV_ADDR(dev_addr);
ca43e58c	118	iowrite32be(mdio_ctl, &regs->mdio_ctl);
1fcf77c8 AF	119
	120	/* Set the register address */
	121	if (regnum & MII_ADDR_C45) {
ca43e58c	122	iowrite32be(regnum & 0xffff, &regs->mdio_addr);
1fcf77c8 AF	123
	124	ret = xgmac_wait_until_free(&bus->dev, regs);
	125	if (ret)
	126	return ret;
	127	}
	128
9f35a734	129	/* Write the value to the register */
ca43e58c	130	iowrite32be(MDIO_DATA(value), &regs->mdio_data);
9f35a734 TT	131
	132	ret = xgmac_wait_until_done(&bus->dev, regs);
	133	if (ret)
	134	return ret;
	135
	136	return 0;
	137	}
	138
	139	/*
	140	* Reads from register regnum in the PHY for device dev, returning the value.
	141	* Clears miimcom first. All PHY configuration has to be done through the
	142	* TSEC1 MIIM regs.
	143	*/
	144	static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
	145	{
	146	struct tgec_mdio_controller __iomem *regs = bus->priv;
1fcf77c8 AF	147	uint16_t dev_addr;
1fcf77c8 AF	148	uint32_t mdio_stat;
9f35a734 TT	149	uint32_t mdio_ctl;
	150	uint16_t value;
	151	int ret;
	152
ca43e58c	153	mdio_stat = ioread32be(&regs->mdio_stat);
1fcf77c8 AF	154	if (regnum & MII_ADDR_C45) {
	155	dev_addr = (regnum >> 16) & 0x1f;
	156	mdio_stat \|= MDIO_STAT_ENC;
	157	} else {
	158	dev_addr = regnum & 0x1f;
e54bfe9d	159	mdio_stat &= ~MDIO_STAT_ENC;
1fcf77c8 AF	160	}
1fcf77c8 AF	161
ca43e58c	162	iowrite32be(mdio_stat, &regs->mdio_stat);
1fcf77c8 AF	163
	164	ret = xgmac_wait_until_free(&bus->dev, regs);
	165	if (ret)
	166	return ret;
	167
9f35a734 TT	168	/* Set the Port and Device Addrs */
9f35a734 TT	169	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) \| MDIO_CTL_DEV_ADDR(dev_addr);
ca43e58c	170	iowrite32be(mdio_ctl, &regs->mdio_ctl);
9f35a734 TT	171
9f35a734 TT	172	/* Set the register address */
1fcf77c8	173	if (regnum & MII_ADDR_C45) {
ca43e58c	174	iowrite32be(regnum & 0xffff, &regs->mdio_addr);
9f35a734	175
1fcf77c8 AF	176	ret = xgmac_wait_until_free(&bus->dev, regs);
	177	if (ret)
	178	return ret;
	179	}
9f35a734 TT	180
9f35a734 TT	181	/* Initiate the read */
ca43e58c	182	iowrite32be(mdio_ctl \| MDIO_CTL_READ, &regs->mdio_ctl);
9f35a734 TT	183
	184	ret = xgmac_wait_until_done(&bus->dev, regs);
	185	if (ret)
	186	return ret;
	187
	188	/* Return all Fs if nothing was there */
ca43e58c	189	if (ioread32be(&regs->mdio_stat) & MDIO_STAT_RD_ER) {
55fd3641	190	dev_err(&bus->dev,
9e6492ec	191	"Error while reading PHY%d reg at %d.%hhu\n",
55fd3641	192	phy_id, dev_addr, regnum);
9f35a734 TT	193	return 0xffff;
	194	}
	195
ca43e58c	196	value = ioread32be(&regs->mdio_data) & 0xffff;
9f35a734 TT	197	dev_dbg(&bus->dev, "read %04x\n", value);
	198
	199	return value;
	200	}
	201
33897cc8	202	static int xgmac_mdio_probe(struct platform_device *pdev)
9f35a734 TT	203	{
	204	struct device_node *np = pdev->dev.of_node;
	205	struct mii_bus *bus;
	206	struct resource res;
	207	int ret;
	208
	209	ret = of_address_to_resource(np, 0, &res);
	210	if (ret) {
	211	dev_err(&pdev->dev, "could not obtain address\n");
	212	return ret;
	213	}
	214
aa842478	215	bus = mdiobus_alloc();
9f35a734 TT	216	if (!bus)
	217	return -ENOMEM;
	218
	219	bus->name = "Freescale XGMAC MDIO Bus";
	220	bus->read = xgmac_mdio_read;
	221	bus->write = xgmac_mdio_write;
9f35a734 TT	222	bus->parent = &pdev->dev;
	223	snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
	224
	225	/* Set the PHY base address */
	226	bus->priv = of_iomap(np, 0);
	227	if (!bus->priv) {
	228	ret = -ENOMEM;
	229	goto err_ioremap;
	230	}
	231
	232	ret = of_mdiobus_register(bus, np);
	233	if (ret) {
	234	dev_err(&pdev->dev, "cannot register MDIO bus\n");
	235	goto err_registration;
	236	}
	237
8513fbd8	238	platform_set_drvdata(pdev, bus);
9f35a734 TT	239
	240	return 0;
	241
	242	err_registration:
	243	iounmap(bus->priv);
	244
	245	err_ioremap:
	246	mdiobus_free(bus);
	247
	248	return ret;
	249	}
	250
33897cc8	251	static int xgmac_mdio_remove(struct platform_device *pdev)
9f35a734	252	{
8513fbd8	253	struct mii_bus *bus = platform_get_drvdata(pdev);
9f35a734 TT	254
	255	mdiobus_unregister(bus);
	256	iounmap(bus->priv);
	257	mdiobus_free(bus);
	258
	259	return 0;
	260	}
	261
	262	static struct of_device_id xgmac_mdio_match[] = {
	263	{
	264	.compatible = "fsl,fman-xmdio",
	265	},
1fcf77c8 AF	266	{
	267	.compatible = "fsl,fman-memac-mdio",
	268	},
9f35a734 TT	269	{},
	270	};
	271	MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
	272
	273	static struct platform_driver xgmac_mdio_driver = {
	274	.driver = {
	275	.name = "fsl-fman_xmdio",
	276	.of_match_table = xgmac_mdio_match,
	277	},
	278	.probe = xgmac_mdio_probe,
	279	.remove = xgmac_mdio_remove,
	280	};
	281
	282	module_platform_driver(xgmac_mdio_driver);
	283
	284	MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
	285	MODULE_LICENSE("GPL v2");