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1 | /* Copyright (c) 2014 Linaro Ltd. |
2 | * Copyright (c) 2014 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/of_net.h> | |
15 | #include <linux/of_mdio.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/circ_buf.h> | |
18 | ||
19 | #define STATION_ADDR_LOW 0x0000 | |
20 | #define STATION_ADDR_HIGH 0x0004 | |
21 | #define MAC_DUPLEX_HALF_CTRL 0x0008 | |
22 | #define MAX_FRM_SIZE 0x003c | |
23 | #define PORT_MODE 0x0040 | |
24 | #define PORT_EN 0x0044 | |
25 | #define BITS_TX_EN BIT(2) | |
26 | #define BITS_RX_EN BIT(1) | |
27 | #define REC_FILT_CONTROL 0x0064 | |
28 | #define BIT_CRC_ERR_PASS BIT(5) | |
29 | #define BIT_PAUSE_FRM_PASS BIT(4) | |
30 | #define BIT_VLAN_DROP_EN BIT(3) | |
31 | #define BIT_BC_DROP_EN BIT(2) | |
32 | #define BIT_MC_MATCH_EN BIT(1) | |
33 | #define BIT_UC_MATCH_EN BIT(0) | |
34 | #define PORT_MC_ADDR_LOW 0x0068 | |
35 | #define PORT_MC_ADDR_HIGH 0x006C | |
36 | #define CF_CRC_STRIP 0x01b0 | |
37 | #define MODE_CHANGE_EN 0x01b4 | |
38 | #define BIT_MODE_CHANGE_EN BIT(0) | |
39 | #define COL_SLOT_TIME 0x01c0 | |
40 | #define RECV_CONTROL 0x01e0 | |
41 | #define BIT_STRIP_PAD_EN BIT(3) | |
42 | #define BIT_RUNT_PKT_EN BIT(4) | |
43 | #define CONTROL_WORD 0x0214 | |
44 | #define MDIO_SINGLE_CMD 0x03c0 | |
45 | #define MDIO_SINGLE_DATA 0x03c4 | |
46 | #define MDIO_CTRL 0x03cc | |
47 | #define MDIO_RDATA_STATUS 0x03d0 | |
48 | ||
49 | #define MDIO_START BIT(20) | |
50 | #define MDIO_R_VALID BIT(0) | |
51 | #define MDIO_READ (BIT(17) | MDIO_START) | |
52 | #define MDIO_WRITE (BIT(16) | MDIO_START) | |
53 | ||
54 | #define RX_FQ_START_ADDR 0x0500 | |
55 | #define RX_FQ_DEPTH 0x0504 | |
56 | #define RX_FQ_WR_ADDR 0x0508 | |
57 | #define RX_FQ_RD_ADDR 0x050c | |
58 | #define RX_FQ_VLDDESC_CNT 0x0510 | |
59 | #define RX_FQ_ALEMPTY_TH 0x0514 | |
60 | #define RX_FQ_REG_EN 0x0518 | |
61 | #define BITS_RX_FQ_START_ADDR_EN BIT(2) | |
62 | #define BITS_RX_FQ_DEPTH_EN BIT(1) | |
63 | #define BITS_RX_FQ_RD_ADDR_EN BIT(0) | |
64 | #define RX_FQ_ALFULL_TH 0x051c | |
65 | #define RX_BQ_START_ADDR 0x0520 | |
66 | #define RX_BQ_DEPTH 0x0524 | |
67 | #define RX_BQ_WR_ADDR 0x0528 | |
68 | #define RX_BQ_RD_ADDR 0x052c | |
69 | #define RX_BQ_FREE_DESC_CNT 0x0530 | |
70 | #define RX_BQ_ALEMPTY_TH 0x0534 | |
71 | #define RX_BQ_REG_EN 0x0538 | |
72 | #define BITS_RX_BQ_START_ADDR_EN BIT(2) | |
73 | #define BITS_RX_BQ_DEPTH_EN BIT(1) | |
74 | #define BITS_RX_BQ_WR_ADDR_EN BIT(0) | |
75 | #define RX_BQ_ALFULL_TH 0x053c | |
76 | #define TX_BQ_START_ADDR 0x0580 | |
77 | #define TX_BQ_DEPTH 0x0584 | |
78 | #define TX_BQ_WR_ADDR 0x0588 | |
79 | #define TX_BQ_RD_ADDR 0x058c | |
80 | #define TX_BQ_VLDDESC_CNT 0x0590 | |
81 | #define TX_BQ_ALEMPTY_TH 0x0594 | |
82 | #define TX_BQ_REG_EN 0x0598 | |
83 | #define BITS_TX_BQ_START_ADDR_EN BIT(2) | |
84 | #define BITS_TX_BQ_DEPTH_EN BIT(1) | |
85 | #define BITS_TX_BQ_RD_ADDR_EN BIT(0) | |
86 | #define TX_BQ_ALFULL_TH 0x059c | |
87 | #define TX_RQ_START_ADDR 0x05a0 | |
88 | #define TX_RQ_DEPTH 0x05a4 | |
89 | #define TX_RQ_WR_ADDR 0x05a8 | |
90 | #define TX_RQ_RD_ADDR 0x05ac | |
91 | #define TX_RQ_FREE_DESC_CNT 0x05b0 | |
92 | #define TX_RQ_ALEMPTY_TH 0x05b4 | |
93 | #define TX_RQ_REG_EN 0x05b8 | |
94 | #define BITS_TX_RQ_START_ADDR_EN BIT(2) | |
95 | #define BITS_TX_RQ_DEPTH_EN BIT(1) | |
96 | #define BITS_TX_RQ_WR_ADDR_EN BIT(0) | |
97 | #define TX_RQ_ALFULL_TH 0x05bc | |
98 | #define RAW_PMU_INT 0x05c0 | |
99 | #define ENA_PMU_INT 0x05c4 | |
100 | #define STATUS_PMU_INT 0x05c8 | |
101 | #define MAC_FIFO_ERR_IN BIT(30) | |
102 | #define TX_RQ_IN_TIMEOUT_INT BIT(29) | |
103 | #define RX_BQ_IN_TIMEOUT_INT BIT(28) | |
104 | #define TXOUTCFF_FULL_INT BIT(27) | |
105 | #define TXOUTCFF_EMPTY_INT BIT(26) | |
106 | #define TXCFF_FULL_INT BIT(25) | |
107 | #define TXCFF_EMPTY_INT BIT(24) | |
108 | #define RXOUTCFF_FULL_INT BIT(23) | |
109 | #define RXOUTCFF_EMPTY_INT BIT(22) | |
110 | #define RXCFF_FULL_INT BIT(21) | |
111 | #define RXCFF_EMPTY_INT BIT(20) | |
112 | #define TX_RQ_IN_INT BIT(19) | |
113 | #define TX_BQ_OUT_INT BIT(18) | |
114 | #define RX_BQ_IN_INT BIT(17) | |
115 | #define RX_FQ_OUT_INT BIT(16) | |
116 | #define TX_RQ_EMPTY_INT BIT(15) | |
117 | #define TX_RQ_FULL_INT BIT(14) | |
118 | #define TX_RQ_ALEMPTY_INT BIT(13) | |
119 | #define TX_RQ_ALFULL_INT BIT(12) | |
120 | #define TX_BQ_EMPTY_INT BIT(11) | |
121 | #define TX_BQ_FULL_INT BIT(10) | |
122 | #define TX_BQ_ALEMPTY_INT BIT(9) | |
123 | #define TX_BQ_ALFULL_INT BIT(8) | |
124 | #define RX_BQ_EMPTY_INT BIT(7) | |
125 | #define RX_BQ_FULL_INT BIT(6) | |
126 | #define RX_BQ_ALEMPTY_INT BIT(5) | |
127 | #define RX_BQ_ALFULL_INT BIT(4) | |
128 | #define RX_FQ_EMPTY_INT BIT(3) | |
129 | #define RX_FQ_FULL_INT BIT(2) | |
130 | #define RX_FQ_ALEMPTY_INT BIT(1) | |
131 | #define RX_FQ_ALFULL_INT BIT(0) | |
132 | ||
133 | #define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \ | |
134 | TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT) | |
135 | ||
136 | #define DESC_WR_RD_ENA 0x05cc | |
137 | #define IN_QUEUE_TH 0x05d8 | |
138 | #define OUT_QUEUE_TH 0x05dc | |
139 | #define QUEUE_TX_BQ_SHIFT 16 | |
140 | #define RX_BQ_IN_TIMEOUT_TH 0x05e0 | |
141 | #define TX_RQ_IN_TIMEOUT_TH 0x05e4 | |
142 | #define STOP_CMD 0x05e8 | |
143 | #define BITS_TX_STOP BIT(1) | |
144 | #define BITS_RX_STOP BIT(0) | |
145 | #define FLUSH_CMD 0x05eC | |
146 | #define BITS_TX_FLUSH_CMD BIT(5) | |
147 | #define BITS_RX_FLUSH_CMD BIT(4) | |
148 | #define BITS_TX_FLUSH_FLAG_DOWN BIT(3) | |
149 | #define BITS_TX_FLUSH_FLAG_UP BIT(2) | |
150 | #define BITS_RX_FLUSH_FLAG_DOWN BIT(1) | |
151 | #define BITS_RX_FLUSH_FLAG_UP BIT(0) | |
152 | #define RX_CFF_NUM_REG 0x05f0 | |
153 | #define PMU_FSM_REG 0x05f8 | |
154 | #define RX_FIFO_PKT_IN_NUM 0x05fc | |
155 | #define RX_FIFO_PKT_OUT_NUM 0x0600 | |
156 | ||
157 | #define RGMII_SPEED_1000 0x2c | |
158 | #define RGMII_SPEED_100 0x2f | |
159 | #define RGMII_SPEED_10 0x2d | |
160 | #define MII_SPEED_100 0x0f | |
161 | #define MII_SPEED_10 0x0d | |
162 | #define GMAC_SPEED_1000 0x05 | |
163 | #define GMAC_SPEED_100 0x01 | |
164 | #define GMAC_SPEED_10 0x00 | |
165 | #define GMAC_FULL_DUPLEX BIT(4) | |
166 | ||
167 | #define RX_BQ_INT_THRESHOLD 0x01 | |
168 | #define TX_RQ_INT_THRESHOLD 0x01 | |
169 | #define RX_BQ_IN_TIMEOUT 0x10000 | |
170 | #define TX_RQ_IN_TIMEOUT 0x50000 | |
171 | ||
172 | #define MAC_MAX_FRAME_SIZE 1600 | |
173 | #define DESC_SIZE 32 | |
174 | #define RX_DESC_NUM 1024 | |
175 | #define TX_DESC_NUM 1024 | |
176 | ||
177 | #define DESC_VLD_FREE 0 | |
178 | #define DESC_VLD_BUSY 0x80000000 | |
179 | #define DESC_FL_MID 0 | |
180 | #define DESC_FL_LAST 0x20000000 | |
181 | #define DESC_FL_FIRST 0x40000000 | |
182 | #define DESC_FL_FULL 0x60000000 | |
183 | #define DESC_DATA_LEN_OFF 16 | |
184 | #define DESC_BUFF_LEN_OFF 0 | |
185 | #define DESC_DATA_MASK 0x7ff | |
186 | ||
187 | /* DMA descriptor ring helpers */ | |
188 | #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) | |
189 | #define dma_cnt(n) ((n) >> 5) | |
190 | #define dma_byte(n) ((n) << 5) | |
191 | ||
192 | struct hix5hd2_desc { | |
193 | __le32 buff_addr; | |
194 | __le32 cmd; | |
195 | } __aligned(32); | |
196 | ||
197 | struct hix5hd2_desc_sw { | |
198 | struct hix5hd2_desc *desc; | |
199 | dma_addr_t phys_addr; | |
200 | unsigned int count; | |
201 | unsigned int size; | |
202 | }; | |
203 | ||
204 | #define QUEUE_NUMS 4 | |
205 | struct hix5hd2_priv { | |
206 | struct hix5hd2_desc_sw pool[QUEUE_NUMS]; | |
207 | #define rx_fq pool[0] | |
208 | #define rx_bq pool[1] | |
209 | #define tx_bq pool[2] | |
210 | #define tx_rq pool[3] | |
211 | ||
212 | void __iomem *base; | |
213 | void __iomem *ctrl_base; | |
214 | ||
215 | struct sk_buff *tx_skb[TX_DESC_NUM]; | |
216 | struct sk_buff *rx_skb[RX_DESC_NUM]; | |
217 | ||
218 | struct device *dev; | |
219 | struct net_device *netdev; | |
220 | ||
221 | struct phy_device *phy; | |
222 | struct device_node *phy_node; | |
223 | phy_interface_t phy_mode; | |
224 | ||
225 | unsigned int speed; | |
226 | unsigned int duplex; | |
227 | ||
228 | struct clk *clk; | |
229 | struct mii_bus *bus; | |
230 | struct napi_struct napi; | |
231 | struct work_struct tx_timeout_task; | |
232 | }; | |
233 | ||
234 | static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex) | |
235 | { | |
236 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
237 | u32 val; | |
238 | ||
239 | priv->speed = speed; | |
240 | priv->duplex = duplex; | |
241 | ||
242 | switch (priv->phy_mode) { | |
243 | case PHY_INTERFACE_MODE_RGMII: | |
244 | if (speed == SPEED_1000) | |
245 | val = RGMII_SPEED_1000; | |
246 | else if (speed == SPEED_100) | |
247 | val = RGMII_SPEED_100; | |
248 | else | |
249 | val = RGMII_SPEED_10; | |
250 | break; | |
251 | case PHY_INTERFACE_MODE_MII: | |
252 | if (speed == SPEED_100) | |
253 | val = MII_SPEED_100; | |
254 | else | |
255 | val = MII_SPEED_10; | |
256 | break; | |
257 | default: | |
258 | netdev_warn(dev, "not supported mode\n"); | |
259 | val = MII_SPEED_10; | |
260 | break; | |
261 | } | |
262 | ||
263 | if (duplex) | |
264 | val |= GMAC_FULL_DUPLEX; | |
265 | writel_relaxed(val, priv->ctrl_base); | |
266 | ||
267 | writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); | |
268 | if (speed == SPEED_1000) | |
269 | val = GMAC_SPEED_1000; | |
270 | else if (speed == SPEED_100) | |
271 | val = GMAC_SPEED_100; | |
272 | else | |
273 | val = GMAC_SPEED_10; | |
274 | writel_relaxed(val, priv->base + PORT_MODE); | |
275 | writel_relaxed(0, priv->base + MODE_CHANGE_EN); | |
276 | writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); | |
277 | } | |
278 | ||
279 | static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx) | |
280 | { | |
281 | writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); | |
282 | writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); | |
283 | writel_relaxed(0, priv->base + RX_FQ_REG_EN); | |
284 | ||
285 | writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); | |
286 | writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); | |
287 | writel_relaxed(0, priv->base + RX_BQ_REG_EN); | |
288 | ||
289 | writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); | |
290 | writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); | |
291 | writel_relaxed(0, priv->base + TX_BQ_REG_EN); | |
292 | ||
293 | writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); | |
294 | writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); | |
295 | writel_relaxed(0, priv->base + TX_RQ_REG_EN); | |
296 | } | |
297 | ||
298 | static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) | |
299 | { | |
300 | writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); | |
301 | writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); | |
302 | writel_relaxed(0, priv->base + RX_FQ_REG_EN); | |
303 | } | |
304 | ||
305 | static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) | |
306 | { | |
307 | writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); | |
308 | writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); | |
309 | writel_relaxed(0, priv->base + RX_BQ_REG_EN); | |
310 | } | |
311 | ||
312 | static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) | |
313 | { | |
314 | writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); | |
315 | writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); | |
316 | writel_relaxed(0, priv->base + TX_BQ_REG_EN); | |
317 | } | |
318 | ||
319 | static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) | |
320 | { | |
321 | writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); | |
322 | writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); | |
323 | writel_relaxed(0, priv->base + TX_RQ_REG_EN); | |
324 | } | |
325 | ||
326 | static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv) | |
327 | { | |
328 | hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr); | |
329 | hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr); | |
330 | hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr); | |
331 | hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr); | |
332 | } | |
333 | ||
334 | static void hix5hd2_hw_init(struct hix5hd2_priv *priv) | |
335 | { | |
336 | u32 val; | |
337 | ||
338 | /* disable and clear all interrupts */ | |
339 | writel_relaxed(0, priv->base + ENA_PMU_INT); | |
340 | writel_relaxed(~0, priv->base + RAW_PMU_INT); | |
341 | ||
342 | writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); | |
343 | writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); | |
344 | writel_relaxed(0, priv->base + COL_SLOT_TIME); | |
345 | ||
346 | val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT; | |
347 | writel_relaxed(val, priv->base + IN_QUEUE_TH); | |
348 | ||
349 | writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); | |
350 | writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); | |
351 | ||
352 | hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); | |
353 | hix5hd2_set_desc_addr(priv); | |
354 | } | |
355 | ||
356 | static void hix5hd2_irq_enable(struct hix5hd2_priv *priv) | |
357 | { | |
358 | writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); | |
359 | } | |
360 | ||
361 | static void hix5hd2_irq_disable(struct hix5hd2_priv *priv) | |
362 | { | |
363 | writel_relaxed(0, priv->base + ENA_PMU_INT); | |
364 | } | |
365 | ||
366 | static void hix5hd2_port_enable(struct hix5hd2_priv *priv) | |
367 | { | |
368 | writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); | |
369 | writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); | |
370 | } | |
371 | ||
372 | static void hix5hd2_port_disable(struct hix5hd2_priv *priv) | |
373 | { | |
951b5d95 | 374 | writel_relaxed(~(u32)(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); |
57c5bc9a ZG |
375 | writel_relaxed(0, priv->base + DESC_WR_RD_ENA); |
376 | } | |
377 | ||
378 | static void hix5hd2_hw_set_mac_addr(struct net_device *dev) | |
379 | { | |
380 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
381 | unsigned char *mac = dev->dev_addr; | |
382 | u32 val; | |
383 | ||
384 | val = mac[1] | (mac[0] << 8); | |
385 | writel_relaxed(val, priv->base + STATION_ADDR_HIGH); | |
386 | ||
387 | val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); | |
388 | writel_relaxed(val, priv->base + STATION_ADDR_LOW); | |
389 | } | |
390 | ||
391 | static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p) | |
392 | { | |
393 | int ret; | |
394 | ||
395 | ret = eth_mac_addr(dev, p); | |
396 | if (!ret) | |
397 | hix5hd2_hw_set_mac_addr(dev); | |
398 | ||
399 | return ret; | |
400 | } | |
401 | ||
402 | static void hix5hd2_adjust_link(struct net_device *dev) | |
403 | { | |
404 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
405 | struct phy_device *phy = priv->phy; | |
406 | ||
407 | if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) { | |
408 | hix5hd2_config_port(dev, phy->speed, phy->duplex); | |
409 | phy_print_status(phy); | |
410 | } | |
411 | } | |
412 | ||
413 | static void hix5hd2_rx_refill(struct hix5hd2_priv *priv) | |
414 | { | |
415 | struct hix5hd2_desc *desc; | |
416 | struct sk_buff *skb; | |
417 | u32 start, end, num, pos, i; | |
418 | u32 len = MAC_MAX_FRAME_SIZE; | |
419 | dma_addr_t addr; | |
420 | ||
421 | /* software write pointer */ | |
422 | start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); | |
423 | /* logic read pointer */ | |
424 | end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); | |
425 | num = CIRC_SPACE(start, end, RX_DESC_NUM); | |
426 | ||
427 | for (i = 0, pos = start; i < num; i++) { | |
428 | if (priv->rx_skb[pos]) { | |
429 | break; | |
430 | } else { | |
431 | skb = netdev_alloc_skb_ip_align(priv->netdev, len); | |
432 | if (unlikely(skb == NULL)) | |
433 | break; | |
434 | } | |
435 | ||
436 | addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE); | |
437 | if (dma_mapping_error(priv->dev, addr)) { | |
438 | dev_kfree_skb_any(skb); | |
439 | break; | |
440 | } | |
441 | ||
442 | desc = priv->rx_fq.desc + pos; | |
443 | desc->buff_addr = cpu_to_le32(addr); | |
444 | priv->rx_skb[pos] = skb; | |
445 | desc->cmd = cpu_to_le32(DESC_VLD_FREE | | |
446 | (len - 1) << DESC_BUFF_LEN_OFF); | |
447 | pos = dma_ring_incr(pos, RX_DESC_NUM); | |
448 | } | |
449 | ||
450 | /* ensure desc updated */ | |
451 | wmb(); | |
452 | ||
453 | if (pos != start) | |
454 | writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); | |
455 | } | |
456 | ||
457 | static int hix5hd2_rx(struct net_device *dev, int limit) | |
458 | { | |
459 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
460 | struct sk_buff *skb; | |
461 | struct hix5hd2_desc *desc; | |
462 | dma_addr_t addr; | |
463 | u32 start, end, num, pos, i, len; | |
464 | ||
465 | /* software read pointer */ | |
466 | start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); | |
467 | /* logic write pointer */ | |
468 | end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); | |
469 | num = CIRC_CNT(end, start, RX_DESC_NUM); | |
470 | if (num > limit) | |
471 | num = limit; | |
472 | ||
473 | /* ensure get updated desc */ | |
474 | rmb(); | |
475 | for (i = 0, pos = start; i < num; i++) { | |
476 | skb = priv->rx_skb[pos]; | |
477 | if (unlikely(!skb)) { | |
478 | netdev_err(dev, "inconsistent rx_skb\n"); | |
479 | break; | |
480 | } | |
481 | priv->rx_skb[pos] = NULL; | |
482 | ||
483 | desc = priv->rx_bq.desc + pos; | |
484 | len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) & | |
485 | DESC_DATA_MASK; | |
486 | addr = le32_to_cpu(desc->buff_addr); | |
487 | dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE, | |
488 | DMA_FROM_DEVICE); | |
489 | ||
490 | skb_put(skb, len); | |
491 | if (skb->len > MAC_MAX_FRAME_SIZE) { | |
492 | netdev_err(dev, "rcv len err, len = %d\n", skb->len); | |
493 | dev->stats.rx_errors++; | |
494 | dev->stats.rx_length_errors++; | |
495 | dev_kfree_skb_any(skb); | |
496 | goto next; | |
497 | } | |
498 | ||
499 | skb->protocol = eth_type_trans(skb, dev); | |
500 | napi_gro_receive(&priv->napi, skb); | |
501 | dev->stats.rx_packets++; | |
502 | dev->stats.rx_bytes += skb->len; | |
57c5bc9a ZG |
503 | next: |
504 | pos = dma_ring_incr(pos, RX_DESC_NUM); | |
505 | } | |
506 | ||
507 | if (pos != start) | |
508 | writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); | |
509 | ||
510 | hix5hd2_rx_refill(priv); | |
511 | ||
512 | return num; | |
513 | } | |
514 | ||
515 | static void hix5hd2_xmit_reclaim(struct net_device *dev) | |
516 | { | |
517 | struct sk_buff *skb; | |
518 | struct hix5hd2_desc *desc; | |
519 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
520 | unsigned int bytes_compl = 0, pkts_compl = 0; | |
521 | u32 start, end, num, pos, i; | |
522 | dma_addr_t addr; | |
523 | ||
524 | netif_tx_lock(dev); | |
525 | ||
526 | /* software read */ | |
527 | start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); | |
528 | /* logic write */ | |
529 | end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); | |
530 | num = CIRC_CNT(end, start, TX_DESC_NUM); | |
531 | ||
532 | for (i = 0, pos = start; i < num; i++) { | |
533 | skb = priv->tx_skb[pos]; | |
534 | if (unlikely(!skb)) { | |
535 | netdev_err(dev, "inconsistent tx_skb\n"); | |
536 | break; | |
537 | } | |
538 | ||
539 | pkts_compl++; | |
540 | bytes_compl += skb->len; | |
541 | desc = priv->tx_rq.desc + pos; | |
542 | addr = le32_to_cpu(desc->buff_addr); | |
543 | dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); | |
544 | priv->tx_skb[pos] = NULL; | |
545 | dev_consume_skb_any(skb); | |
546 | pos = dma_ring_incr(pos, TX_DESC_NUM); | |
547 | } | |
548 | ||
549 | if (pos != start) | |
550 | writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); | |
551 | ||
552 | netif_tx_unlock(dev); | |
553 | ||
554 | if (pkts_compl || bytes_compl) | |
555 | netdev_completed_queue(dev, pkts_compl, bytes_compl); | |
556 | ||
557 | if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) | |
558 | netif_wake_queue(priv->netdev); | |
559 | } | |
560 | ||
561 | static int hix5hd2_poll(struct napi_struct *napi, int budget) | |
562 | { | |
563 | struct hix5hd2_priv *priv = container_of(napi, | |
564 | struct hix5hd2_priv, napi); | |
565 | struct net_device *dev = priv->netdev; | |
566 | int work_done = 0, task = budget; | |
567 | int ints, num; | |
568 | ||
569 | do { | |
570 | hix5hd2_xmit_reclaim(dev); | |
571 | num = hix5hd2_rx(dev, task); | |
572 | work_done += num; | |
573 | task -= num; | |
574 | if ((work_done >= budget) || (num == 0)) | |
575 | break; | |
576 | ||
577 | ints = readl_relaxed(priv->base + RAW_PMU_INT); | |
578 | writel_relaxed(ints, priv->base + RAW_PMU_INT); | |
579 | } while (ints & DEF_INT_MASK); | |
580 | ||
581 | if (work_done < budget) { | |
582 | napi_complete(napi); | |
583 | hix5hd2_irq_enable(priv); | |
584 | } | |
585 | ||
586 | return work_done; | |
587 | } | |
588 | ||
589 | static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id) | |
590 | { | |
591 | struct net_device *dev = (struct net_device *)dev_id; | |
592 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
593 | int ints = readl_relaxed(priv->base + RAW_PMU_INT); | |
594 | ||
595 | writel_relaxed(ints, priv->base + RAW_PMU_INT); | |
596 | if (likely(ints & DEF_INT_MASK)) { | |
597 | hix5hd2_irq_disable(priv); | |
598 | napi_schedule(&priv->napi); | |
599 | } | |
600 | ||
601 | return IRQ_HANDLED; | |
602 | } | |
603 | ||
604 | static int hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev) | |
605 | { | |
606 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
607 | struct hix5hd2_desc *desc; | |
608 | dma_addr_t addr; | |
609 | u32 pos; | |
610 | ||
611 | /* software write pointer */ | |
612 | pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); | |
613 | if (unlikely(priv->tx_skb[pos])) { | |
614 | dev->stats.tx_dropped++; | |
615 | dev->stats.tx_fifo_errors++; | |
616 | netif_stop_queue(dev); | |
617 | return NETDEV_TX_BUSY; | |
618 | } | |
619 | ||
620 | addr = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE); | |
621 | if (dma_mapping_error(priv->dev, addr)) { | |
622 | dev_kfree_skb_any(skb); | |
623 | return NETDEV_TX_OK; | |
624 | } | |
625 | ||
626 | desc = priv->tx_bq.desc + pos; | |
627 | desc->buff_addr = cpu_to_le32(addr); | |
628 | priv->tx_skb[pos] = skb; | |
629 | desc->cmd = cpu_to_le32(DESC_VLD_BUSY | DESC_FL_FULL | | |
630 | (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF | | |
631 | (skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF); | |
632 | ||
633 | /* ensure desc updated */ | |
634 | wmb(); | |
635 | ||
636 | pos = dma_ring_incr(pos, TX_DESC_NUM); | |
637 | writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); | |
638 | ||
860e9538 | 639 | netif_trans_update(dev); |
57c5bc9a ZG |
640 | dev->stats.tx_packets++; |
641 | dev->stats.tx_bytes += skb->len; | |
642 | netdev_sent_queue(dev, skb->len); | |
643 | ||
644 | return NETDEV_TX_OK; | |
645 | } | |
646 | ||
647 | static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv) | |
648 | { | |
649 | struct hix5hd2_desc *desc; | |
650 | dma_addr_t addr; | |
651 | int i; | |
652 | ||
653 | for (i = 0; i < RX_DESC_NUM; i++) { | |
654 | struct sk_buff *skb = priv->rx_skb[i]; | |
655 | if (skb == NULL) | |
656 | continue; | |
657 | ||
658 | desc = priv->rx_fq.desc + i; | |
659 | addr = le32_to_cpu(desc->buff_addr); | |
660 | dma_unmap_single(priv->dev, addr, | |
661 | MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE); | |
662 | dev_kfree_skb_any(skb); | |
663 | priv->rx_skb[i] = NULL; | |
664 | } | |
665 | ||
666 | for (i = 0; i < TX_DESC_NUM; i++) { | |
667 | struct sk_buff *skb = priv->tx_skb[i]; | |
668 | if (skb == NULL) | |
669 | continue; | |
670 | ||
671 | desc = priv->tx_rq.desc + i; | |
672 | addr = le32_to_cpu(desc->buff_addr); | |
673 | dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); | |
674 | dev_kfree_skb_any(skb); | |
675 | priv->tx_skb[i] = NULL; | |
676 | } | |
677 | } | |
678 | ||
679 | static int hix5hd2_net_open(struct net_device *dev) | |
680 | { | |
681 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
682 | int ret; | |
683 | ||
684 | ret = clk_prepare_enable(priv->clk); | |
685 | if (ret < 0) { | |
686 | netdev_err(dev, "failed to enable clk %d\n", ret); | |
687 | return ret; | |
688 | } | |
689 | ||
690 | priv->phy = of_phy_connect(dev, priv->phy_node, | |
691 | &hix5hd2_adjust_link, 0, priv->phy_mode); | |
692 | if (!priv->phy) | |
693 | return -ENODEV; | |
694 | ||
695 | phy_start(priv->phy); | |
696 | hix5hd2_hw_init(priv); | |
697 | hix5hd2_rx_refill(priv); | |
698 | ||
699 | netdev_reset_queue(dev); | |
700 | netif_start_queue(dev); | |
701 | napi_enable(&priv->napi); | |
702 | ||
703 | hix5hd2_port_enable(priv); | |
704 | hix5hd2_irq_enable(priv); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static int hix5hd2_net_close(struct net_device *dev) | |
710 | { | |
711 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
712 | ||
713 | hix5hd2_port_disable(priv); | |
714 | hix5hd2_irq_disable(priv); | |
715 | napi_disable(&priv->napi); | |
716 | netif_stop_queue(dev); | |
717 | hix5hd2_free_dma_desc_rings(priv); | |
718 | ||
719 | if (priv->phy) { | |
720 | phy_stop(priv->phy); | |
721 | phy_disconnect(priv->phy); | |
722 | } | |
723 | ||
724 | clk_disable_unprepare(priv->clk); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | static void hix5hd2_tx_timeout_task(struct work_struct *work) | |
730 | { | |
731 | struct hix5hd2_priv *priv; | |
732 | ||
733 | priv = container_of(work, struct hix5hd2_priv, tx_timeout_task); | |
734 | hix5hd2_net_close(priv->netdev); | |
735 | hix5hd2_net_open(priv->netdev); | |
736 | } | |
737 | ||
738 | static void hix5hd2_net_timeout(struct net_device *dev) | |
739 | { | |
740 | struct hix5hd2_priv *priv = netdev_priv(dev); | |
741 | ||
742 | schedule_work(&priv->tx_timeout_task); | |
743 | } | |
744 | ||
745 | static const struct net_device_ops hix5hd2_netdev_ops = { | |
746 | .ndo_open = hix5hd2_net_open, | |
747 | .ndo_stop = hix5hd2_net_close, | |
748 | .ndo_start_xmit = hix5hd2_net_xmit, | |
749 | .ndo_tx_timeout = hix5hd2_net_timeout, | |
750 | .ndo_set_mac_address = hix5hd2_net_set_mac_address, | |
751 | }; | |
752 | ||
753 | static int hix5hd2_get_settings(struct net_device *net_dev, | |
754 | struct ethtool_cmd *cmd) | |
755 | { | |
756 | struct hix5hd2_priv *priv = netdev_priv(net_dev); | |
757 | ||
758 | if (!priv->phy) | |
759 | return -ENODEV; | |
760 | ||
761 | return phy_ethtool_gset(priv->phy, cmd); | |
762 | } | |
763 | ||
764 | static int hix5hd2_set_settings(struct net_device *net_dev, | |
765 | struct ethtool_cmd *cmd) | |
766 | { | |
767 | struct hix5hd2_priv *priv = netdev_priv(net_dev); | |
768 | ||
769 | if (!priv->phy) | |
770 | return -ENODEV; | |
771 | ||
772 | return phy_ethtool_sset(priv->phy, cmd); | |
773 | } | |
774 | ||
775 | static struct ethtool_ops hix5hd2_ethtools_ops = { | |
776 | .get_link = ethtool_op_get_link, | |
777 | .get_settings = hix5hd2_get_settings, | |
778 | .set_settings = hix5hd2_set_settings, | |
779 | }; | |
780 | ||
781 | static int hix5hd2_mdio_wait_ready(struct mii_bus *bus) | |
782 | { | |
783 | struct hix5hd2_priv *priv = bus->priv; | |
784 | void __iomem *base = priv->base; | |
785 | int i, timeout = 10000; | |
786 | ||
787 | for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { | |
788 | if (i == timeout) | |
789 | return -ETIMEDOUT; | |
790 | usleep_range(10, 20); | |
791 | } | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg) | |
797 | { | |
798 | struct hix5hd2_priv *priv = bus->priv; | |
799 | void __iomem *base = priv->base; | |
800 | int val, ret; | |
801 | ||
802 | ret = hix5hd2_mdio_wait_ready(bus); | |
803 | if (ret < 0) | |
804 | goto out; | |
805 | ||
806 | writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); | |
807 | ret = hix5hd2_mdio_wait_ready(bus); | |
808 | if (ret < 0) | |
809 | goto out; | |
810 | ||
811 | val = readl_relaxed(base + MDIO_RDATA_STATUS); | |
812 | if (val & MDIO_R_VALID) { | |
813 | dev_err(bus->parent, "SMI bus read not valid\n"); | |
814 | ret = -ENODEV; | |
815 | goto out; | |
816 | } | |
817 | ||
818 | val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); | |
819 | ret = (val >> 16) & 0xFFFF; | |
820 | out: | |
821 | return ret; | |
822 | } | |
823 | ||
824 | static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) | |
825 | { | |
826 | struct hix5hd2_priv *priv = bus->priv; | |
827 | void __iomem *base = priv->base; | |
828 | int ret; | |
829 | ||
830 | ret = hix5hd2_mdio_wait_ready(bus); | |
831 | if (ret < 0) | |
832 | goto out; | |
833 | ||
834 | writel_relaxed(val, base + MDIO_SINGLE_DATA); | |
835 | writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); | |
836 | ret = hix5hd2_mdio_wait_ready(bus); | |
837 | out: | |
838 | return ret; | |
839 | } | |
840 | ||
841 | static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv) | |
842 | { | |
843 | int i; | |
844 | ||
845 | for (i = 0; i < QUEUE_NUMS; i++) { | |
846 | if (priv->pool[i].desc) { | |
847 | dma_free_coherent(priv->dev, priv->pool[i].size, | |
848 | priv->pool[i].desc, | |
849 | priv->pool[i].phys_addr); | |
850 | priv->pool[i].desc = NULL; | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv) | |
856 | { | |
857 | struct device *dev = priv->dev; | |
858 | struct hix5hd2_desc *virt_addr; | |
859 | dma_addr_t phys_addr; | |
860 | int size, i; | |
861 | ||
862 | priv->rx_fq.count = RX_DESC_NUM; | |
863 | priv->rx_bq.count = RX_DESC_NUM; | |
864 | priv->tx_bq.count = TX_DESC_NUM; | |
865 | priv->tx_rq.count = TX_DESC_NUM; | |
866 | ||
867 | for (i = 0; i < QUEUE_NUMS; i++) { | |
868 | size = priv->pool[i].count * sizeof(struct hix5hd2_desc); | |
869 | virt_addr = dma_alloc_coherent(dev, size, &phys_addr, | |
870 | GFP_KERNEL); | |
871 | if (virt_addr == NULL) | |
872 | goto error_free_pool; | |
873 | ||
874 | memset(virt_addr, 0, size); | |
875 | priv->pool[i].size = size; | |
876 | priv->pool[i].desc = virt_addr; | |
877 | priv->pool[i].phys_addr = phys_addr; | |
878 | } | |
879 | return 0; | |
880 | ||
881 | error_free_pool: | |
882 | hix5hd2_destroy_hw_desc_queue(priv); | |
883 | ||
884 | return -ENOMEM; | |
885 | } | |
886 | ||
887 | static int hix5hd2_dev_probe(struct platform_device *pdev) | |
888 | { | |
889 | struct device *dev = &pdev->dev; | |
890 | struct device_node *node = dev->of_node; | |
891 | struct net_device *ndev; | |
892 | struct hix5hd2_priv *priv; | |
893 | struct resource *res; | |
894 | struct mii_bus *bus; | |
895 | const char *mac_addr; | |
896 | int ret; | |
897 | ||
898 | ndev = alloc_etherdev(sizeof(struct hix5hd2_priv)); | |
899 | if (!ndev) | |
900 | return -ENOMEM; | |
901 | ||
902 | platform_set_drvdata(pdev, ndev); | |
903 | ||
904 | priv = netdev_priv(ndev); | |
905 | priv->dev = dev; | |
906 | priv->netdev = ndev; | |
907 | ||
908 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
909 | priv->base = devm_ioremap_resource(dev, res); | |
910 | if (IS_ERR(priv->base)) { | |
911 | ret = PTR_ERR(priv->base); | |
912 | goto out_free_netdev; | |
913 | } | |
914 | ||
915 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
916 | priv->ctrl_base = devm_ioremap_resource(dev, res); | |
917 | if (IS_ERR(priv->ctrl_base)) { | |
918 | ret = PTR_ERR(priv->ctrl_base); | |
919 | goto out_free_netdev; | |
920 | } | |
921 | ||
922 | priv->clk = devm_clk_get(&pdev->dev, NULL); | |
923 | if (IS_ERR(priv->clk)) { | |
924 | netdev_err(ndev, "failed to get clk\n"); | |
925 | ret = -ENODEV; | |
926 | goto out_free_netdev; | |
927 | } | |
928 | ||
929 | ret = clk_prepare_enable(priv->clk); | |
930 | if (ret < 0) { | |
931 | netdev_err(ndev, "failed to enable clk %d\n", ret); | |
932 | goto out_free_netdev; | |
933 | } | |
934 | ||
935 | bus = mdiobus_alloc(); | |
936 | if (bus == NULL) { | |
937 | ret = -ENOMEM; | |
938 | goto out_free_netdev; | |
939 | } | |
940 | ||
941 | bus->priv = priv; | |
942 | bus->name = "hix5hd2_mii_bus"; | |
943 | bus->read = hix5hd2_mdio_read; | |
944 | bus->write = hix5hd2_mdio_write; | |
945 | bus->parent = &pdev->dev; | |
946 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); | |
947 | priv->bus = bus; | |
948 | ||
949 | ret = of_mdiobus_register(bus, node); | |
950 | if (ret) | |
951 | goto err_free_mdio; | |
952 | ||
953 | priv->phy_mode = of_get_phy_mode(node); | |
954 | if (priv->phy_mode < 0) { | |
955 | netdev_err(ndev, "not find phy-mode\n"); | |
956 | ret = -EINVAL; | |
957 | goto err_mdiobus; | |
958 | } | |
959 | ||
960 | priv->phy_node = of_parse_phandle(node, "phy-handle", 0); | |
961 | if (!priv->phy_node) { | |
962 | netdev_err(ndev, "not find phy-handle\n"); | |
963 | ret = -EINVAL; | |
964 | goto err_mdiobus; | |
965 | } | |
966 | ||
967 | ndev->irq = platform_get_irq(pdev, 0); | |
968 | if (ndev->irq <= 0) { | |
969 | netdev_err(ndev, "No irq resource\n"); | |
970 | ret = -EINVAL; | |
971 | goto out_phy_node; | |
972 | } | |
973 | ||
974 | ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt, | |
975 | 0, pdev->name, ndev); | |
976 | if (ret) { | |
977 | netdev_err(ndev, "devm_request_irq failed\n"); | |
978 | goto out_phy_node; | |
979 | } | |
980 | ||
981 | mac_addr = of_get_mac_address(node); | |
982 | if (mac_addr) | |
983 | ether_addr_copy(ndev->dev_addr, mac_addr); | |
984 | if (!is_valid_ether_addr(ndev->dev_addr)) { | |
985 | eth_hw_addr_random(ndev); | |
986 | netdev_warn(ndev, "using random MAC address %pM\n", | |
987 | ndev->dev_addr); | |
988 | } | |
989 | ||
990 | INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task); | |
991 | ndev->watchdog_timeo = 6 * HZ; | |
992 | ndev->priv_flags |= IFF_UNICAST_FLT; | |
993 | ndev->netdev_ops = &hix5hd2_netdev_ops; | |
994 | ndev->ethtool_ops = &hix5hd2_ethtools_ops; | |
995 | SET_NETDEV_DEV(ndev, dev); | |
996 | ||
997 | ret = hix5hd2_init_hw_desc_queue(priv); | |
998 | if (ret) | |
999 | goto out_phy_node; | |
1000 | ||
1001 | netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT); | |
1002 | ret = register_netdev(priv->netdev); | |
1003 | if (ret) { | |
1004 | netdev_err(ndev, "register_netdev failed!"); | |
1005 | goto out_destroy_queue; | |
1006 | } | |
1007 | ||
1008 | clk_disable_unprepare(priv->clk); | |
1009 | ||
1010 | return ret; | |
1011 | ||
1012 | out_destroy_queue: | |
1013 | netif_napi_del(&priv->napi); | |
1014 | hix5hd2_destroy_hw_desc_queue(priv); | |
1015 | out_phy_node: | |
1016 | of_node_put(priv->phy_node); | |
1017 | err_mdiobus: | |
1018 | mdiobus_unregister(bus); | |
1019 | err_free_mdio: | |
1020 | mdiobus_free(bus); | |
1021 | out_free_netdev: | |
1022 | free_netdev(ndev); | |
1023 | ||
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | static int hix5hd2_dev_remove(struct platform_device *pdev) | |
1028 | { | |
1029 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1030 | struct hix5hd2_priv *priv = netdev_priv(ndev); | |
1031 | ||
1032 | netif_napi_del(&priv->napi); | |
1033 | unregister_netdev(ndev); | |
1034 | mdiobus_unregister(priv->bus); | |
1035 | mdiobus_free(priv->bus); | |
1036 | ||
1037 | hix5hd2_destroy_hw_desc_queue(priv); | |
1038 | of_node_put(priv->phy_node); | |
1039 | cancel_work_sync(&priv->tx_timeout_task); | |
1040 | free_netdev(ndev); | |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static const struct of_device_id hix5hd2_of_match[] = { | |
1046 | {.compatible = "hisilicon,hix5hd2-gmac",}, | |
1047 | {}, | |
1048 | }; | |
1049 | ||
1050 | MODULE_DEVICE_TABLE(of, hix5hd2_of_match); | |
1051 | ||
1052 | static struct platform_driver hix5hd2_dev_driver = { | |
1053 | .driver = { | |
1054 | .name = "hix5hd2-gmac", | |
1055 | .of_match_table = hix5hd2_of_match, | |
1056 | }, | |
1057 | .probe = hix5hd2_dev_probe, | |
1058 | .remove = hix5hd2_dev_remove, | |
1059 | }; | |
1060 | ||
1061 | module_platform_driver(hix5hd2_dev_driver); | |
1062 | ||
1063 | MODULE_DESCRIPTION("HISILICON HIX5HD2 Ethernet driver"); | |
1064 | MODULE_LICENSE("GPL v2"); | |
1065 | MODULE_ALIAS("platform:hix5hd2-gmac"); |