[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

enum _dsm_op_index {
	HNS_OP_RESET_FUNC               = 0x1,
	HNS_OP_SERDES_LP_FUNC           = 0x2,
	HNS_OP_LED_SET_FUNC             = 0x3,
	HNS_OP_GET_PORT_TYPE_FUNC       = 0x4,
	HNS_OP_GET_SFP_STAT_FUNC        = 0x5,
};

enum _dsm_rst_type {
	HNS_DSAF_RESET_FUNC     = 0x1,
	HNS_PPE_RESET_FUNC      = 0x2,
	HNS_XGE_CORE_RESET_FUNC = 0x3,
	HNS_XGE_RESET_FUNC      = 0x4,
	HNS_GE_RESET_FUNC       = 0x5,
};

const u8 hns_dsaf_acpi_dsm_uuid[] = {
	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
};

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
			     u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_ctrl) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_syscon(mac_cb->cpld_ctrl,
					  mac_cb->cpld_ctrl_reg, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
		dsaf_write_syscon(mac_cb->cpld_ctrl,
				  mac_cb->cpld_ctrl_reg, value);
		mac_cb->cpld_led_value = value;
	}
}

static void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_ctrl)
		return;

	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
			  CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
			   enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value =
			dsaf_read_syscon(mac_cb->cpld_ctrl,
					 mac_cb->cpld_ctrl_reg);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	default:
		dev_err(mac_cb->dev, "invalid led state: %d!", status);
		return -EINVAL;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
				       u32 port_type, u32 port, u32 val)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = port_type;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = port;
	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	obj_args[2].integer.value = val;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 3;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	if (!obj) {
		dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
			 port_type, port);
		return;
	}

	ACPI_FREE(obj);
}

static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!dereset) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_DSAF_RESET_FUNC,
				   0, dereset);
}

static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				      bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;
	reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= XGMAC_TRX_CORE_SRST_M
		<< dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_dsaf_srst_chns - reset dsaf channels
 * @dsaf_dev: dsaf device struct pointer
 * @msk: xbar channels mask value:
 * bit0-5 for xge0-5
 * bit6-11 for ppe0-5
 * bit12-17 for roce0-5
 * bit18-19 for com/dfx
 * @enable: false - request reset , true - drop reset
 */
void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable)
{
	u32 reg_addr;

	if (!enable)
		reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, msk);
}

void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable)
{
	if (!enable) {
		dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
	} else {
		dsaf_write_sub(dsaf_dev,
			       DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);
		dsaf_write_sub(dsaf_dev,
			       DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);
		msleep(20);
		dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);
	}
}

static void
hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
				    u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_CORE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				     bool dereset)
{
	u32 reg_val_1;
	u32 reg_val_2;
	u32 port_rst_off;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
		/* there is difference between V1 and V2 in register.*/
		reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
				0x1041041 : 0x2082082;
		reg_val_2 <<= port_rst_off;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540;
		reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;

		reg_val_1 <<= dsaf_dev->reset_offset;
		reg_val_2 <<= dsaf_dev->reset_offset;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					  u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_GE_RESET_FUNC, port, dereset);
}

static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				 bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	reg_val |= RESET_REQ_OR_DREQ <<	dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void
hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_PPE_RESET_FUNC, port, dereset);
}

static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 reg_val;
	u32 reg_addr;

	if (!(dev_of_node(dsaf_dev->dev)))
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (!dereset)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (!dereset)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if;

	if (is_ver1) {
		if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
			return PHY_INTERFACE_MODE_SGMII;

		if (mac_id >= 0 && mac_id <= 3)
			reg = HNS_MAC_HILINK4_REG;
		else
			reg = HNS_MAC_HILINK3_REG;
	} else{
		if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
			reg = HNS_MAC_HILINK4V2_REG;
		else
			reg = HNS_MAC_HILINK3V2_REG;
	}

	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
		phy_if = PHY_INTERFACE_MODE_XGMII;
	else
		phy_if = PHY_INTERFACE_MODE_SGMII;

	return phy_if;
}

static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
{
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	union acpi_object *obj;
	union acpi_object obj_args, argv4;

	obj_args.integer.type = ACPI_TYPE_INTEGER;
	obj_args.integer.value = mac_cb->mac_id;

	argv4.type = ACPI_TYPE_PACKAGE,
	argv4.package.count = 1,
	argv4.package.elements = &obj_args,

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_GET_PORT_TYPE_FUNC, &argv4);

	if (!obj || obj->type != ACPI_TYPE_INTEGER)
		return phy_if;

	phy_if = obj->integer.value ?
		PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;

	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);

	ACPI_FREE(obj);

	return phy_if;
}

int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
{
	if (!mac_cb->cpld_ctrl)
		return -ENODEV;

	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
					+ MAC_SFP_PORT_OFFSET);

	return 0;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
{
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_dev) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin;

		if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
#define HILINK_ACCESS_SEL_CFG		0x40008
			/* hilink4 & hilink3 use the same xge training and
			 * xge u adaptor. There is a hilink access sel cfg
			 * register to select which one to be configed
			 */
			if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
			    (mac_cb->mac_id <= 3))
				dsaf_write_syscon(mac_cb->serdes_ctrl,
						  HILINK_ACCESS_SEL_CFG, 0);
			else
				dsaf_write_syscon(mac_cb->serdes_ctrl,
						  HILINK_ACCESS_SEL_CFG, 3);
		}

		origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
				(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
	}

	return 0;
}

static int
hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = mac_cb->mac_id;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = !!en;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 2;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_SERDES_LP_FUNC, &argv4);
	if (!obj) {
		dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
			 mac_cb->mac_id);

		return -ENOTSUPP;
	}

	ACPI_FREE(obj);

	return 0;
}

struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
{
	struct dsaf_misc_op *misc_op;

	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	if (!misc_op)
		return NULL;

	if (dev_of_node(dsaf_dev->dev)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
		misc_op->ppe_srst = hns_ppe_srst_by_port;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst_acpi;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
		misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	} else {
		devm_kfree(dsaf_dev->dev, (void *)misc_op);
		misc_op = NULL;
	}

	return (void *)misc_op;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
f00ef863 KY	15	enum _dsm_op_index {
	16	HNS_OP_RESET_FUNC = 0x1,
	17	HNS_OP_SERDES_LP_FUNC = 0x2,
	18	HNS_OP_LED_SET_FUNC = 0x3,
	19	HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
	20	HNS_OP_GET_SFP_STAT_FUNC = 0x5,
	21	};
	22
	23	enum _dsm_rst_type {
	24	HNS_DSAF_RESET_FUNC = 0x1,
	25	HNS_PPE_RESET_FUNC = 0x2,
	26	HNS_XGE_CORE_RESET_FUNC = 0x3,
	27	HNS_XGE_RESET_FUNC = 0x4,
	28	HNS_GE_RESET_FUNC = 0x5,
	29	};
	30
	31	const u8 hns_dsaf_acpi_dsm_uuid[] = {
	32	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	33	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
	34	};
	35
831d828b YZZ	36	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	37	{
	38	if (dsaf_dev->sub_ctrl)
	39	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	40	else
	41	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	42	}
	43
	44	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	45	{
	46	u32 ret;
	47
	48	if (dsaf_dev->sub_ctrl)
	49	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	50	else
	51	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	52
	53	return ret;
	54	}
	55
a24274aa KY	56	static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
a24274aa KY	57	u16 speed, int data)
511e6bc0	58	{
	59	int speed_reg = 0;
	60	u8 value;
	61
	62	if (!mac_cb) {
	63	pr_err("sfp_led_opt mac_dev is null!\n");
	64	return;
	65	}
31d4446d YZZ	66	if (!mac_cb->cpld_ctrl) {
31d4446d YZZ	67	dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
511e6bc0	68	mac_cb->mac_id);
	69	return;
	70	}
	71
	72	if (speed == MAC_SPEED_10000)
	73	speed_reg = 1;
	74
	75	value = mac_cb->cpld_led_value;
	76
	77	if (link_status) {
	78	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	79	dsaf_set_field(value, DSAF_LED_SPEED_M,
	80	DSAF_LED_SPEED_S, speed_reg);
	81	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	82
	83	if (value != mac_cb->cpld_led_value) {
31d4446d YZZ	84	dsaf_write_syscon(mac_cb->cpld_ctrl,
31d4446d YZZ	85	mac_cb->cpld_ctrl_reg, value);
511e6bc0	86	mac_cb->cpld_led_value = value;
	87	}
	88	} else {
d8a8371e DH	89	value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
	90	dsaf_write_syscon(mac_cb->cpld_ctrl,
	91	mac_cb->cpld_ctrl_reg, value);
	92	mac_cb->cpld_led_value = value;
511e6bc0	93	}
	94	}
	95
a24274aa	96	static void cpld_led_reset(struct hns_mac_cb *mac_cb)
511e6bc0	97	{
31d4446d	98	if (!mac_cb \|\| !mac_cb->cpld_ctrl)
511e6bc0	99	return;
511e6bc0	100
31d4446d YZZ	101	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	102	CPLD_LED_DEFAULT_VALUE);
511e6bc0	103	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	104	}
	105
a24274aa KY	106	static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
a24274aa KY	107	enum hnae_led_state status)
511e6bc0	108	{
	109	switch (status) {
	110	case HNAE_LED_ACTIVE:
31d4446d YZZ	111	mac_cb->cpld_led_value =
	112	dsaf_read_syscon(mac_cb->cpld_ctrl,
	113	mac_cb->cpld_ctrl_reg);
511e6bc0	114	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
511e6bc0	115	CPLD_LED_ON_VALUE);
31d4446d YZZ	116	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	117	mac_cb->cpld_led_value);
d8a8371e	118	break;
511e6bc0	119	case HNAE_LED_INACTIVE:
	120	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	121	CPLD_LED_DEFAULT_VALUE);
31d4446d YZZ	122	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	123	mac_cb->cpld_led_value);
511e6bc0	124	break;
511e6bc0	125	default:
d8a8371e DH	126	dev_err(mac_cb->dev, "invalid led state: %d!", status);
d8a8371e DH	127	return -EINVAL;
511e6bc0	128	}
	129
	130	return 0;
	131	}
	132
	133	#define RESET_REQ_OR_DREQ 1
	134
f00ef863 KY	135	static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
	136	u32 port_type, u32 port, u32 val)
	137	{
	138	union acpi_object *obj;
	139	union acpi_object obj_args[3], argv4;
	140
	141	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	142	obj_args[0].integer.value = port_type;
	143	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	144	obj_args[1].integer.value = port;
	145	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	146	obj_args[2].integer.value = val;
	147
	148	argv4.type = ACPI_TYPE_PACKAGE;
	149	argv4.package.count = 3;
	150	argv4.package.elements = obj_args;
	151
	152	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
	153	hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	154	if (!obj) {
	155	dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
	156	port_type, port);
	157	return;
	158	}
	159
	160	ACPI_FREE(obj);
	161	}
	162
a24274aa	163	static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	164	{
	165	u32 xbar_reg_addr;
	166	u32 nt_reg_addr;
	167
a24274aa	168	if (!dereset) {
511e6bc0	169	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	170	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	171	} else {
	172	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	173	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	174	}
	175
831d828b YZZ	176	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	177	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	178	}
511e6bc0	179
f00ef863 KY	180	static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
	181	{
	182	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	183	HNS_DSAF_RESET_FUNC,
	184	0, dereset);
	185	}
	186
a24274aa KY	187	static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	188	bool dereset)
511e6bc0	189	{
	190	u32 reg_val = 0;
	191	u32 reg_addr;
	192
	193	if (port >= DSAF_XGE_NUM)
	194	return;
	195
	196	reg_val \|= RESET_REQ_OR_DREQ;
850bfa3b	197	reg_val \|= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	198
a24274aa	199	if (!dereset)
511e6bc0	200	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	201	else
	202	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	203
831d828b	204	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	205	}
511e6bc0	206
f00ef863 KY	207	static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	208	u32 port, bool dereset)
	209	{
	210	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	211	HNS_XGE_RESET_FUNC, port, dereset);
	212	}
	213
a24274aa KY	214	static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
a24274aa KY	215	u32 port, bool dereset)
511e6bc0	216	{
	217	u32 reg_val = 0;
	218	u32 reg_addr;
	219
	220	if (port >= DSAF_XGE_NUM)
	221	return;
	222
850bfa3b YZZ	223	reg_val \|= XGMAC_TRX_CORE_SRST_M
850bfa3b YZZ	224	<< dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	225
a24274aa	226	if (!dereset)
511e6bc0	227	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	228	else
	229	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	230
831d828b	231	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	232	}
511e6bc0	233
e0180688	234	/**
	235	* hns_dsaf_srst_chns - reset dsaf channels
	236	* @dsaf_dev: dsaf device struct pointer
	237	* @msk: xbar channels mask value:
	238	* bit0-5 for xge0-5
	239	* bit6-11 for ppe0-5
	240	* bit12-17 for roce0-5
	241	* bit18-19 for com/dfx
	242	* @enable: false - request reset , true - drop reset
	243	*/
	244	void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool enable)
	245	{
	246	u32 reg_addr;
	247
	248	if (!enable)
	249	reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
	250	else
	251	reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;
	252
	253	dsaf_write_sub(dsaf_dev, reg_addr, msk);
	254	}
	255
	256	void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool enable)
	257	{
	258	if (!enable) {
	259	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
	260	} else {
	261	dsaf_write_sub(dsaf_dev,
	262	DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);
	263	dsaf_write_sub(dsaf_dev,
	264	DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);
	265	msleep(20);
	266	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);
	267	}
	268	}
	269
f00ef863 KY	270	static void
	271	hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	272	u32 port, bool dereset)
	273	{
	274	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	275	HNS_XGE_CORE_RESET_FUNC, port, dereset);
	276	}
	277
a24274aa KY	278	static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	279	bool dereset)
511e6bc0	280	{
	281	u32 reg_val_1;
	282	u32 reg_val_2;
850bfa3b	283	u32 port_rst_off;
511e6bc0	284
	285	if (port >= DSAF_GE_NUM)
	286	return;
	287
89a44093	288	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	289	reg_val_1 = 0x1 << port;
850bfa3b	290	port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
13ac695e	291	/* there is difference between V1 and V2 in register.*/
d9fdb4ed DH	292	reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
	293	0x1041041 : 0x2082082;
	294	reg_val_2 <<= port_rst_off;
511e6bc0	295
a24274aa	296	if (!dereset) {
831d828b	297	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	298	reg_val_1);
511e6bc0	299
831d828b	300	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	301	reg_val_2);
511e6bc0	302	} else {
831d828b	303	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	304	reg_val_2);
511e6bc0	305
831d828b	306	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	307	reg_val_1);
	308	}
	309	} else {
d9fdb4ed DH	310	reg_val_1 = 0x15540;
d9fdb4ed DH	311	reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;
0b03fd85	312
d9fdb4ed DH	313	reg_val_1 <<= dsaf_dev->reset_offset;
d9fdb4ed DH	314	reg_val_2 <<= dsaf_dev->reset_offset;
511e6bc0	315
a24274aa	316	if (!dereset) {
831d828b	317	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	318	reg_val_1);
511e6bc0	319
831d828b	320	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	321	reg_val_2);
511e6bc0	322	} else {
831d828b	323	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	324	reg_val_1);
511e6bc0	325
831d828b	326	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	327	reg_val_2);
	328	}
	329	}
	330	}
	331
f00ef863 KY	332	static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	333	u32 port, bool dereset)
	334	{
	335	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	336	HNS_GE_RESET_FUNC, port, dereset);
	337	}
	338
a24274aa KY	339	static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	340	bool dereset)
511e6bc0	341	{
	342	u32 reg_val = 0;
	343	u32 reg_addr;
	344
850bfa3b	345	reg_val \|= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	346
a24274aa	347	if (!dereset)
511e6bc0	348	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	349	else
	350	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	351
831d828b	352	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	353	}
511e6bc0	354
f00ef863 KY	355	static void
	356	hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
	357	{
	358	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	359	HNS_PPE_RESET_FUNC, port, dereset);
	360	}
	361
a24274aa	362	static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	363	{
511e6bc0	364	u32 reg_val;
	365	u32 reg_addr;
	366
f00ef863 KY	367	if (!(dev_of_node(dsaf_dev->dev)))
	368	return;
	369
89a44093	370	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	371	reg_val = RESET_REQ_OR_DREQ;
a24274aa	372	if (!dereset)
511e6bc0	373	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	374	else
	375	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	376
	377	} else {
422c3107	378	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	379
a24274aa	380	if (!dereset)
511e6bc0	381	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	382	else
	383	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	384	}
	385
831d828b	386	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	387	}
	388
	389	/**
	390	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	391	* @mac_cb: mac control block
	392	* retuen phy interface
	393	*/
a24274aa	394	static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
511e6bc0	395	{
c1203fe7 SL	396	u32 mode;
c1203fe7 SL	397	u32 reg;
c1203fe7	398	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	399	int mac_id = mac_cb->mac_id;
0d768fc6	400	phy_interface_t phy_if;
511e6bc0	401
0d768fc6 YZZ	402	if (is_ver1) {
	403	if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
	404	return PHY_INTERFACE_MODE_SGMII;
	405
	406	if (mac_id >= 0 && mac_id <= 3)
	407	reg = HNS_MAC_HILINK4_REG;
511e6bc0	408	else
0d768fc6 YZZ	409	reg = HNS_MAC_HILINK3_REG;
	410	} else{
	411	if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
	412	reg = HNS_MAC_HILINK4V2_REG;
c1203fe7	413	else
0d768fc6	414	reg = HNS_MAC_HILINK3V2_REG;
511e6bc0	415	}
0d768fc6 YZZ	416
	417	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	418	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
	419	phy_if = PHY_INTERFACE_MODE_XGMII;
	420	else
	421	phy_if = PHY_INTERFACE_MODE_SGMII;
	422
511e6bc0	423	return phy_if;
	424	}
	425
f00ef863 KY	426	static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
	427	{
	428	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	429	union acpi_object *obj;
	430	union acpi_object obj_args, argv4;
	431
	432	obj_args.integer.type = ACPI_TYPE_INTEGER;
	433	obj_args.integer.value = mac_cb->mac_id;
	434
	435	argv4.type = ACPI_TYPE_PACKAGE,
	436	argv4.package.count = 1,
	437	argv4.package.elements = &obj_args,
	438
	439	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
	440	hns_dsaf_acpi_dsm_uuid, 0,
	441	HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
	442
	443	if (!obj \|\| obj->type != ACPI_TYPE_INTEGER)
	444	return phy_if;
	445
	446	phy_if = obj->integer.value ?
	447	PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
	448
	449	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
	450
	451	ACPI_FREE(obj);
	452
	453	return phy_if;
	454	}
	455
31d4446d YZZ	456	int hns_mac_get_sfp_prsnt(struct hns_mac_cb mac_cb, int sfp_prsnt)
	457	{
	458	if (!mac_cb->cpld_ctrl)
	459	return -ENODEV;
	460
	461	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
	462	+ MAC_SFP_PORT_OFFSET);
	463
	464	return 0;
	465	}
	466
511e6bc0	467	/**
	468	* hns_mac_config_sds_loopback - set loop back for serdes
	469	* @mac_cb: mac control block
	470	* retuen 0 == success
	471	*/
a24274aa	472	static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
511e6bc0	473	{
511e6bc0	474	const u8 lane_id[] = {
	475	0, /* mac 0 -> lane 0 */
	476	1, /* mac 1 -> lane 1 */
	477	2, /* mac 2 -> lane 2 */
	478	3, /* mac 3 -> lane 3 */
	479	2, /* mac 4 -> lane 2 */
	480	3, /* mac 5 -> lane 3 */
	481	0, /* mac 6 -> lane 0 */
	482	1 /* mac 7 -> lane 1 */
	483	};
	484	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	485	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	486
	487	int sfp_prsnt;
	488	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	489
652d39b0	490	if (!mac_cb->phy_dev) {
511e6bc0	491	if (ret)
	492	pr_info("please confirm sfp is present or not\n");
	493	else
	494	if (!sfp_prsnt)
	495	pr_info("no sfp in this eth\n");
	496	}
	497
831d828b	498	if (mac_cb->serdes_ctrl) {
89a6b1aa KY	499	u32 origin;
	500
	501	if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
	502	#define HILINK_ACCESS_SEL_CFG 0x40008
	503	/* hilink4 & hilink3 use the same xge training and
	504	* xge u adaptor. There is a hilink access sel cfg
	505	* register to select which one to be configed
	506	*/
	507	if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
	508	(mac_cb->mac_id <= 3))
	509	dsaf_write_syscon(mac_cb->serdes_ctrl,
	510	HILINK_ACCESS_SEL_CFG, 0);
	511	else
	512	dsaf_write_syscon(mac_cb->serdes_ctrl,
	513	HILINK_ACCESS_SEL_CFG, 3);
	514	}
	515
	516	origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
831d828b	517
a24274aa	518	dsaf_set_field(origin, 1ull << 10, 10, en);
831d828b YZZ	519	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
831d828b YZZ	520	} else {
89a6b1aa KY	521	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
89a6b1aa KY	522	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
a24274aa	523	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
831d828b	524	}
511e6bc0	525
	526	return 0;
	527	}
a24274aa	528
f00ef863 KY	529	static int
	530	hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
	531	{
	532	union acpi_object *obj;
	533	union acpi_object obj_args[3], argv4;
	534
	535	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	536	obj_args[0].integer.value = mac_cb->mac_id;
	537	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	538	obj_args[1].integer.value = !!en;
	539
	540	argv4.type = ACPI_TYPE_PACKAGE;
	541	argv4.package.count = 2;
	542	argv4.package.elements = obj_args;
	543
	544	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
	545	hns_dsaf_acpi_dsm_uuid, 0,
	546	HNS_OP_SERDES_LP_FUNC, &argv4);
	547	if (!obj) {
	548	dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
	549	mac_cb->mac_id);
	550
	551	return -ENOTSUPP;
	552	}
	553
	554	ACPI_FREE(obj);
	555
	556	return 0;
	557	}
	558
a24274aa KY	559	struct dsaf_misc_op hns_misc_op_get(struct dsaf_device dsaf_dev)
	560	{
	561	struct dsaf_misc_op *misc_op;
	562
	563	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	564	if (!misc_op)
	565	return NULL;
	566
8413b3be KY	567	if (dev_of_node(dsaf_dev->dev)) {
	568	misc_op->cpld_set_led = hns_cpld_set_led;
	569	misc_op->cpld_reset_led = cpld_led_reset;
	570	misc_op->cpld_set_led_id = cpld_set_led_id;
	571
	572	misc_op->dsaf_reset = hns_dsaf_rst;
	573	misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
	574	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
	575	misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
	576	misc_op->ppe_srst = hns_ppe_srst_by_port;
	577	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	578
	579	misc_op->get_phy_if = hns_mac_get_phy_if;
	580	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	581
	582	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
f00ef863 KY	583	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
	584	misc_op->cpld_set_led = hns_cpld_set_led;
	585	misc_op->cpld_reset_led = cpld_led_reset;
	586	misc_op->cpld_set_led_id = cpld_set_led_id;
	587
	588	misc_op->dsaf_reset = hns_dsaf_rst_acpi;
	589	misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
	590	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
	591	misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
	592	misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
	593	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	594
	595	misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
	596	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	597
	598	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	599	} else {
	600	devm_kfree(dsaf_dev->dev, (void *)misc_op);
	601	misc_op = NULL;
8413b3be	602	}
a24274aa KY	603
	604	return (void *)misc_op;
	605	}