[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
		      u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_vaddr) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_b(mac_cb->cpld_vaddr, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	}
}

void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_vaddr)
		return;

	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

int cpld_set_led_id(struct hns_mac_cb *mac_cb,
		    enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
		return 2;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
		break;
	default:
		break;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!val) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
		       RESET_REQ_OR_DREQ);
	dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
		       RESET_REQ_OR_DREQ);
}

void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= 0x2082082 << port;
	else
		reg_val |= 0x2082082 << (dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
}

void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
				    u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= XGMAC_TRX_CORE_SRST_M << port;
	else
		reg_val |= XGMAC_TRX_CORE_SRST_M <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
}

void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val_1;
	u32 reg_val_2;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		/* there is difference between V1 and V2 in register.*/
		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
			reg_val_2  = 0x1041041 << port;
		else
			reg_val_2  = 0x2082082 << port;

		if (val == 0) {
			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
		reg_val_2 = 0x100 << dsaf_dev->reset_offset;

		if (val == 0) {
			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_reg(dsaf_dev->sc_base,
				       DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= RESET_REQ_OR_DREQ << port;
	else
		reg_val |= RESET_REQ_OR_DREQ <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
}

void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
{
	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	u32 reg_val;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (val == 0)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (val == 0)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	u32 shift;
	u32 phy_offset;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;

	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		phy_if = PHY_INTERFACE_MODE_SGMII;
	} else if (mac_id >= 0 && mac_id <= 3 &&
		   !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
		mode = dsaf_read_reg(sys_ctl_vaddr, reg);
		/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
		shift = is_ver1 ? 0 : mac_id;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	} else {
		reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
		mode = dsaf_read_reg(sys_ctl_vaddr, reg);
		/* mac_id 4, 5,---> hilink3 lane 2, 3
		 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1
		 */
		phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
		shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	}
	return phy_if;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
{
	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	 */
	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_node) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);

	return 0;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
	15	void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
	16	u16 speed, int data)
	17	{
	18	int speed_reg = 0;
	19	u8 value;
	20
	21	if (!mac_cb) {
	22	pr_err("sfp_led_opt mac_dev is null!\n");
	23	return;
	24	}
	25	if (!mac_cb->cpld_vaddr) {
	26	dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
	27	mac_cb->mac_id);
	28	return;
	29	}
	30
	31	if (speed == MAC_SPEED_10000)
	32	speed_reg = 1;
	33
	34	value = mac_cb->cpld_led_value;
	35
	36	if (link_status) {
	37	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	38	dsaf_set_field(value, DSAF_LED_SPEED_M,
	39	DSAF_LED_SPEED_S, speed_reg);
	40	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	41
	42	if (value != mac_cb->cpld_led_value) {
	43	dsaf_write_b(mac_cb->cpld_vaddr, value);
	44	mac_cb->cpld_led_value = value;
	45	}
	46	} else {
	47	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	48	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	49	}
	50	}
	51
	52	void cpld_led_reset(struct hns_mac_cb *mac_cb)
	53	{
	54	if (!mac_cb \|\| !mac_cb->cpld_vaddr)
	55	return;
	56
	57	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	58	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	59	}
	60
	61	int cpld_set_led_id(struct hns_mac_cb *mac_cb,
	62	enum hnae_led_state status)
	63	{
	64	switch (status) {
	65	case HNAE_LED_ACTIVE:
	66	mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
511e6bc0	67	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	68	CPLD_LED_ON_VALUE);
	69	dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
edc9b427	70	return 2;
511e6bc0	71	case HNAE_LED_INACTIVE:
	72	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	73	CPLD_LED_DEFAULT_VALUE);
	74	dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
	75	break;
	76	default:
	77	break;
	78	}
	79
	80	return 0;
	81	}
	82
	83	#define RESET_REQ_OR_DREQ 1
	84
	85	void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
	86	{
	87	u32 xbar_reg_addr;
	88	u32 nt_reg_addr;
	89
	90	if (!val) {
	91	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	92	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	93	} else {
	94	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	95	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	96	}
	97
	98	dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
	99	RESET_REQ_OR_DREQ);
	100	dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
	101	RESET_REQ_OR_DREQ);
	102	}
	103
	104	void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	105	{
	106	u32 reg_val = 0;
	107	u32 reg_addr;
	108
	109	if (port >= DSAF_XGE_NUM)
	110	return;
	111
	112	reg_val \|= RESET_REQ_OR_DREQ;
422c3107 YZZ	113
	114	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	115	reg_val \|= 0x2082082 << port;
	116	else
	117	reg_val \|= 0x2082082 << (dsaf_dev->reset_offset + 6);
511e6bc0	118
	119	if (val == 0)
	120	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	121	else
	122	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	123
	124	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
	125	}
	126
	127	void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
	128	u32 port, u32 val)
	129	{
	130	u32 reg_val = 0;
	131	u32 reg_addr;
	132
	133	if (port >= DSAF_XGE_NUM)
	134	return;
	135
422c3107 YZZ	136	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	137	reg_val \|= XGMAC_TRX_CORE_SRST_M << port;
	138	else
	139	reg_val \|= XGMAC_TRX_CORE_SRST_M <<
	140	(dsaf_dev->reset_offset + 6);
511e6bc0	141
	142	if (val == 0)
	143	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	144	else
	145	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	146
	147	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
	148	}
	149
	150	void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	151	{
	152	u32 reg_val_1;
	153	u32 reg_val_2;
	154
	155	if (port >= DSAF_GE_NUM)
	156	return;
	157
89a44093	158	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	159	reg_val_1 = 0x1 << port;
13ac695e S	160	/* there is difference between V1 and V2 in register.*/
	161	if (AE_IS_VER1(dsaf_dev->dsaf_ver))
	162	reg_val_2 = 0x1041041 << port;
	163	else
	164	reg_val_2 = 0x2082082 << port;
511e6bc0	165
	166	if (val == 0) {
	167	dsaf_write_reg(dsaf_dev->sc_base,
	168	DSAF_SUB_SC_GE_RESET_REQ1_REG,
	169	reg_val_1);
	170
	171	dsaf_write_reg(dsaf_dev->sc_base,
	172	DSAF_SUB_SC_GE_RESET_REQ0_REG,
	173	reg_val_2);
	174	} else {
	175	dsaf_write_reg(dsaf_dev->sc_base,
	176	DSAF_SUB_SC_GE_RESET_DREQ0_REG,
	177	reg_val_2);
	178
	179	dsaf_write_reg(dsaf_dev->sc_base,
	180	DSAF_SUB_SC_GE_RESET_DREQ1_REG,
	181	reg_val_1);
	182	}
	183	} else {
422c3107 YZZ	184	reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
422c3107 YZZ	185	reg_val_2 = 0x100 << dsaf_dev->reset_offset;
511e6bc0	186
	187	if (val == 0) {
	188	dsaf_write_reg(dsaf_dev->sc_base,
	189	DSAF_SUB_SC_GE_RESET_REQ1_REG,
	190	reg_val_1);
	191
	192	dsaf_write_reg(dsaf_dev->sc_base,
	193	DSAF_SUB_SC_PPE_RESET_REQ_REG,
	194	reg_val_2);
	195	} else {
	196	dsaf_write_reg(dsaf_dev->sc_base,
	197	DSAF_SUB_SC_GE_RESET_DREQ1_REG,
	198	reg_val_1);
	199
	200	dsaf_write_reg(dsaf_dev->sc_base,
	201	DSAF_SUB_SC_PPE_RESET_DREQ_REG,
	202	reg_val_2);
	203	}
	204	}
	205	}
	206
	207	void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	208	{
	209	u32 reg_val = 0;
	210	u32 reg_addr;
	211
422c3107 YZZ	212	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	213	reg_val \|= RESET_REQ_OR_DREQ << port;
	214	else
	215	reg_val \|= RESET_REQ_OR_DREQ <<
	216	(dsaf_dev->reset_offset + 6);
511e6bc0	217
	218	if (val == 0)
	219	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	220	else
	221	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	222
	223	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
	224	}
	225
	226	void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
	227	{
511e6bc0	228	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	229	u32 reg_val;
	230	u32 reg_addr;
	231
89a44093	232	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	233	reg_val = RESET_REQ_OR_DREQ;
	234	if (val == 0)
	235	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	236	else
	237	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	238
	239	} else {
422c3107	240	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	241
	242	if (val == 0)
	243	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	244	else
	245	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	246	}
	247
	248	dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
	249	}
	250
	251	/**
	252	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	253	* @mac_cb: mac control block
	254	* retuen phy interface
	255	*/
	256	phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
	257	{
c1203fe7 SL	258	u32 mode;
	259	u32 reg;
	260	u32 shift;
422c3107	261	u32 phy_offset;
c1203fe7	262	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
511e6bc0	263	void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
c1203fe7	264	int mac_id = mac_cb->mac_id;
511e6bc0	265	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
511e6bc0	266
422c3107	267	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	268	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107 YZZ	269	} else if (mac_id >= 0 && mac_id <= 3 &&
422c3107 YZZ	270	!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7 SL	271	reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
	272	mode = dsaf_read_reg(sys_ctl_vaddr, reg);
	273	/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
	274	shift = is_ver1 ? 0 : mac_id;
	275	if (dsaf_get_bit(mode, shift))
511e6bc0	276	phy_if = PHY_INTERFACE_MODE_XGMII;
511e6bc0	277	else
c1203fe7	278	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107	279	} else {
c1203fe7 SL	280	reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
c1203fe7 SL	281	mode = dsaf_read_reg(sys_ctl_vaddr, reg);
422c3107 YZZ	282	/* mac_id 4, 5,---> hilink3 lane 2, 3
	283	* debug port 0(6), 1(7) ---> hilink3 lane 0, 1
	284	*/
	285	phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
	286	shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
c1203fe7	287	if (dsaf_get_bit(mode, shift))
511e6bc0	288	phy_if = PHY_INTERFACE_MODE_XGMII;
c1203fe7 SL	289	else
c1203fe7 SL	290	phy_if = PHY_INTERFACE_MODE_SGMII;
511e6bc0	291	}
511e6bc0	292	return phy_if;
	293	}
	294
	295	/**
	296	* hns_mac_config_sds_loopback - set loop back for serdes
	297	* @mac_cb: mac control block
	298	* retuen 0 == success
	299	*/
	300	int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
	301	{
	302	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	303	* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	304	*/
	305	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
	306	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	307	const u8 lane_id[] = {
	308	0, /* mac 0 -> lane 0 */
	309	1, /* mac 1 -> lane 1 */
	310	2, /* mac 2 -> lane 2 */
	311	3, /* mac 3 -> lane 3 */
	312	2, /* mac 4 -> lane 2 */
	313	3, /* mac 5 -> lane 3 */
	314	0, /* mac 6 -> lane 0 */
	315	1 /* mac 7 -> lane 1 */
	316	};
	317	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	318	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	319
	320	int sfp_prsnt;
	321	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	322
	323	if (!mac_cb->phy_node) {
	324	if (ret)
	325	pr_info("please confirm sfp is present or not\n");
	326	else
	327	if (!sfp_prsnt)
	328	pr_info("no sfp in this eth\n");
	329	}
	330
	331	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	332
	333	return 0;
	334	}