[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

enum _dsm_op_index {
	HNS_OP_RESET_FUNC               = 0x1,
	HNS_OP_SERDES_LP_FUNC           = 0x2,
	HNS_OP_LED_SET_FUNC             = 0x3,
	HNS_OP_GET_PORT_TYPE_FUNC       = 0x4,
	HNS_OP_GET_SFP_STAT_FUNC        = 0x5,
};

enum _dsm_rst_type {
	HNS_DSAF_RESET_FUNC     = 0x1,
	HNS_PPE_RESET_FUNC      = 0x2,
	HNS_XGE_CORE_RESET_FUNC = 0x3,
	HNS_XGE_RESET_FUNC      = 0x4,
	HNS_GE_RESET_FUNC       = 0x5,
};

const u8 hns_dsaf_acpi_dsm_uuid[] = {
	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
};

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
			     u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_ctrl) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_syscon(mac_cb->cpld_ctrl,
					  mac_cb->cpld_ctrl_reg, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  CPLD_LED_DEFAULT_VALUE);
		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	}
}

static void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_ctrl)
		return;

	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
			  CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
			   enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value =
			dsaf_read_syscon(mac_cb->cpld_ctrl,
					 mac_cb->cpld_ctrl_reg);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		return 2;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	default:
		break;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
				       u32 port_type, u32 port, u32 val)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = port_type;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = port;
	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	obj_args[2].integer.value = val;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 3;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	if (!obj) {
		dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
			 port_type, port);
		return;
	}

	ACPI_FREE(obj);
}

static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!dereset) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_DSAF_RESET_FUNC,
				   0, dereset);
}

static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				      bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;
	reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
					   u32 port, bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= XGMAC_TRX_CORE_SRST_M
		<< dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void
hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
				    u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_XGE_CORE_RESET_FUNC, port, dereset);
}

static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				     bool dereset)
{
	u32 reg_val_1;
	u32 reg_val_2;
	u32 port_rst_off;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
		/* there is difference between V1 and V2 in register.*/
		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
			reg_val_2  = 0x1041041 << port_rst_off;
		else
			reg_val_2  = 0x2082082 << port_rst_off;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
		reg_val_2 = 0x100 << dsaf_dev->reset_offset;

		if (!dereset) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
					  u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_GE_RESET_FUNC, port, dereset);
}

static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
				 bool dereset)
{
	u32 reg_val = 0;
	u32 reg_addr;

	reg_val |= RESET_REQ_OR_DREQ <<	dsaf_dev->mac_cb[port]->port_rst_off;

	if (!dereset)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

static void
hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
{
	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
				   HNS_PPE_RESET_FUNC, port, dereset);
}

static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
{
	u32 reg_val;
	u32 reg_addr;

	if (!(dev_of_node(dsaf_dev->dev)))
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (!dereset)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (!dereset)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if;

	if (is_ver1) {
		if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
			return PHY_INTERFACE_MODE_SGMII;

		if (mac_id >= 0 && mac_id <= 3)
			reg = HNS_MAC_HILINK4_REG;
		else
			reg = HNS_MAC_HILINK3_REG;
	} else{
		if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
			reg = HNS_MAC_HILINK4V2_REG;
		else
			reg = HNS_MAC_HILINK3V2_REG;
	}

	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
		phy_if = PHY_INTERFACE_MODE_XGMII;
	else
		phy_if = PHY_INTERFACE_MODE_SGMII;

	return phy_if;
}

static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
{
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	union acpi_object *obj;
	union acpi_object obj_args, argv4;

	obj_args.integer.type = ACPI_TYPE_INTEGER;
	obj_args.integer.value = mac_cb->mac_id;

	argv4.type = ACPI_TYPE_PACKAGE,
	argv4.package.count = 1,
	argv4.package.elements = &obj_args,

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_GET_PORT_TYPE_FUNC, &argv4);

	if (!obj || obj->type != ACPI_TYPE_INTEGER)
		return phy_if;

	phy_if = obj->integer.value ?
		PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;

	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);

	ACPI_FREE(obj);

	return phy_if;
}

int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
{
	if (!mac_cb->cpld_ctrl)
		return -ENODEV;

	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
					+ MAC_SFP_PORT_OFFSET);

	return 0;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
{
	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	 */
	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_dev) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
	}

	return 0;
}

static int
hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
{
	union acpi_object *obj;
	union acpi_object obj_args[3], argv4;

	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	obj_args[0].integer.value = mac_cb->mac_id;
	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	obj_args[1].integer.value = !!en;

	argv4.type = ACPI_TYPE_PACKAGE;
	argv4.package.count = 2;
	argv4.package.elements = obj_args;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
				hns_dsaf_acpi_dsm_uuid, 0,
				HNS_OP_SERDES_LP_FUNC, &argv4);
	if (!obj) {
		dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
			 mac_cb->mac_id);

		return -ENOTSUPP;
	}

	ACPI_FREE(obj);

	return 0;
}

struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
{
	struct dsaf_misc_op *misc_op;

	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	if (!misc_op)
		return NULL;

	if (dev_of_node(dsaf_dev->dev)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
		misc_op->ppe_srst = hns_ppe_srst_by_port;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
		misc_op->cpld_set_led = hns_cpld_set_led;
		misc_op->cpld_reset_led = cpld_led_reset;
		misc_op->cpld_set_led_id = cpld_set_led_id;

		misc_op->dsaf_reset = hns_dsaf_rst_acpi;
		misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
		misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
		misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
		misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
		misc_op->ppe_comm_srst = hns_ppe_com_srst;

		misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
		misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;

		misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	} else {
		devm_kfree(dsaf_dev->dev, (void *)misc_op);
		misc_op = NULL;
	}

	return (void *)misc_op;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
f00ef863 KY	15	enum _dsm_op_index {
	16	HNS_OP_RESET_FUNC = 0x1,
	17	HNS_OP_SERDES_LP_FUNC = 0x2,
	18	HNS_OP_LED_SET_FUNC = 0x3,
	19	HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
	20	HNS_OP_GET_SFP_STAT_FUNC = 0x5,
	21	};
	22
	23	enum _dsm_rst_type {
	24	HNS_DSAF_RESET_FUNC = 0x1,
	25	HNS_PPE_RESET_FUNC = 0x2,
	26	HNS_XGE_CORE_RESET_FUNC = 0x3,
	27	HNS_XGE_RESET_FUNC = 0x4,
	28	HNS_GE_RESET_FUNC = 0x5,
	29	};
	30
	31	const u8 hns_dsaf_acpi_dsm_uuid[] = {
	32	0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
	33	0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
	34	};
	35
831d828b YZZ	36	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	37	{
	38	if (dsaf_dev->sub_ctrl)
	39	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	40	else
	41	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	42	}
	43
	44	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	45	{
	46	u32 ret;
	47
	48	if (dsaf_dev->sub_ctrl)
	49	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	50	else
	51	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	52
	53	return ret;
	54	}
	55
a24274aa KY	56	static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
a24274aa KY	57	u16 speed, int data)
511e6bc0	58	{
	59	int speed_reg = 0;
	60	u8 value;
	61
	62	if (!mac_cb) {
	63	pr_err("sfp_led_opt mac_dev is null!\n");
	64	return;
	65	}
31d4446d YZZ	66	if (!mac_cb->cpld_ctrl) {
31d4446d YZZ	67	dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
511e6bc0	68	mac_cb->mac_id);
	69	return;
	70	}
	71
	72	if (speed == MAC_SPEED_10000)
	73	speed_reg = 1;
	74
	75	value = mac_cb->cpld_led_value;
	76
	77	if (link_status) {
	78	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	79	dsaf_set_field(value, DSAF_LED_SPEED_M,
	80	DSAF_LED_SPEED_S, speed_reg);
	81	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	82
	83	if (value != mac_cb->cpld_led_value) {
31d4446d YZZ	84	dsaf_write_syscon(mac_cb->cpld_ctrl,
31d4446d YZZ	85	mac_cb->cpld_ctrl_reg, value);
511e6bc0	86	mac_cb->cpld_led_value = value;
	87	}
	88	} else {
31d4446d YZZ	89	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	90	CPLD_LED_DEFAULT_VALUE);
511e6bc0	91	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	92	}
	93	}
	94
a24274aa	95	static void cpld_led_reset(struct hns_mac_cb *mac_cb)
511e6bc0	96	{
31d4446d	97	if (!mac_cb \|\| !mac_cb->cpld_ctrl)
511e6bc0	98	return;
511e6bc0	99
31d4446d YZZ	100	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	101	CPLD_LED_DEFAULT_VALUE);
511e6bc0	102	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	103	}
	104
a24274aa KY	105	static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
a24274aa KY	106	enum hnae_led_state status)
511e6bc0	107	{
	108	switch (status) {
	109	case HNAE_LED_ACTIVE:
31d4446d YZZ	110	mac_cb->cpld_led_value =
	111	dsaf_read_syscon(mac_cb->cpld_ctrl,
	112	mac_cb->cpld_ctrl_reg);
511e6bc0	113	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
511e6bc0	114	CPLD_LED_ON_VALUE);
31d4446d YZZ	115	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	116	mac_cb->cpld_led_value);
edc9b427	117	return 2;
511e6bc0	118	case HNAE_LED_INACTIVE:
	119	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	120	CPLD_LED_DEFAULT_VALUE);
31d4446d YZZ	121	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	122	mac_cb->cpld_led_value);
511e6bc0	123	break;
	124	default:
	125	break;
	126	}
	127
	128	return 0;
	129	}
	130
	131	#define RESET_REQ_OR_DREQ 1
	132
f00ef863 KY	133	static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
	134	u32 port_type, u32 port, u32 val)
	135	{
	136	union acpi_object *obj;
	137	union acpi_object obj_args[3], argv4;
	138
	139	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	140	obj_args[0].integer.value = port_type;
	141	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	142	obj_args[1].integer.value = port;
	143	obj_args[2].integer.type = ACPI_TYPE_INTEGER;
	144	obj_args[2].integer.value = val;
	145
	146	argv4.type = ACPI_TYPE_PACKAGE;
	147	argv4.package.count = 3;
	148	argv4.package.elements = obj_args;
	149
	150	obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
	151	hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
	152	if (!obj) {
	153	dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
	154	port_type, port);
	155	return;
	156	}
	157
	158	ACPI_FREE(obj);
	159	}
	160
a24274aa	161	static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	162	{
	163	u32 xbar_reg_addr;
	164	u32 nt_reg_addr;
	165
a24274aa	166	if (!dereset) {
511e6bc0	167	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	168	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	169	} else {
	170	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	171	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	172	}
	173
831d828b YZZ	174	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	175	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	176	}
511e6bc0	177
f00ef863 KY	178	static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
	179	{
	180	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	181	HNS_DSAF_RESET_FUNC,
	182	0, dereset);
	183	}
	184
a24274aa KY	185	static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	186	bool dereset)
511e6bc0	187	{
	188	u32 reg_val = 0;
	189	u32 reg_addr;
	190
	191	if (port >= DSAF_XGE_NUM)
	192	return;
	193
	194	reg_val \|= RESET_REQ_OR_DREQ;
850bfa3b	195	reg_val \|= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	196
a24274aa	197	if (!dereset)
511e6bc0	198	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	199	else
	200	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	201
831d828b	202	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	203	}
511e6bc0	204
f00ef863 KY	205	static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	206	u32 port, bool dereset)
	207	{
	208	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	209	HNS_XGE_RESET_FUNC, port, dereset);
	210	}
	211
a24274aa KY	212	static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
a24274aa KY	213	u32 port, bool dereset)
511e6bc0	214	{
	215	u32 reg_val = 0;
	216	u32 reg_addr;
	217
	218	if (port >= DSAF_XGE_NUM)
	219	return;
	220
850bfa3b YZZ	221	reg_val \|= XGMAC_TRX_CORE_SRST_M
850bfa3b YZZ	222	<< dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	223
a24274aa	224	if (!dereset)
511e6bc0	225	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	226	else
	227	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	228
831d828b	229	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	230	}
511e6bc0	231
f00ef863 KY	232	static void
	233	hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	234	u32 port, bool dereset)
	235	{
	236	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	237	HNS_XGE_CORE_RESET_FUNC, port, dereset);
	238	}
	239
a24274aa KY	240	static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	241	bool dereset)
511e6bc0	242	{
	243	u32 reg_val_1;
	244	u32 reg_val_2;
850bfa3b	245	u32 port_rst_off;
511e6bc0	246
	247	if (port >= DSAF_GE_NUM)
	248	return;
	249
89a44093	250	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	251	reg_val_1 = 0x1 << port;
850bfa3b	252	port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
13ac695e S	253	/* there is difference between V1 and V2 in register.*/
13ac695e S	254	if (AE_IS_VER1(dsaf_dev->dsaf_ver))
850bfa3b	255	reg_val_2 = 0x1041041 << port_rst_off;
13ac695e	256	else
850bfa3b	257	reg_val_2 = 0x2082082 << port_rst_off;
511e6bc0	258
a24274aa	259	if (!dereset) {
831d828b	260	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	261	reg_val_1);
511e6bc0	262
831d828b	263	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	264	reg_val_2);
511e6bc0	265	} else {
831d828b	266	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	267	reg_val_2);
511e6bc0	268
831d828b	269	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	270	reg_val_1);
	271	}
	272	} else {
422c3107 YZZ	273	reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
422c3107 YZZ	274	reg_val_2 = 0x100 << dsaf_dev->reset_offset;
511e6bc0	275
a24274aa	276	if (!dereset) {
831d828b	277	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	278	reg_val_1);
511e6bc0	279
831d828b	280	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	281	reg_val_2);
511e6bc0	282	} else {
831d828b	283	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	284	reg_val_1);
511e6bc0	285
831d828b	286	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	287	reg_val_2);
	288	}
	289	}
	290	}
	291
f00ef863 KY	292	static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
	293	u32 port, bool dereset)
	294	{
	295	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	296	HNS_GE_RESET_FUNC, port, dereset);
	297	}
	298
a24274aa KY	299	static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
a24274aa KY	300	bool dereset)
511e6bc0	301	{
	302	u32 reg_val = 0;
	303	u32 reg_addr;
	304
850bfa3b	305	reg_val \|= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	306
a24274aa	307	if (!dereset)
511e6bc0	308	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	309	else
	310	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	311
831d828b	312	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	313	}
511e6bc0	314
f00ef863 KY	315	static void
	316	hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
	317	{
	318	hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
	319	HNS_PPE_RESET_FUNC, port, dereset);
	320	}
	321
a24274aa	322	static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
511e6bc0	323	{
511e6bc0	324	u32 reg_val;
	325	u32 reg_addr;
	326
f00ef863 KY	327	if (!(dev_of_node(dsaf_dev->dev)))
	328	return;
	329
89a44093	330	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	331	reg_val = RESET_REQ_OR_DREQ;
a24274aa	332	if (!dereset)
511e6bc0	333	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	334	else
	335	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	336
	337	} else {
422c3107	338	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	339
a24274aa	340	if (!dereset)
511e6bc0	341	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	342	else
	343	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	344	}
	345
831d828b	346	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	347	}
	348
	349	/**
	350	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	351	* @mac_cb: mac control block
	352	* retuen phy interface
	353	*/
a24274aa	354	static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
511e6bc0	355	{
c1203fe7 SL	356	u32 mode;
c1203fe7 SL	357	u32 reg;
c1203fe7	358	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	359	int mac_id = mac_cb->mac_id;
0d768fc6	360	phy_interface_t phy_if;
511e6bc0	361
0d768fc6 YZZ	362	if (is_ver1) {
	363	if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
	364	return PHY_INTERFACE_MODE_SGMII;
	365
	366	if (mac_id >= 0 && mac_id <= 3)
	367	reg = HNS_MAC_HILINK4_REG;
511e6bc0	368	else
0d768fc6 YZZ	369	reg = HNS_MAC_HILINK3_REG;
	370	} else{
	371	if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
	372	reg = HNS_MAC_HILINK4V2_REG;
c1203fe7	373	else
0d768fc6	374	reg = HNS_MAC_HILINK3V2_REG;
511e6bc0	375	}
0d768fc6 YZZ	376
	377	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
	378	if (dsaf_get_bit(mode, mac_cb->port_mode_off))
	379	phy_if = PHY_INTERFACE_MODE_XGMII;
	380	else
	381	phy_if = PHY_INTERFACE_MODE_SGMII;
	382
511e6bc0	383	return phy_if;
	384	}
	385
f00ef863 KY	386	static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
	387	{
	388	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
	389	union acpi_object *obj;
	390	union acpi_object obj_args, argv4;
	391
	392	obj_args.integer.type = ACPI_TYPE_INTEGER;
	393	obj_args.integer.value = mac_cb->mac_id;
	394
	395	argv4.type = ACPI_TYPE_PACKAGE,
	396	argv4.package.count = 1,
	397	argv4.package.elements = &obj_args,
	398
	399	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
	400	hns_dsaf_acpi_dsm_uuid, 0,
	401	HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
	402
	403	if (!obj \|\| obj->type != ACPI_TYPE_INTEGER)
	404	return phy_if;
	405
	406	phy_if = obj->integer.value ?
	407	PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
	408
	409	dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
	410
	411	ACPI_FREE(obj);
	412
	413	return phy_if;
	414	}
	415
31d4446d YZZ	416	int hns_mac_get_sfp_prsnt(struct hns_mac_cb mac_cb, int sfp_prsnt)
	417	{
	418	if (!mac_cb->cpld_ctrl)
	419	return -ENODEV;
	420
	421	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
	422	+ MAC_SFP_PORT_OFFSET);
	423
	424	return 0;
	425	}
	426
511e6bc0	427	/**
	428	* hns_mac_config_sds_loopback - set loop back for serdes
	429	* @mac_cb: mac control block
	430	* retuen 0 == success
	431	*/
a24274aa	432	static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
511e6bc0	433	{
	434	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	435	* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	436	*/
	437	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
	438	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	439	const u8 lane_id[] = {
	440	0, /* mac 0 -> lane 0 */
	441	1, /* mac 1 -> lane 1 */
	442	2, /* mac 2 -> lane 2 */
	443	3, /* mac 3 -> lane 3 */
	444	2, /* mac 4 -> lane 2 */
	445	3, /* mac 5 -> lane 3 */
	446	0, /* mac 6 -> lane 0 */
	447	1 /* mac 7 -> lane 1 */
	448	};
	449	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	450	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	451
	452	int sfp_prsnt;
	453	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	454
652d39b0	455	if (!mac_cb->phy_dev) {
511e6bc0	456	if (ret)
	457	pr_info("please confirm sfp is present or not\n");
	458	else
	459	if (!sfp_prsnt)
	460	pr_info("no sfp in this eth\n");
	461	}
	462
831d828b YZZ	463	if (mac_cb->serdes_ctrl) {
	464	u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
	465
a24274aa	466	dsaf_set_field(origin, 1ull << 10, 10, en);
831d828b YZZ	467	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
831d828b YZZ	468	} else {
a24274aa	469	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
831d828b	470	}
511e6bc0	471
	472	return 0;
	473	}
a24274aa	474
f00ef863 KY	475	static int
	476	hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
	477	{
	478	union acpi_object *obj;
	479	union acpi_object obj_args[3], argv4;
	480
	481	obj_args[0].integer.type = ACPI_TYPE_INTEGER;
	482	obj_args[0].integer.value = mac_cb->mac_id;
	483	obj_args[1].integer.type = ACPI_TYPE_INTEGER;
	484	obj_args[1].integer.value = !!en;
	485
	486	argv4.type = ACPI_TYPE_PACKAGE;
	487	argv4.package.count = 2;
	488	argv4.package.elements = obj_args;
	489
	490	obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
	491	hns_dsaf_acpi_dsm_uuid, 0,
	492	HNS_OP_SERDES_LP_FUNC, &argv4);
	493	if (!obj) {
	494	dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
	495	mac_cb->mac_id);
	496
	497	return -ENOTSUPP;
	498	}
	499
	500	ACPI_FREE(obj);
	501
	502	return 0;
	503	}
	504
a24274aa KY	505	struct dsaf_misc_op hns_misc_op_get(struct dsaf_device dsaf_dev)
	506	{
	507	struct dsaf_misc_op *misc_op;
	508
	509	misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
	510	if (!misc_op)
	511	return NULL;
	512
8413b3be KY	513	if (dev_of_node(dsaf_dev->dev)) {
	514	misc_op->cpld_set_led = hns_cpld_set_led;
	515	misc_op->cpld_reset_led = cpld_led_reset;
	516	misc_op->cpld_set_led_id = cpld_set_led_id;
	517
	518	misc_op->dsaf_reset = hns_dsaf_rst;
	519	misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
	520	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
	521	misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
	522	misc_op->ppe_srst = hns_ppe_srst_by_port;
	523	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	524
	525	misc_op->get_phy_if = hns_mac_get_phy_if;
	526	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	527
	528	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
f00ef863 KY	529	} else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
	530	misc_op->cpld_set_led = hns_cpld_set_led;
	531	misc_op->cpld_reset_led = cpld_led_reset;
	532	misc_op->cpld_set_led_id = cpld_set_led_id;
	533
	534	misc_op->dsaf_reset = hns_dsaf_rst_acpi;
	535	misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
	536	misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
	537	misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
	538	misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
	539	misc_op->ppe_comm_srst = hns_ppe_com_srst;
	540
	541	misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
	542	misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
	543
	544	misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
	545	} else {
	546	devm_kfree(dsaf_dev->dev, (void *)misc_op);
	547	misc_op = NULL;
8413b3be	548	}
a24274aa KY	549
	550	return (void *)misc_op;
	551	}