[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
		      u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_vaddr) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_b(mac_cb->cpld_vaddr, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	}
}

void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_vaddr)
		return;

	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

int cpld_set_led_id(struct hns_mac_cb *mac_cb,
		    enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
		return 2;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
		break;
	default:
		break;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!val) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= 0x2082082 << port;
	else
		reg_val |= 0x2082082 << (dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
				    u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= XGMAC_TRX_CORE_SRST_M << port;
	else
		reg_val |= XGMAC_TRX_CORE_SRST_M <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val_1;
	u32 reg_val_2;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		/* there is difference between V1 and V2 in register.*/
		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
			reg_val_2  = 0x1041041 << port;
		else
			reg_val_2  = 0x2082082 << port;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
		reg_val_2 = 0x100 << dsaf_dev->reset_offset;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
		reg_val |= RESET_REQ_OR_DREQ << port;
	else
		reg_val |= RESET_REQ_OR_DREQ <<
			(dsaf_dev->reset_offset + 6);

	if (val == 0)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
{
	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	u32 reg_val;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (val == 0)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (val == 0)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	u32 shift;
	u32 phy_offset;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;

	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		phy_if = PHY_INTERFACE_MODE_SGMII;
	} else if (mac_id >= 0 && mac_id <= 3 &&
		   !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
		shift = is_ver1 ? 0 : mac_id;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	} else {
		reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 4, 5,---> hilink3 lane 2, 3
		 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1
		 */
		phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
		shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	}
	return phy_if;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
{
	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	 */
	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_node) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, !!en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	}

	return 0;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
831d828b YZZ	15	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	16	{
	17	if (dsaf_dev->sub_ctrl)
	18	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	19	else
	20	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	21	}
	22
	23	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	24	{
	25	u32 ret;
	26
	27	if (dsaf_dev->sub_ctrl)
	28	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	29	else
	30	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	31
	32	return ret;
	33	}
	34
511e6bc0	35	void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
	36	u16 speed, int data)
	37	{
	38	int speed_reg = 0;
	39	u8 value;
	40
	41	if (!mac_cb) {
	42	pr_err("sfp_led_opt mac_dev is null!\n");
	43	return;
	44	}
	45	if (!mac_cb->cpld_vaddr) {
	46	dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
	47	mac_cb->mac_id);
	48	return;
	49	}
	50
	51	if (speed == MAC_SPEED_10000)
	52	speed_reg = 1;
	53
	54	value = mac_cb->cpld_led_value;
	55
	56	if (link_status) {
	57	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	58	dsaf_set_field(value, DSAF_LED_SPEED_M,
	59	DSAF_LED_SPEED_S, speed_reg);
	60	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	61
	62	if (value != mac_cb->cpld_led_value) {
	63	dsaf_write_b(mac_cb->cpld_vaddr, value);
	64	mac_cb->cpld_led_value = value;
	65	}
	66	} else {
	67	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	68	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	69	}
	70	}
	71
	72	void cpld_led_reset(struct hns_mac_cb *mac_cb)
	73	{
	74	if (!mac_cb \|\| !mac_cb->cpld_vaddr)
	75	return;
	76
	77	dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
	78	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	79	}
	80
	81	int cpld_set_led_id(struct hns_mac_cb *mac_cb,
	82	enum hnae_led_state status)
	83	{
	84	switch (status) {
	85	case HNAE_LED_ACTIVE:
	86	mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
511e6bc0	87	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	88	CPLD_LED_ON_VALUE);
	89	dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
edc9b427	90	return 2;
511e6bc0	91	case HNAE_LED_INACTIVE:
	92	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	93	CPLD_LED_DEFAULT_VALUE);
	94	dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
	95	break;
	96	default:
	97	break;
	98	}
	99
	100	return 0;
	101	}
	102
	103	#define RESET_REQ_OR_DREQ 1
	104
	105	void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
	106	{
	107	u32 xbar_reg_addr;
	108	u32 nt_reg_addr;
	109
	110	if (!val) {
	111	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	112	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	113	} else {
	114	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	115	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	116	}
	117
831d828b YZZ	118	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	119	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	120	}
	121
	122	void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	123	{
	124	u32 reg_val = 0;
	125	u32 reg_addr;
	126
	127	if (port >= DSAF_XGE_NUM)
	128	return;
	129
	130	reg_val \|= RESET_REQ_OR_DREQ;
422c3107 YZZ	131
	132	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	133	reg_val \|= 0x2082082 << port;
	134	else
	135	reg_val \|= 0x2082082 << (dsaf_dev->reset_offset + 6);
511e6bc0	136
	137	if (val == 0)
	138	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	139	else
	140	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	141
831d828b	142	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	143	}
	144
	145	void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
	146	u32 port, u32 val)
	147	{
	148	u32 reg_val = 0;
	149	u32 reg_addr;
	150
	151	if (port >= DSAF_XGE_NUM)
	152	return;
	153
422c3107 YZZ	154	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	155	reg_val \|= XGMAC_TRX_CORE_SRST_M << port;
	156	else
	157	reg_val \|= XGMAC_TRX_CORE_SRST_M <<
	158	(dsaf_dev->reset_offset + 6);
511e6bc0	159
	160	if (val == 0)
	161	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	162	else
	163	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	164
831d828b	165	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	166	}
	167
	168	void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	169	{
	170	u32 reg_val_1;
	171	u32 reg_val_2;
	172
	173	if (port >= DSAF_GE_NUM)
	174	return;
	175
89a44093	176	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	177	reg_val_1 = 0x1 << port;
13ac695e S	178	/* there is difference between V1 and V2 in register.*/
	179	if (AE_IS_VER1(dsaf_dev->dsaf_ver))
	180	reg_val_2 = 0x1041041 << port;
	181	else
	182	reg_val_2 = 0x2082082 << port;
511e6bc0	183
511e6bc0	184	if (val == 0) {
831d828b	185	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	186	reg_val_1);
511e6bc0	187
831d828b	188	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	189	reg_val_2);
511e6bc0	190	} else {
831d828b	191	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	192	reg_val_2);
511e6bc0	193
831d828b	194	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	195	reg_val_1);
	196	}
	197	} else {
422c3107 YZZ	198	reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
422c3107 YZZ	199	reg_val_2 = 0x100 << dsaf_dev->reset_offset;
511e6bc0	200
511e6bc0	201	if (val == 0) {
831d828b	202	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	203	reg_val_1);
511e6bc0	204
831d828b	205	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	206	reg_val_2);
511e6bc0	207	} else {
831d828b	208	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	209	reg_val_1);
511e6bc0	210
831d828b	211	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	212	reg_val_2);
	213	}
	214	}
	215	}
	216
	217	void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	218	{
	219	u32 reg_val = 0;
	220	u32 reg_addr;
	221
422c3107 YZZ	222	if (!HNS_DSAF_IS_DEBUG(dsaf_dev))
	223	reg_val \|= RESET_REQ_OR_DREQ << port;
	224	else
	225	reg_val \|= RESET_REQ_OR_DREQ <<
	226	(dsaf_dev->reset_offset + 6);
511e6bc0	227
	228	if (val == 0)
	229	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	230	else
	231	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	232
831d828b	233	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	234	}
	235
	236	void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
	237	{
511e6bc0	238	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	239	u32 reg_val;
	240	u32 reg_addr;
	241
89a44093	242	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	243	reg_val = RESET_REQ_OR_DREQ;
	244	if (val == 0)
	245	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	246	else
	247	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	248
	249	} else {
422c3107	250	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	251
	252	if (val == 0)
	253	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	254	else
	255	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	256	}
	257
831d828b	258	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	259	}
	260
	261	/**
	262	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	263	* @mac_cb: mac control block
	264	* retuen phy interface
	265	*/
	266	phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
	267	{
c1203fe7 SL	268	u32 mode;
	269	u32 reg;
	270	u32 shift;
422c3107	271	u32 phy_offset;
c1203fe7	272	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	273	int mac_id = mac_cb->mac_id;
511e6bc0	274	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
511e6bc0	275
422c3107	276	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	277	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107 YZZ	278	} else if (mac_id >= 0 && mac_id <= 3 &&
422c3107 YZZ	279	!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	280	reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
831d828b	281	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
c1203fe7 SL	282	/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
	283	shift = is_ver1 ? 0 : mac_id;
	284	if (dsaf_get_bit(mode, shift))
511e6bc0	285	phy_if = PHY_INTERFACE_MODE_XGMII;
511e6bc0	286	else
c1203fe7	287	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107	288	} else {
c1203fe7	289	reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
831d828b	290	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
422c3107 YZZ	291	/* mac_id 4, 5,---> hilink3 lane 2, 3
	292	* debug port 0(6), 1(7) ---> hilink3 lane 0, 1
	293	*/
	294	phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
	295	shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
c1203fe7	296	if (dsaf_get_bit(mode, shift))
511e6bc0	297	phy_if = PHY_INTERFACE_MODE_XGMII;
c1203fe7 SL	298	else
c1203fe7 SL	299	phy_if = PHY_INTERFACE_MODE_SGMII;
511e6bc0	300	}
511e6bc0	301	return phy_if;
	302	}
	303
	304	/**
	305	* hns_mac_config_sds_loopback - set loop back for serdes
	306	* @mac_cb: mac control block
	307	* retuen 0 == success
	308	*/
	309	int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
	310	{
	311	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	312	* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	313	*/
	314	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
	315	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	316	const u8 lane_id[] = {
	317	0, /* mac 0 -> lane 0 */
	318	1, /* mac 1 -> lane 1 */
	319	2, /* mac 2 -> lane 2 */
	320	3, /* mac 3 -> lane 3 */
	321	2, /* mac 4 -> lane 2 */
	322	3, /* mac 5 -> lane 3 */
	323	0, /* mac 6 -> lane 0 */
	324	1 /* mac 7 -> lane 1 */
	325	};
	326	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	327	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	328
	329	int sfp_prsnt;
	330	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	331
	332	if (!mac_cb->phy_node) {
	333	if (ret)
	334	pr_info("please confirm sfp is present or not\n");
	335	else
	336	if (!sfp_prsnt)
	337	pr_info("no sfp in this eth\n");
	338	}
	339
831d828b YZZ	340	if (mac_cb->serdes_ctrl) {
	341	u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
	342
	343	dsaf_set_field(origin, 1ull << 10, 10, !!en);
	344	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	345	} else {
	346	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	347	}
511e6bc0	348
	349	return 0;
	350	}