[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns / hns_dsaf_misc.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "hns_dsaf_mac.h"
#include "hns_dsaf_misc.h"
#include "hns_dsaf_ppe.h"
#include "hns_dsaf_reg.h"

static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
{
	if (dsaf_dev->sub_ctrl)
		dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	else
		dsaf_write_reg(dsaf_dev->sc_base, reg, val);
}

static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
{
	u32 ret;

	if (dsaf_dev->sub_ctrl)
		ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	else
		ret = dsaf_read_reg(dsaf_dev->sc_base, reg);

	return ret;
}

void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
		      u16 speed, int data)
{
	int speed_reg = 0;
	u8 value;

	if (!mac_cb) {
		pr_err("sfp_led_opt mac_dev is null!\n");
		return;
	}
	if (!mac_cb->cpld_ctrl) {
		dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
			mac_cb->mac_id);
		return;
	}

	if (speed == MAC_SPEED_10000)
		speed_reg = 1;

	value = mac_cb->cpld_led_value;

	if (link_status) {
		dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
		dsaf_set_field(value, DSAF_LED_SPEED_M,
			       DSAF_LED_SPEED_S, speed_reg);
		dsaf_set_bit(value, DSAF_LED_DATA_B, data);

		if (value != mac_cb->cpld_led_value) {
			dsaf_write_syscon(mac_cb->cpld_ctrl,
					  mac_cb->cpld_ctrl_reg, value);
			mac_cb->cpld_led_value = value;
		}
	} else {
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  CPLD_LED_DEFAULT_VALUE);
		mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	}
}

void cpld_led_reset(struct hns_mac_cb *mac_cb)
{
	if (!mac_cb || !mac_cb->cpld_ctrl)
		return;

	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
			  CPLD_LED_DEFAULT_VALUE);
	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
}

int cpld_set_led_id(struct hns_mac_cb *mac_cb,
		    enum hnae_led_state status)
{
	switch (status) {
	case HNAE_LED_ACTIVE:
		mac_cb->cpld_led_value =
			dsaf_read_syscon(mac_cb->cpld_ctrl,
					 mac_cb->cpld_ctrl_reg);
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_ON_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		return 2;
	case HNAE_LED_INACTIVE:
		dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
			     CPLD_LED_DEFAULT_VALUE);
		dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
				  mac_cb->cpld_led_value);
		break;
	default:
		break;
	}

	return 0;
}

#define RESET_REQ_OR_DREQ 1

void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
{
	u32 xbar_reg_addr;
	u32 nt_reg_addr;

	if (!val) {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	} else {
		xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
		nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
}

void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= RESET_REQ_OR_DREQ;
	reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
				    u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	if (port >= DSAF_XGE_NUM)
		return;

	reg_val |= XGMAC_TRX_CORE_SRST_M
		<< dsaf_dev->mac_cb[port]->port_rst_off;

	if (val == 0)
		reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val_1;
	u32 reg_val_2;
	u32 port_rst_off;

	if (port >= DSAF_GE_NUM)
		return;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val_1  = 0x1 << port;
		port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
		/* there is difference between V1 and V2 in register.*/
		if (AE_IS_VER1(dsaf_dev->dsaf_ver))
			reg_val_2  = 0x1041041 << port_rst_off;
		else
			reg_val_2  = 0x2082082 << port_rst_off;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
				       reg_val_2);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);
		}
	} else {
		reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
		reg_val_2 = 0x100 << dsaf_dev->reset_offset;

		if (val == 0) {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
				       reg_val_2);
		} else {
			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
				       reg_val_1);

			dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
				       reg_val_2);
		}
	}
}

void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
{
	u32 reg_val = 0;
	u32 reg_addr;

	reg_val |= RESET_REQ_OR_DREQ <<	dsaf_dev->mac_cb[port]->port_rst_off;

	if (val == 0)
		reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	else
		reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
{
	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	u32 reg_val;
	u32 reg_addr;

	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
		reg_val = RESET_REQ_OR_DREQ;
		if (val == 0)
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;

	} else {
		reg_val = 0x100 << dsaf_dev->reset_offset;

		if (val == 0)
			reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
		else
			reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	}

	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
}

/**
 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
 * @mac_cb: mac control block
 * retuen phy interface
 */
phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
{
	u32 mode;
	u32 reg;
	u32 shift;
	u32 phy_offset;
	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
	int mac_id = mac_cb->mac_id;
	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;

	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		phy_if = PHY_INTERFACE_MODE_SGMII;
	} else if (mac_id >= 0 && mac_id <= 3 &&
		   !HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
		reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
		shift = is_ver1 ? 0 : mac_id;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	} else {
		reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
		mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
		/* mac_id 4, 5,---> hilink3 lane 2, 3
		 * debug port 0(6), 1(7) ---> hilink3 lane 0, 1
		 */
		phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
		shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
		if (dsaf_get_bit(mode, shift))
			phy_if = PHY_INTERFACE_MODE_XGMII;
		else
			phy_if = PHY_INTERFACE_MODE_SGMII;
	}
	return phy_if;
}

int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
{
	if (!mac_cb->cpld_ctrl)
		return -ENODEV;

	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
					+ MAC_SFP_PORT_OFFSET);

	return 0;
}

/**
 * hns_mac_config_sds_loopback - set loop back for serdes
 * @mac_cb: mac control block
 * retuen 0 == success
 */
int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
{
	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	 * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	 */
	u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
		       (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	const u8 lane_id[] = {
		0,	/* mac 0 -> lane 0 */
		1,	/* mac 1 -> lane 1 */
		2,	/* mac 2 -> lane 2 */
		3,	/* mac 3 -> lane 3 */
		2,	/* mac 4 -> lane 2 */
		3,	/* mac 5 -> lane 3 */
		0,	/* mac 6 -> lane 0 */
		1	/* mac 7 -> lane 1 */
	};
#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);

	int sfp_prsnt;
	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);

	if (!mac_cb->phy_node) {
		if (ret)
			pr_info("please confirm sfp is present or not\n");
		else
			if (!sfp_prsnt)
				pr_info("no sfp in this eth\n");
	}

	if (mac_cb->serdes_ctrl) {
		u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);

		dsaf_set_field(origin, 1ull << 10, 10, !!en);
		dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	} else {
		dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	}

	return 0;
}
Commit	Line	Data
511e6bc0	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
511e6bc0	10	#include "hns_dsaf_mac.h"
2e2591b1	11	#include "hns_dsaf_misc.h"
511e6bc0	12	#include "hns_dsaf_ppe.h"
2e2591b1	13	#include "hns_dsaf_reg.h"
511e6bc0	14
831d828b YZZ	15	static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
	16	{
	17	if (dsaf_dev->sub_ctrl)
	18	dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
	19	else
	20	dsaf_write_reg(dsaf_dev->sc_base, reg, val);
	21	}
	22
	23	static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
	24	{
	25	u32 ret;
	26
	27	if (dsaf_dev->sub_ctrl)
	28	ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
	29	else
	30	ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
	31
	32	return ret;
	33	}
	34
511e6bc0	35	void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
	36	u16 speed, int data)
	37	{
	38	int speed_reg = 0;
	39	u8 value;
	40
	41	if (!mac_cb) {
	42	pr_err("sfp_led_opt mac_dev is null!\n");
	43	return;
	44	}
31d4446d YZZ	45	if (!mac_cb->cpld_ctrl) {
31d4446d YZZ	46	dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
511e6bc0	47	mac_cb->mac_id);
	48	return;
	49	}
	50
	51	if (speed == MAC_SPEED_10000)
	52	speed_reg = 1;
	53
	54	value = mac_cb->cpld_led_value;
	55
	56	if (link_status) {
	57	dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
	58	dsaf_set_field(value, DSAF_LED_SPEED_M,
	59	DSAF_LED_SPEED_S, speed_reg);
	60	dsaf_set_bit(value, DSAF_LED_DATA_B, data);
	61
	62	if (value != mac_cb->cpld_led_value) {
31d4446d YZZ	63	dsaf_write_syscon(mac_cb->cpld_ctrl,
31d4446d YZZ	64	mac_cb->cpld_ctrl_reg, value);
511e6bc0	65	mac_cb->cpld_led_value = value;
	66	}
	67	} else {
31d4446d YZZ	68	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	69	CPLD_LED_DEFAULT_VALUE);
511e6bc0	70	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	71	}
	72	}
	73
	74	void cpld_led_reset(struct hns_mac_cb *mac_cb)
	75	{
31d4446d	76	if (!mac_cb \|\| !mac_cb->cpld_ctrl)
511e6bc0	77	return;
511e6bc0	78
31d4446d YZZ	79	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	80	CPLD_LED_DEFAULT_VALUE);
511e6bc0	81	mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
	82	}
	83
	84	int cpld_set_led_id(struct hns_mac_cb *mac_cb,
	85	enum hnae_led_state status)
	86	{
	87	switch (status) {
	88	case HNAE_LED_ACTIVE:
31d4446d YZZ	89	mac_cb->cpld_led_value =
	90	dsaf_read_syscon(mac_cb->cpld_ctrl,
	91	mac_cb->cpld_ctrl_reg);
511e6bc0	92	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
511e6bc0	93	CPLD_LED_ON_VALUE);
31d4446d YZZ	94	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	95	mac_cb->cpld_led_value);
edc9b427	96	return 2;
511e6bc0	97	case HNAE_LED_INACTIVE:
	98	dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
	99	CPLD_LED_DEFAULT_VALUE);
31d4446d YZZ	100	dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
31d4446d YZZ	101	mac_cb->cpld_led_value);
511e6bc0	102	break;
	103	default:
	104	break;
	105	}
	106
	107	return 0;
	108	}
	109
	110	#define RESET_REQ_OR_DREQ 1
	111
	112	void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
	113	{
	114	u32 xbar_reg_addr;
	115	u32 nt_reg_addr;
	116
	117	if (!val) {
	118	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
	119	nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
	120	} else {
	121	xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
	122	nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
	123	}
	124
831d828b YZZ	125	dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
831d828b YZZ	126	dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
511e6bc0	127	}
	128
	129	void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	130	{
	131	u32 reg_val = 0;
	132	u32 reg_addr;
	133
	134	if (port >= DSAF_XGE_NUM)
	135	return;
	136
	137	reg_val \|= RESET_REQ_OR_DREQ;
850bfa3b	138	reg_val \|= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	139
	140	if (val == 0)
	141	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	142	else
	143	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	144
831d828b	145	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	146	}
	147
	148	void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
	149	u32 port, u32 val)
	150	{
	151	u32 reg_val = 0;
	152	u32 reg_addr;
	153
	154	if (port >= DSAF_XGE_NUM)
	155	return;
	156
850bfa3b YZZ	157	reg_val \|= XGMAC_TRX_CORE_SRST_M
850bfa3b YZZ	158	<< dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	159
	160	if (val == 0)
	161	reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
	162	else
	163	reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
	164
831d828b	165	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	166	}
	167
	168	void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	169	{
	170	u32 reg_val_1;
	171	u32 reg_val_2;
850bfa3b	172	u32 port_rst_off;
511e6bc0	173
	174	if (port >= DSAF_GE_NUM)
	175	return;
	176
89a44093	177	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	178	reg_val_1 = 0x1 << port;
850bfa3b	179	port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
13ac695e S	180	/* there is difference between V1 and V2 in register.*/
13ac695e S	181	if (AE_IS_VER1(dsaf_dev->dsaf_ver))
850bfa3b	182	reg_val_2 = 0x1041041 << port_rst_off;
13ac695e	183	else
850bfa3b	184	reg_val_2 = 0x2082082 << port_rst_off;
511e6bc0	185
511e6bc0	186	if (val == 0) {
831d828b	187	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	188	reg_val_1);
511e6bc0	189
831d828b	190	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
511e6bc0	191	reg_val_2);
511e6bc0	192	} else {
831d828b	193	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
511e6bc0	194	reg_val_2);
511e6bc0	195
831d828b	196	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	197	reg_val_1);
	198	}
	199	} else {
422c3107 YZZ	200	reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
422c3107 YZZ	201	reg_val_2 = 0x100 << dsaf_dev->reset_offset;
511e6bc0	202
511e6bc0	203	if (val == 0) {
831d828b	204	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
511e6bc0	205	reg_val_1);
511e6bc0	206
831d828b	207	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
511e6bc0	208	reg_val_2);
511e6bc0	209	} else {
831d828b	210	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
511e6bc0	211	reg_val_1);
511e6bc0	212
831d828b	213	dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
511e6bc0	214	reg_val_2);
	215	}
	216	}
	217	}
	218
	219	void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
	220	{
	221	u32 reg_val = 0;
	222	u32 reg_addr;
	223
850bfa3b	224	reg_val \|= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
511e6bc0	225
	226	if (val == 0)
	227	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	228	else
	229	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	230
831d828b	231	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	232	}
	233
	234	void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
	235	{
511e6bc0	236	struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
	237	u32 reg_val;
	238	u32 reg_addr;
	239
89a44093	240	if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
511e6bc0	241	reg_val = RESET_REQ_OR_DREQ;
	242	if (val == 0)
	243	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
	244	else
	245	reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
	246
	247	} else {
422c3107	248	reg_val = 0x100 << dsaf_dev->reset_offset;
511e6bc0	249
	250	if (val == 0)
	251	reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
	252	else
	253	reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
	254	}
	255
831d828b	256	dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
511e6bc0	257	}
	258
	259	/**
	260	* hns_mac_get_sds_mode - get phy ifterface form serdes mode
	261	* @mac_cb: mac control block
	262	* retuen phy interface
	263	*/
	264	phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
	265	{
c1203fe7 SL	266	u32 mode;
	267	u32 reg;
	268	u32 shift;
422c3107	269	u32 phy_offset;
c1203fe7	270	bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
c1203fe7	271	int mac_id = mac_cb->mac_id;
511e6bc0	272	phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
511e6bc0	273
422c3107	274	if (is_ver1 && HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	275	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107 YZZ	276	} else if (mac_id >= 0 && mac_id <= 3 &&
422c3107 YZZ	277	!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) {
c1203fe7	278	reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
831d828b	279	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
c1203fe7 SL	280	/* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
	281	shift = is_ver1 ? 0 : mac_id;
	282	if (dsaf_get_bit(mode, shift))
511e6bc0	283	phy_if = PHY_INTERFACE_MODE_XGMII;
511e6bc0	284	else
c1203fe7	285	phy_if = PHY_INTERFACE_MODE_SGMII;
422c3107	286	} else {
c1203fe7	287	reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
831d828b	288	mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
422c3107 YZZ	289	/* mac_id 4, 5,---> hilink3 lane 2, 3
	290	* debug port 0(6), 1(7) ---> hilink3 lane 0, 1
	291	*/
	292	phy_offset = mac_cb->dsaf_dev->reset_offset - 1;
	293	shift = is_ver1 ? 0 : mac_id >= 4 ? mac_id - 2 : phy_offset;
c1203fe7	294	if (dsaf_get_bit(mode, shift))
511e6bc0	295	phy_if = PHY_INTERFACE_MODE_XGMII;
c1203fe7 SL	296	else
c1203fe7 SL	297	phy_if = PHY_INTERFACE_MODE_SGMII;
511e6bc0	298	}
511e6bc0	299	return phy_if;
	300	}
	301
31d4446d YZZ	302	int hns_mac_get_sfp_prsnt(struct hns_mac_cb mac_cb, int sfp_prsnt)
	303	{
	304	if (!mac_cb->cpld_ctrl)
	305	return -ENODEV;
	306
	307	*sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
	308	+ MAC_SFP_PORT_OFFSET);
	309
	310	return 0;
	311	}
	312
511e6bc0	313	/**
	314	* hns_mac_config_sds_loopback - set loop back for serdes
	315	* @mac_cb: mac control block
	316	* retuen 0 == success
	317	*/
	318	int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
	319	{
	320	/* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
	321	* port 4-7 hilink3 base is serdes_vaddr + 0x00200000
	322	*/
	323	u8 base_addr = (u8 )mac_cb->serdes_vaddr +
	324	(mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
	325	const u8 lane_id[] = {
	326	0, /* mac 0 -> lane 0 */
	327	1, /* mac 1 -> lane 1 */
	328	2, /* mac 2 -> lane 2 */
	329	3, /* mac 3 -> lane 3 */
	330	2, /* mac 4 -> lane 2 */
	331	3, /* mac 5 -> lane 3 */
	332	0, /* mac 6 -> lane 0 */
	333	1 /* mac 7 -> lane 1 */
	334	};
	335	#define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
	336	u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
	337
	338	int sfp_prsnt;
	339	int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
	340
	341	if (!mac_cb->phy_node) {
	342	if (ret)
	343	pr_info("please confirm sfp is present or not\n");
	344	else
	345	if (!sfp_prsnt)
	346	pr_info("no sfp in this eth\n");
	347	}
	348
831d828b YZZ	349	if (mac_cb->serdes_ctrl) {
	350	u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
	351
	352	dsaf_set_field(origin, 1ull << 10, 10, !!en);
	353	dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
	354	} else {
	355	dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
	356	}
511e6bc0	357
	358	return 0;
	359	}