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511e6bc0 | 1 | /* |
2 | * Copyright (c) 2014-2015 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #ifndef _DSAF_REG_H_ | |
11 | #define _DSAF_REG_H_ | |
12 | ||
13ac695e S |
13 | #define HNS_DEBUG_RING_IRQ_IDX 55 |
14 | #define HNS_SERVICE_RING_IRQ_IDX 59 | |
15 | #define HNS_DEBUG_RING_IRQ_OFFSET 2 | |
16 | #define HNSV2_DEBUG_RING_IRQ_IDX 409 | |
17 | #define HNSV2_SERVICE_RING_IRQ_IDX 25 | |
18 | #define HNSV2_DEBUG_RING_IRQ_OFFSET 9 | |
511e6bc0 | 19 | |
20 | #define DSAF_MAX_PORT_NUM_PER_CHIP 8 | |
21 | #define DSAF_SERVICE_PORT_NUM_PER_DSAF 6 | |
22 | #define DSAF_MAX_VM_NUM 128 | |
23 | ||
24 | #define DSAF_COMM_DEV_NUM 3 | |
25 | #define DSAF_PPE_INODE_BASE 6 | |
26 | #define HNS_DSAF_COMM_SERVICE_NW_IDX 0 | |
27 | #define DSAF_DEBUG_NW_NUM 2 | |
28 | #define DSAF_SERVICE_NW_NUM 6 | |
29 | #define DSAF_COMM_CHN DSAF_SERVICE_NW_NUM | |
30 | #define DSAF_GE_NUM ((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM)) | |
31 | #define DSAF_PORT_NUM ((DSAF_SERVICE_NW_NUM) + (DSAF_DEBUG_NW_NUM)) | |
32 | #define DSAF_XGE_NUM DSAF_SERVICE_NW_NUM | |
13ac695e | 33 | #define DSAF_PORT_TYPE_NUM 3 |
511e6bc0 | 34 | #define DSAF_NODE_NUM 18 |
35 | #define DSAF_XOD_BIG_NUM DSAF_NODE_NUM | |
36 | #define DSAF_SBM_NUM DSAF_NODE_NUM | |
13ac695e S |
37 | #define DSAFV2_SBM_NUM 8 |
38 | #define DSAFV2_SBM_XGE_CHN 6 | |
39 | #define DSAFV2_SBM_PPE_CHN 1 | |
40 | #define DASFV2_ROCEE_CRD_NUM 8 | |
41 | ||
511e6bc0 | 42 | #define DSAF_VOQ_NUM DSAF_NODE_NUM |
43 | #define DSAF_INODE_NUM DSAF_NODE_NUM | |
44 | #define DSAF_XOD_NUM 8 | |
45 | #define DSAF_TBL_NUM 8 | |
46 | #define DSAF_SW_PORT_NUM 8 | |
47 | #define DSAF_TOTAL_QUEUE_NUM 129 | |
48 | ||
49 | #define DSAF_TCAM_SUM 512 | |
50 | #define DSAF_LINE_SUM (2048 * 14) | |
51 | ||
8044f97e S |
52 | #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100 |
53 | #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180 | |
54 | #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184 | |
55 | #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188 | |
56 | #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C | |
57 | #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190 | |
58 | #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194 | |
59 | #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300 | |
60 | #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304 | |
61 | #define DSAF_SUB_SC_NT_CLK_EN_REG 0x308 | |
62 | #define DSAF_SUB_SC_NT_CLK_DIS_REG 0x30C | |
63 | #define DSAF_SUB_SC_XGE_CLK_EN_REG 0x310 | |
64 | #define DSAF_SUB_SC_XGE_CLK_DIS_REG 0x314 | |
65 | #define DSAF_SUB_SC_GE_CLK_EN_REG 0x318 | |
66 | #define DSAF_SUB_SC_GE_CLK_DIS_REG 0x31C | |
67 | #define DSAF_SUB_SC_PPE_CLK_EN_REG 0x320 | |
68 | #define DSAF_SUB_SC_PPE_CLK_DIS_REG 0x324 | |
69 | #define DSAF_SUB_SC_RCB_PPE_COM_CLK_EN_REG 0x350 | |
70 | #define DSAF_SUB_SC_RCB_PPE_COM_CLK_DIS_REG 0x354 | |
71 | #define DSAF_SUB_SC_XBAR_RESET_REQ_REG 0xA00 | |
72 | #define DSAF_SUB_SC_XBAR_RESET_DREQ_REG 0xA04 | |
73 | #define DSAF_SUB_SC_NT_RESET_REQ_REG 0xA08 | |
74 | #define DSAF_SUB_SC_NT_RESET_DREQ_REG 0xA0C | |
75 | #define DSAF_SUB_SC_XGE_RESET_REQ_REG 0xA10 | |
76 | #define DSAF_SUB_SC_XGE_RESET_DREQ_REG 0xA14 | |
77 | #define DSAF_SUB_SC_GE_RESET_REQ0_REG 0xA18 | |
78 | #define DSAF_SUB_SC_GE_RESET_DREQ0_REG 0xA1C | |
79 | #define DSAF_SUB_SC_GE_RESET_REQ1_REG 0xA20 | |
80 | #define DSAF_SUB_SC_GE_RESET_DREQ1_REG 0xA24 | |
81 | #define DSAF_SUB_SC_PPE_RESET_REQ_REG 0xA48 | |
82 | #define DSAF_SUB_SC_PPE_RESET_DREQ_REG 0xA4C | |
83 | #define DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG 0xA88 | |
84 | #define DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG 0xA8C | |
85 | #define DSAF_SUB_SC_LIGHT_MODULE_DETECT_EN_REG 0x2060 | |
86 | #define DSAF_SUB_SC_TCAM_MBIST_EN_REG 0x2300 | |
87 | #define DSAF_SUB_SC_DSAF_CLK_ST_REG 0x5300 | |
88 | #define DSAF_SUB_SC_NT_CLK_ST_REG 0x5304 | |
89 | #define DSAF_SUB_SC_XGE_CLK_ST_REG 0x5308 | |
90 | #define DSAF_SUB_SC_GE_CLK_ST_REG 0x530C | |
91 | #define DSAF_SUB_SC_PPE_CLK_ST_REG 0x5310 | |
92 | #define DSAF_SUB_SC_ROCEE_CLK_ST_REG 0x5314 | |
93 | #define DSAF_SUB_SC_CPU_CLK_ST_REG 0x5318 | |
94 | #define DSAF_SUB_SC_RCB_PPE_COM_CLK_ST_REG 0x5328 | |
95 | #define DSAF_SUB_SC_XBAR_RESET_ST_REG 0x5A00 | |
96 | #define DSAF_SUB_SC_NT_RESET_ST_REG 0x5A04 | |
97 | #define DSAF_SUB_SC_XGE_RESET_ST_REG 0x5A08 | |
98 | #define DSAF_SUB_SC_GE_RESET_ST0_REG 0x5A0C | |
99 | #define DSAF_SUB_SC_GE_RESET_ST1_REG 0x5A10 | |
100 | #define DSAF_SUB_SC_PPE_RESET_ST_REG 0x5A24 | |
101 | #define DSAF_SUB_SC_RCB_PPE_COM_RESET_ST_REG 0x5A44 | |
511e6bc0 | 102 | |
103 | /*serdes offset**/ | |
104 | #define HNS_MAC_HILINK3_REG DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG | |
105 | #define HNS_MAC_HILINK4_REG DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG | |
c1203fe7 SL |
106 | #define HNS_MAC_HILINK3V2_REG DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG |
107 | #define HNS_MAC_HILINK4V2_REG DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG | |
511e6bc0 | 108 | #define HNS_MAC_LANE0_CTLEDFE_REG 0x000BFFCCULL |
109 | #define HNS_MAC_LANE1_CTLEDFE_REG 0x000BFFBCULL | |
110 | #define HNS_MAC_LANE2_CTLEDFE_REG 0x000BFFACULL | |
111 | #define HNS_MAC_LANE3_CTLEDFE_REG 0x000BFF9CULL | |
112 | #define HNS_MAC_LANE0_STATE_REG 0x000BFFD4ULL | |
113 | #define HNS_MAC_LANE1_STATE_REG 0x000BFFC4ULL | |
114 | #define HNS_MAC_LANE2_STATE_REG 0x000BFFB4ULL | |
115 | #define HNS_MAC_LANE3_STATE_REG 0x000BFFA4ULL | |
116 | ||
117 | #define HILINK_RESET_TIMOUT 10000 | |
118 | ||
119 | #define DSAF_SRAM_INIT_OVER_0_REG 0x0 | |
120 | #define DSAF_CFG_0_REG 0x4 | |
121 | #define DSAF_ECC_ERR_INVERT_0_REG 0x8 | |
122 | #define DSAF_ABNORMAL_TIMEOUT_0_REG 0x1C | |
123 | #define DSAF_FSM_TIMEOUT_0_REG 0x20 | |
124 | #define DSAF_DSA_REG_CNT_CLR_CE_REG 0x2C | |
125 | #define DSAF_DSA_SBM_INF_FIFO_THRD_REG 0x30 | |
126 | #define DSAF_DSA_SRAM_1BIT_ECC_SEL_REG 0x34 | |
127 | #define DSAF_DSA_SRAM_1BIT_ECC_CNT_REG 0x38 | |
128 | #define DSAF_PFC_EN_0_REG 0x50 | |
129 | #define DSAF_PFC_UNIT_CNT_0_REG 0x70 | |
130 | #define DSAF_XGE_INT_MSK_0_REG 0x100 | |
131 | #define DSAF_PPE_INT_MSK_0_REG 0x120 | |
132 | #define DSAF_ROCEE_INT_MSK_0_REG 0x140 | |
133 | #define DSAF_XGE_INT_SRC_0_REG 0x160 | |
134 | #define DSAF_PPE_INT_SRC_0_REG 0x180 | |
135 | #define DSAF_ROCEE_INT_SRC_0_REG 0x1A0 | |
136 | #define DSAF_XGE_INT_STS_0_REG 0x1C0 | |
137 | #define DSAF_PPE_INT_STS_0_REG 0x1E0 | |
138 | #define DSAF_ROCEE_INT_STS_0_REG 0x200 | |
68c222a6 | 139 | #define DSAFV2_SERDES_LBK_0_REG 0x220 |
511e6bc0 | 140 | #define DSAF_PPE_QID_CFG_0_REG 0x300 |
141 | #define DSAF_SW_PORT_TYPE_0_REG 0x320 | |
142 | #define DSAF_STP_PORT_TYPE_0_REG 0x340 | |
143 | #define DSAF_MIX_DEF_QID_0_REG 0x360 | |
144 | #define DSAF_PORT_DEF_VLAN_0_REG 0x380 | |
145 | #define DSAF_VM_DEF_VLAN_0_REG 0x400 | |
146 | ||
147 | #define DSAF_INODE_CUT_THROUGH_CFG_0_REG 0x1000 | |
148 | #define DSAF_INODE_ECC_INVERT_EN_0_REG 0x1008 | |
149 | #define DSAF_INODE_ECC_ERR_ADDR_0_REG 0x100C | |
150 | #define DSAF_INODE_IN_PORT_NUM_0_REG 0x1018 | |
151 | #define DSAF_INODE_PRI_TC_CFG_0_REG 0x101C | |
152 | #define DSAF_INODE_BP_STATUS_0_REG 0x1020 | |
153 | #define DSAF_INODE_PAD_DISCARD_NUM_0_REG 0x1028 | |
154 | #define DSAF_INODE_FINAL_IN_MAN_NUM_0_REG 0x102C | |
155 | #define DSAF_INODE_FINAL_IN_PKT_NUM_0_REG 0x1030 | |
156 | #define DSAF_INODE_SBM_PID_NUM_0_REG 0x1038 | |
157 | #define DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG 0x103C | |
158 | #define DSAF_INODE_SBM_RELS_NUM_0_REG 0x104C | |
159 | #define DSAF_INODE_SBM_DROP_NUM_0_REG 0x1050 | |
160 | #define DSAF_INODE_CRC_FALSE_NUM_0_REG 0x1054 | |
161 | #define DSAF_INODE_BP_DISCARD_NUM_0_REG 0x1058 | |
162 | #define DSAF_INODE_RSLT_DISCARD_NUM_0_REG 0x105C | |
163 | #define DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG 0x1060 | |
164 | #define DSAF_INODE_VOQ_OVER_NUM_0_REG 0x1068 | |
165 | #define DSAF_INODE_BD_SAVE_STATUS_0_REG 0x1900 | |
166 | #define DSAF_INODE_BD_ORDER_STATUS_0_REG 0x1950 | |
167 | #define DSAF_INODE_SW_VLAN_TAG_DISC_0_REG 0x1A00 | |
168 | #define DSAF_INODE_IN_DATA_STP_DISC_0_REG 0x1A50 | |
169 | #define DSAF_INODE_GE_FC_EN_0_REG 0x1B00 | |
170 | #define DSAF_INODE_VC0_IN_PKT_NUM_0_REG 0x1B50 | |
171 | #define DSAF_INODE_VC1_IN_PKT_NUM_0_REG 0x1C00 | |
172 | ||
173 | #define DSAF_SBM_CFG_REG_0_REG 0x2000 | |
174 | #define DSAF_SBM_BP_CFG_0_XGE_REG_0_REG 0x2004 | |
175 | #define DSAF_SBM_BP_CFG_0_PPE_REG_0_REG 0x2304 | |
176 | #define DSAF_SBM_BP_CFG_0_ROCEE_REG_0_REG 0x2604 | |
177 | #define DSAF_SBM_BP_CFG_1_REG_0_REG 0x2008 | |
178 | #define DSAF_SBM_BP_CFG_2_XGE_REG_0_REG 0x200C | |
179 | #define DSAF_SBM_BP_CFG_2_PPE_REG_0_REG 0x230C | |
180 | #define DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x260C | |
13ac695e | 181 | #define DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG 0x238C |
511e6bc0 | 182 | #define DSAF_SBM_FREE_CNT_0_0_REG 0x2010 |
183 | #define DSAF_SBM_FREE_CNT_1_0_REG 0x2014 | |
184 | #define DSAF_SBM_BP_CNT_0_0_REG 0x2018 | |
185 | #define DSAF_SBM_BP_CNT_1_0_REG 0x201C | |
186 | #define DSAF_SBM_BP_CNT_2_0_REG 0x2020 | |
187 | #define DSAF_SBM_BP_CNT_3_0_REG 0x2024 | |
188 | #define DSAF_SBM_INER_ST_0_REG 0x2028 | |
189 | #define DSAF_SBM_MIB_REQ_FAILED_TC_0_REG 0x202C | |
190 | #define DSAF_SBM_LNK_INPORT_CNT_0_REG 0x2030 | |
191 | #define DSAF_SBM_LNK_DROP_CNT_0_REG 0x2034 | |
192 | #define DSAF_SBM_INF_OUTPORT_CNT_0_REG 0x2038 | |
193 | #define DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG 0x203C | |
194 | #define DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG 0x2040 | |
195 | #define DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG 0x2044 | |
196 | #define DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG 0x2048 | |
197 | #define DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG 0x204C | |
198 | #define DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG 0x2050 | |
199 | #define DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG 0x2054 | |
200 | #define DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG 0x2058 | |
201 | #define DSAF_SBM_LNK_REQ_CNT_0_REG 0x205C | |
202 | #define DSAF_SBM_LNK_RELS_CNT_0_REG 0x2060 | |
203 | #define DSAF_SBM_BP_CFG_3_REG_0_REG 0x2068 | |
204 | #define DSAF_SBM_BP_CFG_4_REG_0_REG 0x206C | |
205 | ||
206 | #define DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG 0x3000 | |
207 | #define DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG 0x3004 | |
208 | #define DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG 0x3008 | |
209 | #define DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG 0x300C | |
210 | #define DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG 0x3010 | |
211 | #define DSAF_XOD_ETS_TOKEN_CFG_0_REG 0x3014 | |
212 | #define DSAF_XOD_PFS_CFG_0_0_REG 0x3018 | |
213 | #define DSAF_XOD_PFS_CFG_1_0_REG 0x301C | |
214 | #define DSAF_XOD_PFS_CFG_2_0_REG 0x3020 | |
215 | #define DSAF_XOD_GNT_L_0_REG 0x3024 | |
216 | #define DSAF_XOD_GNT_H_0_REG 0x3028 | |
217 | #define DSAF_XOD_CONNECT_STATE_0_REG 0x302C | |
218 | #define DSAF_XOD_RCVPKT_CNT_0_REG 0x3030 | |
219 | #define DSAF_XOD_RCVTC0_CNT_0_REG 0x3034 | |
220 | #define DSAF_XOD_RCVTC1_CNT_0_REG 0x3038 | |
221 | #define DSAF_XOD_RCVTC2_CNT_0_REG 0x303C | |
222 | #define DSAF_XOD_RCVTC3_CNT_0_REG 0x3040 | |
223 | #define DSAF_XOD_RCVVC0_CNT_0_REG 0x3044 | |
224 | #define DSAF_XOD_RCVVC1_CNT_0_REG 0x3048 | |
225 | #define DSAF_XOD_XGE_RCVIN0_CNT_0_REG 0x304C | |
226 | #define DSAF_XOD_XGE_RCVIN1_CNT_0_REG 0x3050 | |
227 | #define DSAF_XOD_XGE_RCVIN2_CNT_0_REG 0x3054 | |
228 | #define DSAF_XOD_XGE_RCVIN3_CNT_0_REG 0x3058 | |
229 | #define DSAF_XOD_XGE_RCVIN4_CNT_0_REG 0x305C | |
230 | #define DSAF_XOD_XGE_RCVIN5_CNT_0_REG 0x3060 | |
231 | #define DSAF_XOD_XGE_RCVIN6_CNT_0_REG 0x3064 | |
232 | #define DSAF_XOD_XGE_RCVIN7_CNT_0_REG 0x3068 | |
233 | #define DSAF_XOD_PPE_RCVIN0_CNT_0_REG 0x306C | |
234 | #define DSAF_XOD_PPE_RCVIN1_CNT_0_REG 0x3070 | |
235 | #define DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG 0x3074 | |
236 | #define DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG 0x3078 | |
237 | #define DSAF_XOD_FIFO_STATUS_0_REG 0x307C | |
238 | ||
239 | #define DSAF_VOQ_ECC_INVERT_EN_0_REG 0x4004 | |
240 | #define DSAF_VOQ_SRAM_PKT_NUM_0_REG 0x4008 | |
241 | #define DSAF_VOQ_IN_PKT_NUM_0_REG 0x400C | |
242 | #define DSAF_VOQ_OUT_PKT_NUM_0_REG 0x4010 | |
243 | #define DSAF_VOQ_ECC_ERR_ADDR_0_REG 0x4014 | |
244 | #define DSAF_VOQ_BP_STATUS_0_REG 0x4018 | |
245 | #define DSAF_VOQ_SPUP_IDLE_0_REG 0x401C | |
246 | #define DSAF_VOQ_XGE_XOD_REQ_0_0_REG 0x4024 | |
247 | #define DSAF_VOQ_XGE_XOD_REQ_1_0_REG 0x4028 | |
248 | #define DSAF_VOQ_PPE_XOD_REQ_0_REG 0x402C | |
249 | #define DSAF_VOQ_ROCEE_XOD_REQ_0_REG 0x4030 | |
250 | #define DSAF_VOQ_BP_ALL_THRD_0_REG 0x4034 | |
251 | ||
252 | #define DSAF_TBL_CTRL_0_REG 0x5000 | |
253 | #define DSAF_TBL_INT_MSK_0_REG 0x5004 | |
254 | #define DSAF_TBL_INT_SRC_0_REG 0x5008 | |
255 | #define DSAF_TBL_INT_STS_0_REG 0x5100 | |
256 | #define DSAF_TBL_TCAM_ADDR_0_REG 0x500C | |
257 | #define DSAF_TBL_LINE_ADDR_0_REG 0x5010 | |
258 | #define DSAF_TBL_TCAM_HIGH_0_REG 0x5014 | |
259 | #define DSAF_TBL_TCAM_LOW_0_REG 0x5018 | |
260 | #define DSAF_TBL_TCAM_MCAST_CFG_4_0_REG 0x501C | |
261 | #define DSAF_TBL_TCAM_MCAST_CFG_3_0_REG 0x5020 | |
262 | #define DSAF_TBL_TCAM_MCAST_CFG_2_0_REG 0x5024 | |
263 | #define DSAF_TBL_TCAM_MCAST_CFG_1_0_REG 0x5028 | |
264 | #define DSAF_TBL_TCAM_MCAST_CFG_0_0_REG 0x502C | |
265 | #define DSAF_TBL_TCAM_UCAST_CFG_0_REG 0x5030 | |
266 | #define DSAF_TBL_LIN_CFG_0_REG 0x5034 | |
267 | #define DSAF_TBL_TCAM_RDATA_HIGH_0_REG 0x5038 | |
268 | #define DSAF_TBL_TCAM_RDATA_LOW_0_REG 0x503C | |
269 | #define DSAF_TBL_TCAM_RAM_RDATA4_0_REG 0x5040 | |
270 | #define DSAF_TBL_TCAM_RAM_RDATA3_0_REG 0x5044 | |
271 | #define DSAF_TBL_TCAM_RAM_RDATA2_0_REG 0x5048 | |
272 | #define DSAF_TBL_TCAM_RAM_RDATA1_0_REG 0x504C | |
273 | #define DSAF_TBL_TCAM_RAM_RDATA0_0_REG 0x5050 | |
274 | #define DSAF_TBL_LIN_RDATA_0_REG 0x5054 | |
275 | #define DSAF_TBL_DA0_MIS_INFO1_0_REG 0x5058 | |
276 | #define DSAF_TBL_DA0_MIS_INFO0_0_REG 0x505C | |
277 | #define DSAF_TBL_SA_MIS_INFO2_0_REG 0x5104 | |
278 | #define DSAF_TBL_SA_MIS_INFO1_0_REG 0x5098 | |
279 | #define DSAF_TBL_SA_MIS_INFO0_0_REG 0x509C | |
280 | #define DSAF_TBL_PUL_0_REG 0x50A0 | |
281 | #define DSAF_TBL_OLD_RSLT_0_REG 0x50A4 | |
282 | #define DSAF_TBL_OLD_SCAN_VAL_0_REG 0x50A8 | |
283 | #define DSAF_TBL_DFX_CTRL_0_REG 0x50AC | |
284 | #define DSAF_TBL_DFX_STAT_0_REG 0x50B0 | |
285 | #define DSAF_TBL_DFX_STAT_2_0_REG 0x5108 | |
286 | #define DSAF_TBL_LKUP_NUM_I_0_REG 0x50C0 | |
287 | #define DSAF_TBL_LKUP_NUM_O_0_REG 0x50E0 | |
288 | #define DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG 0x510C | |
289 | ||
290 | #define DSAF_INODE_FIFO_WL_0_REG 0x6000 | |
291 | #define DSAF_ONODE_FIFO_WL_0_REG 0x6020 | |
292 | #define DSAF_XGE_GE_WORK_MODE_0_REG 0x6040 | |
293 | #define DSAF_XGE_APP_RX_LINK_UP_0_REG 0x6080 | |
294 | #define DSAF_NETPORT_CTRL_SIG_0_REG 0x60A0 | |
295 | #define DSAF_XGE_CTRL_SIG_CFG_0_REG 0x60C0 | |
296 | ||
297 | #define PPE_COM_CFG_QID_MODE_REG 0x0 | |
298 | #define PPE_COM_INTEN_REG 0x110 | |
299 | #define PPE_COM_RINT_REG 0x114 | |
300 | #define PPE_COM_INTSTS_REG 0x118 | |
301 | #define PPE_COM_COMMON_CNT_CLR_CE_REG 0x1120 | |
302 | #define PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG 0x300 | |
303 | #define PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG 0x600 | |
304 | #define PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG 0x900 | |
305 | #define PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG 0xC00 | |
306 | #define PPE_COM_COMMON_CNT_CLR_CE_REG 0x1120 | |
307 | ||
308 | #define PPE_CFG_TX_FIFO_THRSLD_REG 0x0 | |
309 | #define PPE_CFG_RX_FIFO_THRSLD_REG 0x4 | |
310 | #define PPE_CFG_RX_FIFO_PAUSE_THRSLD_REG 0x8 | |
311 | #define PPE_CFG_RX_FIFO_SW_BP_THRSLD_REG 0xC | |
312 | #define PPE_CFG_PAUSE_IDLE_CNT_REG 0x10 | |
313 | #define PPE_CFG_BUS_CTRL_REG 0x40 | |
314 | #define PPE_CFG_TNL_TO_BE_RST_REG 0x48 | |
315 | #define PPE_CURR_TNL_CAN_RST_REG 0x4C | |
316 | #define PPE_CFG_XGE_MODE_REG 0x80 | |
317 | #define PPE_CFG_MAX_FRAME_LEN_REG 0x84 | |
318 | #define PPE_CFG_RX_PKT_MODE_REG 0x88 | |
319 | #define PPE_CFG_RX_VLAN_TAG_REG 0x8C | |
320 | #define PPE_CFG_TAG_GEN_REG 0x90 | |
321 | #define PPE_CFG_PARSE_TAG_REG 0x94 | |
322 | #define PPE_CFG_PRO_CHECK_EN_REG 0x98 | |
8044f97e S |
323 | #define PPEV2_CFG_TSO_EN_REG 0xA0 |
324 | #define PPEV2_VLAN_STRIP_EN_REG 0xAC | |
511e6bc0 | 325 | #define PPE_INTEN_REG 0x100 |
326 | #define PPE_RINT_REG 0x104 | |
327 | #define PPE_INTSTS_REG 0x108 | |
328 | #define PPE_CFG_RX_PKT_INT_REG 0x140 | |
329 | #define PPE_CFG_HEAT_DECT_TIME0_REG 0x144 | |
330 | #define PPE_CFG_HEAT_DECT_TIME1_REG 0x148 | |
331 | #define PPE_HIS_RX_SW_PKT_CNT_REG 0x200 | |
332 | #define PPE_HIS_RX_WR_BD_OK_PKT_CNT_REG 0x204 | |
333 | #define PPE_HIS_RX_PKT_NO_BUF_CNT_REG 0x208 | |
334 | #define PPE_HIS_TX_BD_CNT_REG 0x20C | |
335 | #define PPE_HIS_TX_PKT_CNT_REG 0x210 | |
336 | #define PPE_HIS_TX_PKT_OK_CNT_REG 0x214 | |
337 | #define PPE_HIS_TX_PKT_EPT_CNT_REG 0x218 | |
338 | #define PPE_HIS_TX_PKT_CS_FAIL_CNT_REG 0x21C | |
339 | #define PPE_HIS_RX_APP_BUF_FAIL_CNT_REG 0x220 | |
340 | #define PPE_HIS_RX_APP_BUF_WAIT_CNT_REG 0x224 | |
341 | #define PPE_HIS_RX_PKT_DROP_FUL_CNT_REG 0x228 | |
342 | #define PPE_HIS_RX_PKT_DROP_PRT_CNT_REG 0x22C | |
343 | #define PPE_TNL_0_5_CNT_CLR_CE_REG 0x300 | |
344 | #define PPE_CFG_AXI_DBG_REG 0x304 | |
345 | #define PPE_HIS_PRO_ERR_REG 0x308 | |
346 | #define PPE_HIS_TNL_FIFO_ERR_REG 0x30C | |
347 | #define PPE_CURR_CFF_DATA_NUM_REG 0x310 | |
348 | #define PPE_CURR_RX_ST_REG 0x314 | |
349 | #define PPE_CURR_TX_ST_REG 0x318 | |
350 | #define PPE_CURR_RX_FIFO0_REG 0x31C | |
351 | #define PPE_CURR_RX_FIFO1_REG 0x320 | |
352 | #define PPE_CURR_TX_FIFO0_REG 0x324 | |
353 | #define PPE_CURR_TX_FIFO1_REG 0x328 | |
354 | #define PPE_ECO0_REG 0x32C | |
355 | #define PPE_ECO1_REG 0x330 | |
356 | #define PPE_ECO2_REG 0x334 | |
6bc0ce7d S |
357 | #define PPEV2_INDRECTION_TBL_REG 0x800 |
358 | #define PPEV2_RSS_KEY_REG 0x900 | |
511e6bc0 | 359 | |
360 | #define RCB_COM_CFG_ENDIAN_REG 0x0 | |
361 | #define RCB_COM_CFG_SYS_FSH_REG 0xC | |
362 | #define RCB_COM_CFG_INIT_FLAG_REG 0x10 | |
363 | #define RCB_COM_CFG_PKT_REG 0x30 | |
364 | #define RCB_COM_CFG_RINVLD_REG 0x34 | |
365 | #define RCB_COM_CFG_FNA_REG 0x38 | |
366 | #define RCB_COM_CFG_FA_REG 0x3C | |
367 | #define RCB_COM_CFG_PKT_TC_BP_REG 0x40 | |
368 | #define RCB_COM_CFG_PPE_TNL_CLKEN_REG 0x44 | |
918f618f | 369 | #define RCBV2_COM_CFG_USER_REG 0x30 |
370 | #define RCBV2_COM_CFG_TSO_MODE_REG 0x50 | |
511e6bc0 | 371 | |
372 | #define RCB_COM_INTMSK_TX_PKT_REG 0x3A0 | |
373 | #define RCB_COM_RINT_TX_PKT_REG 0x3A8 | |
374 | #define RCB_COM_INTMASK_ECC_ERR_REG 0x400 | |
375 | #define RCB_COM_INTSTS_ECC_ERR_REG 0x408 | |
376 | #define RCB_COM_EBD_SRAM_ERR_REG 0x410 | |
377 | #define RCB_COM_RXRING_ERR_REG 0x41C | |
378 | #define RCB_COM_TXRING_ERR_REG 0x420 | |
379 | #define RCB_COM_TX_FBD_ERR_REG 0x424 | |
380 | #define RCB_SRAM_ECC_CHK_EN_REG 0x428 | |
381 | #define RCB_SRAM_ECC_CHK0_REG 0x42C | |
382 | #define RCB_SRAM_ECC_CHK1_REG 0x430 | |
383 | #define RCB_SRAM_ECC_CHK2_REG 0x434 | |
384 | #define RCB_SRAM_ECC_CHK3_REG 0x438 | |
385 | #define RCB_SRAM_ECC_CHK4_REG 0x43c | |
386 | #define RCB_SRAM_ECC_CHK5_REG 0x440 | |
387 | #define RCB_ECC_ERR_ADDR0_REG 0x450 | |
388 | #define RCB_ECC_ERR_ADDR3_REG 0x45C | |
389 | #define RCB_ECC_ERR_ADDR4_REG 0x460 | |
390 | #define RCB_ECC_ERR_ADDR5_REG 0x464 | |
391 | ||
392 | #define RCB_COM_SF_CFG_INTMASK_RING 0x480 | |
393 | #define RCB_COM_SF_CFG_RING_STS 0x484 | |
394 | #define RCB_COM_SF_CFG_RING 0x488 | |
395 | #define RCB_COM_SF_CFG_INTMASK_BD 0x48C | |
396 | #define RCB_COM_SF_CFG_BD_RINT_STS 0x470 | |
397 | #define RCB_COM_RCB_RD_BD_BUSY 0x490 | |
398 | #define RCB_COM_RCB_FBD_CRT_EN 0x494 | |
399 | #define RCB_COM_AXI_WR_ERR_INTMASK 0x498 | |
400 | #define RCB_COM_AXI_ERR_STS 0x49C | |
401 | #define RCB_COM_CHK_TX_FBD_NUM_REG 0x4a0 | |
402 | ||
403 | #define RCB_CFG_BD_NUM_REG 0x9000 | |
404 | #define RCB_CFG_PKTLINE_REG 0x9050 | |
405 | ||
406 | #define RCB_CFG_OVERTIME_REG 0x9300 | |
407 | #define RCB_CFG_PKTLINE_INT_NUM_REG 0x9304 | |
408 | #define RCB_CFG_OVERTIME_INT_NUM_REG 0x9308 | |
43adc067 | 409 | #define RCB_PORT_CFG_OVERTIME_REG 0x9430 |
511e6bc0 | 410 | |
411 | #define RCB_RING_RX_RING_BASEADDR_L_REG 0x00000 | |
412 | #define RCB_RING_RX_RING_BASEADDR_H_REG 0x00004 | |
413 | #define RCB_RING_RX_RING_BD_NUM_REG 0x00008 | |
414 | #define RCB_RING_RX_RING_BD_LEN_REG 0x0000C | |
415 | #define RCB_RING_RX_RING_PKTLINE_REG 0x00010 | |
416 | #define RCB_RING_RX_RING_TAIL_REG 0x00018 | |
417 | #define RCB_RING_RX_RING_HEAD_REG 0x0001C | |
418 | #define RCB_RING_RX_RING_FBDNUM_REG 0x00020 | |
419 | #define RCB_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C | |
420 | ||
421 | #define RCB_RING_TX_RING_BASEADDR_L_REG 0x00040 | |
422 | #define RCB_RING_TX_RING_BASEADDR_H_REG 0x00044 | |
423 | #define RCB_RING_TX_RING_BD_NUM_REG 0x00048 | |
424 | #define RCB_RING_TX_RING_BD_LEN_REG 0x0004C | |
425 | #define RCB_RING_TX_RING_PKTLINE_REG 0x00050 | |
426 | #define RCB_RING_TX_RING_TAIL_REG 0x00058 | |
427 | #define RCB_RING_TX_RING_HEAD_REG 0x0005C | |
428 | #define RCB_RING_TX_RING_FBDNUM_REG 0x00060 | |
429 | #define RCB_RING_TX_RING_OFFSET_REG 0x00064 | |
430 | #define RCB_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C | |
431 | ||
432 | #define RCB_RING_PREFETCH_EN_REG 0x0007C | |
433 | #define RCB_RING_CFG_VF_NUM_REG 0x00080 | |
434 | #define RCB_RING_ASID_REG 0x0008C | |
435 | #define RCB_RING_RX_VM_REG 0x00090 | |
436 | #define RCB_RING_T0_BE_RST 0x00094 | |
437 | #define RCB_RING_COULD_BE_RST 0x00098 | |
438 | #define RCB_RING_WRR_WEIGHT_REG 0x0009c | |
439 | ||
440 | #define RCB_RING_INTMSK_RXWL_REG 0x000A0 | |
441 | #define RCB_RING_INTSTS_RX_RING_REG 0x000A4 | |
13ac695e | 442 | #define RCBV2_RX_RING_INT_STS_REG 0x000A8 |
511e6bc0 | 443 | #define RCB_RING_INTMSK_TXWL_REG 0x000AC |
444 | #define RCB_RING_INTSTS_TX_RING_REG 0x000B0 | |
13ac695e | 445 | #define RCBV2_TX_RING_INT_STS_REG 0x000B4 |
511e6bc0 | 446 | #define RCB_RING_INTMSK_RX_OVERTIME_REG 0x000B8 |
447 | #define RCB_RING_INTSTS_RX_OVERTIME_REG 0x000BC | |
448 | #define RCB_RING_INTMSK_TX_OVERTIME_REG 0x000C4 | |
449 | #define RCB_RING_INTSTS_TX_OVERTIME_REG 0x000C8 | |
450 | ||
451 | #define GMAC_DUPLEX_TYPE_REG 0x0008UL | |
452 | #define GMAC_FD_FC_TYPE_REG 0x000CUL | |
453 | #define GMAC_FC_TX_TIMER_REG 0x001CUL | |
454 | #define GMAC_FD_FC_ADDR_LOW_REG 0x0020UL | |
455 | #define GMAC_FD_FC_ADDR_HIGH_REG 0x0024UL | |
456 | #define GMAC_IPG_TX_TIMER_REG 0x0030UL | |
457 | #define GMAC_PAUSE_THR_REG 0x0038UL | |
458 | #define GMAC_MAX_FRM_SIZE_REG 0x003CUL | |
459 | #define GMAC_PORT_MODE_REG 0x0040UL | |
460 | #define GMAC_PORT_EN_REG 0x0044UL | |
461 | #define GMAC_PAUSE_EN_REG 0x0048UL | |
462 | #define GMAC_SHORT_RUNTS_THR_REG 0x0050UL | |
463 | #define GMAC_AN_NEG_STATE_REG 0x0058UL | |
464 | #define GMAC_TX_LOCAL_PAGE_REG 0x005CUL | |
465 | #define GMAC_TRANSMIT_CONTROL_REG 0x0060UL | |
466 | #define GMAC_REC_FILT_CONTROL_REG 0x0064UL | |
467 | #define GMAC_PTP_CONFIG_REG 0x0074UL | |
468 | ||
469 | #define GMAC_RX_OCTETS_TOTAL_OK_REG 0x0080UL | |
470 | #define GMAC_RX_OCTETS_BAD_REG 0x0084UL | |
471 | #define GMAC_RX_UC_PKTS_REG 0x0088UL | |
472 | #define GMAC_RX_MC_PKTS_REG 0x008CUL | |
473 | #define GMAC_RX_BC_PKTS_REG 0x0090UL | |
474 | #define GMAC_RX_PKTS_64OCTETS_REG 0x0094UL | |
475 | #define GMAC_RX_PKTS_65TO127OCTETS_REG 0x0098UL | |
476 | #define GMAC_RX_PKTS_128TO255OCTETS_REG 0x009CUL | |
477 | #define GMAC_RX_PKTS_255TO511OCTETS_REG 0x00A0UL | |
478 | #define GMAC_RX_PKTS_512TO1023OCTETS_REG 0x00A4UL | |
479 | #define GMAC_RX_PKTS_1024TO1518OCTETS_REG 0x00A8UL | |
480 | #define GMAC_RX_PKTS_1519TOMAXOCTETS_REG 0x00ACUL | |
481 | #define GMAC_RX_FCS_ERRORS_REG 0x00B0UL | |
482 | #define GMAC_RX_TAGGED_REG 0x00B4UL | |
483 | #define GMAC_RX_DATA_ERR_REG 0x00B8UL | |
484 | #define GMAC_RX_ALIGN_ERRORS_REG 0x00BCUL | |
485 | #define GMAC_RX_LONG_ERRORS_REG 0x00C0UL | |
486 | #define GMAC_RX_JABBER_ERRORS_REG 0x00C4UL | |
487 | #define GMAC_RX_PAUSE_MACCTRL_FRAM_REG 0x00C8UL | |
488 | #define GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG 0x00CCUL | |
489 | #define GMAC_RX_VERY_LONG_ERR_CNT_REG 0x00D0UL | |
490 | #define GMAC_RX_RUNT_ERR_CNT_REG 0x00D4UL | |
491 | #define GMAC_RX_SHORT_ERR_CNT_REG 0x00D8UL | |
492 | #define GMAC_RX_FILT_PKT_CNT_REG 0x00E8UL | |
493 | #define GMAC_RX_OCTETS_TOTAL_FILT_REG 0x00ECUL | |
494 | #define GMAC_OCTETS_TRANSMITTED_OK_REG 0x0100UL | |
495 | #define GMAC_OCTETS_TRANSMITTED_BAD_REG 0x0104UL | |
496 | #define GMAC_TX_UC_PKTS_REG 0x0108UL | |
497 | #define GMAC_TX_MC_PKTS_REG 0x010CUL | |
498 | #define GMAC_TX_BC_PKTS_REG 0x0110UL | |
499 | #define GMAC_TX_PKTS_64OCTETS_REG 0x0114UL | |
500 | #define GMAC_TX_PKTS_65TO127OCTETS_REG 0x0118UL | |
501 | #define GMAC_TX_PKTS_128TO255OCTETS_REG 0x011CUL | |
502 | #define GMAC_TX_PKTS_255TO511OCTETS_REG 0x0120UL | |
503 | #define GMAC_TX_PKTS_512TO1023OCTETS_REG 0x0124UL | |
504 | #define GMAC_TX_PKTS_1024TO1518OCTETS_REG 0x0128UL | |
505 | #define GMAC_TX_PKTS_1519TOMAXOCTETS_REG 0x012CUL | |
506 | #define GMAC_TX_EXCESSIVE_LENGTH_DROP_REG 0x014CUL | |
507 | #define GMAC_TX_UNDERRUN_REG 0x0150UL | |
508 | #define GMAC_TX_TAGGED_REG 0x0154UL | |
509 | #define GMAC_TX_CRC_ERROR_REG 0x0158UL | |
510 | #define GMAC_TX_PAUSE_FRAMES_REG 0x015CUL | |
511 | #define GAMC_RX_MAX_FRAME 0x0170UL | |
512 | #define GMAC_LINE_LOOP_BACK_REG 0x01A8UL | |
513 | #define GMAC_CF_CRC_STRIP_REG 0x01B0UL | |
514 | #define GMAC_MODE_CHANGE_EN_REG 0x01B4UL | |
515 | #define GMAC_SIXTEEN_BIT_CNTR_REG 0x01CCUL | |
516 | #define GMAC_LD_LINK_COUNTER_REG 0x01D0UL | |
517 | #define GMAC_LOOP_REG 0x01DCUL | |
518 | #define GMAC_RECV_CONTROL_REG 0x01E0UL | |
519 | #define GMAC_VLAN_CODE_REG 0x01E8UL | |
520 | #define GMAC_RX_OVERRUN_CNT_REG 0x01ECUL | |
521 | #define GMAC_RX_LENGTHFIELD_ERR_CNT_REG 0x01F4UL | |
522 | #define GMAC_RX_FAIL_COMMA_CNT_REG 0x01F8UL | |
523 | #define GMAC_STATION_ADDR_LOW_0_REG 0x0200UL | |
524 | #define GMAC_STATION_ADDR_HIGH_0_REG 0x0204UL | |
525 | #define GMAC_STATION_ADDR_LOW_1_REG 0x0208UL | |
526 | #define GMAC_STATION_ADDR_HIGH_1_REG 0x020CUL | |
527 | #define GMAC_STATION_ADDR_LOW_2_REG 0x0210UL | |
528 | #define GMAC_STATION_ADDR_HIGH_2_REG 0x0214UL | |
529 | #define GMAC_STATION_ADDR_LOW_3_REG 0x0218UL | |
530 | #define GMAC_STATION_ADDR_HIGH_3_REG 0x021CUL | |
531 | #define GMAC_STATION_ADDR_LOW_4_REG 0x0220UL | |
532 | #define GMAC_STATION_ADDR_HIGH_4_REG 0x0224UL | |
533 | #define GMAC_STATION_ADDR_LOW_5_REG 0x0228UL | |
534 | #define GMAC_STATION_ADDR_HIGH_5_REG 0x022CUL | |
535 | #define GMAC_STATION_ADDR_LOW_MSK_0_REG 0x0230UL | |
536 | #define GMAC_STATION_ADDR_HIGH_MSK_0_REG 0x0234UL | |
537 | #define GMAC_STATION_ADDR_LOW_MSK_1_REG 0x0238UL | |
538 | #define GMAC_STATION_ADDR_HIGH_MSK_1_REG 0x023CUL | |
539 | #define GMAC_MAC_SKIP_LEN_REG 0x0240UL | |
540 | #define GMAC_TX_LOOP_PKT_PRI_REG 0x0378UL | |
541 | ||
542 | #define XGMAC_INT_STATUS_REG 0x0 | |
543 | #define XGMAC_INT_ENABLE_REG 0x4 | |
544 | #define XGMAC_INT_SET_REG 0x8 | |
545 | #define XGMAC_IERR_U_INFO_REG 0xC | |
546 | #define XGMAC_OVF_INFO_REG 0x10 | |
547 | #define XGMAC_OVF_CNT_REG 0x14 | |
548 | #define XGMAC_PORT_MODE_REG 0x40 | |
549 | #define XGMAC_CLK_ENABLE_REG 0x44 | |
550 | #define XGMAC_RESET_REG 0x48 | |
551 | #define XGMAC_LINK_CONTROL_REG 0x50 | |
552 | #define XGMAC_LINK_STATUS_REG 0x54 | |
553 | #define XGMAC_SPARE_REG 0xC0 | |
554 | #define XGMAC_SPARE_CNT_REG 0xC4 | |
555 | ||
556 | #define XGMAC_MAC_ENABLE_REG 0x100 | |
557 | #define XGMAC_MAC_CONTROL_REG 0x104 | |
558 | #define XGMAC_MAC_IPG_REG 0x120 | |
559 | #define XGMAC_MAC_MSG_CRC_EN_REG 0x124 | |
560 | #define XGMAC_MAC_MSG_IMG_REG 0x128 | |
561 | #define XGMAC_MAC_MSG_FC_CFG_REG 0x12C | |
562 | #define XGMAC_MAC_MSG_TC_CFG_REG 0x130 | |
563 | #define XGMAC_MAC_PAD_SIZE_REG 0x134 | |
564 | #define XGMAC_MAC_MIN_PKT_SIZE_REG 0x138 | |
565 | #define XGMAC_MAC_MAX_PKT_SIZE_REG 0x13C | |
566 | #define XGMAC_MAC_PAUSE_CTRL_REG 0x160 | |
567 | #define XGMAC_MAC_PAUSE_TIME_REG 0x164 | |
568 | #define XGMAC_MAC_PAUSE_GAP_REG 0x168 | |
569 | #define XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG 0x16C | |
570 | #define XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG 0x170 | |
571 | #define XGMAC_MAC_PAUSE_PEER_MAC_H_REG 0x174 | |
572 | #define XGMAC_MAC_PAUSE_PEER_MAC_L_REG 0x178 | |
573 | #define XGMAC_MAC_PFC_PRI_EN_REG 0x17C | |
574 | #define XGMAC_MAC_1588_CTRL_REG 0x180 | |
575 | #define XGMAC_MAC_1588_TX_PORT_DLY_REG 0x184 | |
576 | #define XGMAC_MAC_1588_RX_PORT_DLY_REG 0x188 | |
577 | #define XGMAC_MAC_1588_ASYM_DLY_REG 0x18C | |
578 | #define XGMAC_MAC_1588_ADJUST_CFG_REG 0x190 | |
579 | #define XGMAC_MAC_Y1731_ETH_TYPE_REG 0x194 | |
580 | #define XGMAC_MAC_MIB_CONTROL_REG 0x198 | |
581 | #define XGMAC_MAC_WAN_RATE_ADJUST_REG 0x19C | |
582 | #define XGMAC_MAC_TX_ERR_MARK_REG 0x1A0 | |
583 | #define XGMAC_MAC_TX_LF_RF_CONTROL_REG 0x1A4 | |
584 | #define XGMAC_MAC_RX_LF_RF_STATUS_REG 0x1A8 | |
585 | #define XGMAC_MAC_TX_RUNT_PKT_CNT_REG 0x1C0 | |
586 | #define XGMAC_MAC_RX_RUNT_PKT_CNT_REG 0x1C4 | |
587 | #define XGMAC_MAC_RX_PREAM_ERR_PKT_CNT_REG 0x1C8 | |
588 | #define XGMAC_MAC_TX_LF_RF_TERM_PKT_CNT_REG 0x1CC | |
589 | #define XGMAC_MAC_TX_SN_MISMATCH_PKT_CNT_REG 0x1D0 | |
590 | #define XGMAC_MAC_RX_ERR_MSG_CNT_REG 0x1D4 | |
591 | #define XGMAC_MAC_RX_ERR_EFD_CNT_REG 0x1D8 | |
592 | #define XGMAC_MAC_ERR_INFO_REG 0x1DC | |
593 | #define XGMAC_MAC_DBG_INFO_REG 0x1E0 | |
594 | ||
595 | #define XGMAC_PCS_BASER_SYNC_THD_REG 0x330 | |
596 | #define XGMAC_PCS_STATUS1_REG 0x404 | |
597 | #define XGMAC_PCS_BASER_STATUS1_REG 0x410 | |
598 | #define XGMAC_PCS_BASER_STATUS2_REG 0x414 | |
599 | #define XGMAC_PCS_BASER_SEEDA_0_REG 0x420 | |
600 | #define XGMAC_PCS_BASER_SEEDA_1_REG 0x424 | |
601 | #define XGMAC_PCS_BASER_SEEDB_0_REG 0x428 | |
602 | #define XGMAC_PCS_BASER_SEEDB_1_REG 0x42C | |
603 | #define XGMAC_PCS_BASER_TEST_CONTROL_REG 0x430 | |
604 | #define XGMAC_PCS_BASER_TEST_ERR_CNT_REG 0x434 | |
605 | #define XGMAC_PCS_DBG_INFO_REG 0x4C0 | |
606 | #define XGMAC_PCS_DBG_INFO1_REG 0x4C4 | |
607 | #define XGMAC_PCS_DBG_INFO2_REG 0x4C8 | |
608 | #define XGMAC_PCS_DBG_INFO3_REG 0x4CC | |
609 | ||
610 | #define XGMAC_PMA_ENABLE_REG 0x700 | |
611 | #define XGMAC_PMA_CONTROL_REG 0x704 | |
612 | #define XGMAC_PMA_SIGNAL_STATUS_REG 0x708 | |
613 | #define XGMAC_PMA_DBG_INFO_REG 0x70C | |
614 | #define XGMAC_PMA_FEC_ABILITY_REG 0x740 | |
615 | #define XGMAC_PMA_FEC_CONTROL_REG 0x744 | |
616 | #define XGMAC_PMA_FEC_CORR_BLOCK_CNT__REG 0x750 | |
617 | #define XGMAC_PMA_FEC_UNCORR_BLOCK_CNT__REG 0x760 | |
618 | ||
619 | #define XGMAC_TX_PKTS_FRAGMENT 0x0000 | |
620 | #define XGMAC_TX_PKTS_UNDERSIZE 0x0008 | |
621 | #define XGMAC_TX_PKTS_UNDERMIN 0x0010 | |
622 | #define XGMAC_TX_PKTS_64OCTETS 0x0018 | |
623 | #define XGMAC_TX_PKTS_65TO127OCTETS 0x0020 | |
624 | #define XGMAC_TX_PKTS_128TO255OCTETS 0x0028 | |
625 | #define XGMAC_TX_PKTS_256TO511OCTETS 0x0030 | |
626 | #define XGMAC_TX_PKTS_512TO1023OCTETS 0x0038 | |
627 | #define XGMAC_TX_PKTS_1024TO1518OCTETS 0x0040 | |
628 | #define XGMAC_TX_PKTS_1519TOMAXOCTETS 0x0048 | |
629 | #define XGMAC_TX_PKTS_1519TOMAXOCTETSOK 0x0050 | |
630 | #define XGMAC_TX_PKTS_OVERSIZE 0x0058 | |
631 | #define XGMAC_TX_PKTS_JABBER 0x0060 | |
632 | #define XGMAC_TX_GOODPKTS 0x0068 | |
633 | #define XGMAC_TX_GOODOCTETS 0x0070 | |
634 | #define XGMAC_TX_TOTAL_PKTS 0x0078 | |
635 | #define XGMAC_TX_TOTALOCTETS 0x0080 | |
636 | #define XGMAC_TX_UNICASTPKTS 0x0088 | |
637 | #define XGMAC_TX_MULTICASTPKTS 0x0090 | |
638 | #define XGMAC_TX_BROADCASTPKTS 0x0098 | |
639 | #define XGMAC_TX_PRI0PAUSEPKTS 0x00a0 | |
640 | #define XGMAC_TX_PRI1PAUSEPKTS 0x00a8 | |
641 | #define XGMAC_TX_PRI2PAUSEPKTS 0x00b0 | |
642 | #define XGMAC_TX_PRI3PAUSEPKTS 0x00b8 | |
643 | #define XGMAC_TX_PRI4PAUSEPKTS 0x00c0 | |
644 | #define XGMAC_TX_PRI5PAUSEPKTS 0x00c8 | |
645 | #define XGMAC_TX_PRI6PAUSEPKTS 0x00d0 | |
646 | #define XGMAC_TX_PRI7PAUSEPKTS 0x00d8 | |
647 | #define XGMAC_TX_MACCTRLPKTS 0x00e0 | |
648 | #define XGMAC_TX_1731PKTS 0x00e8 | |
649 | #define XGMAC_TX_1588PKTS 0x00f0 | |
650 | #define XGMAC_RX_FROMAPPGOODPKTS 0x00f8 | |
651 | #define XGMAC_RX_FROMAPPBADPKTS 0x0100 | |
652 | #define XGMAC_TX_ERRALLPKTS 0x0108 | |
653 | ||
654 | #define XGMAC_RX_PKTS_FRAGMENT 0x0110 | |
655 | #define XGMAC_RX_PKTSUNDERSIZE 0x0118 | |
656 | #define XGMAC_RX_PKTS_UNDERMIN 0x0120 | |
657 | #define XGMAC_RX_PKTS_64OCTETS 0x0128 | |
658 | #define XGMAC_RX_PKTS_65TO127OCTETS 0x0130 | |
659 | #define XGMAC_RX_PKTS_128TO255OCTETS 0x0138 | |
660 | #define XGMAC_RX_PKTS_256TO511OCTETS 0x0140 | |
661 | #define XGMAC_RX_PKTS_512TO1023OCTETS 0x0148 | |
662 | #define XGMAC_RX_PKTS_1024TO1518OCTETS 0x0150 | |
663 | #define XGMAC_RX_PKTS_1519TOMAXOCTETS 0x0158 | |
664 | #define XGMAC_RX_PKTS_1519TOMAXOCTETSOK 0x0160 | |
665 | #define XGMAC_RX_PKTS_OVERSIZE 0x0168 | |
666 | #define XGMAC_RX_PKTS_JABBER 0x0170 | |
667 | #define XGMAC_RX_GOODPKTS 0x0178 | |
668 | #define XGMAC_RX_GOODOCTETS 0x0180 | |
669 | #define XGMAC_RX_TOTAL_PKTS 0x0188 | |
670 | #define XGMAC_RX_TOTALOCTETS 0x0190 | |
671 | #define XGMAC_RX_UNICASTPKTS 0x0198 | |
672 | #define XGMAC_RX_MULTICASTPKTS 0x01a0 | |
673 | #define XGMAC_RX_BROADCASTPKTS 0x01a8 | |
674 | #define XGMAC_RX_PRI0PAUSEPKTS 0x01b0 | |
675 | #define XGMAC_RX_PRI1PAUSEPKTS 0x01b8 | |
676 | #define XGMAC_RX_PRI2PAUSEPKTS 0x01c0 | |
677 | #define XGMAC_RX_PRI3PAUSEPKTS 0x01c8 | |
678 | #define XGMAC_RX_PRI4PAUSEPKTS 0x01d0 | |
679 | #define XGMAC_RX_PRI5PAUSEPKTS 0x01d8 | |
680 | #define XGMAC_RX_PRI6PAUSEPKTS 0x01e0 | |
681 | #define XGMAC_RX_PRI7PAUSEPKTS 0x01e8 | |
682 | #define XGMAC_RX_MACCTRLPKTS 0x01f0 | |
683 | #define XGMAC_TX_SENDAPPGOODPKTS 0x01f8 | |
684 | #define XGMAC_TX_SENDAPPBADPKTS 0x0200 | |
685 | #define XGMAC_RX_1731PKTS 0x0208 | |
686 | #define XGMAC_RX_SYMBOLERRPKTS 0x0210 | |
687 | #define XGMAC_RX_FCSERRPKTS 0x0218 | |
688 | ||
689 | #define XGMAC_TRX_CORE_SRST_M 0x2080 | |
690 | ||
13ac695e S |
691 | #define DSAF_SRAM_INIT_OVER_M 0xff |
692 | #define DSAFV2_SRAM_INIT_OVER_M 0x3ff | |
693 | #define DSAF_SRAM_INIT_OVER_S 0 | |
694 | ||
511e6bc0 | 695 | #define DSAF_CFG_EN_S 0 |
696 | #define DSAF_CFG_TC_MODE_S 1 | |
697 | #define DSAF_CFG_CRC_EN_S 2 | |
698 | #define DSAF_CFG_SBM_INIT_S 3 | |
699 | #define DSAF_CFG_MIX_MODE_S 4 | |
700 | #define DSAF_CFG_STP_MODE_S 5 | |
701 | #define DSAF_CFG_LOCA_ADDR_EN_S 6 | |
13ac695e | 702 | #define DSAFV2_CFG_VLAN_TAG_MODE_S 17 |
511e6bc0 | 703 | |
704 | #define DSAF_CNT_CLR_CE_S 0 | |
705 | #define DSAF_SNAP_EN_S 1 | |
706 | ||
707 | #define HNS_DSAF_PFC_UNIT_CNT_FOR_XGE 41 | |
708 | #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000 410 | |
709 | #define HNS_DSAF_PFC_UNIT_CNT_FOR_GE_2500 103 | |
710 | ||
711 | #define DSAF_PFC_UNINT_CNT_M ((1ULL << 9) - 1) | |
712 | #define DSAF_PFC_UNINT_CNT_S 0 | |
713 | ||
714 | #define DSAF_PPE_QID_CFG_M 0xFF | |
715 | #define DSAF_PPE_QID_CFG_S 0 | |
716 | ||
717 | #define DSAF_SW_PORT_TYPE_M 3 | |
718 | #define DSAF_SW_PORT_TYPE_S 0 | |
719 | ||
720 | #define DSAF_STP_PORT_TYPE_M 7 | |
721 | #define DSAF_STP_PORT_TYPE_S 0 | |
722 | ||
723 | #define DSAF_INODE_IN_PORT_NUM_M 7 | |
724 | #define DSAF_INODE_IN_PORT_NUM_S 0 | |
13ac695e S |
725 | #define DSAFV2_INODE_IN_PORT1_NUM_M (7ULL << 3) |
726 | #define DSAFV2_INODE_IN_PORT1_NUM_S 3 | |
727 | #define DSAFV2_INODE_IN_PORT2_NUM_M (7ULL << 6) | |
728 | #define DSAFV2_INODE_IN_PORT2_NUM_S 6 | |
729 | #define DSAFV2_INODE_IN_PORT3_NUM_M (7ULL << 9) | |
730 | #define DSAFV2_INODE_IN_PORT3_NUM_S 9 | |
731 | #define DSAFV2_INODE_IN_PORT4_NUM_M (7ULL << 12) | |
732 | #define DSAFV2_INODE_IN_PORT4_NUM_S 12 | |
733 | #define DSAFV2_INODE_IN_PORT5_NUM_M (7ULL << 15) | |
734 | #define DSAFV2_INODE_IN_PORT5_NUM_S 15 | |
511e6bc0 | 735 | |
736 | #define HNS_DSAF_I4TC_CFG 0x18688688 | |
737 | #define HNS_DSAF_I8TC_CFG 0x18FAC688 | |
738 | ||
739 | #define DSAF_SBM_CFG_SHCUT_EN_S 0 | |
740 | #define DSAF_SBM_CFG_EN_S 1 | |
741 | #define DSAF_SBM_CFG_MIB_EN_S 2 | |
742 | #define DSAF_SBM_CFG_ECC_INVERT_EN_S 3 | |
743 | ||
744 | #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S 0 | |
745 | #define DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0) | |
746 | #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S 10 | |
747 | #define DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10) | |
748 | #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S 20 | |
749 | #define DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 11) - 1) << 20) | |
750 | ||
751 | #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S 0 | |
752 | #define DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 0) | |
753 | #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S 10 | |
754 | #define DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 10) | |
755 | ||
756 | #define DSAF_SBM_CFG2_SET_BUF_NUM_S 0 | |
757 | #define DSAF_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 10) - 1) << 0) | |
758 | #define DSAF_SBM_CFG2_RESET_BUF_NUM_S 10 | |
759 | #define DSAF_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 10) - 1) << 10) | |
760 | ||
761 | #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0 | |
762 | #define DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 0) | |
763 | #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 10 | |
764 | #define DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 10) - 1) << 10) | |
765 | ||
13ac695e S |
766 | #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S 0 |
767 | #define DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0) | |
768 | #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S 9 | |
769 | #define DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9) | |
770 | #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S 18 | |
771 | #define DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M (((1ULL << 10) - 1) << 18) | |
772 | ||
773 | #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S 0 | |
774 | #define DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 0) | |
775 | #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S 9 | |
776 | #define DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M (((1ULL << 9) - 1) << 9) | |
777 | ||
778 | #define DSAFV2_SBM_CFG2_SET_BUF_NUM_S 0 | |
779 | #define DSAFV2_SBM_CFG2_SET_BUF_NUM_M (((1ULL << 9) - 1) << 0) | |
780 | #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_S 9 | |
781 | #define DSAFV2_SBM_CFG2_RESET_BUF_NUM_M (((1ULL << 9) - 1) << 9) | |
782 | ||
783 | #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S 0 | |
784 | #define DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0) | |
785 | #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S 9 | |
786 | #define DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9) | |
787 | ||
788 | #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S 0 | |
789 | #define DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 0) | |
790 | #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S 9 | |
791 | #define DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M (((1ULL << 9) - 1) << 9) | |
792 | ||
511e6bc0 | 793 | #define DSAF_TBL_TCAM_ADDR_S 0 |
794 | #define DSAF_TBL_TCAM_ADDR_M ((1ULL << 9) - 1) | |
795 | ||
796 | #define DSAF_TBL_LINE_ADDR_S 0 | |
797 | #define DSAF_TBL_LINE_ADDR_M ((1ULL << 15) - 1) | |
798 | ||
799 | #define DSAF_TBL_MCAST_CFG4_VM128_112_S 0 | |
800 | #define DSAF_TBL_MCAST_CFG4_VM128_112_M (((1ULL << 7) - 1) << 0) | |
801 | #define DSAF_TBL_MCAST_CFG4_ITEM_VLD_S 7 | |
802 | #define DSAF_TBL_MCAST_CFG4_OLD_EN_S 8 | |
803 | ||
804 | #define DSAF_TBL_MCAST_CFG0_XGE5_0_S 0 | |
805 | #define DSAF_TBL_MCAST_CFG0_XGE5_0_M (((1ULL << 6) - 1) << 0) | |
806 | #define DSAF_TBL_MCAST_CFG0_VM25_0_S 6 | |
807 | #define DSAF_TBL_MCAST_CFG0_VM25_0_M (((1ULL << 26) - 1) << 6) | |
808 | ||
809 | #define DSAF_TBL_UCAST_CFG1_OUT_PORT_S 0 | |
810 | #define DSAF_TBL_UCAST_CFG1_OUT_PORT_M (((1ULL << 8) - 1) << 0) | |
811 | #define DSAF_TBL_UCAST_CFG1_DVC_S 8 | |
812 | #define DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S 9 | |
813 | #define DSAF_TBL_UCAST_CFG1_ITEM_VLD_S 10 | |
814 | #define DSAF_TBL_UCAST_CFG1_OLD_EN_S 11 | |
815 | ||
816 | #define DSAF_TBL_LINE_CFG_OUT_PORT_S 0 | |
817 | #define DSAF_TBL_LINE_CFG_OUT_PORT_M (((1ULL << 8) - 1) << 0) | |
818 | #define DSAF_TBL_LINE_CFG_DVC_S 8 | |
819 | #define DSAF_TBL_LINE_CFG_MAC_DISCARD_S 9 | |
820 | ||
821 | #define DSAF_TBL_PUL_OLD_RSLT_RE_S 0 | |
822 | #define DSAF_TBL_PUL_MCAST_VLD_S 1 | |
823 | #define DSAF_TBL_PUL_TCAM_DATA_VLD_S 2 | |
824 | #define DSAF_TBL_PUL_UCAST_VLD_S 3 | |
825 | #define DSAF_TBL_PUL_LINE_VLD_S 4 | |
826 | #define DSAF_TBL_PUL_TCAM_LOAD_S 5 | |
827 | #define DSAF_TBL_PUL_LINE_LOAD_S 6 | |
828 | ||
829 | #define DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S 0 | |
830 | #define DSAF_TBL_DFX_UC_LKUP_NUM_EN_S 1 | |
831 | #define DSAF_TBL_DFX_MC_LKUP_NUM_EN_S 2 | |
832 | #define DSAF_TBL_DFX_BC_LKUP_NUM_EN_S 3 | |
833 | #define DSAF_TBL_DFX_RAM_ERR_INJECT_EN_S 4 | |
834 | ||
835 | #define DSAF_VOQ_BP_ALL_DOWNTHRD_S 0 | |
836 | #define DSAF_VOQ_BP_ALL_DOWNTHRD_M (((1ULL << 10) - 1) << 0) | |
837 | #define DSAF_VOQ_BP_ALL_UPTHRD_S 10 | |
838 | #define DSAF_VOQ_BP_ALL_UPTHRD_M (((1ULL << 10) - 1) << 10) | |
839 | ||
840 | #define DSAF_XGE_GE_WORK_MODE_S 0 | |
841 | #define DSAF_XGE_GE_LOOPBACK_S 1 | |
842 | ||
843 | #define DSAF_FC_XGE_TX_PAUSE_S 0 | |
844 | #define DSAF_REGS_XGE_CNT_CAR_S 1 | |
845 | ||
846 | #define PPE_CFG_QID_MODE_DEF_QID_S 0 | |
847 | #define PPE_CFG_QID_MODE_DEF_QID_M (0xff << PPE_CFG_QID_MODE_DEF_QID_S) | |
848 | ||
849 | #define PPE_CFG_QID_MODE_CF_QID_MODE_S 8 | |
850 | #define PPE_CFG_QID_MODE_CF_QID_MODE_M (0x7 << PPE_CFG_QID_MODE_CF_QID_MODE_S) | |
851 | ||
6bc0ce7d S |
852 | #define PPEV2_CFG_RSS_TBL_4N0_S 0 |
853 | #define PPEV2_CFG_RSS_TBL_4N0_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N0_S) | |
854 | ||
855 | #define PPEV2_CFG_RSS_TBL_4N1_S 8 | |
856 | #define PPEV2_CFG_RSS_TBL_4N1_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N1_S) | |
857 | ||
858 | #define PPEV2_CFG_RSS_TBL_4N2_S 16 | |
859 | #define PPEV2_CFG_RSS_TBL_4N2_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N2_S) | |
860 | ||
861 | #define PPEV2_CFG_RSS_TBL_4N3_S 24 | |
862 | #define PPEV2_CFG_RSS_TBL_4N3_M (((1UL << 5) - 1) << PPEV2_CFG_RSS_TBL_4N3_S) | |
863 | ||
68c222a6 | 864 | #define DSAFV2_SERDES_LBK_EN_B 8 |
865 | #define DSAFV2_SERDES_LBK_QID_S 0 | |
866 | #define DSAFV2_SERDES_LBK_QID_M (((1UL << 8) - 1) << DSAFV2_SERDES_LBK_QID_S) | |
867 | ||
511e6bc0 | 868 | #define PPE_CNT_CLR_CE_B 0 |
869 | #define PPE_CNT_CLR_SNAP_EN_B 1 | |
870 | ||
871 | #define PPE_COMMON_CNT_CLR_CE_B 0 | |
872 | #define PPE_COMMON_CNT_CLR_SNAP_EN_B 1 | |
918f618f | 873 | #define RCB_COM_TSO_MODE_B 0 |
874 | #define RCB_COM_CFG_FNA_B 1 | |
875 | #define RCB_COM_CFG_FA_B 0 | |
511e6bc0 | 876 | |
877 | #define GMAC_DUPLEX_TYPE_B 0 | |
878 | ||
879 | #define GMAC_FC_TX_TIMER_S 0 | |
880 | #define GMAC_FC_TX_TIMER_M 0xffff | |
881 | ||
882 | #define GMAC_MAX_FRM_SIZE_S 0 | |
883 | #define GMAC_MAX_FRM_SIZE_M 0xffff | |
884 | ||
885 | #define GMAC_PORT_MODE_S 0 | |
886 | #define GMAC_PORT_MODE_M 0xf | |
887 | ||
888 | #define GMAC_RGMII_1000M_DELAY_B 4 | |
889 | #define GMAC_MII_TX_EDGE_SEL_B 5 | |
890 | #define GMAC_FIFO_ERR_AUTO_RST_B 6 | |
891 | #define GMAC_DBG_CLK_LOS_MSK_B 7 | |
892 | ||
893 | #define GMAC_PORT_RX_EN_B 1 | |
894 | #define GMAC_PORT_TX_EN_B 2 | |
895 | ||
896 | #define GMAC_PAUSE_EN_RX_FDFC_B 0 | |
897 | #define GMAC_PAUSE_EN_TX_FDFC_B 1 | |
898 | #define GMAC_PAUSE_EN_TX_HDFC_B 2 | |
899 | ||
900 | #define GMAC_SHORT_RUNTS_THR_S 0 | |
901 | #define GMAC_SHORT_RUNTS_THR_M 0x1f | |
902 | ||
903 | #define GMAC_AN_NEG_STAT_FD_B 5 | |
904 | #define GMAC_AN_NEG_STAT_HD_B 6 | |
905 | #define GMAC_AN_NEG_STAT_RF1_DUPLIEX_B 12 | |
906 | #define GMAC_AN_NEG_STAT_RF2_B 13 | |
907 | ||
908 | #define GMAC_AN_NEG_STAT_NP_LNK_OK_B 15 | |
909 | #define GMAC_AN_NEG_STAT_RX_SYNC_OK_B 20 | |
910 | #define GMAC_AN_NEG_STAT_AN_DONE_B 21 | |
911 | ||
912 | #define GMAC_AN_NEG_STAT_PS_S 7 | |
913 | #define GMAC_AN_NEG_STAT_PS_M (0x3 << GMAC_AN_NEG_STAT_PS_S) | |
914 | ||
915 | #define GMAC_AN_NEG_STAT_SPEED_S 10 | |
916 | #define GMAC_AN_NEG_STAT_SPEED_M (0x3 << GMAC_AN_NEG_STAT_SPEED_S) | |
917 | ||
918 | #define GMAC_TX_AN_EN_B 5 | |
919 | #define GMAC_TX_CRC_ADD_B 6 | |
920 | #define GMAC_TX_PAD_EN_B 7 | |
921 | ||
922 | #define GMAC_LINE_LOOPBACK_B 0 | |
923 | ||
924 | #define GMAC_LP_REG_CF_EXT_DRV_LP_B 1 | |
925 | #define GMAC_LP_REG_CF2MI_LP_EN_B 2 | |
926 | ||
927 | #define GMAC_MODE_CHANGE_EB_B 0 | |
d5679849 KY |
928 | #define GMAC_UC_MATCH_EN_B 0 |
929 | #define GMAC_ADDR_EN_B 16 | |
511e6bc0 | 930 | |
931 | #define GMAC_RECV_CTRL_STRIP_PAD_EN_B 3 | |
932 | #define GMAC_RECV_CTRL_RUNT_PKT_EN_B 4 | |
933 | ||
934 | #define GMAC_TX_LOOP_PKT_HIG_PRI_B 0 | |
935 | #define GMAC_TX_LOOP_PKT_EN_B 1 | |
936 | ||
937 | #define XGMAC_PORT_MODE_TX_S 0x0 | |
938 | #define XGMAC_PORT_MODE_TX_M (0x3 << XGMAC_PORT_MODE_TX_S) | |
939 | #define XGMAC_PORT_MODE_TX_40G_B 0x3 | |
940 | #define XGMAC_PORT_MODE_RX_S 0x4 | |
941 | #define XGMAC_PORT_MODE_RX_M (0x3 << XGMAC_PORT_MODE_RX_S) | |
942 | #define XGMAC_PORT_MODE_RX_40G_B 0x7 | |
943 | ||
944 | #define XGMAC_ENABLE_TX_B 0 | |
945 | #define XGMAC_ENABLE_RX_B 1 | |
946 | ||
947 | #define XGMAC_CTL_TX_FCS_B 0 | |
948 | #define XGMAC_CTL_TX_PAD_B 1 | |
949 | #define XGMAC_CTL_TX_PREAMBLE_TRANS_B 3 | |
950 | #define XGMAC_CTL_TX_UNDER_MIN_ERR_B 4 | |
951 | #define XGMAC_CTL_TX_TRUNCATE_B 5 | |
952 | #define XGMAC_CTL_TX_1588_B 8 | |
953 | #define XGMAC_CTL_TX_1731_B 9 | |
954 | #define XGMAC_CTL_TX_PFC_B 10 | |
955 | #define XGMAC_CTL_RX_FCS_B 16 | |
956 | #define XGMAC_CTL_RX_FCS_STRIP_B 17 | |
957 | #define XGMAC_CTL_RX_PREAMBLE_TRANS_B 19 | |
958 | #define XGMAC_CTL_RX_UNDER_MIN_ERR_B 20 | |
959 | #define XGMAC_CTL_RX_TRUNCATE_B 21 | |
960 | #define XGMAC_CTL_RX_1588_B 24 | |
961 | #define XGMAC_CTL_RX_1731_B 25 | |
962 | #define XGMAC_CTL_RX_PFC_B 26 | |
963 | ||
964 | #define XGMAC_PMA_FEC_CTL_TX_B 0 | |
965 | #define XGMAC_PMA_FEC_CTL_RX_B 1 | |
966 | #define XGMAC_PMA_FEC_CTL_ERR_EN 2 | |
967 | #define XGMAC_PMA_FEC_CTL_ERR_SH 3 | |
968 | ||
969 | #define XGMAC_PAUSE_CTL_TX_B 0 | |
970 | #define XGMAC_PAUSE_CTL_RX_B 1 | |
971 | #define XGMAC_PAUSE_CTL_RSP_MODE_B 2 | |
972 | #define XGMAC_PAUSE_CTL_TX_XOFF_B 3 | |
973 | ||
946973a3 | 974 | static inline void dsaf_write_reg(void __iomem *base, u32 reg, u32 value) |
511e6bc0 | 975 | { |
976 | u8 __iomem *reg_addr = ACCESS_ONCE(base); | |
977 | ||
978 | writel(value, reg_addr + reg); | |
979 | } | |
980 | ||
981 | #define dsaf_write_dev(a, reg, value) \ | |
982 | dsaf_write_reg((a)->io_base, (reg), (value)) | |
983 | ||
946973a3 | 984 | static inline u32 dsaf_read_reg(u8 __iomem *base, u32 reg) |
511e6bc0 | 985 | { |
986 | u8 __iomem *reg_addr = ACCESS_ONCE(base); | |
987 | ||
988 | return readl(reg_addr + reg); | |
989 | } | |
990 | ||
991 | #define dsaf_read_dev(a, reg) \ | |
992 | dsaf_read_reg((a)->io_base, (reg)) | |
993 | ||
994 | #define dsaf_set_field(origin, mask, shift, val) \ | |
995 | do { \ | |
996 | (origin) &= (~(mask)); \ | |
997 | (origin) |= (((val) << (shift)) & (mask)); \ | |
998 | } while (0) | |
999 | ||
1000 | #define dsaf_set_bit(origin, shift, val) \ | |
1001 | dsaf_set_field((origin), (1ull << (shift)), (shift), (val)) | |
1002 | ||
946973a3 AS |
1003 | static inline void dsaf_set_reg_field(void __iomem *base, u32 reg, u32 mask, |
1004 | u32 shift, u32 val) | |
511e6bc0 | 1005 | { |
1006 | u32 origin = dsaf_read_reg(base, reg); | |
1007 | ||
1008 | dsaf_set_field(origin, mask, shift, val); | |
1009 | dsaf_write_reg(base, reg, origin); | |
1010 | } | |
1011 | ||
1012 | #define dsaf_set_dev_field(dev, reg, mask, shift, val) \ | |
1013 | dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val)) | |
1014 | ||
1015 | #define dsaf_set_dev_bit(dev, reg, bit, val) \ | |
1016 | dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val)) | |
1017 | ||
1018 | #define dsaf_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) | |
1019 | ||
1020 | #define dsaf_get_bit(origin, shift) \ | |
1021 | dsaf_get_field((origin), (1ull << (shift)), (shift)) | |
1022 | ||
946973a3 AS |
1023 | static inline u32 dsaf_get_reg_field(void __iomem *base, u32 reg, u32 mask, |
1024 | u32 shift) | |
511e6bc0 | 1025 | { |
1026 | u32 origin; | |
1027 | ||
1028 | origin = dsaf_read_reg(base, reg); | |
1029 | return dsaf_get_field(origin, mask, shift); | |
1030 | } | |
1031 | ||
1032 | #define dsaf_get_dev_field(dev, reg, mask, shift) \ | |
1033 | dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift)) | |
1034 | ||
1035 | #define dsaf_get_dev_bit(dev, reg, bit) \ | |
1036 | dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit)) | |
1037 | ||
1038 | #define dsaf_write_b(addr, data)\ | |
1039 | writeb((data), (__iomem unsigned char *)(addr)) | |
1040 | #define dsaf_read_b(addr)\ | |
1041 | readb((__iomem unsigned char *)(addr)) | |
1042 | ||
1043 | #define hns_mac_reg_read64(drv, offset) \ | |
e4600d69 | 1044 | readq((__iomem void *)(((u8 *)(drv)->io_base + 0xc00 + (offset)))) |
511e6bc0 | 1045 | |
1046 | #endif /* _DSAF_REG_H */ |