[deliverable/linux.git] / drivers / net / ethernet / hisilicon / hns_mdio.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/acpi.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spinlock_types.h>

#define MDIO_DRV_NAME "Hi-HNS_MDIO"
#define MDIO_BUS_NAME "Hisilicon MII Bus"
#define MDIO_DRV_VERSION "1.3.0"
#define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
#define MDIO_DRV_STRING MDIO_BUS_NAME
#define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME

#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)

#define MDIO_TIMEOUT			1000000

struct hns_mdio_sc_reg {
	u16 mdio_clk_en;
	u16 mdio_clk_dis;
	u16 mdio_reset_req;
	u16 mdio_reset_dreq;
	u16 mdio_clk_st;
	u16 mdio_reset_st;
};

struct hns_mdio_device {
	void *vbase;		/* mdio reg base address */
	struct regmap *subctrl_vbase;
	struct hns_mdio_sc_reg sc_reg;
};

/* mdio reg */
#define MDIO_COMMAND_REG		0x0
#define MDIO_ADDR_REG			0x4
#define MDIO_WDATA_REG			0x8
#define MDIO_RDATA_REG			0xc
#define MDIO_STA_REG			0x10

/* cfg phy bit map */
#define MDIO_CMD_DEVAD_M	0x1f
#define MDIO_CMD_DEVAD_S	0
#define MDIO_CMD_PRTAD_M	0x1f
#define MDIO_CMD_PRTAD_S	5
#define MDIO_CMD_OP_M		0x3
#define MDIO_CMD_OP_S		10
#define MDIO_CMD_ST_M		0x3
#define MDIO_CMD_ST_S		12
#define MDIO_CMD_START_B	14

#define MDIO_ADDR_DATA_M	0xffff
#define MDIO_ADDR_DATA_S	0

#define MDIO_WDATA_DATA_M	0xffff
#define MDIO_WDATA_DATA_S	0

#define MDIO_RDATA_DATA_M	0xffff
#define MDIO_RDATA_DATA_S	0

#define MDIO_STATE_STA_B	0

enum mdio_st_clause {
	MDIO_ST_CLAUSE_45 = 0,
	MDIO_ST_CLAUSE_22
};

enum mdio_c22_op_seq {
	MDIO_C22_WRITE = 1,
	MDIO_C22_READ = 2
};

enum mdio_c45_op_seq {
	MDIO_C45_WRITE_ADDR = 0,
	MDIO_C45_WRITE_DATA,
	MDIO_C45_READ_INCREMENT,
	MDIO_C45_READ
};

/* peri subctrl reg */
#define MDIO_SC_CLK_EN		0x338
#define MDIO_SC_CLK_DIS		0x33C
#define MDIO_SC_RESET_REQ	0xA38
#define MDIO_SC_RESET_DREQ	0xA3C
#define MDIO_SC_CLK_ST		0x531C
#define MDIO_SC_RESET_ST	0x5A1C

static void mdio_write_reg(void *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	writel_relaxed(value, reg_addr + reg);
}

#define MDIO_WRITE_REG(a, reg, value) \
	mdio_write_reg((a)->vbase, (reg), (value))

static u32 mdio_read_reg(void *base, u32 reg)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	return readl_relaxed(reg_addr + reg);
}

#define mdio_set_field(origin, mask, shift, val) \
	do { \
		(origin) &= (~((mask) << (shift))); \
		(origin) |= (((val) & (mask)) << (shift)); \
	} while (0)

#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))

static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
			       u32 val)
{
	u32 origin = mdio_read_reg(base, reg);

	mdio_set_field(origin, mask, shift, val);
	mdio_write_reg(base, reg, origin);
}

#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))

static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
{
	u32 origin;

	origin = mdio_read_reg(base, reg);
	return mdio_get_field(origin, mask, shift);
}

#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
		mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))

#define MDIO_GET_REG_BIT(dev, reg, bit) \
		mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))

#define MDIO_CHECK_SET_ST	1
#define MDIO_CHECK_CLR_ST	0

static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
				 u32 cfg_reg, u32 set_val,
				 u32 st_reg, u32 st_msk, u8 check_st)
{
	u32 time_cnt;
	u32 reg_value;

	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);

	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
		regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
		reg_value &= st_msk;
		if ((!!check_st) == (!!reg_value))
			break;
	}

	if ((!!check_st) != (!!reg_value))
		return -EBUSY;

	return 0;
}

static int hns_mdio_wait_ready(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = bus->priv;
	int i;
	u32 cmd_reg_value = 1;

	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	/* after that can do read or write*/
	for (i = 0; cmd_reg_value; i++) {
		cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
						 MDIO_COMMAND_REG,
						 MDIO_CMD_START_B);
		if (i == MDIO_TIMEOUT)
			return -ETIMEDOUT;
	}

	return 0;
}

static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
			       u8 is_c45, u8 op, u8 phy_id, u16 cmd)
{
	u32 cmd_reg_value;
	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;

	cmd_reg_value = st << MDIO_CMD_ST_S;
	cmd_reg_value |= op << MDIO_CMD_OP_S;
	cmd_reg_value |=
		(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	cmd_reg_value |= 1 << MDIO_CMD_START_B;

	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
}

/**
 * hns_mdio_write - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_write(struct mii_bus *bus,
			  int phy_id, int regnum, u16 data)
{
	int ret;
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	u8 op;
	u16 cmd_reg_cfg;

	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
		phy_id, is_c45, devad, reg, data);

	/* wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		cmd_reg_cfg = reg;
		op = MDIO_C22_WRITE;
	} else {
		/* config the cmd-reg to write addr*/
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		/* config the data needed writing */
		cmd_reg_cfg = devad;
		op = MDIO_C45_WRITE_ADDR;
	}

	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
			   MDIO_WDATA_DATA_S, data);

	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);

	return 0;
}

/**
 * hns_mdio_read - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return phy register value
 */
static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
	int ret;
	u16 reg_val = 0;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;

	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
		phy_id, is_c45, devad, reg);

	/* Step 1: wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C22_READ, phy_id, reg);
	} else {
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		/* Step 2; config the cmd-reg to write addr*/
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* Step 3: check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);
	}

	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
	/* check for read or write opt is finished */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
	if (reg_val) {
		dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
		return -EBUSY;
	}

	/* Step 6; get out data*/
	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
					  MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);

	return reg_val;
}

/**
 * hns_mdio_reset - reset mdio bus
 * @bus: mdio bus
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_reset(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	const struct hns_mdio_sc_reg *sc_reg;
	int ret;

	if (dev_of_node(bus->parent)) {
		if (!mdio_dev->subctrl_vbase) {
			dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
			return -ENODEV;
		}

		sc_reg = &mdio_dev->sc_reg;
		/* 1. reset req, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO reset fail\n");
			return ret;
		}

		/* 2. dis clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 3. reset dreq, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 4. en clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret)
			dev_err(&bus->dev, "MDIO en clk fail\n");
	} else if (is_acpi_node(bus->parent->fwnode)) {
		acpi_status s;

		s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
					 "_RST", NULL, NULL);
		if (ACPI_FAILURE(s)) {
			dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
			ret = -EBUSY;
		} else {
			ret = 0;
		}
	} else {
		dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}
	return ret;
}

/**
 * hns_mdio_probe - probe mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_probe(struct platform_device *pdev)
{
	struct hns_mdio_device *mdio_dev;
	struct mii_bus *new_bus;
	struct resource *res;
	int ret = -ENODEV;

	if (!pdev) {
		dev_err(NULL, "pdev is NULL!\r\n");
		return -ENODEV;
	}

	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	if (!mdio_dev)
		return -ENOMEM;

	new_bus = devm_mdiobus_alloc(&pdev->dev);
	if (!new_bus) {
		dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
		return -ENOMEM;
	}

	new_bus->name = MDIO_BUS_NAME;
	new_bus->read = hns_mdio_read;
	new_bus->write = hns_mdio_write;
	new_bus->reset = hns_mdio_reset;
	new_bus->priv = mdio_dev;
	new_bus->parent = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdio_dev->vbase)) {
		ret = PTR_ERR(mdio_dev->vbase);
		return ret;
	}

	platform_set_drvdata(pdev, new_bus);
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
		 dev_name(&pdev->dev));
	if (dev_of_node(&pdev->dev)) {
		struct of_phandle_args reg_args;

		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
						       "subctrl-vbase",
						       4,
						       0,
						       &reg_args);
		if (!ret) {
			mdio_dev->subctrl_vbase =
				syscon_node_to_regmap(reg_args.np);
			if (IS_ERR(mdio_dev->subctrl_vbase)) {
				dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
				mdio_dev->subctrl_vbase = NULL;
			} else {
				if (reg_args.args_count == 4) {
					mdio_dev->sc_reg.mdio_clk_en =
						(u16)reg_args.args[0];
					mdio_dev->sc_reg.mdio_clk_dis =
						(u16)reg_args.args[0] + 4;
					mdio_dev->sc_reg.mdio_reset_req =
						(u16)reg_args.args[1];
					mdio_dev->sc_reg.mdio_reset_dreq =
						(u16)reg_args.args[1] + 4;
					mdio_dev->sc_reg.mdio_clk_st =
						(u16)reg_args.args[2];
					mdio_dev->sc_reg.mdio_reset_st =
						(u16)reg_args.args[3];
				} else {
					/* for compatible */
					mdio_dev->sc_reg.mdio_clk_en =
						MDIO_SC_CLK_EN;
					mdio_dev->sc_reg.mdio_clk_dis =
						MDIO_SC_CLK_DIS;
					mdio_dev->sc_reg.mdio_reset_req =
						MDIO_SC_RESET_REQ;
					mdio_dev->sc_reg.mdio_reset_dreq =
						MDIO_SC_RESET_DREQ;
					mdio_dev->sc_reg.mdio_clk_st =
						MDIO_SC_CLK_ST;
					mdio_dev->sc_reg.mdio_reset_st =
						MDIO_SC_RESET_ST;
				}
			}
		} else {
			dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
			mdio_dev->subctrl_vbase = NULL;
		}

		ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
	} else if (is_acpi_node(pdev->dev.fwnode)) {
		/* Clear all the IRQ properties */
		memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);

		/* Mask out all PHYs from auto probing. */
		new_bus->phy_mask = ~0;

		/* Register the MDIO bus */
		ret = mdiobus_register(new_bus);
	} else {
		dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}

	if (ret) {
		dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
		platform_set_drvdata(pdev, NULL);
		return ret;
	}

	return 0;
}

/**
 * hns_mdio_remove - remove mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_remove(struct platform_device *pdev)
{
	struct mii_bus *bus;

	bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static const struct of_device_id hns_mdio_match[] = {
	{.compatible = "hisilicon,mdio"},
	{.compatible = "hisilicon,hns-mdio"},
	{}
};

static const struct acpi_device_id hns_mdio_acpi_match[] = {
	{ "HISI0141", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);

static struct platform_driver hns_mdio_driver = {
	.probe = hns_mdio_probe,
	.remove = hns_mdio_remove,
	.driver = {
		   .name = MDIO_DRV_NAME,
		   .of_match_table = hns_mdio_match,
		   .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
		   },
};

module_platform_driver(hns_mdio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
MODULE_ALIAS("platform:" MDIO_DRV_NAME);
Commit	Line	Data
5b904d39	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
8a99ff5a	10	#include <linux/acpi.h>
5b904d39	11	#include <linux/errno.h>
	12	#include <linux/etherdevice.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
c7fc9eb7	15	#include <linux/mfd/syscon.h>
5b904d39	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of.h>
	21	#include <linux/of_mdio.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/phy.h>
	24	#include <linux/platform_device.h>
c7fc9eb7	25	#include <linux/regmap.h>
5b904d39	26	#include <linux/spinlock_types.h>
	27
	28	#define MDIO_DRV_NAME "Hi-HNS_MDIO"
	29	#define MDIO_BUS_NAME "Hisilicon MII Bus"
	30	#define MDIO_DRV_VERSION "1.3.0"
	31	#define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
	32	#define MDIO_DRV_STRING MDIO_BUS_NAME
	33	#define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME
	34
	35	#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
	36	#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
	37
	38	#define MDIO_TIMEOUT 1000000
	39
b15dc292 KY	40	struct hns_mdio_sc_reg {
	41	u16 mdio_clk_en;
	42	u16 mdio_clk_dis;
	43	u16 mdio_reset_req;
	44	u16 mdio_reset_dreq;
	45	u16 mdio_clk_st;
	46	u16 mdio_reset_st;
	47	};
	48
5b904d39	49	struct hns_mdio_device {
5b904d39	50	void vbase; / mdio reg base address */
c7fc9eb7	51	struct regmap *subctrl_vbase;
b15dc292	52	struct hns_mdio_sc_reg sc_reg;
5b904d39	53	};
	54
	55	/* mdio reg */
	56	#define MDIO_COMMAND_REG 0x0
	57	#define MDIO_ADDR_REG 0x4
	58	#define MDIO_WDATA_REG 0x8
	59	#define MDIO_RDATA_REG 0xc
	60	#define MDIO_STA_REG 0x10
	61
	62	/* cfg phy bit map */
	63	#define MDIO_CMD_DEVAD_M 0x1f
	64	#define MDIO_CMD_DEVAD_S 0
	65	#define MDIO_CMD_PRTAD_M 0x1f
	66	#define MDIO_CMD_PRTAD_S 5
	67	#define MDIO_CMD_OP_M 0x3
	68	#define MDIO_CMD_OP_S 10
	69	#define MDIO_CMD_ST_M 0x3
	70	#define MDIO_CMD_ST_S 12
	71	#define MDIO_CMD_START_B 14
	72
	73	#define MDIO_ADDR_DATA_M 0xffff
	74	#define MDIO_ADDR_DATA_S 0
	75
	76	#define MDIO_WDATA_DATA_M 0xffff
	77	#define MDIO_WDATA_DATA_S 0
	78
	79	#define MDIO_RDATA_DATA_M 0xffff
	80	#define MDIO_RDATA_DATA_S 0
	81
	82	#define MDIO_STATE_STA_B 0
	83
	84	enum mdio_st_clause {
	85	MDIO_ST_CLAUSE_45 = 0,
	86	MDIO_ST_CLAUSE_22
	87	};
	88
	89	enum mdio_c22_op_seq {
	90	MDIO_C22_WRITE = 1,
	91	MDIO_C22_READ = 2
	92	};
	93
	94	enum mdio_c45_op_seq {
	95	MDIO_C45_WRITE_ADDR = 0,
	96	MDIO_C45_WRITE_DATA,
	97	MDIO_C45_READ_INCREMENT,
	98	MDIO_C45_READ
	99	};
	100
	101	/* peri subctrl reg */
	102	#define MDIO_SC_CLK_EN 0x338
	103	#define MDIO_SC_CLK_DIS 0x33C
	104	#define MDIO_SC_RESET_REQ 0xA38
	105	#define MDIO_SC_RESET_DREQ 0xA3C
5b904d39	106	#define MDIO_SC_CLK_ST 0x531C
	107	#define MDIO_SC_RESET_ST 0x5A1C
	108
	109	static void mdio_write_reg(void *base, u32 reg, u32 value)
	110	{
	111	u8 __iomem reg_addr = (u8 __iomem )base;
	112
	113	writel_relaxed(value, reg_addr + reg);
	114	}
	115
	116	#define MDIO_WRITE_REG(a, reg, value) \
	117	mdio_write_reg((a)->vbase, (reg), (value))
	118
	119	static u32 mdio_read_reg(void *base, u32 reg)
	120	{
	121	u8 __iomem reg_addr = (u8 __iomem )base;
	122
	123	return readl_relaxed(reg_addr + reg);
	124	}
	125
	126	#define mdio_set_field(origin, mask, shift, val) \
	127	do { \
	128	(origin) &= (~((mask) << (shift))); \
	129	(origin) \|= (((val) & (mask)) << (shift)); \
	130	} while (0)
	131
	132	#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
	133
	134	static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
	135	u32 val)
	136	{
	137	u32 origin = mdio_read_reg(base, reg);
	138
	139	mdio_set_field(origin, mask, shift, val);
	140	mdio_write_reg(base, reg, origin);
	141	}
	142
	143	#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	144	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
	145
	146	static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
	147	{
	148	u32 origin;
	149
	150	origin = mdio_read_reg(base, reg);
	151	return mdio_get_field(origin, mask, shift);
	152	}
	153
	154	#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
	155	mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
	156
	157	#define MDIO_GET_REG_BIT(dev, reg, bit) \
	158	mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
	159
	160	#define MDIO_CHECK_SET_ST 1
	161	#define MDIO_CHECK_CLR_ST 0
	162
	163	static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
	164	u32 cfg_reg, u32 set_val,
	165	u32 st_reg, u32 st_msk, u8 check_st)
	166	{
	167	u32 time_cnt;
	168	u32 reg_value;
	169
c7fc9eb7	170	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
5b904d39	171
5b904d39	172	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
c7fc9eb7	173	regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
5b904d39	174	reg_value &= st_msk;
	175	if ((!!check_st) == (!!reg_value))
	176	break;
	177	}
	178
	179	if ((!!check_st) != (!!reg_value))
	180	return -EBUSY;
	181
	182	return 0;
	183	}
	184
	185	static int hns_mdio_wait_ready(struct mii_bus *bus)
	186	{
	187	struct hns_mdio_device *mdio_dev = bus->priv;
	188	int i;
	189	u32 cmd_reg_value = 1;
	190
	191	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	192	/* after that can do read or write*/
	193	for (i = 0; cmd_reg_value; i++) {
	194	cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
	195	MDIO_COMMAND_REG,
	196	MDIO_CMD_START_B);
	197	if (i == MDIO_TIMEOUT)
	198	return -ETIMEDOUT;
	199	}
	200
	201	return 0;
	202	}
	203
	204	static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
	205	u8 is_c45, u8 op, u8 phy_id, u16 cmd)
	206	{
	207	u32 cmd_reg_value;
	208	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
	209
	210	cmd_reg_value = st << MDIO_CMD_ST_S;
	211	cmd_reg_value \|= op << MDIO_CMD_OP_S;
	212	cmd_reg_value \|=
	213	(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	214	cmd_reg_value \|= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	215	cmd_reg_value \|= 1 << MDIO_CMD_START_B;
	216
	217	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
	218	}
	219
	220	/**
	221	* hns_mdio_write - access phy register
	222	* @bus: mdio bus
	223	* @phy_id: phy id
	224	* @regnum: register num
	225	* @value: register value
	226	*
	227	* Return 0 on success, negative on failure
	228	*/
	229	static int hns_mdio_write(struct mii_bus *bus,
	230	int phy_id, int regnum, u16 data)
	231	{
	232	int ret;
	233	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
	234	u8 devad = ((regnum >> 16) & 0x1f);
	235	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	236	u16 reg = (u16)(regnum & 0xffff);
	237	u8 op;
238	u16 cmd_reg_cfg;
239
240	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
241	bus->id, mdio_dev->vbase);
242	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
243	phy_id, is_c45, devad, reg, data);
244
245	/* wait for ready */
246	ret = hns_mdio_wait_ready(bus);
247	if (ret) {
248	dev_err(&bus->dev, "MDIO bus is busy\n");
249	return ret;
250	}
251
252	if (!is_c45) {
253	cmd_reg_cfg = reg;
254	op = MDIO_C22_WRITE;
255	} else {
256	/* config the cmd-reg to write addr*/
257	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
258	MDIO_ADDR_DATA_S, reg);
259
260	hns_mdio_cmd_write(mdio_dev, is_c45,
261	MDIO_C45_WRITE_ADDR, phy_id, devad);
262
263	/* check for read or write opt is finished */
264	ret = hns_mdio_wait_ready(bus);
265	if (ret) {
266	dev_err(&bus->dev, "MDIO bus is busy\n");
267	return ret;
268	}
269
270	/* config the data needed writing */
271	cmd_reg_cfg = devad;
272	op = MDIO_C45_WRITE_ADDR;
273	}
274
275	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
276	MDIO_WDATA_DATA_S, data);
277
278	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
279
280	return 0;
281	}
282
283	/**
284	* hns_mdio_read - access phy register
285	* @bus: mdio bus
286	* @phy_id: phy id
287	* @regnum: register num
288	* @value: register value
289	*
290	* Return phy register value
291	*/
292	static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
293	{
294	int ret;
295	u16 reg_val = 0;
296	u8 devad = ((regnum >> 16) & 0x1f);
297	u8 is_c45 = !!(regnum & MII_ADDR_C45);
298	u16 reg = (u16)(regnum & 0xffff);
299	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
300
301	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
302	bus->id, mdio_dev->vbase);
303	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
304	phy_id, is_c45, devad, reg);
305
306	/* Step 1: wait for ready */
307	ret = hns_mdio_wait_ready(bus);
308	if (ret) {
309	dev_err(&bus->dev, "MDIO bus is busy\n");
310	return ret;
311	}
312
313	if (!is_c45) {
314	hns_mdio_cmd_write(mdio_dev, is_c45,
315	MDIO_C22_READ, phy_id, reg);
316	} else {
317	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
318	MDIO_ADDR_DATA_S, reg);
319
320	/* Step 2; config the cmd-reg to write addr*/
321	hns_mdio_cmd_write(mdio_dev, is_c45,
322	MDIO_C45_WRITE_ADDR, phy_id, devad);
323
324	/* Step 3: check for read or write opt is finished */
325	ret = hns_mdio_wait_ready(bus);
326	if (ret) {
327	dev_err(&bus->dev, "MDIO bus is busy\n");
328	return ret;
329	}
330
331	hns_mdio_cmd_write(mdio_dev, is_c45,
332	MDIO_C45_WRITE_ADDR, phy_id, devad);
333	}
334
335	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
336	/* check for read or write opt is finished */
337	ret = hns_mdio_wait_ready(bus);
338	if (ret) {
339	dev_err(&bus->dev, "MDIO bus is busy\n");
340	return ret;
341	}
342
343	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
344	if (reg_val) {
345	dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
346	return -EBUSY;
347	}
348
349	/* Step 6; get out data*/
350	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
351	MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
352
353	return reg_val;
354	}
355
356	/**
357	* hns_mdio_reset - reset mdio bus
358	* @bus: mdio bus
359	*
360	* Return 0 on success, negative on failure
361	*/
362	static int hns_mdio_reset(struct mii_bus *bus)
363	{
364	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
b15dc292	365	const struct hns_mdio_sc_reg *sc_reg;
5b904d39	366	int ret;
5b904d39	367
8a99ff5a KY	368	if (dev_of_node(bus->parent)) {
	369	if (!mdio_dev->subctrl_vbase) {
	370	dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
	371	return -ENODEV;
	372	}
16a9f361	373
b15dc292	374	sc_reg = &mdio_dev->sc_reg;
8a99ff5a	375	/* 1. reset req, and read reset st check */
b15dc292 KY	376	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
b15dc292 KY	377	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	378	MDIO_CHECK_SET_ST);
	379	if (ret) {
	380	dev_err(&bus->dev, "MDIO reset fail\n");
	381	return ret;
	382	}
5b904d39	383
8a99ff5a	384	/* 2. dis clk, and read clk st check */
b15dc292 KY	385	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
b15dc292 KY	386	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	387	MDIO_CHECK_CLR_ST);
	388	if (ret) {
	389	dev_err(&bus->dev, "MDIO dis clk fail\n");
	390	return ret;
	391	}
5b904d39	392
8a99ff5a	393	/* 3. reset dreq, and read reset st check */
b15dc292 KY	394	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
b15dc292 KY	395	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	396	MDIO_CHECK_CLR_ST);
	397	if (ret) {
	398	dev_err(&bus->dev, "MDIO dis clk fail\n");
	399	return ret;
	400	}
5b904d39	401
8a99ff5a	402	/* 4. en clk, and read clk st check */
b15dc292 KY	403	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
b15dc292 KY	404	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	405	MDIO_CHECK_SET_ST);
	406	if (ret)
	407	dev_err(&bus->dev, "MDIO en clk fail\n");
	408	} else if (is_acpi_node(bus->parent->fwnode)) {
	409	acpi_status s;
	410
	411	s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
	412	"_RST", NULL, NULL);
	413	if (ACPI_FAILURE(s)) {
	414	dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
	415	ret = -EBUSY;
	416	} else {
	417	ret = 0;
	418	}
	419	} else {
	420	dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
	421	ret = -ENXIO;
5b904d39	422	}
5b904d39	423	return ret;
	424	}
	425
5b904d39	426	/**
	427	* hns_mdio_probe - probe mdio device
	428	* @pdev: mdio platform device
	429	*
	430	* Return 0 on success, negative on failure
	431	*/
	432	static int hns_mdio_probe(struct platform_device *pdev)
	433	{
5b904d39	434	struct hns_mdio_device *mdio_dev;
	435	struct mii_bus *new_bus;
	436	struct resource *res;
16a9f361	437	int ret = -ENODEV;
5b904d39	438
	439	if (!pdev) {
	440	dev_err(NULL, "pdev is NULL!\r\n");
	441	return -ENODEV;
	442	}
16a9f361	443
5b904d39	444	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	445	if (!mdio_dev)
	446	return -ENOMEM;
	447
	448	new_bus = devm_mdiobus_alloc(&pdev->dev);
	449	if (!new_bus) {
	450	dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
	451	return -ENOMEM;
	452	}
	453
	454	new_bus->name = MDIO_BUS_NAME;
	455	new_bus->read = hns_mdio_read;
	456	new_bus->write = hns_mdio_write;
	457	new_bus->reset = hns_mdio_reset;
	458	new_bus->priv = mdio_dev;
16a9f361	459	new_bus->parent = &pdev->dev;
5b904d39	460
	461	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	462	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	463	if (IS_ERR(mdio_dev->vbase)) {
	464	ret = PTR_ERR(mdio_dev->vbase);
	465	return ret;
	466	}
	467
5b904d39	468	platform_set_drvdata(pdev, new_bus);
16a9f361 KY	469	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
	470	dev_name(&pdev->dev));
	471	if (dev_of_node(&pdev->dev)) {
b15dc292 KY	472	struct of_phandle_args reg_args;
	473
	474	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
	475	"subctrl-vbase",
	476	4,
	477	0,
	478	&reg_args);
	479	if (!ret) {
	480	mdio_dev->subctrl_vbase =
	481	syscon_node_to_regmap(reg_args.np);
	482	if (IS_ERR(mdio_dev->subctrl_vbase)) {
	483	dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
	484	mdio_dev->subctrl_vbase = NULL;
	485	} else {
	486	if (reg_args.args_count == 4) {
	487	mdio_dev->sc_reg.mdio_clk_en =
	488	(u16)reg_args.args[0];
	489	mdio_dev->sc_reg.mdio_clk_dis =
	490	(u16)reg_args.args[0] + 4;
	491	mdio_dev->sc_reg.mdio_reset_req =
	492	(u16)reg_args.args[1];
	493	mdio_dev->sc_reg.mdio_reset_dreq =
	494	(u16)reg_args.args[1] + 4;
	495	mdio_dev->sc_reg.mdio_clk_st =
	496	(u16)reg_args.args[2];
	497	mdio_dev->sc_reg.mdio_reset_st =
	498	(u16)reg_args.args[3];
	499	} else {
	500	/* for compatible */
	501	mdio_dev->sc_reg.mdio_clk_en =
	502	MDIO_SC_CLK_EN;
	503	mdio_dev->sc_reg.mdio_clk_dis =
	504	MDIO_SC_CLK_DIS;
	505	mdio_dev->sc_reg.mdio_reset_req =
	506	MDIO_SC_RESET_REQ;
	507	mdio_dev->sc_reg.mdio_reset_dreq =
	508	MDIO_SC_RESET_DREQ;
	509	mdio_dev->sc_reg.mdio_clk_st =
	510	MDIO_SC_CLK_ST;
	511	mdio_dev->sc_reg.mdio_reset_st =
	512	MDIO_SC_RESET_ST;
	513	}
	514	}
	515	} else {
	516	dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
16a9f361 KY	517	mdio_dev->subctrl_vbase = NULL;
16a9f361 KY	518	}
b15dc292	519
16a9f361	520	ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
8a99ff5a KY	521	} else if (is_acpi_node(pdev->dev.fwnode)) {
	522	/* Clear all the IRQ properties */
	523	memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
	524
	525	/* Mask out all PHYs from auto probing. */
	526	new_bus->phy_mask = ~0;
	527
	528	/* Register the MDIO bus */
	529	ret = mdiobus_register(new_bus);
	530	} else {
	531	dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
	532	ret = -ENXIO;
16a9f361	533	}
5b904d39	534
5b904d39	535	if (ret) {
	536	dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
	537	platform_set_drvdata(pdev, NULL);
	538	return ret;
	539	}
	540
	541	return 0;
	542	}
	543
	544	/**
	545	* hns_mdio_remove - remove mdio device
	546	* @pdev: mdio platform device
	547	*
	548	* Return 0 on success, negative on failure
	549	*/
	550	static int hns_mdio_remove(struct platform_device *pdev)
	551	{
	552	struct mii_bus *bus;
	553
	554	bus = platform_get_drvdata(pdev);
	555
	556	mdiobus_unregister(bus);
	557	platform_set_drvdata(pdev, NULL);
	558	return 0;
	559	}
	560
	561	static const struct of_device_id hns_mdio_match[] = {
	562	{.compatible = "hisilicon,mdio"},
	563	{.compatible = "hisilicon,hns-mdio"},
	564	{}
	565	};
	566
8a99ff5a KY	567	static const struct acpi_device_id hns_mdio_acpi_match[] = {
	568	{ "HISI0141", 0 },
	569	{ },
	570	};
	571	MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
	572
5b904d39	573	static struct platform_driver hns_mdio_driver = {
	574	.probe = hns_mdio_probe,
	575	.remove = hns_mdio_remove,
	576	.driver = {
	577	.name = MDIO_DRV_NAME,
	578	.of_match_table = hns_mdio_match,
8a99ff5a	579	.acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
5b904d39	580	},
	581	};
	582
	583	module_platform_driver(hns_mdio_driver);
	584
	585	MODULE_LICENSE("GPL");
	586	MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
	587	MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
	588	MODULE_ALIAS("platform:" MDIO_DRV_NAME);