Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
bf67044b | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
e921eb1a | 29 | /* 80003ES2LAN Gigabit Ethernet Controller (Copper) |
bc7f75fa AK |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) |
31 | */ | |
32 | ||
bc7f75fa AK |
33 | #include "e1000.h" |
34 | ||
e921eb1a | 35 | /* A table for the GG82563 cable length where the range is defined |
bc7f75fa AK |
36 | * with a lower bound at "index" and the upper bound at |
37 | * "index + 5". | |
38 | */ | |
6480641e BA |
39 | static const u16 e1000_gg82563_cable_length_table[] = { |
40 | 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
eb656d45 BA |
41 | #define GG82563_CABLE_LENGTH_TABLE_SIZE \ |
42 | ARRAY_SIZE(e1000_gg82563_cable_length_table) | |
bc7f75fa AK |
43 | |
44 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
45 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
46 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
47 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
48 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
49 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
50 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
1f96012d BA |
51 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
52 | u16 *data); | |
53 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
54 | u16 data); | |
17f208de | 55 | static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); |
bc7f75fa AK |
56 | |
57 | /** | |
58 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
59 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
60 | **/ |
61 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
62 | { | |
63 | struct e1000_phy_info *phy = &hw->phy; | |
64 | s32 ret_val; | |
65 | ||
318a94d6 | 66 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
67 | phy->type = e1000_phy_none; |
68 | return 0; | |
17f208de BA |
69 | } else { |
70 | phy->ops.power_up = e1000_power_up_phy_copper; | |
71 | phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; | |
bc7f75fa AK |
72 | } |
73 | ||
74 | phy->addr = 1; | |
75 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
76 | phy->reset_delay_us = 100; | |
77 | phy->type = e1000_phy_gg82563; | |
78 | ||
79 | /* This can only be done after all function pointers are setup. */ | |
80 | ret_val = e1000e_get_phy_id(hw); | |
81 | ||
82 | /* Verify phy id */ | |
83 | if (phy->id != GG82563_E_PHY_ID) | |
84 | return -E1000_ERR_PHY; | |
85 | ||
86 | return ret_val; | |
87 | } | |
88 | ||
89 | /** | |
90 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
91 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
92 | **/ |
93 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
94 | { | |
95 | struct e1000_nvm_info *nvm = &hw->nvm; | |
96 | u32 eecd = er32(EECD); | |
97 | u16 size; | |
98 | ||
99 | nvm->opcode_bits = 8; | |
100 | nvm->delay_usec = 1; | |
101 | switch (nvm->override) { | |
102 | case e1000_nvm_override_spi_large: | |
103 | nvm->page_size = 32; | |
104 | nvm->address_bits = 16; | |
105 | break; | |
106 | case e1000_nvm_override_spi_small: | |
107 | nvm->page_size = 8; | |
108 | nvm->address_bits = 8; | |
109 | break; | |
110 | default: | |
111 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
112 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
113 | break; | |
114 | } | |
115 | ||
ad68076e | 116 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
117 | |
118 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
f0ff4398 | 119 | E1000_EECD_SIZE_EX_SHIFT); |
bc7f75fa | 120 | |
e921eb1a | 121 | /* Added to a constant, "size" becomes the left-shift value |
bc7f75fa AK |
122 | * for setting word_size. |
123 | */ | |
124 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
125 | |
126 | /* EEPROM access above 16k is unsupported */ | |
127 | if (size > 14) | |
128 | size = 14; | |
bc7f75fa AK |
129 | nvm->word_size = 1 << size; |
130 | ||
131 | return 0; | |
132 | } | |
133 | ||
134 | /** | |
135 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
136 | * @hw: pointer to the HW structure | |
bc7f75fa | 137 | **/ |
ec34c170 | 138 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) |
bc7f75fa | 139 | { |
bc7f75fa | 140 | struct e1000_mac_info *mac = &hw->mac; |
bc7f75fa | 141 | |
e68782ed | 142 | /* Set media type and media-dependent function pointers */ |
ec34c170 | 143 | switch (hw->adapter->pdev->device) { |
bc7f75fa | 144 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
318a94d6 | 145 | hw->phy.media_type = e1000_media_type_internal_serdes; |
e68782ed BA |
146 | mac->ops.check_for_link = e1000e_check_for_serdes_link; |
147 | mac->ops.setup_physical_interface = | |
148 | e1000e_setup_fiber_serdes_link; | |
bc7f75fa AK |
149 | break; |
150 | default: | |
318a94d6 | 151 | hw->phy.media_type = e1000_media_type_copper; |
e68782ed BA |
152 | mac->ops.check_for_link = e1000e_check_for_copper_link; |
153 | mac->ops.setup_physical_interface = | |
154 | e1000_setup_copper_link_80003es2lan; | |
bc7f75fa AK |
155 | break; |
156 | } | |
157 | ||
158 | /* Set mta register count */ | |
159 | mac->mta_reg_count = 128; | |
160 | /* Set rar entry count */ | |
161 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
a65a4a0d BA |
162 | /* FWSM register */ |
163 | mac->has_fwsm = true; | |
164 | /* ARC supported; valid only if manageability features are enabled. */ | |
04499ec4 | 165 | mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK); |
f464ba87 BA |
166 | /* Adaptive IFS not supported */ |
167 | mac->adaptive_ifs = false; | |
bc7f75fa | 168 | |
f4d2dd4c BA |
169 | /* set lan id for port to determine which phy lock to use */ |
170 | hw->mac.ops.set_lan_id(hw); | |
171 | ||
bc7f75fa AK |
172 | return 0; |
173 | } | |
174 | ||
69e3fd8c | 175 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
176 | { |
177 | struct e1000_hw *hw = &adapter->hw; | |
178 | s32 rc; | |
179 | ||
ec34c170 | 180 | rc = e1000_init_mac_params_80003es2lan(hw); |
bc7f75fa AK |
181 | if (rc) |
182 | return rc; | |
183 | ||
184 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
185 | if (rc) | |
186 | return rc; | |
187 | ||
188 | rc = e1000_init_phy_params_80003es2lan(hw); | |
189 | if (rc) | |
190 | return rc; | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | /** | |
196 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
197 | * @hw: pointer to the HW structure | |
198 | * | |
fe401674 | 199 | * A wrapper to acquire access rights to the correct PHY. |
bc7f75fa AK |
200 | **/ |
201 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
202 | { | |
203 | u16 mask; | |
204 | ||
205 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
bc7f75fa AK |
206 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
207 | } | |
208 | ||
209 | /** | |
210 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
211 | * @hw: pointer to the HW structure | |
212 | * | |
fe401674 | 213 | * A wrapper to release access rights to the correct PHY. |
bc7f75fa AK |
214 | **/ |
215 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
216 | { | |
217 | u16 mask; | |
218 | ||
219 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
75eb0fad BA |
220 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
221 | } | |
222 | ||
223 | /** | |
dffcdde7 | 224 | * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register |
75eb0fad BA |
225 | * @hw: pointer to the HW structure |
226 | * | |
227 | * Acquire the semaphore to access the Kumeran interface. | |
228 | * | |
229 | **/ | |
230 | static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) | |
231 | { | |
232 | u16 mask; | |
233 | ||
234 | mask = E1000_SWFW_CSR_SM; | |
235 | ||
236 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
237 | } | |
238 | ||
239 | /** | |
dffcdde7 | 240 | * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register |
75eb0fad BA |
241 | * @hw: pointer to the HW structure |
242 | * | |
243 | * Release the semaphore used to access the Kumeran interface | |
244 | **/ | |
245 | static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) | |
246 | { | |
247 | u16 mask; | |
248 | ||
249 | mask = E1000_SWFW_CSR_SM; | |
2d9498f3 | 250 | |
bc7f75fa AK |
251 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
252 | } | |
253 | ||
254 | /** | |
255 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
256 | * @hw: pointer to the HW structure | |
257 | * | |
fe401674 | 258 | * Acquire the semaphore to access the EEPROM. |
bc7f75fa AK |
259 | **/ |
260 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
261 | { | |
262 | s32 ret_val; | |
263 | ||
264 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
265 | if (ret_val) | |
266 | return ret_val; | |
267 | ||
268 | ret_val = e1000e_acquire_nvm(hw); | |
269 | ||
270 | if (ret_val) | |
271 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
272 | ||
273 | return ret_val; | |
274 | } | |
275 | ||
276 | /** | |
277 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
278 | * @hw: pointer to the HW structure | |
279 | * | |
fe401674 | 280 | * Release the semaphore used to access the EEPROM. |
bc7f75fa AK |
281 | **/ |
282 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
283 | { | |
284 | e1000e_release_nvm(hw); | |
285 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
286 | } | |
287 | ||
288 | /** | |
289 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
290 | * @hw: pointer to the HW structure | |
291 | * @mask: specifies which semaphore to acquire | |
292 | * | |
293 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
294 | * will also specify which port we're acquiring the lock for. | |
295 | **/ | |
296 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
297 | { | |
298 | u32 swfw_sync; | |
299 | u32 swmask = mask; | |
300 | u32 fwmask = mask << 16; | |
301 | s32 i = 0; | |
75eb0fad | 302 | s32 timeout = 50; |
bc7f75fa AK |
303 | |
304 | while (i < timeout) { | |
305 | if (e1000e_get_hw_semaphore(hw)) | |
306 | return -E1000_ERR_SWFW_SYNC; | |
307 | ||
308 | swfw_sync = er32(SW_FW_SYNC); | |
309 | if (!(swfw_sync & (fwmask | swmask))) | |
310 | break; | |
311 | ||
e921eb1a | 312 | /* Firmware currently using resource (fwmask) |
ad68076e BA |
313 | * or other software thread using resource (swmask) |
314 | */ | |
bc7f75fa AK |
315 | e1000e_put_hw_semaphore(hw); |
316 | mdelay(5); | |
317 | i++; | |
318 | } | |
319 | ||
320 | if (i == timeout) { | |
3bb99fe2 | 321 | e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
bc7f75fa AK |
322 | return -E1000_ERR_SWFW_SYNC; |
323 | } | |
324 | ||
325 | swfw_sync |= swmask; | |
326 | ew32(SW_FW_SYNC, swfw_sync); | |
327 | ||
328 | e1000e_put_hw_semaphore(hw); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | /** | |
334 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
335 | * @hw: pointer to the HW structure | |
336 | * @mask: specifies which semaphore to acquire | |
337 | * | |
338 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
339 | * will also specify which port we're releasing the lock for. | |
340 | **/ | |
341 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
342 | { | |
343 | u32 swfw_sync; | |
344 | ||
184125a3 BA |
345 | while (e1000e_get_hw_semaphore(hw) != 0) |
346 | ; /* Empty */ | |
bc7f75fa AK |
347 | |
348 | swfw_sync = er32(SW_FW_SYNC); | |
349 | swfw_sync &= ~mask; | |
350 | ew32(SW_FW_SYNC, swfw_sync); | |
351 | ||
352 | e1000e_put_hw_semaphore(hw); | |
353 | } | |
354 | ||
355 | /** | |
356 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
357 | * @hw: pointer to the HW structure | |
358 | * @offset: offset of the register to read | |
359 | * @data: pointer to the data returned from the operation | |
360 | * | |
fe401674 | 361 | * Read the GG82563 PHY register. |
bc7f75fa AK |
362 | **/ |
363 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
364 | u32 offset, u16 *data) | |
365 | { | |
366 | s32 ret_val; | |
367 | u32 page_select; | |
368 | u16 temp; | |
369 | ||
2d9498f3 DG |
370 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
371 | if (ret_val) | |
372 | return ret_val; | |
373 | ||
bc7f75fa | 374 | /* Select Configuration Page */ |
2d9498f3 | 375 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 376 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 377 | } else { |
e921eb1a | 378 | /* Use Alternative Page Select register to access |
bc7f75fa AK |
379 | * registers 30 and 31 |
380 | */ | |
381 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 382 | } |
bc7f75fa AK |
383 | |
384 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
385 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
386 | if (ret_val) { | |
387 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 388 | return ret_val; |
2d9498f3 | 389 | } |
bc7f75fa | 390 | |
b4d8e21d | 391 | if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { |
e921eb1a | 392 | /* The "ready" bit in the MDIC register may be incorrectly set |
3421eecd BA |
393 | * before the device has completed the "Page Select" MDI |
394 | * transaction. So we wait 200us after each MDI command... | |
395 | */ | |
396 | udelay(200); | |
bc7f75fa | 397 | |
3421eecd BA |
398 | /* ...and verify the command was successful. */ |
399 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); | |
bc7f75fa | 400 | |
3421eecd | 401 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
3421eecd | 402 | e1000_release_phy_80003es2lan(hw); |
7eb61d81 | 403 | return -E1000_ERR_PHY; |
3421eecd BA |
404 | } |
405 | ||
406 | udelay(200); | |
bc7f75fa | 407 | |
3421eecd | 408 | ret_val = e1000e_read_phy_reg_mdic(hw, |
f0ff4398 BA |
409 | MAX_PHY_REG_ADDRESS & offset, |
410 | data); | |
bc7f75fa | 411 | |
3421eecd BA |
412 | udelay(200); |
413 | } else { | |
414 | ret_val = e1000e_read_phy_reg_mdic(hw, | |
f0ff4398 BA |
415 | MAX_PHY_REG_ADDRESS & offset, |
416 | data); | |
3421eecd | 417 | } |
bc7f75fa | 418 | |
2d9498f3 | 419 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
420 | |
421 | return ret_val; | |
422 | } | |
423 | ||
424 | /** | |
425 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
426 | * @hw: pointer to the HW structure | |
427 | * @offset: offset of the register to read | |
428 | * @data: value to write to the register | |
429 | * | |
fe401674 | 430 | * Write to the GG82563 PHY register. |
bc7f75fa AK |
431 | **/ |
432 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
433 | u32 offset, u16 data) | |
434 | { | |
435 | s32 ret_val; | |
436 | u32 page_select; | |
437 | u16 temp; | |
438 | ||
2d9498f3 DG |
439 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
440 | if (ret_val) | |
441 | return ret_val; | |
442 | ||
bc7f75fa | 443 | /* Select Configuration Page */ |
2d9498f3 | 444 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 445 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 446 | } else { |
e921eb1a | 447 | /* Use Alternative Page Select register to access |
bc7f75fa AK |
448 | * registers 30 and 31 |
449 | */ | |
450 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 451 | } |
bc7f75fa AK |
452 | |
453 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
454 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
455 | if (ret_val) { | |
456 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 457 | return ret_val; |
2d9498f3 | 458 | } |
bc7f75fa | 459 | |
b4d8e21d | 460 | if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { |
e921eb1a | 461 | /* The "ready" bit in the MDIC register may be incorrectly set |
3421eecd BA |
462 | * before the device has completed the "Page Select" MDI |
463 | * transaction. So we wait 200us after each MDI command... | |
464 | */ | |
465 | udelay(200); | |
bc7f75fa | 466 | |
3421eecd BA |
467 | /* ...and verify the command was successful. */ |
468 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); | |
bc7f75fa | 469 | |
3421eecd BA |
470 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
471 | e1000_release_phy_80003es2lan(hw); | |
472 | return -E1000_ERR_PHY; | |
473 | } | |
bc7f75fa | 474 | |
3421eecd | 475 | udelay(200); |
bc7f75fa | 476 | |
3421eecd | 477 | ret_val = e1000e_write_phy_reg_mdic(hw, |
f0ff4398 BA |
478 | MAX_PHY_REG_ADDRESS & |
479 | offset, data); | |
bc7f75fa | 480 | |
3421eecd BA |
481 | udelay(200); |
482 | } else { | |
483 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
f0ff4398 BA |
484 | MAX_PHY_REG_ADDRESS & |
485 | offset, data); | |
3421eecd | 486 | } |
bc7f75fa | 487 | |
2d9498f3 | 488 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
489 | |
490 | return ret_val; | |
491 | } | |
492 | ||
493 | /** | |
494 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
495 | * @hw: pointer to the HW structure | |
496 | * @offset: offset of the register to read | |
497 | * @words: number of words to write | |
498 | * @data: buffer of data to write to the NVM | |
499 | * | |
fe401674 | 500 | * Write "words" of data to the ESB2 NVM. |
bc7f75fa AK |
501 | **/ |
502 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
503 | u16 words, u16 *data) | |
504 | { | |
505 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
506 | } | |
507 | ||
508 | /** | |
509 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
510 | * @hw: pointer to the HW structure | |
511 | * | |
512 | * Wait a specific amount of time for manageability processes to complete. | |
513 | * This is a function pointer entry point called by the phy module. | |
514 | **/ | |
515 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
516 | { | |
517 | s32 timeout = PHY_CFG_TIMEOUT; | |
518 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
519 | ||
520 | if (hw->bus.func == 1) | |
521 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
522 | ||
523 | while (timeout) { | |
524 | if (er32(EEMNGCTL) & mask) | |
525 | break; | |
1bba4386 | 526 | usleep_range(1000, 2000); |
bc7f75fa AK |
527 | timeout--; |
528 | } | |
529 | if (!timeout) { | |
3bb99fe2 | 530 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
531 | return -E1000_ERR_RESET; |
532 | } | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | /** | |
538 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
539 | * @hw: pointer to the HW structure | |
540 | * | |
541 | * Force the speed and duplex settings onto the PHY. This is a | |
542 | * function pointer entry point called by the phy module. | |
543 | **/ | |
544 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
545 | { | |
546 | s32 ret_val; | |
547 | u16 phy_data; | |
548 | bool link; | |
549 | ||
e921eb1a | 550 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
bc7f75fa AK |
551 | * forced whenever speed and duplex are forced. |
552 | */ | |
553 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
554 | if (ret_val) | |
555 | return ret_val; | |
556 | ||
557 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
558 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
559 | if (ret_val) | |
560 | return ret_val; | |
561 | ||
3bb99fe2 | 562 | e_dbg("GG82563 PSCR: %X\n", phy_data); |
bc7f75fa | 563 | |
c2ade1a4 | 564 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
bc7f75fa AK |
565 | if (ret_val) |
566 | return ret_val; | |
567 | ||
568 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
569 | ||
570 | /* Reset the phy to commit changes. */ | |
c2ade1a4 | 571 | phy_data |= BMCR_RESET; |
bc7f75fa | 572 | |
c2ade1a4 | 573 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
bc7f75fa AK |
574 | if (ret_val) |
575 | return ret_val; | |
576 | ||
577 | udelay(1); | |
578 | ||
318a94d6 | 579 | if (hw->phy.autoneg_wait_to_complete) { |
434f1392 | 580 | e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n"); |
bc7f75fa AK |
581 | |
582 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
583 | 100000, &link); | |
584 | if (ret_val) | |
585 | return ret_val; | |
586 | ||
587 | if (!link) { | |
e921eb1a | 588 | /* We didn't get link. |
bc7f75fa AK |
589 | * Reset the DSP and cross our fingers. |
590 | */ | |
591 | ret_val = e1000e_phy_reset_dsp(hw); | |
592 | if (ret_val) | |
593 | return ret_val; | |
594 | } | |
595 | ||
596 | /* Try once more */ | |
597 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
598 | 100000, &link); | |
599 | if (ret_val) | |
600 | return ret_val; | |
601 | } | |
602 | ||
603 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
604 | if (ret_val) | |
605 | return ret_val; | |
606 | ||
e921eb1a | 607 | /* Resetting the phy means we need to verify the TX_CLK corresponds |
bc7f75fa AK |
608 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
609 | */ | |
610 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
611 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
612 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
613 | else | |
614 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
615 | ||
e921eb1a | 616 | /* In addition, we must re-enable CRS on Tx for both half and full |
bc7f75fa AK |
617 | * duplex. |
618 | */ | |
619 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
620 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
621 | ||
622 | return ret_val; | |
623 | } | |
624 | ||
625 | /** | |
626 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
627 | * @hw: pointer to the HW structure | |
628 | * | |
629 | * Find the approximate cable length as measured by the GG82563 PHY. | |
630 | * This is a function pointer entry point called by the phy module. | |
631 | **/ | |
632 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
633 | { | |
634 | struct e1000_phy_info *phy = &hw->phy; | |
70806a7f | 635 | s32 ret_val; |
a708dd88 | 636 | u16 phy_data, index; |
bc7f75fa AK |
637 | |
638 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
639 | if (ret_val) | |
5015e53a | 640 | return ret_val; |
bc7f75fa AK |
641 | |
642 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
eb656d45 | 643 | |
5015e53a BA |
644 | if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) |
645 | return -E1000_ERR_PHY; | |
eb656d45 | 646 | |
bc7f75fa | 647 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; |
eb656d45 | 648 | phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; |
bc7f75fa AK |
649 | |
650 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
651 | ||
5015e53a | 652 | return 0; |
bc7f75fa AK |
653 | } |
654 | ||
655 | /** | |
656 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
657 | * @hw: pointer to the HW structure | |
658 | * @speed: pointer to speed buffer | |
659 | * @duplex: pointer to duplex buffer | |
660 | * | |
661 | * Retrieve the current speed and duplex configuration. | |
bc7f75fa AK |
662 | **/ |
663 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
664 | u16 *duplex) | |
665 | { | |
666 | s32 ret_val; | |
667 | ||
318a94d6 | 668 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
669 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
670 | speed, | |
671 | duplex); | |
75eb0fad | 672 | hw->phy.ops.cfg_on_link_up(hw); |
bc7f75fa AK |
673 | } else { |
674 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
675 | speed, | |
676 | duplex); | |
677 | } | |
678 | ||
679 | return ret_val; | |
680 | } | |
681 | ||
682 | /** | |
683 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
684 | * @hw: pointer to the HW structure | |
685 | * | |
686 | * Perform a global reset to the ESB2 controller. | |
bc7f75fa AK |
687 | **/ |
688 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
689 | { | |
dd93f95e | 690 | u32 ctrl; |
bc7f75fa | 691 | s32 ret_val; |
1c1093a4 | 692 | u16 kum_reg_data; |
bc7f75fa | 693 | |
e921eb1a | 694 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
bc7f75fa AK |
695 | * on the last TLP read/write transaction when MAC is reset. |
696 | */ | |
697 | ret_val = e1000e_disable_pcie_master(hw); | |
698 | if (ret_val) | |
3bb99fe2 | 699 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 700 | |
3bb99fe2 | 701 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
702 | ew32(IMC, 0xffffffff); |
703 | ||
704 | ew32(RCTL, 0); | |
705 | ew32(TCTL, E1000_TCTL_PSP); | |
706 | e1e_flush(); | |
707 | ||
1bba4386 | 708 | usleep_range(10000, 20000); |
bc7f75fa AK |
709 | |
710 | ctrl = er32(CTRL); | |
711 | ||
75eb0fad | 712 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
7dbbe5d5 BA |
713 | if (ret_val) |
714 | return ret_val; | |
715 | ||
3bb99fe2 | 716 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa | 717 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
75eb0fad | 718 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa | 719 | |
1c1093a4 MV |
720 | /* Disable IBIST slave mode (far-end loopback) */ |
721 | e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
722 | &kum_reg_data); | |
723 | kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; | |
724 | e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
725 | kum_reg_data); | |
726 | ||
bc7f75fa AK |
727 | ret_val = e1000e_get_auto_rd_done(hw); |
728 | if (ret_val) | |
729 | /* We don't want to continue accessing MAC registers. */ | |
730 | return ret_val; | |
731 | ||
732 | /* Clear any pending interrupt events. */ | |
733 | ew32(IMC, 0xffffffff); | |
dd93f95e | 734 | er32(ICR); |
bc7f75fa | 735 | |
7eb61d81 | 736 | return e1000_check_alt_mac_addr_generic(hw); |
bc7f75fa AK |
737 | } |
738 | ||
739 | /** | |
740 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
741 | * @hw: pointer to the HW structure | |
742 | * | |
743 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
bc7f75fa AK |
744 | **/ |
745 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
746 | { | |
747 | struct e1000_mac_info *mac = &hw->mac; | |
748 | u32 reg_data; | |
749 | s32 ret_val; | |
d9b24135 | 750 | u16 kum_reg_data; |
bc7f75fa AK |
751 | u16 i; |
752 | ||
753 | e1000_initialize_hw_bits_80003es2lan(hw); | |
754 | ||
755 | /* Initialize identification LED */ | |
d1964eb1 | 756 | ret_val = mac->ops.id_led_init(hw); |
de39b752 | 757 | if (ret_val) |
3bb99fe2 | 758 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 759 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
760 | |
761 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 762 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 763 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
764 | |
765 | /* Setup the receive address. */ | |
766 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
767 | ||
768 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 769 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
770 | for (i = 0; i < mac->mta_reg_count; i++) |
771 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
772 | ||
773 | /* Setup link and flow control */ | |
1a46b40f | 774 | ret_val = mac->ops.setup_link(hw); |
7dbbe5d5 BA |
775 | if (ret_val) |
776 | return ret_val; | |
bc7f75fa | 777 | |
d9b24135 BA |
778 | /* Disable IBIST slave mode (far-end loopback) */ |
779 | e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
780 | &kum_reg_data); | |
781 | kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; | |
782 | e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, | |
783 | kum_reg_data); | |
784 | ||
bc7f75fa | 785 | /* Set the transmit descriptor write-back policy */ |
e9ec2c0f | 786 | reg_data = er32(TXDCTL(0)); |
f0ff4398 BA |
787 | reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | |
788 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); | |
e9ec2c0f | 789 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
790 | |
791 | /* ...for both queues. */ | |
e9ec2c0f | 792 | reg_data = er32(TXDCTL(1)); |
f0ff4398 BA |
793 | reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) | |
794 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC); | |
e9ec2c0f | 795 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
796 | |
797 | /* Enable retransmit on late collisions */ | |
798 | reg_data = er32(TCTL); | |
799 | reg_data |= E1000_TCTL_RTLC; | |
800 | ew32(TCTL, reg_data); | |
801 | ||
802 | /* Configure Gigabit Carry Extend Padding */ | |
803 | reg_data = er32(TCTL_EXT); | |
804 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
805 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
806 | ew32(TCTL_EXT, reg_data); | |
807 | ||
808 | /* Configure Transmit Inter-Packet Gap */ | |
809 | reg_data = er32(TIPG); | |
810 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
811 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
812 | ew32(TIPG, reg_data); | |
813 | ||
814 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
815 | reg_data &= ~0x00100000; | |
816 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
817 | ||
3421eecd BA |
818 | /* default to true to enable the MDIC W/A */ |
819 | hw->dev_spec.e80003es2lan.mdic_wa_enable = true; | |
820 | ||
f0ff4398 BA |
821 | ret_val = |
822 | e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >> | |
823 | E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i); | |
3421eecd BA |
824 | if (!ret_val) { |
825 | if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == | |
826 | E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) | |
827 | hw->dev_spec.e80003es2lan.mdic_wa_enable = false; | |
828 | } | |
829 | ||
e921eb1a | 830 | /* Clear all of the statistics registers (clear on read). It is |
bc7f75fa AK |
831 | * important that we do this after we have tried to establish link |
832 | * because the symbol error count will increment wildly if there | |
833 | * is no link. | |
834 | */ | |
835 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
836 | ||
837 | return ret_val; | |
838 | } | |
839 | ||
840 | /** | |
841 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
842 | * @hw: pointer to the HW structure | |
843 | * | |
844 | * Initializes required hardware-dependent bits needed for normal operation. | |
845 | **/ | |
846 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
847 | { | |
848 | u32 reg; | |
849 | ||
850 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 851 | reg = er32(TXDCTL(0)); |
bc7f75fa | 852 | reg |= (1 << 22); |
e9ec2c0f | 853 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
854 | |
855 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 856 | reg = er32(TXDCTL(1)); |
bc7f75fa | 857 | reg |= (1 << 22); |
e9ec2c0f | 858 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
859 | |
860 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 861 | reg = er32(TARC(0)); |
bc7f75fa | 862 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 863 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 864 | reg &= ~(1 << 20); |
e9ec2c0f | 865 | ew32(TARC(0), reg); |
bc7f75fa AK |
866 | |
867 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 868 | reg = er32(TARC(1)); |
bc7f75fa AK |
869 | if (er32(TCTL) & E1000_TCTL_MULR) |
870 | reg &= ~(1 << 28); | |
871 | else | |
872 | reg |= (1 << 28); | |
e9ec2c0f | 873 | ew32(TARC(1), reg); |
f6bd5577 | 874 | |
e921eb1a | 875 | /* Disable IPv6 extension header parsing because some malformed |
f6bd5577 MV |
876 | * IPv6 headers can hang the Rx. |
877 | */ | |
878 | reg = er32(RFCTL); | |
879 | reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); | |
880 | ew32(RFCTL, reg); | |
bc7f75fa AK |
881 | } |
882 | ||
883 | /** | |
884 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
885 | * @hw: pointer to the HW structure | |
886 | * | |
887 | * Setup some GG82563 PHY registers for obtaining link | |
888 | **/ | |
889 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
890 | { | |
891 | struct e1000_phy_info *phy = &hw->phy; | |
892 | s32 ret_val; | |
893 | u32 ctrl_ext; | |
75eb0fad | 894 | u16 data; |
bc7f75fa | 895 | |
2d9498f3 | 896 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
897 | if (ret_val) |
898 | return ret_val; | |
899 | ||
900 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
901 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
902 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
903 | ||
2d9498f3 | 904 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
905 | if (ret_val) |
906 | return ret_val; | |
907 | ||
e921eb1a | 908 | /* Options: |
bc7f75fa AK |
909 | * MDI/MDI-X = 0 (default) |
910 | * 0 - Auto for all speeds | |
911 | * 1 - MDI mode | |
912 | * 2 - MDI-X mode | |
913 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
914 | */ | |
915 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
916 | if (ret_val) | |
917 | return ret_val; | |
918 | ||
919 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
920 | ||
921 | switch (phy->mdix) { | |
922 | case 1: | |
923 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
924 | break; | |
925 | case 2: | |
926 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
927 | break; | |
928 | case 0: | |
929 | default: | |
930 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
931 | break; | |
932 | } | |
933 | ||
e921eb1a | 934 | /* Options: |
bc7f75fa AK |
935 | * disable_polarity_correction = 0 (default) |
936 | * Automatic Correction for Reversed Cable Polarity | |
937 | * 0 - Disabled | |
938 | * 1 - Enabled | |
939 | */ | |
940 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
941 | if (phy->disable_polarity_correction) | |
942 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
943 | ||
944 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
945 | if (ret_val) | |
946 | return ret_val; | |
947 | ||
948 | /* SW Reset the PHY so all changes take effect */ | |
6b598e1e | 949 | ret_val = hw->phy.ops.commit(hw); |
bc7f75fa | 950 | if (ret_val) { |
3bb99fe2 | 951 | e_dbg("Error Resetting the PHY\n"); |
bc7f75fa AK |
952 | return ret_val; |
953 | } | |
954 | ||
ad68076e | 955 | /* Bypass Rx and Tx FIFO's */ |
75eb0fad BA |
956 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
957 | E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
ad68076e | 958 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
bc7f75fa AK |
959 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
960 | if (ret_val) | |
961 | return ret_val; | |
962 | ||
75eb0fad | 963 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
964 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
965 | &data); | |
966 | if (ret_val) | |
967 | return ret_val; | |
968 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
75eb0fad | 969 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
970 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
971 | data); | |
972 | if (ret_val) | |
973 | return ret_val; | |
974 | ||
bc7f75fa AK |
975 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
976 | if (ret_val) | |
977 | return ret_val; | |
978 | ||
979 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
980 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
981 | if (ret_val) | |
982 | return ret_val; | |
983 | ||
984 | ctrl_ext = er32(CTRL_EXT); | |
985 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
986 | ew32(CTRL_EXT, ctrl_ext); | |
987 | ||
988 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
989 | if (ret_val) | |
990 | return ret_val; | |
991 | ||
e921eb1a | 992 | /* Do not init these registers when the HW is in IAMT mode, since the |
bc7f75fa AK |
993 | * firmware will have already initialized them. We only initialize |
994 | * them if the HW is not in IAMT mode. | |
995 | */ | |
48768329 | 996 | if (!hw->mac.ops.check_mng_mode(hw)) { |
bc7f75fa AK |
997 | /* Enable Electrical Idle on the PHY */ |
998 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
999 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1000 | if (ret_val) | |
1001 | return ret_val; | |
1002 | ||
75eb0fad BA |
1003 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
1004 | if (ret_val) | |
1005 | return ret_val; | |
bc7f75fa AK |
1006 | |
1007 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1008 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1009 | if (ret_val) | |
1010 | return ret_val; | |
1011 | } | |
1012 | ||
e921eb1a | 1013 | /* Workaround: Disable padding in Kumeran interface in the MAC |
bc7f75fa AK |
1014 | * and in the PHY to avoid CRC errors. |
1015 | */ | |
1016 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1017 | if (ret_val) | |
1018 | return ret_val; | |
1019 | ||
1020 | data |= GG82563_ICR_DIS_PADDING; | |
1021 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1022 | if (ret_val) | |
1023 | return ret_val; | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | /** | |
1029 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1030 | * @hw: pointer to the HW structure | |
1031 | * | |
1032 | * Essentially a wrapper for setting up all things "copper" related. | |
1033 | * This is a function pointer entry point called by the mac module. | |
1034 | **/ | |
1035 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1036 | { | |
1037 | u32 ctrl; | |
1038 | s32 ret_val; | |
1039 | u16 reg_data; | |
1040 | ||
1041 | ctrl = er32(CTRL); | |
1042 | ctrl |= E1000_CTRL_SLU; | |
1043 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1044 | ew32(CTRL, ctrl); | |
1045 | ||
e921eb1a | 1046 | /* Set the mac to wait the maximum time between each |
bc7f75fa | 1047 | * iteration and increase the max iterations when |
ad68076e BA |
1048 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1049 | */ | |
75eb0fad | 1050 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
f0ff4398 | 1051 | 0xFFFF); |
bc7f75fa AK |
1052 | if (ret_val) |
1053 | return ret_val; | |
75eb0fad | 1054 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
f0ff4398 | 1055 | ®_data); |
bc7f75fa AK |
1056 | if (ret_val) |
1057 | return ret_val; | |
1058 | reg_data |= 0x3F; | |
75eb0fad | 1059 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
f0ff4398 | 1060 | reg_data); |
bc7f75fa AK |
1061 | if (ret_val) |
1062 | return ret_val; | |
f0ff4398 BA |
1063 | ret_val = |
1064 | e1000_read_kmrn_reg_80003es2lan(hw, | |
1065 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
1066 | ®_data); | |
bc7f75fa AK |
1067 | if (ret_val) |
1068 | return ret_val; | |
1069 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
f0ff4398 BA |
1070 | ret_val = |
1071 | e1000_write_kmrn_reg_80003es2lan(hw, | |
1072 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
1073 | reg_data); | |
bc7f75fa AK |
1074 | if (ret_val) |
1075 | return ret_val; | |
1076 | ||
1077 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1078 | if (ret_val) | |
1079 | return ret_val; | |
1080 | ||
8649f431 | 1081 | return e1000e_setup_copper_link(hw); |
bc7f75fa AK |
1082 | } |
1083 | ||
75eb0fad BA |
1084 | /** |
1085 | * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up | |
1086 | * @hw: pointer to the HW structure | |
1087 | * @duplex: current duplex setting | |
1088 | * | |
1089 | * Configure the KMRN interface by applying last minute quirks for | |
1090 | * 10/100 operation. | |
1091 | **/ | |
1092 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) | |
1093 | { | |
1094 | s32 ret_val = 0; | |
1095 | u16 speed; | |
1096 | u16 duplex; | |
1097 | ||
1098 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1099 | ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, | |
f0ff4398 | 1100 | &duplex); |
75eb0fad BA |
1101 | if (ret_val) |
1102 | return ret_val; | |
1103 | ||
1104 | if (speed == SPEED_1000) | |
1105 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
1106 | else | |
1107 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); | |
1108 | } | |
1109 | ||
1110 | return ret_val; | |
1111 | } | |
1112 | ||
bc7f75fa AK |
1113 | /** |
1114 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1115 | * @hw: pointer to the HW structure | |
1116 | * @duplex: current duplex setting | |
1117 | * | |
1118 | * Configure the KMRN interface by applying last minute quirks for | |
1119 | * 10/100 operation. | |
1120 | **/ | |
1121 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1122 | { | |
1123 | s32 ret_val; | |
1124 | u32 tipg; | |
2d9498f3 DG |
1125 | u32 i = 0; |
1126 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1127 | |
1128 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
f0ff4398 BA |
1129 | ret_val = |
1130 | e1000_write_kmrn_reg_80003es2lan(hw, | |
1131 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1132 | reg_data); | |
bc7f75fa AK |
1133 | if (ret_val) |
1134 | return ret_val; | |
1135 | ||
1136 | /* Configure Transmit Inter-Packet Gap */ | |
1137 | tipg = er32(TIPG); | |
1138 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1139 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1140 | ew32(TIPG, tipg); | |
1141 | ||
2d9498f3 DG |
1142 | do { |
1143 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1144 | if (ret_val) | |
1145 | return ret_val; | |
1146 | ||
1147 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1148 | if (ret_val) | |
1149 | return ret_val; | |
1150 | i++; | |
1151 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1152 | |
1153 | if (duplex == HALF_DUPLEX) | |
1154 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1155 | else | |
1156 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1157 | ||
520d6f22 | 1158 | return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
bc7f75fa AK |
1159 | } |
1160 | ||
1161 | /** | |
1162 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1163 | * @hw: pointer to the HW structure | |
1164 | * | |
1165 | * Configure the KMRN interface by applying last minute quirks for | |
1166 | * gigabit operation. | |
1167 | **/ | |
1168 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1169 | { | |
1170 | s32 ret_val; | |
2d9498f3 | 1171 | u16 reg_data, reg_data2; |
bc7f75fa | 1172 | u32 tipg; |
2d9498f3 | 1173 | u32 i = 0; |
bc7f75fa AK |
1174 | |
1175 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
f0ff4398 BA |
1176 | ret_val = |
1177 | e1000_write_kmrn_reg_80003es2lan(hw, | |
1178 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1179 | reg_data); | |
bc7f75fa AK |
1180 | if (ret_val) |
1181 | return ret_val; | |
1182 | ||
1183 | /* Configure Transmit Inter-Packet Gap */ | |
1184 | tipg = er32(TIPG); | |
1185 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1186 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1187 | ew32(TIPG, tipg); | |
1188 | ||
2d9498f3 DG |
1189 | do { |
1190 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1191 | if (ret_val) | |
1192 | return ret_val; | |
1193 | ||
1194 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1195 | if (ret_val) | |
1196 | return ret_val; | |
1197 | i++; | |
1198 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1199 | |
1200 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
bc7f75fa | 1201 | |
7eb61d81 | 1202 | return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
bc7f75fa AK |
1203 | } |
1204 | ||
75eb0fad BA |
1205 | /** |
1206 | * e1000_read_kmrn_reg_80003es2lan - Read kumeran register | |
1207 | * @hw: pointer to the HW structure | |
1208 | * @offset: register offset to be read | |
1209 | * @data: pointer to the read data | |
1210 | * | |
1211 | * Acquire semaphore, then read the PHY register at offset | |
1212 | * using the kumeran interface. The information retrieved is stored in data. | |
1213 | * Release the semaphore before exiting. | |
1214 | **/ | |
fa4c16da HE |
1215 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1216 | u16 *data) | |
75eb0fad BA |
1217 | { |
1218 | u32 kmrnctrlsta; | |
70806a7f | 1219 | s32 ret_val; |
75eb0fad BA |
1220 | |
1221 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1222 | if (ret_val) | |
1223 | return ret_val; | |
1224 | ||
1225 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
f0ff4398 | 1226 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; |
75eb0fad | 1227 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
945a5151 | 1228 | e1e_flush(); |
75eb0fad BA |
1229 | |
1230 | udelay(2); | |
1231 | ||
1232 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
1233 | *data = (u16)kmrnctrlsta; | |
1234 | ||
1235 | e1000_release_mac_csr_80003es2lan(hw); | |
1236 | ||
1237 | return ret_val; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * e1000_write_kmrn_reg_80003es2lan - Write kumeran register | |
1242 | * @hw: pointer to the HW structure | |
1243 | * @offset: register offset to write to | |
1244 | * @data: data to write at register offset | |
1245 | * | |
1246 | * Acquire semaphore, then write the data to PHY register | |
1247 | * at the offset using the kumeran interface. Release semaphore | |
1248 | * before exiting. | |
1249 | **/ | |
fa4c16da HE |
1250 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1251 | u16 data) | |
75eb0fad BA |
1252 | { |
1253 | u32 kmrnctrlsta; | |
70806a7f | 1254 | s32 ret_val; |
75eb0fad BA |
1255 | |
1256 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1257 | if (ret_val) | |
1258 | return ret_val; | |
1259 | ||
1260 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
f0ff4398 | 1261 | E1000_KMRNCTRLSTA_OFFSET) | data; |
75eb0fad | 1262 | ew32(KMRNCTRLSTA, kmrnctrlsta); |
945a5151 | 1263 | e1e_flush(); |
75eb0fad BA |
1264 | |
1265 | udelay(2); | |
1266 | ||
1267 | e1000_release_mac_csr_80003es2lan(hw); | |
1268 | ||
1269 | return ret_val; | |
1270 | } | |
1271 | ||
608f8a0d BA |
1272 | /** |
1273 | * e1000_read_mac_addr_80003es2lan - Read device MAC address | |
1274 | * @hw: pointer to the HW structure | |
1275 | **/ | |
1276 | static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) | |
1277 | { | |
70806a7f | 1278 | s32 ret_val; |
608f8a0d | 1279 | |
e921eb1a | 1280 | /* If there's an alternate MAC address place it in RAR0 |
608f8a0d BA |
1281 | * so that it will override the Si installed default perm |
1282 | * address. | |
1283 | */ | |
1284 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1285 | if (ret_val) | |
5015e53a | 1286 | return ret_val; |
608f8a0d | 1287 | |
5015e53a | 1288 | return e1000_read_mac_addr_generic(hw); |
608f8a0d BA |
1289 | } |
1290 | ||
17f208de BA |
1291 | /** |
1292 | * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down | |
1293 | * @hw: pointer to the HW structure | |
1294 | * | |
1295 | * In the case of a PHY power down to save power, or to turn off link during a | |
1296 | * driver unload, or wake on lan is not enabled, remove the link. | |
1297 | **/ | |
1298 | static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) | |
1299 | { | |
1300 | /* If the management interface is not enabled, then power down */ | |
1301 | if (!(hw->mac.ops.check_mng_mode(hw) || | |
1302 | hw->phy.ops.check_reset_block(hw))) | |
1303 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1304 | } |
1305 | ||
bc7f75fa AK |
1306 | /** |
1307 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1308 | * @hw: pointer to the HW structure | |
1309 | * | |
1310 | * Clears the hardware counters by reading the counter registers. | |
1311 | **/ | |
1312 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1313 | { | |
bc7f75fa AK |
1314 | e1000e_clear_hw_cntrs_base(hw); |
1315 | ||
99673d9b BA |
1316 | er32(PRC64); |
1317 | er32(PRC127); | |
1318 | er32(PRC255); | |
1319 | er32(PRC511); | |
1320 | er32(PRC1023); | |
1321 | er32(PRC1522); | |
1322 | er32(PTC64); | |
1323 | er32(PTC127); | |
1324 | er32(PTC255); | |
1325 | er32(PTC511); | |
1326 | er32(PTC1023); | |
1327 | er32(PTC1522); | |
1328 | ||
1329 | er32(ALGNERRC); | |
1330 | er32(RXERRC); | |
1331 | er32(TNCRS); | |
1332 | er32(CEXTERR); | |
1333 | er32(TSCTC); | |
1334 | er32(TSCTFC); | |
1335 | ||
1336 | er32(MGTPRC); | |
1337 | er32(MGTPDC); | |
1338 | er32(MGTPTC); | |
1339 | ||
1340 | er32(IAC); | |
1341 | er32(ICRXOC); | |
1342 | ||
1343 | er32(ICRXPTC); | |
1344 | er32(ICRXATC); | |
1345 | er32(ICTXPTC); | |
1346 | er32(ICTXATC); | |
1347 | er32(ICTXQEC); | |
1348 | er32(ICTXQMTC); | |
1349 | er32(ICRXDMTC); | |
bc7f75fa AK |
1350 | } |
1351 | ||
8ce9d6c7 | 1352 | static const struct e1000_mac_operations es2_mac_ops = { |
608f8a0d | 1353 | .read_mac_addr = e1000_read_mac_addr_80003es2lan, |
d1964eb1 | 1354 | .id_led_init = e1000e_id_led_init_generic, |
dbf80dcb | 1355 | .blink_led = e1000e_blink_led_generic, |
4662e82b | 1356 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1357 | /* check_for_link dependent on media type */ |
1358 | .cleanup_led = e1000e_cleanup_led_generic, | |
1359 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1360 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1361 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa AK |
1362 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, |
1363 | .led_on = e1000e_led_on_generic, | |
1364 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1365 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1366 | .write_vfta = e1000_write_vfta_generic, |
1367 | .clear_vfta = e1000_clear_vfta_generic, | |
bc7f75fa AK |
1368 | .reset_hw = e1000_reset_hw_80003es2lan, |
1369 | .init_hw = e1000_init_hw_80003es2lan, | |
1a46b40f | 1370 | .setup_link = e1000e_setup_link_generic, |
bc7f75fa | 1371 | /* setup_physical_interface dependent on media type */ |
a4f58f54 | 1372 | .setup_led = e1000e_setup_led_generic, |
57cde763 | 1373 | .config_collision_dist = e1000e_config_collision_dist_generic, |
69e1e019 | 1374 | .rar_set = e1000e_rar_set_generic, |
bc7f75fa AK |
1375 | }; |
1376 | ||
8ce9d6c7 | 1377 | static const struct e1000_phy_operations es2_phy_ops = { |
94d8186a | 1378 | .acquire = e1000_acquire_phy_80003es2lan, |
94e5b651 | 1379 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1380 | .check_reset_block = e1000e_check_reset_block_generic, |
55c5f55e BA |
1381 | .commit = e1000e_phy_sw_reset, |
1382 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, | |
1383 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1384 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
1385 | .get_info = e1000e_get_phy_info_m88, | |
1386 | .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
94d8186a | 1387 | .release = e1000_release_phy_80003es2lan, |
55c5f55e BA |
1388 | .reset = e1000e_phy_hw_reset_generic, |
1389 | .set_d0_lplu_state = NULL, | |
1390 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1391 | .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, | |
1392 | .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, | |
bc7f75fa AK |
1393 | }; |
1394 | ||
8ce9d6c7 | 1395 | static const struct e1000_nvm_operations es2_nvm_ops = { |
94d8186a BA |
1396 | .acquire = e1000_acquire_nvm_80003es2lan, |
1397 | .read = e1000e_read_nvm_eerd, | |
1398 | .release = e1000_release_nvm_80003es2lan, | |
e85e3639 | 1399 | .reload = e1000e_reload_nvm_generic, |
94d8186a | 1400 | .update = e1000e_update_nvm_checksum_generic, |
bc7f75fa | 1401 | .valid_led_default = e1000e_valid_led_default, |
94d8186a BA |
1402 | .validate = e1000e_validate_nvm_checksum_generic, |
1403 | .write = e1000_write_nvm_80003es2lan, | |
bc7f75fa AK |
1404 | }; |
1405 | ||
8ce9d6c7 | 1406 | const struct e1000_info e1000_es2_info = { |
bc7f75fa AK |
1407 | .mac = e1000_80003es2lan, |
1408 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1409 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1410 | | FLAG_HAS_WOL |
1411 | | FLAG_APME_IN_CTRL3 | |
bc7f75fa | 1412 | | FLAG_HAS_CTRLEXT_ON_LOAD |
bc7f75fa AK |
1413 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1414 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1415 | | FLAG_APME_CHECK_PORT_B | |
6a92f732 | 1416 | | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */ |
3a3b7586 | 1417 | .flags2 = FLAG2_DMA_BURST, |
bc7f75fa | 1418 | .pba = 38, |
2adc55c9 | 1419 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1420 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1421 | .mac_ops = &es2_mac_ops, |
1422 | .phy_ops = &es2_phy_ops, | |
1423 | .nvm_ops = &es2_nvm_ops, | |
1424 | }; | |
1425 |