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e1000e: fix flow-control thresholds for jumbo frames on 82579/I217/I218
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / e1000.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
86d70e53 34#include <linux/bitops.h>
bc7f75fa
AK		 35#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
d8014dbc 40#include <linux/pci.h>
6f461f6c 41#include <linux/pci-aspm.h>
fe46f58f 42#include <linux/crc32.h>
86d70e53 43#include <linux/if_vlan.h>
b67e1913
BA		 44#include <linux/clocksource.h>
45#include <linux/net_tstamp.h>
bc7f75fa
AK		 46
47#include "hw.h"
48
49struct e1000_info;
50
44defeb3 51#define e_dbg(format, arg...) \
8544b9f7 52 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 53#define e_err(format, arg...) \
8544b9f7 54 netdev_err(adapter->netdev, format, ## arg)
44defeb3 55#define e_info(format, arg...) \
8544b9f7 56 netdev_info(adapter->netdev, format, ## arg)
44defeb3 57#define e_warn(format, arg...) \
8544b9f7 58 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 59#define e_notice(format, arg...) \
8544b9f7 60 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 61
62
98a1708d 63/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 64#define E1000E_INT_MODE_LEGACY 0
65#define E1000E_INT_MODE_MSI 1
66#define E1000E_INT_MODE_MSIX 2
67
ad68076e 68/* Tx/Rx descriptor defines */
bc7f75fa
AK		 69#define E1000_DEFAULT_TXD 256
70#define E1000_MAX_TXD 4096
7b1be198 71#define E1000_MIN_TXD 64
bc7f75fa
AK		 72
73#define E1000_DEFAULT_RXD 256
74#define E1000_MAX_RXD 4096
7b1be198 75#define E1000_MIN_RXD 64
bc7f75fa 76
de5b3077
AK		 77#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
78#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
79
bc7f75fa
AK		 80/* Early Receive defines */
81#define E1000_ERT_2048 0x100
82
83#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
84
85/* How many Tx Descriptors do we need to call netif_wake_queue ? */
86/* How many Rx Buffers do we bundle into one write to the hardware ? */
87#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
88
89#define AUTO_ALL_MODES 0
90#define E1000_EEPROM_APME 0x0400
91
92#define E1000_MNG_VLAN_NONE (-1)
93
94/* Number of packet split data buffers (not including the header buffer) */
95#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
96
2adc55c9
BA		 97#define DEFAULT_JUMBO 9234
98
a4f58f54
BA		 99/* BM/HV Specific Registers */
100#define BM_PORT_CTRL_PAGE 769
101
102#define PHY_UPPER_SHIFT 21
103#define BM_PHY_REG(page, reg) \
104 (((reg) & MAX_PHY_REG_ADDRESS) |\
105 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
106 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
107
108/* PHY Wakeup Registers and defines */
3ebfc7c9 109#define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
a4f58f54
BA		 110#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
111#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
112#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
113#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
114#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
115#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
116#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
117#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
118#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
119
120#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
121#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
122#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
123#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
124#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
125#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
126#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
127
2b6b168d
BA		 128#define HV_STATS_PAGE 778
129#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
130#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
131#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
132#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
133#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
134#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
135#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
136#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
137#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
138#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
139#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
140#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
141#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
142#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
a4f58f54 143
38eb394e
BA		 144#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
145
1d5846b9
BA		 146/* BM PHY Copper Specific Status */
147#define BM_CS_STATUS 17
148#define BM_CS_STATUS_LINK_UP 0x0400
149#define BM_CS_STATUS_RESOLVED 0x0800
150#define BM_CS_STATUS_SPEED_MASK 0xC000
151#define BM_CS_STATUS_SPEED_1000 0x8000
152
153/* 82577 Mobile Phy Status Register */
154#define HV_M_STATUS 26
155#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
156#define HV_M_STATUS_SPEED_MASK 0x0300
157#define HV_M_STATUS_SPEED_1000 0x0200
158#define HV_M_STATUS_LINK_UP 0x0040
159
c6e7f51e
BA		 160#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
161#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
162
23606cf5
RW		 163/* Time to wait before putting the device into D3 if there's no link (in ms). */
164#define LINK_TIMEOUT 100
165
e921eb1a 166/* Count for polling __E1000_RESET condition every 10-20msec.
bb9e44d0
BA		 167 * Experimentation has shown the reset can take approximately 210msec.
168 */
169#define E1000_CHECK_RESET_COUNT 25
170
3a3b7586
JB		 171#define DEFAULT_RDTR 0
172#define DEFAULT_RADV 8
173#define BURST_RDTR 0x20
174#define BURST_RADV 0x20
175
e921eb1a 176/* in the case of WTHRESH, it appears at least the 82571/2 hardware
3a3b7586 177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
8edc0e62
HS		 178 * WTHRESH=4, so a setting of 5 gives the most efficient bus
179 * utilization but to avoid possible Tx stalls, set it to 1
3a3b7586
JB		 180 */
181#define E1000_TXDCTL_DMA_BURST_ENABLE \
182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
183 E1000_TXDCTL_COUNT_DESC | \
8edc0e62 184 (1 << 16) | /* wthresh must be +1 more than desired */\
3a3b7586
JB		 185 (1 << 8) | /* hthresh */ \
186 0x1f) /* pthresh */
187
188#define E1000_RXDCTL_DMA_BURST_ENABLE \
189 (0x01000000 | /* set descriptor granularity */ \
190 (4 << 16) | /* set writeback threshold */ \
191 (4 << 8) | /* set prefetch threshold */ \
192 0x20) /* set hthresh */
193
194#define E1000_TIDV_FPD (1 << 31)
195#define E1000_RDTR_FPD (1 << 31)
196
bc7f75fa
AK		 197enum e1000_boards {
198 board_82571,
199 board_82572,
200 board_82573,
4662e82b 201 board_82574,
8c81c9c3 202 board_82583,
bc7f75fa
AK		 203 board_80003es2lan,
204 board_ich8lan,
205 board_ich9lan,
f4187b56 206 board_ich10lan,
a4f58f54 207 board_pchlan,
d3738bb8 208 board_pch2lan,
2fbe4526 209 board_pch_lpt,
bc7f75fa
AK		 210};
211
bc7f75fa
AK		 212struct e1000_ps_page {
213 struct page *page;
214 u64 dma; /* must be u64 - written to hw */
215};
216
e921eb1a 217/* wrappers around a pointer to a socket buffer,
bc7f75fa
AK		 218 * so a DMA handle can be stored along with the buffer
219 */
220struct e1000_buffer {
221 dma_addr_t dma;
222 struct sk_buff *skb;
223 union {
ad68076e 224 /* Tx */
bc7f75fa
AK		 225 struct {
226 unsigned long time_stamp;
227 u16 length;
228 u16 next_to_watch;
9ed318d5
TH		 229 unsigned int segs;
230 unsigned int bytecount;
03b1320d 231 u16 mapped_as_page;
bc7f75fa 232 };
ad68076e 233 /* Rx */
03b1320d
AD		 234 struct {
235 /* arrays of page information for packet split */
236 struct e1000_ps_page *ps_pages;
237 struct page *page;
238 };
bc7f75fa 239 };
bc7f75fa
AK		 240};
241
242struct e1000_ring {
55aa6985 243 struct e1000_adapter *adapter; /* back pointer to adapter */
bc7f75fa
AK		 244 void *desc; /* pointer to ring memory */
245 dma_addr_t dma; /* phys address of ring */
246 unsigned int size; /* length of ring in bytes */
247 unsigned int count; /* number of desc. in ring */
248
249 u16 next_to_use;
250 u16 next_to_clean;
251
c5083cf6
BA		 252 void __iomem *head;
253 void __iomem *tail;
bc7f75fa
AK		 254
255 /* array of buffer information structs */
256 struct e1000_buffer *buffer_info;
257
4662e82b
BA		 258 char name[IFNAMSIZ + 5];
259 u32 ims_val;
260 u32 itr_val;
c5083cf6 261 void __iomem *itr_register;
4662e82b
BA		 262 int set_itr;
263
bc7f75fa 264 struct sk_buff *rx_skb_top;
bc7f75fa
AK		 265};
266
7c25769f
BA		 267/* PHY register snapshot values */
268struct e1000_phy_regs {
269 u16 bmcr; /* basic mode control register */
270 u16 bmsr; /* basic mode status register */
271 u16 advertise; /* auto-negotiation advertisement */
272 u16 lpa; /* link partner ability register */
273 u16 expansion; /* auto-negotiation expansion reg */
274 u16 ctrl1000; /* 1000BASE-T control register */
275 u16 stat1000; /* 1000BASE-T status register */
276 u16 estatus; /* extended status register */
277};
278
bc7f75fa
AK		 279/* board specific private data structure */
280struct e1000_adapter {
281 struct timer_list watchdog_timer;
282 struct timer_list phy_info_timer;
283 struct timer_list blink_timer;
284
285 struct work_struct reset_task;
286 struct work_struct watchdog_task;
287
288 const struct e1000_info *ei;
289
86d70e53 290 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
bc7f75fa
AK		 291 u32 bd_number;
292 u32 rx_buffer_len;
293 u16 mng_vlan_id;
294 u16 link_speed;
295 u16 link_duplex;
84527590 296 u16 eeprom_vers;
bc7f75fa 297
bc7f75fa
AK		 298 /* track device up/down/testing state */
299 unsigned long state;
300
301 /* Interrupt Throttle Rate */
302 u32 itr;
303 u32 itr_setting;
304 u16 tx_itr;
305 u16 rx_itr;
306
e921eb1a 307 /* Tx */
bc7f75fa
AK		 308 struct e1000_ring *tx_ring /* One per active queue */
309 ____cacheline_aligned_in_smp;
d821a4c4 310 u32 tx_fifo_limit;
bc7f75fa
AK		 311
312 struct napi_struct napi;
313
bc7f75fa
AK		 314 unsigned int restart_queue;
315 u32 txd_cmd;
316
317 bool detect_tx_hung;
09357b00 318 bool tx_hang_recheck;
bc7f75fa
AK		 319 u8 tx_timeout_factor;
320
321 u32 tx_int_delay;
322 u32 tx_abs_int_delay;
323
324 unsigned int total_tx_bytes;
325 unsigned int total_tx_packets;
326 unsigned int total_rx_bytes;
327 unsigned int total_rx_packets;
328
ad68076e 329 /* Tx stats */
bc7f75fa
AK		 330 u64 tpt_old;
331 u64 colc_old;
7c25769f
BA		 332 u32 gotc;
333 u64 gotc_old;
bc7f75fa
AK		 334 u32 tx_timeout_count;
335 u32 tx_fifo_head;
336 u32 tx_head_addr;
337 u32 tx_fifo_size;
338 u32 tx_dma_failed;
339
e921eb1a 340 /* Rx */
55aa6985
BA		 341 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
342 int work_to_do) ____cacheline_aligned_in_smp;
343 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
344 gfp_t gfp);
bc7f75fa
AK		 345 struct e1000_ring *rx_ring;
346
347 u32 rx_int_delay;
348 u32 rx_abs_int_delay;
349
ad68076e 350 /* Rx stats */
bc7f75fa
AK		 351 u64 hw_csum_err;
352 u64 hw_csum_good;
353 u64 rx_hdr_split;
7c25769f
BA		 354 u32 gorc;
355 u64 gorc_old;
bc7f75fa
AK		 356 u32 alloc_rx_buff_failed;
357 u32 rx_dma_failed;
b67e1913 358 u32 rx_hwtstamp_cleared;
bc7f75fa
AK		 359
360 unsigned int rx_ps_pages;
361 u16 rx_ps_bsize0;
318a94d6
JK		 362 u32 max_frame_size;
363 u32 min_frame_size;
bc7f75fa
AK		 364
365 /* OS defined structs */
366 struct net_device *netdev;
367 struct pci_dev *pdev;
bc7f75fa
AK		 368
369 /* structs defined in e1000_hw.h */
370 struct e1000_hw hw;
371
67fd4fcb 372 spinlock_t stats64_lock;
bc7f75fa
AK		 373 struct e1000_hw_stats stats;
374 struct e1000_phy_info phy_info;
375 struct e1000_phy_stats phy_stats;
376
7c25769f
BA		 377 /* Snapshot of PHY registers */
378 struct e1000_phy_regs phy_regs;
379
bc7f75fa
AK		 380 struct e1000_ring test_tx_ring;
381 struct e1000_ring test_rx_ring;
382 u32 test_icr;
383
384 u32 msg_enable;
8e86acd7 385 unsigned int num_vectors;
4662e82b
BA		 386 struct msix_entry *msix_entries;
387 int int_mode;
388 u32 eiac_mask;
bc7f75fa
AK		 389
390 u32 eeprom_wol;
391 u32 wol;
392 u32 pba;
2adc55c9 393 u32 max_hw_frame_size;
bc7f75fa 394
318a94d6 395 bool fc_autoneg;
bc7f75fa 396
bc7f75fa 397 unsigned int flags;
eb7c3adb 398 unsigned int flags2;
a8f88ff5
JB		 399 struct work_struct downshift_task;
400 struct work_struct update_phy_task;
41cec6f1 401 struct work_struct print_hang_task;
23606cf5
RW		 402
403 bool idle_check;
ff10e13c 404 int phy_hang_count;
55aa6985
BA		 405
406 u16 tx_ring_count;
407 u16 rx_ring_count;
b67e1913
BA		 408
409 struct hwtstamp_config hwtstamp_config;
410 struct delayed_work systim_overflow_work;
411 struct sk_buff *tx_hwtstamp_skb;
412 struct work_struct tx_hwtstamp_work;
413 spinlock_t systim_lock; /* protects SYSTIML/H regsters */
414 struct cyclecounter cc;
415 struct timecounter tc;
bc7f75fa
AK		 416};
417
418struct e1000_info {
419 enum e1000_mac_type mac;
420 unsigned int flags;
6f461f6c 421 unsigned int flags2;
bc7f75fa 422 u32 pba;
2adc55c9 423 u32 max_hw_frame_size;
69e3fd8c 424 s32 (*get_variants)(struct e1000_adapter *);
8ce9d6c7
JK		 425 const struct e1000_mac_operations *mac_ops;
426 const struct e1000_phy_operations *phy_ops;
427 const struct e1000_nvm_operations *nvm_ops;
bc7f75fa
AK		 428};
429
b67e1913
BA		 430/* The system time is maintained by a 64-bit counter comprised of the 32-bit
431 * SYSTIMH and SYSTIML registers. How the counter increments (and therefore
432 * its resolution) is based on the contents of the TIMINCA register - it
433 * increments every incperiod (bits 31:24) clock ticks by incvalue (bits 23:0).
434 * For the best accuracy, the incperiod should be as small as possible. The
435 * incvalue is scaled by a factor as large as possible (while still fitting
436 * in bits 23:0) so that relatively small clock corrections can be made.
437 *
438 * As a result, a shift of INCVALUE_SHIFT_n is used to fit a value of
439 * INCVALUE_n into the TIMINCA register allowing 32+8+(24-INCVALUE_SHIFT_n)
440 * bits to count nanoseconds leaving the rest for fractional nonseconds.
441 */
442#define INCVALUE_96MHz 125
443#define INCVALUE_SHIFT_96MHz 17
444#define INCPERIOD_SHIFT_96MHz 2
445#define INCPERIOD_96MHz (12 >> INCPERIOD_SHIFT_96MHz)
446
447#define INCVALUE_25MHz 40
448#define INCVALUE_SHIFT_25MHz 18
449#define INCPERIOD_25MHz 1
450
451/* Another drawback of scaling the incvalue by a large factor is the
452 * 64-bit SYSTIM register overflows more quickly. This is dealt with
453 * by simply reading the clock before it overflows.
454 *
455 * Clock ns bits Overflows after
456 * ~~~~~~ ~~~~~~~ ~~~~~~~~~~~~~~~
457 * 96MHz 47-bit 2^(47-INCPERIOD_SHIFT_96MHz) / 10^9 / 3600 = 9.77 hrs
458 * 25MHz 46-bit 2^46 / 10^9 / 3600 = 19.55 hours
459 */
460#define E1000_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 60 * 4)
461
bc7f75fa
AK		 462/* hardware capability, feature, and workaround flags */
463#define FLAG_HAS_AMT (1 << 0)
464#define FLAG_HAS_FLASH (1 << 1)
465#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
466#define FLAG_HAS_WOL (1 << 3)
79d4e908 467/* reserved bit4 */
bc7f75fa
AK		 468#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
469#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
470#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 471#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 472#define FLAG_IS_ICH (1 << 9)
4662e82b 473#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 474#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
475#define FLAG_IS_QUAD_PORT_A (1 << 12)
476#define FLAG_IS_QUAD_PORT (1 << 13)
b67e1913 477#define FLAG_HAS_HW_TIMESTAMP (1 << 14)
bc7f75fa
AK		 478#define FLAG_APME_IN_WUC (1 << 15)
479#define FLAG_APME_IN_CTRL3 (1 << 16)
480#define FLAG_APME_CHECK_PORT_B (1 << 17)
481#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
482#define FLAG_NO_WAKE_UCAST (1 << 19)
483#define FLAG_MNG_PT_ENABLED (1 << 20)
484#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
485#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
486#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
487#define FLAG_RX_NEEDS_RESTART (1 << 24)
488#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
489#define FLAG_SMART_POWER_DOWN (1 << 26)
490#define FLAG_MSI_ENABLED (1 << 27)
dc221294 491/* reserved (1 << 28) */
bc7f75fa 492#define FLAG_TSO_FORCE (1 << 29)
12d43f7d 493#define FLAG_RESTART_NOW (1 << 30)
f8d59f78 494#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 495
eb7c3adb 496#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 497#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 498#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 499#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 500#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 501#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 502#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 503#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 504#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 505#define FLAG2_CHECK_PHY_HANG (1 << 9)
7f99ae63 506#define FLAG2_NO_DISABLE_RX (1 << 10)
c6e7f51e 507#define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
0184039a 508#define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
b67e1913 509#define FLAG2_CHECK_RX_HWTSTAMP (1 << 13)
eb7c3adb 510
bc7f75fa
AK		 511#define E1000_RX_DESC_PS(R, i) \
512 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
5f450212
BA		 513#define E1000_RX_DESC_EXT(R, i) \
514 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
bc7f75fa 515#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
bc7f75fa
AK		 516#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
517#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
518
519enum e1000_state_t {
520 __E1000_TESTING,
521 __E1000_RESETTING,
a90b412c 522 __E1000_ACCESS_SHARED_RESOURCE,
bc7f75fa
AK		 523 __E1000_DOWN
524};
525
526enum latency_range {
527 lowest_latency = 0,
528 low_latency = 1,
529 bulk_latency = 2,
530 latency_invalid = 255
531};
532
533extern char e1000e_driver_name[];
534extern const char e1000e_driver_version[];
535
536extern void e1000e_check_options(struct e1000_adapter *adapter);
537extern void e1000e_set_ethtool_ops(struct net_device *netdev);
538
539extern int e1000e_up(struct e1000_adapter *adapter);
540extern void e1000e_down(struct e1000_adapter *adapter);
541extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
542extern void e1000e_reset(struct e1000_adapter *adapter);
543extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
55aa6985
BA		 544extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
545extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
546extern void e1000e_free_rx_resources(struct e1000_ring *ring);
547extern void e1000e_free_tx_resources(struct e1000_ring *ring);
67fd4fcb
JK		 548extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
549 struct rtnl_link_stats64
550 *stats);
4662e82b
BA		 551extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
552extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
31dbe5b4
BA		 553extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
554extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
22a4cca2 555extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
bc7f75fa
AK		 556
557extern unsigned int copybreak;
558
559extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
560
8ce9d6c7
JK		 561extern const struct e1000_info e1000_82571_info;
562extern const struct e1000_info e1000_82572_info;
563extern const struct e1000_info e1000_82573_info;
564extern const struct e1000_info e1000_82574_info;
565extern const struct e1000_info e1000_82583_info;
566extern const struct e1000_info e1000_ich8_info;
567extern const struct e1000_info e1000_ich9_info;
568extern const struct e1000_info e1000_ich10_info;
569extern const struct e1000_info e1000_pch_info;
570extern const struct e1000_info e1000_pch2_info;
2fbe4526 571extern const struct e1000_info e1000_pch_lpt_info;
8ce9d6c7 572extern const struct e1000_info e1000_es2_info;
bc7f75fa 573
073287c0
BA		 574extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
575 u32 pba_num_size);
bc7f75fa
AK		 576
577extern s32 e1000e_commit_phy(struct e1000_hw *hw);
578
579extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
580
581extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
582extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
583
4a770358 584extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 585extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
586 bool state);
587extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
588extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
99730e4c
BA		 589extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
590extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
bb436b20 591extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
d3738bb8
BA		 592extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
593extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 594
595extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
596extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
597extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 598extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 599extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
600extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
601extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
602extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 603extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
604extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 605extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
606extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
607extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
608extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
d1964eb1 609extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
bc7f75fa
AK		 610extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
611extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
612extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
613extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
1a46b40f 614extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
caaddaf8 615extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 616extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 617extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
618 u8 *mc_addr_list,
ab8932f3 619 u32 mc_addr_count);
69e1e019 620extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
bc7f75fa
AK		 621extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
622extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
623extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
624extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
57cde763 625extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
bc7f75fa
AK		 626extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
627extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
dbf80dcb 628extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
caaddaf8 629extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 630extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 631extern void e1000e_reset_adaptive(struct e1000_hw *hw);
632extern void e1000e_update_adaptive(struct e1000_hw *hw);
633
634extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
635extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
636extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
637extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
638extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
639extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
640extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
2b6b168d 641extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
bc7f75fa 642extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 643extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
644 u16 *data);
bc7f75fa
AK		 645extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
646extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
647extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 648extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
649 u16 data);
bc7f75fa
AK		 650extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
651extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
652extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
653extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
654extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
655extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
656extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 657extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 658extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 659extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
660extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
661extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
2b6b168d
BA		 662extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
663 u16 *phy_reg);
664extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
665 u16 *phy_reg);
4662e82b
BA		 666extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
667extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 668extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
669extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 670extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
671 u16 data);
bc7f75fa 672extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 673extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
674 u16 *data);
bc7f75fa
AK		 675extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
676 u32 usec_interval, bool *success);
677extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 678extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
679extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 680extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
681extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 682extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 683extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 684extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
685 u16 *data);
2b6b168d
BA		 686extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
687 u16 *data);
a4f58f54 688extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 689extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
690 u16 data);
2b6b168d
BA		 691extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
692 u16 data);
a4f58f54
BA		 693extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
694extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
695extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
696extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
697extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
698extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 699
0be84010
BA		 700extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
701extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
702extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
703extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
704extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
ff10e13c 705extern bool e1000_check_phy_82574(struct e1000_hw *hw);
203e4151 706extern s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
0be84010 707
bc7f75fa
AK		 708static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
709{
94d8186a 710 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 711}
712
bc7f75fa
AK		 713static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
714{
94d8186a 715 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 716}
717
f1430d69
BA		 718static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
719{
720 return hw->phy.ops.read_reg_locked(hw, offset, data);
721}
722
bc7f75fa
AK		 723static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
724{
94d8186a 725 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 726}
727
f1430d69
BA		 728static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
729{
730 return hw->phy.ops.write_reg_locked(hw, offset, data);
731}
732
bc7f75fa
AK		 733static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
734{
735 return hw->phy.ops.get_cable_length(hw);
736}
737
738extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
739extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
740extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
741extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
bc7f75fa
AK		 742extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
743extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
744extern void e1000e_release_nvm(struct e1000_hw *hw);
e85e3639 745extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
608f8a0d
BA		 746extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
747
748static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
749{
750 if (hw->mac.ops.read_mac_addr)
751 return hw->mac.ops.read_mac_addr(hw);
752
753 return e1000_read_mac_addr_generic(hw);
754}
bc7f75fa
AK		 755
756static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
757{
94d8186a 758 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 759}
760
761static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
762{
94d8186a 763 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 764}
765
766static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
767{
94d8186a 768 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 769}
770
771static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
772{
94d8186a 773 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 774}
775
776static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
777{
94d8186a 778 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 779}
780
4662e82b 781extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 782extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
783extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
784
785static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
786{
787 return readl(hw->hw_addr + reg);
788}
789
bdc125f7
BA		 790#define er32(reg) __er32(hw, E1000_##reg)
791
792/**
793 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
794 * @hw: pointer to the HW structure
795 *
796 * When updating the MAC CSR registers, the Manageability Engine (ME) could
797 * be accessing the registers at the same time. Normally, this is handled in
798 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
799 * accesses later than it should which could result in the register to have
800 * an incorrect value. Workaround this by checking the FWSM register which
801 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
802 * and try again a number of times.
803 **/
804static inline s32 __ew32_prepare(struct e1000_hw *hw)
805{
806 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
807
808 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
809 udelay(50);
810
811 return i;
812}
813
bc7f75fa
AK		 814static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
815{
bdc125f7
BA		 816 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
817 __ew32_prepare(hw);
818
bc7f75fa
AK		 819 writel(val, hw->hw_addr + reg);
820}
821
bdc125f7
BA		 822#define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
823
824#define e1e_flush() er32(STATUS)
825
826#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
827 (__ew32((a), (reg + ((offset) << 2)), (value)))
828
829#define E1000_READ_REG_ARRAY(a, reg, offset) \
830 (readl((a)->hw_addr + reg + ((offset) << 2)))
831
bc7f75fa 832#endif /* _E1000_H_ */
Linux kernel - Deliverables
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