projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
e1000e: cosmetic move of function prototypes to the new mac.h
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / hw.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _E1000_HW_H_
30#define _E1000_HW_H_
31
a9bb6290 32#include "defines.h"
bc7f75fa
AK		 33
34struct e1000_hw;
bc7f75fa 35
bc7f75fa
AK		 36enum e1e_registers {
37 E1000_CTRL = 0x00000, /* Device Control - RW */
38 E1000_STATUS = 0x00008, /* Device Status - RO */
39 E1000_EECD = 0x00010, /* EEPROM/Flash Control - RW */
40 E1000_EERD = 0x00014, /* EEPROM Read - RW */
41 E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
42 E1000_FLA = 0x0001C, /* Flash Access - RW */
43 E1000_MDIC = 0x00020, /* MDI Control - RW */
44 E1000_SCTL = 0x00024, /* SerDes Control - RW */
45 E1000_FCAL = 0x00028, /* Flow Control Address Low - RW */
46 E1000_FCAH = 0x0002C, /* Flow Control Address High -RW */
831bd2e6 47 E1000_FEXTNVM4 = 0x00024, /* Future Extended NVM 4 - RW */
bc7f75fa
AK		 48 E1000_FEXTNVM = 0x00028, /* Future Extended NVM - RW */
49 E1000_FCT = 0x00030, /* Flow Control Type - RW */
50 E1000_VET = 0x00038, /* VLAN Ether Type - RW */
62bc813e 51 E1000_FEXTNVM3 = 0x0003C, /* Future Extended NVM 3 - RW */
bc7f75fa
AK		 52 E1000_ICR = 0x000C0, /* Interrupt Cause Read - R/clr */
53 E1000_ITR = 0x000C4, /* Interrupt Throttling Rate - RW */
54 E1000_ICS = 0x000C8, /* Interrupt Cause Set - WO */
55 E1000_IMS = 0x000D0, /* Interrupt Mask Set - RW */
56 E1000_IMC = 0x000D8, /* Interrupt Mask Clear - WO */
57 E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */
4662e82b 58 E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */
b67e1913 59 E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */
203e4151 60 E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */
ad68076e 61 E1000_RCTL = 0x00100, /* Rx Control - RW */
bc7f75fa 62 E1000_FCTTV = 0x00170, /* Flow Control Transmit Timer Value - RW */
ad68076e
BA		 63 E1000_TXCW = 0x00178, /* Tx Configuration Word - RW */
64 E1000_RXCW = 0x00180, /* Rx Configuration Word - RO */
65 E1000_TCTL = 0x00400, /* Tx Control - RW */
66 E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
67 E1000_TIPG = 0x00410, /* Tx Inter-packet gap -RW */
68 E1000_AIT = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
bc7f75fa
AK		 69 E1000_LEDCTL = 0x00E00, /* LED Control - RW */
70 E1000_EXTCNF_CTRL = 0x00F00, /* Extended Configuration Control */
71 E1000_EXTCNF_SIZE = 0x00F08, /* Extended Configuration Size */
72 E1000_PHY_CTRL = 0x00F10, /* PHY Control Register in CSR */
77996d1d 73#define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
bc7f75fa
AK		 74 E1000_PBA = 0x01000, /* Packet Buffer Allocation - RW */
75 E1000_PBS = 0x01008, /* Packet Buffer Size */
94fb848b 76 E1000_PBECCSTS = 0x0100C, /* Packet Buffer ECC Status - RW */
bc7f75fa
AK		 77 E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
78 E1000_EEWR = 0x0102C, /* EEPROM Write Register - RW */
79 E1000_FLOP = 0x0103C, /* FLASH Opcode Register */
6ea7ae1d 80 E1000_PBA_ECC = 0x01100, /* PBA ECC Register */
bc7f75fa
AK		 81 E1000_ERT = 0x02008, /* Early Rx Threshold - RW */
82 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
83 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
84 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
e921eb1a 85/* Convenience macros
bc7f75fa
AK		 86 *
87 * Note: "_n" is the queue number of the register to be written to.
88 *
89 * Example usage:
1e36052e 90 * E1000_RDBAL(current_rx_queue)
bc7f75fa 91 */
1e36052e
BA		 92 E1000_RDBAL_BASE = 0x02800, /* Rx Descriptor Base Address Low - RW */
93#define E1000_RDBAL(_n) (E1000_RDBAL_BASE + (_n << 8))
94 E1000_RDBAH_BASE = 0x02804, /* Rx Descriptor Base Address High - RW */
95#define E1000_RDBAH(_n) (E1000_RDBAH_BASE + (_n << 8))
96 E1000_RDLEN_BASE = 0x02808, /* Rx Descriptor Length - RW */
97#define E1000_RDLEN(_n) (E1000_RDLEN_BASE + (_n << 8))
98 E1000_RDH_BASE = 0x02810, /* Rx Descriptor Head - RW */
99#define E1000_RDH(_n) (E1000_RDH_BASE + (_n << 8))
100 E1000_RDT_BASE = 0x02818, /* Rx Descriptor Tail - RW */
101#define E1000_RDT(_n) (E1000_RDT_BASE + (_n << 8))
102 E1000_RDTR = 0x02820, /* Rx Delay Timer - RW */
103 E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
104#define E1000_RXDCTL(_n) (E1000_RXDCTL_BASE + (_n << 8))
105 E1000_RADV = 0x0282C, /* Rx Interrupt Absolute Delay Timer - RW */
106
bc7f75fa 107 E1000_KABGTXD = 0x03004, /* AFE Band Gap Transmit Ref Data */
1e36052e
BA		 108 E1000_TDBAL_BASE = 0x03800, /* Tx Descriptor Base Address Low - RW */
109#define E1000_TDBAL(_n) (E1000_TDBAL_BASE + (_n << 8))
110 E1000_TDBAH_BASE = 0x03804, /* Tx Descriptor Base Address High - RW */
111#define E1000_TDBAH(_n) (E1000_TDBAH_BASE + (_n << 8))
112 E1000_TDLEN_BASE = 0x03808, /* Tx Descriptor Length - RW */
113#define E1000_TDLEN(_n) (E1000_TDLEN_BASE + (_n << 8))
114 E1000_TDH_BASE = 0x03810, /* Tx Descriptor Head - RW */
115#define E1000_TDH(_n) (E1000_TDH_BASE + (_n << 8))
116 E1000_TDT_BASE = 0x03818, /* Tx Descriptor Tail - RW */
117#define E1000_TDT(_n) (E1000_TDT_BASE + (_n << 8))
ad68076e 118 E1000_TIDV = 0x03820, /* Tx Interrupt Delay Value - RW */
e9ec2c0f
JK		 119 E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
120#define E1000_TXDCTL(_n) (E1000_TXDCTL_BASE + (_n << 8))
ad68076e 121 E1000_TADV = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
e9ec2c0f
JK		 122 E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
123#define E1000_TARC(_n) (E1000_TARC_BASE + (_n << 8))
bc7f75fa
AK		 124 E1000_CRCERRS = 0x04000, /* CRC Error Count - R/clr */
125 E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
126 E1000_SYMERRS = 0x04008, /* Symbol Error Count - R/clr */
127 E1000_RXERRC = 0x0400C, /* Receive Error Count - R/clr */
128 E1000_MPC = 0x04010, /* Missed Packet Count - R/clr */
129 E1000_SCC = 0x04014, /* Single Collision Count - R/clr */
130 E1000_ECOL = 0x04018, /* Excessive Collision Count - R/clr */
131 E1000_MCC = 0x0401C, /* Multiple Collision Count - R/clr */
132 E1000_LATECOL = 0x04020, /* Late Collision Count - R/clr */
133 E1000_COLC = 0x04028, /* Collision Count - R/clr */
134 E1000_DC = 0x04030, /* Defer Count - R/clr */
ad68076e 135 E1000_TNCRS = 0x04034, /* Tx-No CRS - R/clr */
bc7f75fa
AK		 136 E1000_SEC = 0x04038, /* Sequence Error Count - R/clr */
137 E1000_CEXTERR = 0x0403C, /* Carrier Extension Error Count - R/clr */
138 E1000_RLEC = 0x04040, /* Receive Length Error Count - R/clr */
ad68076e
BA		 139 E1000_XONRXC = 0x04048, /* XON Rx Count - R/clr */
140 E1000_XONTXC = 0x0404C, /* XON Tx Count - R/clr */
141 E1000_XOFFRXC = 0x04050, /* XOFF Rx Count - R/clr */
142 E1000_XOFFTXC = 0x04054, /* XOFF Tx Count - R/clr */
143 E1000_FCRUC = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
144 E1000_PRC64 = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
145 E1000_PRC127 = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
146 E1000_PRC255 = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
147 E1000_PRC511 = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
148 E1000_PRC1023 = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
149 E1000_PRC1522 = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
150 E1000_GPRC = 0x04074, /* Good Packets Rx Count - R/clr */
151 E1000_BPRC = 0x04078, /* Broadcast Packets Rx Count - R/clr */
152 E1000_MPRC = 0x0407C, /* Multicast Packets Rx Count - R/clr */
153 E1000_GPTC = 0x04080, /* Good Packets Tx Count - R/clr */
154 E1000_GORCL = 0x04088, /* Good Octets Rx Count Low - R/clr */
155 E1000_GORCH = 0x0408C, /* Good Octets Rx Count High - R/clr */
156 E1000_GOTCL = 0x04090, /* Good Octets Tx Count Low - R/clr */
157 E1000_GOTCH = 0x04094, /* Good Octets Tx Count High - R/clr */
158 E1000_RNBC = 0x040A0, /* Rx No Buffers Count - R/clr */
159 E1000_RUC = 0x040A4, /* Rx Undersize Count - R/clr */
160 E1000_RFC = 0x040A8, /* Rx Fragment Count - R/clr */
161 E1000_ROC = 0x040AC, /* Rx Oversize Count - R/clr */
162 E1000_RJC = 0x040B0, /* Rx Jabber Count - R/clr */
163 E1000_MGTPRC = 0x040B4, /* Management Packets Rx Count - R/clr */
bc7f75fa 164 E1000_MGTPDC = 0x040B8, /* Management Packets Dropped Count - R/clr */
ad68076e
BA		 165 E1000_MGTPTC = 0x040BC, /* Management Packets Tx Count - R/clr */
166 E1000_TORL = 0x040C0, /* Total Octets Rx Low - R/clr */
167 E1000_TORH = 0x040C4, /* Total Octets Rx High - R/clr */
168 E1000_TOTL = 0x040C8, /* Total Octets Tx Low - R/clr */
169 E1000_TOTH = 0x040CC, /* Total Octets Tx High - R/clr */
170 E1000_TPR = 0x040D0, /* Total Packets Rx - R/clr */
171 E1000_TPT = 0x040D4, /* Total Packets Tx - R/clr */
172 E1000_PTC64 = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
173 E1000_PTC127 = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
174 E1000_PTC255 = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
175 E1000_PTC511 = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
176 E1000_PTC1023 = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
177 E1000_PTC1522 = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
178 E1000_MPTC = 0x040F0, /* Multicast Packets Tx Count - R/clr */
179 E1000_BPTC = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
180 E1000_TSCTC = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
181 E1000_TSCTFC = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
bc7f75fa
AK		 182 E1000_IAC = 0x04100, /* Interrupt Assertion Count */
183 E1000_ICRXPTC = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
184 E1000_ICRXATC = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
185 E1000_ICTXPTC = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
186 E1000_ICTXATC = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
187 E1000_ICTXQEC = 0x04118, /* Irq Cause Tx Queue Empty Count */
188 E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
189 E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
190 E1000_ICRXOC = 0x04124, /* Irq Cause Receiver Overrun Count */
1241f29f
BA		 191 E1000_PCS_LCTL = 0x04208, /* PCS Link Control - RW */
192 E1000_PCS_LSTAT = 0x0420C, /* PCS Link Status - RO */
193 E1000_PCS_ANADV = 0x04218, /* AN advertisement - RW */
194 E1000_PCS_LPAB = 0x0421C, /* Link Partner Ability - RW */
ad68076e 195 E1000_RXCSUM = 0x05000, /* Rx Checksum Control - RW */
489815ce 196 E1000_RFCTL = 0x05008, /* Receive Filter Control */
bc7f75fa 197 E1000_MTA = 0x05200, /* Multicast Table Array - RW Array */
a4f58f54
BA		 198 E1000_RAL_BASE = 0x05400, /* Receive Address Low - RW */
199#define E1000_RAL(_n) (E1000_RAL_BASE + ((_n) * 8))
200#define E1000_RA (E1000_RAL(0))
201 E1000_RAH_BASE = 0x05404, /* Receive Address High - RW */
202#define E1000_RAH(_n) (E1000_RAH_BASE + ((_n) * 8))
69e1e019
BA		 203 E1000_SHRAL_BASE = 0x05438, /* Shared Receive Address Low - RW */
204#define E1000_SHRAL(_n) (E1000_SHRAL_BASE + ((_n) * 8))
205 E1000_SHRAH_BASE = 0x0543C, /* Shared Receive Address High - RW */
206#define E1000_SHRAH(_n) (E1000_SHRAH_BASE + ((_n) * 8))
bc7f75fa
AK		 207 E1000_VFTA = 0x05600, /* VLAN Filter Table Array - RW Array */
208 E1000_WUC = 0x05800, /* Wakeup Control - RW */
209 E1000_WUFC = 0x05808, /* Wakeup Filter Control - RW */
210 E1000_WUS = 0x05810, /* Wakeup Status - RO */
70495a50 211 E1000_MRQC = 0x05818, /* Multiple Receive Control - RW */
bc7f75fa
AK		 212 E1000_MANC = 0x05820, /* Management Control - RW */
213 E1000_FFLT = 0x05F00, /* Flexible Filter Length Table - RW Array */
1b41db37 214 E1000_CRC_OFFSET = 0x05F50, /* CRC Offset register */
bc7f75fa
AK		 215 E1000_HOST_IF = 0x08800, /* Host Interface */
216
217 E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
218 E1000_MANC2H = 0x05860, /* Management Control To Host - RW */
cd791618
BA		 219 E1000_MDEF_BASE = 0x05890, /* Management Decision Filters */
220#define E1000_MDEF(_n) (E1000_MDEF_BASE + ((_n) * 4))
bc7f75fa
AK		 221 E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
222 E1000_GCR = 0x05B00, /* PCI-Ex Control */
78272bba 223 E1000_GCR2 = 0x05B64, /* PCI-Ex Control #2 */
bc7f75fa
AK		 224 E1000_FACTPS = 0x05B30, /* Function Active and Power State to MNG */
225 E1000_SWSM = 0x05B50, /* SW Semaphore */
226 E1000_FWSM = 0x05B54, /* FW Semaphore */
23a2d1b2 227 E1000_SWSM2 = 0x05B58, /* Driver-only SW semaphore */
70495a50
BA		 228 E1000_RETA_BASE = 0x05C00, /* Redirection Table - RW */
229#define E1000_RETA(_n) (E1000_RETA_BASE + ((_n) * 4))
230 E1000_RSSRK_BASE = 0x05C80, /* RSS Random Key - RW */
231#define E1000_RSSRK(_n) (E1000_RSSRK_BASE + ((_n) * 4))
d3738bb8 232 E1000_FFLT_DBG = 0x05F04, /* Debug Register */
489815ce 233 E1000_HICR = 0x08F00, /* Host Interface Control */
b67e1913
BA		 234 E1000_SYSTIML = 0x0B600, /* System time register Low - RO */
235 E1000_SYSTIMH = 0x0B604, /* System time register High - RO */
236 E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */
237 E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */
238 E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */
239 E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */
240 E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */
241 E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */
242 E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */
d89777bf
BA		 243 E1000_RXMTRL = 0x0B634, /* Timesync Rx EtherType and Msg Type - RW */
244 E1000_RXUDP = 0x0B638, /* Timesync Rx UDP Port - RW */
bc7f75fa
AK		 245};
246
5eb6f3c7 247#define E1000_MAX_PHY_ADDR 4
bc7f75fa
AK		 248
249/* IGP01E1000 Specific Registers */
250#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
251#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */
252#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */
253#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
254#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */
255#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */
97ac8cae
BA		 256#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
257#define IGP_PAGE_SHIFT 5
258#define PHY_REG_MASK 0x1F
259
260#define BM_WUC_PAGE 800
261#define BM_WUC_ADDRESS_OPCODE 0x11
262#define BM_WUC_DATA_OPCODE 0x12
263#define BM_WUC_ENABLE_PAGE 769
264#define BM_WUC_ENABLE_REG 17
265#define BM_WUC_ENABLE_BIT (1 << 2)
266#define BM_WUC_HOST_WU_BIT (1 << 4)
2b6b168d 267#define BM_WUC_ME_WU_BIT (1 << 5)
97ac8cae 268
bc7f75fa
AK		 269#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
270#define IGP01E1000_PHY_POLARITY_MASK 0x0078
271
272#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
273#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
274
275#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
276
277#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
278#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */
279#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */
280
281#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
282
283#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
cbe7a81a 284#define IGP01E1000_PSSR_MDIX 0x0800
bc7f75fa
AK		 285#define IGP01E1000_PSSR_SPEED_MASK 0xC000
286#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
287
288#define IGP02E1000_PHY_CHANNEL_NUM 4
289#define IGP02E1000_PHY_AGC_A 0x11B1
290#define IGP02E1000_PHY_AGC_B 0x12B1
291#define IGP02E1000_PHY_AGC_C 0x14B1
292#define IGP02E1000_PHY_AGC_D 0x18B1
293
294#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
295#define IGP02E1000_AGC_LENGTH_MASK 0x7F
296#define IGP02E1000_AGC_RANGE 15
297
298/* manage.c */
299#define E1000_VFTA_ENTRY_SHIFT 5
300#define E1000_VFTA_ENTRY_MASK 0x7F
301#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
302
303#define E1000_HICR_EN 0x01 /* Enable bit - RO */
ad68076e
BA		 304/* Driver sets this bit when done to put command in RAM */
305#define E1000_HICR_C 0x02
bc7f75fa
AK		 306#define E1000_HICR_FW_RESET_ENABLE 0x40
307#define E1000_HICR_FW_RESET 0x80
308
309#define E1000_FWSM_MODE_MASK 0xE
310#define E1000_FWSM_MODE_SHIFT 1
311
312#define E1000_MNG_IAMT_MODE 0x3
313#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10
314#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0
315#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10
316#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
317#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
318#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
319
320/* nvm.c */
321#define E1000_STM_OPCODE 0xDB00
322
323#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000
324#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16
325#define E1000_KMRNCTRLSTA_REN 0x00200000
d3738bb8 326#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */
bc7f75fa 327#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
07818950
BA		 328#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
329#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
d9b24135 330#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
bc7f75fa 331#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
7d3cabbc 332#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7
ff847ac2 333#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002
96f2bd13 334#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */
bc7f75fa
AK		 335
336#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
337#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
338#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
339#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
340
341/* IFE PHY Extended Status Control */
342#define IFE_PESC_POLARITY_REVERSED 0x0100
343
344/* IFE PHY Special Control */
345#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
346#define IFE_PSC_FORCE_POLARITY 0x0020
347
348/* IFE PHY Special Control and LED Control */
349#define IFE_PSCL_PROBE_MODE 0x0020
350#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
351#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
352
353/* IFE PHY MDIX Control */
354#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
355#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
356#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
357
358#define E1000_CABLE_LENGTH_UNDEFINED 0xFF
359
360#define E1000_DEV_ID_82571EB_COPPER 0x105E
361#define E1000_DEV_ID_82571EB_FIBER 0x105F
362#define E1000_DEV_ID_82571EB_SERDES 0x1060
363#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9 364#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa
AK		 365#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
366#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9
AK		 367#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
368#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa
AK		 369#define E1000_DEV_ID_82572EI_COPPER 0x107D
370#define E1000_DEV_ID_82572EI_FIBER 0x107E
371#define E1000_DEV_ID_82572EI_SERDES 0x107F
372#define E1000_DEV_ID_82572EI 0x10B9
373#define E1000_DEV_ID_82573E 0x108B
374#define E1000_DEV_ID_82573E_IAMT 0x108C
375#define E1000_DEV_ID_82573L 0x109A
4662e82b 376#define E1000_DEV_ID_82574L 0x10D3
bef28b11 377#define E1000_DEV_ID_82574LA 0x10F6
a9bb6290 378#define E1000_DEV_ID_82583V 0x150C
bc7f75fa
AK		 379#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
380#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
381#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
382#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
9e135a2e 383#define E1000_DEV_ID_ICH8_82567V_3 0x1501
bc7f75fa
AK		 384#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
385#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
386#define E1000_DEV_ID_ICH8_IGP_C 0x104B
387#define E1000_DEV_ID_ICH8_IFE 0x104C
388#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
389#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
390#define E1000_DEV_ID_ICH8_IGP_M 0x104D
391#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6 392#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae
BA		 393#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
394#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
395#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa
AK		 396#define E1000_DEV_ID_ICH9_IGP_C 0x294C
397#define E1000_DEV_ID_ICH9_IFE 0x10C0
398#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
399#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae
BA		 400#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
401#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
402#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56
BA		 403#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
404#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
10df0b91 405#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
a4f58f54
BA		 406#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
407#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
408#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
409#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
d3738bb8
BA		 410#define E1000_DEV_ID_PCH2_LV_LM 0x1502
411#define E1000_DEV_ID_PCH2_LV_V 0x1503
2fbe4526
BA		 412#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
413#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
16e310ae
BA		 414#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
415#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
bc7f75fa 416
a9bb6290 417#define E1000_REVISION_4 4
4662e82b 418
a9bb6290 419#define E1000_FUNC_1 1
bc7f75fa 420
a9bb6290
BA		 421#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
422#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
608f8a0d 423
bc7f75fa
AK		 424enum e1000_mac_type {
425 e1000_82571,
426 e1000_82572,
427 e1000_82573,
4662e82b 428 e1000_82574,
8c81c9c3 429 e1000_82583,
bc7f75fa
AK		 430 e1000_80003es2lan,
431 e1000_ich8lan,
432 e1000_ich9lan,
f4187b56 433 e1000_ich10lan,
a4f58f54 434 e1000_pchlan,
d3738bb8 435 e1000_pch2lan,
2fbe4526 436 e1000_pch_lpt,
bc7f75fa
AK		 437};
438
439enum e1000_media_type {
440 e1000_media_type_unknown = 0,
441 e1000_media_type_copper = 1,
442 e1000_media_type_fiber = 2,
443 e1000_media_type_internal_serdes = 3,
444 e1000_num_media_types
445};
446
447enum e1000_nvm_type {
448 e1000_nvm_unknown = 0,
449 e1000_nvm_none,
450 e1000_nvm_eeprom_spi,
451 e1000_nvm_flash_hw,
452 e1000_nvm_flash_sw
453};
454
455enum e1000_nvm_override {
456 e1000_nvm_override_none = 0,
457 e1000_nvm_override_spi_small,
458 e1000_nvm_override_spi_large
459};
460
461enum e1000_phy_type {
462 e1000_phy_unknown = 0,
463 e1000_phy_none,
464 e1000_phy_m88,
465 e1000_phy_igp,
466 e1000_phy_igp_2,
467 e1000_phy_gg82563,
468 e1000_phy_igp_3,
469 e1000_phy_ife,
97ac8cae 470 e1000_phy_bm,
a4f58f54
BA		 471 e1000_phy_82578,
472 e1000_phy_82577,
d3738bb8 473 e1000_phy_82579,
2fbe4526 474 e1000_phy_i217,
bc7f75fa
AK		 475};
476
477enum e1000_bus_width {
478 e1000_bus_width_unknown = 0,
479 e1000_bus_width_pcie_x1,
480 e1000_bus_width_pcie_x2,
481 e1000_bus_width_pcie_x4 = 4,
482 e1000_bus_width_32,
483 e1000_bus_width_64,
484 e1000_bus_width_reserved
485};
486
487enum e1000_1000t_rx_status {
488 e1000_1000t_rx_status_not_ok = 0,
489 e1000_1000t_rx_status_ok,
490 e1000_1000t_rx_status_undefined = 0xFF
491};
492
493enum e1000_rev_polarity{
494 e1000_rev_polarity_normal = 0,
495 e1000_rev_polarity_reversed,
496 e1000_rev_polarity_undefined = 0xFF
497};
498
5c48ef3e 499enum e1000_fc_mode {
bc7f75fa
AK		 500 e1000_fc_none = 0,
501 e1000_fc_rx_pause,
502 e1000_fc_tx_pause,
503 e1000_fc_full,
504 e1000_fc_default = 0xFF
505};
506
507enum e1000_ms_type {
508 e1000_ms_hw_default = 0,
509 e1000_ms_force_master,
510 e1000_ms_force_slave,
511 e1000_ms_auto
512};
513
514enum e1000_smart_speed {
515 e1000_smart_speed_default = 0,
516 e1000_smart_speed_on,
517 e1000_smart_speed_off
518};
519
c9523379 520enum e1000_serdes_link_state {
521 e1000_serdes_link_down = 0,
522 e1000_serdes_link_autoneg_progress,
523 e1000_serdes_link_autoneg_complete,
524 e1000_serdes_link_forced_up
525};
526
bc7f75fa
AK		 527/* Receive Descriptor - Extended */
528union e1000_rx_desc_extended {
529 struct {
a39fe742
AV		 530 __le64 buffer_addr;
531 __le64 reserved;
bc7f75fa
AK		 532 } read;
533 struct {
534 struct {
a39fe742 535 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 536 union {
a39fe742 537 __le32 rss; /* RSS Hash */
bc7f75fa 538 struct {
a39fe742
AV		 539 __le16 ip_id; /* IP id */
540 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 541 } csum_ip;
542 } hi_dword;
543 } lower;
544 struct {
a39fe742
AV		 545 __le32 status_error; /* ext status/error */
546 __le16 length;
547 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 548 } upper;
549 } wb; /* writeback */
550};
551
552#define MAX_PS_BUFFERS 4
553/* Receive Descriptor - Packet Split */
554union e1000_rx_desc_packet_split {
555 struct {
556 /* one buffer for protocol header(s), three data buffers */
a39fe742 557 __le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa
AK		 558 } read;
559 struct {
560 struct {
a39fe742 561 __le32 mrq; /* Multiple Rx Queues */
bc7f75fa 562 union {
a39fe742 563 __le32 rss; /* RSS Hash */
bc7f75fa 564 struct {
a39fe742
AV		 565 __le16 ip_id; /* IP id */
566 __le16 csum; /* Packet Checksum */
bc7f75fa
AK		 567 } csum_ip;
568 } hi_dword;
569 } lower;
570 struct {
a39fe742
AV		 571 __le32 status_error; /* ext status/error */
572 __le16 length0; /* length of buffer 0 */
573 __le16 vlan; /* VLAN tag */
bc7f75fa
AK		 574 } middle;
575 struct {
a39fe742
AV		 576 __le16 header_status;
577 __le16 length[3]; /* length of buffers 1-3 */
bc7f75fa 578 } upper;
a39fe742 579 __le64 reserved;
bc7f75fa
AK		 580 } wb; /* writeback */
581};
582
583/* Transmit Descriptor */
584struct e1000_tx_desc {
a39fe742 585 __le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa 586 union {
a39fe742 587 __le32 data;
bc7f75fa 588 struct {
a39fe742 589 __le16 length; /* Data buffer length */
bc7f75fa
AK		 590 u8 cso; /* Checksum offset */
591 u8 cmd; /* Descriptor control */
592 } flags;
593 } lower;
594 union {
a39fe742 595 __le32 data;
bc7f75fa
AK		 596 struct {
597 u8 status; /* Descriptor status */
598 u8 css; /* Checksum start */
a39fe742 599 __le16 special;
bc7f75fa
AK		 600 } fields;
601 } upper;
602};
603
604/* Offload Context Descriptor */
605struct e1000_context_desc {
606 union {
a39fe742 607 __le32 ip_config;
bc7f75fa
AK		 608 struct {
609 u8 ipcss; /* IP checksum start */
610 u8 ipcso; /* IP checksum offset */
a39fe742 611 __le16 ipcse; /* IP checksum end */
bc7f75fa
AK		 612 } ip_fields;
613 } lower_setup;
614 union {
a39fe742 615 __le32 tcp_config;
bc7f75fa
AK		 616 struct {
617 u8 tucss; /* TCP checksum start */
618 u8 tucso; /* TCP checksum offset */
a39fe742 619 __le16 tucse; /* TCP checksum end */
bc7f75fa
AK		 620 } tcp_fields;
621 } upper_setup;
a39fe742 622 __le32 cmd_and_length;
bc7f75fa 623 union {
a39fe742 624 __le32 data;
bc7f75fa
AK		 625 struct {
626 u8 status; /* Descriptor status */
627 u8 hdr_len; /* Header length */
a39fe742 628 __le16 mss; /* Maximum segment size */
bc7f75fa
AK		 629 } fields;
630 } tcp_seg_setup;
631};
632
633/* Offload data descriptor */
634struct e1000_data_desc {
a39fe742 635 __le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa 636 union {
a39fe742 637 __le32 data;
bc7f75fa 638 struct {
a39fe742 639 __le16 length; /* Data buffer length */
bc7f75fa
AK		 640 u8 typ_len_ext;
641 u8 cmd;
642 } flags;
643 } lower;
644 union {
a39fe742 645 __le32 data;
bc7f75fa
AK		 646 struct {
647 u8 status; /* Descriptor status */
648 u8 popts; /* Packet Options */
a9bb6290 649 __le16 special;
bc7f75fa
AK		 650 } fields;
651 } upper;
652};
653
654/* Statistics counters collected by the MAC */
655struct e1000_hw_stats {
656 u64 crcerrs;
657 u64 algnerrc;
658 u64 symerrs;
659 u64 rxerrc;
660 u64 mpc;
661 u64 scc;
662 u64 ecol;
663 u64 mcc;
664 u64 latecol;
665 u64 colc;
666 u64 dc;
667 u64 tncrs;
668 u64 sec;
669 u64 cexterr;
670 u64 rlec;
671 u64 xonrxc;
672 u64 xontxc;
673 u64 xoffrxc;
674 u64 xofftxc;
675 u64 fcruc;
676 u64 prc64;
677 u64 prc127;
678 u64 prc255;
679 u64 prc511;
680 u64 prc1023;
681 u64 prc1522;
682 u64 gprc;
683 u64 bprc;
684 u64 mprc;
685 u64 gptc;
7c25769f
BA		 686 u64 gorc;
687 u64 gotc;
bc7f75fa
AK		 688 u64 rnbc;
689 u64 ruc;
690 u64 rfc;
691 u64 roc;
692 u64 rjc;
693 u64 mgprc;
694 u64 mgpdc;
695 u64 mgptc;
7c25769f
BA		 696 u64 tor;
697 u64 tot;
bc7f75fa
AK		 698 u64 tpr;
699 u64 tpt;
700 u64 ptc64;
701 u64 ptc127;
702 u64 ptc255;
703 u64 ptc511;
704 u64 ptc1023;
705 u64 ptc1522;
706 u64 mptc;
707 u64 bptc;
708 u64 tsctc;
709 u64 tsctfc;
710 u64 iac;
711 u64 icrxptc;
712 u64 icrxatc;
713 u64 ictxptc;
714 u64 ictxatc;
715 u64 ictxqec;
716 u64 ictxqmtc;
717 u64 icrxdmtc;
718 u64 icrxoc;
719};
720
721struct e1000_phy_stats {
722 u32 idle_errors;
723 u32 receive_errors;
724};
725
726struct e1000_host_mng_dhcp_cookie {
727 u32 signature;
728 u8 status;
729 u8 reserved0;
730 u16 vlan_id;
731 u32 reserved1;
732 u16 reserved2;
733 u8 reserved3;
734 u8 checksum;
735};
736
737/* Host Interface "Rev 1" */
738struct e1000_host_command_header {
739 u8 command_id;
740 u8 command_length;
741 u8 command_options;
742 u8 checksum;
743};
744
a9bb6290 745#define E1000_HI_MAX_DATA_LENGTH 252
bc7f75fa
AK		 746struct e1000_host_command_info {
747 struct e1000_host_command_header command_header;
748 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
749};
750
751/* Host Interface "Rev 2" */
752struct e1000_host_mng_command_header {
753 u8 command_id;
754 u8 checksum;
755 u16 reserved1;
756 u16 reserved2;
757 u16 command_length;
758};
759
a9bb6290 760#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
bc7f75fa
AK		 761struct e1000_host_mng_command_info {
762 struct e1000_host_mng_command_header command_header;
763 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
764};
765
bdfe2da6
BA		 766#include "mac.h"
767
a9bb6290 768/* Function pointers for the MAC. */
bc7f75fa 769struct e1000_mac_operations {
a4f58f54 770 s32 (*id_led_init)(struct e1000_hw *);
dbf80dcb 771 s32 (*blink_led)(struct e1000_hw *);
4662e82b 772 bool (*check_mng_mode)(struct e1000_hw *);
bc7f75fa
AK		 773 s32 (*check_for_link)(struct e1000_hw *);
774 s32 (*cleanup_led)(struct e1000_hw *);
775 void (*clear_hw_cntrs)(struct e1000_hw *);
caaddaf8 776 void (*clear_vfta)(struct e1000_hw *);
bc7f75fa 777 s32 (*get_bus_info)(struct e1000_hw *);
f4d2dd4c 778 void (*set_lan_id)(struct e1000_hw *);
bc7f75fa
AK		 779 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
780 s32 (*led_on)(struct e1000_hw *);
781 s32 (*led_off)(struct e1000_hw *);
ab8932f3 782 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
bc7f75fa
AK		 783 s32 (*reset_hw)(struct e1000_hw *);
784 s32 (*init_hw)(struct e1000_hw *);
785 s32 (*setup_link)(struct e1000_hw *);
786 s32 (*setup_physical_interface)(struct e1000_hw *);
a4f58f54 787 s32 (*setup_led)(struct e1000_hw *);
caaddaf8 788 void (*write_vfta)(struct e1000_hw *, u32, u32);
57cde763 789 void (*config_collision_dist)(struct e1000_hw *);
69e1e019 790 void (*rar_set)(struct e1000_hw *, u8 *, u32);
608f8a0d 791 s32 (*read_mac_addr)(struct e1000_hw *);
bc7f75fa
AK		 792};
793
e921eb1a 794/* When to use various PHY register access functions:
2b6b168d
BA		 795 *
796 * Func Caller
797 * Function Does Does When to use
798 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
799 * X_reg L,P,A n/a for simple PHY reg accesses
800 * X_reg_locked P,A L for multiple accesses of different regs
801 * on different pages
802 * X_reg_page A L,P for multiple accesses of different regs
803 * on the same page
804 *
805 * Where X=[read|write], L=locking, P=sets page, A=register access
806 *
807 */
bc7f75fa 808struct e1000_phy_operations {
94d8186a
BA		 809 s32 (*acquire)(struct e1000_hw *);
810 s32 (*cfg_on_link_up)(struct e1000_hw *);
a4f58f54 811 s32 (*check_polarity)(struct e1000_hw *);
bc7f75fa 812 s32 (*check_reset_block)(struct e1000_hw *);
94d8186a 813 s32 (*commit)(struct e1000_hw *);
bc7f75fa
AK		 814 s32 (*force_speed_duplex)(struct e1000_hw *);
815 s32 (*get_cfg_done)(struct e1000_hw *hw);
816 s32 (*get_cable_length)(struct e1000_hw *);
94d8186a 817 s32 (*get_info)(struct e1000_hw *);
2b6b168d 818 s32 (*set_page)(struct e1000_hw *, u16);
94d8186a
BA		 819 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
820 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
2b6b168d 821 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
94d8186a
BA		 822 void (*release)(struct e1000_hw *);
823 s32 (*reset)(struct e1000_hw *);
bc7f75fa
AK		 824 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
825 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
94d8186a
BA		 826 s32 (*write_reg)(struct e1000_hw *, u32, u16);
827 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
2b6b168d 828 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
17f208de
BA		 829 void (*power_up)(struct e1000_hw *);
830 void (*power_down)(struct e1000_hw *);
bc7f75fa
AK		 831};
832
833/* Function pointers for the NVM. */
834struct e1000_nvm_operations {
94d8186a
BA		 835 s32 (*acquire)(struct e1000_hw *);
836 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
837 void (*release)(struct e1000_hw *);
e85e3639 838 void (*reload)(struct e1000_hw *);
94d8186a 839 s32 (*update)(struct e1000_hw *);
bc7f75fa 840 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
94d8186a
BA		 841 s32 (*validate)(struct e1000_hw *);
842 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
bc7f75fa
AK		 843};
844
845struct e1000_mac_info {
846 struct e1000_mac_operations ops;
d8d5f8ae
BA		 847 u8 addr[ETH_ALEN];
848 u8 perm_addr[ETH_ALEN];
bc7f75fa
AK		 849
850 enum e1000_mac_type type;
bc7f75fa
AK		 851
852 u32 collision_delta;
853 u32 ledctl_default;
854 u32 ledctl_mode1;
855 u32 ledctl_mode2;
bc7f75fa 856 u32 mc_filter_type;
bc7f75fa
AK		 857 u32 tx_packet_delta;
858 u32 txcw;
859
860 u16 current_ifs_val;
861 u16 ifs_max_val;
862 u16 ifs_min_val;
863 u16 ifs_ratio;
864 u16 ifs_step_size;
865 u16 mta_reg_count;
ab8932f3
BA		 866
867 /* Maximum size of the MTA register table in all supported adapters */
868 #define MAX_MTA_REG 128
869 u32 mta_shadow[MAX_MTA_REG];
bc7f75fa 870 u16 rar_entry_count;
bc7f75fa
AK		 871
872 u8 forced_speed_duplex;
873
f464ba87 874 bool adaptive_ifs;
a65a4a0d 875 bool has_fwsm;
bc7f75fa
AK		 876 bool arc_subsystem_valid;
877 bool autoneg;
878 bool autoneg_failed;
879 bool get_link_status;
880 bool in_ifs_mode;
881 bool serdes_has_link;
882 bool tx_pkt_filtering;
c9523379 883 enum e1000_serdes_link_state serdes_link_state;
bc7f75fa
AK		 884};
885
886struct e1000_phy_info {
887 struct e1000_phy_operations ops;
888
889 enum e1000_phy_type type;
890
891 enum e1000_1000t_rx_status local_rx;
892 enum e1000_1000t_rx_status remote_rx;
893 enum e1000_ms_type ms_type;
894 enum e1000_ms_type original_ms_type;
895 enum e1000_rev_polarity cable_polarity;
896 enum e1000_smart_speed smart_speed;
897
898 u32 addr;
899 u32 id;
900 u32 reset_delay_us; /* in usec */
901 u32 revision;
902
318a94d6
JK		 903 enum e1000_media_type media_type;
904
bc7f75fa
AK		 905 u16 autoneg_advertised;
906 u16 autoneg_mask;
907 u16 cable_length;
908 u16 max_cable_length;
909 u16 min_cable_length;
910
911 u8 mdix;
912
913 bool disable_polarity_correction;
914 bool is_mdix;
915 bool polarity_correction;
916 bool speed_downgraded;
318a94d6 917 bool autoneg_wait_to_complete;
bc7f75fa
AK		 918};
919
920struct e1000_nvm_info {
921 struct e1000_nvm_operations ops;
922
923 enum e1000_nvm_type type;
924 enum e1000_nvm_override override;
925
926 u32 flash_bank_size;
927 u32 flash_base_addr;
928
929 u16 word_size;
930 u16 delay_usec;
931 u16 address_bits;
932 u16 opcode_bits;
933 u16 page_size;
934};
935
936struct e1000_bus_info {
937 enum e1000_bus_width width;
938
939 u16 func;
940};
941
318a94d6
JK		 942struct e1000_fc_info {
943 u32 high_water; /* Flow control high-water mark */
944 u32 low_water; /* Flow control low-water mark */
945 u16 pause_time; /* Flow control pause timer */
a305595b 946 u16 refresh_time; /* Flow control refresh timer */
318a94d6
JK		 947 bool send_xon; /* Flow control send XON */
948 bool strict_ieee; /* Strict IEEE mode */
5c48ef3e
BA		 949 enum e1000_fc_mode current_mode; /* FC mode in effect */
950 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6
JK		 951};
952
bc7f75fa
AK		 953struct e1000_dev_spec_82571 {
954 bool laa_is_present;
23a2d1b2 955 u32 smb_counter;
bc7f75fa
AK		 956};
957
3421eecd
BA		 958struct e1000_dev_spec_80003es2lan {
959 bool mdic_wa_enable;
960};
961
bc7f75fa
AK		 962struct e1000_shadow_ram {
963 u16 value;
964 bool modified;
965};
966
967#define E1000_ICH8_SHADOW_RAM_WORDS 2048
968
969struct e1000_dev_spec_ich8lan {
970 bool kmrn_lock_loss_workaround_enabled;
971 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1d5846b9 972 bool nvm_k1_enabled;
e52997f9 973 bool eee_disable;
2fbe4526 974 u16 eee_lp_ability;
bc7f75fa
AK		 975};
976
977struct e1000_hw {
978 struct e1000_adapter *adapter;
979
c5083cf6
BA		 980 void __iomem *hw_addr;
981 void __iomem *flash_address;
bc7f75fa
AK		 982
983 struct e1000_mac_info mac;
318a94d6 984 struct e1000_fc_info fc;
bc7f75fa
AK		 985 struct e1000_phy_info phy;
986 struct e1000_nvm_info nvm;
987 struct e1000_bus_info bus;
988 struct e1000_host_mng_dhcp_cookie mng_cookie;
989
990 union {
991 struct e1000_dev_spec_82571 e82571;
3421eecd 992 struct e1000_dev_spec_80003es2lan e80003es2lan;
bc7f75fa
AK		 993 struct e1000_dev_spec_ich8lan ich8lan;
994 } dev_spec;
bc7f75fa
AK		 995};
996
f25701df 997#include "82571.h"
21b5a6f8 998#include "80003es2lan.h"
1b41db37 999#include "ich8lan.h"
f25701df 1000
bc7f75fa 1001#endif
Linux kernel - Deliverables
This page took 0.636165 seconds and 5 git commands to generate.