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e1000e: Workaround for dropped packets in Gig/100 speeds on 82579
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
e921eb1a 22/* 82562G 10/100 Network Connection
bc7f75fa
AK		 23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
97ac8cae
BA		 34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
1605927f 36 * 82567V Gigabit Network Connection
97ac8cae
BA		 37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
2f15f9d6 42 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
d3738bb8
BA		 47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
3b70d4f8
DE		 49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
bc7f75fa
AK		 57 */
58
bc7f75fa
AK		 59#include "e1000.h"
60
bc7f75fa
AK		 61/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62/* Offset 04h HSFSTS */
63union ich8_hws_flash_status {
64 struct ich8_hsfsts {
362e20ca
BA		 65 u16 flcdone:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr:1; /* bit 1 Flash Cycle Error */
67 u16 dael:1; /* bit 2 Direct Access error Log */
68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1:2; /* bit 13:6 Reserved */
71 u16 reserved2:6; /* bit 13:6 Reserved */
72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
bc7f75fa
AK		 74 } hsf_status;
75 u16 regval;
76};
77
78/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79/* Offset 06h FLCTL */
80union ich8_hws_flash_ctrl {
81 struct ich8_hsflctl {
362e20ca
BA		 82 u16 flcgo:1; /* 0 Flash Cycle Go */
83 u16 flcycle:2; /* 2:1 Flash Cycle */
84 u16 reserved:5; /* 7:3 Reserved */
85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn:6; /* 15:10 Reserved */
bc7f75fa
AK		 87 } hsf_ctrl;
88 u16 regval;
89};
90
91/* ICH Flash Region Access Permissions */
92union ich8_hws_flash_regacc {
93 struct ich8_flracc {
362e20ca
BA		 94 u32 grra:8; /* 0:7 GbE region Read Access */
95 u32 grwa:8; /* 8:15 GbE region Write Access */
96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
bc7f75fa
AK		 98 } hsf_flregacc;
99 u16 regval;
100};
101
4a770358
BA		 102/* ICH Flash Protected Region */
103union ich8_flash_protected_range {
104 struct ich8_pr {
e80bd1d1
BA		 105 u32 base:13; /* 0:12 Protected Range Base */
106 u32 reserved1:2; /* 13:14 Reserved */
107 u32 rpe:1; /* 15 Read Protection Enable */
108 u32 limit:13; /* 16:28 Protected Range Limit */
109 u32 reserved2:2; /* 29:30 Reserved */
110 u32 wpe:1; /* 31 Write Protection Enable */
4a770358
BA		 111 } range;
112 u32 regval;
113};
114
bc7f75fa
AK		 115static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 117static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
f4187b56
BA		 120static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 *data);
bc7f75fa
AK		 122static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data);
124static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
bc7f75fa 126static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 127static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
128static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
129static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
130static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
131static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
132static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
133static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
134static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 135static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 136static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 137static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1f96012d 138static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 139static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 140static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
141static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
69e1e019 142static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
2fbe4526 143static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
831bd2e6 144static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 145static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
74f350ee 146static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
ea8179a7 147static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
74f350ee 148static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
bc7f75fa
AK		 149
150static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
151{
152 return readw(hw->flash_address + reg);
153}
154
155static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
156{
157 return readl(hw->flash_address + reg);
158}
159
160static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
161{
162 writew(val, hw->flash_address + reg);
163}
164
165static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
166{
167 writel(val, hw->flash_address + reg);
168}
169
170#define er16flash(reg) __er16flash(hw, (reg))
171#define er32flash(reg) __er32flash(hw, (reg))
0e15df49
BA		 172#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
173#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
bc7f75fa 174
cb17aab9
BA		 175/**
176 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
177 * @hw: pointer to the HW structure
178 *
179 * Test access to the PHY registers by reading the PHY ID registers. If
180 * the PHY ID is already known (e.g. resume path) compare it with known ID,
181 * otherwise assume the read PHY ID is correct if it is valid.
182 *
183 * Assumes the sw/fw/hw semaphore is already acquired.
184 **/
185static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
99730e4c 186{
a52359b5
BA		 187 u16 phy_reg = 0;
188 u32 phy_id = 0;
189 s32 ret_val;
190 u16 retry_count;
16b095a4 191 u32 mac_reg = 0;
a52359b5
BA		 192
193 for (retry_count = 0; retry_count < 2; retry_count++) {
c2ade1a4 194 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
a52359b5
BA		 195 if (ret_val || (phy_reg == 0xFFFF))
196 continue;
197 phy_id = (u32)(phy_reg << 16);
198
c2ade1a4 199 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
a52359b5
BA		 200 if (ret_val || (phy_reg == 0xFFFF)) {
201 phy_id = 0;
202 continue;
203 }
204 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
205 break;
206 }
cb17aab9
BA		 207
208 if (hw->phy.id) {
209 if (hw->phy.id == phy_id)
16b095a4 210 goto out;
a52359b5
BA		 211 } else if (phy_id) {
212 hw->phy.id = phy_id;
213 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
16b095a4 214 goto out;
cb17aab9
BA		 215 }
216
e921eb1a 217 /* In case the PHY needs to be in mdio slow mode,
a52359b5
BA		 218 * set slow mode and try to get the PHY id again.
219 */
220 hw->phy.ops.release(hw);
221 ret_val = e1000_set_mdio_slow_mode_hv(hw);
222 if (!ret_val)
223 ret_val = e1000e_get_phy_id(hw);
224 hw->phy.ops.acquire(hw);
225
16b095a4
BA		 226 if (ret_val)
227 return false;
228out:
229 if (hw->mac.type == e1000_pch_lpt) {
230 /* Unforce SMBus mode in PHY */
231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
232 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
234
235 /* Unforce SMBus mode in MAC */
236 mac_reg = er32(CTRL_EXT);
237 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
238 ew32(CTRL_EXT, mac_reg);
239 }
240
241 return true;
cb17aab9
BA		 242}
243
74f350ee
DE		 244/**
245 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
246 * @hw: pointer to the HW structure
247 *
248 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
249 * used to reset the PHY to a quiescent state when necessary.
250 **/
251static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
252{
253 u32 mac_reg;
254
255 /* Set Phy Config Counter to 50msec */
256 mac_reg = er32(FEXTNVM3);
257 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
258 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
259 ew32(FEXTNVM3, mac_reg);
260
261 /* Toggle LANPHYPC Value bit */
262 mac_reg = er32(CTRL);
263 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
264 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267 usleep_range(10, 20);
268 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
269 ew32(CTRL, mac_reg);
270 e1e_flush();
271
272 if (hw->mac.type < e1000_pch_lpt) {
273 msleep(50);
274 } else {
275 u16 count = 20;
276
277 do {
278 usleep_range(5000, 10000);
279 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
280
281 msleep(30);
282 }
283}
284
cb17aab9
BA		 285/**
286 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
287 * @hw: pointer to the HW structure
288 *
289 * Workarounds/flow necessary for PHY initialization during driver load
290 * and resume paths.
291 **/
292static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
293{
f7235ef6 294 struct e1000_adapter *adapter = hw->adapter;
cb17aab9
BA		 295 u32 mac_reg, fwsm = er32(FWSM);
296 s32 ret_val;
297
6e928b72
BA		 298 /* Gate automatic PHY configuration by hardware on managed and
299 * non-managed 82579 and newer adapters.
300 */
301 e1000_gate_hw_phy_config_ich8lan(hw, true);
302
74f350ee
DE		 303 /* It is not possible to be certain of the current state of ULP
304 * so forcibly disable it.
305 */
306 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
307 e1000_disable_ulp_lpt_lp(hw, true);
308
cb17aab9
BA		 309 ret_val = hw->phy.ops.acquire(hw);
310 if (ret_val) {
311 e_dbg("Failed to initialize PHY flow\n");
6e928b72 312 goto out;
cb17aab9
BA		 313 }
314
e921eb1a 315 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
cb17aab9
BA		 316 * inaccessible and resetting the PHY is not blocked, toggle the
317 * LANPHYPC Value bit to force the interconnect to PCIe mode.
318 */
319 switch (hw->mac.type) {
2fbe4526
BA		 320 case e1000_pch_lpt:
321 if (e1000_phy_is_accessible_pchlan(hw))
322 break;
323
e921eb1a 324 /* Before toggling LANPHYPC, see if PHY is accessible by
2fbe4526
BA		 325 * forcing MAC to SMBus mode first.
326 */
327 mac_reg = er32(CTRL_EXT);
328 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
329 ew32(CTRL_EXT, mac_reg);
330
16b095a4
BA		 331 /* Wait 50 milliseconds for MAC to finish any retries
332 * that it might be trying to perform from previous
333 * attempts to acknowledge any phy read requests.
334 */
335 msleep(50);
336
2fbe4526 337 /* fall-through */
cb17aab9 338 case e1000_pch2lan:
16b095a4 339 if (e1000_phy_is_accessible_pchlan(hw))
cb17aab9
BA		 340 break;
341
342 /* fall-through */
343 case e1000_pchlan:
344 if ((hw->mac.type == e1000_pchlan) &&
345 (fwsm & E1000_ICH_FWSM_FW_VALID))
346 break;
347
348 if (hw->phy.ops.check_reset_block(hw)) {
349 e_dbg("Required LANPHYPC toggle blocked by ME\n");
16b095a4 350 ret_val = -E1000_ERR_PHY;
cb17aab9
BA		 351 break;
352 }
353
cb17aab9 354 /* Toggle LANPHYPC Value bit */
74f350ee
DE		 355 e1000_toggle_lanphypc_pch_lpt(hw);
356 if (hw->mac.type >= e1000_pch_lpt) {
16b095a4
BA		 357 if (e1000_phy_is_accessible_pchlan(hw))
358 break;
359
360 /* Toggling LANPHYPC brings the PHY out of SMBus mode
361 * so ensure that the MAC is also out of SMBus mode
362 */
363 mac_reg = er32(CTRL_EXT);
364 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
365 ew32(CTRL_EXT, mac_reg);
366
367 if (e1000_phy_is_accessible_pchlan(hw))
368 break;
369
370 ret_val = -E1000_ERR_PHY;
2fbe4526 371 }
cb17aab9
BA		 372 break;
373 default:
374 break;
375 }
376
377 hw->phy.ops.release(hw);
16b095a4 378 if (!ret_val) {
f7235ef6
DE		 379
380 /* Check to see if able to reset PHY. Print error if not */
381 if (hw->phy.ops.check_reset_block(hw)) {
382 e_err("Reset blocked by ME\n");
383 goto out;
384 }
385
16b095a4
BA		 386 /* Reset the PHY before any access to it. Doing so, ensures
387 * that the PHY is in a known good state before we read/write
388 * PHY registers. The generic reset is sufficient here,
389 * because we haven't determined the PHY type yet.
390 */
391 ret_val = e1000e_phy_hw_reset_generic(hw);
f7235ef6
DE		 392 if (ret_val)
393 goto out;
394
395 /* On a successful reset, possibly need to wait for the PHY
396 * to quiesce to an accessible state before returning control
397 * to the calling function. If the PHY does not quiesce, then
398 * return E1000E_BLK_PHY_RESET, as this is the condition that
399 * the PHY is in.
400 */
401 ret_val = hw->phy.ops.check_reset_block(hw);
402 if (ret_val)
403 e_err("ME blocked access to PHY after reset\n");
16b095a4 404 }
cb17aab9 405
6e928b72 406out:
cb17aab9
BA		 407 /* Ungate automatic PHY configuration on non-managed 82579 */
408 if ((hw->mac.type == e1000_pch2lan) &&
409 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
410 usleep_range(10000, 20000);
411 e1000_gate_hw_phy_config_ich8lan(hw, false);
412 }
413
414 return ret_val;
99730e4c
BA		 415}
416
a4f58f54
BA		 417/**
418 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
419 * @hw: pointer to the HW structure
420 *
421 * Initialize family-specific PHY parameters and function pointers.
422 **/
423static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
424{
425 struct e1000_phy_info *phy = &hw->phy;
70806a7f 426 s32 ret_val;
a4f58f54 427
e80bd1d1
BA		 428 phy->addr = 1;
429 phy->reset_delay_us = 100;
430
431 phy->ops.set_page = e1000_set_page_igp;
432 phy->ops.read_reg = e1000_read_phy_reg_hv;
433 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
434 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
435 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
436 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
437 phy->ops.write_reg = e1000_write_phy_reg_hv;
438 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
439 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
440 phy->ops.power_up = e1000_power_up_phy_copper;
441 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
442 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
a4f58f54 443
cb17aab9 444 phy->id = e1000_phy_unknown;
627c8a04 445
cb17aab9
BA		 446 ret_val = e1000_init_phy_workarounds_pchlan(hw);
447 if (ret_val)
448 return ret_val;
605c82ba 449
cb17aab9
BA		 450 if (phy->id == e1000_phy_unknown)
451 switch (hw->mac.type) {
452 default:
453 ret_val = e1000e_get_phy_id(hw);
454 if (ret_val)
455 return ret_val;
456 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
457 break;
458 /* fall-through */
459 case e1000_pch2lan:
2fbe4526 460 case e1000_pch_lpt:
e921eb1a 461 /* In case the PHY needs to be in mdio slow mode,
cb17aab9
BA		 462 * set slow mode and try to get the PHY id again.
463 */
464 ret_val = e1000_set_mdio_slow_mode_hv(hw);
465 if (ret_val)
466 return ret_val;
467 ret_val = e1000e_get_phy_id(hw);
468 if (ret_val)
469 return ret_val;
664dc878 470 break;
cb17aab9 471 }
a4f58f54
BA		 472 phy->type = e1000e_get_phy_type_from_id(phy->id);
473
0be84010
BA		 474 switch (phy->type) {
475 case e1000_phy_82577:
d3738bb8 476 case e1000_phy_82579:
2fbe4526 477 case e1000_phy_i217:
a4f58f54
BA		 478 phy->ops.check_polarity = e1000_check_polarity_82577;
479 phy->ops.force_speed_duplex =
6cc7aaed 480 e1000_phy_force_speed_duplex_82577;
0be84010 481 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 482 phy->ops.get_info = e1000_get_phy_info_82577;
483 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 484 break;
0be84010
BA		 485 case e1000_phy_82578:
486 phy->ops.check_polarity = e1000_check_polarity_m88;
487 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
488 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
489 phy->ops.get_info = e1000e_get_phy_info_m88;
490 break;
491 default:
492 ret_val = -E1000_ERR_PHY;
493 break;
a4f58f54
BA		 494 }
495
496 return ret_val;
497}
498
bc7f75fa
AK		 499/**
500 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
501 * @hw: pointer to the HW structure
502 *
503 * Initialize family-specific PHY parameters and function pointers.
504 **/
505static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
506{
507 struct e1000_phy_info *phy = &hw->phy;
508 s32 ret_val;
509 u16 i = 0;
510
e80bd1d1
BA		 511 phy->addr = 1;
512 phy->reset_delay_us = 100;
bc7f75fa 513
e80bd1d1
BA		 514 phy->ops.power_up = e1000_power_up_phy_copper;
515 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
17f208de 516
e921eb1a 517 /* We may need to do this twice - once for IGP and if that fails,
97ac8cae
BA		 518 * we'll set BM func pointers and try again
519 */
520 ret_val = e1000e_determine_phy_address(hw);
521 if (ret_val) {
94d8186a 522 phy->ops.write_reg = e1000e_write_phy_reg_bm;
e80bd1d1 523 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 524 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 525 if (ret_val) {
526 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 527 return ret_val;
9b71b419 528 }
97ac8cae
BA		 529 }
530
bc7f75fa
AK		 531 phy->id = 0;
532 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
533 (i++ < 100)) {
1bba4386 534 usleep_range(1000, 2000);
bc7f75fa
AK		 535 ret_val = e1000e_get_phy_id(hw);
536 if (ret_val)
537 return ret_val;
538 }
539
540 /* Verify phy id */
541 switch (phy->id) {
542 case IGP03E1000_E_PHY_ID:
543 phy->type = e1000_phy_igp_3;
544 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 545 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
546 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 547 phy->ops.get_info = e1000e_get_phy_info_igp;
548 phy->ops.check_polarity = e1000_check_polarity_igp;
549 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 550 break;
551 case IFE_E_PHY_ID:
552 case IFE_PLUS_E_PHY_ID:
553 case IFE_C_E_PHY_ID:
554 phy->type = e1000_phy_ife;
555 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 556 phy->ops.get_info = e1000_get_phy_info_ife;
557 phy->ops.check_polarity = e1000_check_polarity_ife;
558 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 559 break;
97ac8cae
BA		 560 case BME1000_E_PHY_ID:
561 phy->type = e1000_phy_bm;
562 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 563 phy->ops.read_reg = e1000e_read_phy_reg_bm;
564 phy->ops.write_reg = e1000e_write_phy_reg_bm;
565 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 566 phy->ops.get_info = e1000e_get_phy_info_m88;
567 phy->ops.check_polarity = e1000_check_polarity_m88;
568 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 569 break;
bc7f75fa
AK		 570 default:
571 return -E1000_ERR_PHY;
572 break;
573 }
574
575 return 0;
576}
577
578/**
579 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
580 * @hw: pointer to the HW structure
581 *
582 * Initialize family-specific NVM parameters and function
583 * pointers.
584 **/
585static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
586{
587 struct e1000_nvm_info *nvm = &hw->nvm;
588 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 589 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 590 u16 i;
591
ad68076e 592 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 593 if (!hw->flash_address) {
3bb99fe2 594 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 595 return -E1000_ERR_CONFIG;
596 }
597
598 nvm->type = e1000_nvm_flash_sw;
599
600 gfpreg = er32flash(ICH_FLASH_GFPREG);
601
e921eb1a 602 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 603 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 604 * the overall size.
605 */
bc7f75fa
AK		 606 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
607 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
608
609 /* flash_base_addr is byte-aligned */
610 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
611
e921eb1a 612 /* find total size of the NVM, then cut in half since the total
ad68076e
BA		 613 * size represents two separate NVM banks.
614 */
f0ff4398
BA		 615 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
616 << FLASH_SECTOR_ADDR_SHIFT);
bc7f75fa
AK		 617 nvm->flash_bank_size /= 2;
618 /* Adjust to word count */
619 nvm->flash_bank_size /= sizeof(u16);
620
621 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
622
623 /* Clear shadow ram */
624 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 625 dev_spec->shadow_ram[i].modified = false;
e80bd1d1 626 dev_spec->shadow_ram[i].value = 0xFFFF;
bc7f75fa
AK		 627 }
628
629 return 0;
630}
631
632/**
633 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
634 * @hw: pointer to the HW structure
635 *
636 * Initialize family-specific MAC parameters and function
637 * pointers.
638 **/
ec34c170 639static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
bc7f75fa 640{
bc7f75fa
AK		 641 struct e1000_mac_info *mac = &hw->mac;
642
643 /* Set media type function pointer */
318a94d6 644 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 645
646 /* Set mta register count */
647 mac->mta_reg_count = 32;
648 /* Set rar entry count */
649 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
650 if (mac->type == e1000_ich8lan)
651 mac->rar_entry_count--;
a65a4a0d
BA		 652 /* FWSM register */
653 mac->has_fwsm = true;
654 /* ARC subsystem not supported */
655 mac->arc_subsystem_valid = false;
f464ba87
BA		 656 /* Adaptive IFS supported */
657 mac->adaptive_ifs = true;
bc7f75fa 658
2fbe4526 659 /* LED and other operations */
a4f58f54
BA		 660 switch (mac->type) {
661 case e1000_ich8lan:
662 case e1000_ich9lan:
663 case e1000_ich10lan:
eb7700dc
BA		 664 /* check management mode */
665 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54 666 /* ID LED init */
d1964eb1 667 mac->ops.id_led_init = e1000e_id_led_init_generic;
dbf80dcb
BA		 668 /* blink LED */
669 mac->ops.blink_led = e1000e_blink_led_generic;
a4f58f54
BA		 670 /* setup LED */
671 mac->ops.setup_led = e1000e_setup_led_generic;
672 /* cleanup LED */
673 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
674 /* turn on/off LED */
675 mac->ops.led_on = e1000_led_on_ich8lan;
676 mac->ops.led_off = e1000_led_off_ich8lan;
677 break;
d3738bb8 678 case e1000_pch2lan:
69e1e019
BA		 679 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
680 mac->ops.rar_set = e1000_rar_set_pch2lan;
681 /* fall-through */
2fbe4526 682 case e1000_pch_lpt:
69e1e019 683 case e1000_pchlan:
eb7700dc
BA		 684 /* check management mode */
685 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 686 /* ID LED init */
687 mac->ops.id_led_init = e1000_id_led_init_pchlan;
688 /* setup LED */
689 mac->ops.setup_led = e1000_setup_led_pchlan;
690 /* cleanup LED */
691 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
692 /* turn on/off LED */
693 mac->ops.led_on = e1000_led_on_pchlan;
694 mac->ops.led_off = e1000_led_off_pchlan;
695 break;
696 default:
697 break;
698 }
699
2fbe4526
BA		 700 if (mac->type == e1000_pch_lpt) {
701 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
702 mac->ops.rar_set = e1000_rar_set_pch_lpt;
ea8179a7
BA		 703 mac->ops.setup_physical_interface =
704 e1000_setup_copper_link_pch_lpt;
2fbe4526
BA		 705 }
706
bc7f75fa
AK		 707 /* Enable PCS Lock-loss workaround for ICH8 */
708 if (mac->type == e1000_ich8lan)
564ea9bb 709 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 710
711 return 0;
712}
713
4ddc48a9
BA		 714/**
715 * __e1000_access_emi_reg_locked - Read/write EMI register
716 * @hw: pointer to the HW structure
717 * @addr: EMI address to program
718 * @data: pointer to value to read/write from/to the EMI address
719 * @read: boolean flag to indicate read or write
720 *
721 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
722 **/
723static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
724 u16 *data, bool read)
725{
70806a7f 726 s32 ret_val;
4ddc48a9
BA		 727
728 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
729 if (ret_val)
730 return ret_val;
731
732 if (read)
733 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
734 else
735 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
736
737 return ret_val;
738}
739
740/**
741 * e1000_read_emi_reg_locked - Read Extended Management Interface register
742 * @hw: pointer to the HW structure
743 * @addr: EMI address to program
744 * @data: value to be read from the EMI address
745 *
746 * Assumes the SW/FW/HW Semaphore is already acquired.
747 **/
203e4151 748s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
4ddc48a9
BA		 749{
750 return __e1000_access_emi_reg_locked(hw, addr, data, true);
751}
752
753/**
754 * e1000_write_emi_reg_locked - Write Extended Management Interface register
755 * @hw: pointer to the HW structure
756 * @addr: EMI address to program
757 * @data: value to be written to the EMI address
758 *
759 * Assumes the SW/FW/HW Semaphore is already acquired.
760 **/
d495bcb8 761s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
4ddc48a9
BA		 762{
763 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
764}
765
e52997f9
BA		 766/**
767 * e1000_set_eee_pchlan - Enable/disable EEE support
768 * @hw: pointer to the HW structure
769 *
3d4d5755
BA		 770 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
771 * the link and the EEE capabilities of the link partner. The LPI Control
772 * register bits will remain set only if/when link is up.
a03206ed
DE		 773 *
774 * EEE LPI must not be asserted earlier than one second after link is up.
775 * On 82579, EEE LPI should not be enabled until such time otherwise there
776 * can be link issues with some switches. Other devices can have EEE LPI
777 * enabled immediately upon link up since they have a timer in hardware which
778 * prevents LPI from being asserted too early.
e52997f9 779 **/
a03206ed 780s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
e52997f9 781{
2fbe4526 782 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3d4d5755 783 s32 ret_val;
d495bcb8 784 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
e52997f9 785
d495bcb8
BA		 786 switch (hw->phy.type) {
787 case e1000_phy_82579:
788 lpa = I82579_EEE_LP_ABILITY;
789 pcs_status = I82579_EEE_PCS_STATUS;
790 adv_addr = I82579_EEE_ADVERTISEMENT;
791 break;
792 case e1000_phy_i217:
793 lpa = I217_EEE_LP_ABILITY;
794 pcs_status = I217_EEE_PCS_STATUS;
795 adv_addr = I217_EEE_ADVERTISEMENT;
796 break;
797 default:
5015e53a 798 return 0;
d495bcb8 799 }
e52997f9 800
3d4d5755 801 ret_val = hw->phy.ops.acquire(hw);
e52997f9 802 if (ret_val)
5015e53a 803 return ret_val;
e52997f9 804
3d4d5755 805 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
2fbe4526 806 if (ret_val)
3d4d5755
BA		 807 goto release;
808
809 /* Clear bits that enable EEE in various speeds */
810 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
811
812 /* Enable EEE if not disabled by user */
813 if (!dev_spec->eee_disable) {
2fbe4526 814 /* Save off link partner's EEE ability */
3d4d5755 815 ret_val = e1000_read_emi_reg_locked(hw, lpa,
4ddc48a9 816 &dev_spec->eee_lp_ability);
2fbe4526
BA		 817 if (ret_val)
818 goto release;
2fbe4526 819
d495bcb8
BA		 820 /* Read EEE advertisement */
821 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
822 if (ret_val)
823 goto release;
824
3d4d5755 825 /* Enable EEE only for speeds in which the link partner is
d495bcb8 826 * EEE capable and for which we advertise EEE.
2fbe4526 827 */
d495bcb8 828 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
3d4d5755
BA		 829 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
830
d495bcb8 831 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
c2ade1a4
BA		 832 e1e_rphy_locked(hw, MII_LPA, &data);
833 if (data & LPA_100FULL)
3d4d5755
BA		 834 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
835 else
836 /* EEE is not supported in 100Half, so ignore
837 * partner's EEE in 100 ability if full-duplex
838 * is not advertised.
839 */
840 dev_spec->eee_lp_ability &=
841 ~I82579_EEE_100_SUPPORTED;
842 }
2fbe4526
BA		 843 }
844
d495bcb8
BA		 845 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
846 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
847 if (ret_val)
848 goto release;
849
3d4d5755
BA		 850 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
851release:
852 hw->phy.ops.release(hw);
853
854 return ret_val;
e52997f9
BA		 855}
856
e08f626b
BA		 857/**
858 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
859 * @hw: pointer to the HW structure
860 * @link: link up bool flag
861 *
862 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
863 * preventing further DMA write requests. Workaround the issue by disabling
864 * the de-assertion of the clock request when in 1Gpbs mode.
e0236ad9
BA		 865 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
866 * speeds in order to avoid Tx hangs.
e08f626b
BA		 867 **/
868static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
869{
870 u32 fextnvm6 = er32(FEXTNVM6);
e0236ad9 871 u32 status = er32(STATUS);
e08f626b 872 s32 ret_val = 0;
e0236ad9 873 u16 reg;
e08f626b 874
e0236ad9 875 if (link && (status & E1000_STATUS_SPEED_1000)) {
e08f626b
BA		 876 ret_val = hw->phy.ops.acquire(hw);
877 if (ret_val)
878 return ret_val;
879
880 ret_val =
881 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 882 &reg);
e08f626b
BA		 883 if (ret_val)
884 goto release;
885
886 ret_val =
887 e1000e_write_kmrn_reg_locked(hw,
888 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 889 reg &
e08f626b
BA		 890 ~E1000_KMRNCTRLSTA_K1_ENABLE);
891 if (ret_val)
892 goto release;
893
894 usleep_range(10, 20);
895
896 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
897
898 ret_val =
899 e1000e_write_kmrn_reg_locked(hw,
900 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 901 reg);
e08f626b
BA		 902release:
903 hw->phy.ops.release(hw);
904 } else {
905 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
e0236ad9
BA		 906 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
907
908 if (!link || ((status & E1000_STATUS_SPEED_100) &&
909 (status & E1000_STATUS_FD)))
910 goto update_fextnvm6;
911
912 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
913 if (ret_val)
914 return ret_val;
915
916 /* Clear link status transmit timeout */
917 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
918
919 if (status & E1000_STATUS_SPEED_100) {
920 /* Set inband Tx timeout to 5x10us for 100Half */
921 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
922
923 /* Do not extend the K1 entry latency for 100Half */
924 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
925 } else {
926 /* Set inband Tx timeout to 50x10us for 10Full/Half */
927 reg |= 50 <<
928 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
929
930 /* Extend the K1 entry latency for 10 Mbps */
931 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
932 }
933
934 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
935 if (ret_val)
936 return ret_val;
937
938update_fextnvm6:
939 ew32(FEXTNVM6, fextnvm6);
e08f626b
BA		 940 }
941
942 return ret_val;
943}
944
cf8fb73c
BA		 945/**
946 * e1000_platform_pm_pch_lpt - Set platform power management values
947 * @hw: pointer to the HW structure
948 * @link: bool indicating link status
949 *
950 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
951 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
952 * when link is up (which must not exceed the maximum latency supported
953 * by the platform), otherwise specify there is no LTR requirement.
954 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
955 * latencies in the LTR Extended Capability Structure in the PCIe Extended
956 * Capability register set, on this device LTR is set by writing the
957 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
958 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
959 * message to the PMC.
960 **/
961static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
962{
963 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
964 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
965 u16 lat_enc = 0; /* latency encoded */
966
967 if (link) {
968 u16 speed, duplex, scale = 0;
969 u16 max_snoop, max_nosnoop;
970 u16 max_ltr_enc; /* max LTR latency encoded */
971 s64 lat_ns; /* latency (ns) */
972 s64 value;
973 u32 rxa;
974
975 if (!hw->adapter->max_frame_size) {
976 e_dbg("max_frame_size not set.\n");
977 return -E1000_ERR_CONFIG;
978 }
979
980 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
981 if (!speed) {
982 e_dbg("Speed not set.\n");
983 return -E1000_ERR_CONFIG;
984 }
985
986 /* Rx Packet Buffer Allocation size (KB) */
987 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
988
989 /* Determine the maximum latency tolerated by the device.
990 *
991 * Per the PCIe spec, the tolerated latencies are encoded as
992 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
993 * a 10-bit value (0-1023) to provide a range from 1 ns to
994 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
995 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
996 */
997 lat_ns = ((s64)rxa * 1024 -
998 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
999 if (lat_ns < 0)
1000 lat_ns = 0;
1001 else
1002 do_div(lat_ns, speed);
1003
1004 value = lat_ns;
1005 while (value > PCI_LTR_VALUE_MASK) {
1006 scale++;
1007 value = DIV_ROUND_UP(value, (1 << 5));
1008 }
1009 if (scale > E1000_LTRV_SCALE_MAX) {
1010 e_dbg("Invalid LTR latency scale %d\n", scale);
1011 return -E1000_ERR_CONFIG;
1012 }
1013 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1014
1015 /* Determine the maximum latency tolerated by the platform */
1016 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1017 &max_snoop);
1018 pci_read_config_word(hw->adapter->pdev,
1019 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1020 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1021
1022 if (lat_enc > max_ltr_enc)
1023 lat_enc = max_ltr_enc;
1024 }
1025
1026 /* Set Snoop and No-Snoop latencies the same */
1027 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1028 ew32(LTRV, reg);
1029
1030 return 0;
1031}
1032
74f350ee
DE		 1033/**
1034 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1035 * @hw: pointer to the HW structure
1036 * @to_sx: boolean indicating a system power state transition to Sx
1037 *
1038 * When link is down, configure ULP mode to significantly reduce the power
1039 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1040 * ME firmware to start the ULP configuration. If not on an ME enabled
1041 * system, configure the ULP mode by software.
1042 */
1043s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1044{
1045 u32 mac_reg;
1046 s32 ret_val = 0;
1047 u16 phy_reg;
1048
1049 if ((hw->mac.type < e1000_pch_lpt) ||
1050 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1051 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1052 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1053 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1054 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1055 return 0;
1056
1057 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1058 /* Request ME configure ULP mode in the PHY */
1059 mac_reg = er32(H2ME);
1060 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1061 ew32(H2ME, mac_reg);
1062
1063 goto out;
1064 }
1065
1066 if (!to_sx) {
1067 int i = 0;
1068
1069 /* Poll up to 5 seconds for Cable Disconnected indication */
1070 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1071 /* Bail if link is re-acquired */
1072 if (er32(STATUS) & E1000_STATUS_LU)
1073 return -E1000_ERR_PHY;
1074
1075 if (i++ == 100)
1076 break;
1077
1078 msleep(50);
1079 }
1080 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1081 (er32(FEXT) &
1082 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1083 }
1084
1085 ret_val = hw->phy.ops.acquire(hw);
1086 if (ret_val)
1087 goto out;
1088
1089 /* Force SMBus mode in PHY */
1090 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1091 if (ret_val)
1092 goto release;
1093 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1094 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1095
1096 /* Force SMBus mode in MAC */
1097 mac_reg = er32(CTRL_EXT);
1098 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1099 ew32(CTRL_EXT, mac_reg);
1100
1101 /* Set Inband ULP Exit, Reset to SMBus mode and
1102 * Disable SMBus Release on PERST# in PHY
1103 */
1104 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1105 if (ret_val)
1106 goto release;
1107 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1108 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1109 if (to_sx) {
1110 if (er32(WUFC) & E1000_WUFC_LNKC)
1111 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1112
1113 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1114 } else {
1115 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1116 }
1117 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1118
1119 /* Set Disable SMBus Release on PERST# in MAC */
1120 mac_reg = er32(FEXTNVM7);
1121 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1122 ew32(FEXTNVM7, mac_reg);
1123
1124 /* Commit ULP changes in PHY by starting auto ULP configuration */
1125 phy_reg |= I218_ULP_CONFIG1_START;
1126 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1127release:
1128 hw->phy.ops.release(hw);
1129out:
1130 if (ret_val)
1131 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1132 else
1133 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1134
1135 return ret_val;
1136}
1137
1138/**
1139 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1140 * @hw: pointer to the HW structure
1141 * @force: boolean indicating whether or not to force disabling ULP
1142 *
1143 * Un-configure ULP mode when link is up, the system is transitioned from
1144 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1145 * system, poll for an indication from ME that ULP has been un-configured.
1146 * If not on an ME enabled system, un-configure the ULP mode by software.
1147 *
1148 * During nominal operation, this function is called when link is acquired
1149 * to disable ULP mode (force=false); otherwise, for example when unloading
1150 * the driver or during Sx->S0 transitions, this is called with force=true
1151 * to forcibly disable ULP.
1152 */
1153static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1154{
1155 s32 ret_val = 0;
1156 u32 mac_reg;
1157 u16 phy_reg;
1158 int i = 0;
1159
1160 if ((hw->mac.type < e1000_pch_lpt) ||
1161 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1162 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1163 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1164 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1165 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1166 return 0;
1167
1168 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1169 if (force) {
1170 /* Request ME un-configure ULP mode in the PHY */
1171 mac_reg = er32(H2ME);
1172 mac_reg &= ~E1000_H2ME_ULP;
1173 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1174 ew32(H2ME, mac_reg);
1175 }
1176
1177 /* Poll up to 100msec for ME to clear ULP_CFG_DONE */
1178 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1179 if (i++ == 10) {
1180 ret_val = -E1000_ERR_PHY;
1181 goto out;
1182 }
1183
1184 usleep_range(10000, 20000);
1185 }
1186 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1187
1188 if (force) {
1189 mac_reg = er32(H2ME);
1190 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1191 ew32(H2ME, mac_reg);
1192 } else {
1193 /* Clear H2ME.ULP after ME ULP configuration */
1194 mac_reg = er32(H2ME);
1195 mac_reg &= ~E1000_H2ME_ULP;
1196 ew32(H2ME, mac_reg);
1197 }
1198
1199 goto out;
1200 }
1201
1202 ret_val = hw->phy.ops.acquire(hw);
1203 if (ret_val)
1204 goto out;
1205
1206 if (force)
1207 /* Toggle LANPHYPC Value bit */
1208 e1000_toggle_lanphypc_pch_lpt(hw);
1209
1210 /* Unforce SMBus mode in PHY */
1211 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1212 if (ret_val) {
1213 /* The MAC might be in PCIe mode, so temporarily force to
1214 * SMBus mode in order to access the PHY.
1215 */
1216 mac_reg = er32(CTRL_EXT);
1217 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1218 ew32(CTRL_EXT, mac_reg);
1219
1220 msleep(50);
1221
1222 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1223 &phy_reg);
1224 if (ret_val)
1225 goto release;
1226 }
1227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1228 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1229
1230 /* Unforce SMBus mode in MAC */
1231 mac_reg = er32(CTRL_EXT);
1232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1233 ew32(CTRL_EXT, mac_reg);
1234
1235 /* When ULP mode was previously entered, K1 was disabled by the
1236 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1237 */
1238 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1239 if (ret_val)
1240 goto release;
1241 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1242 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1243
1244 /* Clear ULP enabled configuration */
1245 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1246 if (ret_val)
1247 goto release;
1248 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1249 I218_ULP_CONFIG1_STICKY_ULP |
1250 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1251 I218_ULP_CONFIG1_WOL_HOST |
1252 I218_ULP_CONFIG1_INBAND_EXIT |
1253 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1254 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1255
1256 /* Commit ULP changes by starting auto ULP configuration */
1257 phy_reg |= I218_ULP_CONFIG1_START;
1258 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1259
1260 /* Clear Disable SMBus Release on PERST# in MAC */
1261 mac_reg = er32(FEXTNVM7);
1262 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1263 ew32(FEXTNVM7, mac_reg);
1264
1265release:
1266 hw->phy.ops.release(hw);
1267 if (force) {
1268 e1000_phy_hw_reset(hw);
1269 msleep(50);
1270 }
1271out:
1272 if (ret_val)
1273 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1274 else
1275 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1276
1277 return ret_val;
1278}
1279
7d3cabbc
BA		 1280/**
1281 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1282 * @hw: pointer to the HW structure
1283 *
1284 * Checks to see of the link status of the hardware has changed. If a
1285 * change in link status has been detected, then we read the PHY registers
1286 * to get the current speed/duplex if link exists.
1287 **/
1288static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1289{
1290 struct e1000_mac_info *mac = &hw->mac;
1291 s32 ret_val;
1292 bool link;
1d2101a7 1293 u16 phy_reg;
7d3cabbc 1294
e921eb1a 1295 /* We only want to go out to the PHY registers to see if Auto-Neg
7d3cabbc
BA		 1296 * has completed and/or if our link status has changed. The
1297 * get_link_status flag is set upon receiving a Link Status
1298 * Change or Rx Sequence Error interrupt.
1299 */
5015e53a
BA		 1300 if (!mac->get_link_status)
1301 return 0;
7d3cabbc 1302
e921eb1a 1303 /* First we want to see if the MII Status Register reports
7d3cabbc
BA		 1304 * link. If so, then we want to get the current speed/duplex
1305 * of the PHY.
1306 */
1307 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1308 if (ret_val)
5015e53a 1309 return ret_val;
7d3cabbc 1310
1d5846b9
BA		 1311 if (hw->mac.type == e1000_pchlan) {
1312 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1313 if (ret_val)
5015e53a 1314 return ret_val;
1d5846b9
BA		 1315 }
1316
772d05c5
BA		 1317 /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1318 * aggressive resulting in many collisions. To avoid this, increase
1319 * the IPG and reduce Rx latency in the PHY.
1320 */
1321 if ((hw->mac.type == e1000_pch2lan) && link) {
1322 u32 reg;
1323 reg = er32(STATUS);
1324 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1325 reg = er32(TIPG);
1326 reg &= ~E1000_TIPG_IPGT_MASK;
1327 reg |= 0xFF;
1328 ew32(TIPG, reg);
1329
1330 /* Reduce Rx latency in analog PHY */
1331 ret_val = hw->phy.ops.acquire(hw);
1332 if (ret_val)
1333 return ret_val;
1334
1335 ret_val =
1336 e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1337
1338 hw->phy.ops.release(hw);
1339
1340 if (ret_val)
1341 return ret_val;
1342 }
1343 }
1344
e08f626b
BA		 1345 /* Work-around I218 hang issue */
1346 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 1347 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1348 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1349 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
e08f626b
BA		 1350 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1351 if (ret_val)
1352 return ret_val;
1353 }
1354
cf8fb73c
BA		 1355 if (hw->mac.type == e1000_pch_lpt) {
1356 /* Set platform power management values for
1357 * Latency Tolerance Reporting (LTR)
1358 */
1359 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1360 if (ret_val)
1361 return ret_val;
1362 }
1363
2fbe4526
BA		 1364 /* Clear link partner's EEE ability */
1365 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1366
7d3cabbc 1367 if (!link)
e80bd1d1 1368 return 0; /* No link detected */
7d3cabbc
BA		 1369
1370 mac->get_link_status = false;
1371
1d2101a7
BA		 1372 switch (hw->mac.type) {
1373 case e1000_pch2lan:
831bd2e6
BA		 1374 ret_val = e1000_k1_workaround_lv(hw);
1375 if (ret_val)
5015e53a 1376 return ret_val;
1d2101a7
BA		 1377 /* fall-thru */
1378 case e1000_pchlan:
1379 if (hw->phy.type == e1000_phy_82578) {
1380 ret_val = e1000_link_stall_workaround_hv(hw);
1381 if (ret_val)
5015e53a 1382 return ret_val;
1d2101a7
BA		 1383 }
1384
e921eb1a 1385 /* Workaround for PCHx parts in half-duplex:
1d2101a7
BA		 1386 * Set the number of preambles removed from the packet
1387 * when it is passed from the PHY to the MAC to prevent
1388 * the MAC from misinterpreting the packet type.
1389 */
1390 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1391 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1392
1393 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1394 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1395
1396 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1397 break;
1398 default:
1399 break;
831bd2e6
BA		 1400 }
1401
e921eb1a 1402 /* Check if there was DownShift, must be checked
7d3cabbc
BA		 1403 * immediately after link-up
1404 */
1405 e1000e_check_downshift(hw);
1406
e52997f9 1407 /* Enable/Disable EEE after link up */
a03206ed
DE		 1408 if (hw->phy.type > e1000_phy_82579) {
1409 ret_val = e1000_set_eee_pchlan(hw);
1410 if (ret_val)
1411 return ret_val;
1412 }
e52997f9 1413
e921eb1a 1414 /* If we are forcing speed/duplex, then we simply return since
7d3cabbc
BA		 1415 * we have already determined whether we have link or not.
1416 */
5015e53a
BA		 1417 if (!mac->autoneg)
1418 return -E1000_ERR_CONFIG;
7d3cabbc 1419
e921eb1a 1420 /* Auto-Neg is enabled. Auto Speed Detection takes care
7d3cabbc
BA		 1421 * of MAC speed/duplex configuration. So we only need to
1422 * configure Collision Distance in the MAC.
1423 */
57cde763 1424 mac->ops.config_collision_dist(hw);
7d3cabbc 1425
e921eb1a 1426 /* Configure Flow Control now that Auto-Neg has completed.
7d3cabbc
BA		 1427 * First, we need to restore the desired flow control
1428 * settings because we may have had to re-autoneg with a
1429 * different link partner.
1430 */
1431 ret_val = e1000e_config_fc_after_link_up(hw);
1432 if (ret_val)
3bb99fe2 1433 e_dbg("Error configuring flow control\n");
7d3cabbc 1434
7d3cabbc
BA		 1435 return ret_val;
1436}
1437
69e3fd8c 1438static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 1439{
1440 struct e1000_hw *hw = &adapter->hw;
1441 s32 rc;
1442
ec34c170 1443 rc = e1000_init_mac_params_ich8lan(hw);
bc7f75fa
AK		 1444 if (rc)
1445 return rc;
1446
1447 rc = e1000_init_nvm_params_ich8lan(hw);
1448 if (rc)
1449 return rc;
1450
d3738bb8
BA		 1451 switch (hw->mac.type) {
1452 case e1000_ich8lan:
1453 case e1000_ich9lan:
1454 case e1000_ich10lan:
a4f58f54 1455 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 1456 break;
1457 case e1000_pchlan:
1458 case e1000_pch2lan:
2fbe4526 1459 case e1000_pch_lpt:
d3738bb8
BA		 1460 rc = e1000_init_phy_params_pchlan(hw);
1461 break;
1462 default:
1463 break;
1464 }
bc7f75fa
AK		 1465 if (rc)
1466 return rc;
1467
e921eb1a 1468 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
23e4f061
BA		 1469 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1470 */
1471 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1472 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1473 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
2adc55c9
BA		 1474 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1475 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
dbf80dcb
BA		 1476
1477 hw->mac.ops.blink_led = NULL;
2adc55c9
BA		 1478 }
1479
bc7f75fa 1480 if ((adapter->hw.mac.type == e1000_ich8lan) &&
462d5994 1481 (adapter->hw.phy.type != e1000_phy_ife))
bc7f75fa
AK		 1482 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1483
c6e7f51e
BA		 1484 /* Enable workaround for 82579 w/ ME enabled */
1485 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1486 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1487 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1488
bc7f75fa
AK		 1489 return 0;
1490}
1491
717d438d 1492static DEFINE_MUTEX(nvm_mutex);
717d438d 1493
ca15df58
BA		 1494/**
1495 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1496 * @hw: pointer to the HW structure
1497 *
1498 * Acquires the mutex for performing NVM operations.
1499 **/
8bb62869 1500static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1501{
1502 mutex_lock(&nvm_mutex);
1503
1504 return 0;
1505}
1506
1507/**
1508 * e1000_release_nvm_ich8lan - Release NVM mutex
1509 * @hw: pointer to the HW structure
1510 *
1511 * Releases the mutex used while performing NVM operations.
1512 **/
8bb62869 1513static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1514{
1515 mutex_unlock(&nvm_mutex);
ca15df58
BA		 1516}
1517
bc7f75fa
AK		 1518/**
1519 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1520 * @hw: pointer to the HW structure
1521 *
ca15df58
BA		 1522 * Acquires the software control flag for performing PHY and select
1523 * MAC CSR accesses.
bc7f75fa
AK		 1524 **/
1525static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1526{
373a88d7
BA		 1527 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1528 s32 ret_val = 0;
bc7f75fa 1529
a90b412c
BA		 1530 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1531 &hw->adapter->state)) {
34c9ef8b 1532 e_dbg("contention for Phy access\n");
a90b412c
BA		 1533 return -E1000_ERR_PHY;
1534 }
717d438d 1535
bc7f75fa
AK		 1536 while (timeout) {
1537 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 1538 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1539 break;
bc7f75fa 1540
373a88d7
BA		 1541 mdelay(1);
1542 timeout--;
1543 }
1544
1545 if (!timeout) {
a90b412c 1546 e_dbg("SW has already locked the resource.\n");
373a88d7
BA		 1547 ret_val = -E1000_ERR_CONFIG;
1548 goto out;
1549 }
1550
53ac5a88 1551 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 1552
1553 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1554 ew32(EXTCNF_CTRL, extcnf_ctrl);
1555
1556 while (timeout) {
1557 extcnf_ctrl = er32(EXTCNF_CTRL);
1558 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1559 break;
a4f58f54 1560
bc7f75fa
AK		 1561 mdelay(1);
1562 timeout--;
1563 }
1564
1565 if (!timeout) {
434f1392 1566 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
a90b412c 1567 er32(FWSM), extcnf_ctrl);
2e2e8d53
BA		 1568 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1569 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 1570 ret_val = -E1000_ERR_CONFIG;
1571 goto out;
bc7f75fa
AK		 1572 }
1573
373a88d7
BA		 1574out:
1575 if (ret_val)
a90b412c 1576 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
373a88d7
BA		 1577
1578 return ret_val;
bc7f75fa
AK		 1579}
1580
1581/**
1582 * e1000_release_swflag_ich8lan - Release software control flag
1583 * @hw: pointer to the HW structure
1584 *
ca15df58
BA		 1585 * Releases the software control flag for performing PHY and select
1586 * MAC CSR accesses.
bc7f75fa
AK		 1587 **/
1588static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1589{
1590 u32 extcnf_ctrl;
1591
1592 extcnf_ctrl = er32(EXTCNF_CTRL);
c5caf482
BA		 1593
1594 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1595 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1596 ew32(EXTCNF_CTRL, extcnf_ctrl);
1597 } else {
1598 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1599 }
717d438d 1600
a90b412c 1601 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
bc7f75fa
AK		 1602}
1603
4662e82b
BA		 1604/**
1605 * e1000_check_mng_mode_ich8lan - Checks management mode
1606 * @hw: pointer to the HW structure
1607 *
eb7700dc 1608 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 1609 * This is a function pointer entry point only called by read/write
1610 * routines for the PHY and NVM parts.
1611 **/
1612static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1613{
a708dd88
BA		 1614 u32 fwsm;
1615
1616 fwsm = er32(FWSM);
f0ff4398
BA		 1617 return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1618 ((fwsm & E1000_FWSM_MODE_MASK) ==
1619 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
eb7700dc 1620}
4662e82b 1621
eb7700dc
BA		 1622/**
1623 * e1000_check_mng_mode_pchlan - Checks management mode
1624 * @hw: pointer to the HW structure
1625 *
1626 * This checks if the adapter has iAMT enabled.
1627 * This is a function pointer entry point only called by read/write
1628 * routines for the PHY and NVM parts.
1629 **/
1630static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1631{
1632 u32 fwsm;
1633
1634 fwsm = er32(FWSM);
1635 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
f0ff4398 1636 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 1637}
1638
69e1e019
BA		 1639/**
1640 * e1000_rar_set_pch2lan - Set receive address register
1641 * @hw: pointer to the HW structure
1642 * @addr: pointer to the receive address
1643 * @index: receive address array register
1644 *
1645 * Sets the receive address array register at index to the address passed
1646 * in by addr. For 82579, RAR[0] is the base address register that is to
1647 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1648 * Use SHRA[0-3] in place of those reserved for ME.
1649 **/
1650static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1651{
1652 u32 rar_low, rar_high;
1653
e921eb1a 1654 /* HW expects these in little endian so we reverse the byte order
69e1e019
BA		 1655 * from network order (big endian) to little endian
1656 */
1657 rar_low = ((u32)addr[0] |
1658 ((u32)addr[1] << 8) |
1659 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1660
1661 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1662
1663 /* If MAC address zero, no need to set the AV bit */
1664 if (rar_low || rar_high)
1665 rar_high |= E1000_RAH_AV;
1666
1667 if (index == 0) {
1668 ew32(RAL(index), rar_low);
1669 e1e_flush();
1670 ew32(RAH(index), rar_high);
1671 e1e_flush();
1672 return;
1673 }
1674
c3a0dce3
DE		 1675 /* RAR[1-6] are owned by manageability. Skip those and program the
1676 * next address into the SHRA register array.
1677 */
96dee024 1678 if (index < (u32)(hw->mac.rar_entry_count)) {
69e1e019
BA		 1679 s32 ret_val;
1680
1681 ret_val = e1000_acquire_swflag_ich8lan(hw);
1682 if (ret_val)
1683 goto out;
1684
1685 ew32(SHRAL(index - 1), rar_low);
1686 e1e_flush();
1687 ew32(SHRAH(index - 1), rar_high);
1688 e1e_flush();
1689
1690 e1000_release_swflag_ich8lan(hw);
1691
1692 /* verify the register updates */
1693 if ((er32(SHRAL(index - 1)) == rar_low) &&
1694 (er32(SHRAH(index - 1)) == rar_high))
1695 return;
1696
1697 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1698 (index - 1), er32(FWSM));
1699 }
1700
1701out:
1702 e_dbg("Failed to write receive address at index %d\n", index);
1703}
1704
2fbe4526
BA		 1705/**
1706 * e1000_rar_set_pch_lpt - Set receive address registers
1707 * @hw: pointer to the HW structure
1708 * @addr: pointer to the receive address
1709 * @index: receive address array register
1710 *
1711 * Sets the receive address register array at index to the address passed
1712 * in by addr. For LPT, RAR[0] is the base address register that is to
1713 * contain the MAC address. SHRA[0-10] are the shared receive address
1714 * registers that are shared between the Host and manageability engine (ME).
1715 **/
1716static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1717{
1718 u32 rar_low, rar_high;
1719 u32 wlock_mac;
1720
e921eb1a 1721 /* HW expects these in little endian so we reverse the byte order
2fbe4526
BA		 1722 * from network order (big endian) to little endian
1723 */
1724 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1725 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1726
1727 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1728
1729 /* If MAC address zero, no need to set the AV bit */
1730 if (rar_low || rar_high)
1731 rar_high |= E1000_RAH_AV;
1732
1733 if (index == 0) {
1734 ew32(RAL(index), rar_low);
1735 e1e_flush();
1736 ew32(RAH(index), rar_high);
1737 e1e_flush();
1738 return;
1739 }
1740
e921eb1a 1741 /* The manageability engine (ME) can lock certain SHRAR registers that
2fbe4526
BA		 1742 * it is using - those registers are unavailable for use.
1743 */
1744 if (index < hw->mac.rar_entry_count) {
1745 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1746 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1747
1748 /* Check if all SHRAR registers are locked */
1749 if (wlock_mac == 1)
1750 goto out;
1751
1752 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1753 s32 ret_val;
1754
1755 ret_val = e1000_acquire_swflag_ich8lan(hw);
1756
1757 if (ret_val)
1758 goto out;
1759
1760 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1761 e1e_flush();
1762 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1763 e1e_flush();
1764
1765 e1000_release_swflag_ich8lan(hw);
1766
1767 /* verify the register updates */
1768 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1769 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1770 return;
1771 }
1772 }
1773
1774out:
1775 e_dbg("Failed to write receive address at index %d\n", index);
1776}
1777
bc7f75fa
AK		 1778/**
1779 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1780 * @hw: pointer to the HW structure
1781 *
1782 * Checks if firmware is blocking the reset of the PHY.
1783 * This is a function pointer entry point only called by
1784 * reset routines.
1785 **/
1786static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1787{
f7235ef6
DE		 1788 bool blocked = false;
1789 int i = 0;
bc7f75fa 1790
f7235ef6
DE		 1791 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
1792 (i++ < 10))
1793 usleep_range(10000, 20000);
1794 return blocked ? E1000_BLK_PHY_RESET : 0;
bc7f75fa
AK		 1795}
1796
8395ae83
BA		 1797/**
1798 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1799 * @hw: pointer to the HW structure
1800 *
1801 * Assumes semaphore already acquired.
1802 *
1803 **/
1804static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1805{
1806 u16 phy_data;
1807 u32 strap = er32(STRAP);
2fbe4526
BA		 1808 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1809 E1000_STRAP_SMT_FREQ_SHIFT;
70806a7f 1810 s32 ret_val;
8395ae83
BA		 1811
1812 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1813
1814 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1815 if (ret_val)
5015e53a 1816 return ret_val;
8395ae83
BA		 1817
1818 phy_data &= ~HV_SMB_ADDR_MASK;
1819 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1820 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
8395ae83 1821
2fbe4526
BA		 1822 if (hw->phy.type == e1000_phy_i217) {
1823 /* Restore SMBus frequency */
1824 if (freq--) {
1825 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1826 phy_data |= (freq & (1 << 0)) <<
1827 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1828 phy_data |= (freq & (1 << 1)) <<
1829 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1830 } else {
1831 e_dbg("Unsupported SMB frequency in PHY\n");
1832 }
1833 }
1834
5015e53a 1835 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
8395ae83
BA		 1836}
1837
f523d211
BA		 1838/**
1839 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1840 * @hw: pointer to the HW structure
1841 *
1842 * SW should configure the LCD from the NVM extended configuration region
1843 * as a workaround for certain parts.
1844 **/
1845static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1846{
1847 struct e1000_phy_info *phy = &hw->phy;
1848 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 1849 s32 ret_val = 0;
f523d211
BA		 1850 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1851
e921eb1a 1852 /* Initialize the PHY from the NVM on ICH platforms. This
f523d211
BA		 1853 * is needed due to an issue where the NVM configuration is
1854 * not properly autoloaded after power transitions.
1855 * Therefore, after each PHY reset, we will load the
1856 * configuration data out of the NVM manually.
1857 */
3f0c16e8
BA		 1858 switch (hw->mac.type) {
1859 case e1000_ich8lan:
1860 if (phy->type != e1000_phy_igp_3)
1861 return ret_val;
1862
5f3eed6f
BA		 1863 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1864 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 1865 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1866 break;
1867 }
1868 /* Fall-thru */
1869 case e1000_pchlan:
d3738bb8 1870 case e1000_pch2lan:
2fbe4526 1871 case e1000_pch_lpt:
8b802a7e 1872 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 1873 break;
1874 default:
1875 return ret_val;
1876 }
1877
1878 ret_val = hw->phy.ops.acquire(hw);
1879 if (ret_val)
1880 return ret_val;
8b802a7e
BA		 1881
1882 data = er32(FEXTNVM);
1883 if (!(data & sw_cfg_mask))
75ce1532 1884 goto release;
f523d211 1885
e921eb1a 1886 /* Make sure HW does not configure LCD from PHY
8b802a7e
BA		 1887 * extended configuration before SW configuration
1888 */
1889 data = er32(EXTCNF_CTRL);
2fbe4526
BA		 1890 if ((hw->mac.type < e1000_pch2lan) &&
1891 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1892 goto release;
8b802a7e
BA		 1893
1894 cnf_size = er32(EXTCNF_SIZE);
1895 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1896 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1897 if (!cnf_size)
75ce1532 1898 goto release;
8b802a7e
BA		 1899
1900 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1901 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1902
2fbe4526
BA		 1903 if (((hw->mac.type == e1000_pchlan) &&
1904 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1905 (hw->mac.type > e1000_pchlan)) {
e921eb1a 1906 /* HW configures the SMBus address and LEDs when the
8b802a7e
BA		 1907 * OEM and LCD Write Enable bits are set in the NVM.
1908 * When both NVM bits are cleared, SW will configure
1909 * them instead.
f523d211 1910 */
8395ae83 1911 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1912 if (ret_val)
75ce1532 1913 goto release;
f523d211 1914
8b802a7e
BA		 1915 data = er32(LEDCTL);
1916 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1917 (u16)data);
1918 if (ret_val)
75ce1532 1919 goto release;
8b802a7e 1920 }
f523d211 1921
8b802a7e
BA		 1922 /* Configure LCD from extended configuration region. */
1923
1924 /* cnf_base_addr is in DWORD */
1925 word_addr = (u16)(cnf_base_addr << 1);
1926
1927 for (i = 0; i < cnf_size; i++) {
e5fe2541 1928 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
8b802a7e 1929 if (ret_val)
75ce1532 1930 goto release;
8b802a7e
BA		 1931
1932 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1933 1, &reg_addr);
1934 if (ret_val)
75ce1532 1935 goto release;
8b802a7e
BA		 1936
1937 /* Save off the PHY page for future writes. */
1938 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1939 phy_page = reg_data;
1940 continue;
f523d211 1941 }
8b802a7e
BA		 1942
1943 reg_addr &= PHY_REG_MASK;
1944 reg_addr |= phy_page;
1945
f1430d69 1946 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
8b802a7e 1947 if (ret_val)
75ce1532 1948 goto release;
f523d211
BA		 1949 }
1950
75ce1532 1951release:
94d8186a 1952 hw->phy.ops.release(hw);
f523d211
BA		 1953 return ret_val;
1954}
1955
1d5846b9
BA		 1956/**
1957 * e1000_k1_gig_workaround_hv - K1 Si workaround
1958 * @hw: pointer to the HW structure
1959 * @link: link up bool flag
1960 *
1961 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1962 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1963 * If link is down, the function will restore the default K1 setting located
1964 * in the NVM.
1965 **/
1966static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1967{
1968 s32 ret_val = 0;
1969 u16 status_reg = 0;
1970 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1971
1972 if (hw->mac.type != e1000_pchlan)
5015e53a 1973 return 0;
1d5846b9
BA		 1974
1975 /* Wrap the whole flow with the sw flag */
94d8186a 1976 ret_val = hw->phy.ops.acquire(hw);
1d5846b9 1977 if (ret_val)
5015e53a 1978 return ret_val;
1d5846b9
BA		 1979
1980 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1981 if (link) {
1982 if (hw->phy.type == e1000_phy_82578) {
f1430d69
BA		 1983 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1984 &status_reg);
1d5846b9
BA		 1985 if (ret_val)
1986 goto release;
1987
f0ff4398
BA		 1988 status_reg &= (BM_CS_STATUS_LINK_UP |
1989 BM_CS_STATUS_RESOLVED |
1990 BM_CS_STATUS_SPEED_MASK);
1d5846b9
BA		 1991
1992 if (status_reg == (BM_CS_STATUS_LINK_UP |
f0ff4398
BA		 1993 BM_CS_STATUS_RESOLVED |
1994 BM_CS_STATUS_SPEED_1000))
1d5846b9
BA		 1995 k1_enable = false;
1996 }
1997
1998 if (hw->phy.type == e1000_phy_82577) {
f1430d69 1999 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1d5846b9
BA		 2000 if (ret_val)
2001 goto release;
2002
f0ff4398
BA		 2003 status_reg &= (HV_M_STATUS_LINK_UP |
2004 HV_M_STATUS_AUTONEG_COMPLETE |
2005 HV_M_STATUS_SPEED_MASK);
1d5846b9
BA		 2006
2007 if (status_reg == (HV_M_STATUS_LINK_UP |
f0ff4398
BA		 2008 HV_M_STATUS_AUTONEG_COMPLETE |
2009 HV_M_STATUS_SPEED_1000))
1d5846b9
BA		 2010 k1_enable = false;
2011 }
2012
2013 /* Link stall fix for link up */
f1430d69 2014 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1d5846b9
BA		 2015 if (ret_val)
2016 goto release;
2017
2018 } else {
2019 /* Link stall fix for link down */
f1430d69 2020 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1d5846b9
BA		 2021 if (ret_val)
2022 goto release;
2023 }
2024
2025 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2026
2027release:
94d8186a 2028 hw->phy.ops.release(hw);
5015e53a 2029
1d5846b9
BA		 2030 return ret_val;
2031}
2032
2033/**
2034 * e1000_configure_k1_ich8lan - Configure K1 power state
2035 * @hw: pointer to the HW structure
2036 * @enable: K1 state to configure
2037 *
2038 * Configure the K1 power state based on the provided parameter.
2039 * Assumes semaphore already acquired.
2040 *
2041 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2042 **/
bb436b20 2043s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9 2044{
70806a7f 2045 s32 ret_val;
1d5846b9
BA		 2046 u32 ctrl_reg = 0;
2047 u32 ctrl_ext = 0;
2048 u32 reg = 0;
2049 u16 kmrn_reg = 0;
2050
3d3a1676
BA		 2051 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2052 &kmrn_reg);
1d5846b9 2053 if (ret_val)
5015e53a 2054 return ret_val;
1d5846b9
BA		 2055
2056 if (k1_enable)
2057 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2058 else
2059 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2060
3d3a1676
BA		 2061 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2062 kmrn_reg);
1d5846b9 2063 if (ret_val)
5015e53a 2064 return ret_val;
1d5846b9 2065
ce43a216 2066 usleep_range(20, 40);
1d5846b9
BA		 2067 ctrl_ext = er32(CTRL_EXT);
2068 ctrl_reg = er32(CTRL);
2069
2070 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2071 reg |= E1000_CTRL_FRCSPD;
2072 ew32(CTRL, reg);
2073
2074 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
945a5151 2075 e1e_flush();
ce43a216 2076 usleep_range(20, 40);
1d5846b9
BA		 2077 ew32(CTRL, ctrl_reg);
2078 ew32(CTRL_EXT, ctrl_ext);
945a5151 2079 e1e_flush();
ce43a216 2080 usleep_range(20, 40);
1d5846b9 2081
5015e53a 2082 return 0;
1d5846b9
BA		 2083}
2084
f523d211
BA		 2085/**
2086 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2087 * @hw: pointer to the HW structure
2088 * @d0_state: boolean if entering d0 or d3 device state
2089 *
2090 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2091 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2092 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2093 **/
2094static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2095{
2096 s32 ret_val = 0;
2097 u32 mac_reg;
2098 u16 oem_reg;
2099
2fbe4526 2100 if (hw->mac.type < e1000_pchlan)
f523d211
BA		 2101 return ret_val;
2102
94d8186a 2103 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 2104 if (ret_val)
2105 return ret_val;
2106
2fbe4526 2107 if (hw->mac.type == e1000_pchlan) {
d3738bb8
BA		 2108 mac_reg = er32(EXTCNF_CTRL);
2109 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
75ce1532 2110 goto release;
d3738bb8 2111 }
f523d211
BA		 2112
2113 mac_reg = er32(FEXTNVM);
2114 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
75ce1532 2115 goto release;
f523d211
BA		 2116
2117 mac_reg = er32(PHY_CTRL);
2118
f1430d69 2119 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211 2120 if (ret_val)
75ce1532 2121 goto release;
f523d211
BA		 2122
2123 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2124
2125 if (d0_state) {
2126 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2127 oem_reg |= HV_OEM_BITS_GBE_DIS;
2128
2129 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2130 oem_reg |= HV_OEM_BITS_LPLU;
2131 } else {
03299e46
BA		 2132 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2133 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
f523d211
BA		 2134 oem_reg |= HV_OEM_BITS_GBE_DIS;
2135
03299e46
BA		 2136 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2137 E1000_PHY_CTRL_NOND0A_LPLU))
f523d211
BA		 2138 oem_reg |= HV_OEM_BITS_LPLU;
2139 }
03299e46 2140
92fe1733
BA		 2141 /* Set Restart auto-neg to activate the bits */
2142 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2143 !hw->phy.ops.check_reset_block(hw))
2144 oem_reg |= HV_OEM_BITS_RESTART_AN;
2145
f1430d69 2146 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
f523d211 2147
75ce1532 2148release:
94d8186a 2149 hw->phy.ops.release(hw);
f523d211
BA		 2150
2151 return ret_val;
2152}
2153
fddaa1af
BA		 2154/**
2155 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2156 * @hw: pointer to the HW structure
2157 **/
2158static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2159{
2160 s32 ret_val;
2161 u16 data;
2162
2163 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2164 if (ret_val)
2165 return ret_val;
2166
2167 data |= HV_KMRN_MDIO_SLOW;
2168
2169 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2170
2171 return ret_val;
2172}
2173
a4f58f54
BA		 2174/**
2175 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2176 * done after every PHY reset.
2177 **/
2178static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2179{
2180 s32 ret_val = 0;
baf86c9d 2181 u16 phy_data;
a4f58f54
BA		 2182
2183 if (hw->mac.type != e1000_pchlan)
5015e53a 2184 return 0;
a4f58f54 2185
fddaa1af
BA		 2186 /* Set MDIO slow mode before any other MDIO access */
2187 if (hw->phy.type == e1000_phy_82577) {
2188 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2189 if (ret_val)
5015e53a 2190 return ret_val;
fddaa1af
BA		 2191 }
2192
a4f58f54
BA		 2193 if (((hw->phy.type == e1000_phy_82577) &&
2194 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2195 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2196 /* Disable generation of early preamble */
2197 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2198 if (ret_val)
2199 return ret_val;
2200
2201 /* Preamble tuning for SSC */
1d2101a7 2202 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
a4f58f54
BA		 2203 if (ret_val)
2204 return ret_val;
2205 }
2206
2207 if (hw->phy.type == e1000_phy_82578) {
e921eb1a 2208 /* Return registers to default by doing a soft reset then
a4f58f54
BA		 2209 * writing 0x3140 to the control register.
2210 */
2211 if (hw->phy.revision < 2) {
2212 e1000e_phy_sw_reset(hw);
c2ade1a4 2213 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
a4f58f54
BA		 2214 }
2215 }
2216
2217 /* Select page 0 */
94d8186a 2218 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 2219 if (ret_val)
2220 return ret_val;
1d5846b9 2221
a4f58f54 2222 hw->phy.addr = 1;
1d5846b9 2223 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 2224 hw->phy.ops.release(hw);
1d5846b9 2225 if (ret_val)
5015e53a 2226 return ret_val;
a4f58f54 2227
e921eb1a 2228 /* Configure the K1 Si workaround during phy reset assuming there is
1d5846b9
BA		 2229 * link so that it disables K1 if link is in 1Gbps.
2230 */
2231 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d 2232 if (ret_val)
5015e53a 2233 return ret_val;
1d5846b9 2234
baf86c9d
BA		 2235 /* Workaround for link disconnects on a busy hub in half duplex */
2236 ret_val = hw->phy.ops.acquire(hw);
2237 if (ret_val)
5015e53a 2238 return ret_val;
f1430d69 2239 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
baf86c9d
BA		 2240 if (ret_val)
2241 goto release;
f1430d69 2242 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
651fb102
BA		 2243 if (ret_val)
2244 goto release;
2245
2246 /* set MSE higher to enable link to stay up when noise is high */
2247 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
baf86c9d
BA		 2248release:
2249 hw->phy.ops.release(hw);
5015e53a 2250
a4f58f54
BA		 2251 return ret_val;
2252}
2253
d3738bb8
BA		 2254/**
2255 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2256 * @hw: pointer to the HW structure
2257 **/
2258void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2259{
2260 u32 mac_reg;
2b6b168d
BA		 2261 u16 i, phy_reg = 0;
2262 s32 ret_val;
2263
2264 ret_val = hw->phy.ops.acquire(hw);
2265 if (ret_val)
2266 return;
2267 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2268 if (ret_val)
2269 goto release;
d3738bb8 2270
c3a0dce3
DE		 2271 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2272 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
d3738bb8 2273 mac_reg = er32(RAL(i));
2b6b168d
BA		 2274 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2275 (u16)(mac_reg & 0xFFFF));
2276 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2277 (u16)((mac_reg >> 16) & 0xFFFF));
2278
d3738bb8 2279 mac_reg = er32(RAH(i));
2b6b168d
BA		 2280 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2281 (u16)(mac_reg & 0xFFFF));
2282 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2283 (u16)((mac_reg & E1000_RAH_AV)
2284 >> 16));
d3738bb8 2285 }
2b6b168d
BA		 2286
2287 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2288
2289release:
2290 hw->phy.ops.release(hw);
d3738bb8
BA		 2291}
2292
d3738bb8
BA		 2293/**
2294 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2295 * with 82579 PHY
2296 * @hw: pointer to the HW structure
2297 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2298 **/
2299s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2300{
2301 s32 ret_val = 0;
2302 u16 phy_reg, data;
2303 u32 mac_reg;
2304 u16 i;
2305
2fbe4526 2306 if (hw->mac.type < e1000_pch2lan)
5015e53a 2307 return 0;
d3738bb8
BA		 2308
2309 /* disable Rx path while enabling/disabling workaround */
2310 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2311 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2312 if (ret_val)
5015e53a 2313 return ret_val;
d3738bb8
BA		 2314
2315 if (enable) {
c3a0dce3 2316 /* Write Rx addresses (rar_entry_count for RAL/H, and
d3738bb8
BA		 2317 * SHRAL/H) and initial CRC values to the MAC
2318 */
c3a0dce3 2319 for (i = 0; i < hw->mac.rar_entry_count; i++) {
362e20ca 2320 u8 mac_addr[ETH_ALEN] = { 0 };
d3738bb8
BA		 2321 u32 addr_high, addr_low;
2322
2323 addr_high = er32(RAH(i));
2324 if (!(addr_high & E1000_RAH_AV))
2325 continue;
2326 addr_low = er32(RAL(i));
2327 mac_addr[0] = (addr_low & 0xFF);
2328 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2329 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2330 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2331 mac_addr[4] = (addr_high & 0xFF);
2332 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2333
fe46f58f 2334 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
d3738bb8
BA		 2335 }
2336
2337 /* Write Rx addresses to the PHY */
2338 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2339
2340 /* Enable jumbo frame workaround in the MAC */
2341 mac_reg = er32(FFLT_DBG);
2342 mac_reg &= ~(1 << 14);
2343 mac_reg |= (7 << 15);
2344 ew32(FFLT_DBG, mac_reg);
2345
2346 mac_reg = er32(RCTL);
2347 mac_reg |= E1000_RCTL_SECRC;
2348 ew32(RCTL, mac_reg);
2349
2350 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2351 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2352 &data);
d3738bb8 2353 if (ret_val)
5015e53a 2354 return ret_val;
d3738bb8
BA		 2355 ret_val = e1000e_write_kmrn_reg(hw,
2356 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2357 data | (1 << 0));
2358 if (ret_val)
5015e53a 2359 return ret_val;
d3738bb8 2360 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2361 E1000_KMRNCTRLSTA_HD_CTRL,
2362 &data);
d3738bb8 2363 if (ret_val)
5015e53a 2364 return ret_val;
d3738bb8
BA		 2365 data &= ~(0xF << 8);
2366 data |= (0xB << 8);
2367 ret_val = e1000e_write_kmrn_reg(hw,
2368 E1000_KMRNCTRLSTA_HD_CTRL,
2369 data);
2370 if (ret_val)
5015e53a 2371 return ret_val;
d3738bb8
BA		 2372
2373 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 2374 e1e_rphy(hw, PHY_REG(769, 23), &data);
2375 data &= ~(0x7F << 5);
2376 data |= (0x37 << 5);
2377 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2378 if (ret_val)
5015e53a 2379 return ret_val;
d3738bb8
BA		 2380 e1e_rphy(hw, PHY_REG(769, 16), &data);
2381 data &= ~(1 << 13);
d3738bb8
BA		 2382 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2383 if (ret_val)
5015e53a 2384 return ret_val;
d3738bb8
BA		 2385 e1e_rphy(hw, PHY_REG(776, 20), &data);
2386 data &= ~(0x3FF << 2);
2387 data |= (0x1A << 2);
2388 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2389 if (ret_val)
5015e53a 2390 return ret_val;
b64e9dd5 2391 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
d3738bb8 2392 if (ret_val)
5015e53a 2393 return ret_val;
d3738bb8
BA		 2394 e1e_rphy(hw, HV_PM_CTRL, &data);
2395 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2396 if (ret_val)
5015e53a 2397 return ret_val;
d3738bb8
BA		 2398 } else {
2399 /* Write MAC register values back to h/w defaults */
2400 mac_reg = er32(FFLT_DBG);
2401 mac_reg &= ~(0xF << 14);
2402 ew32(FFLT_DBG, mac_reg);
2403
2404 mac_reg = er32(RCTL);
2405 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 2406 ew32(RCTL, mac_reg);
d3738bb8
BA		 2407
2408 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2409 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2410 &data);
d3738bb8 2411 if (ret_val)
5015e53a 2412 return ret_val;
d3738bb8
BA		 2413 ret_val = e1000e_write_kmrn_reg(hw,
2414 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2415 data & ~(1 << 0));
2416 if (ret_val)
5015e53a 2417 return ret_val;
d3738bb8 2418 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2419 E1000_KMRNCTRLSTA_HD_CTRL,
2420 &data);
d3738bb8 2421 if (ret_val)
5015e53a 2422 return ret_val;
d3738bb8
BA		 2423 data &= ~(0xF << 8);
2424 data |= (0xB << 8);
2425 ret_val = e1000e_write_kmrn_reg(hw,
2426 E1000_KMRNCTRLSTA_HD_CTRL,
2427 data);
2428 if (ret_val)
5015e53a 2429 return ret_val;
d3738bb8
BA		 2430
2431 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 2432 e1e_rphy(hw, PHY_REG(769, 23), &data);
2433 data &= ~(0x7F << 5);
2434 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2435 if (ret_val)
5015e53a 2436 return ret_val;
d3738bb8 2437 e1e_rphy(hw, PHY_REG(769, 16), &data);
d3738bb8
BA		 2438 data |= (1 << 13);
2439 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2440 if (ret_val)
5015e53a 2441 return ret_val;
d3738bb8
BA		 2442 e1e_rphy(hw, PHY_REG(776, 20), &data);
2443 data &= ~(0x3FF << 2);
2444 data |= (0x8 << 2);
2445 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2446 if (ret_val)
5015e53a 2447 return ret_val;
d3738bb8
BA		 2448 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2449 if (ret_val)
5015e53a 2450 return ret_val;
d3738bb8
BA		 2451 e1e_rphy(hw, HV_PM_CTRL, &data);
2452 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2453 if (ret_val)
5015e53a 2454 return ret_val;
d3738bb8
BA		 2455 }
2456
2457 /* re-enable Rx path after enabling/disabling workaround */
5015e53a 2458 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
d3738bb8
BA		 2459}
2460
2461/**
2462 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2463 * done after every PHY reset.
2464 **/
2465static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2466{
2467 s32 ret_val = 0;
2468
2469 if (hw->mac.type != e1000_pch2lan)
5015e53a 2470 return 0;
d3738bb8
BA		 2471
2472 /* Set MDIO slow mode before any other MDIO access */
2473 ret_val = e1000_set_mdio_slow_mode_hv(hw);
8e5ab42d
BA		 2474 if (ret_val)
2475 return ret_val;
d3738bb8 2476
4d24136c
BA		 2477 ret_val = hw->phy.ops.acquire(hw);
2478 if (ret_val)
5015e53a 2479 return ret_val;
4d24136c 2480 /* set MSE higher to enable link to stay up when noise is high */
4ddc48a9 2481 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
4d24136c
BA		 2482 if (ret_val)
2483 goto release;
2484 /* drop link after 5 times MSE threshold was reached */
4ddc48a9 2485 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
4d24136c
BA		 2486release:
2487 hw->phy.ops.release(hw);
2488
d3738bb8
BA		 2489 return ret_val;
2490}
2491
831bd2e6
BA		 2492/**
2493 * e1000_k1_gig_workaround_lv - K1 Si workaround
2494 * @hw: pointer to the HW structure
2495 *
77e61146
DE		 2496 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2497 * Disable K1 in 1000Mbps and 100Mbps
831bd2e6
BA		 2498 **/
2499static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2500{
2501 s32 ret_val = 0;
2502 u16 status_reg = 0;
831bd2e6
BA		 2503
2504 if (hw->mac.type != e1000_pch2lan)
5015e53a 2505 return 0;
831bd2e6 2506
77e61146 2507 /* Set K1 beacon duration based on 10Mbs speed */
831bd2e6
BA		 2508 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2509 if (ret_val)
5015e53a 2510 return ret_val;
831bd2e6
BA		 2511
2512 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2513 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
77e61146
DE		 2514 if (status_reg &
2515 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
36ceeb43
BA		 2516 u16 pm_phy_reg;
2517
77e61146 2518 /* LV 1G/100 Packet drop issue wa */
36ceeb43
BA		 2519 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2520 if (ret_val)
2521 return ret_val;
77e61146 2522 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
36ceeb43
BA		 2523 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2524 if (ret_val)
2525 return ret_val;
0ed013e2 2526 } else {
77e61146
DE		 2527 u32 mac_reg;
2528
2529 mac_reg = er32(FEXTNVM4);
2530 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
831bd2e6 2531 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
77e61146 2532 ew32(FEXTNVM4, mac_reg);
0ed013e2 2533 }
831bd2e6
BA		 2534 }
2535
831bd2e6
BA		 2536 return ret_val;
2537}
2538
605c82ba
BA		 2539/**
2540 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2541 * @hw: pointer to the HW structure
2542 * @gate: boolean set to true to gate, false to ungate
2543 *
2544 * Gate/ungate the automatic PHY configuration via hardware; perform
2545 * the configuration via software instead.
2546 **/
2547static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2548{
2549 u32 extcnf_ctrl;
2550
2fbe4526 2551 if (hw->mac.type < e1000_pch2lan)
605c82ba
BA		 2552 return;
2553
2554 extcnf_ctrl = er32(EXTCNF_CTRL);
2555
2556 if (gate)
2557 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2558 else
2559 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2560
2561 ew32(EXTCNF_CTRL, extcnf_ctrl);
605c82ba
BA		 2562}
2563
fc0c7760
BA		 2564/**
2565 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2566 * @hw: pointer to the HW structure
2567 *
2568 * Check the appropriate indication the MAC has finished configuring the
2569 * PHY after a software reset.
2570 **/
2571static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2572{
2573 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2574
2575 /* Wait for basic configuration completes before proceeding */
2576 do {
2577 data = er32(STATUS);
2578 data &= E1000_STATUS_LAN_INIT_DONE;
ce43a216 2579 usleep_range(100, 200);
fc0c7760
BA		 2580 } while ((!data) && --loop);
2581
e921eb1a 2582 /* If basic configuration is incomplete before the above loop
fc0c7760
BA		 2583 * count reaches 0, loading the configuration from NVM will
2584 * leave the PHY in a bad state possibly resulting in no link.
2585 */
2586 if (loop == 0)
3bb99fe2 2587 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 2588
2589 /* Clear the Init Done bit for the next init event */
2590 data = er32(STATUS);
2591 data &= ~E1000_STATUS_LAN_INIT_DONE;
2592 ew32(STATUS, data);
2593}
2594
bc7f75fa 2595/**
e98cac44 2596 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 2597 * @hw: pointer to the HW structure
bc7f75fa 2598 **/
e98cac44 2599static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 2600{
f523d211
BA		 2601 s32 ret_val = 0;
2602 u16 reg;
bc7f75fa 2603
44abd5c1 2604 if (hw->phy.ops.check_reset_block(hw))
5015e53a 2605 return 0;
fc0c7760 2606
5f3eed6f 2607 /* Allow time for h/w to get to quiescent state after reset */
1bba4386 2608 usleep_range(10000, 20000);
5f3eed6f 2609
fddaa1af 2610 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 2611 switch (hw->mac.type) {
2612 case e1000_pchlan:
a4f58f54
BA		 2613 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2614 if (ret_val)
5015e53a 2615 return ret_val;
e98cac44 2616 break;
d3738bb8
BA		 2617 case e1000_pch2lan:
2618 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2619 if (ret_val)
5015e53a 2620 return ret_val;
d3738bb8 2621 break;
e98cac44
BA		 2622 default:
2623 break;
a4f58f54
BA		 2624 }
2625
3ebfc7c9
BA		 2626 /* Clear the host wakeup bit after lcd reset */
2627 if (hw->mac.type >= e1000_pchlan) {
2628 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2629 reg &= ~BM_WUC_HOST_WU_BIT;
2630 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2631 }
db2932ec 2632
f523d211
BA		 2633 /* Configure the LCD with the extended configuration region in NVM */
2634 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2635 if (ret_val)
5015e53a 2636 return ret_val;
bc7f75fa 2637
f523d211 2638 /* Configure the LCD with the OEM bits in NVM */
e98cac44 2639 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 2640
1effb45c
BA		 2641 if (hw->mac.type == e1000_pch2lan) {
2642 /* Ungate automatic PHY configuration on non-managed 82579 */
2643 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1bba4386 2644 usleep_range(10000, 20000);
1effb45c
BA		 2645 e1000_gate_hw_phy_config_ich8lan(hw, false);
2646 }
2647
2648 /* Set EEE LPI Update Timer to 200usec */
2649 ret_val = hw->phy.ops.acquire(hw);
2650 if (ret_val)
5015e53a 2651 return ret_val;
4ddc48a9
BA		 2652 ret_val = e1000_write_emi_reg_locked(hw,
2653 I82579_LPI_UPDATE_TIMER,
2654 0x1387);
1effb45c 2655 hw->phy.ops.release(hw);
605c82ba
BA		 2656 }
2657
e98cac44
BA		 2658 return ret_val;
2659}
2660
2661/**
2662 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2663 * @hw: pointer to the HW structure
2664 *
2665 * Resets the PHY
2666 * This is a function pointer entry point called by drivers
2667 * or other shared routines.
2668 **/
2669static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2670{
2671 s32 ret_val = 0;
2672
605c82ba
BA		 2673 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2674 if ((hw->mac.type == e1000_pch2lan) &&
2675 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2676 e1000_gate_hw_phy_config_ich8lan(hw, true);
2677
e98cac44
BA		 2678 ret_val = e1000e_phy_hw_reset_generic(hw);
2679 if (ret_val)
5015e53a 2680 return ret_val;
e98cac44 2681
5015e53a 2682 return e1000_post_phy_reset_ich8lan(hw);
bc7f75fa
AK		 2683}
2684
fa2ce13c
BA		 2685/**
2686 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2687 * @hw: pointer to the HW structure
2688 * @active: true to enable LPLU, false to disable
2689 *
2690 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2691 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2692 * the phy speed. This function will manually set the LPLU bit and restart
2693 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2694 * since it configures the same bit.
2695 **/
2696static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2697{
70806a7f 2698 s32 ret_val;
fa2ce13c
BA		 2699 u16 oem_reg;
2700
2701 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2702 if (ret_val)
5015e53a 2703 return ret_val;
fa2ce13c
BA		 2704
2705 if (active)
2706 oem_reg |= HV_OEM_BITS_LPLU;
2707 else
2708 oem_reg &= ~HV_OEM_BITS_LPLU;
2709
44abd5c1 2710 if (!hw->phy.ops.check_reset_block(hw))
464c85e3
BA		 2711 oem_reg |= HV_OEM_BITS_RESTART_AN;
2712
5015e53a 2713 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
fa2ce13c
BA		 2714}
2715
bc7f75fa
AK		 2716/**
2717 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2718 * @hw: pointer to the HW structure
564ea9bb 2719 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2720 *
2721 * Sets the LPLU D0 state according to the active flag. When
2722 * activating LPLU this function also disables smart speed
2723 * and vice versa. LPLU will not be activated unless the
2724 * device autonegotiation advertisement meets standards of
2725 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2726 * This is a function pointer entry point only called by
2727 * PHY setup routines.
2728 **/
2729static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2730{
2731 struct e1000_phy_info *phy = &hw->phy;
2732 u32 phy_ctrl;
2733 s32 ret_val = 0;
2734 u16 data;
2735
97ac8cae 2736 if (phy->type == e1000_phy_ife)
82607255 2737 return 0;
bc7f75fa
AK		 2738
2739 phy_ctrl = er32(PHY_CTRL);
2740
2741 if (active) {
2742 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2743 ew32(PHY_CTRL, phy_ctrl);
2744
60f1292f
BA		 2745 if (phy->type != e1000_phy_igp_3)
2746 return 0;
2747
e921eb1a 2748 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2749 * any PHY registers
2750 */
60f1292f 2751 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2752 e1000e_gig_downshift_workaround_ich8lan(hw);
2753
2754 /* When LPLU is enabled, we should disable SmartSpeed */
2755 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
7dbbe5d5
BA		 2756 if (ret_val)
2757 return ret_val;
bc7f75fa
AK		 2758 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2759 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2760 if (ret_val)
2761 return ret_val;
2762 } else {
2763 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2764 ew32(PHY_CTRL, phy_ctrl);
2765
60f1292f
BA		 2766 if (phy->type != e1000_phy_igp_3)
2767 return 0;
2768
e921eb1a 2769 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2770 * during Dx states where the power conservation is most
2771 * important. During driver activity we should enable
ad68076e
BA		 2772 * SmartSpeed, so performance is maintained.
2773 */
bc7f75fa
AK		 2774 if (phy->smart_speed == e1000_smart_speed_on) {
2775 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2776 &data);
bc7f75fa
AK		 2777 if (ret_val)
2778 return ret_val;
2779
2780 data |= IGP01E1000_PSCFR_SMART_SPEED;
2781 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2782 data);
bc7f75fa
AK		 2783 if (ret_val)
2784 return ret_val;
2785 } else if (phy->smart_speed == e1000_smart_speed_off) {
2786 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2787 &data);
bc7f75fa
AK		 2788 if (ret_val)
2789 return ret_val;
2790
2791 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2792 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2793 data);
bc7f75fa
AK		 2794 if (ret_val)
2795 return ret_val;
2796 }
2797 }
2798
2799 return 0;
2800}
2801
2802/**
2803 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2804 * @hw: pointer to the HW structure
564ea9bb 2805 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2806 *
2807 * Sets the LPLU D3 state according to the active flag. When
2808 * activating LPLU this function also disables smart speed
2809 * and vice versa. LPLU will not be activated unless the
2810 * device autonegotiation advertisement meets standards of
2811 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2812 * This is a function pointer entry point only called by
2813 * PHY setup routines.
2814 **/
2815static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2816{
2817 struct e1000_phy_info *phy = &hw->phy;
2818 u32 phy_ctrl;
d7eb3384 2819 s32 ret_val = 0;
bc7f75fa
AK		 2820 u16 data;
2821
2822 phy_ctrl = er32(PHY_CTRL);
2823
2824 if (!active) {
2825 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2826 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 2827
2828 if (phy->type != e1000_phy_igp_3)
2829 return 0;
2830
e921eb1a 2831 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2832 * during Dx states where the power conservation is most
2833 * important. During driver activity we should enable
ad68076e
BA		 2834 * SmartSpeed, so performance is maintained.
2835 */
bc7f75fa 2836 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 2837 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2838 &data);
bc7f75fa
AK		 2839 if (ret_val)
2840 return ret_val;
2841
2842 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2843 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2844 data);
bc7f75fa
AK		 2845 if (ret_val)
2846 return ret_val;
2847 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 2848 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2849 &data);
bc7f75fa
AK		 2850 if (ret_val)
2851 return ret_val;
2852
2853 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2854 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2855 data);
bc7f75fa
AK		 2856 if (ret_val)
2857 return ret_val;
2858 }
2859 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2860 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2861 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2862 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2863 ew32(PHY_CTRL, phy_ctrl);
2864
60f1292f
BA		 2865 if (phy->type != e1000_phy_igp_3)
2866 return 0;
2867
e921eb1a 2868 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2869 * any PHY registers
2870 */
60f1292f 2871 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2872 e1000e_gig_downshift_workaround_ich8lan(hw);
2873
2874 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 2875 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 2876 if (ret_val)
2877 return ret_val;
2878
2879 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 2880 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 2881 }
2882
d7eb3384 2883 return ret_val;
bc7f75fa
AK		 2884}
2885
f4187b56
BA		 2886/**
2887 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2888 * @hw: pointer to the HW structure
2889 * @bank: pointer to the variable that returns the active bank
2890 *
2891 * Reads signature byte from the NVM using the flash access registers.
e243455d 2892 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 2893 **/
2894static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2895{
e243455d 2896 u32 eecd;
f4187b56 2897 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 2898 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2899 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d 2900 u8 sig_byte = 0;
f71dde6a 2901 s32 ret_val;
f4187b56 2902
e243455d
BA		 2903 switch (hw->mac.type) {
2904 case e1000_ich8lan:
2905 case e1000_ich9lan:
2906 eecd = er32(EECD);
2907 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2908 E1000_EECD_SEC1VAL_VALID_MASK) {
2909 if (eecd & E1000_EECD_SEC1VAL)
2910 *bank = 1;
2911 else
2912 *bank = 0;
2913
2914 return 0;
2915 }
434f1392 2916 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
e243455d
BA		 2917 /* fall-thru */
2918 default:
2919 /* set bank to 0 in case flash read fails */
2920 *bank = 0;
2921
2922 /* Check bank 0 */
2923 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
f0ff4398 2924 &sig_byte);
e243455d
BA		 2925 if (ret_val)
2926 return ret_val;
2927 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2928 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 2929 *bank = 0;
e243455d
BA		 2930 return 0;
2931 }
f4187b56 2932
e243455d
BA		 2933 /* Check bank 1 */
2934 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
f0ff4398
BA		 2935 bank1_offset,
2936 &sig_byte);
e243455d
BA		 2937 if (ret_val)
2938 return ret_val;
2939 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2940 E1000_ICH_NVM_SIG_VALUE) {
2941 *bank = 1;
2942 return 0;
f4187b56 2943 }
e243455d 2944
3bb99fe2 2945 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 2946 return -E1000_ERR_NVM;
f4187b56 2947 }
f4187b56
BA		 2948}
2949
bc7f75fa
AK		 2950/**
2951 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2952 * @hw: pointer to the HW structure
2953 * @offset: The offset (in bytes) of the word(s) to read.
2954 * @words: Size of data to read in words
2955 * @data: Pointer to the word(s) to read at offset.
2956 *
2957 * Reads a word(s) from the NVM using the flash access registers.
2958 **/
2959static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2960 u16 *data)
2961{
2962 struct e1000_nvm_info *nvm = &hw->nvm;
2963 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2964 u32 act_offset;
148675a7 2965 s32 ret_val = 0;
f4187b56 2966 u32 bank = 0;
bc7f75fa
AK		 2967 u16 i, word;
2968
2969 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2970 (words == 0)) {
3bb99fe2 2971 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 2972 ret_val = -E1000_ERR_NVM;
2973 goto out;
bc7f75fa
AK		 2974 }
2975
94d8186a 2976 nvm->ops.acquire(hw);
bc7f75fa 2977
f4187b56 2978 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 2979 if (ret_val) {
3bb99fe2 2980 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 2981 bank = 0;
2982 }
f4187b56
BA		 2983
2984 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 2985 act_offset += offset;
2986
148675a7 2987 ret_val = 0;
bc7f75fa 2988 for (i = 0; i < words; i++) {
362e20ca
BA		 2989 if (dev_spec->shadow_ram[offset + i].modified) {
2990 data[i] = dev_spec->shadow_ram[offset + i].value;
bc7f75fa
AK		 2991 } else {
2992 ret_val = e1000_read_flash_word_ich8lan(hw,
2993 act_offset + i,
2994 &word);
2995 if (ret_val)
2996 break;
2997 data[i] = word;
2998 }
2999 }
3000
94d8186a 3001 nvm->ops.release(hw);
bc7f75fa 3002
e243455d
BA		 3003out:
3004 if (ret_val)
3bb99fe2 3005 e_dbg("NVM read error: %d\n", ret_val);
e243455d 3006
bc7f75fa
AK		 3007 return ret_val;
3008}
3009
3010/**
3011 * e1000_flash_cycle_init_ich8lan - Initialize flash
3012 * @hw: pointer to the HW structure
3013 *
3014 * This function does initial flash setup so that a new read/write/erase cycle
3015 * can be started.
3016 **/
3017static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3018{
3019 union ich8_hws_flash_status hsfsts;
3020 s32 ret_val = -E1000_ERR_NVM;
bc7f75fa
AK		 3021
3022 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3023
3024 /* Check if the flash descriptor is valid */
04499ec4 3025 if (!hsfsts.hsf_status.fldesvalid) {
434f1392 3026 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
bc7f75fa
AK		 3027 return -E1000_ERR_NVM;
3028 }
3029
3030 /* Clear FCERR and DAEL in hw status by writing 1 */
3031 hsfsts.hsf_status.flcerr = 1;
3032 hsfsts.hsf_status.dael = 1;
3033
3034 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3035
e921eb1a 3036 /* Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 3037 * bit to check against, in order to start a new cycle or
3038 * FDONE bit should be changed in the hardware so that it
489815ce 3039 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 3040 * indication whether a cycle is in progress or has been
3041 * completed.
3042 */
3043
04499ec4 3044 if (!hsfsts.hsf_status.flcinprog) {
e921eb1a 3045 /* There is no cycle running at present,
5ff5b664 3046 * so we can start a cycle.
ad68076e
BA		 3047 * Begin by setting Flash Cycle Done.
3048 */
bc7f75fa
AK		 3049 hsfsts.hsf_status.flcdone = 1;
3050 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3051 ret_val = 0;
3052 } else {
f71dde6a 3053 s32 i;
90da0669 3054
e921eb1a 3055 /* Otherwise poll for sometime so the current
ad68076e
BA		 3056 * cycle has a chance to end before giving up.
3057 */
bc7f75fa 3058 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
c8243ee0 3059 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3060 if (!hsfsts.hsf_status.flcinprog) {
bc7f75fa
AK		 3061 ret_val = 0;
3062 break;
3063 }
3064 udelay(1);
3065 }
9e2d7657 3066 if (!ret_val) {
e921eb1a 3067 /* Successful in waiting for previous cycle to timeout,
ad68076e
BA		 3068 * now set the Flash Cycle Done.
3069 */
bc7f75fa
AK		 3070 hsfsts.hsf_status.flcdone = 1;
3071 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3072 } else {
2c73e1fe 3073 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 3074 }
3075 }
3076
3077 return ret_val;
3078}
3079
3080/**
3081 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3082 * @hw: pointer to the HW structure
3083 * @timeout: maximum time to wait for completion
3084 *
3085 * This function starts a flash cycle and waits for its completion.
3086 **/
3087static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3088{
3089 union ich8_hws_flash_ctrl hsflctl;
3090 union ich8_hws_flash_status hsfsts;
bc7f75fa
AK		 3091 u32 i = 0;
3092
3093 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3094 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3095 hsflctl.hsf_ctrl.flcgo = 1;
3096 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3097
3098 /* wait till FDONE bit is set to 1 */
3099 do {
3100 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3101 if (hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 3102 break;
3103 udelay(1);
3104 } while (i++ < timeout);
3105
04499ec4 3106 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 3107 return 0;
3108
55920b5e 3109 return -E1000_ERR_NVM;
bc7f75fa
AK		 3110}
3111
3112/**
3113 * e1000_read_flash_word_ich8lan - Read word from flash
3114 * @hw: pointer to the HW structure
3115 * @offset: offset to data location
3116 * @data: pointer to the location for storing the data
3117 *
3118 * Reads the flash word at offset into data. Offset is converted
3119 * to bytes before read.
3120 **/
3121static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3122 u16 *data)
3123{
3124 /* Must convert offset into bytes. */
3125 offset <<= 1;
3126
3127 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3128}
3129
f4187b56
BA		 3130/**
3131 * e1000_read_flash_byte_ich8lan - Read byte from flash
3132 * @hw: pointer to the HW structure
3133 * @offset: The offset of the byte to read.
3134 * @data: Pointer to a byte to store the value read.
3135 *
3136 * Reads a single byte from the NVM using the flash access registers.
3137 **/
3138static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3139 u8 *data)
3140{
3141 s32 ret_val;
3142 u16 word = 0;
3143
3144 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3145 if (ret_val)
3146 return ret_val;
3147
3148 *data = (u8)word;
3149
3150 return 0;
3151}
3152
bc7f75fa
AK		 3153/**
3154 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3155 * @hw: pointer to the HW structure
3156 * @offset: The offset (in bytes) of the byte or word to read.
3157 * @size: Size of data to read, 1=byte 2=word
3158 * @data: Pointer to the word to store the value read.
3159 *
3160 * Reads a byte or word from the NVM using the flash access registers.
3161 **/
3162static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3163 u8 size, u16 *data)
3164{
3165 union ich8_hws_flash_status hsfsts;
3166 union ich8_hws_flash_ctrl hsflctl;
3167 u32 flash_linear_addr;
3168 u32 flash_data = 0;
3169 s32 ret_val = -E1000_ERR_NVM;
3170 u8 count = 0;
3171
e80bd1d1 3172 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
bc7f75fa
AK		 3173 return -E1000_ERR_NVM;
3174
f0ff4398
BA		 3175 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3176 hw->nvm.flash_base_addr);
bc7f75fa
AK		 3177
3178 do {
3179 udelay(1);
3180 /* Steps */
3181 ret_val = e1000_flash_cycle_init_ich8lan(hw);
9e2d7657 3182 if (ret_val)
bc7f75fa
AK		 3183 break;
3184
3185 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3186 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3187 hsflctl.hsf_ctrl.fldbcount = size - 1;
3188 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3189 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3190
3191 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3192
17e813ec
BA		 3193 ret_val =
3194 e1000_flash_cycle_ich8lan(hw,
3195 ICH_FLASH_READ_COMMAND_TIMEOUT);
bc7f75fa 3196
e921eb1a 3197 /* Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 3198 * and try the whole sequence a few more times, else
3199 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 3200 * least significant byte first msb to lsb
3201 */
9e2d7657 3202 if (!ret_val) {
bc7f75fa 3203 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 3204 if (size == 1)
bc7f75fa 3205 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 3206 else if (size == 2)
bc7f75fa 3207 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 3208 break;
3209 } else {
e921eb1a 3210 /* If we've gotten here, then things are probably
bc7f75fa
AK		 3211 * completely hosed, but if the error condition is
3212 * detected, it won't hurt to give it another try...
3213 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3214 */
3215 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3216 if (hsfsts.hsf_status.flcerr) {
bc7f75fa
AK		 3217 /* Repeat for some time before giving up. */
3218 continue;
04499ec4 3219 } else if (!hsfsts.hsf_status.flcdone) {
434f1392 3220 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 3221 break;
3222 }
3223 }
3224 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3225
3226 return ret_val;
3227}
3228
3229/**
3230 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3231 * @hw: pointer to the HW structure
3232 * @offset: The offset (in bytes) of the word(s) to write.
3233 * @words: Size of data to write in words
3234 * @data: Pointer to the word(s) to write at offset.
3235 *
3236 * Writes a byte or word to the NVM using the flash access registers.
3237 **/
3238static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3239 u16 *data)
3240{
3241 struct e1000_nvm_info *nvm = &hw->nvm;
3242 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 3243 u16 i;
3244
3245 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3246 (words == 0)) {
3bb99fe2 3247 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 3248 return -E1000_ERR_NVM;
3249 }
3250
94d8186a 3251 nvm->ops.acquire(hw);
ca15df58 3252
bc7f75fa 3253 for (i = 0; i < words; i++) {
362e20ca
BA		 3254 dev_spec->shadow_ram[offset + i].modified = true;
3255 dev_spec->shadow_ram[offset + i].value = data[i];
bc7f75fa
AK		 3256 }
3257
94d8186a 3258 nvm->ops.release(hw);
ca15df58 3259
bc7f75fa
AK		 3260 return 0;
3261}
3262
3263/**
3264 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3265 * @hw: pointer to the HW structure
3266 *
3267 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3268 * which writes the checksum to the shadow ram. The changes in the shadow
3269 * ram are then committed to the EEPROM by processing each bank at a time
3270 * checking for the modified bit and writing only the pending changes.
489815ce 3271 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 3272 * future writes.
3273 **/
3274static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3275{
3276 struct e1000_nvm_info *nvm = &hw->nvm;
3277 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 3278 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 3279 s32 ret_val;
3280 u16 data;
3281
3282 ret_val = e1000e_update_nvm_checksum_generic(hw);
3283 if (ret_val)
e243455d 3284 goto out;
bc7f75fa
AK		 3285
3286 if (nvm->type != e1000_nvm_flash_sw)
e243455d 3287 goto out;
bc7f75fa 3288
94d8186a 3289 nvm->ops.acquire(hw);
bc7f75fa 3290
e921eb1a 3291 /* We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 3292 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 3293 * is going to be written
3294 */
e80bd1d1 3295 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 3296 if (ret_val) {
3bb99fe2 3297 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 3298 bank = 0;
e243455d 3299 }
f4187b56
BA		 3300
3301 if (bank == 0) {
bc7f75fa
AK		 3302 new_bank_offset = nvm->flash_bank_size;
3303 old_bank_offset = 0;
e243455d 3304 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 3305 if (ret_val)
3306 goto release;
bc7f75fa
AK		 3307 } else {
3308 old_bank_offset = nvm->flash_bank_size;
3309 new_bank_offset = 0;
e243455d 3310 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 3311 if (ret_val)
3312 goto release;
bc7f75fa
AK		 3313 }
3314
3315 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
e921eb1a 3316 /* Determine whether to write the value stored
bc7f75fa 3317 * in the other NVM bank or a modified value stored
ad68076e
BA		 3318 * in the shadow RAM
3319 */
bc7f75fa
AK		 3320 if (dev_spec->shadow_ram[i].modified) {
3321 data = dev_spec->shadow_ram[i].value;
3322 } else {
e243455d 3323 ret_val = e1000_read_flash_word_ich8lan(hw, i +
f0ff4398
BA		 3324 old_bank_offset,
3325 &data);
e243455d
BA		 3326 if (ret_val)
3327 break;
bc7f75fa
AK		 3328 }
3329
e921eb1a 3330 /* If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 3331 * (15:14) are 11b until the commit has completed.
3332 * This will allow us to write 10b which indicates the
3333 * signature is valid. We want to do this after the write
3334 * has completed so that we don't mark the segment valid
ad68076e
BA		 3335 * while the write is still in progress
3336 */
bc7f75fa
AK		 3337 if (i == E1000_ICH_NVM_SIG_WORD)
3338 data |= E1000_ICH_NVM_SIG_MASK;
3339
3340 /* Convert offset to bytes. */
3341 act_offset = (i + new_bank_offset) << 1;
3342
ce43a216 3343 usleep_range(100, 200);
bc7f75fa
AK		 3344 /* Write the bytes to the new bank. */
3345 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3346 act_offset,
3347 (u8)data);
3348 if (ret_val)
3349 break;
3350
ce43a216 3351 usleep_range(100, 200);
bc7f75fa 3352 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
f0ff4398
BA		 3353 act_offset + 1,
3354 (u8)(data >> 8));
bc7f75fa
AK		 3355 if (ret_val)
3356 break;
3357 }
3358
e921eb1a 3359 /* Don't bother writing the segment valid bits if sector
ad68076e
BA		 3360 * programming failed.
3361 */
bc7f75fa 3362 if (ret_val) {
4a770358 3363 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 3364 e_dbg("Flash commit failed.\n");
9c5e209d 3365 goto release;
bc7f75fa
AK		 3366 }
3367
e921eb1a 3368 /* Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 3369 * to 10b in word 0x13 , this can be done without an
3370 * erase as well since these bits are 11 to start with
ad68076e
BA		 3371 * and we need to change bit 14 to 0b
3372 */
bc7f75fa 3373 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 3374 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 3375 if (ret_val)
3376 goto release;
3377
bc7f75fa
AK		 3378 data &= 0xBFFF;
3379 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3380 act_offset * 2 + 1,
3381 (u8)(data >> 8));
9c5e209d
BA		 3382 if (ret_val)
3383 goto release;
bc7f75fa 3384
e921eb1a 3385 /* And invalidate the previously valid segment by setting
bc7f75fa
AK		 3386 * its signature word (0x13) high_byte to 0b. This can be
3387 * done without an erase because flash erase sets all bits
ad68076e
BA		 3388 * to 1's. We can write 1's to 0's without an erase
3389 */
bc7f75fa
AK		 3390 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3391 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 3392 if (ret_val)
3393 goto release;
bc7f75fa
AK		 3394
3395 /* Great! Everything worked, we can now clear the cached entries. */
3396 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 3397 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 3398 dev_spec->shadow_ram[i].value = 0xFFFF;
3399 }
3400
9c5e209d 3401release:
94d8186a 3402 nvm->ops.release(hw);
bc7f75fa 3403
e921eb1a 3404 /* Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 3405 * until after the next adapter reset.
3406 */
9c5e209d 3407 if (!ret_val) {
e85e3639 3408 nvm->ops.reload(hw);
1bba4386 3409 usleep_range(10000, 20000);
9c5e209d 3410 }
bc7f75fa 3411
e243455d
BA		 3412out:
3413 if (ret_val)
3bb99fe2 3414 e_dbg("NVM update error: %d\n", ret_val);
e243455d 3415
bc7f75fa
AK		 3416 return ret_val;
3417}
3418
3419/**
3420 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3421 * @hw: pointer to the HW structure
3422 *
3423 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3424 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3425 * calculated, in which case we need to calculate the checksum and set bit 6.
3426 **/
3427static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3428{
3429 s32 ret_val;
3430 u16 data;
1cc7a3a1
BA		 3431 u16 word;
3432 u16 valid_csum_mask;
bc7f75fa 3433
1cc7a3a1
BA		 3434 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3435 * the checksum needs to be fixed. This bit is an indication that
3436 * the NVM was prepared by OEM software and did not calculate
3437 * the checksum...a likely scenario.
bc7f75fa 3438 */
1cc7a3a1
BA		 3439 switch (hw->mac.type) {
3440 case e1000_pch_lpt:
3441 word = NVM_COMPAT;
3442 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3443 break;
3444 default:
3445 word = NVM_FUTURE_INIT_WORD1;
3446 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3447 break;
3448 }
3449
3450 ret_val = e1000_read_nvm(hw, word, 1, &data);
bc7f75fa
AK		 3451 if (ret_val)
3452 return ret_val;
3453
1cc7a3a1
BA		 3454 if (!(data & valid_csum_mask)) {
3455 data |= valid_csum_mask;
3456 ret_val = e1000_write_nvm(hw, word, 1, &data);
bc7f75fa
AK		 3457 if (ret_val)
3458 return ret_val;
3459 ret_val = e1000e_update_nvm_checksum(hw);
3460 if (ret_val)
3461 return ret_val;
3462 }
3463
3464 return e1000e_validate_nvm_checksum_generic(hw);
3465}
3466
4a770358
BA		 3467/**
3468 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3469 * @hw: pointer to the HW structure
3470 *
3471 * To prevent malicious write/erase of the NVM, set it to be read-only
3472 * so that the hardware ignores all write/erase cycles of the NVM via
3473 * the flash control registers. The shadow-ram copy of the NVM will
3474 * still be updated, however any updates to this copy will not stick
3475 * across driver reloads.
3476 **/
3477void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3478{
ca15df58 3479 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 3480 union ich8_flash_protected_range pr0;
3481 union ich8_hws_flash_status hsfsts;
3482 u32 gfpreg;
4a770358 3483
94d8186a 3484 nvm->ops.acquire(hw);
4a770358
BA		 3485
3486 gfpreg = er32flash(ICH_FLASH_GFPREG);
3487
3488 /* Write-protect GbE Sector of NVM */
3489 pr0.regval = er32flash(ICH_FLASH_PR0);
3490 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3491 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3492 pr0.range.wpe = true;
3493 ew32flash(ICH_FLASH_PR0, pr0.regval);
3494
e921eb1a 3495 /* Lock down a subset of GbE Flash Control Registers, e.g.
4a770358
BA		 3496 * PR0 to prevent the write-protection from being lifted.
3497 * Once FLOCKDN is set, the registers protected by it cannot
3498 * be written until FLOCKDN is cleared by a hardware reset.
3499 */
3500 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3501 hsfsts.hsf_status.flockdn = true;
3502 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3503
94d8186a 3504 nvm->ops.release(hw);
4a770358
BA		 3505}
3506
bc7f75fa
AK		 3507/**
3508 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3509 * @hw: pointer to the HW structure
3510 * @offset: The offset (in bytes) of the byte/word to read.
3511 * @size: Size of data to read, 1=byte 2=word
3512 * @data: The byte(s) to write to the NVM.
3513 *
3514 * Writes one/two bytes to the NVM using the flash access registers.
3515 **/
3516static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3517 u8 size, u16 data)
3518{
3519 union ich8_hws_flash_status hsfsts;
3520 union ich8_hws_flash_ctrl hsflctl;
3521 u32 flash_linear_addr;
3522 u32 flash_data = 0;
3523 s32 ret_val;
3524 u8 count = 0;
3525
3526 if (size < 1 || size > 2 || data > size * 0xff ||
3527 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3528 return -E1000_ERR_NVM;
3529
f0ff4398
BA		 3530 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3531 hw->nvm.flash_base_addr);
bc7f75fa
AK		 3532
3533 do {
3534 udelay(1);
3535 /* Steps */
3536 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3537 if (ret_val)
3538 break;
3539
3540 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3541 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
362e20ca 3542 hsflctl.hsf_ctrl.fldbcount = size - 1;
bc7f75fa
AK		 3543 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3544 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3545
3546 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3547
3548 if (size == 1)
3549 flash_data = (u32)data & 0x00FF;
3550 else
3551 flash_data = (u32)data;
3552
3553 ew32flash(ICH_FLASH_FDATA0, flash_data);
3554
e921eb1a 3555 /* check if FCERR is set to 1 , if set to 1, clear it
ad68076e
BA		 3556 * and try the whole sequence a few more times else done
3557 */
17e813ec
BA		 3558 ret_val =
3559 e1000_flash_cycle_ich8lan(hw,
3560 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
bc7f75fa
AK		 3561 if (!ret_val)
3562 break;
3563
e921eb1a 3564 /* If we're here, then things are most likely
bc7f75fa
AK		 3565 * completely hosed, but if the error condition
3566 * is detected, it won't hurt to give it another
3567 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3568 */
3569 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3570 if (hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 3571 /* Repeat for some time before giving up. */
3572 continue;
04499ec4 3573 if (!hsfsts.hsf_status.flcdone) {
434f1392 3574 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 3575 break;
3576 }
3577 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3578
3579 return ret_val;
3580}
3581
3582/**
3583 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3584 * @hw: pointer to the HW structure
3585 * @offset: The index of the byte to read.
3586 * @data: The byte to write to the NVM.
3587 *
3588 * Writes a single byte to the NVM using the flash access registers.
3589 **/
3590static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3591 u8 data)
3592{
3593 u16 word = (u16)data;
3594
3595 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3596}
3597
3598/**
3599 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3600 * @hw: pointer to the HW structure
3601 * @offset: The offset of the byte to write.
3602 * @byte: The byte to write to the NVM.
3603 *
3604 * Writes a single byte to the NVM using the flash access registers.
3605 * Goes through a retry algorithm before giving up.
3606 **/
3607static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3608 u32 offset, u8 byte)
3609{
3610 s32 ret_val;
3611 u16 program_retries;
3612
3613 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3614 if (!ret_val)
3615 return ret_val;
3616
3617 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 3618 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
ce43a216 3619 usleep_range(100, 200);
bc7f75fa
AK		 3620 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3621 if (!ret_val)
3622 break;
3623 }
3624 if (program_retries == 100)
3625 return -E1000_ERR_NVM;
3626
3627 return 0;
3628}
3629
3630/**
3631 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3632 * @hw: pointer to the HW structure
3633 * @bank: 0 for first bank, 1 for second bank, etc.
3634 *
3635 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3636 * bank N is 4096 * N + flash_reg_addr.
3637 **/
3638static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3639{
3640 struct e1000_nvm_info *nvm = &hw->nvm;
3641 union ich8_hws_flash_status hsfsts;
3642 union ich8_hws_flash_ctrl hsflctl;
3643 u32 flash_linear_addr;
3644 /* bank size is in 16bit words - adjust to bytes */
3645 u32 flash_bank_size = nvm->flash_bank_size * 2;
3646 s32 ret_val;
3647 s32 count = 0;
a708dd88 3648 s32 j, iteration, sector_size;
bc7f75fa
AK		 3649
3650 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3651
e921eb1a 3652 /* Determine HW Sector size: Read BERASE bits of hw flash status
ad68076e
BA		 3653 * register
3654 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 3655 * consecutive sectors. The start index for the nth Hw sector
3656 * can be calculated as = bank * 4096 + n * 256
3657 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3658 * The start index for the nth Hw sector can be calculated
3659 * as = bank * 4096
3660 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3661 * (ich9 only, otherwise error condition)
3662 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3663 */
3664 switch (hsfsts.hsf_status.berasesz) {
3665 case 0:
3666 /* Hw sector size 256 */
3667 sector_size = ICH_FLASH_SEG_SIZE_256;
3668 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3669 break;
3670 case 1:
3671 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 3672 iteration = 1;
bc7f75fa
AK		 3673 break;
3674 case 2:
148675a7
BA		 3675 sector_size = ICH_FLASH_SEG_SIZE_8K;
3676 iteration = 1;
bc7f75fa
AK		 3677 break;
3678 case 3:
3679 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 3680 iteration = 1;
bc7f75fa
AK		 3681 break;
3682 default:
3683 return -E1000_ERR_NVM;
3684 }
3685
3686 /* Start with the base address, then add the sector offset. */
3687 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 3688 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa 3689
53aa82da 3690 for (j = 0; j < iteration; j++) {
bc7f75fa 3691 do {
17e813ec
BA		 3692 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3693
bc7f75fa
AK		 3694 /* Steps */
3695 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3696 if (ret_val)
3697 return ret_val;
3698
e921eb1a 3699 /* Write a value 11 (block Erase) in Flash
ad68076e
BA		 3700 * Cycle field in hw flash control
3701 */
bc7f75fa
AK		 3702 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3703 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3704 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3705
e921eb1a 3706 /* Write the last 24 bits of an index within the
bc7f75fa
AK		 3707 * block into Flash Linear address field in Flash
3708 * Address.
3709 */
3710 flash_linear_addr += (j * sector_size);
3711 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3712
17e813ec 3713 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
9e2d7657 3714 if (!ret_val)
bc7f75fa
AK		 3715 break;
3716
e921eb1a 3717 /* Check if FCERR is set to 1. If 1,
bc7f75fa 3718 * clear it and try the whole sequence
ad68076e
BA		 3719 * a few more times else Done
3720 */
bc7f75fa 3721 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3722 if (hsfsts.hsf_status.flcerr)
ad68076e 3723 /* repeat for some time before giving up */
bc7f75fa 3724 continue;
04499ec4 3725 else if (!hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 3726 return ret_val;
3727 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3728 }
3729
3730 return 0;
3731}
3732
3733/**
3734 * e1000_valid_led_default_ich8lan - Set the default LED settings
3735 * @hw: pointer to the HW structure
3736 * @data: Pointer to the LED settings
3737 *
3738 * Reads the LED default settings from the NVM to data. If the NVM LED
3739 * settings is all 0's or F's, set the LED default to a valid LED default
3740 * setting.
3741 **/
3742static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3743{
3744 s32 ret_val;
3745
3746 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3747 if (ret_val) {
3bb99fe2 3748 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 3749 return ret_val;
3750 }
3751
e5fe2541 3752 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
bc7f75fa
AK		 3753 *data = ID_LED_DEFAULT_ICH8LAN;
3754
3755 return 0;
3756}
3757
a4f58f54
BA		 3758/**
3759 * e1000_id_led_init_pchlan - store LED configurations
3760 * @hw: pointer to the HW structure
3761 *
3762 * PCH does not control LEDs via the LEDCTL register, rather it uses
3763 * the PHY LED configuration register.
3764 *
3765 * PCH also does not have an "always on" or "always off" mode which
3766 * complicates the ID feature. Instead of using the "on" mode to indicate
d1964eb1 3767 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
a4f58f54
BA		 3768 * use "link_up" mode. The LEDs will still ID on request if there is no
3769 * link based on logic in e1000_led_[on|off]_pchlan().
3770 **/
3771static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3772{
3773 struct e1000_mac_info *mac = &hw->mac;
3774 s32 ret_val;
3775 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3776 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3777 u16 data, i, temp, shift;
3778
3779 /* Get default ID LED modes */
3780 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3781 if (ret_val)
5015e53a 3782 return ret_val;
a4f58f54
BA		 3783
3784 mac->ledctl_default = er32(LEDCTL);
3785 mac->ledctl_mode1 = mac->ledctl_default;
3786 mac->ledctl_mode2 = mac->ledctl_default;
3787
3788 for (i = 0; i < 4; i++) {
3789 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3790 shift = (i * 5);
3791 switch (temp) {
3792 case ID_LED_ON1_DEF2:
3793 case ID_LED_ON1_ON2:
3794 case ID_LED_ON1_OFF2:
3795 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3796 mac->ledctl_mode1 |= (ledctl_on << shift);
3797 break;
3798 case ID_LED_OFF1_DEF2:
3799 case ID_LED_OFF1_ON2:
3800 case ID_LED_OFF1_OFF2:
3801 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3802 mac->ledctl_mode1 |= (ledctl_off << shift);
3803 break;
3804 default:
3805 /* Do nothing */
3806 break;
3807 }
3808 switch (temp) {
3809 case ID_LED_DEF1_ON2:
3810 case ID_LED_ON1_ON2:
3811 case ID_LED_OFF1_ON2:
3812 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3813 mac->ledctl_mode2 |= (ledctl_on << shift);
3814 break;
3815 case ID_LED_DEF1_OFF2:
3816 case ID_LED_ON1_OFF2:
3817 case ID_LED_OFF1_OFF2:
3818 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3819 mac->ledctl_mode2 |= (ledctl_off << shift);
3820 break;
3821 default:
3822 /* Do nothing */
3823 break;
3824 }
3825 }
3826
5015e53a 3827 return 0;
a4f58f54
BA		 3828}
3829
bc7f75fa
AK		 3830/**
3831 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3832 * @hw: pointer to the HW structure
3833 *
3834 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3835 * register, so the the bus width is hard coded.
3836 **/
3837static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3838{
3839 struct e1000_bus_info *bus = &hw->bus;
3840 s32 ret_val;
3841
3842 ret_val = e1000e_get_bus_info_pcie(hw);
3843
e921eb1a 3844 /* ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 3845 * a configuration space, but do not contain
3846 * PCI Express Capability registers, so bus width
3847 * must be hardcoded.
3848 */
3849 if (bus->width == e1000_bus_width_unknown)
3850 bus->width = e1000_bus_width_pcie_x1;
3851
3852 return ret_val;
3853}
3854
3855/**
3856 * e1000_reset_hw_ich8lan - Reset the hardware
3857 * @hw: pointer to the HW structure
3858 *
3859 * Does a full reset of the hardware which includes a reset of the PHY and
3860 * MAC.
3861 **/
3862static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3863{
1d5846b9 3864 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
62bc813e
BA		 3865 u16 kum_cfg;
3866 u32 ctrl, reg;
bc7f75fa
AK		 3867 s32 ret_val;
3868
e921eb1a 3869 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 3870 * on the last TLP read/write transaction when MAC is reset.
3871 */
3872 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 3873 if (ret_val)
3bb99fe2 3874 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 3875
3bb99fe2 3876 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 3877 ew32(IMC, 0xffffffff);
3878
e921eb1a 3879 /* Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 3880 * any pending transactions to complete before we hit the MAC
3881 * with the global reset.
3882 */
3883 ew32(RCTL, 0);
3884 ew32(TCTL, E1000_TCTL_PSP);
3885 e1e_flush();
3886
1bba4386 3887 usleep_range(10000, 20000);
bc7f75fa
AK		 3888
3889 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3890 if (hw->mac.type == e1000_ich8lan) {
3891 /* Set Tx and Rx buffer allocation to 8k apiece. */
3892 ew32(PBA, E1000_PBA_8K);
3893 /* Set Packet Buffer Size to 16k. */
3894 ew32(PBS, E1000_PBS_16K);
3895 }
3896
1d5846b9 3897 if (hw->mac.type == e1000_pchlan) {
62bc813e
BA		 3898 /* Save the NVM K1 bit setting */
3899 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
1d5846b9
BA		 3900 if (ret_val)
3901 return ret_val;
3902
62bc813e 3903 if (kum_cfg & E1000_NVM_K1_ENABLE)
1d5846b9
BA		 3904 dev_spec->nvm_k1_enabled = true;
3905 else
3906 dev_spec->nvm_k1_enabled = false;
3907 }
3908
bc7f75fa
AK		 3909 ctrl = er32(CTRL);
3910
44abd5c1 3911 if (!hw->phy.ops.check_reset_block(hw)) {
e921eb1a 3912 /* Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 3913 * time to make sure the interface between MAC and the
3914 * external PHY is reset.
3915 */
3916 ctrl |= E1000_CTRL_PHY_RST;
605c82ba 3917
e921eb1a 3918 /* Gate automatic PHY configuration by hardware on
605c82ba
BA		 3919 * non-managed 82579
3920 */
3921 if ((hw->mac.type == e1000_pch2lan) &&
3922 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3923 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 3924 }
3925 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 3926 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa 3927 ew32(CTRL, (ctrl | E1000_CTRL_RST));
945a5151 3928 /* cannot issue a flush here because it hangs the hardware */
bc7f75fa
AK		 3929 msleep(20);
3930
62bc813e
BA		 3931 /* Set Phy Config Counter to 50msec */
3932 if (hw->mac.type == e1000_pch2lan) {
3933 reg = er32(FEXTNVM3);
3934 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3935 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3936 ew32(FEXTNVM3, reg);
3937 }
3938
fc0c7760 3939 if (!ret_val)
a90b412c 3940 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
37f40239 3941
e98cac44 3942 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 3943 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44 3944 if (ret_val)
5015e53a 3945 return ret_val;
fc0c7760 3946
e98cac44 3947 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211 3948 if (ret_val)
5015e53a 3949 return ret_val;
f523d211 3950 }
e98cac44 3951
e921eb1a 3952 /* For PCH, this write will make sure that any noise
7d3cabbc
BA		 3953 * will be detected as a CRC error and be dropped rather than show up
3954 * as a bad packet to the DMA engine.
3955 */
3956 if (hw->mac.type == e1000_pchlan)
3957 ew32(CRC_OFFSET, 0x65656565);
3958
bc7f75fa 3959 ew32(IMC, 0xffffffff);
dd93f95e 3960 er32(ICR);
bc7f75fa 3961
62bc813e
BA		 3962 reg = er32(KABGTXD);
3963 reg |= E1000_KABGTXD_BGSQLBIAS;
3964 ew32(KABGTXD, reg);
bc7f75fa 3965
5015e53a 3966 return 0;
bc7f75fa
AK		 3967}
3968
3969/**
3970 * e1000_init_hw_ich8lan - Initialize the hardware
3971 * @hw: pointer to the HW structure
3972 *
3973 * Prepares the hardware for transmit and receive by doing the following:
3974 * - initialize hardware bits
3975 * - initialize LED identification
3976 * - setup receive address registers
3977 * - setup flow control
489815ce 3978 * - setup transmit descriptors
bc7f75fa
AK		 3979 * - clear statistics
3980 **/
3981static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3982{
3983 struct e1000_mac_info *mac = &hw->mac;
3984 u32 ctrl_ext, txdctl, snoop;
3985 s32 ret_val;
3986 u16 i;
3987
3988 e1000_initialize_hw_bits_ich8lan(hw);
3989
3990 /* Initialize identification LED */
a4f58f54 3991 ret_val = mac->ops.id_led_init(hw);
33550cec 3992 /* An error is not fatal and we should not stop init due to this */
de39b752 3993 if (ret_val)
3bb99fe2 3994 e_dbg("Error initializing identification LED\n");
bc7f75fa
AK		 3995
3996 /* Setup the receive address. */
3997 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3998
3999 /* Zero out the Multicast HASH table */
3bb99fe2 4000 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 4001 for (i = 0; i < mac->mta_reg_count; i++)
4002 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4003
e921eb1a 4004 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3ebfc7c9 4005 * the ME. Disable wakeup by clearing the host wakeup bit.
fc0c7760
BA		 4006 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4007 */
4008 if (hw->phy.type == e1000_phy_82578) {
3ebfc7c9
BA		 4009 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4010 i &= ~BM_WUC_HOST_WU_BIT;
4011 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fc0c7760
BA		 4012 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4013 if (ret_val)
4014 return ret_val;
4015 }
4016
bc7f75fa 4017 /* Setup link and flow control */
1a46b40f 4018 ret_val = mac->ops.setup_link(hw);
bc7f75fa
AK		 4019
4020 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 4021 txdctl = er32(TXDCTL(0));
f0ff4398
BA		 4022 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4023 E1000_TXDCTL_FULL_TX_DESC_WB);
4024 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4025 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f
JK		 4026 ew32(TXDCTL(0), txdctl);
4027 txdctl = er32(TXDCTL(1));
f0ff4398
BA		 4028 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4029 E1000_TXDCTL_FULL_TX_DESC_WB);
4030 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4031 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f 4032 ew32(TXDCTL(1), txdctl);
bc7f75fa 4033
e921eb1a 4034 /* ICH8 has opposite polarity of no_snoop bits.
ad68076e
BA		 4035 * By default, we should use snoop behavior.
4036 */
bc7f75fa
AK		 4037 if (mac->type == e1000_ich8lan)
4038 snoop = PCIE_ICH8_SNOOP_ALL;
4039 else
53aa82da 4040 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
bc7f75fa
AK		 4041 e1000e_set_pcie_no_snoop(hw, snoop);
4042
4043 ctrl_ext = er32(CTRL_EXT);
4044 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4045 ew32(CTRL_EXT, ctrl_ext);
4046
e921eb1a 4047 /* Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 4048 * important that we do this after we have tried to establish link
4049 * because the symbol error count will increment wildly if there
4050 * is no link.
4051 */
4052 e1000_clear_hw_cntrs_ich8lan(hw);
4053
e561a705 4054 return ret_val;
bc7f75fa 4055}
fc830b78 4056
bc7f75fa
AK		 4057/**
4058 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4059 * @hw: pointer to the HW structure
4060 *
4061 * Sets/Clears required hardware bits necessary for correctly setting up the
4062 * hardware for transmit and receive.
4063 **/
4064static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4065{
4066 u32 reg;
4067
4068 /* Extended Device Control */
4069 reg = er32(CTRL_EXT);
4070 reg |= (1 << 22);
a4f58f54
BA		 4071 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4072 if (hw->mac.type >= e1000_pchlan)
4073 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 4074 ew32(CTRL_EXT, reg);
4075
4076 /* Transmit Descriptor Control 0 */
e9ec2c0f 4077 reg = er32(TXDCTL(0));
bc7f75fa 4078 reg |= (1 << 22);
e9ec2c0f 4079 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 4080
4081 /* Transmit Descriptor Control 1 */
e9ec2c0f 4082 reg = er32(TXDCTL(1));
bc7f75fa 4083 reg |= (1 << 22);
e9ec2c0f 4084 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 4085
4086 /* Transmit Arbitration Control 0 */
e9ec2c0f 4087 reg = er32(TARC(0));
bc7f75fa
AK		 4088 if (hw->mac.type == e1000_ich8lan)
4089 reg |= (1 << 28) | (1 << 29);
4090 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 4091 ew32(TARC(0), reg);
bc7f75fa
AK		 4092
4093 /* Transmit Arbitration Control 1 */
e9ec2c0f 4094 reg = er32(TARC(1));
bc7f75fa
AK		 4095 if (er32(TCTL) & E1000_TCTL_MULR)
4096 reg &= ~(1 << 28);
4097 else
4098 reg |= (1 << 28);
4099 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 4100 ew32(TARC(1), reg);
bc7f75fa
AK		 4101
4102 /* Device Status */
4103 if (hw->mac.type == e1000_ich8lan) {
4104 reg = er32(STATUS);
4105 reg &= ~(1 << 31);
4106 ew32(STATUS, reg);
4107 }
a80483d3 4108
e921eb1a 4109 /* work-around descriptor data corruption issue during nfs v2 udp
a80483d3
JB		 4110 * traffic, just disable the nfs filtering capability
4111 */
4112 reg = er32(RFCTL);
4113 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
f6bd5577 4114
e921eb1a 4115 /* Disable IPv6 extension header parsing because some malformed
f6bd5577
MV		 4116 * IPv6 headers can hang the Rx.
4117 */
4118 if (hw->mac.type == e1000_ich8lan)
4119 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
a80483d3 4120 ew32(RFCTL, reg);
94fb848b
BA		 4121
4122 /* Enable ECC on Lynxpoint */
4123 if (hw->mac.type == e1000_pch_lpt) {
4124 reg = er32(PBECCSTS);
4125 reg |= E1000_PBECCSTS_ECC_ENABLE;
4126 ew32(PBECCSTS, reg);
4127
4128 reg = er32(CTRL);
4129 reg |= E1000_CTRL_MEHE;
4130 ew32(CTRL, reg);
4131 }
bc7f75fa
AK		 4132}
4133
4134/**
4135 * e1000_setup_link_ich8lan - Setup flow control and link settings
4136 * @hw: pointer to the HW structure
4137 *
4138 * Determines which flow control settings to use, then configures flow
4139 * control. Calls the appropriate media-specific link configuration
4140 * function. Assuming the adapter has a valid link partner, a valid link
4141 * should be established. Assumes the hardware has previously been reset
4142 * and the transmitter and receiver are not enabled.
4143 **/
4144static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4145{
bc7f75fa
AK		 4146 s32 ret_val;
4147
44abd5c1 4148 if (hw->phy.ops.check_reset_block(hw))
bc7f75fa
AK		 4149 return 0;
4150
e921eb1a 4151 /* ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 4152 * the default flow control setting, so we explicitly
4153 * set it to full.
4154 */
37289d9c
BA		 4155 if (hw->fc.requested_mode == e1000_fc_default) {
4156 /* Workaround h/w hang when Tx flow control enabled */
4157 if (hw->mac.type == e1000_pchlan)
4158 hw->fc.requested_mode = e1000_fc_rx_pause;
4159 else
4160 hw->fc.requested_mode = e1000_fc_full;
4161 }
bc7f75fa 4162
e921eb1a 4163 /* Save off the requested flow control mode for use later. Depending
5c48ef3e
BA		 4164 * on the link partner's capabilities, we may or may not use this mode.
4165 */
4166 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 4167
17e813ec 4168 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
bc7f75fa
AK		 4169
4170 /* Continue to configure the copper link. */
944ce011 4171 ret_val = hw->mac.ops.setup_physical_interface(hw);
bc7f75fa
AK		 4172 if (ret_val)
4173 return ret_val;
4174
318a94d6 4175 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 4176 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 4177 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 4178 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 4179 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 4180 ew32(FCRTV_PCH, hw->fc.refresh_time);
4181
482fed85
BA		 4182 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4183 hw->fc.pause_time);
a4f58f54
BA		 4184 if (ret_val)
4185 return ret_val;
4186 }
bc7f75fa
AK		 4187
4188 return e1000e_set_fc_watermarks(hw);
4189}
4190
4191/**
4192 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4193 * @hw: pointer to the HW structure
4194 *
4195 * Configures the kumeran interface to the PHY to wait the appropriate time
4196 * when polling the PHY, then call the generic setup_copper_link to finish
4197 * configuring the copper link.
4198 **/
4199static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4200{
4201 u32 ctrl;
4202 s32 ret_val;
4203 u16 reg_data;
4204
4205 ctrl = er32(CTRL);
4206 ctrl |= E1000_CTRL_SLU;
4207 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4208 ew32(CTRL, ctrl);
4209
e921eb1a 4210 /* Set the mac to wait the maximum time between each iteration
bc7f75fa 4211 * and increase the max iterations when polling the phy;
ad68076e
BA		 4212 * this fixes erroneous timeouts at 10Mbps.
4213 */
07818950 4214 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 4215 if (ret_val)
4216 return ret_val;
07818950 4217 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 4218 &reg_data);
bc7f75fa
AK		 4219 if (ret_val)
4220 return ret_val;
4221 reg_data |= 0x3F;
07818950 4222 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 4223 reg_data);
bc7f75fa
AK		 4224 if (ret_val)
4225 return ret_val;
4226
a4f58f54
BA		 4227 switch (hw->phy.type) {
4228 case e1000_phy_igp_3:
bc7f75fa
AK		 4229 ret_val = e1000e_copper_link_setup_igp(hw);
4230 if (ret_val)
4231 return ret_val;
a4f58f54
BA		 4232 break;
4233 case e1000_phy_bm:
4234 case e1000_phy_82578:
97ac8cae
BA		 4235 ret_val = e1000e_copper_link_setup_m88(hw);
4236 if (ret_val)
4237 return ret_val;
a4f58f54
BA		 4238 break;
4239 case e1000_phy_82577:
d3738bb8 4240 case e1000_phy_82579:
a4f58f54
BA		 4241 ret_val = e1000_copper_link_setup_82577(hw);
4242 if (ret_val)
4243 return ret_val;
4244 break;
4245 case e1000_phy_ife:
482fed85 4246 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
97ac8cae
BA		 4247 if (ret_val)
4248 return ret_val;
4249
4250 reg_data &= ~IFE_PMC_AUTO_MDIX;
4251
4252 switch (hw->phy.mdix) {
4253 case 1:
4254 reg_data &= ~IFE_PMC_FORCE_MDIX;
4255 break;
4256 case 2:
4257 reg_data |= IFE_PMC_FORCE_MDIX;
4258 break;
4259 case 0:
4260 default:
4261 reg_data |= IFE_PMC_AUTO_MDIX;
4262 break;
4263 }
482fed85 4264 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
97ac8cae
BA		 4265 if (ret_val)
4266 return ret_val;
a4f58f54
BA		 4267 break;
4268 default:
4269 break;
97ac8cae 4270 }
3fa82936 4271
bc7f75fa
AK		 4272 return e1000e_setup_copper_link(hw);
4273}
4274
ea8179a7
BA		 4275/**
4276 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
4277 * @hw: pointer to the HW structure
4278 *
4279 * Calls the PHY specific link setup function and then calls the
4280 * generic setup_copper_link to finish configuring the link for
4281 * Lynxpoint PCH devices
4282 **/
4283static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
4284{
4285 u32 ctrl;
4286 s32 ret_val;
4287
4288 ctrl = er32(CTRL);
4289 ctrl |= E1000_CTRL_SLU;
4290 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4291 ew32(CTRL, ctrl);
4292
4293 ret_val = e1000_copper_link_setup_82577(hw);
4294 if (ret_val)
4295 return ret_val;
4296
4297 return e1000e_setup_copper_link(hw);
4298}
4299
bc7f75fa
AK		 4300/**
4301 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4302 * @hw: pointer to the HW structure
4303 * @speed: pointer to store current link speed
4304 * @duplex: pointer to store the current link duplex
4305 *
ad68076e 4306 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 4307 * information and then calls the Kumeran lock loss workaround for links at
4308 * gigabit speeds.
4309 **/
4310static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4311 u16 *duplex)
4312{
4313 s32 ret_val;
4314
4315 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4316 if (ret_val)
4317 return ret_val;
4318
4319 if ((hw->mac.type == e1000_ich8lan) &&
e5fe2541 4320 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
bc7f75fa
AK		 4321 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4322 }
4323
4324 return ret_val;
4325}
4326
4327/**
4328 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4329 * @hw: pointer to the HW structure
4330 *
4331 * Work-around for 82566 Kumeran PCS lock loss:
4332 * On link status change (i.e. PCI reset, speed change) and link is up and
4333 * speed is gigabit-
4334 * 0) if workaround is optionally disabled do nothing
4335 * 1) wait 1ms for Kumeran link to come up
4336 * 2) check Kumeran Diagnostic register PCS lock loss bit
4337 * 3) if not set the link is locked (all is good), otherwise...
4338 * 4) reset the PHY
4339 * 5) repeat up to 10 times
4340 * Note: this is only called for IGP3 copper when speed is 1gb.
4341 **/
4342static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4343{
4344 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4345 u32 phy_ctrl;
4346 s32 ret_val;
4347 u16 i, data;
4348 bool link;
4349
4350 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4351 return 0;
4352
e921eb1a 4353 /* Make sure link is up before proceeding. If not just return.
bc7f75fa 4354 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 4355 * stability
4356 */
bc7f75fa
AK		 4357 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4358 if (!link)
4359 return 0;
4360
4361 for (i = 0; i < 10; i++) {
4362 /* read once to clear */
4363 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4364 if (ret_val)
4365 return ret_val;
4366 /* and again to get new status */
4367 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4368 if (ret_val)
4369 return ret_val;
4370
4371 /* check for PCS lock */
4372 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4373 return 0;
4374
4375 /* Issue PHY reset */
4376 e1000_phy_hw_reset(hw);
4377 mdelay(5);
4378 }
4379 /* Disable GigE link negotiation */
4380 phy_ctrl = er32(PHY_CTRL);
4381 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4382 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4383 ew32(PHY_CTRL, phy_ctrl);
4384
e921eb1a 4385 /* Call gig speed drop workaround on Gig disable before accessing
ad68076e
BA		 4386 * any PHY registers
4387 */
bc7f75fa
AK		 4388 e1000e_gig_downshift_workaround_ich8lan(hw);
4389
4390 /* unable to acquire PCS lock */
4391 return -E1000_ERR_PHY;
4392}
4393
4394/**
6e3c8075 4395 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 4396 * @hw: pointer to the HW structure
489815ce 4397 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 4398 *
564ea9bb
BA		 4399 * If ICH8, set the current Kumeran workaround state (enabled - true
4400 * /disabled - false).
bc7f75fa
AK		 4401 **/
4402void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
17e813ec 4403 bool state)
bc7f75fa
AK		 4404{
4405 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4406
4407 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 4408 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 4409 return;
4410 }
4411
4412 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4413}
4414
4415/**
4416 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4417 * @hw: pointer to the HW structure
4418 *
4419 * Workaround for 82566 power-down on D3 entry:
4420 * 1) disable gigabit link
4421 * 2) write VR power-down enable
4422 * 3) read it back
4423 * Continue if successful, else issue LCD reset and repeat
4424 **/
4425void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4426{
4427 u32 reg;
4428 u16 data;
e80bd1d1 4429 u8 retry = 0;
bc7f75fa
AK		 4430
4431 if (hw->phy.type != e1000_phy_igp_3)
4432 return;
4433
4434 /* Try the workaround twice (if needed) */
4435 do {
4436 /* Disable link */
4437 reg = er32(PHY_CTRL);
4438 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4439 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4440 ew32(PHY_CTRL, reg);
4441
e921eb1a 4442 /* Call gig speed drop workaround on Gig disable before
ad68076e
BA		 4443 * accessing any PHY registers
4444 */
bc7f75fa
AK		 4445 if (hw->mac.type == e1000_ich8lan)
4446 e1000e_gig_downshift_workaround_ich8lan(hw);
4447
4448 /* Write VR power-down enable */
4449 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4450 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4451 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4452
4453 /* Read it back and test */
4454 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4455 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4456 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4457 break;
4458
4459 /* Issue PHY reset and repeat at most one more time */
4460 reg = er32(CTRL);
4461 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4462 retry++;
4463 } while (retry);
4464}
4465
4466/**
4467 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4468 * @hw: pointer to the HW structure
4469 *
4470 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 4471 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 4472 * 1) Set Kumeran Near-end loopback
4473 * 2) Clear Kumeran Near-end loopback
462d5994 4474 * Should only be called for ICH8[m] devices with any 1G Phy.
bc7f75fa
AK		 4475 **/
4476void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4477{
4478 s32 ret_val;
4479 u16 reg_data;
4480
462d5994 4481 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
bc7f75fa
AK		 4482 return;
4483
4484 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 4485 &reg_data);
bc7f75fa
AK		 4486 if (ret_val)
4487 return;
4488 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4489 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 4490 reg_data);
bc7f75fa
AK		 4491 if (ret_val)
4492 return;
4493 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
7dbbe5d5 4494 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
bc7f75fa
AK		 4495}
4496
97ac8cae 4497/**
99730e4c 4498 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
97ac8cae
BA		 4499 * @hw: pointer to the HW structure
4500 *
4501 * During S0 to Sx transition, it is possible the link remains at gig
4502 * instead of negotiating to a lower speed. Before going to Sx, set
c077a906
BA		 4503 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4504 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4505 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4506 * needs to be written.
2fbe4526
BA		 4507 * Parts that support (and are linked to a partner which support) EEE in
4508 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4509 * than 10Mbps w/o EEE.
97ac8cae 4510 **/
99730e4c 4511void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
97ac8cae 4512{
2fbe4526 4513 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
97ac8cae 4514 u32 phy_ctrl;
8395ae83 4515 s32 ret_val;
97ac8cae 4516
17f085df 4517 phy_ctrl = er32(PHY_CTRL);
c077a906 4518 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
e08f626b 4519
2fbe4526 4520 if (hw->phy.type == e1000_phy_i217) {
e08f626b
BA		 4521 u16 phy_reg, device_id = hw->adapter->pdev->device;
4522
4523 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 4524 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4525 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4526 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
e08f626b
BA		 4527 u32 fextnvm6 = er32(FEXTNVM6);
4528
4529 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4530 }
2fbe4526
BA		 4531
4532 ret_val = hw->phy.ops.acquire(hw);
4533 if (ret_val)
4534 goto out;
4535
4536 if (!dev_spec->eee_disable) {
4537 u16 eee_advert;
4538
4ddc48a9
BA		 4539 ret_val =
4540 e1000_read_emi_reg_locked(hw,
4541 I217_EEE_ADVERTISEMENT,
4542 &eee_advert);
2fbe4526
BA		 4543 if (ret_val)
4544 goto release;
2fbe4526 4545
e921eb1a 4546 /* Disable LPLU if both link partners support 100BaseT
2fbe4526
BA		 4547 * EEE and 100Full is advertised on both ends of the
4548 * link.
4549 */
3d4d5755 4550 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
2fbe4526 4551 (dev_spec->eee_lp_ability &
3d4d5755 4552 I82579_EEE_100_SUPPORTED) &&
2fbe4526
BA		 4553 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4554 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4555 E1000_PHY_CTRL_NOND0A_LPLU);
4556 }
4557
e921eb1a 4558 /* For i217 Intel Rapid Start Technology support,
2fbe4526
BA		 4559 * when the system is going into Sx and no manageability engine
4560 * is present, the driver must configure proxy to reset only on
4561 * power good. LPI (Low Power Idle) state must also reset only
4562 * on power good, as well as the MTA (Multicast table array).
4563 * The SMBus release must also be disabled on LCD reset.
4564 */
4565 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2fbe4526
BA		 4566 /* Enable proxy to reset only on power good. */
4567 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4568 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4569 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4570
e921eb1a 4571 /* Set bit enable LPI (EEE) to reset only on
2fbe4526
BA		 4572 * power good.
4573 */
4574 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
6d7407bf 4575 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
2fbe4526
BA		 4576 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4577
4578 /* Disable the SMB release on LCD reset. */
4579 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
6d7407bf 4580 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4581 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4582 }
4583
e921eb1a 4584 /* Enable MTA to reset for Intel Rapid Start Technology
2fbe4526
BA		 4585 * Support
4586 */
4587 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
6d7407bf 4588 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4589 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4590
4591release:
4592 hw->phy.ops.release(hw);
4593 }
4594out:
17f085df 4595 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 4596
462d5994
BA		 4597 if (hw->mac.type == e1000_ich8lan)
4598 e1000e_gig_downshift_workaround_ich8lan(hw);
4599
8395ae83 4600 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 4601 e1000_oem_bits_config_ich8lan(hw, false);
92fe1733
BA		 4602
4603 /* Reset PHY to activate OEM bits on 82577/8 */
4604 if (hw->mac.type == e1000_pchlan)
4605 e1000e_phy_hw_reset_generic(hw);
4606
8395ae83
BA		 4607 ret_val = hw->phy.ops.acquire(hw);
4608 if (ret_val)
4609 return;
4610 e1000_write_smbus_addr(hw);
4611 hw->phy.ops.release(hw);
4612 }
97ac8cae
BA		 4613}
4614
99730e4c
BA		 4615/**
4616 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4617 * @hw: pointer to the HW structure
4618 *
4619 * During Sx to S0 transitions on non-managed devices or managed devices
4620 * on which PHY resets are not blocked, if the PHY registers cannot be
4621 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4622 * the PHY.
2fbe4526 4623 * On i217, setup Intel Rapid Start Technology.
99730e4c
BA		 4624 **/
4625void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4626{
90b82984 4627 s32 ret_val;
99730e4c 4628
cb17aab9 4629 if (hw->mac.type < e1000_pch2lan)
99730e4c
BA		 4630 return;
4631
cb17aab9 4632 ret_val = e1000_init_phy_workarounds_pchlan(hw);
90b82984 4633 if (ret_val) {
cb17aab9 4634 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
90b82984
BA		 4635 return;
4636 }
2fbe4526 4637
e921eb1a 4638 /* For i217 Intel Rapid Start Technology support when the system
2fbe4526
BA		 4639 * is transitioning from Sx and no manageability engine is present
4640 * configure SMBus to restore on reset, disable proxy, and enable
4641 * the reset on MTA (Multicast table array).
4642 */
4643 if (hw->phy.type == e1000_phy_i217) {
4644 u16 phy_reg;
4645
4646 ret_val = hw->phy.ops.acquire(hw);
4647 if (ret_val) {
4648 e_dbg("Failed to setup iRST\n");
4649 return;
4650 }
4651
4652 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
e921eb1a 4653 /* Restore clear on SMB if no manageability engine
2fbe4526
BA		 4654 * is present
4655 */
4656 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4657 if (ret_val)
4658 goto release;
6d7407bf 4659 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4660 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4661
4662 /* Disable Proxy */
4663 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4664 }
4665 /* Enable reset on MTA */
4666 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4667 if (ret_val)
4668 goto release;
6d7407bf 4669 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4670 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4671release:
4672 if (ret_val)
4673 e_dbg("Error %d in resume workarounds\n", ret_val);
4674 hw->phy.ops.release(hw);
4675 }
99730e4c
BA		 4676}
4677
bc7f75fa
AK		 4678/**
4679 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4680 * @hw: pointer to the HW structure
4681 *
4682 * Return the LED back to the default configuration.
4683 **/
4684static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4685{
4686 if (hw->phy.type == e1000_phy_ife)
4687 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4688
4689 ew32(LEDCTL, hw->mac.ledctl_default);
4690 return 0;
4691}
4692
4693/**
489815ce 4694 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 4695 * @hw: pointer to the HW structure
4696 *
489815ce 4697 * Turn on the LEDs.
bc7f75fa
AK		 4698 **/
4699static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4700{
4701 if (hw->phy.type == e1000_phy_ife)
4702 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4703 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4704
4705 ew32(LEDCTL, hw->mac.ledctl_mode2);
4706 return 0;
4707}
4708
4709/**
489815ce 4710 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 4711 * @hw: pointer to the HW structure
4712 *
489815ce 4713 * Turn off the LEDs.
bc7f75fa
AK		 4714 **/
4715static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4716{
4717 if (hw->phy.type == e1000_phy_ife)
4718 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
482fed85
BA		 4719 (IFE_PSCL_PROBE_MODE |
4720 IFE_PSCL_PROBE_LEDS_OFF));
bc7f75fa
AK		 4721
4722 ew32(LEDCTL, hw->mac.ledctl_mode1);
4723 return 0;
4724}
4725
a4f58f54
BA		 4726/**
4727 * e1000_setup_led_pchlan - Configures SW controllable LED
4728 * @hw: pointer to the HW structure
4729 *
4730 * This prepares the SW controllable LED for use.
4731 **/
4732static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4733{
482fed85 4734 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
a4f58f54
BA		 4735}
4736
4737/**
4738 * e1000_cleanup_led_pchlan - Restore the default LED operation
4739 * @hw: pointer to the HW structure
4740 *
4741 * Return the LED back to the default configuration.
4742 **/
4743static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4744{
482fed85 4745 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
a4f58f54
BA		 4746}
4747
4748/**
4749 * e1000_led_on_pchlan - Turn LEDs on
4750 * @hw: pointer to the HW structure
4751 *
4752 * Turn on the LEDs.
4753 **/
4754static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4755{
4756 u16 data = (u16)hw->mac.ledctl_mode2;
4757 u32 i, led;
4758
e921eb1a 4759 /* If no link, then turn LED on by setting the invert bit
a4f58f54
BA		 4760 * for each LED that's mode is "link_up" in ledctl_mode2.
4761 */
4762 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4763 for (i = 0; i < 3; i++) {
4764 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4765 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4766 E1000_LEDCTL_MODE_LINK_UP)
4767 continue;
4768 if (led & E1000_PHY_LED0_IVRT)
4769 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4770 else
4771 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4772 }
4773 }
4774
482fed85 4775 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4776}
4777
4778/**
4779 * e1000_led_off_pchlan - Turn LEDs off
4780 * @hw: pointer to the HW structure
4781 *
4782 * Turn off the LEDs.
4783 **/
4784static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4785{
4786 u16 data = (u16)hw->mac.ledctl_mode1;
4787 u32 i, led;
4788
e921eb1a 4789 /* If no link, then turn LED off by clearing the invert bit
a4f58f54
BA		 4790 * for each LED that's mode is "link_up" in ledctl_mode1.
4791 */
4792 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4793 for (i = 0; i < 3; i++) {
4794 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4795 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4796 E1000_LEDCTL_MODE_LINK_UP)
4797 continue;
4798 if (led & E1000_PHY_LED0_IVRT)
4799 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4800 else
4801 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4802 }
4803 }
4804
482fed85 4805 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4806}
4807
f4187b56 4808/**
e98cac44 4809 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 4810 * @hw: pointer to the HW structure
4811 *
e98cac44
BA		 4812 * Read appropriate register for the config done bit for completion status
4813 * and configure the PHY through s/w for EEPROM-less parts.
4814 *
4815 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4816 * config done bit, so only an error is logged and continues. If we were
4817 * to return with error, EEPROM-less silicon would not be able to be reset
4818 * or change link.
f4187b56
BA		 4819 **/
4820static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4821{
e98cac44 4822 s32 ret_val = 0;
f4187b56 4823 u32 bank = 0;
e98cac44 4824 u32 status;
f4187b56 4825
fe90849f 4826 e1000e_get_cfg_done_generic(hw);
fc0c7760 4827
e98cac44
BA		 4828 /* Wait for indication from h/w that it has completed basic config */
4829 if (hw->mac.type >= e1000_ich10lan) {
4830 e1000_lan_init_done_ich8lan(hw);
4831 } else {
4832 ret_val = e1000e_get_auto_rd_done(hw);
4833 if (ret_val) {
e921eb1a 4834 /* When auto config read does not complete, do not
e98cac44
BA		 4835 * return with an error. This can happen in situations
4836 * where there is no eeprom and prevents getting link.
4837 */
4838 e_dbg("Auto Read Done did not complete\n");
4839 ret_val = 0;
4840 }
fc0c7760
BA		 4841 }
4842
e98cac44
BA		 4843 /* Clear PHY Reset Asserted bit */
4844 status = er32(STATUS);
4845 if (status & E1000_STATUS_PHYRA)
4846 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4847 else
4848 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 4849
4850 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 4851 if (hw->mac.type <= e1000_ich9lan) {
04499ec4 4852 if (!(er32(EECD) & E1000_EECD_PRES) &&
f4187b56
BA		 4853 (hw->phy.type == e1000_phy_igp_3)) {
4854 e1000e_phy_init_script_igp3(hw);
4855 }
4856 } else {
4857 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4858 /* Maybe we should do a basic PHY config */
3bb99fe2 4859 e_dbg("EEPROM not present\n");
e98cac44 4860 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 4861 }
4862 }
4863
e98cac44 4864 return ret_val;
f4187b56
BA		 4865}
4866
17f208de
BA		 4867/**
4868 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4869 * @hw: pointer to the HW structure
4870 *
4871 * In the case of a PHY power down to save power, or to turn off link during a
4872 * driver unload, or wake on lan is not enabled, remove the link.
4873 **/
4874static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4875{
4876 /* If the management interface is not enabled, then power down */
4877 if (!(hw->mac.ops.check_mng_mode(hw) ||
4878 hw->phy.ops.check_reset_block(hw)))
4879 e1000_power_down_phy_copper(hw);
17f208de
BA		 4880}
4881
bc7f75fa
AK		 4882/**
4883 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4884 * @hw: pointer to the HW structure
4885 *
4886 * Clears hardware counters specific to the silicon family and calls
4887 * clear_hw_cntrs_generic to clear all general purpose counters.
4888 **/
4889static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4890{
a4f58f54 4891 u16 phy_data;
2b6b168d 4892 s32 ret_val;
bc7f75fa
AK		 4893
4894 e1000e_clear_hw_cntrs_base(hw);
4895
99673d9b
BA		 4896 er32(ALGNERRC);
4897 er32(RXERRC);
4898 er32(TNCRS);
4899 er32(CEXTERR);
4900 er32(TSCTC);
4901 er32(TSCTFC);
bc7f75fa 4902
99673d9b
BA		 4903 er32(MGTPRC);
4904 er32(MGTPDC);
4905 er32(MGTPTC);
bc7f75fa 4906
99673d9b
BA		 4907 er32(IAC);
4908 er32(ICRXOC);
bc7f75fa 4909
a4f58f54
BA		 4910 /* Clear PHY statistics registers */
4911 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 4912 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 4913 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 4914 (hw->phy.type == e1000_phy_82577)) {
2b6b168d
BA		 4915 ret_val = hw->phy.ops.acquire(hw);
4916 if (ret_val)
4917 return;
4918 ret_val = hw->phy.ops.set_page(hw,
4919 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4920 if (ret_val)
4921 goto release;
4922 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4923 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4924 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4925 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4926 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4927 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4928 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4929 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4930 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4931 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4932 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4933 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4934 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4935 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4936release:
4937 hw->phy.ops.release(hw);
a4f58f54 4938 }
bc7f75fa
AK		 4939}
4940
8ce9d6c7 4941static const struct e1000_mac_operations ich8_mac_ops = {
eb7700dc 4942 /* check_mng_mode dependent on mac type */
7d3cabbc 4943 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 4944 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 4945 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4946 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 4947 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 4948 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 4949 /* led_on dependent on mac type */
4950 /* led_off dependent on mac type */
e2de3eb6 4951 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 4952 .reset_hw = e1000_reset_hw_ich8lan,
4953 .init_hw = e1000_init_hw_ich8lan,
4954 .setup_link = e1000_setup_link_ich8lan,
55c5f55e 4955 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
a4f58f54 4956 /* id_led_init dependent on mac type */
57cde763 4957 .config_collision_dist = e1000e_config_collision_dist_generic,
69e1e019 4958 .rar_set = e1000e_rar_set_generic,
bc7f75fa
AK		 4959};
4960
8ce9d6c7 4961static const struct e1000_phy_operations ich8_phy_ops = {
94d8186a 4962 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 4963 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 4964 .commit = NULL,
f4187b56 4965 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 4966 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 4967 .read_reg = e1000e_read_phy_reg_igp,
4968 .release = e1000_release_swflag_ich8lan,
4969 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 4970 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4971 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 4972 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 4973};
4974
8ce9d6c7 4975static const struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a 4976 .acquire = e1000_acquire_nvm_ich8lan,
55c5f55e 4977 .read = e1000_read_nvm_ich8lan,
94d8186a 4978 .release = e1000_release_nvm_ich8lan,
e85e3639 4979 .reload = e1000e_reload_nvm_generic,
94d8186a 4980 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 4981 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 4982 .validate = e1000_validate_nvm_checksum_ich8lan,
4983 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 4984};
4985
8ce9d6c7 4986const struct e1000_info e1000_ich8_info = {
bc7f75fa
AK		 4987 .mac = e1000_ich8lan,
4988 .flags = FLAG_HAS_WOL
97ac8cae 4989 | FLAG_IS_ICH
bc7f75fa
AK		 4990 | FLAG_HAS_CTRLEXT_ON_LOAD
4991 | FLAG_HAS_AMT
4992 | FLAG_HAS_FLASH
4993 | FLAG_APME_IN_WUC,
4994 .pba = 8,
2adc55c9 4995 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 4996 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4997 .mac_ops = &ich8_mac_ops,
4998 .phy_ops = &ich8_phy_ops,
4999 .nvm_ops = &ich8_nvm_ops,
5000};
5001
8ce9d6c7 5002const struct e1000_info e1000_ich9_info = {
bc7f75fa
AK		 5003 .mac = e1000_ich9lan,
5004 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 5005 | FLAG_IS_ICH
bc7f75fa 5006 | FLAG_HAS_WOL
bc7f75fa
AK		 5007 | FLAG_HAS_CTRLEXT_ON_LOAD
5008 | FLAG_HAS_AMT
bc7f75fa
AK		 5009 | FLAG_HAS_FLASH
5010 | FLAG_APME_IN_WUC,
7f1557e1 5011 .pba = 18,
2adc55c9 5012 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 5013 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 5014 .mac_ops = &ich8_mac_ops,
5015 .phy_ops = &ich8_phy_ops,
5016 .nvm_ops = &ich8_nvm_ops,
5017};
5018
8ce9d6c7 5019const struct e1000_info e1000_ich10_info = {
f4187b56
BA		 5020 .mac = e1000_ich10lan,
5021 .flags = FLAG_HAS_JUMBO_FRAMES
5022 | FLAG_IS_ICH
5023 | FLAG_HAS_WOL
f4187b56
BA		 5024 | FLAG_HAS_CTRLEXT_ON_LOAD
5025 | FLAG_HAS_AMT
f4187b56
BA		 5026 | FLAG_HAS_FLASH
5027 | FLAG_APME_IN_WUC,
7f1557e1 5028 .pba = 18,
2adc55c9 5029 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 5030 .get_variants = e1000_get_variants_ich8lan,
5031 .mac_ops = &ich8_mac_ops,
5032 .phy_ops = &ich8_phy_ops,
5033 .nvm_ops = &ich8_nvm_ops,
5034};
a4f58f54 5035
8ce9d6c7 5036const struct e1000_info e1000_pch_info = {
a4f58f54
BA		 5037 .mac = e1000_pchlan,
5038 .flags = FLAG_IS_ICH
5039 | FLAG_HAS_WOL
a4f58f54
BA		 5040 | FLAG_HAS_CTRLEXT_ON_LOAD
5041 | FLAG_HAS_AMT
5042 | FLAG_HAS_FLASH
5043 | FLAG_HAS_JUMBO_FRAMES
38eb394e 5044 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 5045 | FLAG_APME_IN_WUC,
8c7bbb92 5046 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 5047 .pba = 26,
5048 .max_hw_frame_size = 4096,
5049 .get_variants = e1000_get_variants_ich8lan,
5050 .mac_ops = &ich8_mac_ops,
5051 .phy_ops = &ich8_phy_ops,
5052 .nvm_ops = &ich8_nvm_ops,
5053};
d3738bb8 5054
8ce9d6c7 5055const struct e1000_info e1000_pch2_info = {
d3738bb8
BA		 5056 .mac = e1000_pch2lan,
5057 .flags = FLAG_IS_ICH
5058 | FLAG_HAS_WOL
b67e1913 5059 | FLAG_HAS_HW_TIMESTAMP
d3738bb8
BA		 5060 | FLAG_HAS_CTRLEXT_ON_LOAD
5061 | FLAG_HAS_AMT
5062 | FLAG_HAS_FLASH
5063 | FLAG_HAS_JUMBO_FRAMES
5064 | FLAG_APME_IN_WUC,
e52997f9
BA		 5065 .flags2 = FLAG2_HAS_PHY_STATS
5066 | FLAG2_HAS_EEE,
828bac87 5067 .pba = 26,
c3d2dbf4 5068 .max_hw_frame_size = 9018,
d3738bb8
BA		 5069 .get_variants = e1000_get_variants_ich8lan,
5070 .mac_ops = &ich8_mac_ops,
5071 .phy_ops = &ich8_phy_ops,
5072 .nvm_ops = &ich8_nvm_ops,
5073};
2fbe4526
BA		 5074
5075const struct e1000_info e1000_pch_lpt_info = {
5076 .mac = e1000_pch_lpt,
5077 .flags = FLAG_IS_ICH
5078 | FLAG_HAS_WOL
b67e1913 5079 | FLAG_HAS_HW_TIMESTAMP
2fbe4526
BA		 5080 | FLAG_HAS_CTRLEXT_ON_LOAD
5081 | FLAG_HAS_AMT
5082 | FLAG_HAS_FLASH
5083 | FLAG_HAS_JUMBO_FRAMES
5084 | FLAG_APME_IN_WUC,
5085 .flags2 = FLAG2_HAS_PHY_STATS
5086 | FLAG2_HAS_EEE,
5087 .pba = 26,
ed1a4265 5088 .max_hw_frame_size = 9018,
2fbe4526
BA		 5089 .get_variants = e1000_get_variants_ich8lan,
5090 .mac_ops = &ich8_mac_ops,
5091 .phy_ops = &ich8_phy_ops,
5092 .nvm_ops = &ich8_nvm_ops,
5093};
Linux kernel - Deliverables
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