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e1000e: Cleanup unecessary references
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
e921eb1a 29/* 82562G 10/100 Network Connection
bc7f75fa
AK		 30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
97ac8cae
BA		 41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
1605927f 43 * 82567V Gigabit Network Connection
97ac8cae
BA		 44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
2f15f9d6 49 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
d3738bb8
BA		 54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
bc7f75fa
AK		 56 */
57
bc7f75fa
AK		 58#include "e1000.h"
59
bc7f75fa
AK		 60/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
61/* Offset 04h HSFSTS */
62union ich8_hws_flash_status {
63 struct ich8_hsfsts {
362e20ca
BA		 64 u16 flcdone:1; /* bit 0 Flash Cycle Done */
65 u16 flcerr:1; /* bit 1 Flash Cycle Error */
66 u16 dael:1; /* bit 2 Direct Access error Log */
67 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
68 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
69 u16 reserved1:2; /* bit 13:6 Reserved */
70 u16 reserved2:6; /* bit 13:6 Reserved */
71 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
72 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
bc7f75fa
AK		 73 } hsf_status;
74 u16 regval;
75};
76
77/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
78/* Offset 06h FLCTL */
79union ich8_hws_flash_ctrl {
80 struct ich8_hsflctl {
362e20ca
BA		 81 u16 flcgo:1; /* 0 Flash Cycle Go */
82 u16 flcycle:2; /* 2:1 Flash Cycle */
83 u16 reserved:5; /* 7:3 Reserved */
84 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
85 u16 flockdn:6; /* 15:10 Reserved */
bc7f75fa
AK		 86 } hsf_ctrl;
87 u16 regval;
88};
89
90/* ICH Flash Region Access Permissions */
91union ich8_hws_flash_regacc {
92 struct ich8_flracc {
362e20ca
BA		 93 u32 grra:8; /* 0:7 GbE region Read Access */
94 u32 grwa:8; /* 8:15 GbE region Write Access */
95 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
96 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
bc7f75fa
AK		 97 } hsf_flregacc;
98 u16 regval;
99};
100
4a770358
BA		 101/* ICH Flash Protected Region */
102union ich8_flash_protected_range {
103 struct ich8_pr {
e80bd1d1
BA		 104 u32 base:13; /* 0:12 Protected Range Base */
105 u32 reserved1:2; /* 13:14 Reserved */
106 u32 rpe:1; /* 15 Read Protection Enable */
107 u32 limit:13; /* 16:28 Protected Range Limit */
108 u32 reserved2:2; /* 29:30 Reserved */
109 u32 wpe:1; /* 31 Write Protection Enable */
4a770358
BA		 110 } range;
111 u32 regval;
112};
113
bc7f75fa
AK		 114static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
115static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 116static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
117static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 byte);
f4187b56
BA		 119static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
120 u8 *data);
bc7f75fa
AK		 121static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
122 u16 *data);
123static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
124 u8 size, u16 *data);
bc7f75fa 125static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 126static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
127static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
128static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
129static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
130static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
131static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
132static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
133static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 134static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 135static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 136static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1f96012d 137static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 138static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 139static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
140static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
69e1e019 141static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
2fbe4526 142static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
831bd2e6 143static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 144static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
ea8179a7 145static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
bc7f75fa
AK		 146
147static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
148{
149 return readw(hw->flash_address + reg);
150}
151
152static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
153{
154 return readl(hw->flash_address + reg);
155}
156
157static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
158{
159 writew(val, hw->flash_address + reg);
160}
161
162static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
163{
164 writel(val, hw->flash_address + reg);
165}
166
167#define er16flash(reg) __er16flash(hw, (reg))
168#define er32flash(reg) __er32flash(hw, (reg))
0e15df49
BA		 169#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
170#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
bc7f75fa 171
cb17aab9
BA		 172/**
173 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
174 * @hw: pointer to the HW structure
175 *
176 * Test access to the PHY registers by reading the PHY ID registers. If
177 * the PHY ID is already known (e.g. resume path) compare it with known ID,
178 * otherwise assume the read PHY ID is correct if it is valid.
179 *
180 * Assumes the sw/fw/hw semaphore is already acquired.
181 **/
182static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
99730e4c 183{
a52359b5
BA		 184 u16 phy_reg = 0;
185 u32 phy_id = 0;
186 s32 ret_val;
187 u16 retry_count;
16b095a4 188 u32 mac_reg = 0;
a52359b5
BA		 189
190 for (retry_count = 0; retry_count < 2; retry_count++) {
c2ade1a4 191 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
a52359b5
BA		 192 if (ret_val || (phy_reg == 0xFFFF))
193 continue;
194 phy_id = (u32)(phy_reg << 16);
195
c2ade1a4 196 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
a52359b5
BA		 197 if (ret_val || (phy_reg == 0xFFFF)) {
198 phy_id = 0;
199 continue;
200 }
201 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
202 break;
203 }
cb17aab9
BA		 204
205 if (hw->phy.id) {
206 if (hw->phy.id == phy_id)
16b095a4 207 goto out;
a52359b5
BA		 208 } else if (phy_id) {
209 hw->phy.id = phy_id;
210 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
16b095a4 211 goto out;
cb17aab9
BA		 212 }
213
e921eb1a 214 /* In case the PHY needs to be in mdio slow mode,
a52359b5
BA		 215 * set slow mode and try to get the PHY id again.
216 */
217 hw->phy.ops.release(hw);
218 ret_val = e1000_set_mdio_slow_mode_hv(hw);
219 if (!ret_val)
220 ret_val = e1000e_get_phy_id(hw);
221 hw->phy.ops.acquire(hw);
222
16b095a4
BA		 223 if (ret_val)
224 return false;
225out:
226 if (hw->mac.type == e1000_pch_lpt) {
227 /* Unforce SMBus mode in PHY */
228 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
229 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
230 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
231
232 /* Unforce SMBus mode in MAC */
233 mac_reg = er32(CTRL_EXT);
234 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
235 ew32(CTRL_EXT, mac_reg);
236 }
237
238 return true;
cb17aab9
BA		 239}
240
241/**
242 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
243 * @hw: pointer to the HW structure
244 *
245 * Workarounds/flow necessary for PHY initialization during driver load
246 * and resume paths.
247 **/
248static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
249{
250 u32 mac_reg, fwsm = er32(FWSM);
251 s32 ret_val;
252
6e928b72
BA		 253 /* Gate automatic PHY configuration by hardware on managed and
254 * non-managed 82579 and newer adapters.
255 */
256 e1000_gate_hw_phy_config_ich8lan(hw, true);
257
cb17aab9
BA		 258 ret_val = hw->phy.ops.acquire(hw);
259 if (ret_val) {
260 e_dbg("Failed to initialize PHY flow\n");
6e928b72 261 goto out;
cb17aab9
BA		 262 }
263
e921eb1a 264 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
cb17aab9
BA		 265 * inaccessible and resetting the PHY is not blocked, toggle the
266 * LANPHYPC Value bit to force the interconnect to PCIe mode.
267 */
268 switch (hw->mac.type) {
2fbe4526
BA		 269 case e1000_pch_lpt:
270 if (e1000_phy_is_accessible_pchlan(hw))
271 break;
272
e921eb1a 273 /* Before toggling LANPHYPC, see if PHY is accessible by
2fbe4526
BA		 274 * forcing MAC to SMBus mode first.
275 */
276 mac_reg = er32(CTRL_EXT);
277 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
278 ew32(CTRL_EXT, mac_reg);
279
16b095a4
BA		 280 /* Wait 50 milliseconds for MAC to finish any retries
281 * that it might be trying to perform from previous
282 * attempts to acknowledge any phy read requests.
283 */
284 msleep(50);
285
2fbe4526 286 /* fall-through */
cb17aab9 287 case e1000_pch2lan:
16b095a4 288 if (e1000_phy_is_accessible_pchlan(hw))
cb17aab9
BA		 289 break;
290
291 /* fall-through */
292 case e1000_pchlan:
293 if ((hw->mac.type == e1000_pchlan) &&
294 (fwsm & E1000_ICH_FWSM_FW_VALID))
295 break;
296
297 if (hw->phy.ops.check_reset_block(hw)) {
298 e_dbg("Required LANPHYPC toggle blocked by ME\n");
16b095a4 299 ret_val = -E1000_ERR_PHY;
cb17aab9
BA		 300 break;
301 }
302
303 e_dbg("Toggling LANPHYPC\n");
304
305 /* Set Phy Config Counter to 50msec */
306 mac_reg = er32(FEXTNVM3);
307 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
308 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
309 ew32(FEXTNVM3, mac_reg);
310
311 /* Toggle LANPHYPC Value bit */
312 mac_reg = er32(CTRL);
313 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
314 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
315 ew32(CTRL, mac_reg);
316 e1e_flush();
ce43a216 317 usleep_range(10, 20);
cb17aab9
BA		 318 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
319 ew32(CTRL, mac_reg);
320 e1e_flush();
2fbe4526
BA		 321 if (hw->mac.type < e1000_pch_lpt) {
322 msleep(50);
323 } else {
324 u16 count = 20;
325 do {
326 usleep_range(5000, 10000);
327 } while (!(er32(CTRL_EXT) &
328 E1000_CTRL_EXT_LPCD) && count--);
16b095a4
BA		 329 usleep_range(30000, 60000);
330 if (e1000_phy_is_accessible_pchlan(hw))
331 break;
332
333 /* Toggling LANPHYPC brings the PHY out of SMBus mode
334 * so ensure that the MAC is also out of SMBus mode
335 */
336 mac_reg = er32(CTRL_EXT);
337 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
338 ew32(CTRL_EXT, mac_reg);
339
340 if (e1000_phy_is_accessible_pchlan(hw))
341 break;
342
343 ret_val = -E1000_ERR_PHY;
2fbe4526 344 }
cb17aab9
BA		 345 break;
346 default:
347 break;
348 }
349
350 hw->phy.ops.release(hw);
16b095a4
BA		 351 if (!ret_val) {
352 /* Reset the PHY before any access to it. Doing so, ensures
353 * that the PHY is in a known good state before we read/write
354 * PHY registers. The generic reset is sufficient here,
355 * because we haven't determined the PHY type yet.
356 */
357 ret_val = e1000e_phy_hw_reset_generic(hw);
358 }
cb17aab9 359
6e928b72 360out:
cb17aab9
BA		 361 /* Ungate automatic PHY configuration on non-managed 82579 */
362 if ((hw->mac.type == e1000_pch2lan) &&
363 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
364 usleep_range(10000, 20000);
365 e1000_gate_hw_phy_config_ich8lan(hw, false);
366 }
367
368 return ret_val;
99730e4c
BA		 369}
370
a4f58f54
BA		 371/**
372 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
373 * @hw: pointer to the HW structure
374 *
375 * Initialize family-specific PHY parameters and function pointers.
376 **/
377static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
378{
379 struct e1000_phy_info *phy = &hw->phy;
70806a7f 380 s32 ret_val;
a4f58f54 381
e80bd1d1
BA		 382 phy->addr = 1;
383 phy->reset_delay_us = 100;
384
385 phy->ops.set_page = e1000_set_page_igp;
386 phy->ops.read_reg = e1000_read_phy_reg_hv;
387 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
388 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
389 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
390 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
391 phy->ops.write_reg = e1000_write_phy_reg_hv;
392 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
393 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
394 phy->ops.power_up = e1000_power_up_phy_copper;
395 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
396 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
a4f58f54 397
cb17aab9 398 phy->id = e1000_phy_unknown;
627c8a04 399
cb17aab9
BA		 400 ret_val = e1000_init_phy_workarounds_pchlan(hw);
401 if (ret_val)
402 return ret_val;
605c82ba 403
cb17aab9
BA		 404 if (phy->id == e1000_phy_unknown)
405 switch (hw->mac.type) {
406 default:
407 ret_val = e1000e_get_phy_id(hw);
408 if (ret_val)
409 return ret_val;
410 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
411 break;
412 /* fall-through */
413 case e1000_pch2lan:
2fbe4526 414 case e1000_pch_lpt:
e921eb1a 415 /* In case the PHY needs to be in mdio slow mode,
cb17aab9
BA		 416 * set slow mode and try to get the PHY id again.
417 */
418 ret_val = e1000_set_mdio_slow_mode_hv(hw);
419 if (ret_val)
420 return ret_val;
421 ret_val = e1000e_get_phy_id(hw);
422 if (ret_val)
423 return ret_val;
664dc878 424 break;
cb17aab9 425 }
a4f58f54
BA		 426 phy->type = e1000e_get_phy_type_from_id(phy->id);
427
0be84010
BA		 428 switch (phy->type) {
429 case e1000_phy_82577:
d3738bb8 430 case e1000_phy_82579:
2fbe4526 431 case e1000_phy_i217:
a4f58f54
BA		 432 phy->ops.check_polarity = e1000_check_polarity_82577;
433 phy->ops.force_speed_duplex =
6cc7aaed 434 e1000_phy_force_speed_duplex_82577;
0be84010 435 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 436 phy->ops.get_info = e1000_get_phy_info_82577;
437 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 438 break;
0be84010
BA		 439 case e1000_phy_82578:
440 phy->ops.check_polarity = e1000_check_polarity_m88;
441 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
442 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
443 phy->ops.get_info = e1000e_get_phy_info_m88;
444 break;
445 default:
446 ret_val = -E1000_ERR_PHY;
447 break;
a4f58f54
BA		 448 }
449
450 return ret_val;
451}
452
bc7f75fa
AK		 453/**
454 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
455 * @hw: pointer to the HW structure
456 *
457 * Initialize family-specific PHY parameters and function pointers.
458 **/
459static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
460{
461 struct e1000_phy_info *phy = &hw->phy;
462 s32 ret_val;
463 u16 i = 0;
464
e80bd1d1
BA		 465 phy->addr = 1;
466 phy->reset_delay_us = 100;
bc7f75fa 467
e80bd1d1
BA		 468 phy->ops.power_up = e1000_power_up_phy_copper;
469 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
17f208de 470
e921eb1a 471 /* We may need to do this twice - once for IGP and if that fails,
97ac8cae
BA		 472 * we'll set BM func pointers and try again
473 */
474 ret_val = e1000e_determine_phy_address(hw);
475 if (ret_val) {
94d8186a 476 phy->ops.write_reg = e1000e_write_phy_reg_bm;
e80bd1d1 477 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 478 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 479 if (ret_val) {
480 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 481 return ret_val;
9b71b419 482 }
97ac8cae
BA		 483 }
484
bc7f75fa
AK		 485 phy->id = 0;
486 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
487 (i++ < 100)) {
1bba4386 488 usleep_range(1000, 2000);
bc7f75fa
AK		 489 ret_val = e1000e_get_phy_id(hw);
490 if (ret_val)
491 return ret_val;
492 }
493
494 /* Verify phy id */
495 switch (phy->id) {
496 case IGP03E1000_E_PHY_ID:
497 phy->type = e1000_phy_igp_3;
498 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 499 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
500 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 501 phy->ops.get_info = e1000e_get_phy_info_igp;
502 phy->ops.check_polarity = e1000_check_polarity_igp;
503 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 504 break;
505 case IFE_E_PHY_ID:
506 case IFE_PLUS_E_PHY_ID:
507 case IFE_C_E_PHY_ID:
508 phy->type = e1000_phy_ife;
509 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 510 phy->ops.get_info = e1000_get_phy_info_ife;
511 phy->ops.check_polarity = e1000_check_polarity_ife;
512 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 513 break;
97ac8cae
BA		 514 case BME1000_E_PHY_ID:
515 phy->type = e1000_phy_bm;
516 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 517 phy->ops.read_reg = e1000e_read_phy_reg_bm;
518 phy->ops.write_reg = e1000e_write_phy_reg_bm;
519 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 520 phy->ops.get_info = e1000e_get_phy_info_m88;
521 phy->ops.check_polarity = e1000_check_polarity_m88;
522 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 523 break;
bc7f75fa
AK		 524 default:
525 return -E1000_ERR_PHY;
526 break;
527 }
528
529 return 0;
530}
531
532/**
533 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
534 * @hw: pointer to the HW structure
535 *
536 * Initialize family-specific NVM parameters and function
537 * pointers.
538 **/
539static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
540{
541 struct e1000_nvm_info *nvm = &hw->nvm;
542 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 543 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 544 u16 i;
545
ad68076e 546 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 547 if (!hw->flash_address) {
3bb99fe2 548 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 549 return -E1000_ERR_CONFIG;
550 }
551
552 nvm->type = e1000_nvm_flash_sw;
553
554 gfpreg = er32flash(ICH_FLASH_GFPREG);
555
e921eb1a 556 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 557 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 558 * the overall size.
559 */
bc7f75fa
AK		 560 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
561 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
562
563 /* flash_base_addr is byte-aligned */
564 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
565
e921eb1a 566 /* find total size of the NVM, then cut in half since the total
ad68076e
BA		 567 * size represents two separate NVM banks.
568 */
f0ff4398
BA		 569 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
570 << FLASH_SECTOR_ADDR_SHIFT);
bc7f75fa
AK		 571 nvm->flash_bank_size /= 2;
572 /* Adjust to word count */
573 nvm->flash_bank_size /= sizeof(u16);
574
575 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
576
577 /* Clear shadow ram */
578 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 579 dev_spec->shadow_ram[i].modified = false;
e80bd1d1 580 dev_spec->shadow_ram[i].value = 0xFFFF;
bc7f75fa
AK		 581 }
582
583 return 0;
584}
585
586/**
587 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
588 * @hw: pointer to the HW structure
589 *
590 * Initialize family-specific MAC parameters and function
591 * pointers.
592 **/
ec34c170 593static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
bc7f75fa 594{
bc7f75fa
AK		 595 struct e1000_mac_info *mac = &hw->mac;
596
597 /* Set media type function pointer */
318a94d6 598 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 599
600 /* Set mta register count */
601 mac->mta_reg_count = 32;
602 /* Set rar entry count */
603 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
604 if (mac->type == e1000_ich8lan)
605 mac->rar_entry_count--;
a65a4a0d
BA		 606 /* FWSM register */
607 mac->has_fwsm = true;
608 /* ARC subsystem not supported */
609 mac->arc_subsystem_valid = false;
f464ba87
BA		 610 /* Adaptive IFS supported */
611 mac->adaptive_ifs = true;
bc7f75fa 612
2fbe4526 613 /* LED and other operations */
a4f58f54
BA		 614 switch (mac->type) {
615 case e1000_ich8lan:
616 case e1000_ich9lan:
617 case e1000_ich10lan:
eb7700dc
BA		 618 /* check management mode */
619 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54 620 /* ID LED init */
d1964eb1 621 mac->ops.id_led_init = e1000e_id_led_init_generic;
dbf80dcb
BA		 622 /* blink LED */
623 mac->ops.blink_led = e1000e_blink_led_generic;
a4f58f54
BA		 624 /* setup LED */
625 mac->ops.setup_led = e1000e_setup_led_generic;
626 /* cleanup LED */
627 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
628 /* turn on/off LED */
629 mac->ops.led_on = e1000_led_on_ich8lan;
630 mac->ops.led_off = e1000_led_off_ich8lan;
631 break;
d3738bb8 632 case e1000_pch2lan:
69e1e019
BA		 633 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
634 mac->ops.rar_set = e1000_rar_set_pch2lan;
635 /* fall-through */
2fbe4526 636 case e1000_pch_lpt:
69e1e019 637 case e1000_pchlan:
eb7700dc
BA		 638 /* check management mode */
639 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 640 /* ID LED init */
641 mac->ops.id_led_init = e1000_id_led_init_pchlan;
642 /* setup LED */
643 mac->ops.setup_led = e1000_setup_led_pchlan;
644 /* cleanup LED */
645 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
646 /* turn on/off LED */
647 mac->ops.led_on = e1000_led_on_pchlan;
648 mac->ops.led_off = e1000_led_off_pchlan;
649 break;
650 default:
651 break;
652 }
653
2fbe4526
BA		 654 if (mac->type == e1000_pch_lpt) {
655 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
656 mac->ops.rar_set = e1000_rar_set_pch_lpt;
ea8179a7
BA		 657 mac->ops.setup_physical_interface =
658 e1000_setup_copper_link_pch_lpt;
2fbe4526
BA		 659 }
660
bc7f75fa
AK		 661 /* Enable PCS Lock-loss workaround for ICH8 */
662 if (mac->type == e1000_ich8lan)
564ea9bb 663 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 664
665 return 0;
666}
667
4ddc48a9
BA		 668/**
669 * __e1000_access_emi_reg_locked - Read/write EMI register
670 * @hw: pointer to the HW structure
671 * @addr: EMI address to program
672 * @data: pointer to value to read/write from/to the EMI address
673 * @read: boolean flag to indicate read or write
674 *
675 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
676 **/
677static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
678 u16 *data, bool read)
679{
70806a7f 680 s32 ret_val;
4ddc48a9
BA		 681
682 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
683 if (ret_val)
684 return ret_val;
685
686 if (read)
687 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
688 else
689 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
690
691 return ret_val;
692}
693
694/**
695 * e1000_read_emi_reg_locked - Read Extended Management Interface register
696 * @hw: pointer to the HW structure
697 * @addr: EMI address to program
698 * @data: value to be read from the EMI address
699 *
700 * Assumes the SW/FW/HW Semaphore is already acquired.
701 **/
203e4151 702s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
4ddc48a9
BA		 703{
704 return __e1000_access_emi_reg_locked(hw, addr, data, true);
705}
706
707/**
708 * e1000_write_emi_reg_locked - Write Extended Management Interface register
709 * @hw: pointer to the HW structure
710 * @addr: EMI address to program
711 * @data: value to be written to the EMI address
712 *
713 * Assumes the SW/FW/HW Semaphore is already acquired.
714 **/
d495bcb8 715s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
4ddc48a9
BA		 716{
717 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
718}
719
e52997f9
BA		 720/**
721 * e1000_set_eee_pchlan - Enable/disable EEE support
722 * @hw: pointer to the HW structure
723 *
3d4d5755
BA		 724 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
725 * the link and the EEE capabilities of the link partner. The LPI Control
726 * register bits will remain set only if/when link is up.
e52997f9
BA		 727 **/
728static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
729{
2fbe4526 730 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3d4d5755 731 s32 ret_val;
d495bcb8 732 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
e52997f9 733
d495bcb8
BA		 734 switch (hw->phy.type) {
735 case e1000_phy_82579:
736 lpa = I82579_EEE_LP_ABILITY;
737 pcs_status = I82579_EEE_PCS_STATUS;
738 adv_addr = I82579_EEE_ADVERTISEMENT;
739 break;
740 case e1000_phy_i217:
741 lpa = I217_EEE_LP_ABILITY;
742 pcs_status = I217_EEE_PCS_STATUS;
743 adv_addr = I217_EEE_ADVERTISEMENT;
744 break;
745 default:
5015e53a 746 return 0;
d495bcb8 747 }
e52997f9 748
3d4d5755 749 ret_val = hw->phy.ops.acquire(hw);
e52997f9 750 if (ret_val)
5015e53a 751 return ret_val;
e52997f9 752
3d4d5755 753 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
2fbe4526 754 if (ret_val)
3d4d5755
BA		 755 goto release;
756
757 /* Clear bits that enable EEE in various speeds */
758 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
759
760 /* Enable EEE if not disabled by user */
761 if (!dev_spec->eee_disable) {
2fbe4526 762 /* Save off link partner's EEE ability */
3d4d5755 763 ret_val = e1000_read_emi_reg_locked(hw, lpa,
4ddc48a9 764 &dev_spec->eee_lp_ability);
2fbe4526
BA		 765 if (ret_val)
766 goto release;
2fbe4526 767
d495bcb8
BA		 768 /* Read EEE advertisement */
769 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
770 if (ret_val)
771 goto release;
772
3d4d5755 773 /* Enable EEE only for speeds in which the link partner is
d495bcb8 774 * EEE capable and for which we advertise EEE.
2fbe4526 775 */
d495bcb8 776 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
3d4d5755
BA		 777 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
778
d495bcb8 779 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
c2ade1a4
BA		 780 e1e_rphy_locked(hw, MII_LPA, &data);
781 if (data & LPA_100FULL)
3d4d5755
BA		 782 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
783 else
784 /* EEE is not supported in 100Half, so ignore
785 * partner's EEE in 100 ability if full-duplex
786 * is not advertised.
787 */
788 dev_spec->eee_lp_ability &=
789 ~I82579_EEE_100_SUPPORTED;
790 }
2fbe4526
BA		 791 }
792
d495bcb8
BA		 793 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
794 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
795 if (ret_val)
796 goto release;
797
3d4d5755
BA		 798 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
799release:
800 hw->phy.ops.release(hw);
801
802 return ret_val;
e52997f9
BA		 803}
804
e08f626b
BA		 805/**
806 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
807 * @hw: pointer to the HW structure
808 * @link: link up bool flag
809 *
810 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
811 * preventing further DMA write requests. Workaround the issue by disabling
812 * the de-assertion of the clock request when in 1Gpbs mode.
e0236ad9
BA		 813 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
814 * speeds in order to avoid Tx hangs.
e08f626b
BA		 815 **/
816static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
817{
818 u32 fextnvm6 = er32(FEXTNVM6);
e0236ad9 819 u32 status = er32(STATUS);
e08f626b 820 s32 ret_val = 0;
e0236ad9 821 u16 reg;
e08f626b 822
e0236ad9 823 if (link && (status & E1000_STATUS_SPEED_1000)) {
e08f626b
BA		 824 ret_val = hw->phy.ops.acquire(hw);
825 if (ret_val)
826 return ret_val;
827
828 ret_val =
829 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 830 &reg);
e08f626b
BA		 831 if (ret_val)
832 goto release;
833
834 ret_val =
835 e1000e_write_kmrn_reg_locked(hw,
836 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 837 reg &
e08f626b
BA		 838 ~E1000_KMRNCTRLSTA_K1_ENABLE);
839 if (ret_val)
840 goto release;
841
842 usleep_range(10, 20);
843
844 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
845
846 ret_val =
847 e1000e_write_kmrn_reg_locked(hw,
848 E1000_KMRNCTRLSTA_K1_CONFIG,
e0236ad9 849 reg);
e08f626b
BA		 850release:
851 hw->phy.ops.release(hw);
852 } else {
853 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
e0236ad9
BA		 854 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
855
856 if (!link || ((status & E1000_STATUS_SPEED_100) &&
857 (status & E1000_STATUS_FD)))
858 goto update_fextnvm6;
859
860 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
861 if (ret_val)
862 return ret_val;
863
864 /* Clear link status transmit timeout */
865 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
866
867 if (status & E1000_STATUS_SPEED_100) {
868 /* Set inband Tx timeout to 5x10us for 100Half */
869 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
870
871 /* Do not extend the K1 entry latency for 100Half */
872 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
873 } else {
874 /* Set inband Tx timeout to 50x10us for 10Full/Half */
875 reg |= 50 <<
876 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
877
878 /* Extend the K1 entry latency for 10 Mbps */
879 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
880 }
881
882 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
883 if (ret_val)
884 return ret_val;
885
886update_fextnvm6:
887 ew32(FEXTNVM6, fextnvm6);
e08f626b
BA		 888 }
889
890 return ret_val;
891}
892
cf8fb73c
BA		 893/**
894 * e1000_platform_pm_pch_lpt - Set platform power management values
895 * @hw: pointer to the HW structure
896 * @link: bool indicating link status
897 *
898 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
899 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
900 * when link is up (which must not exceed the maximum latency supported
901 * by the platform), otherwise specify there is no LTR requirement.
902 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
903 * latencies in the LTR Extended Capability Structure in the PCIe Extended
904 * Capability register set, on this device LTR is set by writing the
905 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
906 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
907 * message to the PMC.
908 **/
909static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
910{
911 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
912 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
913 u16 lat_enc = 0; /* latency encoded */
914
915 if (link) {
916 u16 speed, duplex, scale = 0;
917 u16 max_snoop, max_nosnoop;
918 u16 max_ltr_enc; /* max LTR latency encoded */
919 s64 lat_ns; /* latency (ns) */
920 s64 value;
921 u32 rxa;
922
923 if (!hw->adapter->max_frame_size) {
924 e_dbg("max_frame_size not set.\n");
925 return -E1000_ERR_CONFIG;
926 }
927
928 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
929 if (!speed) {
930 e_dbg("Speed not set.\n");
931 return -E1000_ERR_CONFIG;
932 }
933
934 /* Rx Packet Buffer Allocation size (KB) */
935 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
936
937 /* Determine the maximum latency tolerated by the device.
938 *
939 * Per the PCIe spec, the tolerated latencies are encoded as
940 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
941 * a 10-bit value (0-1023) to provide a range from 1 ns to
942 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
943 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
944 */
945 lat_ns = ((s64)rxa * 1024 -
946 (2 * (s64)hw->adapter->max_frame_size)) * 8 * 1000;
947 if (lat_ns < 0)
948 lat_ns = 0;
949 else
950 do_div(lat_ns, speed);
951
952 value = lat_ns;
953 while (value > PCI_LTR_VALUE_MASK) {
954 scale++;
955 value = DIV_ROUND_UP(value, (1 << 5));
956 }
957 if (scale > E1000_LTRV_SCALE_MAX) {
958 e_dbg("Invalid LTR latency scale %d\n", scale);
959 return -E1000_ERR_CONFIG;
960 }
961 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
962
963 /* Determine the maximum latency tolerated by the platform */
964 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
965 &max_snoop);
966 pci_read_config_word(hw->adapter->pdev,
967 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
968 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
969
970 if (lat_enc > max_ltr_enc)
971 lat_enc = max_ltr_enc;
972 }
973
974 /* Set Snoop and No-Snoop latencies the same */
975 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
976 ew32(LTRV, reg);
977
978 return 0;
979}
980
7d3cabbc
BA		 981/**
982 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
983 * @hw: pointer to the HW structure
984 *
985 * Checks to see of the link status of the hardware has changed. If a
986 * change in link status has been detected, then we read the PHY registers
987 * to get the current speed/duplex if link exists.
988 **/
989static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
990{
991 struct e1000_mac_info *mac = &hw->mac;
992 s32 ret_val;
993 bool link;
1d2101a7 994 u16 phy_reg;
7d3cabbc 995
e921eb1a 996 /* We only want to go out to the PHY registers to see if Auto-Neg
7d3cabbc
BA		 997 * has completed and/or if our link status has changed. The
998 * get_link_status flag is set upon receiving a Link Status
999 * Change or Rx Sequence Error interrupt.
1000 */
5015e53a
BA		 1001 if (!mac->get_link_status)
1002 return 0;
7d3cabbc 1003
e921eb1a 1004 /* First we want to see if the MII Status Register reports
7d3cabbc
BA		 1005 * link. If so, then we want to get the current speed/duplex
1006 * of the PHY.
1007 */
1008 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1009 if (ret_val)
5015e53a 1010 return ret_val;
7d3cabbc 1011
1d5846b9
BA		 1012 if (hw->mac.type == e1000_pchlan) {
1013 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1014 if (ret_val)
5015e53a 1015 return ret_val;
1d5846b9
BA		 1016 }
1017
772d05c5
BA		 1018 /* When connected at 10Mbps half-duplex, 82579 parts are excessively
1019 * aggressive resulting in many collisions. To avoid this, increase
1020 * the IPG and reduce Rx latency in the PHY.
1021 */
1022 if ((hw->mac.type == e1000_pch2lan) && link) {
1023 u32 reg;
1024 reg = er32(STATUS);
1025 if (!(reg & (E1000_STATUS_FD | E1000_STATUS_SPEED_MASK))) {
1026 reg = er32(TIPG);
1027 reg &= ~E1000_TIPG_IPGT_MASK;
1028 reg |= 0xFF;
1029 ew32(TIPG, reg);
1030
1031 /* Reduce Rx latency in analog PHY */
1032 ret_val = hw->phy.ops.acquire(hw);
1033 if (ret_val)
1034 return ret_val;
1035
1036 ret_val =
1037 e1000_write_emi_reg_locked(hw, I82579_RX_CONFIG, 0);
1038
1039 hw->phy.ops.release(hw);
1040
1041 if (ret_val)
1042 return ret_val;
1043 }
1044 }
1045
e08f626b
BA		 1046 /* Work-around I218 hang issue */
1047 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 1048 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1049 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1050 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
e08f626b
BA		 1051 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1052 if (ret_val)
1053 return ret_val;
1054 }
1055
cf8fb73c
BA		 1056 if (hw->mac.type == e1000_pch_lpt) {
1057 /* Set platform power management values for
1058 * Latency Tolerance Reporting (LTR)
1059 */
1060 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1061 if (ret_val)
1062 return ret_val;
1063 }
1064
2fbe4526
BA		 1065 /* Clear link partner's EEE ability */
1066 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1067
7d3cabbc 1068 if (!link)
e80bd1d1 1069 return 0; /* No link detected */
7d3cabbc
BA		 1070
1071 mac->get_link_status = false;
1072
1d2101a7
BA		 1073 switch (hw->mac.type) {
1074 case e1000_pch2lan:
831bd2e6
BA		 1075 ret_val = e1000_k1_workaround_lv(hw);
1076 if (ret_val)
5015e53a 1077 return ret_val;
1d2101a7
BA		 1078 /* fall-thru */
1079 case e1000_pchlan:
1080 if (hw->phy.type == e1000_phy_82578) {
1081 ret_val = e1000_link_stall_workaround_hv(hw);
1082 if (ret_val)
5015e53a 1083 return ret_val;
1d2101a7
BA		 1084 }
1085
e921eb1a 1086 /* Workaround for PCHx parts in half-duplex:
1d2101a7
BA		 1087 * Set the number of preambles removed from the packet
1088 * when it is passed from the PHY to the MAC to prevent
1089 * the MAC from misinterpreting the packet type.
1090 */
1091 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1092 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1093
1094 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1095 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1096
1097 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1098 break;
1099 default:
1100 break;
831bd2e6
BA		 1101 }
1102
e921eb1a 1103 /* Check if there was DownShift, must be checked
7d3cabbc
BA		 1104 * immediately after link-up
1105 */
1106 e1000e_check_downshift(hw);
1107
e52997f9
BA		 1108 /* Enable/Disable EEE after link up */
1109 ret_val = e1000_set_eee_pchlan(hw);
1110 if (ret_val)
5015e53a 1111 return ret_val;
e52997f9 1112
e921eb1a 1113 /* If we are forcing speed/duplex, then we simply return since
7d3cabbc
BA		 1114 * we have already determined whether we have link or not.
1115 */
5015e53a
BA		 1116 if (!mac->autoneg)
1117 return -E1000_ERR_CONFIG;
7d3cabbc 1118
e921eb1a 1119 /* Auto-Neg is enabled. Auto Speed Detection takes care
7d3cabbc
BA		 1120 * of MAC speed/duplex configuration. So we only need to
1121 * configure Collision Distance in the MAC.
1122 */
57cde763 1123 mac->ops.config_collision_dist(hw);
7d3cabbc 1124
e921eb1a 1125 /* Configure Flow Control now that Auto-Neg has completed.
7d3cabbc
BA		 1126 * First, we need to restore the desired flow control
1127 * settings because we may have had to re-autoneg with a
1128 * different link partner.
1129 */
1130 ret_val = e1000e_config_fc_after_link_up(hw);
1131 if (ret_val)
3bb99fe2 1132 e_dbg("Error configuring flow control\n");
7d3cabbc 1133
7d3cabbc
BA		 1134 return ret_val;
1135}
1136
69e3fd8c 1137static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 1138{
1139 struct e1000_hw *hw = &adapter->hw;
1140 s32 rc;
1141
ec34c170 1142 rc = e1000_init_mac_params_ich8lan(hw);
bc7f75fa
AK		 1143 if (rc)
1144 return rc;
1145
1146 rc = e1000_init_nvm_params_ich8lan(hw);
1147 if (rc)
1148 return rc;
1149
d3738bb8
BA		 1150 switch (hw->mac.type) {
1151 case e1000_ich8lan:
1152 case e1000_ich9lan:
1153 case e1000_ich10lan:
a4f58f54 1154 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 1155 break;
1156 case e1000_pchlan:
1157 case e1000_pch2lan:
2fbe4526 1158 case e1000_pch_lpt:
d3738bb8
BA		 1159 rc = e1000_init_phy_params_pchlan(hw);
1160 break;
1161 default:
1162 break;
1163 }
bc7f75fa
AK		 1164 if (rc)
1165 return rc;
1166
e921eb1a 1167 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
23e4f061
BA		 1168 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1169 */
1170 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1171 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1172 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
2adc55c9
BA		 1173 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1174 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
dbf80dcb
BA		 1175
1176 hw->mac.ops.blink_led = NULL;
2adc55c9
BA		 1177 }
1178
bc7f75fa 1179 if ((adapter->hw.mac.type == e1000_ich8lan) &&
462d5994 1180 (adapter->hw.phy.type != e1000_phy_ife))
bc7f75fa
AK		 1181 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1182
c6e7f51e
BA		 1183 /* Enable workaround for 82579 w/ ME enabled */
1184 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1185 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1186 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1187
bc7f75fa
AK		 1188 return 0;
1189}
1190
717d438d 1191static DEFINE_MUTEX(nvm_mutex);
717d438d 1192
ca15df58
BA		 1193/**
1194 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1195 * @hw: pointer to the HW structure
1196 *
1197 * Acquires the mutex for performing NVM operations.
1198 **/
8bb62869 1199static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1200{
1201 mutex_lock(&nvm_mutex);
1202
1203 return 0;
1204}
1205
1206/**
1207 * e1000_release_nvm_ich8lan - Release NVM mutex
1208 * @hw: pointer to the HW structure
1209 *
1210 * Releases the mutex used while performing NVM operations.
1211 **/
8bb62869 1212static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 1213{
1214 mutex_unlock(&nvm_mutex);
ca15df58
BA		 1215}
1216
bc7f75fa
AK		 1217/**
1218 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1219 * @hw: pointer to the HW structure
1220 *
ca15df58
BA		 1221 * Acquires the software control flag for performing PHY and select
1222 * MAC CSR accesses.
bc7f75fa
AK		 1223 **/
1224static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1225{
373a88d7
BA		 1226 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1227 s32 ret_val = 0;
bc7f75fa 1228
a90b412c
BA		 1229 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1230 &hw->adapter->state)) {
34c9ef8b 1231 e_dbg("contention for Phy access\n");
a90b412c
BA		 1232 return -E1000_ERR_PHY;
1233 }
717d438d 1234
bc7f75fa
AK		 1235 while (timeout) {
1236 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 1237 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1238 break;
bc7f75fa 1239
373a88d7
BA		 1240 mdelay(1);
1241 timeout--;
1242 }
1243
1244 if (!timeout) {
a90b412c 1245 e_dbg("SW has already locked the resource.\n");
373a88d7
BA		 1246 ret_val = -E1000_ERR_CONFIG;
1247 goto out;
1248 }
1249
53ac5a88 1250 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 1251
1252 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1253 ew32(EXTCNF_CTRL, extcnf_ctrl);
1254
1255 while (timeout) {
1256 extcnf_ctrl = er32(EXTCNF_CTRL);
1257 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1258 break;
a4f58f54 1259
bc7f75fa
AK		 1260 mdelay(1);
1261 timeout--;
1262 }
1263
1264 if (!timeout) {
434f1392 1265 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
a90b412c 1266 er32(FWSM), extcnf_ctrl);
2e2e8d53
BA		 1267 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1268 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 1269 ret_val = -E1000_ERR_CONFIG;
1270 goto out;
bc7f75fa
AK		 1271 }
1272
373a88d7
BA		 1273out:
1274 if (ret_val)
a90b412c 1275 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
373a88d7
BA		 1276
1277 return ret_val;
bc7f75fa
AK		 1278}
1279
1280/**
1281 * e1000_release_swflag_ich8lan - Release software control flag
1282 * @hw: pointer to the HW structure
1283 *
ca15df58
BA		 1284 * Releases the software control flag for performing PHY and select
1285 * MAC CSR accesses.
bc7f75fa
AK		 1286 **/
1287static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1288{
1289 u32 extcnf_ctrl;
1290
1291 extcnf_ctrl = er32(EXTCNF_CTRL);
c5caf482
BA		 1292
1293 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1294 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1295 ew32(EXTCNF_CTRL, extcnf_ctrl);
1296 } else {
1297 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1298 }
717d438d 1299
a90b412c 1300 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
bc7f75fa
AK		 1301}
1302
4662e82b
BA		 1303/**
1304 * e1000_check_mng_mode_ich8lan - Checks management mode
1305 * @hw: pointer to the HW structure
1306 *
eb7700dc 1307 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 1308 * This is a function pointer entry point only called by read/write
1309 * routines for the PHY and NVM parts.
1310 **/
1311static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1312{
a708dd88
BA		 1313 u32 fwsm;
1314
1315 fwsm = er32(FWSM);
f0ff4398
BA		 1316 return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1317 ((fwsm & E1000_FWSM_MODE_MASK) ==
1318 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
eb7700dc 1319}
4662e82b 1320
eb7700dc
BA		 1321/**
1322 * e1000_check_mng_mode_pchlan - Checks management mode
1323 * @hw: pointer to the HW structure
1324 *
1325 * This checks if the adapter has iAMT enabled.
1326 * This is a function pointer entry point only called by read/write
1327 * routines for the PHY and NVM parts.
1328 **/
1329static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1330{
1331 u32 fwsm;
1332
1333 fwsm = er32(FWSM);
1334 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
f0ff4398 1335 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 1336}
1337
69e1e019
BA		 1338/**
1339 * e1000_rar_set_pch2lan - Set receive address register
1340 * @hw: pointer to the HW structure
1341 * @addr: pointer to the receive address
1342 * @index: receive address array register
1343 *
1344 * Sets the receive address array register at index to the address passed
1345 * in by addr. For 82579, RAR[0] is the base address register that is to
1346 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1347 * Use SHRA[0-3] in place of those reserved for ME.
1348 **/
1349static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1350{
1351 u32 rar_low, rar_high;
1352
e921eb1a 1353 /* HW expects these in little endian so we reverse the byte order
69e1e019
BA		 1354 * from network order (big endian) to little endian
1355 */
1356 rar_low = ((u32)addr[0] |
1357 ((u32)addr[1] << 8) |
1358 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1359
1360 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1361
1362 /* If MAC address zero, no need to set the AV bit */
1363 if (rar_low || rar_high)
1364 rar_high |= E1000_RAH_AV;
1365
1366 if (index == 0) {
1367 ew32(RAL(index), rar_low);
1368 e1e_flush();
1369 ew32(RAH(index), rar_high);
1370 e1e_flush();
1371 return;
1372 }
1373
c3a0dce3
DE		 1374 /* RAR[1-6] are owned by manageability. Skip those and program the
1375 * next address into the SHRA register array.
1376 */
1377 if (index < (u32)(hw->mac.rar_entry_count - 6)) {
69e1e019
BA		 1378 s32 ret_val;
1379
1380 ret_val = e1000_acquire_swflag_ich8lan(hw);
1381 if (ret_val)
1382 goto out;
1383
1384 ew32(SHRAL(index - 1), rar_low);
1385 e1e_flush();
1386 ew32(SHRAH(index - 1), rar_high);
1387 e1e_flush();
1388
1389 e1000_release_swflag_ich8lan(hw);
1390
1391 /* verify the register updates */
1392 if ((er32(SHRAL(index - 1)) == rar_low) &&
1393 (er32(SHRAH(index - 1)) == rar_high))
1394 return;
1395
1396 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1397 (index - 1), er32(FWSM));
1398 }
1399
1400out:
1401 e_dbg("Failed to write receive address at index %d\n", index);
1402}
1403
2fbe4526
BA		 1404/**
1405 * e1000_rar_set_pch_lpt - Set receive address registers
1406 * @hw: pointer to the HW structure
1407 * @addr: pointer to the receive address
1408 * @index: receive address array register
1409 *
1410 * Sets the receive address register array at index to the address passed
1411 * in by addr. For LPT, RAR[0] is the base address register that is to
1412 * contain the MAC address. SHRA[0-10] are the shared receive address
1413 * registers that are shared between the Host and manageability engine (ME).
1414 **/
1415static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1416{
1417 u32 rar_low, rar_high;
1418 u32 wlock_mac;
1419
e921eb1a 1420 /* HW expects these in little endian so we reverse the byte order
2fbe4526
BA		 1421 * from network order (big endian) to little endian
1422 */
1423 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1424 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1425
1426 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1427
1428 /* If MAC address zero, no need to set the AV bit */
1429 if (rar_low || rar_high)
1430 rar_high |= E1000_RAH_AV;
1431
1432 if (index == 0) {
1433 ew32(RAL(index), rar_low);
1434 e1e_flush();
1435 ew32(RAH(index), rar_high);
1436 e1e_flush();
1437 return;
1438 }
1439
e921eb1a 1440 /* The manageability engine (ME) can lock certain SHRAR registers that
2fbe4526
BA		 1441 * it is using - those registers are unavailable for use.
1442 */
1443 if (index < hw->mac.rar_entry_count) {
1444 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1445 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1446
1447 /* Check if all SHRAR registers are locked */
1448 if (wlock_mac == 1)
1449 goto out;
1450
1451 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1452 s32 ret_val;
1453
1454 ret_val = e1000_acquire_swflag_ich8lan(hw);
1455
1456 if (ret_val)
1457 goto out;
1458
1459 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1460 e1e_flush();
1461 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1462 e1e_flush();
1463
1464 e1000_release_swflag_ich8lan(hw);
1465
1466 /* verify the register updates */
1467 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1468 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1469 return;
1470 }
1471 }
1472
1473out:
1474 e_dbg("Failed to write receive address at index %d\n", index);
1475}
1476
bc7f75fa
AK		 1477/**
1478 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1479 * @hw: pointer to the HW structure
1480 *
1481 * Checks if firmware is blocking the reset of the PHY.
1482 * This is a function pointer entry point only called by
1483 * reset routines.
1484 **/
1485static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1486{
1487 u32 fwsm;
1488
1489 fwsm = er32(FWSM);
1490
1491 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1492}
1493
8395ae83
BA		 1494/**
1495 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1496 * @hw: pointer to the HW structure
1497 *
1498 * Assumes semaphore already acquired.
1499 *
1500 **/
1501static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1502{
1503 u16 phy_data;
1504 u32 strap = er32(STRAP);
2fbe4526
BA		 1505 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1506 E1000_STRAP_SMT_FREQ_SHIFT;
70806a7f 1507 s32 ret_val;
8395ae83
BA		 1508
1509 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1510
1511 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1512 if (ret_val)
5015e53a 1513 return ret_val;
8395ae83
BA		 1514
1515 phy_data &= ~HV_SMB_ADDR_MASK;
1516 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1517 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
8395ae83 1518
2fbe4526
BA		 1519 if (hw->phy.type == e1000_phy_i217) {
1520 /* Restore SMBus frequency */
1521 if (freq--) {
1522 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1523 phy_data |= (freq & (1 << 0)) <<
1524 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1525 phy_data |= (freq & (1 << 1)) <<
1526 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1527 } else {
1528 e_dbg("Unsupported SMB frequency in PHY\n");
1529 }
1530 }
1531
5015e53a 1532 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
8395ae83
BA		 1533}
1534
f523d211
BA		 1535/**
1536 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1537 * @hw: pointer to the HW structure
1538 *
1539 * SW should configure the LCD from the NVM extended configuration region
1540 * as a workaround for certain parts.
1541 **/
1542static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1543{
1544 struct e1000_phy_info *phy = &hw->phy;
1545 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 1546 s32 ret_val = 0;
f523d211
BA		 1547 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1548
e921eb1a 1549 /* Initialize the PHY from the NVM on ICH platforms. This
f523d211
BA		 1550 * is needed due to an issue where the NVM configuration is
1551 * not properly autoloaded after power transitions.
1552 * Therefore, after each PHY reset, we will load the
1553 * configuration data out of the NVM manually.
1554 */
3f0c16e8
BA		 1555 switch (hw->mac.type) {
1556 case e1000_ich8lan:
1557 if (phy->type != e1000_phy_igp_3)
1558 return ret_val;
1559
5f3eed6f
BA		 1560 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1561 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 1562 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1563 break;
1564 }
1565 /* Fall-thru */
1566 case e1000_pchlan:
d3738bb8 1567 case e1000_pch2lan:
2fbe4526 1568 case e1000_pch_lpt:
8b802a7e 1569 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 1570 break;
1571 default:
1572 return ret_val;
1573 }
1574
1575 ret_val = hw->phy.ops.acquire(hw);
1576 if (ret_val)
1577 return ret_val;
8b802a7e
BA		 1578
1579 data = er32(FEXTNVM);
1580 if (!(data & sw_cfg_mask))
75ce1532 1581 goto release;
f523d211 1582
e921eb1a 1583 /* Make sure HW does not configure LCD from PHY
8b802a7e
BA		 1584 * extended configuration before SW configuration
1585 */
1586 data = er32(EXTCNF_CTRL);
2fbe4526
BA		 1587 if ((hw->mac.type < e1000_pch2lan) &&
1588 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1589 goto release;
8b802a7e
BA		 1590
1591 cnf_size = er32(EXTCNF_SIZE);
1592 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1593 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1594 if (!cnf_size)
75ce1532 1595 goto release;
8b802a7e
BA		 1596
1597 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1598 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1599
2fbe4526
BA		 1600 if (((hw->mac.type == e1000_pchlan) &&
1601 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1602 (hw->mac.type > e1000_pchlan)) {
e921eb1a 1603 /* HW configures the SMBus address and LEDs when the
8b802a7e
BA		 1604 * OEM and LCD Write Enable bits are set in the NVM.
1605 * When both NVM bits are cleared, SW will configure
1606 * them instead.
f523d211 1607 */
8395ae83 1608 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1609 if (ret_val)
75ce1532 1610 goto release;
f523d211 1611
8b802a7e
BA		 1612 data = er32(LEDCTL);
1613 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1614 (u16)data);
1615 if (ret_val)
75ce1532 1616 goto release;
8b802a7e 1617 }
f523d211 1618
8b802a7e
BA		 1619 /* Configure LCD from extended configuration region. */
1620
1621 /* cnf_base_addr is in DWORD */
1622 word_addr = (u16)(cnf_base_addr << 1);
1623
1624 for (i = 0; i < cnf_size; i++) {
e5fe2541 1625 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
8b802a7e 1626 if (ret_val)
75ce1532 1627 goto release;
8b802a7e
BA		 1628
1629 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1630 1, &reg_addr);
1631 if (ret_val)
75ce1532 1632 goto release;
8b802a7e
BA		 1633
1634 /* Save off the PHY page for future writes. */
1635 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1636 phy_page = reg_data;
1637 continue;
f523d211 1638 }
8b802a7e
BA		 1639
1640 reg_addr &= PHY_REG_MASK;
1641 reg_addr |= phy_page;
1642
f1430d69 1643 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
8b802a7e 1644 if (ret_val)
75ce1532 1645 goto release;
f523d211
BA		 1646 }
1647
75ce1532 1648release:
94d8186a 1649 hw->phy.ops.release(hw);
f523d211
BA		 1650 return ret_val;
1651}
1652
1d5846b9
BA		 1653/**
1654 * e1000_k1_gig_workaround_hv - K1 Si workaround
1655 * @hw: pointer to the HW structure
1656 * @link: link up bool flag
1657 *
1658 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1659 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1660 * If link is down, the function will restore the default K1 setting located
1661 * in the NVM.
1662 **/
1663static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1664{
1665 s32 ret_val = 0;
1666 u16 status_reg = 0;
1667 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1668
1669 if (hw->mac.type != e1000_pchlan)
5015e53a 1670 return 0;
1d5846b9
BA		 1671
1672 /* Wrap the whole flow with the sw flag */
94d8186a 1673 ret_val = hw->phy.ops.acquire(hw);
1d5846b9 1674 if (ret_val)
5015e53a 1675 return ret_val;
1d5846b9
BA		 1676
1677 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1678 if (link) {
1679 if (hw->phy.type == e1000_phy_82578) {
f1430d69
BA		 1680 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1681 &status_reg);
1d5846b9
BA		 1682 if (ret_val)
1683 goto release;
1684
f0ff4398
BA		 1685 status_reg &= (BM_CS_STATUS_LINK_UP |
1686 BM_CS_STATUS_RESOLVED |
1687 BM_CS_STATUS_SPEED_MASK);
1d5846b9
BA		 1688
1689 if (status_reg == (BM_CS_STATUS_LINK_UP |
f0ff4398
BA		 1690 BM_CS_STATUS_RESOLVED |
1691 BM_CS_STATUS_SPEED_1000))
1d5846b9
BA		 1692 k1_enable = false;
1693 }
1694
1695 if (hw->phy.type == e1000_phy_82577) {
f1430d69 1696 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1d5846b9
BA		 1697 if (ret_val)
1698 goto release;
1699
f0ff4398
BA		 1700 status_reg &= (HV_M_STATUS_LINK_UP |
1701 HV_M_STATUS_AUTONEG_COMPLETE |
1702 HV_M_STATUS_SPEED_MASK);
1d5846b9
BA		 1703
1704 if (status_reg == (HV_M_STATUS_LINK_UP |
f0ff4398
BA		 1705 HV_M_STATUS_AUTONEG_COMPLETE |
1706 HV_M_STATUS_SPEED_1000))
1d5846b9
BA		 1707 k1_enable = false;
1708 }
1709
1710 /* Link stall fix for link up */
f1430d69 1711 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1d5846b9
BA		 1712 if (ret_val)
1713 goto release;
1714
1715 } else {
1716 /* Link stall fix for link down */
f1430d69 1717 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1d5846b9
BA		 1718 if (ret_val)
1719 goto release;
1720 }
1721
1722 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1723
1724release:
94d8186a 1725 hw->phy.ops.release(hw);
5015e53a 1726
1d5846b9
BA		 1727 return ret_val;
1728}
1729
1730/**
1731 * e1000_configure_k1_ich8lan - Configure K1 power state
1732 * @hw: pointer to the HW structure
1733 * @enable: K1 state to configure
1734 *
1735 * Configure the K1 power state based on the provided parameter.
1736 * Assumes semaphore already acquired.
1737 *
1738 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1739 **/
bb436b20 1740s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9 1741{
70806a7f 1742 s32 ret_val;
1d5846b9
BA		 1743 u32 ctrl_reg = 0;
1744 u32 ctrl_ext = 0;
1745 u32 reg = 0;
1746 u16 kmrn_reg = 0;
1747
3d3a1676
BA		 1748 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1749 &kmrn_reg);
1d5846b9 1750 if (ret_val)
5015e53a 1751 return ret_val;
1d5846b9
BA		 1752
1753 if (k1_enable)
1754 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1755 else
1756 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1757
3d3a1676
BA		 1758 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1759 kmrn_reg);
1d5846b9 1760 if (ret_val)
5015e53a 1761 return ret_val;
1d5846b9 1762
ce43a216 1763 usleep_range(20, 40);
1d5846b9
BA		 1764 ctrl_ext = er32(CTRL_EXT);
1765 ctrl_reg = er32(CTRL);
1766
1767 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1768 reg |= E1000_CTRL_FRCSPD;
1769 ew32(CTRL, reg);
1770
1771 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
945a5151 1772 e1e_flush();
ce43a216 1773 usleep_range(20, 40);
1d5846b9
BA		 1774 ew32(CTRL, ctrl_reg);
1775 ew32(CTRL_EXT, ctrl_ext);
945a5151 1776 e1e_flush();
ce43a216 1777 usleep_range(20, 40);
1d5846b9 1778
5015e53a 1779 return 0;
1d5846b9
BA		 1780}
1781
f523d211
BA		 1782/**
1783 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1784 * @hw: pointer to the HW structure
1785 * @d0_state: boolean if entering d0 or d3 device state
1786 *
1787 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1788 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1789 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1790 **/
1791static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1792{
1793 s32 ret_val = 0;
1794 u32 mac_reg;
1795 u16 oem_reg;
1796
2fbe4526 1797 if (hw->mac.type < e1000_pchlan)
f523d211
BA		 1798 return ret_val;
1799
94d8186a 1800 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1801 if (ret_val)
1802 return ret_val;
1803
2fbe4526 1804 if (hw->mac.type == e1000_pchlan) {
d3738bb8
BA		 1805 mac_reg = er32(EXTCNF_CTRL);
1806 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
75ce1532 1807 goto release;
d3738bb8 1808 }
f523d211
BA		 1809
1810 mac_reg = er32(FEXTNVM);
1811 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
75ce1532 1812 goto release;
f523d211
BA		 1813
1814 mac_reg = er32(PHY_CTRL);
1815
f1430d69 1816 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211 1817 if (ret_val)
75ce1532 1818 goto release;
f523d211
BA		 1819
1820 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1821
1822 if (d0_state) {
1823 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1824 oem_reg |= HV_OEM_BITS_GBE_DIS;
1825
1826 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1827 oem_reg |= HV_OEM_BITS_LPLU;
1828 } else {
03299e46
BA		 1829 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1830 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
f523d211
BA		 1831 oem_reg |= HV_OEM_BITS_GBE_DIS;
1832
03299e46
BA		 1833 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1834 E1000_PHY_CTRL_NOND0A_LPLU))
f523d211
BA		 1835 oem_reg |= HV_OEM_BITS_LPLU;
1836 }
03299e46 1837
92fe1733
BA		 1838 /* Set Restart auto-neg to activate the bits */
1839 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1840 !hw->phy.ops.check_reset_block(hw))
1841 oem_reg |= HV_OEM_BITS_RESTART_AN;
1842
f1430d69 1843 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
f523d211 1844
75ce1532 1845release:
94d8186a 1846 hw->phy.ops.release(hw);
f523d211
BA		 1847
1848 return ret_val;
1849}
1850
fddaa1af
BA		 1851/**
1852 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1853 * @hw: pointer to the HW structure
1854 **/
1855static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1856{
1857 s32 ret_val;
1858 u16 data;
1859
1860 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1861 if (ret_val)
1862 return ret_val;
1863
1864 data |= HV_KMRN_MDIO_SLOW;
1865
1866 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1867
1868 return ret_val;
1869}
1870
a4f58f54
BA		 1871/**
1872 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1873 * done after every PHY reset.
1874 **/
1875static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1876{
1877 s32 ret_val = 0;
baf86c9d 1878 u16 phy_data;
a4f58f54
BA		 1879
1880 if (hw->mac.type != e1000_pchlan)
5015e53a 1881 return 0;
a4f58f54 1882
fddaa1af
BA		 1883 /* Set MDIO slow mode before any other MDIO access */
1884 if (hw->phy.type == e1000_phy_82577) {
1885 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1886 if (ret_val)
5015e53a 1887 return ret_val;
fddaa1af
BA		 1888 }
1889
a4f58f54
BA		 1890 if (((hw->phy.type == e1000_phy_82577) &&
1891 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1892 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1893 /* Disable generation of early preamble */
1894 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1895 if (ret_val)
1896 return ret_val;
1897
1898 /* Preamble tuning for SSC */
1d2101a7 1899 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
a4f58f54
BA		 1900 if (ret_val)
1901 return ret_val;
1902 }
1903
1904 if (hw->phy.type == e1000_phy_82578) {
e921eb1a 1905 /* Return registers to default by doing a soft reset then
a4f58f54
BA		 1906 * writing 0x3140 to the control register.
1907 */
1908 if (hw->phy.revision < 2) {
1909 e1000e_phy_sw_reset(hw);
c2ade1a4 1910 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
a4f58f54
BA		 1911 }
1912 }
1913
1914 /* Select page 0 */
94d8186a 1915 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1916 if (ret_val)
1917 return ret_val;
1d5846b9 1918
a4f58f54 1919 hw->phy.addr = 1;
1d5846b9 1920 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1921 hw->phy.ops.release(hw);
1d5846b9 1922 if (ret_val)
5015e53a 1923 return ret_val;
a4f58f54 1924
e921eb1a 1925 /* Configure the K1 Si workaround during phy reset assuming there is
1d5846b9
BA		 1926 * link so that it disables K1 if link is in 1Gbps.
1927 */
1928 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d 1929 if (ret_val)
5015e53a 1930 return ret_val;
1d5846b9 1931
baf86c9d
BA		 1932 /* Workaround for link disconnects on a busy hub in half duplex */
1933 ret_val = hw->phy.ops.acquire(hw);
1934 if (ret_val)
5015e53a 1935 return ret_val;
f1430d69 1936 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
baf86c9d
BA		 1937 if (ret_val)
1938 goto release;
f1430d69 1939 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
651fb102
BA		 1940 if (ret_val)
1941 goto release;
1942
1943 /* set MSE higher to enable link to stay up when noise is high */
1944 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
baf86c9d
BA		 1945release:
1946 hw->phy.ops.release(hw);
5015e53a 1947
a4f58f54
BA		 1948 return ret_val;
1949}
1950
d3738bb8
BA		 1951/**
1952 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1953 * @hw: pointer to the HW structure
1954 **/
1955void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1956{
1957 u32 mac_reg;
2b6b168d
BA		 1958 u16 i, phy_reg = 0;
1959 s32 ret_val;
1960
1961 ret_val = hw->phy.ops.acquire(hw);
1962 if (ret_val)
1963 return;
1964 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1965 if (ret_val)
1966 goto release;
d3738bb8 1967
c3a0dce3
DE		 1968 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
1969 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
d3738bb8 1970 mac_reg = er32(RAL(i));
2b6b168d
BA		 1971 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1972 (u16)(mac_reg & 0xFFFF));
1973 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1974 (u16)((mac_reg >> 16) & 0xFFFF));
1975
d3738bb8 1976 mac_reg = er32(RAH(i));
2b6b168d
BA		 1977 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1978 (u16)(mac_reg & 0xFFFF));
1979 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1980 (u16)((mac_reg & E1000_RAH_AV)
1981 >> 16));
d3738bb8 1982 }
2b6b168d
BA		 1983
1984 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1985
1986release:
1987 hw->phy.ops.release(hw);
d3738bb8
BA		 1988}
1989
d3738bb8
BA		 1990/**
1991 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1992 * with 82579 PHY
1993 * @hw: pointer to the HW structure
1994 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1995 **/
1996s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1997{
1998 s32 ret_val = 0;
1999 u16 phy_reg, data;
2000 u32 mac_reg;
2001 u16 i;
2002
2fbe4526 2003 if (hw->mac.type < e1000_pch2lan)
5015e53a 2004 return 0;
d3738bb8
BA		 2005
2006 /* disable Rx path while enabling/disabling workaround */
2007 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2008 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2009 if (ret_val)
5015e53a 2010 return ret_val;
d3738bb8
BA		 2011
2012 if (enable) {
c3a0dce3 2013 /* Write Rx addresses (rar_entry_count for RAL/H, and
d3738bb8
BA		 2014 * SHRAL/H) and initial CRC values to the MAC
2015 */
c3a0dce3 2016 for (i = 0; i < hw->mac.rar_entry_count; i++) {
362e20ca 2017 u8 mac_addr[ETH_ALEN] = { 0 };
d3738bb8
BA		 2018 u32 addr_high, addr_low;
2019
2020 addr_high = er32(RAH(i));
2021 if (!(addr_high & E1000_RAH_AV))
2022 continue;
2023 addr_low = er32(RAL(i));
2024 mac_addr[0] = (addr_low & 0xFF);
2025 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2026 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2027 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2028 mac_addr[4] = (addr_high & 0xFF);
2029 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2030
fe46f58f 2031 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
d3738bb8
BA		 2032 }
2033
2034 /* Write Rx addresses to the PHY */
2035 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2036
2037 /* Enable jumbo frame workaround in the MAC */
2038 mac_reg = er32(FFLT_DBG);
2039 mac_reg &= ~(1 << 14);
2040 mac_reg |= (7 << 15);
2041 ew32(FFLT_DBG, mac_reg);
2042
2043 mac_reg = er32(RCTL);
2044 mac_reg |= E1000_RCTL_SECRC;
2045 ew32(RCTL, mac_reg);
2046
2047 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2048 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2049 &data);
d3738bb8 2050 if (ret_val)
5015e53a 2051 return ret_val;
d3738bb8
BA		 2052 ret_val = e1000e_write_kmrn_reg(hw,
2053 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2054 data | (1 << 0));
2055 if (ret_val)
5015e53a 2056 return ret_val;
d3738bb8 2057 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2058 E1000_KMRNCTRLSTA_HD_CTRL,
2059 &data);
d3738bb8 2060 if (ret_val)
5015e53a 2061 return ret_val;
d3738bb8
BA		 2062 data &= ~(0xF << 8);
2063 data |= (0xB << 8);
2064 ret_val = e1000e_write_kmrn_reg(hw,
2065 E1000_KMRNCTRLSTA_HD_CTRL,
2066 data);
2067 if (ret_val)
5015e53a 2068 return ret_val;
d3738bb8
BA		 2069
2070 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 2071 e1e_rphy(hw, PHY_REG(769, 23), &data);
2072 data &= ~(0x7F << 5);
2073 data |= (0x37 << 5);
2074 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2075 if (ret_val)
5015e53a 2076 return ret_val;
d3738bb8
BA		 2077 e1e_rphy(hw, PHY_REG(769, 16), &data);
2078 data &= ~(1 << 13);
d3738bb8
BA		 2079 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2080 if (ret_val)
5015e53a 2081 return ret_val;
d3738bb8
BA		 2082 e1e_rphy(hw, PHY_REG(776, 20), &data);
2083 data &= ~(0x3FF << 2);
2084 data |= (0x1A << 2);
2085 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2086 if (ret_val)
5015e53a 2087 return ret_val;
b64e9dd5 2088 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
d3738bb8 2089 if (ret_val)
5015e53a 2090 return ret_val;
d3738bb8
BA		 2091 e1e_rphy(hw, HV_PM_CTRL, &data);
2092 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2093 if (ret_val)
5015e53a 2094 return ret_val;
d3738bb8
BA		 2095 } else {
2096 /* Write MAC register values back to h/w defaults */
2097 mac_reg = er32(FFLT_DBG);
2098 mac_reg &= ~(0xF << 14);
2099 ew32(FFLT_DBG, mac_reg);
2100
2101 mac_reg = er32(RCTL);
2102 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 2103 ew32(RCTL, mac_reg);
d3738bb8
BA		 2104
2105 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2106 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2107 &data);
d3738bb8 2108 if (ret_val)
5015e53a 2109 return ret_val;
d3738bb8
BA		 2110 ret_val = e1000e_write_kmrn_reg(hw,
2111 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2112 data & ~(1 << 0));
2113 if (ret_val)
5015e53a 2114 return ret_val;
d3738bb8 2115 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 2116 E1000_KMRNCTRLSTA_HD_CTRL,
2117 &data);
d3738bb8 2118 if (ret_val)
5015e53a 2119 return ret_val;
d3738bb8
BA		 2120 data &= ~(0xF << 8);
2121 data |= (0xB << 8);
2122 ret_val = e1000e_write_kmrn_reg(hw,
2123 E1000_KMRNCTRLSTA_HD_CTRL,
2124 data);
2125 if (ret_val)
5015e53a 2126 return ret_val;
d3738bb8
BA		 2127
2128 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 2129 e1e_rphy(hw, PHY_REG(769, 23), &data);
2130 data &= ~(0x7F << 5);
2131 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2132 if (ret_val)
5015e53a 2133 return ret_val;
d3738bb8 2134 e1e_rphy(hw, PHY_REG(769, 16), &data);
d3738bb8
BA		 2135 data |= (1 << 13);
2136 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2137 if (ret_val)
5015e53a 2138 return ret_val;
d3738bb8
BA		 2139 e1e_rphy(hw, PHY_REG(776, 20), &data);
2140 data &= ~(0x3FF << 2);
2141 data |= (0x8 << 2);
2142 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2143 if (ret_val)
5015e53a 2144 return ret_val;
d3738bb8
BA		 2145 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2146 if (ret_val)
5015e53a 2147 return ret_val;
d3738bb8
BA		 2148 e1e_rphy(hw, HV_PM_CTRL, &data);
2149 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2150 if (ret_val)
5015e53a 2151 return ret_val;
d3738bb8
BA		 2152 }
2153
2154 /* re-enable Rx path after enabling/disabling workaround */
5015e53a 2155 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
d3738bb8
BA		 2156}
2157
2158/**
2159 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2160 * done after every PHY reset.
2161 **/
2162static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2163{
2164 s32 ret_val = 0;
2165
2166 if (hw->mac.type != e1000_pch2lan)
5015e53a 2167 return 0;
d3738bb8
BA		 2168
2169 /* Set MDIO slow mode before any other MDIO access */
2170 ret_val = e1000_set_mdio_slow_mode_hv(hw);
8e5ab42d
BA		 2171 if (ret_val)
2172 return ret_val;
d3738bb8 2173
4d24136c
BA		 2174 ret_val = hw->phy.ops.acquire(hw);
2175 if (ret_val)
5015e53a 2176 return ret_val;
4d24136c 2177 /* set MSE higher to enable link to stay up when noise is high */
4ddc48a9 2178 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
4d24136c
BA		 2179 if (ret_val)
2180 goto release;
2181 /* drop link after 5 times MSE threshold was reached */
4ddc48a9 2182 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
4d24136c
BA		 2183release:
2184 hw->phy.ops.release(hw);
2185
d3738bb8
BA		 2186 return ret_val;
2187}
2188
831bd2e6
BA		 2189/**
2190 * e1000_k1_gig_workaround_lv - K1 Si workaround
2191 * @hw: pointer to the HW structure
2192 *
2193 * Workaround to set the K1 beacon duration for 82579 parts
2194 **/
2195static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2196{
2197 s32 ret_val = 0;
2198 u16 status_reg = 0;
2199 u32 mac_reg;
0ed013e2 2200 u16 phy_reg;
831bd2e6
BA		 2201
2202 if (hw->mac.type != e1000_pch2lan)
5015e53a 2203 return 0;
831bd2e6
BA		 2204
2205 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2206 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2207 if (ret_val)
5015e53a 2208 return ret_val;
831bd2e6
BA		 2209
2210 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2211 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2212 mac_reg = er32(FEXTNVM4);
2213 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2214
0ed013e2
BA		 2215 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2216 if (ret_val)
5015e53a 2217 return ret_val;
0ed013e2
BA		 2218
2219 if (status_reg & HV_M_STATUS_SPEED_1000) {
36ceeb43
BA		 2220 u16 pm_phy_reg;
2221
831bd2e6 2222 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
0ed013e2 2223 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
36ceeb43
BA		 2224 /* LV 1G Packet drop issue wa */
2225 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2226 if (ret_val)
2227 return ret_val;
2228 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2229 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2230 if (ret_val)
2231 return ret_val;
0ed013e2 2232 } else {
831bd2e6 2233 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
0ed013e2
BA		 2234 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2235 }
831bd2e6 2236 ew32(FEXTNVM4, mac_reg);
0ed013e2 2237 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
831bd2e6
BA		 2238 }
2239
831bd2e6
BA		 2240 return ret_val;
2241}
2242
605c82ba
BA		 2243/**
2244 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2245 * @hw: pointer to the HW structure
2246 * @gate: boolean set to true to gate, false to ungate
2247 *
2248 * Gate/ungate the automatic PHY configuration via hardware; perform
2249 * the configuration via software instead.
2250 **/
2251static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2252{
2253 u32 extcnf_ctrl;
2254
2fbe4526 2255 if (hw->mac.type < e1000_pch2lan)
605c82ba
BA		 2256 return;
2257
2258 extcnf_ctrl = er32(EXTCNF_CTRL);
2259
2260 if (gate)
2261 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2262 else
2263 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2264
2265 ew32(EXTCNF_CTRL, extcnf_ctrl);
605c82ba
BA		 2266}
2267
fc0c7760
BA		 2268/**
2269 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2270 * @hw: pointer to the HW structure
2271 *
2272 * Check the appropriate indication the MAC has finished configuring the
2273 * PHY after a software reset.
2274 **/
2275static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2276{
2277 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2278
2279 /* Wait for basic configuration completes before proceeding */
2280 do {
2281 data = er32(STATUS);
2282 data &= E1000_STATUS_LAN_INIT_DONE;
ce43a216 2283 usleep_range(100, 200);
fc0c7760
BA		 2284 } while ((!data) && --loop);
2285
e921eb1a 2286 /* If basic configuration is incomplete before the above loop
fc0c7760
BA		 2287 * count reaches 0, loading the configuration from NVM will
2288 * leave the PHY in a bad state possibly resulting in no link.
2289 */
2290 if (loop == 0)
3bb99fe2 2291 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 2292
2293 /* Clear the Init Done bit for the next init event */
2294 data = er32(STATUS);
2295 data &= ~E1000_STATUS_LAN_INIT_DONE;
2296 ew32(STATUS, data);
2297}
2298
bc7f75fa 2299/**
e98cac44 2300 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 2301 * @hw: pointer to the HW structure
bc7f75fa 2302 **/
e98cac44 2303static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 2304{
f523d211
BA		 2305 s32 ret_val = 0;
2306 u16 reg;
bc7f75fa 2307
44abd5c1 2308 if (hw->phy.ops.check_reset_block(hw))
5015e53a 2309 return 0;
fc0c7760 2310
5f3eed6f 2311 /* Allow time for h/w to get to quiescent state after reset */
1bba4386 2312 usleep_range(10000, 20000);
5f3eed6f 2313
fddaa1af 2314 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 2315 switch (hw->mac.type) {
2316 case e1000_pchlan:
a4f58f54
BA		 2317 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2318 if (ret_val)
5015e53a 2319 return ret_val;
e98cac44 2320 break;
d3738bb8
BA		 2321 case e1000_pch2lan:
2322 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2323 if (ret_val)
5015e53a 2324 return ret_val;
d3738bb8 2325 break;
e98cac44
BA		 2326 default:
2327 break;
a4f58f54
BA		 2328 }
2329
3ebfc7c9
BA		 2330 /* Clear the host wakeup bit after lcd reset */
2331 if (hw->mac.type >= e1000_pchlan) {
2332 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2333 reg &= ~BM_WUC_HOST_WU_BIT;
2334 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2335 }
db2932ec 2336
f523d211
BA		 2337 /* Configure the LCD with the extended configuration region in NVM */
2338 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2339 if (ret_val)
5015e53a 2340 return ret_val;
bc7f75fa 2341
f523d211 2342 /* Configure the LCD with the OEM bits in NVM */
e98cac44 2343 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 2344
1effb45c
BA		 2345 if (hw->mac.type == e1000_pch2lan) {
2346 /* Ungate automatic PHY configuration on non-managed 82579 */
2347 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1bba4386 2348 usleep_range(10000, 20000);
1effb45c
BA		 2349 e1000_gate_hw_phy_config_ich8lan(hw, false);
2350 }
2351
2352 /* Set EEE LPI Update Timer to 200usec */
2353 ret_val = hw->phy.ops.acquire(hw);
2354 if (ret_val)
5015e53a 2355 return ret_val;
4ddc48a9
BA		 2356 ret_val = e1000_write_emi_reg_locked(hw,
2357 I82579_LPI_UPDATE_TIMER,
2358 0x1387);
1effb45c 2359 hw->phy.ops.release(hw);
605c82ba
BA		 2360 }
2361
e98cac44
BA		 2362 return ret_val;
2363}
2364
2365/**
2366 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2367 * @hw: pointer to the HW structure
2368 *
2369 * Resets the PHY
2370 * This is a function pointer entry point called by drivers
2371 * or other shared routines.
2372 **/
2373static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2374{
2375 s32 ret_val = 0;
2376
605c82ba
BA		 2377 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2378 if ((hw->mac.type == e1000_pch2lan) &&
2379 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2380 e1000_gate_hw_phy_config_ich8lan(hw, true);
2381
e98cac44
BA		 2382 ret_val = e1000e_phy_hw_reset_generic(hw);
2383 if (ret_val)
5015e53a 2384 return ret_val;
e98cac44 2385
5015e53a 2386 return e1000_post_phy_reset_ich8lan(hw);
bc7f75fa
AK		 2387}
2388
fa2ce13c
BA		 2389/**
2390 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2391 * @hw: pointer to the HW structure
2392 * @active: true to enable LPLU, false to disable
2393 *
2394 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2395 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2396 * the phy speed. This function will manually set the LPLU bit and restart
2397 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2398 * since it configures the same bit.
2399 **/
2400static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2401{
70806a7f 2402 s32 ret_val;
fa2ce13c
BA		 2403 u16 oem_reg;
2404
2405 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2406 if (ret_val)
5015e53a 2407 return ret_val;
fa2ce13c
BA		 2408
2409 if (active)
2410 oem_reg |= HV_OEM_BITS_LPLU;
2411 else
2412 oem_reg &= ~HV_OEM_BITS_LPLU;
2413
44abd5c1 2414 if (!hw->phy.ops.check_reset_block(hw))
464c85e3
BA		 2415 oem_reg |= HV_OEM_BITS_RESTART_AN;
2416
5015e53a 2417 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
fa2ce13c
BA		 2418}
2419
bc7f75fa
AK		 2420/**
2421 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2422 * @hw: pointer to the HW structure
564ea9bb 2423 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2424 *
2425 * Sets the LPLU D0 state according to the active flag. When
2426 * activating LPLU this function also disables smart speed
2427 * and vice versa. LPLU will not be activated unless the
2428 * device autonegotiation advertisement meets standards of
2429 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2430 * This is a function pointer entry point only called by
2431 * PHY setup routines.
2432 **/
2433static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2434{
2435 struct e1000_phy_info *phy = &hw->phy;
2436 u32 phy_ctrl;
2437 s32 ret_val = 0;
2438 u16 data;
2439
97ac8cae 2440 if (phy->type == e1000_phy_ife)
82607255 2441 return 0;
bc7f75fa
AK		 2442
2443 phy_ctrl = er32(PHY_CTRL);
2444
2445 if (active) {
2446 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2447 ew32(PHY_CTRL, phy_ctrl);
2448
60f1292f
BA		 2449 if (phy->type != e1000_phy_igp_3)
2450 return 0;
2451
e921eb1a 2452 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2453 * any PHY registers
2454 */
60f1292f 2455 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2456 e1000e_gig_downshift_workaround_ich8lan(hw);
2457
2458 /* When LPLU is enabled, we should disable SmartSpeed */
2459 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
7dbbe5d5
BA		 2460 if (ret_val)
2461 return ret_val;
bc7f75fa
AK		 2462 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2463 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2464 if (ret_val)
2465 return ret_val;
2466 } else {
2467 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2468 ew32(PHY_CTRL, phy_ctrl);
2469
60f1292f
BA		 2470 if (phy->type != e1000_phy_igp_3)
2471 return 0;
2472
e921eb1a 2473 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2474 * during Dx states where the power conservation is most
2475 * important. During driver activity we should enable
ad68076e
BA		 2476 * SmartSpeed, so performance is maintained.
2477 */
bc7f75fa
AK		 2478 if (phy->smart_speed == e1000_smart_speed_on) {
2479 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2480 &data);
bc7f75fa
AK		 2481 if (ret_val)
2482 return ret_val;
2483
2484 data |= IGP01E1000_PSCFR_SMART_SPEED;
2485 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2486 data);
bc7f75fa
AK		 2487 if (ret_val)
2488 return ret_val;
2489 } else if (phy->smart_speed == e1000_smart_speed_off) {
2490 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2491 &data);
bc7f75fa
AK		 2492 if (ret_val)
2493 return ret_val;
2494
2495 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2496 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2497 data);
bc7f75fa
AK		 2498 if (ret_val)
2499 return ret_val;
2500 }
2501 }
2502
2503 return 0;
2504}
2505
2506/**
2507 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2508 * @hw: pointer to the HW structure
564ea9bb 2509 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2510 *
2511 * Sets the LPLU D3 state according to the active flag. When
2512 * activating LPLU this function also disables smart speed
2513 * and vice versa. LPLU will not be activated unless the
2514 * device autonegotiation advertisement meets standards of
2515 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2516 * This is a function pointer entry point only called by
2517 * PHY setup routines.
2518 **/
2519static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2520{
2521 struct e1000_phy_info *phy = &hw->phy;
2522 u32 phy_ctrl;
d7eb3384 2523 s32 ret_val = 0;
bc7f75fa
AK		 2524 u16 data;
2525
2526 phy_ctrl = er32(PHY_CTRL);
2527
2528 if (!active) {
2529 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2530 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 2531
2532 if (phy->type != e1000_phy_igp_3)
2533 return 0;
2534
e921eb1a 2535 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2536 * during Dx states where the power conservation is most
2537 * important. During driver activity we should enable
ad68076e
BA		 2538 * SmartSpeed, so performance is maintained.
2539 */
bc7f75fa 2540 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 2541 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2542 &data);
bc7f75fa
AK		 2543 if (ret_val)
2544 return ret_val;
2545
2546 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2547 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2548 data);
bc7f75fa
AK		 2549 if (ret_val)
2550 return ret_val;
2551 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 2552 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2553 &data);
bc7f75fa
AK		 2554 if (ret_val)
2555 return ret_val;
2556
2557 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2558 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2559 data);
bc7f75fa
AK		 2560 if (ret_val)
2561 return ret_val;
2562 }
2563 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2564 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2565 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2566 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2567 ew32(PHY_CTRL, phy_ctrl);
2568
60f1292f
BA		 2569 if (phy->type != e1000_phy_igp_3)
2570 return 0;
2571
e921eb1a 2572 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2573 * any PHY registers
2574 */
60f1292f 2575 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2576 e1000e_gig_downshift_workaround_ich8lan(hw);
2577
2578 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 2579 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 2580 if (ret_val)
2581 return ret_val;
2582
2583 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 2584 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 2585 }
2586
d7eb3384 2587 return ret_val;
bc7f75fa
AK		 2588}
2589
f4187b56
BA		 2590/**
2591 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2592 * @hw: pointer to the HW structure
2593 * @bank: pointer to the variable that returns the active bank
2594 *
2595 * Reads signature byte from the NVM using the flash access registers.
e243455d 2596 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 2597 **/
2598static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2599{
e243455d 2600 u32 eecd;
f4187b56 2601 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 2602 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2603 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d 2604 u8 sig_byte = 0;
f71dde6a 2605 s32 ret_val;
f4187b56 2606
e243455d
BA		 2607 switch (hw->mac.type) {
2608 case e1000_ich8lan:
2609 case e1000_ich9lan:
2610 eecd = er32(EECD);
2611 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2612 E1000_EECD_SEC1VAL_VALID_MASK) {
2613 if (eecd & E1000_EECD_SEC1VAL)
2614 *bank = 1;
2615 else
2616 *bank = 0;
2617
2618 return 0;
2619 }
434f1392 2620 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
e243455d
BA		 2621 /* fall-thru */
2622 default:
2623 /* set bank to 0 in case flash read fails */
2624 *bank = 0;
2625
2626 /* Check bank 0 */
2627 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
f0ff4398 2628 &sig_byte);
e243455d
BA		 2629 if (ret_val)
2630 return ret_val;
2631 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2632 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 2633 *bank = 0;
e243455d
BA		 2634 return 0;
2635 }
f4187b56 2636
e243455d
BA		 2637 /* Check bank 1 */
2638 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
f0ff4398
BA		 2639 bank1_offset,
2640 &sig_byte);
e243455d
BA		 2641 if (ret_val)
2642 return ret_val;
2643 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2644 E1000_ICH_NVM_SIG_VALUE) {
2645 *bank = 1;
2646 return 0;
f4187b56 2647 }
e243455d 2648
3bb99fe2 2649 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 2650 return -E1000_ERR_NVM;
f4187b56 2651 }
f4187b56
BA		 2652}
2653
bc7f75fa
AK		 2654/**
2655 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2656 * @hw: pointer to the HW structure
2657 * @offset: The offset (in bytes) of the word(s) to read.
2658 * @words: Size of data to read in words
2659 * @data: Pointer to the word(s) to read at offset.
2660 *
2661 * Reads a word(s) from the NVM using the flash access registers.
2662 **/
2663static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2664 u16 *data)
2665{
2666 struct e1000_nvm_info *nvm = &hw->nvm;
2667 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2668 u32 act_offset;
148675a7 2669 s32 ret_val = 0;
f4187b56 2670 u32 bank = 0;
bc7f75fa
AK		 2671 u16 i, word;
2672
2673 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2674 (words == 0)) {
3bb99fe2 2675 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 2676 ret_val = -E1000_ERR_NVM;
2677 goto out;
bc7f75fa
AK		 2678 }
2679
94d8186a 2680 nvm->ops.acquire(hw);
bc7f75fa 2681
f4187b56 2682 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 2683 if (ret_val) {
3bb99fe2 2684 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 2685 bank = 0;
2686 }
f4187b56
BA		 2687
2688 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 2689 act_offset += offset;
2690
148675a7 2691 ret_val = 0;
bc7f75fa 2692 for (i = 0; i < words; i++) {
362e20ca
BA		 2693 if (dev_spec->shadow_ram[offset + i].modified) {
2694 data[i] = dev_spec->shadow_ram[offset + i].value;
bc7f75fa
AK		 2695 } else {
2696 ret_val = e1000_read_flash_word_ich8lan(hw,
2697 act_offset + i,
2698 &word);
2699 if (ret_val)
2700 break;
2701 data[i] = word;
2702 }
2703 }
2704
94d8186a 2705 nvm->ops.release(hw);
bc7f75fa 2706
e243455d
BA		 2707out:
2708 if (ret_val)
3bb99fe2 2709 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2710
bc7f75fa
AK		 2711 return ret_val;
2712}
2713
2714/**
2715 * e1000_flash_cycle_init_ich8lan - Initialize flash
2716 * @hw: pointer to the HW structure
2717 *
2718 * This function does initial flash setup so that a new read/write/erase cycle
2719 * can be started.
2720 **/
2721static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2722{
2723 union ich8_hws_flash_status hsfsts;
2724 s32 ret_val = -E1000_ERR_NVM;
bc7f75fa
AK		 2725
2726 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2727
2728 /* Check if the flash descriptor is valid */
04499ec4 2729 if (!hsfsts.hsf_status.fldesvalid) {
434f1392 2730 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
bc7f75fa
AK		 2731 return -E1000_ERR_NVM;
2732 }
2733
2734 /* Clear FCERR and DAEL in hw status by writing 1 */
2735 hsfsts.hsf_status.flcerr = 1;
2736 hsfsts.hsf_status.dael = 1;
2737
2738 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2739
e921eb1a 2740 /* Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2741 * bit to check against, in order to start a new cycle or
2742 * FDONE bit should be changed in the hardware so that it
489815ce 2743 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2744 * indication whether a cycle is in progress or has been
2745 * completed.
2746 */
2747
04499ec4 2748 if (!hsfsts.hsf_status.flcinprog) {
e921eb1a 2749 /* There is no cycle running at present,
5ff5b664 2750 * so we can start a cycle.
ad68076e
BA		 2751 * Begin by setting Flash Cycle Done.
2752 */
bc7f75fa
AK		 2753 hsfsts.hsf_status.flcdone = 1;
2754 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2755 ret_val = 0;
2756 } else {
f71dde6a 2757 s32 i;
90da0669 2758
e921eb1a 2759 /* Otherwise poll for sometime so the current
ad68076e
BA		 2760 * cycle has a chance to end before giving up.
2761 */
bc7f75fa 2762 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
c8243ee0 2763 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2764 if (!hsfsts.hsf_status.flcinprog) {
bc7f75fa
AK		 2765 ret_val = 0;
2766 break;
2767 }
2768 udelay(1);
2769 }
9e2d7657 2770 if (!ret_val) {
e921eb1a 2771 /* Successful in waiting for previous cycle to timeout,
ad68076e
BA		 2772 * now set the Flash Cycle Done.
2773 */
bc7f75fa
AK		 2774 hsfsts.hsf_status.flcdone = 1;
2775 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2776 } else {
2c73e1fe 2777 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2778 }
2779 }
2780
2781 return ret_val;
2782}
2783
2784/**
2785 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2786 * @hw: pointer to the HW structure
2787 * @timeout: maximum time to wait for completion
2788 *
2789 * This function starts a flash cycle and waits for its completion.
2790 **/
2791static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2792{
2793 union ich8_hws_flash_ctrl hsflctl;
2794 union ich8_hws_flash_status hsfsts;
bc7f75fa
AK		 2795 u32 i = 0;
2796
2797 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2798 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2799 hsflctl.hsf_ctrl.flcgo = 1;
2800 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2801
2802 /* wait till FDONE bit is set to 1 */
2803 do {
2804 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2805 if (hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 2806 break;
2807 udelay(1);
2808 } while (i++ < timeout);
2809
04499ec4 2810 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 2811 return 0;
2812
55920b5e 2813 return -E1000_ERR_NVM;
bc7f75fa
AK		 2814}
2815
2816/**
2817 * e1000_read_flash_word_ich8lan - Read word from flash
2818 * @hw: pointer to the HW structure
2819 * @offset: offset to data location
2820 * @data: pointer to the location for storing the data
2821 *
2822 * Reads the flash word at offset into data. Offset is converted
2823 * to bytes before read.
2824 **/
2825static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2826 u16 *data)
2827{
2828 /* Must convert offset into bytes. */
2829 offset <<= 1;
2830
2831 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2832}
2833
f4187b56
BA		 2834/**
2835 * e1000_read_flash_byte_ich8lan - Read byte from flash
2836 * @hw: pointer to the HW structure
2837 * @offset: The offset of the byte to read.
2838 * @data: Pointer to a byte to store the value read.
2839 *
2840 * Reads a single byte from the NVM using the flash access registers.
2841 **/
2842static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2843 u8 *data)
2844{
2845 s32 ret_val;
2846 u16 word = 0;
2847
2848 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2849 if (ret_val)
2850 return ret_val;
2851
2852 *data = (u8)word;
2853
2854 return 0;
2855}
2856
bc7f75fa
AK		 2857/**
2858 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2859 * @hw: pointer to the HW structure
2860 * @offset: The offset (in bytes) of the byte or word to read.
2861 * @size: Size of data to read, 1=byte 2=word
2862 * @data: Pointer to the word to store the value read.
2863 *
2864 * Reads a byte or word from the NVM using the flash access registers.
2865 **/
2866static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2867 u8 size, u16 *data)
2868{
2869 union ich8_hws_flash_status hsfsts;
2870 union ich8_hws_flash_ctrl hsflctl;
2871 u32 flash_linear_addr;
2872 u32 flash_data = 0;
2873 s32 ret_val = -E1000_ERR_NVM;
2874 u8 count = 0;
2875
e80bd1d1 2876 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
bc7f75fa
AK		 2877 return -E1000_ERR_NVM;
2878
f0ff4398
BA		 2879 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2880 hw->nvm.flash_base_addr);
bc7f75fa
AK		 2881
2882 do {
2883 udelay(1);
2884 /* Steps */
2885 ret_val = e1000_flash_cycle_init_ich8lan(hw);
9e2d7657 2886 if (ret_val)
bc7f75fa
AK		 2887 break;
2888
2889 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2890 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2891 hsflctl.hsf_ctrl.fldbcount = size - 1;
2892 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2893 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2894
2895 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2896
17e813ec
BA		 2897 ret_val =
2898 e1000_flash_cycle_ich8lan(hw,
2899 ICH_FLASH_READ_COMMAND_TIMEOUT);
bc7f75fa 2900
e921eb1a 2901 /* Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2902 * and try the whole sequence a few more times, else
2903 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2904 * least significant byte first msb to lsb
2905 */
9e2d7657 2906 if (!ret_val) {
bc7f75fa 2907 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 2908 if (size == 1)
bc7f75fa 2909 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 2910 else if (size == 2)
bc7f75fa 2911 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 2912 break;
2913 } else {
e921eb1a 2914 /* If we've gotten here, then things are probably
bc7f75fa
AK		 2915 * completely hosed, but if the error condition is
2916 * detected, it won't hurt to give it another try...
2917 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2918 */
2919 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2920 if (hsfsts.hsf_status.flcerr) {
bc7f75fa
AK		 2921 /* Repeat for some time before giving up. */
2922 continue;
04499ec4 2923 } else if (!hsfsts.hsf_status.flcdone) {
434f1392 2924 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 2925 break;
2926 }
2927 }
2928 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2929
2930 return ret_val;
2931}
2932
2933/**
2934 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2935 * @hw: pointer to the HW structure
2936 * @offset: The offset (in bytes) of the word(s) to write.
2937 * @words: Size of data to write in words
2938 * @data: Pointer to the word(s) to write at offset.
2939 *
2940 * Writes a byte or word to the NVM using the flash access registers.
2941 **/
2942static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2943 u16 *data)
2944{
2945 struct e1000_nvm_info *nvm = &hw->nvm;
2946 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2947 u16 i;
2948
2949 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2950 (words == 0)) {
3bb99fe2 2951 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2952 return -E1000_ERR_NVM;
2953 }
2954
94d8186a 2955 nvm->ops.acquire(hw);
ca15df58 2956
bc7f75fa 2957 for (i = 0; i < words; i++) {
362e20ca
BA		 2958 dev_spec->shadow_ram[offset + i].modified = true;
2959 dev_spec->shadow_ram[offset + i].value = data[i];
bc7f75fa
AK		 2960 }
2961
94d8186a 2962 nvm->ops.release(hw);
ca15df58 2963
bc7f75fa
AK		 2964 return 0;
2965}
2966
2967/**
2968 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2969 * @hw: pointer to the HW structure
2970 *
2971 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2972 * which writes the checksum to the shadow ram. The changes in the shadow
2973 * ram are then committed to the EEPROM by processing each bank at a time
2974 * checking for the modified bit and writing only the pending changes.
489815ce 2975 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2976 * future writes.
2977 **/
2978static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2979{
2980 struct e1000_nvm_info *nvm = &hw->nvm;
2981 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2982 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2983 s32 ret_val;
2984 u16 data;
2985
2986 ret_val = e1000e_update_nvm_checksum_generic(hw);
2987 if (ret_val)
e243455d 2988 goto out;
bc7f75fa
AK		 2989
2990 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2991 goto out;
bc7f75fa 2992
94d8186a 2993 nvm->ops.acquire(hw);
bc7f75fa 2994
e921eb1a 2995 /* We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2996 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2997 * is going to be written
2998 */
e80bd1d1 2999 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 3000 if (ret_val) {
3bb99fe2 3001 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 3002 bank = 0;
e243455d 3003 }
f4187b56
BA		 3004
3005 if (bank == 0) {
bc7f75fa
AK		 3006 new_bank_offset = nvm->flash_bank_size;
3007 old_bank_offset = 0;
e243455d 3008 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 3009 if (ret_val)
3010 goto release;
bc7f75fa
AK		 3011 } else {
3012 old_bank_offset = nvm->flash_bank_size;
3013 new_bank_offset = 0;
e243455d 3014 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 3015 if (ret_val)
3016 goto release;
bc7f75fa
AK		 3017 }
3018
3019 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
e921eb1a 3020 /* Determine whether to write the value stored
bc7f75fa 3021 * in the other NVM bank or a modified value stored
ad68076e
BA		 3022 * in the shadow RAM
3023 */
bc7f75fa
AK		 3024 if (dev_spec->shadow_ram[i].modified) {
3025 data = dev_spec->shadow_ram[i].value;
3026 } else {
e243455d 3027 ret_val = e1000_read_flash_word_ich8lan(hw, i +
f0ff4398
BA		 3028 old_bank_offset,
3029 &data);
e243455d
BA		 3030 if (ret_val)
3031 break;
bc7f75fa
AK		 3032 }
3033
e921eb1a 3034 /* If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 3035 * (15:14) are 11b until the commit has completed.
3036 * This will allow us to write 10b which indicates the
3037 * signature is valid. We want to do this after the write
3038 * has completed so that we don't mark the segment valid
ad68076e
BA		 3039 * while the write is still in progress
3040 */
bc7f75fa
AK		 3041 if (i == E1000_ICH_NVM_SIG_WORD)
3042 data |= E1000_ICH_NVM_SIG_MASK;
3043
3044 /* Convert offset to bytes. */
3045 act_offset = (i + new_bank_offset) << 1;
3046
ce43a216 3047 usleep_range(100, 200);
bc7f75fa
AK		 3048 /* Write the bytes to the new bank. */
3049 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3050 act_offset,
3051 (u8)data);
3052 if (ret_val)
3053 break;
3054
ce43a216 3055 usleep_range(100, 200);
bc7f75fa 3056 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
f0ff4398
BA		 3057 act_offset + 1,
3058 (u8)(data >> 8));
bc7f75fa
AK		 3059 if (ret_val)
3060 break;
3061 }
3062
e921eb1a 3063 /* Don't bother writing the segment valid bits if sector
ad68076e
BA		 3064 * programming failed.
3065 */
bc7f75fa 3066 if (ret_val) {
4a770358 3067 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 3068 e_dbg("Flash commit failed.\n");
9c5e209d 3069 goto release;
bc7f75fa
AK		 3070 }
3071
e921eb1a 3072 /* Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 3073 * to 10b in word 0x13 , this can be done without an
3074 * erase as well since these bits are 11 to start with
ad68076e
BA		 3075 * and we need to change bit 14 to 0b
3076 */
bc7f75fa 3077 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 3078 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 3079 if (ret_val)
3080 goto release;
3081
bc7f75fa
AK		 3082 data &= 0xBFFF;
3083 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3084 act_offset * 2 + 1,
3085 (u8)(data >> 8));
9c5e209d
BA		 3086 if (ret_val)
3087 goto release;
bc7f75fa 3088
e921eb1a 3089 /* And invalidate the previously valid segment by setting
bc7f75fa
AK		 3090 * its signature word (0x13) high_byte to 0b. This can be
3091 * done without an erase because flash erase sets all bits
ad68076e
BA		 3092 * to 1's. We can write 1's to 0's without an erase
3093 */
bc7f75fa
AK		 3094 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3095 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 3096 if (ret_val)
3097 goto release;
bc7f75fa
AK		 3098
3099 /* Great! Everything worked, we can now clear the cached entries. */
3100 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 3101 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 3102 dev_spec->shadow_ram[i].value = 0xFFFF;
3103 }
3104
9c5e209d 3105release:
94d8186a 3106 nvm->ops.release(hw);
bc7f75fa 3107
e921eb1a 3108 /* Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 3109 * until after the next adapter reset.
3110 */
9c5e209d 3111 if (!ret_val) {
e85e3639 3112 nvm->ops.reload(hw);
1bba4386 3113 usleep_range(10000, 20000);
9c5e209d 3114 }
bc7f75fa 3115
e243455d
BA		 3116out:
3117 if (ret_val)
3bb99fe2 3118 e_dbg("NVM update error: %d\n", ret_val);
e243455d 3119
bc7f75fa
AK		 3120 return ret_val;
3121}
3122
3123/**
3124 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3125 * @hw: pointer to the HW structure
3126 *
3127 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3128 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3129 * calculated, in which case we need to calculate the checksum and set bit 6.
3130 **/
3131static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3132{
3133 s32 ret_val;
3134 u16 data;
1cc7a3a1
BA		 3135 u16 word;
3136 u16 valid_csum_mask;
bc7f75fa 3137
1cc7a3a1
BA		 3138 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3139 * the checksum needs to be fixed. This bit is an indication that
3140 * the NVM was prepared by OEM software and did not calculate
3141 * the checksum...a likely scenario.
bc7f75fa 3142 */
1cc7a3a1
BA		 3143 switch (hw->mac.type) {
3144 case e1000_pch_lpt:
3145 word = NVM_COMPAT;
3146 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3147 break;
3148 default:
3149 word = NVM_FUTURE_INIT_WORD1;
3150 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3151 break;
3152 }
3153
3154 ret_val = e1000_read_nvm(hw, word, 1, &data);
bc7f75fa
AK		 3155 if (ret_val)
3156 return ret_val;
3157
1cc7a3a1
BA		 3158 if (!(data & valid_csum_mask)) {
3159 data |= valid_csum_mask;
3160 ret_val = e1000_write_nvm(hw, word, 1, &data);
bc7f75fa
AK		 3161 if (ret_val)
3162 return ret_val;
3163 ret_val = e1000e_update_nvm_checksum(hw);
3164 if (ret_val)
3165 return ret_val;
3166 }
3167
3168 return e1000e_validate_nvm_checksum_generic(hw);
3169}
3170
4a770358
BA		 3171/**
3172 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3173 * @hw: pointer to the HW structure
3174 *
3175 * To prevent malicious write/erase of the NVM, set it to be read-only
3176 * so that the hardware ignores all write/erase cycles of the NVM via
3177 * the flash control registers. The shadow-ram copy of the NVM will
3178 * still be updated, however any updates to this copy will not stick
3179 * across driver reloads.
3180 **/
3181void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3182{
ca15df58 3183 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 3184 union ich8_flash_protected_range pr0;
3185 union ich8_hws_flash_status hsfsts;
3186 u32 gfpreg;
4a770358 3187
94d8186a 3188 nvm->ops.acquire(hw);
4a770358
BA		 3189
3190 gfpreg = er32flash(ICH_FLASH_GFPREG);
3191
3192 /* Write-protect GbE Sector of NVM */
3193 pr0.regval = er32flash(ICH_FLASH_PR0);
3194 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3195 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3196 pr0.range.wpe = true;
3197 ew32flash(ICH_FLASH_PR0, pr0.regval);
3198
e921eb1a 3199 /* Lock down a subset of GbE Flash Control Registers, e.g.
4a770358
BA		 3200 * PR0 to prevent the write-protection from being lifted.
3201 * Once FLOCKDN is set, the registers protected by it cannot
3202 * be written until FLOCKDN is cleared by a hardware reset.
3203 */
3204 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3205 hsfsts.hsf_status.flockdn = true;
3206 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3207
94d8186a 3208 nvm->ops.release(hw);
4a770358
BA		 3209}
3210
bc7f75fa
AK		 3211/**
3212 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3213 * @hw: pointer to the HW structure
3214 * @offset: The offset (in bytes) of the byte/word to read.
3215 * @size: Size of data to read, 1=byte 2=word
3216 * @data: The byte(s) to write to the NVM.
3217 *
3218 * Writes one/two bytes to the NVM using the flash access registers.
3219 **/
3220static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3221 u8 size, u16 data)
3222{
3223 union ich8_hws_flash_status hsfsts;
3224 union ich8_hws_flash_ctrl hsflctl;
3225 u32 flash_linear_addr;
3226 u32 flash_data = 0;
3227 s32 ret_val;
3228 u8 count = 0;
3229
3230 if (size < 1 || size > 2 || data > size * 0xff ||
3231 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3232 return -E1000_ERR_NVM;
3233
f0ff4398
BA		 3234 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3235 hw->nvm.flash_base_addr);
bc7f75fa
AK		 3236
3237 do {
3238 udelay(1);
3239 /* Steps */
3240 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3241 if (ret_val)
3242 break;
3243
3244 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3245 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
362e20ca 3246 hsflctl.hsf_ctrl.fldbcount = size - 1;
bc7f75fa
AK		 3247 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3248 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3249
3250 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3251
3252 if (size == 1)
3253 flash_data = (u32)data & 0x00FF;
3254 else
3255 flash_data = (u32)data;
3256
3257 ew32flash(ICH_FLASH_FDATA0, flash_data);
3258
e921eb1a 3259 /* check if FCERR is set to 1 , if set to 1, clear it
ad68076e
BA		 3260 * and try the whole sequence a few more times else done
3261 */
17e813ec
BA		 3262 ret_val =
3263 e1000_flash_cycle_ich8lan(hw,
3264 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
bc7f75fa
AK		 3265 if (!ret_val)
3266 break;
3267
e921eb1a 3268 /* If we're here, then things are most likely
bc7f75fa
AK		 3269 * completely hosed, but if the error condition
3270 * is detected, it won't hurt to give it another
3271 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3272 */
3273 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3274 if (hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 3275 /* Repeat for some time before giving up. */
3276 continue;
04499ec4 3277 if (!hsfsts.hsf_status.flcdone) {
434f1392 3278 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 3279 break;
3280 }
3281 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3282
3283 return ret_val;
3284}
3285
3286/**
3287 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3288 * @hw: pointer to the HW structure
3289 * @offset: The index of the byte to read.
3290 * @data: The byte to write to the NVM.
3291 *
3292 * Writes a single byte to the NVM using the flash access registers.
3293 **/
3294static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3295 u8 data)
3296{
3297 u16 word = (u16)data;
3298
3299 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3300}
3301
3302/**
3303 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3304 * @hw: pointer to the HW structure
3305 * @offset: The offset of the byte to write.
3306 * @byte: The byte to write to the NVM.
3307 *
3308 * Writes a single byte to the NVM using the flash access registers.
3309 * Goes through a retry algorithm before giving up.
3310 **/
3311static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3312 u32 offset, u8 byte)
3313{
3314 s32 ret_val;
3315 u16 program_retries;
3316
3317 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3318 if (!ret_val)
3319 return ret_val;
3320
3321 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 3322 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
ce43a216 3323 usleep_range(100, 200);
bc7f75fa
AK		 3324 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3325 if (!ret_val)
3326 break;
3327 }
3328 if (program_retries == 100)
3329 return -E1000_ERR_NVM;
3330
3331 return 0;
3332}
3333
3334/**
3335 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3336 * @hw: pointer to the HW structure
3337 * @bank: 0 for first bank, 1 for second bank, etc.
3338 *
3339 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3340 * bank N is 4096 * N + flash_reg_addr.
3341 **/
3342static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3343{
3344 struct e1000_nvm_info *nvm = &hw->nvm;
3345 union ich8_hws_flash_status hsfsts;
3346 union ich8_hws_flash_ctrl hsflctl;
3347 u32 flash_linear_addr;
3348 /* bank size is in 16bit words - adjust to bytes */
3349 u32 flash_bank_size = nvm->flash_bank_size * 2;
3350 s32 ret_val;
3351 s32 count = 0;
a708dd88 3352 s32 j, iteration, sector_size;
bc7f75fa
AK		 3353
3354 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3355
e921eb1a 3356 /* Determine HW Sector size: Read BERASE bits of hw flash status
ad68076e
BA		 3357 * register
3358 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 3359 * consecutive sectors. The start index for the nth Hw sector
3360 * can be calculated as = bank * 4096 + n * 256
3361 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3362 * The start index for the nth Hw sector can be calculated
3363 * as = bank * 4096
3364 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3365 * (ich9 only, otherwise error condition)
3366 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3367 */
3368 switch (hsfsts.hsf_status.berasesz) {
3369 case 0:
3370 /* Hw sector size 256 */
3371 sector_size = ICH_FLASH_SEG_SIZE_256;
3372 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3373 break;
3374 case 1:
3375 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 3376 iteration = 1;
bc7f75fa
AK		 3377 break;
3378 case 2:
148675a7
BA		 3379 sector_size = ICH_FLASH_SEG_SIZE_8K;
3380 iteration = 1;
bc7f75fa
AK		 3381 break;
3382 case 3:
3383 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 3384 iteration = 1;
bc7f75fa
AK		 3385 break;
3386 default:
3387 return -E1000_ERR_NVM;
3388 }
3389
3390 /* Start with the base address, then add the sector offset. */
3391 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 3392 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa 3393
53aa82da 3394 for (j = 0; j < iteration; j++) {
bc7f75fa 3395 do {
17e813ec
BA		 3396 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3397
bc7f75fa
AK		 3398 /* Steps */
3399 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3400 if (ret_val)
3401 return ret_val;
3402
e921eb1a 3403 /* Write a value 11 (block Erase) in Flash
ad68076e
BA		 3404 * Cycle field in hw flash control
3405 */
bc7f75fa
AK		 3406 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3407 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3408 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3409
e921eb1a 3410 /* Write the last 24 bits of an index within the
bc7f75fa
AK		 3411 * block into Flash Linear address field in Flash
3412 * Address.
3413 */
3414 flash_linear_addr += (j * sector_size);
3415 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3416
17e813ec 3417 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
9e2d7657 3418 if (!ret_val)
bc7f75fa
AK		 3419 break;
3420
e921eb1a 3421 /* Check if FCERR is set to 1. If 1,
bc7f75fa 3422 * clear it and try the whole sequence
ad68076e
BA		 3423 * a few more times else Done
3424 */
bc7f75fa 3425 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3426 if (hsfsts.hsf_status.flcerr)
ad68076e 3427 /* repeat for some time before giving up */
bc7f75fa 3428 continue;
04499ec4 3429 else if (!hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 3430 return ret_val;
3431 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3432 }
3433
3434 return 0;
3435}
3436
3437/**
3438 * e1000_valid_led_default_ich8lan - Set the default LED settings
3439 * @hw: pointer to the HW structure
3440 * @data: Pointer to the LED settings
3441 *
3442 * Reads the LED default settings from the NVM to data. If the NVM LED
3443 * settings is all 0's or F's, set the LED default to a valid LED default
3444 * setting.
3445 **/
3446static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3447{
3448 s32 ret_val;
3449
3450 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3451 if (ret_val) {
3bb99fe2 3452 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 3453 return ret_val;
3454 }
3455
e5fe2541 3456 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
bc7f75fa
AK		 3457 *data = ID_LED_DEFAULT_ICH8LAN;
3458
3459 return 0;
3460}
3461
a4f58f54
BA		 3462/**
3463 * e1000_id_led_init_pchlan - store LED configurations
3464 * @hw: pointer to the HW structure
3465 *
3466 * PCH does not control LEDs via the LEDCTL register, rather it uses
3467 * the PHY LED configuration register.
3468 *
3469 * PCH also does not have an "always on" or "always off" mode which
3470 * complicates the ID feature. Instead of using the "on" mode to indicate
d1964eb1 3471 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
a4f58f54
BA		 3472 * use "link_up" mode. The LEDs will still ID on request if there is no
3473 * link based on logic in e1000_led_[on|off]_pchlan().
3474 **/
3475static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3476{
3477 struct e1000_mac_info *mac = &hw->mac;
3478 s32 ret_val;
3479 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3480 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3481 u16 data, i, temp, shift;
3482
3483 /* Get default ID LED modes */
3484 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3485 if (ret_val)
5015e53a 3486 return ret_val;
a4f58f54
BA		 3487
3488 mac->ledctl_default = er32(LEDCTL);
3489 mac->ledctl_mode1 = mac->ledctl_default;
3490 mac->ledctl_mode2 = mac->ledctl_default;
3491
3492 for (i = 0; i < 4; i++) {
3493 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3494 shift = (i * 5);
3495 switch (temp) {
3496 case ID_LED_ON1_DEF2:
3497 case ID_LED_ON1_ON2:
3498 case ID_LED_ON1_OFF2:
3499 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3500 mac->ledctl_mode1 |= (ledctl_on << shift);
3501 break;
3502 case ID_LED_OFF1_DEF2:
3503 case ID_LED_OFF1_ON2:
3504 case ID_LED_OFF1_OFF2:
3505 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3506 mac->ledctl_mode1 |= (ledctl_off << shift);
3507 break;
3508 default:
3509 /* Do nothing */
3510 break;
3511 }
3512 switch (temp) {
3513 case ID_LED_DEF1_ON2:
3514 case ID_LED_ON1_ON2:
3515 case ID_LED_OFF1_ON2:
3516 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3517 mac->ledctl_mode2 |= (ledctl_on << shift);
3518 break;
3519 case ID_LED_DEF1_OFF2:
3520 case ID_LED_ON1_OFF2:
3521 case ID_LED_OFF1_OFF2:
3522 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3523 mac->ledctl_mode2 |= (ledctl_off << shift);
3524 break;
3525 default:
3526 /* Do nothing */
3527 break;
3528 }
3529 }
3530
5015e53a 3531 return 0;
a4f58f54
BA		 3532}
3533
bc7f75fa
AK		 3534/**
3535 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3536 * @hw: pointer to the HW structure
3537 *
3538 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3539 * register, so the the bus width is hard coded.
3540 **/
3541static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3542{
3543 struct e1000_bus_info *bus = &hw->bus;
3544 s32 ret_val;
3545
3546 ret_val = e1000e_get_bus_info_pcie(hw);
3547
e921eb1a 3548 /* ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 3549 * a configuration space, but do not contain
3550 * PCI Express Capability registers, so bus width
3551 * must be hardcoded.
3552 */
3553 if (bus->width == e1000_bus_width_unknown)
3554 bus->width = e1000_bus_width_pcie_x1;
3555
3556 return ret_val;
3557}
3558
3559/**
3560 * e1000_reset_hw_ich8lan - Reset the hardware
3561 * @hw: pointer to the HW structure
3562 *
3563 * Does a full reset of the hardware which includes a reset of the PHY and
3564 * MAC.
3565 **/
3566static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3567{
1d5846b9 3568 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
62bc813e
BA		 3569 u16 kum_cfg;
3570 u32 ctrl, reg;
bc7f75fa
AK		 3571 s32 ret_val;
3572
e921eb1a 3573 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 3574 * on the last TLP read/write transaction when MAC is reset.
3575 */
3576 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 3577 if (ret_val)
3bb99fe2 3578 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 3579
3bb99fe2 3580 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 3581 ew32(IMC, 0xffffffff);
3582
e921eb1a 3583 /* Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 3584 * any pending transactions to complete before we hit the MAC
3585 * with the global reset.
3586 */
3587 ew32(RCTL, 0);
3588 ew32(TCTL, E1000_TCTL_PSP);
3589 e1e_flush();
3590
1bba4386 3591 usleep_range(10000, 20000);
bc7f75fa
AK		 3592
3593 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3594 if (hw->mac.type == e1000_ich8lan) {
3595 /* Set Tx and Rx buffer allocation to 8k apiece. */
3596 ew32(PBA, E1000_PBA_8K);
3597 /* Set Packet Buffer Size to 16k. */
3598 ew32(PBS, E1000_PBS_16K);
3599 }
3600
1d5846b9 3601 if (hw->mac.type == e1000_pchlan) {
62bc813e
BA		 3602 /* Save the NVM K1 bit setting */
3603 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
1d5846b9
BA		 3604 if (ret_val)
3605 return ret_val;
3606
62bc813e 3607 if (kum_cfg & E1000_NVM_K1_ENABLE)
1d5846b9
BA		 3608 dev_spec->nvm_k1_enabled = true;
3609 else
3610 dev_spec->nvm_k1_enabled = false;
3611 }
3612
bc7f75fa
AK		 3613 ctrl = er32(CTRL);
3614
44abd5c1 3615 if (!hw->phy.ops.check_reset_block(hw)) {
e921eb1a 3616 /* Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 3617 * time to make sure the interface between MAC and the
3618 * external PHY is reset.
3619 */
3620 ctrl |= E1000_CTRL_PHY_RST;
605c82ba 3621
e921eb1a 3622 /* Gate automatic PHY configuration by hardware on
605c82ba
BA		 3623 * non-managed 82579
3624 */
3625 if ((hw->mac.type == e1000_pch2lan) &&
3626 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3627 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 3628 }
3629 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 3630 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa 3631 ew32(CTRL, (ctrl | E1000_CTRL_RST));
945a5151 3632 /* cannot issue a flush here because it hangs the hardware */
bc7f75fa
AK		 3633 msleep(20);
3634
62bc813e
BA		 3635 /* Set Phy Config Counter to 50msec */
3636 if (hw->mac.type == e1000_pch2lan) {
3637 reg = er32(FEXTNVM3);
3638 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3639 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3640 ew32(FEXTNVM3, reg);
3641 }
3642
fc0c7760 3643 if (!ret_val)
a90b412c 3644 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
37f40239 3645
e98cac44 3646 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 3647 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44 3648 if (ret_val)
5015e53a 3649 return ret_val;
fc0c7760 3650
e98cac44 3651 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211 3652 if (ret_val)
5015e53a 3653 return ret_val;
f523d211 3654 }
e98cac44 3655
e921eb1a 3656 /* For PCH, this write will make sure that any noise
7d3cabbc
BA		 3657 * will be detected as a CRC error and be dropped rather than show up
3658 * as a bad packet to the DMA engine.
3659 */
3660 if (hw->mac.type == e1000_pchlan)
3661 ew32(CRC_OFFSET, 0x65656565);
3662
bc7f75fa 3663 ew32(IMC, 0xffffffff);
dd93f95e 3664 er32(ICR);
bc7f75fa 3665
62bc813e
BA		 3666 reg = er32(KABGTXD);
3667 reg |= E1000_KABGTXD_BGSQLBIAS;
3668 ew32(KABGTXD, reg);
bc7f75fa 3669
5015e53a 3670 return 0;
bc7f75fa
AK		 3671}
3672
3673/**
3674 * e1000_init_hw_ich8lan - Initialize the hardware
3675 * @hw: pointer to the HW structure
3676 *
3677 * Prepares the hardware for transmit and receive by doing the following:
3678 * - initialize hardware bits
3679 * - initialize LED identification
3680 * - setup receive address registers
3681 * - setup flow control
489815ce 3682 * - setup transmit descriptors
bc7f75fa
AK		 3683 * - clear statistics
3684 **/
3685static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3686{
3687 struct e1000_mac_info *mac = &hw->mac;
3688 u32 ctrl_ext, txdctl, snoop;
3689 s32 ret_val;
3690 u16 i;
3691
3692 e1000_initialize_hw_bits_ich8lan(hw);
3693
3694 /* Initialize identification LED */
a4f58f54 3695 ret_val = mac->ops.id_led_init(hw);
33550cec 3696 /* An error is not fatal and we should not stop init due to this */
de39b752 3697 if (ret_val)
3bb99fe2 3698 e_dbg("Error initializing identification LED\n");
bc7f75fa
AK		 3699
3700 /* Setup the receive address. */
3701 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3702
3703 /* Zero out the Multicast HASH table */
3bb99fe2 3704 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3705 for (i = 0; i < mac->mta_reg_count; i++)
3706 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3707
e921eb1a 3708 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3ebfc7c9 3709 * the ME. Disable wakeup by clearing the host wakeup bit.
fc0c7760
BA		 3710 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3711 */
3712 if (hw->phy.type == e1000_phy_82578) {
3ebfc7c9
BA		 3713 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3714 i &= ~BM_WUC_HOST_WU_BIT;
3715 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fc0c7760
BA		 3716 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3717 if (ret_val)
3718 return ret_val;
3719 }
3720
bc7f75fa 3721 /* Setup link and flow control */
1a46b40f 3722 ret_val = mac->ops.setup_link(hw);
bc7f75fa
AK		 3723
3724 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3725 txdctl = er32(TXDCTL(0));
f0ff4398
BA		 3726 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3727 E1000_TXDCTL_FULL_TX_DESC_WB);
3728 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3729 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f
JK		 3730 ew32(TXDCTL(0), txdctl);
3731 txdctl = er32(TXDCTL(1));
f0ff4398
BA		 3732 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3733 E1000_TXDCTL_FULL_TX_DESC_WB);
3734 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3735 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f 3736 ew32(TXDCTL(1), txdctl);
bc7f75fa 3737
e921eb1a 3738 /* ICH8 has opposite polarity of no_snoop bits.
ad68076e
BA		 3739 * By default, we should use snoop behavior.
3740 */
bc7f75fa
AK		 3741 if (mac->type == e1000_ich8lan)
3742 snoop = PCIE_ICH8_SNOOP_ALL;
3743 else
53aa82da 3744 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
bc7f75fa
AK		 3745 e1000e_set_pcie_no_snoop(hw, snoop);
3746
3747 ctrl_ext = er32(CTRL_EXT);
3748 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3749 ew32(CTRL_EXT, ctrl_ext);
3750
e921eb1a 3751 /* Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3752 * important that we do this after we have tried to establish link
3753 * because the symbol error count will increment wildly if there
3754 * is no link.
3755 */
3756 e1000_clear_hw_cntrs_ich8lan(hw);
3757
e561a705 3758 return ret_val;
bc7f75fa 3759}
fc830b78 3760
bc7f75fa
AK		 3761/**
3762 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3763 * @hw: pointer to the HW structure
3764 *
3765 * Sets/Clears required hardware bits necessary for correctly setting up the
3766 * hardware for transmit and receive.
3767 **/
3768static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3769{
3770 u32 reg;
3771
3772 /* Extended Device Control */
3773 reg = er32(CTRL_EXT);
3774 reg |= (1 << 22);
a4f58f54
BA		 3775 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3776 if (hw->mac.type >= e1000_pchlan)
3777 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3778 ew32(CTRL_EXT, reg);
3779
3780 /* Transmit Descriptor Control 0 */
e9ec2c0f 3781 reg = er32(TXDCTL(0));
bc7f75fa 3782 reg |= (1 << 22);
e9ec2c0f 3783 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3784
3785 /* Transmit Descriptor Control 1 */
e9ec2c0f 3786 reg = er32(TXDCTL(1));
bc7f75fa 3787 reg |= (1 << 22);
e9ec2c0f 3788 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3789
3790 /* Transmit Arbitration Control 0 */
e9ec2c0f 3791 reg = er32(TARC(0));
bc7f75fa
AK		 3792 if (hw->mac.type == e1000_ich8lan)
3793 reg |= (1 << 28) | (1 << 29);
3794 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3795 ew32(TARC(0), reg);
bc7f75fa
AK		 3796
3797 /* Transmit Arbitration Control 1 */
e9ec2c0f 3798 reg = er32(TARC(1));
bc7f75fa
AK		 3799 if (er32(TCTL) & E1000_TCTL_MULR)
3800 reg &= ~(1 << 28);
3801 else
3802 reg |= (1 << 28);
3803 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3804 ew32(TARC(1), reg);
bc7f75fa
AK		 3805
3806 /* Device Status */
3807 if (hw->mac.type == e1000_ich8lan) {
3808 reg = er32(STATUS);
3809 reg &= ~(1 << 31);
3810 ew32(STATUS, reg);
3811 }
a80483d3 3812
e921eb1a 3813 /* work-around descriptor data corruption issue during nfs v2 udp
a80483d3
JB		 3814 * traffic, just disable the nfs filtering capability
3815 */
3816 reg = er32(RFCTL);
3817 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
f6bd5577 3818
e921eb1a 3819 /* Disable IPv6 extension header parsing because some malformed
f6bd5577
MV		 3820 * IPv6 headers can hang the Rx.
3821 */
3822 if (hw->mac.type == e1000_ich8lan)
3823 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
a80483d3 3824 ew32(RFCTL, reg);
94fb848b
BA		 3825
3826 /* Enable ECC on Lynxpoint */
3827 if (hw->mac.type == e1000_pch_lpt) {
3828 reg = er32(PBECCSTS);
3829 reg |= E1000_PBECCSTS_ECC_ENABLE;
3830 ew32(PBECCSTS, reg);
3831
3832 reg = er32(CTRL);
3833 reg |= E1000_CTRL_MEHE;
3834 ew32(CTRL, reg);
3835 }
bc7f75fa
AK		 3836}
3837
3838/**
3839 * e1000_setup_link_ich8lan - Setup flow control and link settings
3840 * @hw: pointer to the HW structure
3841 *
3842 * Determines which flow control settings to use, then configures flow
3843 * control. Calls the appropriate media-specific link configuration
3844 * function. Assuming the adapter has a valid link partner, a valid link
3845 * should be established. Assumes the hardware has previously been reset
3846 * and the transmitter and receiver are not enabled.
3847 **/
3848static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3849{
bc7f75fa
AK		 3850 s32 ret_val;
3851
44abd5c1 3852 if (hw->phy.ops.check_reset_block(hw))
bc7f75fa
AK		 3853 return 0;
3854
e921eb1a 3855 /* ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3856 * the default flow control setting, so we explicitly
3857 * set it to full.
3858 */
37289d9c
BA		 3859 if (hw->fc.requested_mode == e1000_fc_default) {
3860 /* Workaround h/w hang when Tx flow control enabled */
3861 if (hw->mac.type == e1000_pchlan)
3862 hw->fc.requested_mode = e1000_fc_rx_pause;
3863 else
3864 hw->fc.requested_mode = e1000_fc_full;
3865 }
bc7f75fa 3866
e921eb1a 3867 /* Save off the requested flow control mode for use later. Depending
5c48ef3e
BA		 3868 * on the link partner's capabilities, we may or may not use this mode.
3869 */
3870 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3871
17e813ec 3872 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
bc7f75fa
AK		 3873
3874 /* Continue to configure the copper link. */
944ce011 3875 ret_val = hw->mac.ops.setup_physical_interface(hw);
bc7f75fa
AK		 3876 if (ret_val)
3877 return ret_val;
3878
318a94d6 3879 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3880 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3881 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 3882 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 3883 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3884 ew32(FCRTV_PCH, hw->fc.refresh_time);
3885
482fed85
BA		 3886 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3887 hw->fc.pause_time);
a4f58f54
BA		 3888 if (ret_val)
3889 return ret_val;
3890 }
bc7f75fa
AK		 3891
3892 return e1000e_set_fc_watermarks(hw);
3893}
3894
3895/**
3896 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3897 * @hw: pointer to the HW structure
3898 *
3899 * Configures the kumeran interface to the PHY to wait the appropriate time
3900 * when polling the PHY, then call the generic setup_copper_link to finish
3901 * configuring the copper link.
3902 **/
3903static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3904{
3905 u32 ctrl;
3906 s32 ret_val;
3907 u16 reg_data;
3908
3909 ctrl = er32(CTRL);
3910 ctrl |= E1000_CTRL_SLU;
3911 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3912 ew32(CTRL, ctrl);
3913
e921eb1a 3914 /* Set the mac to wait the maximum time between each iteration
bc7f75fa 3915 * and increase the max iterations when polling the phy;
ad68076e
BA		 3916 * this fixes erroneous timeouts at 10Mbps.
3917 */
07818950 3918 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3919 if (ret_val)
3920 return ret_val;
07818950 3921 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 3922 &reg_data);
bc7f75fa
AK		 3923 if (ret_val)
3924 return ret_val;
3925 reg_data |= 0x3F;
07818950 3926 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 3927 reg_data);
bc7f75fa
AK		 3928 if (ret_val)
3929 return ret_val;
3930
a4f58f54
BA		 3931 switch (hw->phy.type) {
3932 case e1000_phy_igp_3:
bc7f75fa
AK		 3933 ret_val = e1000e_copper_link_setup_igp(hw);
3934 if (ret_val)
3935 return ret_val;
a4f58f54
BA		 3936 break;
3937 case e1000_phy_bm:
3938 case e1000_phy_82578:
97ac8cae
BA		 3939 ret_val = e1000e_copper_link_setup_m88(hw);
3940 if (ret_val)
3941 return ret_val;
a4f58f54
BA		 3942 break;
3943 case e1000_phy_82577:
d3738bb8 3944 case e1000_phy_82579:
a4f58f54
BA		 3945 ret_val = e1000_copper_link_setup_82577(hw);
3946 if (ret_val)
3947 return ret_val;
3948 break;
3949 case e1000_phy_ife:
482fed85 3950 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
97ac8cae
BA		 3951 if (ret_val)
3952 return ret_val;
3953
3954 reg_data &= ~IFE_PMC_AUTO_MDIX;
3955
3956 switch (hw->phy.mdix) {
3957 case 1:
3958 reg_data &= ~IFE_PMC_FORCE_MDIX;
3959 break;
3960 case 2:
3961 reg_data |= IFE_PMC_FORCE_MDIX;
3962 break;
3963 case 0:
3964 default:
3965 reg_data |= IFE_PMC_AUTO_MDIX;
3966 break;
3967 }
482fed85 3968 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
97ac8cae
BA		 3969 if (ret_val)
3970 return ret_val;
a4f58f54
BA		 3971 break;
3972 default:
3973 break;
97ac8cae 3974 }
3fa82936 3975
bc7f75fa
AK		 3976 return e1000e_setup_copper_link(hw);
3977}
3978
ea8179a7
BA		 3979/**
3980 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
3981 * @hw: pointer to the HW structure
3982 *
3983 * Calls the PHY specific link setup function and then calls the
3984 * generic setup_copper_link to finish configuring the link for
3985 * Lynxpoint PCH devices
3986 **/
3987static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
3988{
3989 u32 ctrl;
3990 s32 ret_val;
3991
3992 ctrl = er32(CTRL);
3993 ctrl |= E1000_CTRL_SLU;
3994 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3995 ew32(CTRL, ctrl);
3996
3997 ret_val = e1000_copper_link_setup_82577(hw);
3998 if (ret_val)
3999 return ret_val;
4000
4001 return e1000e_setup_copper_link(hw);
4002}
4003
bc7f75fa
AK		 4004/**
4005 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
4006 * @hw: pointer to the HW structure
4007 * @speed: pointer to store current link speed
4008 * @duplex: pointer to store the current link duplex
4009 *
ad68076e 4010 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 4011 * information and then calls the Kumeran lock loss workaround for links at
4012 * gigabit speeds.
4013 **/
4014static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
4015 u16 *duplex)
4016{
4017 s32 ret_val;
4018
4019 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
4020 if (ret_val)
4021 return ret_val;
4022
4023 if ((hw->mac.type == e1000_ich8lan) &&
e5fe2541 4024 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
bc7f75fa
AK		 4025 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
4026 }
4027
4028 return ret_val;
4029}
4030
4031/**
4032 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
4033 * @hw: pointer to the HW structure
4034 *
4035 * Work-around for 82566 Kumeran PCS lock loss:
4036 * On link status change (i.e. PCI reset, speed change) and link is up and
4037 * speed is gigabit-
4038 * 0) if workaround is optionally disabled do nothing
4039 * 1) wait 1ms for Kumeran link to come up
4040 * 2) check Kumeran Diagnostic register PCS lock loss bit
4041 * 3) if not set the link is locked (all is good), otherwise...
4042 * 4) reset the PHY
4043 * 5) repeat up to 10 times
4044 * Note: this is only called for IGP3 copper when speed is 1gb.
4045 **/
4046static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
4047{
4048 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4049 u32 phy_ctrl;
4050 s32 ret_val;
4051 u16 i, data;
4052 bool link;
4053
4054 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
4055 return 0;
4056
e921eb1a 4057 /* Make sure link is up before proceeding. If not just return.
bc7f75fa 4058 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 4059 * stability
4060 */
bc7f75fa
AK		 4061 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
4062 if (!link)
4063 return 0;
4064
4065 for (i = 0; i < 10; i++) {
4066 /* read once to clear */
4067 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4068 if (ret_val)
4069 return ret_val;
4070 /* and again to get new status */
4071 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
4072 if (ret_val)
4073 return ret_val;
4074
4075 /* check for PCS lock */
4076 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4077 return 0;
4078
4079 /* Issue PHY reset */
4080 e1000_phy_hw_reset(hw);
4081 mdelay(5);
4082 }
4083 /* Disable GigE link negotiation */
4084 phy_ctrl = er32(PHY_CTRL);
4085 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
4086 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4087 ew32(PHY_CTRL, phy_ctrl);
4088
e921eb1a 4089 /* Call gig speed drop workaround on Gig disable before accessing
ad68076e
BA		 4090 * any PHY registers
4091 */
bc7f75fa
AK		 4092 e1000e_gig_downshift_workaround_ich8lan(hw);
4093
4094 /* unable to acquire PCS lock */
4095 return -E1000_ERR_PHY;
4096}
4097
4098/**
6e3c8075 4099 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 4100 * @hw: pointer to the HW structure
489815ce 4101 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 4102 *
564ea9bb
BA		 4103 * If ICH8, set the current Kumeran workaround state (enabled - true
4104 * /disabled - false).
bc7f75fa
AK		 4105 **/
4106void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
17e813ec 4107 bool state)
bc7f75fa
AK		 4108{
4109 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4110
4111 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 4112 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 4113 return;
4114 }
4115
4116 dev_spec->kmrn_lock_loss_workaround_enabled = state;
4117}
4118
4119/**
4120 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
4121 * @hw: pointer to the HW structure
4122 *
4123 * Workaround for 82566 power-down on D3 entry:
4124 * 1) disable gigabit link
4125 * 2) write VR power-down enable
4126 * 3) read it back
4127 * Continue if successful, else issue LCD reset and repeat
4128 **/
4129void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
4130{
4131 u32 reg;
4132 u16 data;
e80bd1d1 4133 u8 retry = 0;
bc7f75fa
AK		 4134
4135 if (hw->phy.type != e1000_phy_igp_3)
4136 return;
4137
4138 /* Try the workaround twice (if needed) */
4139 do {
4140 /* Disable link */
4141 reg = er32(PHY_CTRL);
4142 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4143 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4144 ew32(PHY_CTRL, reg);
4145
e921eb1a 4146 /* Call gig speed drop workaround on Gig disable before
ad68076e
BA		 4147 * accessing any PHY registers
4148 */
bc7f75fa
AK		 4149 if (hw->mac.type == e1000_ich8lan)
4150 e1000e_gig_downshift_workaround_ich8lan(hw);
4151
4152 /* Write VR power-down enable */
4153 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4154 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4155 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4156
4157 /* Read it back and test */
4158 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4159 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4160 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4161 break;
4162
4163 /* Issue PHY reset and repeat at most one more time */
4164 reg = er32(CTRL);
4165 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4166 retry++;
4167 } while (retry);
4168}
4169
4170/**
4171 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4172 * @hw: pointer to the HW structure
4173 *
4174 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 4175 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 4176 * 1) Set Kumeran Near-end loopback
4177 * 2) Clear Kumeran Near-end loopback
462d5994 4178 * Should only be called for ICH8[m] devices with any 1G Phy.
bc7f75fa
AK		 4179 **/
4180void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4181{
4182 s32 ret_val;
4183 u16 reg_data;
4184
462d5994 4185 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
bc7f75fa
AK		 4186 return;
4187
4188 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 4189 &reg_data);
bc7f75fa
AK		 4190 if (ret_val)
4191 return;
4192 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4193 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 4194 reg_data);
bc7f75fa
AK		 4195 if (ret_val)
4196 return;
4197 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
7dbbe5d5 4198 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
bc7f75fa
AK		 4199}
4200
97ac8cae 4201/**
99730e4c 4202 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
97ac8cae
BA		 4203 * @hw: pointer to the HW structure
4204 *
4205 * During S0 to Sx transition, it is possible the link remains at gig
4206 * instead of negotiating to a lower speed. Before going to Sx, set
c077a906
BA		 4207 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4208 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4209 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4210 * needs to be written.
2fbe4526
BA		 4211 * Parts that support (and are linked to a partner which support) EEE in
4212 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4213 * than 10Mbps w/o EEE.
97ac8cae 4214 **/
99730e4c 4215void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
97ac8cae 4216{
2fbe4526 4217 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
97ac8cae 4218 u32 phy_ctrl;
8395ae83 4219 s32 ret_val;
97ac8cae 4220
17f085df 4221 phy_ctrl = er32(PHY_CTRL);
c077a906 4222 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
e08f626b 4223
2fbe4526 4224 if (hw->phy.type == e1000_phy_i217) {
e08f626b
BA		 4225 u16 phy_reg, device_id = hw->adapter->pdev->device;
4226
4227 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
91a3d82f
BA		 4228 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
4229 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
4230 (device_id == E1000_DEV_ID_PCH_I218_V3)) {
e08f626b
BA		 4231 u32 fextnvm6 = er32(FEXTNVM6);
4232
4233 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
4234 }
2fbe4526
BA		 4235
4236 ret_val = hw->phy.ops.acquire(hw);
4237 if (ret_val)
4238 goto out;
4239
4240 if (!dev_spec->eee_disable) {
4241 u16 eee_advert;
4242
4ddc48a9
BA		 4243 ret_val =
4244 e1000_read_emi_reg_locked(hw,
4245 I217_EEE_ADVERTISEMENT,
4246 &eee_advert);
2fbe4526
BA		 4247 if (ret_val)
4248 goto release;
2fbe4526 4249
e921eb1a 4250 /* Disable LPLU if both link partners support 100BaseT
2fbe4526
BA		 4251 * EEE and 100Full is advertised on both ends of the
4252 * link.
4253 */
3d4d5755 4254 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
2fbe4526 4255 (dev_spec->eee_lp_ability &
3d4d5755 4256 I82579_EEE_100_SUPPORTED) &&
2fbe4526
BA		 4257 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4258 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4259 E1000_PHY_CTRL_NOND0A_LPLU);
4260 }
4261
e921eb1a 4262 /* For i217 Intel Rapid Start Technology support,
2fbe4526
BA		 4263 * when the system is going into Sx and no manageability engine
4264 * is present, the driver must configure proxy to reset only on
4265 * power good. LPI (Low Power Idle) state must also reset only
4266 * on power good, as well as the MTA (Multicast table array).
4267 * The SMBus release must also be disabled on LCD reset.
4268 */
4269 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2fbe4526
BA		 4270 /* Enable proxy to reset only on power good. */
4271 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4272 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4273 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4274
e921eb1a 4275 /* Set bit enable LPI (EEE) to reset only on
2fbe4526
BA		 4276 * power good.
4277 */
4278 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
6d7407bf 4279 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
2fbe4526
BA		 4280 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4281
4282 /* Disable the SMB release on LCD reset. */
4283 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
6d7407bf 4284 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4285 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4286 }
4287
e921eb1a 4288 /* Enable MTA to reset for Intel Rapid Start Technology
2fbe4526
BA		 4289 * Support
4290 */
4291 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
6d7407bf 4292 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4293 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4294
4295release:
4296 hw->phy.ops.release(hw);
4297 }
4298out:
17f085df 4299 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 4300
462d5994
BA		 4301 if (hw->mac.type == e1000_ich8lan)
4302 e1000e_gig_downshift_workaround_ich8lan(hw);
4303
8395ae83 4304 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 4305 e1000_oem_bits_config_ich8lan(hw, false);
92fe1733
BA		 4306
4307 /* Reset PHY to activate OEM bits on 82577/8 */
4308 if (hw->mac.type == e1000_pchlan)
4309 e1000e_phy_hw_reset_generic(hw);
4310
8395ae83
BA		 4311 ret_val = hw->phy.ops.acquire(hw);
4312 if (ret_val)
4313 return;
4314 e1000_write_smbus_addr(hw);
4315 hw->phy.ops.release(hw);
4316 }
97ac8cae
BA		 4317}
4318
99730e4c
BA		 4319/**
4320 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4321 * @hw: pointer to the HW structure
4322 *
4323 * During Sx to S0 transitions on non-managed devices or managed devices
4324 * on which PHY resets are not blocked, if the PHY registers cannot be
4325 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4326 * the PHY.
2fbe4526 4327 * On i217, setup Intel Rapid Start Technology.
99730e4c
BA		 4328 **/
4329void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4330{
90b82984 4331 s32 ret_val;
99730e4c 4332
cb17aab9 4333 if (hw->mac.type < e1000_pch2lan)
99730e4c
BA		 4334 return;
4335
cb17aab9 4336 ret_val = e1000_init_phy_workarounds_pchlan(hw);
90b82984 4337 if (ret_val) {
cb17aab9 4338 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
90b82984
BA		 4339 return;
4340 }
2fbe4526 4341
e921eb1a 4342 /* For i217 Intel Rapid Start Technology support when the system
2fbe4526
BA		 4343 * is transitioning from Sx and no manageability engine is present
4344 * configure SMBus to restore on reset, disable proxy, and enable
4345 * the reset on MTA (Multicast table array).
4346 */
4347 if (hw->phy.type == e1000_phy_i217) {
4348 u16 phy_reg;
4349
4350 ret_val = hw->phy.ops.acquire(hw);
4351 if (ret_val) {
4352 e_dbg("Failed to setup iRST\n");
4353 return;
4354 }
4355
4356 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
e921eb1a 4357 /* Restore clear on SMB if no manageability engine
2fbe4526
BA		 4358 * is present
4359 */
4360 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4361 if (ret_val)
4362 goto release;
6d7407bf 4363 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4364 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4365
4366 /* Disable Proxy */
4367 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4368 }
4369 /* Enable reset on MTA */
4370 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4371 if (ret_val)
4372 goto release;
6d7407bf 4373 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4374 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4375release:
4376 if (ret_val)
4377 e_dbg("Error %d in resume workarounds\n", ret_val);
4378 hw->phy.ops.release(hw);
4379 }
99730e4c
BA		 4380}
4381
bc7f75fa
AK		 4382/**
4383 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4384 * @hw: pointer to the HW structure
4385 *
4386 * Return the LED back to the default configuration.
4387 **/
4388static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4389{
4390 if (hw->phy.type == e1000_phy_ife)
4391 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4392
4393 ew32(LEDCTL, hw->mac.ledctl_default);
4394 return 0;
4395}
4396
4397/**
489815ce 4398 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 4399 * @hw: pointer to the HW structure
4400 *
489815ce 4401 * Turn on the LEDs.
bc7f75fa
AK		 4402 **/
4403static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4404{
4405 if (hw->phy.type == e1000_phy_ife)
4406 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4407 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4408
4409 ew32(LEDCTL, hw->mac.ledctl_mode2);
4410 return 0;
4411}
4412
4413/**
489815ce 4414 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 4415 * @hw: pointer to the HW structure
4416 *
489815ce 4417 * Turn off the LEDs.
bc7f75fa
AK		 4418 **/
4419static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4420{
4421 if (hw->phy.type == e1000_phy_ife)
4422 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
482fed85
BA		 4423 (IFE_PSCL_PROBE_MODE |
4424 IFE_PSCL_PROBE_LEDS_OFF));
bc7f75fa
AK		 4425
4426 ew32(LEDCTL, hw->mac.ledctl_mode1);
4427 return 0;
4428}
4429
a4f58f54
BA		 4430/**
4431 * e1000_setup_led_pchlan - Configures SW controllable LED
4432 * @hw: pointer to the HW structure
4433 *
4434 * This prepares the SW controllable LED for use.
4435 **/
4436static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4437{
482fed85 4438 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
a4f58f54
BA		 4439}
4440
4441/**
4442 * e1000_cleanup_led_pchlan - Restore the default LED operation
4443 * @hw: pointer to the HW structure
4444 *
4445 * Return the LED back to the default configuration.
4446 **/
4447static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4448{
482fed85 4449 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
a4f58f54
BA		 4450}
4451
4452/**
4453 * e1000_led_on_pchlan - Turn LEDs on
4454 * @hw: pointer to the HW structure
4455 *
4456 * Turn on the LEDs.
4457 **/
4458static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4459{
4460 u16 data = (u16)hw->mac.ledctl_mode2;
4461 u32 i, led;
4462
e921eb1a 4463 /* If no link, then turn LED on by setting the invert bit
a4f58f54
BA		 4464 * for each LED that's mode is "link_up" in ledctl_mode2.
4465 */
4466 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4467 for (i = 0; i < 3; i++) {
4468 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4469 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4470 E1000_LEDCTL_MODE_LINK_UP)
4471 continue;
4472 if (led & E1000_PHY_LED0_IVRT)
4473 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4474 else
4475 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4476 }
4477 }
4478
482fed85 4479 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4480}
4481
4482/**
4483 * e1000_led_off_pchlan - Turn LEDs off
4484 * @hw: pointer to the HW structure
4485 *
4486 * Turn off the LEDs.
4487 **/
4488static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4489{
4490 u16 data = (u16)hw->mac.ledctl_mode1;
4491 u32 i, led;
4492
e921eb1a 4493 /* If no link, then turn LED off by clearing the invert bit
a4f58f54
BA		 4494 * for each LED that's mode is "link_up" in ledctl_mode1.
4495 */
4496 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4497 for (i = 0; i < 3; i++) {
4498 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4499 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4500 E1000_LEDCTL_MODE_LINK_UP)
4501 continue;
4502 if (led & E1000_PHY_LED0_IVRT)
4503 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4504 else
4505 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4506 }
4507 }
4508
482fed85 4509 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4510}
4511
f4187b56 4512/**
e98cac44 4513 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 4514 * @hw: pointer to the HW structure
4515 *
e98cac44
BA		 4516 * Read appropriate register for the config done bit for completion status
4517 * and configure the PHY through s/w for EEPROM-less parts.
4518 *
4519 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4520 * config done bit, so only an error is logged and continues. If we were
4521 * to return with error, EEPROM-less silicon would not be able to be reset
4522 * or change link.
f4187b56
BA		 4523 **/
4524static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4525{
e98cac44 4526 s32 ret_val = 0;
f4187b56 4527 u32 bank = 0;
e98cac44 4528 u32 status;
f4187b56 4529
fe90849f 4530 e1000e_get_cfg_done_generic(hw);
fc0c7760 4531
e98cac44
BA		 4532 /* Wait for indication from h/w that it has completed basic config */
4533 if (hw->mac.type >= e1000_ich10lan) {
4534 e1000_lan_init_done_ich8lan(hw);
4535 } else {
4536 ret_val = e1000e_get_auto_rd_done(hw);
4537 if (ret_val) {
e921eb1a 4538 /* When auto config read does not complete, do not
e98cac44
BA		 4539 * return with an error. This can happen in situations
4540 * where there is no eeprom and prevents getting link.
4541 */
4542 e_dbg("Auto Read Done did not complete\n");
4543 ret_val = 0;
4544 }
fc0c7760
BA		 4545 }
4546
e98cac44
BA		 4547 /* Clear PHY Reset Asserted bit */
4548 status = er32(STATUS);
4549 if (status & E1000_STATUS_PHYRA)
4550 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4551 else
4552 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 4553
4554 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 4555 if (hw->mac.type <= e1000_ich9lan) {
04499ec4 4556 if (!(er32(EECD) & E1000_EECD_PRES) &&
f4187b56
BA		 4557 (hw->phy.type == e1000_phy_igp_3)) {
4558 e1000e_phy_init_script_igp3(hw);
4559 }
4560 } else {
4561 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4562 /* Maybe we should do a basic PHY config */
3bb99fe2 4563 e_dbg("EEPROM not present\n");
e98cac44 4564 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 4565 }
4566 }
4567
e98cac44 4568 return ret_val;
f4187b56
BA		 4569}
4570
17f208de
BA		 4571/**
4572 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4573 * @hw: pointer to the HW structure
4574 *
4575 * In the case of a PHY power down to save power, or to turn off link during a
4576 * driver unload, or wake on lan is not enabled, remove the link.
4577 **/
4578static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4579{
4580 /* If the management interface is not enabled, then power down */
4581 if (!(hw->mac.ops.check_mng_mode(hw) ||
4582 hw->phy.ops.check_reset_block(hw)))
4583 e1000_power_down_phy_copper(hw);
17f208de
BA		 4584}
4585
bc7f75fa
AK		 4586/**
4587 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4588 * @hw: pointer to the HW structure
4589 *
4590 * Clears hardware counters specific to the silicon family and calls
4591 * clear_hw_cntrs_generic to clear all general purpose counters.
4592 **/
4593static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4594{
a4f58f54 4595 u16 phy_data;
2b6b168d 4596 s32 ret_val;
bc7f75fa
AK		 4597
4598 e1000e_clear_hw_cntrs_base(hw);
4599
99673d9b
BA		 4600 er32(ALGNERRC);
4601 er32(RXERRC);
4602 er32(TNCRS);
4603 er32(CEXTERR);
4604 er32(TSCTC);
4605 er32(TSCTFC);
bc7f75fa 4606
99673d9b
BA		 4607 er32(MGTPRC);
4608 er32(MGTPDC);
4609 er32(MGTPTC);
bc7f75fa 4610
99673d9b
BA		 4611 er32(IAC);
4612 er32(ICRXOC);
bc7f75fa 4613
a4f58f54
BA		 4614 /* Clear PHY statistics registers */
4615 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 4616 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 4617 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 4618 (hw->phy.type == e1000_phy_82577)) {
2b6b168d
BA		 4619 ret_val = hw->phy.ops.acquire(hw);
4620 if (ret_val)
4621 return;
4622 ret_val = hw->phy.ops.set_page(hw,
4623 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4624 if (ret_val)
4625 goto release;
4626 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4627 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4628 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4629 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4630 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4631 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4632 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4633 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4634 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4635 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4636 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4637 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4638 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4639 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4640release:
4641 hw->phy.ops.release(hw);
a4f58f54 4642 }
bc7f75fa
AK		 4643}
4644
8ce9d6c7 4645static const struct e1000_mac_operations ich8_mac_ops = {
eb7700dc 4646 /* check_mng_mode dependent on mac type */
7d3cabbc 4647 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 4648 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 4649 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4650 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 4651 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 4652 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 4653 /* led_on dependent on mac type */
4654 /* led_off dependent on mac type */
e2de3eb6 4655 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 4656 .reset_hw = e1000_reset_hw_ich8lan,
4657 .init_hw = e1000_init_hw_ich8lan,
4658 .setup_link = e1000_setup_link_ich8lan,
55c5f55e 4659 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
a4f58f54 4660 /* id_led_init dependent on mac type */
57cde763 4661 .config_collision_dist = e1000e_config_collision_dist_generic,
69e1e019 4662 .rar_set = e1000e_rar_set_generic,
bc7f75fa
AK		 4663};
4664
8ce9d6c7 4665static const struct e1000_phy_operations ich8_phy_ops = {
94d8186a 4666 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 4667 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 4668 .commit = NULL,
f4187b56 4669 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 4670 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 4671 .read_reg = e1000e_read_phy_reg_igp,
4672 .release = e1000_release_swflag_ich8lan,
4673 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 4674 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4675 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 4676 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 4677};
4678
8ce9d6c7 4679static const struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a 4680 .acquire = e1000_acquire_nvm_ich8lan,
55c5f55e 4681 .read = e1000_read_nvm_ich8lan,
94d8186a 4682 .release = e1000_release_nvm_ich8lan,
e85e3639 4683 .reload = e1000e_reload_nvm_generic,
94d8186a 4684 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 4685 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 4686 .validate = e1000_validate_nvm_checksum_ich8lan,
4687 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 4688};
4689
8ce9d6c7 4690const struct e1000_info e1000_ich8_info = {
bc7f75fa
AK		 4691 .mac = e1000_ich8lan,
4692 .flags = FLAG_HAS_WOL
97ac8cae 4693 | FLAG_IS_ICH
bc7f75fa
AK		 4694 | FLAG_HAS_CTRLEXT_ON_LOAD
4695 | FLAG_HAS_AMT
4696 | FLAG_HAS_FLASH
4697 | FLAG_APME_IN_WUC,
4698 .pba = 8,
2adc55c9 4699 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 4700 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4701 .mac_ops = &ich8_mac_ops,
4702 .phy_ops = &ich8_phy_ops,
4703 .nvm_ops = &ich8_nvm_ops,
4704};
4705
8ce9d6c7 4706const struct e1000_info e1000_ich9_info = {
bc7f75fa
AK		 4707 .mac = e1000_ich9lan,
4708 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 4709 | FLAG_IS_ICH
bc7f75fa 4710 | FLAG_HAS_WOL
bc7f75fa
AK		 4711 | FLAG_HAS_CTRLEXT_ON_LOAD
4712 | FLAG_HAS_AMT
bc7f75fa
AK		 4713 | FLAG_HAS_FLASH
4714 | FLAG_APME_IN_WUC,
7f1557e1 4715 .pba = 18,
2adc55c9 4716 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 4717 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4718 .mac_ops = &ich8_mac_ops,
4719 .phy_ops = &ich8_phy_ops,
4720 .nvm_ops = &ich8_nvm_ops,
4721};
4722
8ce9d6c7 4723const struct e1000_info e1000_ich10_info = {
f4187b56
BA		 4724 .mac = e1000_ich10lan,
4725 .flags = FLAG_HAS_JUMBO_FRAMES
4726 | FLAG_IS_ICH
4727 | FLAG_HAS_WOL
f4187b56
BA		 4728 | FLAG_HAS_CTRLEXT_ON_LOAD
4729 | FLAG_HAS_AMT
f4187b56
BA		 4730 | FLAG_HAS_FLASH
4731 | FLAG_APME_IN_WUC,
7f1557e1 4732 .pba = 18,
2adc55c9 4733 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 4734 .get_variants = e1000_get_variants_ich8lan,
4735 .mac_ops = &ich8_mac_ops,
4736 .phy_ops = &ich8_phy_ops,
4737 .nvm_ops = &ich8_nvm_ops,
4738};
a4f58f54 4739
8ce9d6c7 4740const struct e1000_info e1000_pch_info = {
a4f58f54
BA		 4741 .mac = e1000_pchlan,
4742 .flags = FLAG_IS_ICH
4743 | FLAG_HAS_WOL
a4f58f54
BA		 4744 | FLAG_HAS_CTRLEXT_ON_LOAD
4745 | FLAG_HAS_AMT
4746 | FLAG_HAS_FLASH
4747 | FLAG_HAS_JUMBO_FRAMES
38eb394e 4748 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 4749 | FLAG_APME_IN_WUC,
8c7bbb92 4750 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 4751 .pba = 26,
4752 .max_hw_frame_size = 4096,
4753 .get_variants = e1000_get_variants_ich8lan,
4754 .mac_ops = &ich8_mac_ops,
4755 .phy_ops = &ich8_phy_ops,
4756 .nvm_ops = &ich8_nvm_ops,
4757};
d3738bb8 4758
8ce9d6c7 4759const struct e1000_info e1000_pch2_info = {
d3738bb8
BA		 4760 .mac = e1000_pch2lan,
4761 .flags = FLAG_IS_ICH
4762 | FLAG_HAS_WOL
b67e1913 4763 | FLAG_HAS_HW_TIMESTAMP
d3738bb8
BA		 4764 | FLAG_HAS_CTRLEXT_ON_LOAD
4765 | FLAG_HAS_AMT
4766 | FLAG_HAS_FLASH
4767 | FLAG_HAS_JUMBO_FRAMES
4768 | FLAG_APME_IN_WUC,
e52997f9
BA		 4769 .flags2 = FLAG2_HAS_PHY_STATS
4770 | FLAG2_HAS_EEE,
828bac87 4771 .pba = 26,
c3d2dbf4 4772 .max_hw_frame_size = 9018,
d3738bb8
BA		 4773 .get_variants = e1000_get_variants_ich8lan,
4774 .mac_ops = &ich8_mac_ops,
4775 .phy_ops = &ich8_phy_ops,
4776 .nvm_ops = &ich8_nvm_ops,
4777};
2fbe4526
BA		 4778
4779const struct e1000_info e1000_pch_lpt_info = {
4780 .mac = e1000_pch_lpt,
4781 .flags = FLAG_IS_ICH
4782 | FLAG_HAS_WOL
b67e1913 4783 | FLAG_HAS_HW_TIMESTAMP
2fbe4526
BA		 4784 | FLAG_HAS_CTRLEXT_ON_LOAD
4785 | FLAG_HAS_AMT
4786 | FLAG_HAS_FLASH
4787 | FLAG_HAS_JUMBO_FRAMES
4788 | FLAG_APME_IN_WUC,
4789 .flags2 = FLAG2_HAS_PHY_STATS
4790 | FLAG2_HAS_EEE,
4791 .pba = 26,
ed1a4265 4792 .max_hw_frame_size = 9018,
2fbe4526
BA		 4793 .get_variants = e1000_get_variants_ich8lan,
4794 .mac_ops = &ich8_mac_ops,
4795 .phy_ops = &ich8_phy_ops,
4796 .nvm_ops = &ich8_nvm_ops,
4797};
Linux kernel - Deliverables
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