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e1000e: cleanup unnecessary line breaks
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
e921eb1a 29/* 82562G 10/100 Network Connection
bc7f75fa
AK		 30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
97ac8cae
BA		 41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
1605927f 43 * 82567V Gigabit Network Connection
97ac8cae
BA		 44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
2f15f9d6 49 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
d3738bb8
BA		 54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
bc7f75fa
AK		 56 */
57
bc7f75fa
AK		 58#include "e1000.h"
59
bc7f75fa
AK		 60/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
61/* Offset 04h HSFSTS */
62union ich8_hws_flash_status {
63 struct ich8_hsfsts {
362e20ca
BA		 64 u16 flcdone:1; /* bit 0 Flash Cycle Done */
65 u16 flcerr:1; /* bit 1 Flash Cycle Error */
66 u16 dael:1; /* bit 2 Direct Access error Log */
67 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
68 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
69 u16 reserved1:2; /* bit 13:6 Reserved */
70 u16 reserved2:6; /* bit 13:6 Reserved */
71 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
72 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
bc7f75fa
AK		 73 } hsf_status;
74 u16 regval;
75};
76
77/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
78/* Offset 06h FLCTL */
79union ich8_hws_flash_ctrl {
80 struct ich8_hsflctl {
362e20ca
BA		 81 u16 flcgo:1; /* 0 Flash Cycle Go */
82 u16 flcycle:2; /* 2:1 Flash Cycle */
83 u16 reserved:5; /* 7:3 Reserved */
84 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
85 u16 flockdn:6; /* 15:10 Reserved */
bc7f75fa
AK		 86 } hsf_ctrl;
87 u16 regval;
88};
89
90/* ICH Flash Region Access Permissions */
91union ich8_hws_flash_regacc {
92 struct ich8_flracc {
362e20ca
BA		 93 u32 grra:8; /* 0:7 GbE region Read Access */
94 u32 grwa:8; /* 8:15 GbE region Write Access */
95 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
96 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
bc7f75fa
AK		 97 } hsf_flregacc;
98 u16 regval;
99};
100
4a770358
BA		 101/* ICH Flash Protected Region */
102union ich8_flash_protected_range {
103 struct ich8_pr {
104 u32 base:13; /* 0:12 Protected Range Base */
105 u32 reserved1:2; /* 13:14 Reserved */
106 u32 rpe:1; /* 15 Read Protection Enable */
107 u32 limit:13; /* 16:28 Protected Range Limit */
108 u32 reserved2:2; /* 29:30 Reserved */
109 u32 wpe:1; /* 31 Write Protection Enable */
110 } range;
111 u32 regval;
112};
113
bc7f75fa
AK		 114static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
115static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 116static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
117static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
118 u32 offset, u8 byte);
f4187b56
BA		 119static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
120 u8 *data);
bc7f75fa
AK		 121static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
122 u16 *data);
123static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
124 u8 size, u16 *data);
bc7f75fa 125static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 126static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
127static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
128static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
129static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
130static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
131static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
132static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
133static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 134static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 135static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 136static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1f96012d 137static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 138static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 139static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
140static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
69e1e019 141static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
2fbe4526 142static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
831bd2e6 143static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 144static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
bc7f75fa
AK		 145
146static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
147{
148 return readw(hw->flash_address + reg);
149}
150
151static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
152{
153 return readl(hw->flash_address + reg);
154}
155
156static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
157{
158 writew(val, hw->flash_address + reg);
159}
160
161static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
162{
163 writel(val, hw->flash_address + reg);
164}
165
166#define er16flash(reg) __er16flash(hw, (reg))
167#define er32flash(reg) __er32flash(hw, (reg))
0e15df49
BA		 168#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
169#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
bc7f75fa 170
cb17aab9
BA		 171/**
172 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
173 * @hw: pointer to the HW structure
174 *
175 * Test access to the PHY registers by reading the PHY ID registers. If
176 * the PHY ID is already known (e.g. resume path) compare it with known ID,
177 * otherwise assume the read PHY ID is correct if it is valid.
178 *
179 * Assumes the sw/fw/hw semaphore is already acquired.
180 **/
181static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
99730e4c 182{
a52359b5
BA		 183 u16 phy_reg = 0;
184 u32 phy_id = 0;
185 s32 ret_val;
186 u16 retry_count;
187
188 for (retry_count = 0; retry_count < 2; retry_count++) {
c2ade1a4 189 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
a52359b5
BA		 190 if (ret_val || (phy_reg == 0xFFFF))
191 continue;
192 phy_id = (u32)(phy_reg << 16);
193
c2ade1a4 194 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
a52359b5
BA		 195 if (ret_val || (phy_reg == 0xFFFF)) {
196 phy_id = 0;
197 continue;
198 }
199 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
200 break;
201 }
cb17aab9
BA		 202
203 if (hw->phy.id) {
204 if (hw->phy.id == phy_id)
205 return true;
a52359b5
BA		 206 } else if (phy_id) {
207 hw->phy.id = phy_id;
208 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
cb17aab9
BA		 209 return true;
210 }
211
e921eb1a 212 /* In case the PHY needs to be in mdio slow mode,
a52359b5
BA		 213 * set slow mode and try to get the PHY id again.
214 */
215 hw->phy.ops.release(hw);
216 ret_val = e1000_set_mdio_slow_mode_hv(hw);
217 if (!ret_val)
218 ret_val = e1000e_get_phy_id(hw);
219 hw->phy.ops.acquire(hw);
220
221 return !ret_val;
cb17aab9
BA		 222}
223
224/**
225 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
226 * @hw: pointer to the HW structure
227 *
228 * Workarounds/flow necessary for PHY initialization during driver load
229 * and resume paths.
230 **/
231static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
232{
233 u32 mac_reg, fwsm = er32(FWSM);
234 s32 ret_val;
2fbe4526 235 u16 phy_reg;
cb17aab9 236
6e928b72
BA		 237 /* Gate automatic PHY configuration by hardware on managed and
238 * non-managed 82579 and newer adapters.
239 */
240 e1000_gate_hw_phy_config_ich8lan(hw, true);
241
cb17aab9
BA		 242 ret_val = hw->phy.ops.acquire(hw);
243 if (ret_val) {
244 e_dbg("Failed to initialize PHY flow\n");
6e928b72 245 goto out;
cb17aab9
BA		 246 }
247
e921eb1a 248 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
cb17aab9
BA		 249 * inaccessible and resetting the PHY is not blocked, toggle the
250 * LANPHYPC Value bit to force the interconnect to PCIe mode.
251 */
252 switch (hw->mac.type) {
2fbe4526
BA		 253 case e1000_pch_lpt:
254 if (e1000_phy_is_accessible_pchlan(hw))
255 break;
256
e921eb1a 257 /* Before toggling LANPHYPC, see if PHY is accessible by
2fbe4526
BA		 258 * forcing MAC to SMBus mode first.
259 */
260 mac_reg = er32(CTRL_EXT);
261 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
262 ew32(CTRL_EXT, mac_reg);
263
264 /* fall-through */
cb17aab9 265 case e1000_pch2lan:
2fbe4526
BA		 266 if (e1000_phy_is_accessible_pchlan(hw)) {
267 if (hw->mac.type == e1000_pch_lpt) {
268 /* Unforce SMBus mode in PHY */
269 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
270 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
271 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
272
273 /* Unforce SMBus mode in MAC */
274 mac_reg = er32(CTRL_EXT);
275 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
276 ew32(CTRL_EXT, mac_reg);
277 }
cb17aab9 278 break;
2fbe4526 279 }
cb17aab9
BA		 280
281 /* fall-through */
282 case e1000_pchlan:
283 if ((hw->mac.type == e1000_pchlan) &&
284 (fwsm & E1000_ICH_FWSM_FW_VALID))
285 break;
286
287 if (hw->phy.ops.check_reset_block(hw)) {
288 e_dbg("Required LANPHYPC toggle blocked by ME\n");
289 break;
290 }
291
292 e_dbg("Toggling LANPHYPC\n");
293
294 /* Set Phy Config Counter to 50msec */
295 mac_reg = er32(FEXTNVM3);
296 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
297 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
298 ew32(FEXTNVM3, mac_reg);
299
4e03510b
BA		 300 if (hw->mac.type == e1000_pch_lpt) {
301 /* Toggling LANPHYPC brings the PHY out of SMBus mode
302 * So ensure that the MAC is also out of SMBus mode
303 */
304 mac_reg = er32(CTRL_EXT);
305 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
306 ew32(CTRL_EXT, mac_reg);
307 }
308
cb17aab9
BA		 309 /* Toggle LANPHYPC Value bit */
310 mac_reg = er32(CTRL);
311 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
312 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
313 ew32(CTRL, mac_reg);
314 e1e_flush();
315 udelay(10);
316 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
317 ew32(CTRL, mac_reg);
318 e1e_flush();
2fbe4526
BA		 319 if (hw->mac.type < e1000_pch_lpt) {
320 msleep(50);
321 } else {
322 u16 count = 20;
323 do {
324 usleep_range(5000, 10000);
325 } while (!(er32(CTRL_EXT) &
326 E1000_CTRL_EXT_LPCD) && count--);
327 }
cb17aab9
BA		 328 break;
329 default:
330 break;
331 }
332
333 hw->phy.ops.release(hw);
334
e921eb1a 335 /* Reset the PHY before any access to it. Doing so, ensures
cb17aab9
BA		 336 * that the PHY is in a known good state before we read/write
337 * PHY registers. The generic reset is sufficient here,
338 * because we haven't determined the PHY type yet.
339 */
340 ret_val = e1000e_phy_hw_reset_generic(hw);
341
6e928b72 342out:
cb17aab9
BA		 343 /* Ungate automatic PHY configuration on non-managed 82579 */
344 if ((hw->mac.type == e1000_pch2lan) &&
345 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
346 usleep_range(10000, 20000);
347 e1000_gate_hw_phy_config_ich8lan(hw, false);
348 }
349
350 return ret_val;
99730e4c
BA		 351}
352
a4f58f54
BA		 353/**
354 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
355 * @hw: pointer to the HW structure
356 *
357 * Initialize family-specific PHY parameters and function pointers.
358 **/
359static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
360{
361 struct e1000_phy_info *phy = &hw->phy;
70806a7f 362 s32 ret_val;
a4f58f54
BA		 363
364 phy->addr = 1;
365 phy->reset_delay_us = 100;
366
2b6b168d 367 phy->ops.set_page = e1000_set_page_igp;
94d8186a
BA		 368 phy->ops.read_reg = e1000_read_phy_reg_hv;
369 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
2b6b168d 370 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
fa2ce13c
BA		 371 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
372 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 373 phy->ops.write_reg = e1000_write_phy_reg_hv;
374 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
2b6b168d 375 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
17f208de
BA		 376 phy->ops.power_up = e1000_power_up_phy_copper;
377 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 378 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
379
cb17aab9 380 phy->id = e1000_phy_unknown;
627c8a04 381
cb17aab9
BA		 382 ret_val = e1000_init_phy_workarounds_pchlan(hw);
383 if (ret_val)
384 return ret_val;
605c82ba 385
cb17aab9
BA		 386 if (phy->id == e1000_phy_unknown)
387 switch (hw->mac.type) {
388 default:
389 ret_val = e1000e_get_phy_id(hw);
390 if (ret_val)
391 return ret_val;
392 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
393 break;
394 /* fall-through */
395 case e1000_pch2lan:
2fbe4526 396 case e1000_pch_lpt:
e921eb1a 397 /* In case the PHY needs to be in mdio slow mode,
cb17aab9
BA		 398 * set slow mode and try to get the PHY id again.
399 */
400 ret_val = e1000_set_mdio_slow_mode_hv(hw);
401 if (ret_val)
402 return ret_val;
403 ret_val = e1000e_get_phy_id(hw);
404 if (ret_val)
405 return ret_val;
664dc878 406 break;
cb17aab9 407 }
a4f58f54
BA		 408 phy->type = e1000e_get_phy_type_from_id(phy->id);
409
0be84010
BA		 410 switch (phy->type) {
411 case e1000_phy_82577:
d3738bb8 412 case e1000_phy_82579:
2fbe4526 413 case e1000_phy_i217:
a4f58f54
BA		 414 phy->ops.check_polarity = e1000_check_polarity_82577;
415 phy->ops.force_speed_duplex =
6cc7aaed 416 e1000_phy_force_speed_duplex_82577;
0be84010 417 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 418 phy->ops.get_info = e1000_get_phy_info_82577;
419 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 420 break;
0be84010
BA		 421 case e1000_phy_82578:
422 phy->ops.check_polarity = e1000_check_polarity_m88;
423 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
424 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
425 phy->ops.get_info = e1000e_get_phy_info_m88;
426 break;
427 default:
428 ret_val = -E1000_ERR_PHY;
429 break;
a4f58f54
BA		 430 }
431
432 return ret_val;
433}
434
bc7f75fa
AK		 435/**
436 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
437 * @hw: pointer to the HW structure
438 *
439 * Initialize family-specific PHY parameters and function pointers.
440 **/
441static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
442{
443 struct e1000_phy_info *phy = &hw->phy;
444 s32 ret_val;
445 u16 i = 0;
446
447 phy->addr = 1;
448 phy->reset_delay_us = 100;
449
17f208de
BA		 450 phy->ops.power_up = e1000_power_up_phy_copper;
451 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
452
e921eb1a 453 /* We may need to do this twice - once for IGP and if that fails,
97ac8cae
BA		 454 * we'll set BM func pointers and try again
455 */
456 ret_val = e1000e_determine_phy_address(hw);
457 if (ret_val) {
94d8186a
BA		 458 phy->ops.write_reg = e1000e_write_phy_reg_bm;
459 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 460 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 461 if (ret_val) {
462 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 463 return ret_val;
9b71b419 464 }
97ac8cae
BA		 465 }
466
bc7f75fa
AK		 467 phy->id = 0;
468 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
469 (i++ < 100)) {
1bba4386 470 usleep_range(1000, 2000);
bc7f75fa
AK		 471 ret_val = e1000e_get_phy_id(hw);
472 if (ret_val)
473 return ret_val;
474 }
475
476 /* Verify phy id */
477 switch (phy->id) {
478 case IGP03E1000_E_PHY_ID:
479 phy->type = e1000_phy_igp_3;
480 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 481 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
482 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 483 phy->ops.get_info = e1000e_get_phy_info_igp;
484 phy->ops.check_polarity = e1000_check_polarity_igp;
485 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 486 break;
487 case IFE_E_PHY_ID:
488 case IFE_PLUS_E_PHY_ID:
489 case IFE_C_E_PHY_ID:
490 phy->type = e1000_phy_ife;
491 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 492 phy->ops.get_info = e1000_get_phy_info_ife;
493 phy->ops.check_polarity = e1000_check_polarity_ife;
494 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 495 break;
97ac8cae
BA		 496 case BME1000_E_PHY_ID:
497 phy->type = e1000_phy_bm;
498 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 499 phy->ops.read_reg = e1000e_read_phy_reg_bm;
500 phy->ops.write_reg = e1000e_write_phy_reg_bm;
501 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 502 phy->ops.get_info = e1000e_get_phy_info_m88;
503 phy->ops.check_polarity = e1000_check_polarity_m88;
504 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 505 break;
bc7f75fa
AK		 506 default:
507 return -E1000_ERR_PHY;
508 break;
509 }
510
511 return 0;
512}
513
514/**
515 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
516 * @hw: pointer to the HW structure
517 *
518 * Initialize family-specific NVM parameters and function
519 * pointers.
520 **/
521static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
522{
523 struct e1000_nvm_info *nvm = &hw->nvm;
524 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 525 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 526 u16 i;
527
ad68076e 528 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 529 if (!hw->flash_address) {
3bb99fe2 530 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 531 return -E1000_ERR_CONFIG;
532 }
533
534 nvm->type = e1000_nvm_flash_sw;
535
536 gfpreg = er32flash(ICH_FLASH_GFPREG);
537
e921eb1a 538 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 539 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 540 * the overall size.
541 */
bc7f75fa
AK		 542 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
543 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
544
545 /* flash_base_addr is byte-aligned */
546 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
547
e921eb1a 548 /* find total size of the NVM, then cut in half since the total
ad68076e
BA		 549 * size represents two separate NVM banks.
550 */
f0ff4398
BA		 551 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
552 << FLASH_SECTOR_ADDR_SHIFT);
bc7f75fa
AK		 553 nvm->flash_bank_size /= 2;
554 /* Adjust to word count */
555 nvm->flash_bank_size /= sizeof(u16);
556
557 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
558
559 /* Clear shadow ram */
560 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 561 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 562 dev_spec->shadow_ram[i].value = 0xFFFF;
563 }
564
565 return 0;
566}
567
568/**
569 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
570 * @hw: pointer to the HW structure
571 *
572 * Initialize family-specific MAC parameters and function
573 * pointers.
574 **/
ec34c170 575static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
bc7f75fa 576{
bc7f75fa
AK		 577 struct e1000_mac_info *mac = &hw->mac;
578
579 /* Set media type function pointer */
318a94d6 580 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 581
582 /* Set mta register count */
583 mac->mta_reg_count = 32;
584 /* Set rar entry count */
585 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
586 if (mac->type == e1000_ich8lan)
587 mac->rar_entry_count--;
a65a4a0d
BA		 588 /* FWSM register */
589 mac->has_fwsm = true;
590 /* ARC subsystem not supported */
591 mac->arc_subsystem_valid = false;
f464ba87
BA		 592 /* Adaptive IFS supported */
593 mac->adaptive_ifs = true;
bc7f75fa 594
2fbe4526 595 /* LED and other operations */
a4f58f54
BA		 596 switch (mac->type) {
597 case e1000_ich8lan:
598 case e1000_ich9lan:
599 case e1000_ich10lan:
eb7700dc
BA		 600 /* check management mode */
601 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54 602 /* ID LED init */
d1964eb1 603 mac->ops.id_led_init = e1000e_id_led_init_generic;
dbf80dcb
BA		 604 /* blink LED */
605 mac->ops.blink_led = e1000e_blink_led_generic;
a4f58f54
BA		 606 /* setup LED */
607 mac->ops.setup_led = e1000e_setup_led_generic;
608 /* cleanup LED */
609 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
610 /* turn on/off LED */
611 mac->ops.led_on = e1000_led_on_ich8lan;
612 mac->ops.led_off = e1000_led_off_ich8lan;
613 break;
d3738bb8 614 case e1000_pch2lan:
69e1e019
BA		 615 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
616 mac->ops.rar_set = e1000_rar_set_pch2lan;
617 /* fall-through */
2fbe4526 618 case e1000_pch_lpt:
69e1e019 619 case e1000_pchlan:
eb7700dc
BA		 620 /* check management mode */
621 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 622 /* ID LED init */
623 mac->ops.id_led_init = e1000_id_led_init_pchlan;
624 /* setup LED */
625 mac->ops.setup_led = e1000_setup_led_pchlan;
626 /* cleanup LED */
627 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
628 /* turn on/off LED */
629 mac->ops.led_on = e1000_led_on_pchlan;
630 mac->ops.led_off = e1000_led_off_pchlan;
631 break;
632 default:
633 break;
634 }
635
2fbe4526
BA		 636 if (mac->type == e1000_pch_lpt) {
637 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
638 mac->ops.rar_set = e1000_rar_set_pch_lpt;
639 }
640
bc7f75fa
AK		 641 /* Enable PCS Lock-loss workaround for ICH8 */
642 if (mac->type == e1000_ich8lan)
564ea9bb 643 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 644
645 return 0;
646}
647
4ddc48a9
BA		 648/**
649 * __e1000_access_emi_reg_locked - Read/write EMI register
650 * @hw: pointer to the HW structure
651 * @addr: EMI address to program
652 * @data: pointer to value to read/write from/to the EMI address
653 * @read: boolean flag to indicate read or write
654 *
655 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
656 **/
657static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
658 u16 *data, bool read)
659{
70806a7f 660 s32 ret_val;
4ddc48a9
BA		 661
662 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
663 if (ret_val)
664 return ret_val;
665
666 if (read)
667 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
668 else
669 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
670
671 return ret_val;
672}
673
674/**
675 * e1000_read_emi_reg_locked - Read Extended Management Interface register
676 * @hw: pointer to the HW structure
677 * @addr: EMI address to program
678 * @data: value to be read from the EMI address
679 *
680 * Assumes the SW/FW/HW Semaphore is already acquired.
681 **/
203e4151 682s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
4ddc48a9
BA		 683{
684 return __e1000_access_emi_reg_locked(hw, addr, data, true);
685}
686
687/**
688 * e1000_write_emi_reg_locked - Write Extended Management Interface register
689 * @hw: pointer to the HW structure
690 * @addr: EMI address to program
691 * @data: value to be written to the EMI address
692 *
693 * Assumes the SW/FW/HW Semaphore is already acquired.
694 **/
695static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
696{
697 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
698}
699
e52997f9
BA		 700/**
701 * e1000_set_eee_pchlan - Enable/disable EEE support
702 * @hw: pointer to the HW structure
703 *
3d4d5755
BA		 704 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
705 * the link and the EEE capabilities of the link partner. The LPI Control
706 * register bits will remain set only if/when link is up.
e52997f9
BA		 707 **/
708static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
709{
2fbe4526 710 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3d4d5755
BA		 711 s32 ret_val;
712 u16 lpi_ctrl;
e52997f9 713
2fbe4526
BA		 714 if ((hw->phy.type != e1000_phy_82579) &&
715 (hw->phy.type != e1000_phy_i217))
5015e53a 716 return 0;
e52997f9 717
3d4d5755 718 ret_val = hw->phy.ops.acquire(hw);
e52997f9 719 if (ret_val)
5015e53a 720 return ret_val;
e52997f9 721
3d4d5755 722 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
2fbe4526 723 if (ret_val)
3d4d5755
BA		 724 goto release;
725
726 /* Clear bits that enable EEE in various speeds */
727 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
728
729 /* Enable EEE if not disabled by user */
730 if (!dev_spec->eee_disable) {
731 u16 lpa, pcs_status, data;
2fbe4526 732
2fbe4526 733 /* Save off link partner's EEE ability */
3d4d5755
BA		 734 switch (hw->phy.type) {
735 case e1000_phy_82579:
736 lpa = I82579_EEE_LP_ABILITY;
737 pcs_status = I82579_EEE_PCS_STATUS;
738 break;
739 case e1000_phy_i217:
740 lpa = I217_EEE_LP_ABILITY;
741 pcs_status = I217_EEE_PCS_STATUS;
742 break;
743 default:
744 ret_val = -E1000_ERR_PHY;
745 goto release;
746 }
747 ret_val = e1000_read_emi_reg_locked(hw, lpa,
4ddc48a9 748 &dev_spec->eee_lp_ability);
2fbe4526
BA		 749 if (ret_val)
750 goto release;
2fbe4526 751
3d4d5755
BA		 752 /* Enable EEE only for speeds in which the link partner is
753 * EEE capable.
2fbe4526 754 */
3d4d5755
BA		 755 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
756 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
757
758 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
c2ade1a4
BA		 759 e1e_rphy_locked(hw, MII_LPA, &data);
760 if (data & LPA_100FULL)
3d4d5755
BA		 761 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
762 else
763 /* EEE is not supported in 100Half, so ignore
764 * partner's EEE in 100 ability if full-duplex
765 * is not advertised.
766 */
767 dev_spec->eee_lp_ability &=
768 ~I82579_EEE_100_SUPPORTED;
769 }
770
771 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
772 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
773 if (ret_val)
774 goto release;
2fbe4526
BA		 775 }
776
3d4d5755
BA		 777 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
778release:
779 hw->phy.ops.release(hw);
780
781 return ret_val;
e52997f9
BA		 782}
783
7d3cabbc
BA		 784/**
785 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
786 * @hw: pointer to the HW structure
787 *
788 * Checks to see of the link status of the hardware has changed. If a
789 * change in link status has been detected, then we read the PHY registers
790 * to get the current speed/duplex if link exists.
791 **/
792static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
793{
794 struct e1000_mac_info *mac = &hw->mac;
795 s32 ret_val;
796 bool link;
1d2101a7 797 u16 phy_reg;
7d3cabbc 798
e921eb1a 799 /* We only want to go out to the PHY registers to see if Auto-Neg
7d3cabbc
BA		 800 * has completed and/or if our link status has changed. The
801 * get_link_status flag is set upon receiving a Link Status
802 * Change or Rx Sequence Error interrupt.
803 */
5015e53a
BA		 804 if (!mac->get_link_status)
805 return 0;
7d3cabbc 806
e921eb1a 807 /* First we want to see if the MII Status Register reports
7d3cabbc
BA		 808 * link. If so, then we want to get the current speed/duplex
809 * of the PHY.
810 */
811 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
812 if (ret_val)
5015e53a 813 return ret_val;
7d3cabbc 814
1d5846b9
BA		 815 if (hw->mac.type == e1000_pchlan) {
816 ret_val = e1000_k1_gig_workaround_hv(hw, link);
817 if (ret_val)
5015e53a 818 return ret_val;
1d5846b9
BA		 819 }
820
2fbe4526
BA		 821 /* Clear link partner's EEE ability */
822 hw->dev_spec.ich8lan.eee_lp_ability = 0;
823
7d3cabbc 824 if (!link)
5015e53a 825 return 0; /* No link detected */
7d3cabbc
BA		 826
827 mac->get_link_status = false;
828
1d2101a7
BA		 829 switch (hw->mac.type) {
830 case e1000_pch2lan:
831bd2e6
BA		 831 ret_val = e1000_k1_workaround_lv(hw);
832 if (ret_val)
5015e53a 833 return ret_val;
1d2101a7
BA		 834 /* fall-thru */
835 case e1000_pchlan:
836 if (hw->phy.type == e1000_phy_82578) {
837 ret_val = e1000_link_stall_workaround_hv(hw);
838 if (ret_val)
5015e53a 839 return ret_val;
1d2101a7
BA		 840 }
841
e921eb1a 842 /* Workaround for PCHx parts in half-duplex:
1d2101a7
BA		 843 * Set the number of preambles removed from the packet
844 * when it is passed from the PHY to the MAC to prevent
845 * the MAC from misinterpreting the packet type.
846 */
847 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
848 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
849
850 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
851 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
852
853 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
854 break;
855 default:
856 break;
831bd2e6
BA		 857 }
858
e921eb1a 859 /* Check if there was DownShift, must be checked
7d3cabbc
BA		 860 * immediately after link-up
861 */
862 e1000e_check_downshift(hw);
863
e52997f9
BA		 864 /* Enable/Disable EEE after link up */
865 ret_val = e1000_set_eee_pchlan(hw);
866 if (ret_val)
5015e53a 867 return ret_val;
e52997f9 868
e921eb1a 869 /* If we are forcing speed/duplex, then we simply return since
7d3cabbc
BA		 870 * we have already determined whether we have link or not.
871 */
5015e53a
BA		 872 if (!mac->autoneg)
873 return -E1000_ERR_CONFIG;
7d3cabbc 874
e921eb1a 875 /* Auto-Neg is enabled. Auto Speed Detection takes care
7d3cabbc
BA		 876 * of MAC speed/duplex configuration. So we only need to
877 * configure Collision Distance in the MAC.
878 */
57cde763 879 mac->ops.config_collision_dist(hw);
7d3cabbc 880
e921eb1a 881 /* Configure Flow Control now that Auto-Neg has completed.
7d3cabbc
BA		 882 * First, we need to restore the desired flow control
883 * settings because we may have had to re-autoneg with a
884 * different link partner.
885 */
886 ret_val = e1000e_config_fc_after_link_up(hw);
887 if (ret_val)
3bb99fe2 888 e_dbg("Error configuring flow control\n");
7d3cabbc 889
7d3cabbc
BA		 890 return ret_val;
891}
892
69e3fd8c 893static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 894{
895 struct e1000_hw *hw = &adapter->hw;
896 s32 rc;
897
ec34c170 898 rc = e1000_init_mac_params_ich8lan(hw);
bc7f75fa
AK		 899 if (rc)
900 return rc;
901
902 rc = e1000_init_nvm_params_ich8lan(hw);
903 if (rc)
904 return rc;
905
d3738bb8
BA		 906 switch (hw->mac.type) {
907 case e1000_ich8lan:
908 case e1000_ich9lan:
909 case e1000_ich10lan:
a4f58f54 910 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 911 break;
912 case e1000_pchlan:
913 case e1000_pch2lan:
2fbe4526 914 case e1000_pch_lpt:
d3738bb8
BA		 915 rc = e1000_init_phy_params_pchlan(hw);
916 break;
917 default:
918 break;
919 }
bc7f75fa
AK		 920 if (rc)
921 return rc;
922
e921eb1a 923 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
23e4f061
BA		 924 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
925 */
926 if ((adapter->hw.phy.type == e1000_phy_ife) ||
927 ((adapter->hw.mac.type >= e1000_pch2lan) &&
928 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
2adc55c9
BA		 929 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
930 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
dbf80dcb
BA		 931
932 hw->mac.ops.blink_led = NULL;
2adc55c9
BA		 933 }
934
bc7f75fa 935 if ((adapter->hw.mac.type == e1000_ich8lan) &&
462d5994 936 (adapter->hw.phy.type != e1000_phy_ife))
bc7f75fa
AK		 937 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
938
c6e7f51e
BA		 939 /* Enable workaround for 82579 w/ ME enabled */
940 if ((adapter->hw.mac.type == e1000_pch2lan) &&
941 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
942 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
943
5a86f28f
BA		 944 /* Disable EEE by default until IEEE802.3az spec is finalized */
945 if (adapter->flags2 & FLAG2_HAS_EEE)
946 adapter->hw.dev_spec.ich8lan.eee_disable = true;
947
bc7f75fa
AK		 948 return 0;
949}
950
717d438d 951static DEFINE_MUTEX(nvm_mutex);
717d438d 952
ca15df58
BA		 953/**
954 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
955 * @hw: pointer to the HW structure
956 *
957 * Acquires the mutex for performing NVM operations.
958 **/
8bb62869 959static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 960{
961 mutex_lock(&nvm_mutex);
962
963 return 0;
964}
965
966/**
967 * e1000_release_nvm_ich8lan - Release NVM mutex
968 * @hw: pointer to the HW structure
969 *
970 * Releases the mutex used while performing NVM operations.
971 **/
8bb62869 972static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
ca15df58
BA		 973{
974 mutex_unlock(&nvm_mutex);
ca15df58
BA		 975}
976
bc7f75fa
AK		 977/**
978 * e1000_acquire_swflag_ich8lan - Acquire software control flag
979 * @hw: pointer to the HW structure
980 *
ca15df58
BA		 981 * Acquires the software control flag for performing PHY and select
982 * MAC CSR accesses.
bc7f75fa
AK		 983 **/
984static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
985{
373a88d7
BA		 986 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
987 s32 ret_val = 0;
bc7f75fa 988
a90b412c
BA		 989 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
990 &hw->adapter->state)) {
34c9ef8b 991 e_dbg("contention for Phy access\n");
a90b412c
BA		 992 return -E1000_ERR_PHY;
993 }
717d438d 994
bc7f75fa
AK		 995 while (timeout) {
996 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 997 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
998 break;
bc7f75fa 999
373a88d7
BA		 1000 mdelay(1);
1001 timeout--;
1002 }
1003
1004 if (!timeout) {
a90b412c 1005 e_dbg("SW has already locked the resource.\n");
373a88d7
BA		 1006 ret_val = -E1000_ERR_CONFIG;
1007 goto out;
1008 }
1009
53ac5a88 1010 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 1011
1012 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1013 ew32(EXTCNF_CTRL, extcnf_ctrl);
1014
1015 while (timeout) {
1016 extcnf_ctrl = er32(EXTCNF_CTRL);
1017 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1018 break;
a4f58f54 1019
bc7f75fa
AK		 1020 mdelay(1);
1021 timeout--;
1022 }
1023
1024 if (!timeout) {
434f1392 1025 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
a90b412c 1026 er32(FWSM), extcnf_ctrl);
2e2e8d53
BA		 1027 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1028 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 1029 ret_val = -E1000_ERR_CONFIG;
1030 goto out;
bc7f75fa
AK		 1031 }
1032
373a88d7
BA		 1033out:
1034 if (ret_val)
a90b412c 1035 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
373a88d7
BA		 1036
1037 return ret_val;
bc7f75fa
AK		 1038}
1039
1040/**
1041 * e1000_release_swflag_ich8lan - Release software control flag
1042 * @hw: pointer to the HW structure
1043 *
ca15df58
BA		 1044 * Releases the software control flag for performing PHY and select
1045 * MAC CSR accesses.
bc7f75fa
AK		 1046 **/
1047static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1048{
1049 u32 extcnf_ctrl;
1050
1051 extcnf_ctrl = er32(EXTCNF_CTRL);
c5caf482
BA		 1052
1053 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1054 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1055 ew32(EXTCNF_CTRL, extcnf_ctrl);
1056 } else {
1057 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1058 }
717d438d 1059
a90b412c 1060 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
bc7f75fa
AK		 1061}
1062
4662e82b
BA		 1063/**
1064 * e1000_check_mng_mode_ich8lan - Checks management mode
1065 * @hw: pointer to the HW structure
1066 *
eb7700dc 1067 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 1068 * This is a function pointer entry point only called by read/write
1069 * routines for the PHY and NVM parts.
1070 **/
1071static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1072{
a708dd88
BA		 1073 u32 fwsm;
1074
1075 fwsm = er32(FWSM);
f0ff4398
BA		 1076 return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
1077 ((fwsm & E1000_FWSM_MODE_MASK) ==
1078 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
eb7700dc 1079}
4662e82b 1080
eb7700dc
BA		 1081/**
1082 * e1000_check_mng_mode_pchlan - Checks management mode
1083 * @hw: pointer to the HW structure
1084 *
1085 * This checks if the adapter has iAMT enabled.
1086 * This is a function pointer entry point only called by read/write
1087 * routines for the PHY and NVM parts.
1088 **/
1089static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1090{
1091 u32 fwsm;
1092
1093 fwsm = er32(FWSM);
1094 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
f0ff4398 1095 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 1096}
1097
69e1e019
BA		 1098/**
1099 * e1000_rar_set_pch2lan - Set receive address register
1100 * @hw: pointer to the HW structure
1101 * @addr: pointer to the receive address
1102 * @index: receive address array register
1103 *
1104 * Sets the receive address array register at index to the address passed
1105 * in by addr. For 82579, RAR[0] is the base address register that is to
1106 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1107 * Use SHRA[0-3] in place of those reserved for ME.
1108 **/
1109static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1110{
1111 u32 rar_low, rar_high;
1112
e921eb1a 1113 /* HW expects these in little endian so we reverse the byte order
69e1e019
BA		 1114 * from network order (big endian) to little endian
1115 */
1116 rar_low = ((u32)addr[0] |
1117 ((u32)addr[1] << 8) |
1118 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1119
1120 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1121
1122 /* If MAC address zero, no need to set the AV bit */
1123 if (rar_low || rar_high)
1124 rar_high |= E1000_RAH_AV;
1125
1126 if (index == 0) {
1127 ew32(RAL(index), rar_low);
1128 e1e_flush();
1129 ew32(RAH(index), rar_high);
1130 e1e_flush();
1131 return;
1132 }
1133
1134 if (index < hw->mac.rar_entry_count) {
1135 s32 ret_val;
1136
1137 ret_val = e1000_acquire_swflag_ich8lan(hw);
1138 if (ret_val)
1139 goto out;
1140
1141 ew32(SHRAL(index - 1), rar_low);
1142 e1e_flush();
1143 ew32(SHRAH(index - 1), rar_high);
1144 e1e_flush();
1145
1146 e1000_release_swflag_ich8lan(hw);
1147
1148 /* verify the register updates */
1149 if ((er32(SHRAL(index - 1)) == rar_low) &&
1150 (er32(SHRAH(index - 1)) == rar_high))
1151 return;
1152
1153 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1154 (index - 1), er32(FWSM));
1155 }
1156
1157out:
1158 e_dbg("Failed to write receive address at index %d\n", index);
1159}
1160
2fbe4526
BA		 1161/**
1162 * e1000_rar_set_pch_lpt - Set receive address registers
1163 * @hw: pointer to the HW structure
1164 * @addr: pointer to the receive address
1165 * @index: receive address array register
1166 *
1167 * Sets the receive address register array at index to the address passed
1168 * in by addr. For LPT, RAR[0] is the base address register that is to
1169 * contain the MAC address. SHRA[0-10] are the shared receive address
1170 * registers that are shared between the Host and manageability engine (ME).
1171 **/
1172static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1173{
1174 u32 rar_low, rar_high;
1175 u32 wlock_mac;
1176
e921eb1a 1177 /* HW expects these in little endian so we reverse the byte order
2fbe4526
BA		 1178 * from network order (big endian) to little endian
1179 */
1180 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1181 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1182
1183 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1184
1185 /* If MAC address zero, no need to set the AV bit */
1186 if (rar_low || rar_high)
1187 rar_high |= E1000_RAH_AV;
1188
1189 if (index == 0) {
1190 ew32(RAL(index), rar_low);
1191 e1e_flush();
1192 ew32(RAH(index), rar_high);
1193 e1e_flush();
1194 return;
1195 }
1196
e921eb1a 1197 /* The manageability engine (ME) can lock certain SHRAR registers that
2fbe4526
BA		 1198 * it is using - those registers are unavailable for use.
1199 */
1200 if (index < hw->mac.rar_entry_count) {
1201 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1202 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1203
1204 /* Check if all SHRAR registers are locked */
1205 if (wlock_mac == 1)
1206 goto out;
1207
1208 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1209 s32 ret_val;
1210
1211 ret_val = e1000_acquire_swflag_ich8lan(hw);
1212
1213 if (ret_val)
1214 goto out;
1215
1216 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1217 e1e_flush();
1218 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1219 e1e_flush();
1220
1221 e1000_release_swflag_ich8lan(hw);
1222
1223 /* verify the register updates */
1224 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1225 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1226 return;
1227 }
1228 }
1229
1230out:
1231 e_dbg("Failed to write receive address at index %d\n", index);
1232}
1233
bc7f75fa
AK		 1234/**
1235 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1236 * @hw: pointer to the HW structure
1237 *
1238 * Checks if firmware is blocking the reset of the PHY.
1239 * This is a function pointer entry point only called by
1240 * reset routines.
1241 **/
1242static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1243{
1244 u32 fwsm;
1245
1246 fwsm = er32(FWSM);
1247
1248 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1249}
1250
8395ae83
BA		 1251/**
1252 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1253 * @hw: pointer to the HW structure
1254 *
1255 * Assumes semaphore already acquired.
1256 *
1257 **/
1258static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1259{
1260 u16 phy_data;
1261 u32 strap = er32(STRAP);
2fbe4526
BA		 1262 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1263 E1000_STRAP_SMT_FREQ_SHIFT;
70806a7f 1264 s32 ret_val;
8395ae83
BA		 1265
1266 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1267
1268 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1269 if (ret_val)
5015e53a 1270 return ret_val;
8395ae83
BA		 1271
1272 phy_data &= ~HV_SMB_ADDR_MASK;
1273 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1274 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
8395ae83 1275
2fbe4526
BA		 1276 if (hw->phy.type == e1000_phy_i217) {
1277 /* Restore SMBus frequency */
1278 if (freq--) {
1279 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1280 phy_data |= (freq & (1 << 0)) <<
1281 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1282 phy_data |= (freq & (1 << 1)) <<
1283 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1284 } else {
1285 e_dbg("Unsupported SMB frequency in PHY\n");
1286 }
1287 }
1288
5015e53a 1289 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
8395ae83
BA		 1290}
1291
f523d211
BA		 1292/**
1293 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1294 * @hw: pointer to the HW structure
1295 *
1296 * SW should configure the LCD from the NVM extended configuration region
1297 * as a workaround for certain parts.
1298 **/
1299static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1300{
1301 struct e1000_phy_info *phy = &hw->phy;
1302 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 1303 s32 ret_val = 0;
f523d211
BA		 1304 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1305
e921eb1a 1306 /* Initialize the PHY from the NVM on ICH platforms. This
f523d211
BA		 1307 * is needed due to an issue where the NVM configuration is
1308 * not properly autoloaded after power transitions.
1309 * Therefore, after each PHY reset, we will load the
1310 * configuration data out of the NVM manually.
1311 */
3f0c16e8
BA		 1312 switch (hw->mac.type) {
1313 case e1000_ich8lan:
1314 if (phy->type != e1000_phy_igp_3)
1315 return ret_val;
1316
5f3eed6f
BA		 1317 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1318 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 1319 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1320 break;
1321 }
1322 /* Fall-thru */
1323 case e1000_pchlan:
d3738bb8 1324 case e1000_pch2lan:
2fbe4526 1325 case e1000_pch_lpt:
8b802a7e 1326 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 1327 break;
1328 default:
1329 return ret_val;
1330 }
1331
1332 ret_val = hw->phy.ops.acquire(hw);
1333 if (ret_val)
1334 return ret_val;
8b802a7e
BA		 1335
1336 data = er32(FEXTNVM);
1337 if (!(data & sw_cfg_mask))
75ce1532 1338 goto release;
f523d211 1339
e921eb1a 1340 /* Make sure HW does not configure LCD from PHY
8b802a7e
BA		 1341 * extended configuration before SW configuration
1342 */
1343 data = er32(EXTCNF_CTRL);
2fbe4526
BA		 1344 if ((hw->mac.type < e1000_pch2lan) &&
1345 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1346 goto release;
8b802a7e
BA		 1347
1348 cnf_size = er32(EXTCNF_SIZE);
1349 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1350 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1351 if (!cnf_size)
75ce1532 1352 goto release;
8b802a7e
BA		 1353
1354 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1355 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1356
2fbe4526
BA		 1357 if (((hw->mac.type == e1000_pchlan) &&
1358 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1359 (hw->mac.type > e1000_pchlan)) {
e921eb1a 1360 /* HW configures the SMBus address and LEDs when the
8b802a7e
BA		 1361 * OEM and LCD Write Enable bits are set in the NVM.
1362 * When both NVM bits are cleared, SW will configure
1363 * them instead.
f523d211 1364 */
8395ae83 1365 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1366 if (ret_val)
75ce1532 1367 goto release;
f523d211 1368
8b802a7e
BA		 1369 data = er32(LEDCTL);
1370 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1371 (u16)data);
1372 if (ret_val)
75ce1532 1373 goto release;
8b802a7e 1374 }
f523d211 1375
8b802a7e
BA		 1376 /* Configure LCD from extended configuration region. */
1377
1378 /* cnf_base_addr is in DWORD */
1379 word_addr = (u16)(cnf_base_addr << 1);
1380
1381 for (i = 0; i < cnf_size; i++) {
e5fe2541 1382 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
8b802a7e 1383 if (ret_val)
75ce1532 1384 goto release;
8b802a7e
BA		 1385
1386 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1387 1, &reg_addr);
1388 if (ret_val)
75ce1532 1389 goto release;
8b802a7e
BA		 1390
1391 /* Save off the PHY page for future writes. */
1392 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1393 phy_page = reg_data;
1394 continue;
f523d211 1395 }
8b802a7e
BA		 1396
1397 reg_addr &= PHY_REG_MASK;
1398 reg_addr |= phy_page;
1399
f1430d69 1400 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
8b802a7e 1401 if (ret_val)
75ce1532 1402 goto release;
f523d211
BA		 1403 }
1404
75ce1532 1405release:
94d8186a 1406 hw->phy.ops.release(hw);
f523d211
BA		 1407 return ret_val;
1408}
1409
1d5846b9
BA		 1410/**
1411 * e1000_k1_gig_workaround_hv - K1 Si workaround
1412 * @hw: pointer to the HW structure
1413 * @link: link up bool flag
1414 *
1415 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1416 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1417 * If link is down, the function will restore the default K1 setting located
1418 * in the NVM.
1419 **/
1420static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1421{
1422 s32 ret_val = 0;
1423 u16 status_reg = 0;
1424 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1425
1426 if (hw->mac.type != e1000_pchlan)
5015e53a 1427 return 0;
1d5846b9
BA		 1428
1429 /* Wrap the whole flow with the sw flag */
94d8186a 1430 ret_val = hw->phy.ops.acquire(hw);
1d5846b9 1431 if (ret_val)
5015e53a 1432 return ret_val;
1d5846b9
BA		 1433
1434 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1435 if (link) {
1436 if (hw->phy.type == e1000_phy_82578) {
f1430d69
BA		 1437 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1438 &status_reg);
1d5846b9
BA		 1439 if (ret_val)
1440 goto release;
1441
f0ff4398
BA		 1442 status_reg &= (BM_CS_STATUS_LINK_UP |
1443 BM_CS_STATUS_RESOLVED |
1444 BM_CS_STATUS_SPEED_MASK);
1d5846b9
BA		 1445
1446 if (status_reg == (BM_CS_STATUS_LINK_UP |
f0ff4398
BA		 1447 BM_CS_STATUS_RESOLVED |
1448 BM_CS_STATUS_SPEED_1000))
1d5846b9
BA		 1449 k1_enable = false;
1450 }
1451
1452 if (hw->phy.type == e1000_phy_82577) {
f1430d69 1453 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1d5846b9
BA		 1454 if (ret_val)
1455 goto release;
1456
f0ff4398
BA		 1457 status_reg &= (HV_M_STATUS_LINK_UP |
1458 HV_M_STATUS_AUTONEG_COMPLETE |
1459 HV_M_STATUS_SPEED_MASK);
1d5846b9
BA		 1460
1461 if (status_reg == (HV_M_STATUS_LINK_UP |
f0ff4398
BA		 1462 HV_M_STATUS_AUTONEG_COMPLETE |
1463 HV_M_STATUS_SPEED_1000))
1d5846b9
BA		 1464 k1_enable = false;
1465 }
1466
1467 /* Link stall fix for link up */
f1430d69 1468 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1d5846b9
BA		 1469 if (ret_val)
1470 goto release;
1471
1472 } else {
1473 /* Link stall fix for link down */
f1430d69 1474 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1d5846b9
BA		 1475 if (ret_val)
1476 goto release;
1477 }
1478
1479 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1480
1481release:
94d8186a 1482 hw->phy.ops.release(hw);
5015e53a 1483
1d5846b9
BA		 1484 return ret_val;
1485}
1486
1487/**
1488 * e1000_configure_k1_ich8lan - Configure K1 power state
1489 * @hw: pointer to the HW structure
1490 * @enable: K1 state to configure
1491 *
1492 * Configure the K1 power state based on the provided parameter.
1493 * Assumes semaphore already acquired.
1494 *
1495 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1496 **/
bb436b20 1497s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9 1498{
70806a7f 1499 s32 ret_val;
1d5846b9
BA		 1500 u32 ctrl_reg = 0;
1501 u32 ctrl_ext = 0;
1502 u32 reg = 0;
1503 u16 kmrn_reg = 0;
1504
3d3a1676
BA		 1505 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1506 &kmrn_reg);
1d5846b9 1507 if (ret_val)
5015e53a 1508 return ret_val;
1d5846b9
BA		 1509
1510 if (k1_enable)
1511 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1512 else
1513 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1514
3d3a1676
BA		 1515 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1516 kmrn_reg);
1d5846b9 1517 if (ret_val)
5015e53a 1518 return ret_val;
1d5846b9
BA		 1519
1520 udelay(20);
1521 ctrl_ext = er32(CTRL_EXT);
1522 ctrl_reg = er32(CTRL);
1523
1524 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1525 reg |= E1000_CTRL_FRCSPD;
1526 ew32(CTRL, reg);
1527
1528 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
945a5151 1529 e1e_flush();
1d5846b9
BA		 1530 udelay(20);
1531 ew32(CTRL, ctrl_reg);
1532 ew32(CTRL_EXT, ctrl_ext);
945a5151 1533 e1e_flush();
1d5846b9
BA		 1534 udelay(20);
1535
5015e53a 1536 return 0;
1d5846b9
BA		 1537}
1538
f523d211
BA		 1539/**
1540 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1541 * @hw: pointer to the HW structure
1542 * @d0_state: boolean if entering d0 or d3 device state
1543 *
1544 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1545 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1546 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1547 **/
1548static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1549{
1550 s32 ret_val = 0;
1551 u32 mac_reg;
1552 u16 oem_reg;
1553
2fbe4526 1554 if (hw->mac.type < e1000_pchlan)
f523d211
BA		 1555 return ret_val;
1556
94d8186a 1557 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1558 if (ret_val)
1559 return ret_val;
1560
2fbe4526 1561 if (hw->mac.type == e1000_pchlan) {
d3738bb8
BA		 1562 mac_reg = er32(EXTCNF_CTRL);
1563 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
75ce1532 1564 goto release;
d3738bb8 1565 }
f523d211
BA		 1566
1567 mac_reg = er32(FEXTNVM);
1568 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
75ce1532 1569 goto release;
f523d211
BA		 1570
1571 mac_reg = er32(PHY_CTRL);
1572
f1430d69 1573 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211 1574 if (ret_val)
75ce1532 1575 goto release;
f523d211
BA		 1576
1577 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1578
1579 if (d0_state) {
1580 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1581 oem_reg |= HV_OEM_BITS_GBE_DIS;
1582
1583 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1584 oem_reg |= HV_OEM_BITS_LPLU;
1585 } else {
03299e46
BA		 1586 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1587 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
f523d211
BA		 1588 oem_reg |= HV_OEM_BITS_GBE_DIS;
1589
03299e46
BA		 1590 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1591 E1000_PHY_CTRL_NOND0A_LPLU))
f523d211
BA		 1592 oem_reg |= HV_OEM_BITS_LPLU;
1593 }
03299e46 1594
92fe1733
BA		 1595 /* Set Restart auto-neg to activate the bits */
1596 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1597 !hw->phy.ops.check_reset_block(hw))
1598 oem_reg |= HV_OEM_BITS_RESTART_AN;
1599
f1430d69 1600 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
f523d211 1601
75ce1532 1602release:
94d8186a 1603 hw->phy.ops.release(hw);
f523d211
BA		 1604
1605 return ret_val;
1606}
1607
fddaa1af
BA		 1608/**
1609 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1610 * @hw: pointer to the HW structure
1611 **/
1612static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1613{
1614 s32 ret_val;
1615 u16 data;
1616
1617 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1618 if (ret_val)
1619 return ret_val;
1620
1621 data |= HV_KMRN_MDIO_SLOW;
1622
1623 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1624
1625 return ret_val;
1626}
1627
a4f58f54
BA		 1628/**
1629 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1630 * done after every PHY reset.
1631 **/
1632static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1633{
1634 s32 ret_val = 0;
baf86c9d 1635 u16 phy_data;
a4f58f54
BA		 1636
1637 if (hw->mac.type != e1000_pchlan)
5015e53a 1638 return 0;
a4f58f54 1639
fddaa1af
BA		 1640 /* Set MDIO slow mode before any other MDIO access */
1641 if (hw->phy.type == e1000_phy_82577) {
1642 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1643 if (ret_val)
5015e53a 1644 return ret_val;
fddaa1af
BA		 1645 }
1646
a4f58f54
BA		 1647 if (((hw->phy.type == e1000_phy_82577) &&
1648 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1649 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1650 /* Disable generation of early preamble */
1651 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1652 if (ret_val)
1653 return ret_val;
1654
1655 /* Preamble tuning for SSC */
1d2101a7 1656 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
a4f58f54
BA		 1657 if (ret_val)
1658 return ret_val;
1659 }
1660
1661 if (hw->phy.type == e1000_phy_82578) {
e921eb1a 1662 /* Return registers to default by doing a soft reset then
a4f58f54
BA		 1663 * writing 0x3140 to the control register.
1664 */
1665 if (hw->phy.revision < 2) {
1666 e1000e_phy_sw_reset(hw);
c2ade1a4 1667 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
a4f58f54
BA		 1668 }
1669 }
1670
1671 /* Select page 0 */
94d8186a 1672 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1673 if (ret_val)
1674 return ret_val;
1d5846b9 1675
a4f58f54 1676 hw->phy.addr = 1;
1d5846b9 1677 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1678 hw->phy.ops.release(hw);
1d5846b9 1679 if (ret_val)
5015e53a 1680 return ret_val;
a4f58f54 1681
e921eb1a 1682 /* Configure the K1 Si workaround during phy reset assuming there is
1d5846b9
BA		 1683 * link so that it disables K1 if link is in 1Gbps.
1684 */
1685 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d 1686 if (ret_val)
5015e53a 1687 return ret_val;
1d5846b9 1688
baf86c9d
BA		 1689 /* Workaround for link disconnects on a busy hub in half duplex */
1690 ret_val = hw->phy.ops.acquire(hw);
1691 if (ret_val)
5015e53a 1692 return ret_val;
f1430d69 1693 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
baf86c9d
BA		 1694 if (ret_val)
1695 goto release;
f1430d69 1696 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
651fb102
BA		 1697 if (ret_val)
1698 goto release;
1699
1700 /* set MSE higher to enable link to stay up when noise is high */
1701 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
baf86c9d
BA		 1702release:
1703 hw->phy.ops.release(hw);
5015e53a 1704
a4f58f54
BA		 1705 return ret_val;
1706}
1707
d3738bb8
BA		 1708/**
1709 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1710 * @hw: pointer to the HW structure
1711 **/
1712void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1713{
1714 u32 mac_reg;
2b6b168d
BA		 1715 u16 i, phy_reg = 0;
1716 s32 ret_val;
1717
1718 ret_val = hw->phy.ops.acquire(hw);
1719 if (ret_val)
1720 return;
1721 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1722 if (ret_val)
1723 goto release;
d3738bb8
BA		 1724
1725 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1726 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1727 mac_reg = er32(RAL(i));
2b6b168d
BA		 1728 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1729 (u16)(mac_reg & 0xFFFF));
1730 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1731 (u16)((mac_reg >> 16) & 0xFFFF));
1732
d3738bb8 1733 mac_reg = er32(RAH(i));
2b6b168d
BA		 1734 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1735 (u16)(mac_reg & 0xFFFF));
1736 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1737 (u16)((mac_reg & E1000_RAH_AV)
1738 >> 16));
d3738bb8 1739 }
2b6b168d
BA		 1740
1741 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1742
1743release:
1744 hw->phy.ops.release(hw);
d3738bb8
BA		 1745}
1746
d3738bb8
BA		 1747/**
1748 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1749 * with 82579 PHY
1750 * @hw: pointer to the HW structure
1751 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1752 **/
1753s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1754{
1755 s32 ret_val = 0;
1756 u16 phy_reg, data;
1757 u32 mac_reg;
1758 u16 i;
1759
2fbe4526 1760 if (hw->mac.type < e1000_pch2lan)
5015e53a 1761 return 0;
d3738bb8
BA		 1762
1763 /* disable Rx path while enabling/disabling workaround */
1764 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1765 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1766 if (ret_val)
5015e53a 1767 return ret_val;
d3738bb8
BA		 1768
1769 if (enable) {
e921eb1a 1770 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
d3738bb8
BA		 1771 * SHRAL/H) and initial CRC values to the MAC
1772 */
1773 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
362e20ca 1774 u8 mac_addr[ETH_ALEN] = { 0 };
d3738bb8
BA		 1775 u32 addr_high, addr_low;
1776
1777 addr_high = er32(RAH(i));
1778 if (!(addr_high & E1000_RAH_AV))
1779 continue;
1780 addr_low = er32(RAL(i));
1781 mac_addr[0] = (addr_low & 0xFF);
1782 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1783 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1784 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1785 mac_addr[4] = (addr_high & 0xFF);
1786 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1787
fe46f58f 1788 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
d3738bb8
BA		 1789 }
1790
1791 /* Write Rx addresses to the PHY */
1792 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1793
1794 /* Enable jumbo frame workaround in the MAC */
1795 mac_reg = er32(FFLT_DBG);
1796 mac_reg &= ~(1 << 14);
1797 mac_reg |= (7 << 15);
1798 ew32(FFLT_DBG, mac_reg);
1799
1800 mac_reg = er32(RCTL);
1801 mac_reg |= E1000_RCTL_SECRC;
1802 ew32(RCTL, mac_reg);
1803
1804 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 1805 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1806 &data);
d3738bb8 1807 if (ret_val)
5015e53a 1808 return ret_val;
d3738bb8
BA		 1809 ret_val = e1000e_write_kmrn_reg(hw,
1810 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1811 data | (1 << 0));
1812 if (ret_val)
5015e53a 1813 return ret_val;
d3738bb8 1814 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 1815 E1000_KMRNCTRLSTA_HD_CTRL,
1816 &data);
d3738bb8 1817 if (ret_val)
5015e53a 1818 return ret_val;
d3738bb8
BA		 1819 data &= ~(0xF << 8);
1820 data |= (0xB << 8);
1821 ret_val = e1000e_write_kmrn_reg(hw,
1822 E1000_KMRNCTRLSTA_HD_CTRL,
1823 data);
1824 if (ret_val)
5015e53a 1825 return ret_val;
d3738bb8
BA		 1826
1827 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 1828 e1e_rphy(hw, PHY_REG(769, 23), &data);
1829 data &= ~(0x7F << 5);
1830 data |= (0x37 << 5);
1831 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1832 if (ret_val)
5015e53a 1833 return ret_val;
d3738bb8
BA		 1834 e1e_rphy(hw, PHY_REG(769, 16), &data);
1835 data &= ~(1 << 13);
d3738bb8
BA		 1836 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1837 if (ret_val)
5015e53a 1838 return ret_val;
d3738bb8
BA		 1839 e1e_rphy(hw, PHY_REG(776, 20), &data);
1840 data &= ~(0x3FF << 2);
1841 data |= (0x1A << 2);
1842 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1843 if (ret_val)
5015e53a 1844 return ret_val;
b64e9dd5 1845 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
d3738bb8 1846 if (ret_val)
5015e53a 1847 return ret_val;
d3738bb8
BA		 1848 e1e_rphy(hw, HV_PM_CTRL, &data);
1849 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1850 if (ret_val)
5015e53a 1851 return ret_val;
d3738bb8
BA		 1852 } else {
1853 /* Write MAC register values back to h/w defaults */
1854 mac_reg = er32(FFLT_DBG);
1855 mac_reg &= ~(0xF << 14);
1856 ew32(FFLT_DBG, mac_reg);
1857
1858 mac_reg = er32(RCTL);
1859 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 1860 ew32(RCTL, mac_reg);
d3738bb8
BA		 1861
1862 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 1863 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1864 &data);
d3738bb8 1865 if (ret_val)
5015e53a 1866 return ret_val;
d3738bb8
BA		 1867 ret_val = e1000e_write_kmrn_reg(hw,
1868 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1869 data & ~(1 << 0));
1870 if (ret_val)
5015e53a 1871 return ret_val;
d3738bb8 1872 ret_val = e1000e_read_kmrn_reg(hw,
17e813ec
BA		 1873 E1000_KMRNCTRLSTA_HD_CTRL,
1874 &data);
d3738bb8 1875 if (ret_val)
5015e53a 1876 return ret_val;
d3738bb8
BA		 1877 data &= ~(0xF << 8);
1878 data |= (0xB << 8);
1879 ret_val = e1000e_write_kmrn_reg(hw,
1880 E1000_KMRNCTRLSTA_HD_CTRL,
1881 data);
1882 if (ret_val)
5015e53a 1883 return ret_val;
d3738bb8
BA		 1884
1885 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 1886 e1e_rphy(hw, PHY_REG(769, 23), &data);
1887 data &= ~(0x7F << 5);
1888 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1889 if (ret_val)
5015e53a 1890 return ret_val;
d3738bb8 1891 e1e_rphy(hw, PHY_REG(769, 16), &data);
d3738bb8
BA		 1892 data |= (1 << 13);
1893 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1894 if (ret_val)
5015e53a 1895 return ret_val;
d3738bb8
BA		 1896 e1e_rphy(hw, PHY_REG(776, 20), &data);
1897 data &= ~(0x3FF << 2);
1898 data |= (0x8 << 2);
1899 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1900 if (ret_val)
5015e53a 1901 return ret_val;
d3738bb8
BA		 1902 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1903 if (ret_val)
5015e53a 1904 return ret_val;
d3738bb8
BA		 1905 e1e_rphy(hw, HV_PM_CTRL, &data);
1906 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1907 if (ret_val)
5015e53a 1908 return ret_val;
d3738bb8
BA		 1909 }
1910
1911 /* re-enable Rx path after enabling/disabling workaround */
5015e53a 1912 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
d3738bb8
BA		 1913}
1914
1915/**
1916 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1917 * done after every PHY reset.
1918 **/
1919static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1920{
1921 s32 ret_val = 0;
1922
1923 if (hw->mac.type != e1000_pch2lan)
5015e53a 1924 return 0;
d3738bb8
BA		 1925
1926 /* Set MDIO slow mode before any other MDIO access */
1927 ret_val = e1000_set_mdio_slow_mode_hv(hw);
8e5ab42d
BA		 1928 if (ret_val)
1929 return ret_val;
d3738bb8 1930
4d24136c
BA		 1931 ret_val = hw->phy.ops.acquire(hw);
1932 if (ret_val)
5015e53a 1933 return ret_val;
4d24136c 1934 /* set MSE higher to enable link to stay up when noise is high */
4ddc48a9 1935 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
4d24136c
BA		 1936 if (ret_val)
1937 goto release;
1938 /* drop link after 5 times MSE threshold was reached */
4ddc48a9 1939 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
4d24136c
BA		 1940release:
1941 hw->phy.ops.release(hw);
1942
d3738bb8
BA		 1943 return ret_val;
1944}
1945
831bd2e6
BA		 1946/**
1947 * e1000_k1_gig_workaround_lv - K1 Si workaround
1948 * @hw: pointer to the HW structure
1949 *
1950 * Workaround to set the K1 beacon duration for 82579 parts
1951 **/
1952static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1953{
1954 s32 ret_val = 0;
1955 u16 status_reg = 0;
1956 u32 mac_reg;
0ed013e2 1957 u16 phy_reg;
831bd2e6
BA		 1958
1959 if (hw->mac.type != e1000_pch2lan)
5015e53a 1960 return 0;
831bd2e6
BA		 1961
1962 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1963 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1964 if (ret_val)
5015e53a 1965 return ret_val;
831bd2e6
BA		 1966
1967 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1968 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1969 mac_reg = er32(FEXTNVM4);
1970 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1971
0ed013e2
BA		 1972 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1973 if (ret_val)
5015e53a 1974 return ret_val;
0ed013e2
BA		 1975
1976 if (status_reg & HV_M_STATUS_SPEED_1000) {
36ceeb43
BA		 1977 u16 pm_phy_reg;
1978
831bd2e6 1979 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
0ed013e2 1980 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
36ceeb43
BA		 1981 /* LV 1G Packet drop issue wa */
1982 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
1983 if (ret_val)
1984 return ret_val;
1985 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
1986 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
1987 if (ret_val)
1988 return ret_val;
0ed013e2 1989 } else {
831bd2e6 1990 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
0ed013e2
BA		 1991 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1992 }
831bd2e6 1993 ew32(FEXTNVM4, mac_reg);
0ed013e2 1994 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
831bd2e6
BA		 1995 }
1996
831bd2e6
BA		 1997 return ret_val;
1998}
1999
605c82ba
BA		 2000/**
2001 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2002 * @hw: pointer to the HW structure
2003 * @gate: boolean set to true to gate, false to ungate
2004 *
2005 * Gate/ungate the automatic PHY configuration via hardware; perform
2006 * the configuration via software instead.
2007 **/
2008static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2009{
2010 u32 extcnf_ctrl;
2011
2fbe4526 2012 if (hw->mac.type < e1000_pch2lan)
605c82ba
BA		 2013 return;
2014
2015 extcnf_ctrl = er32(EXTCNF_CTRL);
2016
2017 if (gate)
2018 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2019 else
2020 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2021
2022 ew32(EXTCNF_CTRL, extcnf_ctrl);
605c82ba
BA		 2023}
2024
fc0c7760
BA		 2025/**
2026 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2027 * @hw: pointer to the HW structure
2028 *
2029 * Check the appropriate indication the MAC has finished configuring the
2030 * PHY after a software reset.
2031 **/
2032static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2033{
2034 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2035
2036 /* Wait for basic configuration completes before proceeding */
2037 do {
2038 data = er32(STATUS);
2039 data &= E1000_STATUS_LAN_INIT_DONE;
2040 udelay(100);
2041 } while ((!data) && --loop);
2042
e921eb1a 2043 /* If basic configuration is incomplete before the above loop
fc0c7760
BA		 2044 * count reaches 0, loading the configuration from NVM will
2045 * leave the PHY in a bad state possibly resulting in no link.
2046 */
2047 if (loop == 0)
3bb99fe2 2048 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 2049
2050 /* Clear the Init Done bit for the next init event */
2051 data = er32(STATUS);
2052 data &= ~E1000_STATUS_LAN_INIT_DONE;
2053 ew32(STATUS, data);
2054}
2055
bc7f75fa 2056/**
e98cac44 2057 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 2058 * @hw: pointer to the HW structure
bc7f75fa 2059 **/
e98cac44 2060static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 2061{
f523d211
BA		 2062 s32 ret_val = 0;
2063 u16 reg;
bc7f75fa 2064
44abd5c1 2065 if (hw->phy.ops.check_reset_block(hw))
5015e53a 2066 return 0;
fc0c7760 2067
5f3eed6f 2068 /* Allow time for h/w to get to quiescent state after reset */
1bba4386 2069 usleep_range(10000, 20000);
5f3eed6f 2070
fddaa1af 2071 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 2072 switch (hw->mac.type) {
2073 case e1000_pchlan:
a4f58f54
BA		 2074 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2075 if (ret_val)
5015e53a 2076 return ret_val;
e98cac44 2077 break;
d3738bb8
BA		 2078 case e1000_pch2lan:
2079 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2080 if (ret_val)
5015e53a 2081 return ret_val;
d3738bb8 2082 break;
e98cac44
BA		 2083 default:
2084 break;
a4f58f54
BA		 2085 }
2086
3ebfc7c9
BA		 2087 /* Clear the host wakeup bit after lcd reset */
2088 if (hw->mac.type >= e1000_pchlan) {
2089 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2090 reg &= ~BM_WUC_HOST_WU_BIT;
2091 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2092 }
db2932ec 2093
f523d211
BA		 2094 /* Configure the LCD with the extended configuration region in NVM */
2095 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2096 if (ret_val)
5015e53a 2097 return ret_val;
bc7f75fa 2098
f523d211 2099 /* Configure the LCD with the OEM bits in NVM */
e98cac44 2100 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 2101
1effb45c
BA		 2102 if (hw->mac.type == e1000_pch2lan) {
2103 /* Ungate automatic PHY configuration on non-managed 82579 */
2104 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1bba4386 2105 usleep_range(10000, 20000);
1effb45c
BA		 2106 e1000_gate_hw_phy_config_ich8lan(hw, false);
2107 }
2108
2109 /* Set EEE LPI Update Timer to 200usec */
2110 ret_val = hw->phy.ops.acquire(hw);
2111 if (ret_val)
5015e53a 2112 return ret_val;
4ddc48a9
BA		 2113 ret_val = e1000_write_emi_reg_locked(hw,
2114 I82579_LPI_UPDATE_TIMER,
2115 0x1387);
1effb45c 2116 hw->phy.ops.release(hw);
605c82ba
BA		 2117 }
2118
e98cac44
BA		 2119 return ret_val;
2120}
2121
2122/**
2123 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2124 * @hw: pointer to the HW structure
2125 *
2126 * Resets the PHY
2127 * This is a function pointer entry point called by drivers
2128 * or other shared routines.
2129 **/
2130static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2131{
2132 s32 ret_val = 0;
2133
605c82ba
BA		 2134 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2135 if ((hw->mac.type == e1000_pch2lan) &&
2136 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2137 e1000_gate_hw_phy_config_ich8lan(hw, true);
2138
e98cac44
BA		 2139 ret_val = e1000e_phy_hw_reset_generic(hw);
2140 if (ret_val)
5015e53a 2141 return ret_val;
e98cac44 2142
5015e53a 2143 return e1000_post_phy_reset_ich8lan(hw);
bc7f75fa
AK		 2144}
2145
fa2ce13c
BA		 2146/**
2147 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2148 * @hw: pointer to the HW structure
2149 * @active: true to enable LPLU, false to disable
2150 *
2151 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2152 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2153 * the phy speed. This function will manually set the LPLU bit and restart
2154 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2155 * since it configures the same bit.
2156 **/
2157static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2158{
70806a7f 2159 s32 ret_val;
fa2ce13c
BA		 2160 u16 oem_reg;
2161
2162 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2163 if (ret_val)
5015e53a 2164 return ret_val;
fa2ce13c
BA		 2165
2166 if (active)
2167 oem_reg |= HV_OEM_BITS_LPLU;
2168 else
2169 oem_reg &= ~HV_OEM_BITS_LPLU;
2170
44abd5c1 2171 if (!hw->phy.ops.check_reset_block(hw))
464c85e3
BA		 2172 oem_reg |= HV_OEM_BITS_RESTART_AN;
2173
5015e53a 2174 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
fa2ce13c
BA		 2175}
2176
bc7f75fa
AK		 2177/**
2178 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2179 * @hw: pointer to the HW structure
564ea9bb 2180 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2181 *
2182 * Sets the LPLU D0 state according to the active flag. When
2183 * activating LPLU this function also disables smart speed
2184 * and vice versa. LPLU will not be activated unless the
2185 * device autonegotiation advertisement meets standards of
2186 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2187 * This is a function pointer entry point only called by
2188 * PHY setup routines.
2189 **/
2190static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2191{
2192 struct e1000_phy_info *phy = &hw->phy;
2193 u32 phy_ctrl;
2194 s32 ret_val = 0;
2195 u16 data;
2196
97ac8cae 2197 if (phy->type == e1000_phy_ife)
82607255 2198 return 0;
bc7f75fa
AK		 2199
2200 phy_ctrl = er32(PHY_CTRL);
2201
2202 if (active) {
2203 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2204 ew32(PHY_CTRL, phy_ctrl);
2205
60f1292f
BA		 2206 if (phy->type != e1000_phy_igp_3)
2207 return 0;
2208
e921eb1a 2209 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2210 * any PHY registers
2211 */
60f1292f 2212 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2213 e1000e_gig_downshift_workaround_ich8lan(hw);
2214
2215 /* When LPLU is enabled, we should disable SmartSpeed */
2216 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
7dbbe5d5
BA		 2217 if (ret_val)
2218 return ret_val;
bc7f75fa
AK		 2219 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2220 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2221 if (ret_val)
2222 return ret_val;
2223 } else {
2224 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2225 ew32(PHY_CTRL, phy_ctrl);
2226
60f1292f
BA		 2227 if (phy->type != e1000_phy_igp_3)
2228 return 0;
2229
e921eb1a 2230 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2231 * during Dx states where the power conservation is most
2232 * important. During driver activity we should enable
ad68076e
BA		 2233 * SmartSpeed, so performance is maintained.
2234 */
bc7f75fa
AK		 2235 if (phy->smart_speed == e1000_smart_speed_on) {
2236 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2237 &data);
bc7f75fa
AK		 2238 if (ret_val)
2239 return ret_val;
2240
2241 data |= IGP01E1000_PSCFR_SMART_SPEED;
2242 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2243 data);
bc7f75fa
AK		 2244 if (ret_val)
2245 return ret_val;
2246 } else if (phy->smart_speed == e1000_smart_speed_off) {
2247 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2248 &data);
bc7f75fa
AK		 2249 if (ret_val)
2250 return ret_val;
2251
2252 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2253 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 2254 data);
bc7f75fa
AK		 2255 if (ret_val)
2256 return ret_val;
2257 }
2258 }
2259
2260 return 0;
2261}
2262
2263/**
2264 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2265 * @hw: pointer to the HW structure
564ea9bb 2266 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 2267 *
2268 * Sets the LPLU D3 state according to the active flag. When
2269 * activating LPLU this function also disables smart speed
2270 * and vice versa. LPLU will not be activated unless the
2271 * device autonegotiation advertisement meets standards of
2272 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2273 * This is a function pointer entry point only called by
2274 * PHY setup routines.
2275 **/
2276static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2277{
2278 struct e1000_phy_info *phy = &hw->phy;
2279 u32 phy_ctrl;
d7eb3384 2280 s32 ret_val = 0;
bc7f75fa
AK		 2281 u16 data;
2282
2283 phy_ctrl = er32(PHY_CTRL);
2284
2285 if (!active) {
2286 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2287 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 2288
2289 if (phy->type != e1000_phy_igp_3)
2290 return 0;
2291
e921eb1a 2292 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 2293 * during Dx states where the power conservation is most
2294 * important. During driver activity we should enable
ad68076e
BA		 2295 * SmartSpeed, so performance is maintained.
2296 */
bc7f75fa 2297 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 2298 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2299 &data);
bc7f75fa
AK		 2300 if (ret_val)
2301 return ret_val;
2302
2303 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2304 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2305 data);
bc7f75fa
AK		 2306 if (ret_val)
2307 return ret_val;
2308 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 2309 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2310 &data);
bc7f75fa
AK		 2311 if (ret_val)
2312 return ret_val;
2313
2314 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 2315 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2316 data);
bc7f75fa
AK		 2317 if (ret_val)
2318 return ret_val;
2319 }
2320 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2321 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2322 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2323 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2324 ew32(PHY_CTRL, phy_ctrl);
2325
60f1292f
BA		 2326 if (phy->type != e1000_phy_igp_3)
2327 return 0;
2328
e921eb1a 2329 /* Call gig speed drop workaround on LPLU before accessing
ad68076e
BA		 2330 * any PHY registers
2331 */
60f1292f 2332 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 2333 e1000e_gig_downshift_workaround_ich8lan(hw);
2334
2335 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 2336 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 2337 if (ret_val)
2338 return ret_val;
2339
2340 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 2341 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 2342 }
2343
d7eb3384 2344 return ret_val;
bc7f75fa
AK		 2345}
2346
f4187b56
BA		 2347/**
2348 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2349 * @hw: pointer to the HW structure
2350 * @bank: pointer to the variable that returns the active bank
2351 *
2352 * Reads signature byte from the NVM using the flash access registers.
e243455d 2353 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 2354 **/
2355static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2356{
e243455d 2357 u32 eecd;
f4187b56 2358 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 2359 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2360 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d 2361 u8 sig_byte = 0;
f71dde6a 2362 s32 ret_val;
f4187b56 2363
e243455d
BA		 2364 switch (hw->mac.type) {
2365 case e1000_ich8lan:
2366 case e1000_ich9lan:
2367 eecd = er32(EECD);
2368 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2369 E1000_EECD_SEC1VAL_VALID_MASK) {
2370 if (eecd & E1000_EECD_SEC1VAL)
2371 *bank = 1;
2372 else
2373 *bank = 0;
2374
2375 return 0;
2376 }
434f1392 2377 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
e243455d
BA		 2378 /* fall-thru */
2379 default:
2380 /* set bank to 0 in case flash read fails */
2381 *bank = 0;
2382
2383 /* Check bank 0 */
2384 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
f0ff4398 2385 &sig_byte);
e243455d
BA		 2386 if (ret_val)
2387 return ret_val;
2388 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2389 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 2390 *bank = 0;
e243455d
BA		 2391 return 0;
2392 }
f4187b56 2393
e243455d
BA		 2394 /* Check bank 1 */
2395 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
f0ff4398
BA		 2396 bank1_offset,
2397 &sig_byte);
e243455d
BA		 2398 if (ret_val)
2399 return ret_val;
2400 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2401 E1000_ICH_NVM_SIG_VALUE) {
2402 *bank = 1;
2403 return 0;
f4187b56 2404 }
e243455d 2405
3bb99fe2 2406 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 2407 return -E1000_ERR_NVM;
f4187b56 2408 }
f4187b56
BA		 2409}
2410
bc7f75fa
AK		 2411/**
2412 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2413 * @hw: pointer to the HW structure
2414 * @offset: The offset (in bytes) of the word(s) to read.
2415 * @words: Size of data to read in words
2416 * @data: Pointer to the word(s) to read at offset.
2417 *
2418 * Reads a word(s) from the NVM using the flash access registers.
2419 **/
2420static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2421 u16 *data)
2422{
2423 struct e1000_nvm_info *nvm = &hw->nvm;
2424 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2425 u32 act_offset;
148675a7 2426 s32 ret_val = 0;
f4187b56 2427 u32 bank = 0;
bc7f75fa
AK		 2428 u16 i, word;
2429
2430 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2431 (words == 0)) {
3bb99fe2 2432 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 2433 ret_val = -E1000_ERR_NVM;
2434 goto out;
bc7f75fa
AK		 2435 }
2436
94d8186a 2437 nvm->ops.acquire(hw);
bc7f75fa 2438
f4187b56 2439 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 2440 if (ret_val) {
3bb99fe2 2441 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 2442 bank = 0;
2443 }
f4187b56
BA		 2444
2445 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 2446 act_offset += offset;
2447
148675a7 2448 ret_val = 0;
bc7f75fa 2449 for (i = 0; i < words; i++) {
362e20ca
BA		 2450 if (dev_spec->shadow_ram[offset + i].modified) {
2451 data[i] = dev_spec->shadow_ram[offset + i].value;
bc7f75fa
AK		 2452 } else {
2453 ret_val = e1000_read_flash_word_ich8lan(hw,
2454 act_offset + i,
2455 &word);
2456 if (ret_val)
2457 break;
2458 data[i] = word;
2459 }
2460 }
2461
94d8186a 2462 nvm->ops.release(hw);
bc7f75fa 2463
e243455d
BA		 2464out:
2465 if (ret_val)
3bb99fe2 2466 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2467
bc7f75fa
AK		 2468 return ret_val;
2469}
2470
2471/**
2472 * e1000_flash_cycle_init_ich8lan - Initialize flash
2473 * @hw: pointer to the HW structure
2474 *
2475 * This function does initial flash setup so that a new read/write/erase cycle
2476 * can be started.
2477 **/
2478static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2479{
2480 union ich8_hws_flash_status hsfsts;
2481 s32 ret_val = -E1000_ERR_NVM;
bc7f75fa
AK		 2482
2483 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2484
2485 /* Check if the flash descriptor is valid */
04499ec4 2486 if (!hsfsts.hsf_status.fldesvalid) {
434f1392 2487 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
bc7f75fa
AK		 2488 return -E1000_ERR_NVM;
2489 }
2490
2491 /* Clear FCERR and DAEL in hw status by writing 1 */
2492 hsfsts.hsf_status.flcerr = 1;
2493 hsfsts.hsf_status.dael = 1;
2494
2495 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2496
e921eb1a 2497 /* Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2498 * bit to check against, in order to start a new cycle or
2499 * FDONE bit should be changed in the hardware so that it
489815ce 2500 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2501 * indication whether a cycle is in progress or has been
2502 * completed.
2503 */
2504
04499ec4 2505 if (!hsfsts.hsf_status.flcinprog) {
e921eb1a 2506 /* There is no cycle running at present,
5ff5b664 2507 * so we can start a cycle.
ad68076e
BA		 2508 * Begin by setting Flash Cycle Done.
2509 */
bc7f75fa
AK		 2510 hsfsts.hsf_status.flcdone = 1;
2511 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2512 ret_val = 0;
2513 } else {
f71dde6a 2514 s32 i;
90da0669 2515
e921eb1a 2516 /* Otherwise poll for sometime so the current
ad68076e
BA		 2517 * cycle has a chance to end before giving up.
2518 */
bc7f75fa 2519 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
c8243ee0 2520 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2521 if (!hsfsts.hsf_status.flcinprog) {
bc7f75fa
AK		 2522 ret_val = 0;
2523 break;
2524 }
2525 udelay(1);
2526 }
9e2d7657 2527 if (!ret_val) {
e921eb1a 2528 /* Successful in waiting for previous cycle to timeout,
ad68076e
BA		 2529 * now set the Flash Cycle Done.
2530 */
bc7f75fa
AK		 2531 hsfsts.hsf_status.flcdone = 1;
2532 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2533 } else {
2c73e1fe 2534 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2535 }
2536 }
2537
2538 return ret_val;
2539}
2540
2541/**
2542 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2543 * @hw: pointer to the HW structure
2544 * @timeout: maximum time to wait for completion
2545 *
2546 * This function starts a flash cycle and waits for its completion.
2547 **/
2548static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2549{
2550 union ich8_hws_flash_ctrl hsflctl;
2551 union ich8_hws_flash_status hsfsts;
bc7f75fa
AK		 2552 u32 i = 0;
2553
2554 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2555 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2556 hsflctl.hsf_ctrl.flcgo = 1;
2557 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2558
2559 /* wait till FDONE bit is set to 1 */
2560 do {
2561 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2562 if (hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 2563 break;
2564 udelay(1);
2565 } while (i++ < timeout);
2566
04499ec4 2567 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 2568 return 0;
2569
55920b5e 2570 return -E1000_ERR_NVM;
bc7f75fa
AK		 2571}
2572
2573/**
2574 * e1000_read_flash_word_ich8lan - Read word from flash
2575 * @hw: pointer to the HW structure
2576 * @offset: offset to data location
2577 * @data: pointer to the location for storing the data
2578 *
2579 * Reads the flash word at offset into data. Offset is converted
2580 * to bytes before read.
2581 **/
2582static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2583 u16 *data)
2584{
2585 /* Must convert offset into bytes. */
2586 offset <<= 1;
2587
2588 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2589}
2590
f4187b56
BA		 2591/**
2592 * e1000_read_flash_byte_ich8lan - Read byte from flash
2593 * @hw: pointer to the HW structure
2594 * @offset: The offset of the byte to read.
2595 * @data: Pointer to a byte to store the value read.
2596 *
2597 * Reads a single byte from the NVM using the flash access registers.
2598 **/
2599static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2600 u8 *data)
2601{
2602 s32 ret_val;
2603 u16 word = 0;
2604
2605 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2606 if (ret_val)
2607 return ret_val;
2608
2609 *data = (u8)word;
2610
2611 return 0;
2612}
2613
bc7f75fa
AK		 2614/**
2615 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2616 * @hw: pointer to the HW structure
2617 * @offset: The offset (in bytes) of the byte or word to read.
2618 * @size: Size of data to read, 1=byte 2=word
2619 * @data: Pointer to the word to store the value read.
2620 *
2621 * Reads a byte or word from the NVM using the flash access registers.
2622 **/
2623static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2624 u8 size, u16 *data)
2625{
2626 union ich8_hws_flash_status hsfsts;
2627 union ich8_hws_flash_ctrl hsflctl;
2628 u32 flash_linear_addr;
2629 u32 flash_data = 0;
2630 s32 ret_val = -E1000_ERR_NVM;
2631 u8 count = 0;
2632
2633 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2634 return -E1000_ERR_NVM;
2635
f0ff4398
BA		 2636 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2637 hw->nvm.flash_base_addr);
bc7f75fa
AK		 2638
2639 do {
2640 udelay(1);
2641 /* Steps */
2642 ret_val = e1000_flash_cycle_init_ich8lan(hw);
9e2d7657 2643 if (ret_val)
bc7f75fa
AK		 2644 break;
2645
2646 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2647 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2648 hsflctl.hsf_ctrl.fldbcount = size - 1;
2649 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2650 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2651
2652 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2653
17e813ec
BA		 2654 ret_val =
2655 e1000_flash_cycle_ich8lan(hw,
2656 ICH_FLASH_READ_COMMAND_TIMEOUT);
bc7f75fa 2657
e921eb1a 2658 /* Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2659 * and try the whole sequence a few more times, else
2660 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2661 * least significant byte first msb to lsb
2662 */
9e2d7657 2663 if (!ret_val) {
bc7f75fa 2664 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 2665 if (size == 1)
bc7f75fa 2666 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 2667 else if (size == 2)
bc7f75fa 2668 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 2669 break;
2670 } else {
e921eb1a 2671 /* If we've gotten here, then things are probably
bc7f75fa
AK		 2672 * completely hosed, but if the error condition is
2673 * detected, it won't hurt to give it another try...
2674 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2675 */
2676 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 2677 if (hsfsts.hsf_status.flcerr) {
bc7f75fa
AK		 2678 /* Repeat for some time before giving up. */
2679 continue;
04499ec4 2680 } else if (!hsfsts.hsf_status.flcdone) {
434f1392 2681 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 2682 break;
2683 }
2684 }
2685 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2686
2687 return ret_val;
2688}
2689
2690/**
2691 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2692 * @hw: pointer to the HW structure
2693 * @offset: The offset (in bytes) of the word(s) to write.
2694 * @words: Size of data to write in words
2695 * @data: Pointer to the word(s) to write at offset.
2696 *
2697 * Writes a byte or word to the NVM using the flash access registers.
2698 **/
2699static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2700 u16 *data)
2701{
2702 struct e1000_nvm_info *nvm = &hw->nvm;
2703 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2704 u16 i;
2705
2706 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2707 (words == 0)) {
3bb99fe2 2708 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2709 return -E1000_ERR_NVM;
2710 }
2711
94d8186a 2712 nvm->ops.acquire(hw);
ca15df58 2713
bc7f75fa 2714 for (i = 0; i < words; i++) {
362e20ca
BA		 2715 dev_spec->shadow_ram[offset + i].modified = true;
2716 dev_spec->shadow_ram[offset + i].value = data[i];
bc7f75fa
AK		 2717 }
2718
94d8186a 2719 nvm->ops.release(hw);
ca15df58 2720
bc7f75fa
AK		 2721 return 0;
2722}
2723
2724/**
2725 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2726 * @hw: pointer to the HW structure
2727 *
2728 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2729 * which writes the checksum to the shadow ram. The changes in the shadow
2730 * ram are then committed to the EEPROM by processing each bank at a time
2731 * checking for the modified bit and writing only the pending changes.
489815ce 2732 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2733 * future writes.
2734 **/
2735static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2736{
2737 struct e1000_nvm_info *nvm = &hw->nvm;
2738 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2739 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2740 s32 ret_val;
2741 u16 data;
2742
2743 ret_val = e1000e_update_nvm_checksum_generic(hw);
2744 if (ret_val)
e243455d 2745 goto out;
bc7f75fa
AK		 2746
2747 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2748 goto out;
bc7f75fa 2749
94d8186a 2750 nvm->ops.acquire(hw);
bc7f75fa 2751
e921eb1a 2752 /* We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2753 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2754 * is going to be written
2755 */
f4187b56 2756 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 2757 if (ret_val) {
3bb99fe2 2758 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2759 bank = 0;
e243455d 2760 }
f4187b56
BA		 2761
2762 if (bank == 0) {
bc7f75fa
AK		 2763 new_bank_offset = nvm->flash_bank_size;
2764 old_bank_offset = 0;
e243455d 2765 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 2766 if (ret_val)
2767 goto release;
bc7f75fa
AK		 2768 } else {
2769 old_bank_offset = nvm->flash_bank_size;
2770 new_bank_offset = 0;
e243455d 2771 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 2772 if (ret_val)
2773 goto release;
bc7f75fa
AK		 2774 }
2775
2776 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
e921eb1a 2777 /* Determine whether to write the value stored
bc7f75fa 2778 * in the other NVM bank or a modified value stored
ad68076e
BA		 2779 * in the shadow RAM
2780 */
bc7f75fa
AK		 2781 if (dev_spec->shadow_ram[i].modified) {
2782 data = dev_spec->shadow_ram[i].value;
2783 } else {
e243455d 2784 ret_val = e1000_read_flash_word_ich8lan(hw, i +
f0ff4398
BA		 2785 old_bank_offset,
2786 &data);
e243455d
BA		 2787 if (ret_val)
2788 break;
bc7f75fa
AK		 2789 }
2790
e921eb1a 2791 /* If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2792 * (15:14) are 11b until the commit has completed.
2793 * This will allow us to write 10b which indicates the
2794 * signature is valid. We want to do this after the write
2795 * has completed so that we don't mark the segment valid
ad68076e
BA		 2796 * while the write is still in progress
2797 */
bc7f75fa
AK		 2798 if (i == E1000_ICH_NVM_SIG_WORD)
2799 data |= E1000_ICH_NVM_SIG_MASK;
2800
2801 /* Convert offset to bytes. */
2802 act_offset = (i + new_bank_offset) << 1;
2803
2804 udelay(100);
2805 /* Write the bytes to the new bank. */
2806 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2807 act_offset,
2808 (u8)data);
2809 if (ret_val)
2810 break;
2811
2812 udelay(100);
2813 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
f0ff4398
BA		 2814 act_offset + 1,
2815 (u8)(data >> 8));
bc7f75fa
AK		 2816 if (ret_val)
2817 break;
2818 }
2819
e921eb1a 2820 /* Don't bother writing the segment valid bits if sector
ad68076e
BA		 2821 * programming failed.
2822 */
bc7f75fa 2823 if (ret_val) {
4a770358 2824 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2825 e_dbg("Flash commit failed.\n");
9c5e209d 2826 goto release;
bc7f75fa
AK		 2827 }
2828
e921eb1a 2829 /* Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2830 * to 10b in word 0x13 , this can be done without an
2831 * erase as well since these bits are 11 to start with
ad68076e
BA		 2832 * and we need to change bit 14 to 0b
2833 */
bc7f75fa 2834 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2835 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2836 if (ret_val)
2837 goto release;
2838
bc7f75fa
AK		 2839 data &= 0xBFFF;
2840 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2841 act_offset * 2 + 1,
2842 (u8)(data >> 8));
9c5e209d
BA		 2843 if (ret_val)
2844 goto release;
bc7f75fa 2845
e921eb1a 2846 /* And invalidate the previously valid segment by setting
bc7f75fa
AK		 2847 * its signature word (0x13) high_byte to 0b. This can be
2848 * done without an erase because flash erase sets all bits
ad68076e
BA		 2849 * to 1's. We can write 1's to 0's without an erase
2850 */
bc7f75fa
AK		 2851 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2852 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2853 if (ret_val)
2854 goto release;
bc7f75fa
AK		 2855
2856 /* Great! Everything worked, we can now clear the cached entries. */
2857 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2858 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2859 dev_spec->shadow_ram[i].value = 0xFFFF;
2860 }
2861
9c5e209d 2862release:
94d8186a 2863 nvm->ops.release(hw);
bc7f75fa 2864
e921eb1a 2865 /* Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2866 * until after the next adapter reset.
2867 */
9c5e209d 2868 if (!ret_val) {
e85e3639 2869 nvm->ops.reload(hw);
1bba4386 2870 usleep_range(10000, 20000);
9c5e209d 2871 }
bc7f75fa 2872
e243455d
BA		 2873out:
2874 if (ret_val)
3bb99fe2 2875 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2876
bc7f75fa
AK		 2877 return ret_val;
2878}
2879
2880/**
2881 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2882 * @hw: pointer to the HW structure
2883 *
2884 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2885 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2886 * calculated, in which case we need to calculate the checksum and set bit 6.
2887 **/
2888static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2889{
2890 s32 ret_val;
2891 u16 data;
1cc7a3a1
BA		 2892 u16 word;
2893 u16 valid_csum_mask;
bc7f75fa 2894
1cc7a3a1
BA		 2895 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
2896 * the checksum needs to be fixed. This bit is an indication that
2897 * the NVM was prepared by OEM software and did not calculate
2898 * the checksum...a likely scenario.
bc7f75fa 2899 */
1cc7a3a1
BA		 2900 switch (hw->mac.type) {
2901 case e1000_pch_lpt:
2902 word = NVM_COMPAT;
2903 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
2904 break;
2905 default:
2906 word = NVM_FUTURE_INIT_WORD1;
2907 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
2908 break;
2909 }
2910
2911 ret_val = e1000_read_nvm(hw, word, 1, &data);
bc7f75fa
AK		 2912 if (ret_val)
2913 return ret_val;
2914
1cc7a3a1
BA		 2915 if (!(data & valid_csum_mask)) {
2916 data |= valid_csum_mask;
2917 ret_val = e1000_write_nvm(hw, word, 1, &data);
bc7f75fa
AK		 2918 if (ret_val)
2919 return ret_val;
2920 ret_val = e1000e_update_nvm_checksum(hw);
2921 if (ret_val)
2922 return ret_val;
2923 }
2924
2925 return e1000e_validate_nvm_checksum_generic(hw);
2926}
2927
4a770358
BA		 2928/**
2929 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2930 * @hw: pointer to the HW structure
2931 *
2932 * To prevent malicious write/erase of the NVM, set it to be read-only
2933 * so that the hardware ignores all write/erase cycles of the NVM via
2934 * the flash control registers. The shadow-ram copy of the NVM will
2935 * still be updated, however any updates to this copy will not stick
2936 * across driver reloads.
2937 **/
2938void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2939{
ca15df58 2940 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2941 union ich8_flash_protected_range pr0;
2942 union ich8_hws_flash_status hsfsts;
2943 u32 gfpreg;
4a770358 2944
94d8186a 2945 nvm->ops.acquire(hw);
4a770358
BA		 2946
2947 gfpreg = er32flash(ICH_FLASH_GFPREG);
2948
2949 /* Write-protect GbE Sector of NVM */
2950 pr0.regval = er32flash(ICH_FLASH_PR0);
2951 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2952 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2953 pr0.range.wpe = true;
2954 ew32flash(ICH_FLASH_PR0, pr0.regval);
2955
e921eb1a 2956 /* Lock down a subset of GbE Flash Control Registers, e.g.
4a770358
BA		 2957 * PR0 to prevent the write-protection from being lifted.
2958 * Once FLOCKDN is set, the registers protected by it cannot
2959 * be written until FLOCKDN is cleared by a hardware reset.
2960 */
2961 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2962 hsfsts.hsf_status.flockdn = true;
2963 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2964
94d8186a 2965 nvm->ops.release(hw);
4a770358
BA		 2966}
2967
bc7f75fa
AK		 2968/**
2969 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2970 * @hw: pointer to the HW structure
2971 * @offset: The offset (in bytes) of the byte/word to read.
2972 * @size: Size of data to read, 1=byte 2=word
2973 * @data: The byte(s) to write to the NVM.
2974 *
2975 * Writes one/two bytes to the NVM using the flash access registers.
2976 **/
2977static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2978 u8 size, u16 data)
2979{
2980 union ich8_hws_flash_status hsfsts;
2981 union ich8_hws_flash_ctrl hsflctl;
2982 u32 flash_linear_addr;
2983 u32 flash_data = 0;
2984 s32 ret_val;
2985 u8 count = 0;
2986
2987 if (size < 1 || size > 2 || data > size * 0xff ||
2988 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2989 return -E1000_ERR_NVM;
2990
f0ff4398
BA		 2991 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2992 hw->nvm.flash_base_addr);
bc7f75fa
AK		 2993
2994 do {
2995 udelay(1);
2996 /* Steps */
2997 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2998 if (ret_val)
2999 break;
3000
3001 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3002 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
362e20ca 3003 hsflctl.hsf_ctrl.fldbcount = size - 1;
bc7f75fa
AK		 3004 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3005 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3006
3007 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3008
3009 if (size == 1)
3010 flash_data = (u32)data & 0x00FF;
3011 else
3012 flash_data = (u32)data;
3013
3014 ew32flash(ICH_FLASH_FDATA0, flash_data);
3015
e921eb1a 3016 /* check if FCERR is set to 1 , if set to 1, clear it
ad68076e
BA		 3017 * and try the whole sequence a few more times else done
3018 */
17e813ec
BA		 3019 ret_val =
3020 e1000_flash_cycle_ich8lan(hw,
3021 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
bc7f75fa
AK		 3022 if (!ret_val)
3023 break;
3024
e921eb1a 3025 /* If we're here, then things are most likely
bc7f75fa
AK		 3026 * completely hosed, but if the error condition
3027 * is detected, it won't hurt to give it another
3028 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3029 */
3030 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3031 if (hsfsts.hsf_status.flcerr)
bc7f75fa
AK		 3032 /* Repeat for some time before giving up. */
3033 continue;
04499ec4 3034 if (!hsfsts.hsf_status.flcdone) {
434f1392 3035 e_dbg("Timeout error - flash cycle did not complete.\n");
bc7f75fa
AK		 3036 break;
3037 }
3038 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3039
3040 return ret_val;
3041}
3042
3043/**
3044 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3045 * @hw: pointer to the HW structure
3046 * @offset: The index of the byte to read.
3047 * @data: The byte to write to the NVM.
3048 *
3049 * Writes a single byte to the NVM using the flash access registers.
3050 **/
3051static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3052 u8 data)
3053{
3054 u16 word = (u16)data;
3055
3056 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3057}
3058
3059/**
3060 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3061 * @hw: pointer to the HW structure
3062 * @offset: The offset of the byte to write.
3063 * @byte: The byte to write to the NVM.
3064 *
3065 * Writes a single byte to the NVM using the flash access registers.
3066 * Goes through a retry algorithm before giving up.
3067 **/
3068static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3069 u32 offset, u8 byte)
3070{
3071 s32 ret_val;
3072 u16 program_retries;
3073
3074 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3075 if (!ret_val)
3076 return ret_val;
3077
3078 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 3079 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 3080 udelay(100);
3081 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3082 if (!ret_val)
3083 break;
3084 }
3085 if (program_retries == 100)
3086 return -E1000_ERR_NVM;
3087
3088 return 0;
3089}
3090
3091/**
3092 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3093 * @hw: pointer to the HW structure
3094 * @bank: 0 for first bank, 1 for second bank, etc.
3095 *
3096 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3097 * bank N is 4096 * N + flash_reg_addr.
3098 **/
3099static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3100{
3101 struct e1000_nvm_info *nvm = &hw->nvm;
3102 union ich8_hws_flash_status hsfsts;
3103 union ich8_hws_flash_ctrl hsflctl;
3104 u32 flash_linear_addr;
3105 /* bank size is in 16bit words - adjust to bytes */
3106 u32 flash_bank_size = nvm->flash_bank_size * 2;
3107 s32 ret_val;
3108 s32 count = 0;
a708dd88 3109 s32 j, iteration, sector_size;
bc7f75fa
AK		 3110
3111 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3112
e921eb1a 3113 /* Determine HW Sector size: Read BERASE bits of hw flash status
ad68076e
BA		 3114 * register
3115 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 3116 * consecutive sectors. The start index for the nth Hw sector
3117 * can be calculated as = bank * 4096 + n * 256
3118 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3119 * The start index for the nth Hw sector can be calculated
3120 * as = bank * 4096
3121 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3122 * (ich9 only, otherwise error condition)
3123 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3124 */
3125 switch (hsfsts.hsf_status.berasesz) {
3126 case 0:
3127 /* Hw sector size 256 */
3128 sector_size = ICH_FLASH_SEG_SIZE_256;
3129 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3130 break;
3131 case 1:
3132 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 3133 iteration = 1;
bc7f75fa
AK		 3134 break;
3135 case 2:
148675a7
BA		 3136 sector_size = ICH_FLASH_SEG_SIZE_8K;
3137 iteration = 1;
bc7f75fa
AK		 3138 break;
3139 case 3:
3140 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 3141 iteration = 1;
bc7f75fa
AK		 3142 break;
3143 default:
3144 return -E1000_ERR_NVM;
3145 }
3146
3147 /* Start with the base address, then add the sector offset. */
3148 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 3149 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa 3150
53aa82da 3151 for (j = 0; j < iteration; j++) {
bc7f75fa 3152 do {
17e813ec
BA		 3153 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
3154
bc7f75fa
AK		 3155 /* Steps */
3156 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3157 if (ret_val)
3158 return ret_val;
3159
e921eb1a 3160 /* Write a value 11 (block Erase) in Flash
ad68076e
BA		 3161 * Cycle field in hw flash control
3162 */
bc7f75fa
AK		 3163 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3164 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3165 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3166
e921eb1a 3167 /* Write the last 24 bits of an index within the
bc7f75fa
AK		 3168 * block into Flash Linear address field in Flash
3169 * Address.
3170 */
3171 flash_linear_addr += (j * sector_size);
3172 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3173
17e813ec 3174 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
9e2d7657 3175 if (!ret_val)
bc7f75fa
AK		 3176 break;
3177
e921eb1a 3178 /* Check if FCERR is set to 1. If 1,
bc7f75fa 3179 * clear it and try the whole sequence
ad68076e
BA		 3180 * a few more times else Done
3181 */
bc7f75fa 3182 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
04499ec4 3183 if (hsfsts.hsf_status.flcerr)
ad68076e 3184 /* repeat for some time before giving up */
bc7f75fa 3185 continue;
04499ec4 3186 else if (!hsfsts.hsf_status.flcdone)
bc7f75fa
AK		 3187 return ret_val;
3188 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3189 }
3190
3191 return 0;
3192}
3193
3194/**
3195 * e1000_valid_led_default_ich8lan - Set the default LED settings
3196 * @hw: pointer to the HW structure
3197 * @data: Pointer to the LED settings
3198 *
3199 * Reads the LED default settings from the NVM to data. If the NVM LED
3200 * settings is all 0's or F's, set the LED default to a valid LED default
3201 * setting.
3202 **/
3203static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3204{
3205 s32 ret_val;
3206
3207 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3208 if (ret_val) {
3bb99fe2 3209 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 3210 return ret_val;
3211 }
3212
e5fe2541 3213 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
bc7f75fa
AK		 3214 *data = ID_LED_DEFAULT_ICH8LAN;
3215
3216 return 0;
3217}
3218
a4f58f54
BA		 3219/**
3220 * e1000_id_led_init_pchlan - store LED configurations
3221 * @hw: pointer to the HW structure
3222 *
3223 * PCH does not control LEDs via the LEDCTL register, rather it uses
3224 * the PHY LED configuration register.
3225 *
3226 * PCH also does not have an "always on" or "always off" mode which
3227 * complicates the ID feature. Instead of using the "on" mode to indicate
d1964eb1 3228 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
a4f58f54
BA		 3229 * use "link_up" mode. The LEDs will still ID on request if there is no
3230 * link based on logic in e1000_led_[on|off]_pchlan().
3231 **/
3232static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3233{
3234 struct e1000_mac_info *mac = &hw->mac;
3235 s32 ret_val;
3236 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3237 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3238 u16 data, i, temp, shift;
3239
3240 /* Get default ID LED modes */
3241 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3242 if (ret_val)
5015e53a 3243 return ret_val;
a4f58f54
BA		 3244
3245 mac->ledctl_default = er32(LEDCTL);
3246 mac->ledctl_mode1 = mac->ledctl_default;
3247 mac->ledctl_mode2 = mac->ledctl_default;
3248
3249 for (i = 0; i < 4; i++) {
3250 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3251 shift = (i * 5);
3252 switch (temp) {
3253 case ID_LED_ON1_DEF2:
3254 case ID_LED_ON1_ON2:
3255 case ID_LED_ON1_OFF2:
3256 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3257 mac->ledctl_mode1 |= (ledctl_on << shift);
3258 break;
3259 case ID_LED_OFF1_DEF2:
3260 case ID_LED_OFF1_ON2:
3261 case ID_LED_OFF1_OFF2:
3262 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3263 mac->ledctl_mode1 |= (ledctl_off << shift);
3264 break;
3265 default:
3266 /* Do nothing */
3267 break;
3268 }
3269 switch (temp) {
3270 case ID_LED_DEF1_ON2:
3271 case ID_LED_ON1_ON2:
3272 case ID_LED_OFF1_ON2:
3273 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3274 mac->ledctl_mode2 |= (ledctl_on << shift);
3275 break;
3276 case ID_LED_DEF1_OFF2:
3277 case ID_LED_ON1_OFF2:
3278 case ID_LED_OFF1_OFF2:
3279 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3280 mac->ledctl_mode2 |= (ledctl_off << shift);
3281 break;
3282 default:
3283 /* Do nothing */
3284 break;
3285 }
3286 }
3287
5015e53a 3288 return 0;
a4f58f54
BA		 3289}
3290
bc7f75fa
AK		 3291/**
3292 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3293 * @hw: pointer to the HW structure
3294 *
3295 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3296 * register, so the the bus width is hard coded.
3297 **/
3298static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3299{
3300 struct e1000_bus_info *bus = &hw->bus;
3301 s32 ret_val;
3302
3303 ret_val = e1000e_get_bus_info_pcie(hw);
3304
e921eb1a 3305 /* ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 3306 * a configuration space, but do not contain
3307 * PCI Express Capability registers, so bus width
3308 * must be hardcoded.
3309 */
3310 if (bus->width == e1000_bus_width_unknown)
3311 bus->width = e1000_bus_width_pcie_x1;
3312
3313 return ret_val;
3314}
3315
3316/**
3317 * e1000_reset_hw_ich8lan - Reset the hardware
3318 * @hw: pointer to the HW structure
3319 *
3320 * Does a full reset of the hardware which includes a reset of the PHY and
3321 * MAC.
3322 **/
3323static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3324{
1d5846b9 3325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
62bc813e
BA		 3326 u16 kum_cfg;
3327 u32 ctrl, reg;
bc7f75fa
AK		 3328 s32 ret_val;
3329
e921eb1a 3330 /* Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 3331 * on the last TLP read/write transaction when MAC is reset.
3332 */
3333 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 3334 if (ret_val)
3bb99fe2 3335 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 3336
3bb99fe2 3337 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 3338 ew32(IMC, 0xffffffff);
3339
e921eb1a 3340 /* Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 3341 * any pending transactions to complete before we hit the MAC
3342 * with the global reset.
3343 */
3344 ew32(RCTL, 0);
3345 ew32(TCTL, E1000_TCTL_PSP);
3346 e1e_flush();
3347
1bba4386 3348 usleep_range(10000, 20000);
bc7f75fa
AK		 3349
3350 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3351 if (hw->mac.type == e1000_ich8lan) {
3352 /* Set Tx and Rx buffer allocation to 8k apiece. */
3353 ew32(PBA, E1000_PBA_8K);
3354 /* Set Packet Buffer Size to 16k. */
3355 ew32(PBS, E1000_PBS_16K);
3356 }
3357
1d5846b9 3358 if (hw->mac.type == e1000_pchlan) {
62bc813e
BA		 3359 /* Save the NVM K1 bit setting */
3360 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
1d5846b9
BA		 3361 if (ret_val)
3362 return ret_val;
3363
62bc813e 3364 if (kum_cfg & E1000_NVM_K1_ENABLE)
1d5846b9
BA		 3365 dev_spec->nvm_k1_enabled = true;
3366 else
3367 dev_spec->nvm_k1_enabled = false;
3368 }
3369
bc7f75fa
AK		 3370 ctrl = er32(CTRL);
3371
44abd5c1 3372 if (!hw->phy.ops.check_reset_block(hw)) {
e921eb1a 3373 /* Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 3374 * time to make sure the interface between MAC and the
3375 * external PHY is reset.
3376 */
3377 ctrl |= E1000_CTRL_PHY_RST;
605c82ba 3378
e921eb1a 3379 /* Gate automatic PHY configuration by hardware on
605c82ba
BA		 3380 * non-managed 82579
3381 */
3382 if ((hw->mac.type == e1000_pch2lan) &&
3383 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3384 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 3385 }
3386 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 3387 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa 3388 ew32(CTRL, (ctrl | E1000_CTRL_RST));
945a5151 3389 /* cannot issue a flush here because it hangs the hardware */
bc7f75fa
AK		 3390 msleep(20);
3391
62bc813e
BA		 3392 /* Set Phy Config Counter to 50msec */
3393 if (hw->mac.type == e1000_pch2lan) {
3394 reg = er32(FEXTNVM3);
3395 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3396 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3397 ew32(FEXTNVM3, reg);
3398 }
3399
fc0c7760 3400 if (!ret_val)
a90b412c 3401 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
37f40239 3402
e98cac44 3403 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 3404 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44 3405 if (ret_val)
5015e53a 3406 return ret_val;
fc0c7760 3407
e98cac44 3408 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211 3409 if (ret_val)
5015e53a 3410 return ret_val;
f523d211 3411 }
e98cac44 3412
e921eb1a 3413 /* For PCH, this write will make sure that any noise
7d3cabbc
BA		 3414 * will be detected as a CRC error and be dropped rather than show up
3415 * as a bad packet to the DMA engine.
3416 */
3417 if (hw->mac.type == e1000_pchlan)
3418 ew32(CRC_OFFSET, 0x65656565);
3419
bc7f75fa 3420 ew32(IMC, 0xffffffff);
dd93f95e 3421 er32(ICR);
bc7f75fa 3422
62bc813e
BA		 3423 reg = er32(KABGTXD);
3424 reg |= E1000_KABGTXD_BGSQLBIAS;
3425 ew32(KABGTXD, reg);
bc7f75fa 3426
5015e53a 3427 return 0;
bc7f75fa
AK		 3428}
3429
3430/**
3431 * e1000_init_hw_ich8lan - Initialize the hardware
3432 * @hw: pointer to the HW structure
3433 *
3434 * Prepares the hardware for transmit and receive by doing the following:
3435 * - initialize hardware bits
3436 * - initialize LED identification
3437 * - setup receive address registers
3438 * - setup flow control
489815ce 3439 * - setup transmit descriptors
bc7f75fa
AK		 3440 * - clear statistics
3441 **/
3442static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3443{
3444 struct e1000_mac_info *mac = &hw->mac;
3445 u32 ctrl_ext, txdctl, snoop;
3446 s32 ret_val;
3447 u16 i;
3448
3449 e1000_initialize_hw_bits_ich8lan(hw);
3450
3451 /* Initialize identification LED */
a4f58f54 3452 ret_val = mac->ops.id_led_init(hw);
33550cec 3453 /* An error is not fatal and we should not stop init due to this */
de39b752 3454 if (ret_val)
3bb99fe2 3455 e_dbg("Error initializing identification LED\n");
bc7f75fa
AK		 3456
3457 /* Setup the receive address. */
3458 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3459
3460 /* Zero out the Multicast HASH table */
3bb99fe2 3461 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3462 for (i = 0; i < mac->mta_reg_count; i++)
3463 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3464
e921eb1a 3465 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3ebfc7c9 3466 * the ME. Disable wakeup by clearing the host wakeup bit.
fc0c7760
BA		 3467 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3468 */
3469 if (hw->phy.type == e1000_phy_82578) {
3ebfc7c9
BA		 3470 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3471 i &= ~BM_WUC_HOST_WU_BIT;
3472 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
fc0c7760
BA		 3473 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3474 if (ret_val)
3475 return ret_val;
3476 }
3477
bc7f75fa 3478 /* Setup link and flow control */
1a46b40f 3479 ret_val = mac->ops.setup_link(hw);
bc7f75fa
AK		 3480
3481 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3482 txdctl = er32(TXDCTL(0));
f0ff4398
BA		 3483 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3484 E1000_TXDCTL_FULL_TX_DESC_WB);
3485 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3486 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f
JK		 3487 ew32(TXDCTL(0), txdctl);
3488 txdctl = er32(TXDCTL(1));
f0ff4398
BA		 3489 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
3490 E1000_TXDCTL_FULL_TX_DESC_WB);
3491 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
3492 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
e9ec2c0f 3493 ew32(TXDCTL(1), txdctl);
bc7f75fa 3494
e921eb1a 3495 /* ICH8 has opposite polarity of no_snoop bits.
ad68076e
BA		 3496 * By default, we should use snoop behavior.
3497 */
bc7f75fa
AK		 3498 if (mac->type == e1000_ich8lan)
3499 snoop = PCIE_ICH8_SNOOP_ALL;
3500 else
53aa82da 3501 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
bc7f75fa
AK		 3502 e1000e_set_pcie_no_snoop(hw, snoop);
3503
3504 ctrl_ext = er32(CTRL_EXT);
3505 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3506 ew32(CTRL_EXT, ctrl_ext);
3507
e921eb1a 3508 /* Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3509 * important that we do this after we have tried to establish link
3510 * because the symbol error count will increment wildly if there
3511 * is no link.
3512 */
3513 e1000_clear_hw_cntrs_ich8lan(hw);
3514
e561a705 3515 return ret_val;
bc7f75fa 3516}
fc830b78 3517
bc7f75fa
AK		 3518/**
3519 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3520 * @hw: pointer to the HW structure
3521 *
3522 * Sets/Clears required hardware bits necessary for correctly setting up the
3523 * hardware for transmit and receive.
3524 **/
3525static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3526{
3527 u32 reg;
3528
3529 /* Extended Device Control */
3530 reg = er32(CTRL_EXT);
3531 reg |= (1 << 22);
a4f58f54
BA		 3532 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3533 if (hw->mac.type >= e1000_pchlan)
3534 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3535 ew32(CTRL_EXT, reg);
3536
3537 /* Transmit Descriptor Control 0 */
e9ec2c0f 3538 reg = er32(TXDCTL(0));
bc7f75fa 3539 reg |= (1 << 22);
e9ec2c0f 3540 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3541
3542 /* Transmit Descriptor Control 1 */
e9ec2c0f 3543 reg = er32(TXDCTL(1));
bc7f75fa 3544 reg |= (1 << 22);
e9ec2c0f 3545 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3546
3547 /* Transmit Arbitration Control 0 */
e9ec2c0f 3548 reg = er32(TARC(0));
bc7f75fa
AK		 3549 if (hw->mac.type == e1000_ich8lan)
3550 reg |= (1 << 28) | (1 << 29);
3551 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3552 ew32(TARC(0), reg);
bc7f75fa
AK		 3553
3554 /* Transmit Arbitration Control 1 */
e9ec2c0f 3555 reg = er32(TARC(1));
bc7f75fa
AK		 3556 if (er32(TCTL) & E1000_TCTL_MULR)
3557 reg &= ~(1 << 28);
3558 else
3559 reg |= (1 << 28);
3560 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3561 ew32(TARC(1), reg);
bc7f75fa
AK		 3562
3563 /* Device Status */
3564 if (hw->mac.type == e1000_ich8lan) {
3565 reg = er32(STATUS);
3566 reg &= ~(1 << 31);
3567 ew32(STATUS, reg);
3568 }
a80483d3 3569
e921eb1a 3570 /* work-around descriptor data corruption issue during nfs v2 udp
a80483d3
JB		 3571 * traffic, just disable the nfs filtering capability
3572 */
3573 reg = er32(RFCTL);
3574 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
f6bd5577 3575
e921eb1a 3576 /* Disable IPv6 extension header parsing because some malformed
f6bd5577
MV		 3577 * IPv6 headers can hang the Rx.
3578 */
3579 if (hw->mac.type == e1000_ich8lan)
3580 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
a80483d3 3581 ew32(RFCTL, reg);
94fb848b
BA		 3582
3583 /* Enable ECC on Lynxpoint */
3584 if (hw->mac.type == e1000_pch_lpt) {
3585 reg = er32(PBECCSTS);
3586 reg |= E1000_PBECCSTS_ECC_ENABLE;
3587 ew32(PBECCSTS, reg);
3588
3589 reg = er32(CTRL);
3590 reg |= E1000_CTRL_MEHE;
3591 ew32(CTRL, reg);
3592 }
bc7f75fa
AK		 3593}
3594
3595/**
3596 * e1000_setup_link_ich8lan - Setup flow control and link settings
3597 * @hw: pointer to the HW structure
3598 *
3599 * Determines which flow control settings to use, then configures flow
3600 * control. Calls the appropriate media-specific link configuration
3601 * function. Assuming the adapter has a valid link partner, a valid link
3602 * should be established. Assumes the hardware has previously been reset
3603 * and the transmitter and receiver are not enabled.
3604 **/
3605static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3606{
bc7f75fa
AK		 3607 s32 ret_val;
3608
44abd5c1 3609 if (hw->phy.ops.check_reset_block(hw))
bc7f75fa
AK		 3610 return 0;
3611
e921eb1a 3612 /* ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3613 * the default flow control setting, so we explicitly
3614 * set it to full.
3615 */
37289d9c
BA		 3616 if (hw->fc.requested_mode == e1000_fc_default) {
3617 /* Workaround h/w hang when Tx flow control enabled */
3618 if (hw->mac.type == e1000_pchlan)
3619 hw->fc.requested_mode = e1000_fc_rx_pause;
3620 else
3621 hw->fc.requested_mode = e1000_fc_full;
3622 }
bc7f75fa 3623
e921eb1a 3624 /* Save off the requested flow control mode for use later. Depending
5c48ef3e
BA		 3625 * on the link partner's capabilities, we may or may not use this mode.
3626 */
3627 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3628
17e813ec 3629 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
bc7f75fa
AK		 3630
3631 /* Continue to configure the copper link. */
944ce011 3632 ret_val = hw->mac.ops.setup_physical_interface(hw);
bc7f75fa
AK		 3633 if (ret_val)
3634 return ret_val;
3635
318a94d6 3636 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3637 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3638 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 3639 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 3640 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3641 ew32(FCRTV_PCH, hw->fc.refresh_time);
3642
482fed85
BA		 3643 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3644 hw->fc.pause_time);
a4f58f54
BA		 3645 if (ret_val)
3646 return ret_val;
3647 }
bc7f75fa
AK		 3648
3649 return e1000e_set_fc_watermarks(hw);
3650}
3651
3652/**
3653 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3654 * @hw: pointer to the HW structure
3655 *
3656 * Configures the kumeran interface to the PHY to wait the appropriate time
3657 * when polling the PHY, then call the generic setup_copper_link to finish
3658 * configuring the copper link.
3659 **/
3660static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3661{
3662 u32 ctrl;
3663 s32 ret_val;
3664 u16 reg_data;
3665
3666 ctrl = er32(CTRL);
3667 ctrl |= E1000_CTRL_SLU;
3668 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3669 ew32(CTRL, ctrl);
3670
e921eb1a 3671 /* Set the mac to wait the maximum time between each iteration
bc7f75fa 3672 * and increase the max iterations when polling the phy;
ad68076e
BA		 3673 * this fixes erroneous timeouts at 10Mbps.
3674 */
07818950 3675 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3676 if (ret_val)
3677 return ret_val;
07818950 3678 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 3679 &reg_data);
bc7f75fa
AK		 3680 if (ret_val)
3681 return ret_val;
3682 reg_data |= 0x3F;
07818950 3683 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
f0ff4398 3684 reg_data);
bc7f75fa
AK		 3685 if (ret_val)
3686 return ret_val;
3687
a4f58f54
BA		 3688 switch (hw->phy.type) {
3689 case e1000_phy_igp_3:
bc7f75fa
AK		 3690 ret_val = e1000e_copper_link_setup_igp(hw);
3691 if (ret_val)
3692 return ret_val;
a4f58f54
BA		 3693 break;
3694 case e1000_phy_bm:
3695 case e1000_phy_82578:
97ac8cae
BA		 3696 ret_val = e1000e_copper_link_setup_m88(hw);
3697 if (ret_val)
3698 return ret_val;
a4f58f54
BA		 3699 break;
3700 case e1000_phy_82577:
d3738bb8 3701 case e1000_phy_82579:
2fbe4526 3702 case e1000_phy_i217:
a4f58f54
BA		 3703 ret_val = e1000_copper_link_setup_82577(hw);
3704 if (ret_val)
3705 return ret_val;
3706 break;
3707 case e1000_phy_ife:
482fed85 3708 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
97ac8cae
BA		 3709 if (ret_val)
3710 return ret_val;
3711
3712 reg_data &= ~IFE_PMC_AUTO_MDIX;
3713
3714 switch (hw->phy.mdix) {
3715 case 1:
3716 reg_data &= ~IFE_PMC_FORCE_MDIX;
3717 break;
3718 case 2:
3719 reg_data |= IFE_PMC_FORCE_MDIX;
3720 break;
3721 case 0:
3722 default:
3723 reg_data |= IFE_PMC_AUTO_MDIX;
3724 break;
3725 }
482fed85 3726 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
97ac8cae
BA		 3727 if (ret_val)
3728 return ret_val;
a4f58f54
BA		 3729 break;
3730 default:
3731 break;
97ac8cae 3732 }
3fa82936 3733
bc7f75fa
AK		 3734 return e1000e_setup_copper_link(hw);
3735}
3736
3737/**
3738 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3739 * @hw: pointer to the HW structure
3740 * @speed: pointer to store current link speed
3741 * @duplex: pointer to store the current link duplex
3742 *
ad68076e 3743 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 3744 * information and then calls the Kumeran lock loss workaround for links at
3745 * gigabit speeds.
3746 **/
3747static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3748 u16 *duplex)
3749{
3750 s32 ret_val;
3751
3752 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3753 if (ret_val)
3754 return ret_val;
3755
3756 if ((hw->mac.type == e1000_ich8lan) &&
e5fe2541 3757 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
bc7f75fa
AK		 3758 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3759 }
3760
3761 return ret_val;
3762}
3763
3764/**
3765 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3766 * @hw: pointer to the HW structure
3767 *
3768 * Work-around for 82566 Kumeran PCS lock loss:
3769 * On link status change (i.e. PCI reset, speed change) and link is up and
3770 * speed is gigabit-
3771 * 0) if workaround is optionally disabled do nothing
3772 * 1) wait 1ms for Kumeran link to come up
3773 * 2) check Kumeran Diagnostic register PCS lock loss bit
3774 * 3) if not set the link is locked (all is good), otherwise...
3775 * 4) reset the PHY
3776 * 5) repeat up to 10 times
3777 * Note: this is only called for IGP3 copper when speed is 1gb.
3778 **/
3779static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3780{
3781 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3782 u32 phy_ctrl;
3783 s32 ret_val;
3784 u16 i, data;
3785 bool link;
3786
3787 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3788 return 0;
3789
e921eb1a 3790 /* Make sure link is up before proceeding. If not just return.
bc7f75fa 3791 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3792 * stability
3793 */
bc7f75fa
AK		 3794 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3795 if (!link)
3796 return 0;
3797
3798 for (i = 0; i < 10; i++) {
3799 /* read once to clear */
3800 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3801 if (ret_val)
3802 return ret_val;
3803 /* and again to get new status */
3804 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3805 if (ret_val)
3806 return ret_val;
3807
3808 /* check for PCS lock */
3809 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3810 return 0;
3811
3812 /* Issue PHY reset */
3813 e1000_phy_hw_reset(hw);
3814 mdelay(5);
3815 }
3816 /* Disable GigE link negotiation */
3817 phy_ctrl = er32(PHY_CTRL);
3818 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3819 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3820 ew32(PHY_CTRL, phy_ctrl);
3821
e921eb1a 3822 /* Call gig speed drop workaround on Gig disable before accessing
ad68076e
BA		 3823 * any PHY registers
3824 */
bc7f75fa
AK		 3825 e1000e_gig_downshift_workaround_ich8lan(hw);
3826
3827 /* unable to acquire PCS lock */
3828 return -E1000_ERR_PHY;
3829}
3830
3831/**
6e3c8075 3832 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3833 * @hw: pointer to the HW structure
489815ce 3834 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3835 *
564ea9bb
BA		 3836 * If ICH8, set the current Kumeran workaround state (enabled - true
3837 * /disabled - false).
bc7f75fa
AK		 3838 **/
3839void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
17e813ec 3840 bool state)
bc7f75fa
AK		 3841{
3842 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3843
3844 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3845 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3846 return;
3847 }
3848
3849 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3850}
3851
3852/**
3853 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3854 * @hw: pointer to the HW structure
3855 *
3856 * Workaround for 82566 power-down on D3 entry:
3857 * 1) disable gigabit link
3858 * 2) write VR power-down enable
3859 * 3) read it back
3860 * Continue if successful, else issue LCD reset and repeat
3861 **/
3862void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3863{
3864 u32 reg;
3865 u16 data;
3866 u8 retry = 0;
3867
3868 if (hw->phy.type != e1000_phy_igp_3)
3869 return;
3870
3871 /* Try the workaround twice (if needed) */
3872 do {
3873 /* Disable link */
3874 reg = er32(PHY_CTRL);
3875 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3876 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3877 ew32(PHY_CTRL, reg);
3878
e921eb1a 3879 /* Call gig speed drop workaround on Gig disable before
ad68076e
BA		 3880 * accessing any PHY registers
3881 */
bc7f75fa
AK		 3882 if (hw->mac.type == e1000_ich8lan)
3883 e1000e_gig_downshift_workaround_ich8lan(hw);
3884
3885 /* Write VR power-down enable */
3886 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3887 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3888 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3889
3890 /* Read it back and test */
3891 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3892 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3893 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3894 break;
3895
3896 /* Issue PHY reset and repeat at most one more time */
3897 reg = er32(CTRL);
3898 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3899 retry++;
3900 } while (retry);
3901}
3902
3903/**
3904 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3905 * @hw: pointer to the HW structure
3906 *
3907 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3908 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3909 * 1) Set Kumeran Near-end loopback
3910 * 2) Clear Kumeran Near-end loopback
462d5994 3911 * Should only be called for ICH8[m] devices with any 1G Phy.
bc7f75fa
AK		 3912 **/
3913void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3914{
3915 s32 ret_val;
3916 u16 reg_data;
3917
462d5994 3918 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
bc7f75fa
AK		 3919 return;
3920
3921 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 3922 &reg_data);
bc7f75fa
AK		 3923 if (ret_val)
3924 return;
3925 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3926 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
17e813ec 3927 reg_data);
bc7f75fa
AK		 3928 if (ret_val)
3929 return;
3930 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
7dbbe5d5 3931 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
bc7f75fa
AK		 3932}
3933
97ac8cae 3934/**
99730e4c 3935 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
97ac8cae
BA		 3936 * @hw: pointer to the HW structure
3937 *
3938 * During S0 to Sx transition, it is possible the link remains at gig
3939 * instead of negotiating to a lower speed. Before going to Sx, set
c077a906
BA		 3940 * 'Gig Disable' to force link speed negotiation to a lower speed based on
3941 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
3942 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3943 * needs to be written.
2fbe4526
BA		 3944 * Parts that support (and are linked to a partner which support) EEE in
3945 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
3946 * than 10Mbps w/o EEE.
97ac8cae 3947 **/
99730e4c 3948void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
97ac8cae 3949{
2fbe4526 3950 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
97ac8cae 3951 u32 phy_ctrl;
8395ae83 3952 s32 ret_val;
97ac8cae 3953
17f085df 3954 phy_ctrl = er32(PHY_CTRL);
c077a906 3955 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
2fbe4526
BA		 3956 if (hw->phy.type == e1000_phy_i217) {
3957 u16 phy_reg;
3958
3959 ret_val = hw->phy.ops.acquire(hw);
3960 if (ret_val)
3961 goto out;
3962
3963 if (!dev_spec->eee_disable) {
3964 u16 eee_advert;
3965
4ddc48a9
BA		 3966 ret_val =
3967 e1000_read_emi_reg_locked(hw,
3968 I217_EEE_ADVERTISEMENT,
3969 &eee_advert);
2fbe4526
BA		 3970 if (ret_val)
3971 goto release;
2fbe4526 3972
e921eb1a 3973 /* Disable LPLU if both link partners support 100BaseT
2fbe4526
BA		 3974 * EEE and 100Full is advertised on both ends of the
3975 * link.
3976 */
3d4d5755 3977 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
2fbe4526 3978 (dev_spec->eee_lp_ability &
3d4d5755 3979 I82579_EEE_100_SUPPORTED) &&
2fbe4526
BA		 3980 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
3981 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
3982 E1000_PHY_CTRL_NOND0A_LPLU);
3983 }
3984
e921eb1a 3985 /* For i217 Intel Rapid Start Technology support,
2fbe4526
BA		 3986 * when the system is going into Sx and no manageability engine
3987 * is present, the driver must configure proxy to reset only on
3988 * power good. LPI (Low Power Idle) state must also reset only
3989 * on power good, as well as the MTA (Multicast table array).
3990 * The SMBus release must also be disabled on LCD reset.
3991 */
3992 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2fbe4526
BA		 3993 /* Enable proxy to reset only on power good. */
3994 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
3995 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
3996 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
3997
e921eb1a 3998 /* Set bit enable LPI (EEE) to reset only on
2fbe4526
BA		 3999 * power good.
4000 */
4001 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
6d7407bf 4002 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
2fbe4526
BA		 4003 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4004
4005 /* Disable the SMB release on LCD reset. */
4006 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
6d7407bf 4007 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4008 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4009 }
4010
e921eb1a 4011 /* Enable MTA to reset for Intel Rapid Start Technology
2fbe4526
BA		 4012 * Support
4013 */
4014 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
6d7407bf 4015 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4016 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4017
4018release:
4019 hw->phy.ops.release(hw);
4020 }
4021out:
17f085df 4022 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 4023
462d5994
BA		 4024 if (hw->mac.type == e1000_ich8lan)
4025 e1000e_gig_downshift_workaround_ich8lan(hw);
4026
8395ae83 4027 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 4028 e1000_oem_bits_config_ich8lan(hw, false);
92fe1733
BA		 4029
4030 /* Reset PHY to activate OEM bits on 82577/8 */
4031 if (hw->mac.type == e1000_pchlan)
4032 e1000e_phy_hw_reset_generic(hw);
4033
8395ae83
BA		 4034 ret_val = hw->phy.ops.acquire(hw);
4035 if (ret_val)
4036 return;
4037 e1000_write_smbus_addr(hw);
4038 hw->phy.ops.release(hw);
4039 }
97ac8cae
BA		 4040}
4041
99730e4c
BA		 4042/**
4043 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4044 * @hw: pointer to the HW structure
4045 *
4046 * During Sx to S0 transitions on non-managed devices or managed devices
4047 * on which PHY resets are not blocked, if the PHY registers cannot be
4048 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4049 * the PHY.
2fbe4526 4050 * On i217, setup Intel Rapid Start Technology.
99730e4c
BA		 4051 **/
4052void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4053{
90b82984 4054 s32 ret_val;
99730e4c 4055
cb17aab9 4056 if (hw->mac.type < e1000_pch2lan)
99730e4c
BA		 4057 return;
4058
cb17aab9 4059 ret_val = e1000_init_phy_workarounds_pchlan(hw);
90b82984 4060 if (ret_val) {
cb17aab9 4061 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
90b82984
BA		 4062 return;
4063 }
2fbe4526 4064
e921eb1a 4065 /* For i217 Intel Rapid Start Technology support when the system
2fbe4526
BA		 4066 * is transitioning from Sx and no manageability engine is present
4067 * configure SMBus to restore on reset, disable proxy, and enable
4068 * the reset on MTA (Multicast table array).
4069 */
4070 if (hw->phy.type == e1000_phy_i217) {
4071 u16 phy_reg;
4072
4073 ret_val = hw->phy.ops.acquire(hw);
4074 if (ret_val) {
4075 e_dbg("Failed to setup iRST\n");
4076 return;
4077 }
4078
4079 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
e921eb1a 4080 /* Restore clear on SMB if no manageability engine
2fbe4526
BA		 4081 * is present
4082 */
4083 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4084 if (ret_val)
4085 goto release;
6d7407bf 4086 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
2fbe4526
BA		 4087 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4088
4089 /* Disable Proxy */
4090 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4091 }
4092 /* Enable reset on MTA */
4093 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4094 if (ret_val)
4095 goto release;
6d7407bf 4096 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
2fbe4526
BA		 4097 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4098release:
4099 if (ret_val)
4100 e_dbg("Error %d in resume workarounds\n", ret_val);
4101 hw->phy.ops.release(hw);
4102 }
99730e4c
BA		 4103}
4104
bc7f75fa
AK		 4105/**
4106 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4107 * @hw: pointer to the HW structure
4108 *
4109 * Return the LED back to the default configuration.
4110 **/
4111static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4112{
4113 if (hw->phy.type == e1000_phy_ife)
4114 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4115
4116 ew32(LEDCTL, hw->mac.ledctl_default);
4117 return 0;
4118}
4119
4120/**
489815ce 4121 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 4122 * @hw: pointer to the HW structure
4123 *
489815ce 4124 * Turn on the LEDs.
bc7f75fa
AK		 4125 **/
4126static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4127{
4128 if (hw->phy.type == e1000_phy_ife)
4129 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4130 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4131
4132 ew32(LEDCTL, hw->mac.ledctl_mode2);
4133 return 0;
4134}
4135
4136/**
489815ce 4137 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 4138 * @hw: pointer to the HW structure
4139 *
489815ce 4140 * Turn off the LEDs.
bc7f75fa
AK		 4141 **/
4142static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4143{
4144 if (hw->phy.type == e1000_phy_ife)
4145 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
482fed85
BA		 4146 (IFE_PSCL_PROBE_MODE |
4147 IFE_PSCL_PROBE_LEDS_OFF));
bc7f75fa
AK		 4148
4149 ew32(LEDCTL, hw->mac.ledctl_mode1);
4150 return 0;
4151}
4152
a4f58f54
BA		 4153/**
4154 * e1000_setup_led_pchlan - Configures SW controllable LED
4155 * @hw: pointer to the HW structure
4156 *
4157 * This prepares the SW controllable LED for use.
4158 **/
4159static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4160{
482fed85 4161 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
a4f58f54
BA		 4162}
4163
4164/**
4165 * e1000_cleanup_led_pchlan - Restore the default LED operation
4166 * @hw: pointer to the HW structure
4167 *
4168 * Return the LED back to the default configuration.
4169 **/
4170static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4171{
482fed85 4172 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
a4f58f54
BA		 4173}
4174
4175/**
4176 * e1000_led_on_pchlan - Turn LEDs on
4177 * @hw: pointer to the HW structure
4178 *
4179 * Turn on the LEDs.
4180 **/
4181static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4182{
4183 u16 data = (u16)hw->mac.ledctl_mode2;
4184 u32 i, led;
4185
e921eb1a 4186 /* If no link, then turn LED on by setting the invert bit
a4f58f54
BA		 4187 * for each LED that's mode is "link_up" in ledctl_mode2.
4188 */
4189 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4190 for (i = 0; i < 3; i++) {
4191 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4192 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4193 E1000_LEDCTL_MODE_LINK_UP)
4194 continue;
4195 if (led & E1000_PHY_LED0_IVRT)
4196 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4197 else
4198 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4199 }
4200 }
4201
482fed85 4202 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4203}
4204
4205/**
4206 * e1000_led_off_pchlan - Turn LEDs off
4207 * @hw: pointer to the HW structure
4208 *
4209 * Turn off the LEDs.
4210 **/
4211static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4212{
4213 u16 data = (u16)hw->mac.ledctl_mode1;
4214 u32 i, led;
4215
e921eb1a 4216 /* If no link, then turn LED off by clearing the invert bit
a4f58f54
BA		 4217 * for each LED that's mode is "link_up" in ledctl_mode1.
4218 */
4219 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4220 for (i = 0; i < 3; i++) {
4221 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4222 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4223 E1000_LEDCTL_MODE_LINK_UP)
4224 continue;
4225 if (led & E1000_PHY_LED0_IVRT)
4226 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4227 else
4228 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4229 }
4230 }
4231
482fed85 4232 return e1e_wphy(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 4233}
4234
f4187b56 4235/**
e98cac44 4236 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 4237 * @hw: pointer to the HW structure
4238 *
e98cac44
BA		 4239 * Read appropriate register for the config done bit for completion status
4240 * and configure the PHY through s/w for EEPROM-less parts.
4241 *
4242 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4243 * config done bit, so only an error is logged and continues. If we were
4244 * to return with error, EEPROM-less silicon would not be able to be reset
4245 * or change link.
f4187b56
BA		 4246 **/
4247static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4248{
e98cac44 4249 s32 ret_val = 0;
f4187b56 4250 u32 bank = 0;
e98cac44 4251 u32 status;
f4187b56 4252
fe90849f 4253 e1000e_get_cfg_done_generic(hw);
fc0c7760 4254
e98cac44
BA		 4255 /* Wait for indication from h/w that it has completed basic config */
4256 if (hw->mac.type >= e1000_ich10lan) {
4257 e1000_lan_init_done_ich8lan(hw);
4258 } else {
4259 ret_val = e1000e_get_auto_rd_done(hw);
4260 if (ret_val) {
e921eb1a 4261 /* When auto config read does not complete, do not
e98cac44
BA		 4262 * return with an error. This can happen in situations
4263 * where there is no eeprom and prevents getting link.
4264 */
4265 e_dbg("Auto Read Done did not complete\n");
4266 ret_val = 0;
4267 }
fc0c7760
BA		 4268 }
4269
e98cac44
BA		 4270 /* Clear PHY Reset Asserted bit */
4271 status = er32(STATUS);
4272 if (status & E1000_STATUS_PHYRA)
4273 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4274 else
4275 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 4276
4277 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 4278 if (hw->mac.type <= e1000_ich9lan) {
04499ec4 4279 if (!(er32(EECD) & E1000_EECD_PRES) &&
f4187b56
BA		 4280 (hw->phy.type == e1000_phy_igp_3)) {
4281 e1000e_phy_init_script_igp3(hw);
4282 }
4283 } else {
4284 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4285 /* Maybe we should do a basic PHY config */
3bb99fe2 4286 e_dbg("EEPROM not present\n");
e98cac44 4287 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 4288 }
4289 }
4290
e98cac44 4291 return ret_val;
f4187b56
BA		 4292}
4293
17f208de
BA		 4294/**
4295 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4296 * @hw: pointer to the HW structure
4297 *
4298 * In the case of a PHY power down to save power, or to turn off link during a
4299 * driver unload, or wake on lan is not enabled, remove the link.
4300 **/
4301static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4302{
4303 /* If the management interface is not enabled, then power down */
4304 if (!(hw->mac.ops.check_mng_mode(hw) ||
4305 hw->phy.ops.check_reset_block(hw)))
4306 e1000_power_down_phy_copper(hw);
17f208de
BA		 4307}
4308
bc7f75fa
AK		 4309/**
4310 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4311 * @hw: pointer to the HW structure
4312 *
4313 * Clears hardware counters specific to the silicon family and calls
4314 * clear_hw_cntrs_generic to clear all general purpose counters.
4315 **/
4316static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4317{
a4f58f54 4318 u16 phy_data;
2b6b168d 4319 s32 ret_val;
bc7f75fa
AK		 4320
4321 e1000e_clear_hw_cntrs_base(hw);
4322
99673d9b
BA		 4323 er32(ALGNERRC);
4324 er32(RXERRC);
4325 er32(TNCRS);
4326 er32(CEXTERR);
4327 er32(TSCTC);
4328 er32(TSCTFC);
bc7f75fa 4329
99673d9b
BA		 4330 er32(MGTPRC);
4331 er32(MGTPDC);
4332 er32(MGTPTC);
bc7f75fa 4333
99673d9b
BA		 4334 er32(IAC);
4335 er32(ICRXOC);
bc7f75fa 4336
a4f58f54
BA		 4337 /* Clear PHY statistics registers */
4338 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 4339 (hw->phy.type == e1000_phy_82579) ||
2fbe4526 4340 (hw->phy.type == e1000_phy_i217) ||
a4f58f54 4341 (hw->phy.type == e1000_phy_82577)) {
2b6b168d
BA		 4342 ret_val = hw->phy.ops.acquire(hw);
4343 if (ret_val)
4344 return;
4345 ret_val = hw->phy.ops.set_page(hw,
4346 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4347 if (ret_val)
4348 goto release;
4349 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4350 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4351 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4352 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4353 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4354 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4355 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4356 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4357 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4358 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4359 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4360 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4361 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4362 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4363release:
4364 hw->phy.ops.release(hw);
a4f58f54 4365 }
bc7f75fa
AK		 4366}
4367
8ce9d6c7 4368static const struct e1000_mac_operations ich8_mac_ops = {
eb7700dc 4369 /* check_mng_mode dependent on mac type */
7d3cabbc 4370 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 4371 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 4372 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4373 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 4374 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 4375 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 4376 /* led_on dependent on mac type */
4377 /* led_off dependent on mac type */
e2de3eb6 4378 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 4379 .reset_hw = e1000_reset_hw_ich8lan,
4380 .init_hw = e1000_init_hw_ich8lan,
4381 .setup_link = e1000_setup_link_ich8lan,
55c5f55e 4382 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
a4f58f54 4383 /* id_led_init dependent on mac type */
57cde763 4384 .config_collision_dist = e1000e_config_collision_dist_generic,
69e1e019 4385 .rar_set = e1000e_rar_set_generic,
bc7f75fa
AK		 4386};
4387
8ce9d6c7 4388static const struct e1000_phy_operations ich8_phy_ops = {
94d8186a 4389 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 4390 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 4391 .commit = NULL,
f4187b56 4392 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 4393 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 4394 .read_reg = e1000e_read_phy_reg_igp,
4395 .release = e1000_release_swflag_ich8lan,
4396 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 4397 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4398 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 4399 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 4400};
4401
8ce9d6c7 4402static const struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a 4403 .acquire = e1000_acquire_nvm_ich8lan,
55c5f55e 4404 .read = e1000_read_nvm_ich8lan,
94d8186a 4405 .release = e1000_release_nvm_ich8lan,
e85e3639 4406 .reload = e1000e_reload_nvm_generic,
94d8186a 4407 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 4408 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 4409 .validate = e1000_validate_nvm_checksum_ich8lan,
4410 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 4411};
4412
8ce9d6c7 4413const struct e1000_info e1000_ich8_info = {
bc7f75fa
AK		 4414 .mac = e1000_ich8lan,
4415 .flags = FLAG_HAS_WOL
97ac8cae 4416 | FLAG_IS_ICH
bc7f75fa
AK		 4417 | FLAG_HAS_CTRLEXT_ON_LOAD
4418 | FLAG_HAS_AMT
4419 | FLAG_HAS_FLASH
4420 | FLAG_APME_IN_WUC,
4421 .pba = 8,
2adc55c9 4422 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 4423 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4424 .mac_ops = &ich8_mac_ops,
4425 .phy_ops = &ich8_phy_ops,
4426 .nvm_ops = &ich8_nvm_ops,
4427};
4428
8ce9d6c7 4429const struct e1000_info e1000_ich9_info = {
bc7f75fa
AK		 4430 .mac = e1000_ich9lan,
4431 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 4432 | FLAG_IS_ICH
bc7f75fa 4433 | FLAG_HAS_WOL
bc7f75fa
AK		 4434 | FLAG_HAS_CTRLEXT_ON_LOAD
4435 | FLAG_HAS_AMT
bc7f75fa
AK		 4436 | FLAG_HAS_FLASH
4437 | FLAG_APME_IN_WUC,
7f1557e1 4438 .pba = 18,
2adc55c9 4439 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 4440 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 4441 .mac_ops = &ich8_mac_ops,
4442 .phy_ops = &ich8_phy_ops,
4443 .nvm_ops = &ich8_nvm_ops,
4444};
4445
8ce9d6c7 4446const struct e1000_info e1000_ich10_info = {
f4187b56
BA		 4447 .mac = e1000_ich10lan,
4448 .flags = FLAG_HAS_JUMBO_FRAMES
4449 | FLAG_IS_ICH
4450 | FLAG_HAS_WOL
f4187b56
BA		 4451 | FLAG_HAS_CTRLEXT_ON_LOAD
4452 | FLAG_HAS_AMT
f4187b56
BA		 4453 | FLAG_HAS_FLASH
4454 | FLAG_APME_IN_WUC,
7f1557e1 4455 .pba = 18,
2adc55c9 4456 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 4457 .get_variants = e1000_get_variants_ich8lan,
4458 .mac_ops = &ich8_mac_ops,
4459 .phy_ops = &ich8_phy_ops,
4460 .nvm_ops = &ich8_nvm_ops,
4461};
a4f58f54 4462
8ce9d6c7 4463const struct e1000_info e1000_pch_info = {
a4f58f54
BA		 4464 .mac = e1000_pchlan,
4465 .flags = FLAG_IS_ICH
4466 | FLAG_HAS_WOL
a4f58f54
BA		 4467 | FLAG_HAS_CTRLEXT_ON_LOAD
4468 | FLAG_HAS_AMT
4469 | FLAG_HAS_FLASH
4470 | FLAG_HAS_JUMBO_FRAMES
38eb394e 4471 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 4472 | FLAG_APME_IN_WUC,
8c7bbb92 4473 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 4474 .pba = 26,
4475 .max_hw_frame_size = 4096,
4476 .get_variants = e1000_get_variants_ich8lan,
4477 .mac_ops = &ich8_mac_ops,
4478 .phy_ops = &ich8_phy_ops,
4479 .nvm_ops = &ich8_nvm_ops,
4480};
d3738bb8 4481
8ce9d6c7 4482const struct e1000_info e1000_pch2_info = {
d3738bb8
BA		 4483 .mac = e1000_pch2lan,
4484 .flags = FLAG_IS_ICH
4485 | FLAG_HAS_WOL
b67e1913 4486 | FLAG_HAS_HW_TIMESTAMP
d3738bb8
BA		 4487 | FLAG_HAS_CTRLEXT_ON_LOAD
4488 | FLAG_HAS_AMT
4489 | FLAG_HAS_FLASH
4490 | FLAG_HAS_JUMBO_FRAMES
4491 | FLAG_APME_IN_WUC,
e52997f9
BA		 4492 .flags2 = FLAG2_HAS_PHY_STATS
4493 | FLAG2_HAS_EEE,
828bac87 4494 .pba = 26,
c3d2dbf4 4495 .max_hw_frame_size = 9018,
d3738bb8
BA		 4496 .get_variants = e1000_get_variants_ich8lan,
4497 .mac_ops = &ich8_mac_ops,
4498 .phy_ops = &ich8_phy_ops,
4499 .nvm_ops = &ich8_nvm_ops,
4500};
2fbe4526
BA		 4501
4502const struct e1000_info e1000_pch_lpt_info = {
4503 .mac = e1000_pch_lpt,
4504 .flags = FLAG_IS_ICH
4505 | FLAG_HAS_WOL
b67e1913 4506 | FLAG_HAS_HW_TIMESTAMP
2fbe4526
BA		 4507 | FLAG_HAS_CTRLEXT_ON_LOAD
4508 | FLAG_HAS_AMT
4509 | FLAG_HAS_FLASH
4510 | FLAG_HAS_JUMBO_FRAMES
4511 | FLAG_APME_IN_WUC,
4512 .flags2 = FLAG2_HAS_PHY_STATS
4513 | FLAG2_HAS_EEE,
4514 .pba = 26,
ed1a4265 4515 .max_hw_frame_size = 9018,
2fbe4526
BA		 4516 .get_variants = e1000_get_variants_ich8lan,
4517 .mac_ops = &ich8_mac_ops,
4518 .phy_ops = &ich8_phy_ops,
4519 .nvm_ops = &ich8_nvm_ops,
4520};
Linux kernel - Deliverables
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