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e1000e: Support RXFCS feature flag.
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
058e8edd 59#define DRV_VERSION "1.9.5" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
f36bb6ca 140 {0, NULL}
84f4ee90
TI		 141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29 185 struct my_u0 {
e885d762
BA		 186 __le64 a;
187 __le64 b;
af667a29 188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29 193 struct my_u1 {
e885d762
BA		 194 __le64 a;
195 __le64 b;
196 __le64 c;
197 __le64 d;
af667a29 198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90 223 if (!netdev || !netif_running(netdev))
fe1e980f 224 return;
84f4ee90 225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90 310 if (!netif_msg_rx_status(adapter))
fe1e980f 311 return;
84f4ee90 312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
84f4ee90
TI		 452}
453
bc7f75fa
AK		 454/**
455 * e1000_desc_unused - calculate if we have unused descriptors
456 **/
457static int e1000_desc_unused(struct e1000_ring *ring)
458{
459 if (ring->next_to_clean > ring->next_to_use)
460 return ring->next_to_clean - ring->next_to_use - 1;
461
462 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
463}
464
465/**
ad68076e 466 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 467 * @adapter: board private structure
468 * @status: descriptor status field as written by hardware
469 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
470 * @skb: pointer to sk_buff to be indicated to stack
471 **/
472static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 473 struct net_device *netdev, struct sk_buff *skb,
a39fe742 474 u8 status, __le16 vlan)
bc7f75fa 475{
86d70e53 476 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 477 skb->protocol = eth_type_trans(skb, netdev);
478
86d70e53
JK		 479 if (status & E1000_RXD_STAT_VP)
480 __vlan_hwaccel_put_tag(skb, tag);
481
482 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 483}
484
485/**
af667a29 486 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 487 * @adapter: board private structure
488 * @status_err: receive descriptor status and error fields
489 * @csum: receive descriptor csum field
490 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 491 **/
492static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 493 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 494{
495 u16 status = (u16)status_err;
496 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 497
498 skb_checksum_none_assert(skb);
bc7f75fa 499
afd12939
BA		 500 /* Rx checksum disabled */
501 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
502 return;
503
bc7f75fa
AK		 504 /* Ignore Checksum bit is set */
505 if (status & E1000_RXD_STAT_IXSM)
506 return;
afd12939 507
bc7f75fa
AK		 508 /* TCP/UDP checksum error bit is set */
509 if (errors & E1000_RXD_ERR_TCPE) {
510 /* let the stack verify checksum errors */
511 adapter->hw_csum_err++;
512 return;
513 }
514
515 /* TCP/UDP Checksum has not been calculated */
516 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
517 return;
518
519 /* It must be a TCP or UDP packet with a valid checksum */
520 if (status & E1000_RXD_STAT_TCPCS) {
521 /* TCP checksum is good */
522 skb->ip_summed = CHECKSUM_UNNECESSARY;
523 } else {
ad68076e
BA		 524 /*
525 * IP fragment with UDP payload
526 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 527 * and then put the value in host order for further stack use.
528 */
afd12939 529 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 530 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 531 skb->ip_summed = CHECKSUM_COMPLETE;
532 }
533 adapter->hw_csum_good++;
534}
535
c6e7f51e
BA		 536/**
537 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
538 * @hw: pointer to the HW structure
539 * @tail: address of tail descriptor register
540 * @i: value to write to tail descriptor register
541 *
542 * When updating the tail register, the ME could be accessing Host CSR
543 * registers at the same time. Normally, this is handled in h/w by an
544 * arbiter but on some parts there is a bug that acknowledges Host accesses
545 * later than it should which could result in the descriptor register to
546 * have an incorrect value. Workaround this by checking the FWSM register
547 * which has bit 24 set while ME is accessing Host CSR registers, wait
548 * if it is set and try again a number of times.
549 **/
c5083cf6 550static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 551 unsigned int i)
552{
553 unsigned int j = 0;
554
555 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
556 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
557 udelay(50);
558
559 writel(i, tail);
560
561 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
562 return E1000_ERR_SWFW_SYNC;
563
564 return 0;
565}
566
55aa6985 567static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 568{
55aa6985 569 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 570 struct e1000_hw *hw = &adapter->hw;
571
55aa6985 572 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 573 u32 rctl = er32(RCTL);
574 ew32(RCTL, rctl & ~E1000_RCTL_EN);
575 e_err("ME firmware caused invalid RDT - resetting\n");
576 schedule_work(&adapter->reset_task);
577 }
578}
579
55aa6985 580static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 581{
55aa6985 582 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 583 struct e1000_hw *hw = &adapter->hw;
584
55aa6985 585 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 586 u32 tctl = er32(TCTL);
587 ew32(TCTL, tctl & ~E1000_TCTL_EN);
588 e_err("ME firmware caused invalid TDT - resetting\n");
589 schedule_work(&adapter->reset_task);
590 }
591}
592
bc7f75fa 593/**
5f450212 594 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 595 * @rx_ring: Rx descriptor ring
bc7f75fa 596 **/
55aa6985 597static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 598 int cleaned_count, gfp_t gfp)
bc7f75fa 599{
55aa6985 600 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 601 struct net_device *netdev = adapter->netdev;
602 struct pci_dev *pdev = adapter->pdev;
5f450212 603 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 604 struct e1000_buffer *buffer_info;
605 struct sk_buff *skb;
606 unsigned int i;
89d71a66 607 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 608
609 i = rx_ring->next_to_use;
610 buffer_info = &rx_ring->buffer_info[i];
611
612 while (cleaned_count--) {
613 skb = buffer_info->skb;
614 if (skb) {
615 skb_trim(skb, 0);
616 goto map_skb;
617 }
618
c2fed996 619 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 620 if (!skb) {
621 /* Better luck next round */
622 adapter->alloc_rx_buff_failed++;
623 break;
624 }
625
bc7f75fa
AK		 626 buffer_info->skb = skb;
627map_skb:
0be3f55f 628 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 629 adapter->rx_buffer_len,
0be3f55f
NN		 630 DMA_FROM_DEVICE);
631 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 632 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 633 adapter->rx_dma_failed++;
634 break;
635 }
636
5f450212
BA		 637 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
638 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 639
50849d79
TH		 640 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
641 /*
642 * Force memory writes to complete before letting h/w
643 * know there are new descriptors to fetch. (Only
644 * applicable for weak-ordered memory model archs,
645 * such as IA-64).
646 */
647 wmb();
c6e7f51e 648 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 649 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 650 else
c5083cf6 651 writel(i, rx_ring->tail);
50849d79 652 }
bc7f75fa
AK		 653 i++;
654 if (i == rx_ring->count)
655 i = 0;
656 buffer_info = &rx_ring->buffer_info[i];
657 }
658
50849d79 659 rx_ring->next_to_use = i;
bc7f75fa
AK		 660}
661
662/**
663 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 664 * @rx_ring: Rx descriptor ring
bc7f75fa 665 **/
55aa6985 666static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 667 int cleaned_count, gfp_t gfp)
bc7f75fa 668{
55aa6985 669 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 670 struct net_device *netdev = adapter->netdev;
671 struct pci_dev *pdev = adapter->pdev;
672 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 673 struct e1000_buffer *buffer_info;
674 struct e1000_ps_page *ps_page;
675 struct sk_buff *skb;
676 unsigned int i, j;
677
678 i = rx_ring->next_to_use;
679 buffer_info = &rx_ring->buffer_info[i];
680
681 while (cleaned_count--) {
682 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683
684 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 685 ps_page = &buffer_info->ps_pages[j];
686 if (j >= adapter->rx_ps_pages) {
687 /* all unused desc entries get hw null ptr */
af667a29
BA		 688 rx_desc->read.buffer_addr[j + 1] =
689 ~cpu_to_le64(0);
47f44e40
AK		 690 continue;
691 }
692 if (!ps_page->page) {
c2fed996 693 ps_page->page = alloc_page(gfp);
bc7f75fa 694 if (!ps_page->page) {
47f44e40
AK		 695 adapter->alloc_rx_buff_failed++;
696 goto no_buffers;
697 }
0be3f55f
NN		 698 ps_page->dma = dma_map_page(&pdev->dev,
699 ps_page->page,
700 0, PAGE_SIZE,
701 DMA_FROM_DEVICE);
702 if (dma_mapping_error(&pdev->dev,
703 ps_page->dma)) {
47f44e40 704 dev_err(&adapter->pdev->dev,
af667a29 705 "Rx DMA page map failed\n");
47f44e40
AK		 706 adapter->rx_dma_failed++;
707 goto no_buffers;
bc7f75fa 708 }
bc7f75fa 709 }
47f44e40
AK		 710 /*
711 * Refresh the desc even if buffer_addrs
712 * didn't change because each write-back
713 * erases this info.
714 */
af667a29
BA		 715 rx_desc->read.buffer_addr[j + 1] =
716 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 717 }
718
c2fed996
JK		 719 skb = __netdev_alloc_skb_ip_align(netdev,
720 adapter->rx_ps_bsize0,
721 gfp);
bc7f75fa
AK		 722
723 if (!skb) {
724 adapter->alloc_rx_buff_failed++;
725 break;
726 }
727
bc7f75fa 728 buffer_info->skb = skb;
0be3f55f 729 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 730 adapter->rx_ps_bsize0,
0be3f55f
NN		 731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 733 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 734 adapter->rx_dma_failed++;
735 /* cleanup skb */
736 dev_kfree_skb_any(skb);
737 buffer_info->skb = NULL;
738 break;
739 }
740
741 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
742
50849d79
TH		 743 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
744 /*
745 * Force memory writes to complete before letting h/w
746 * know there are new descriptors to fetch. (Only
747 * applicable for weak-ordered memory model archs,
748 * such as IA-64).
749 */
750 wmb();
c6e7f51e 751 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 752 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 753 else
c5083cf6 754 writel(i << 1, rx_ring->tail);
50849d79
TH		 755 }
756
bc7f75fa
AK		 757 i++;
758 if (i == rx_ring->count)
759 i = 0;
760 buffer_info = &rx_ring->buffer_info[i];
761 }
762
763no_buffers:
50849d79 764 rx_ring->next_to_use = i;
bc7f75fa
AK		 765}
766
97ac8cae
BA		 767/**
768 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 769 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 770 * @cleaned_count: number of buffers to allocate this pass
771 **/
772
55aa6985 773static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 774 int cleaned_count, gfp_t gfp)
97ac8cae 775{
55aa6985 776 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 777 struct net_device *netdev = adapter->netdev;
778 struct pci_dev *pdev = adapter->pdev;
5f450212 779 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 780 struct e1000_buffer *buffer_info;
781 struct sk_buff *skb;
782 unsigned int i;
89d71a66 783 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 784
785 i = rx_ring->next_to_use;
786 buffer_info = &rx_ring->buffer_info[i];
787
788 while (cleaned_count--) {
789 skb = buffer_info->skb;
790 if (skb) {
791 skb_trim(skb, 0);
792 goto check_page;
793 }
794
c2fed996 795 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 796 if (unlikely(!skb)) {
797 /* Better luck next round */
798 adapter->alloc_rx_buff_failed++;
799 break;
800 }
801
97ac8cae
BA		 802 buffer_info->skb = skb;
803check_page:
804 /* allocate a new page if necessary */
805 if (!buffer_info->page) {
c2fed996 806 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 807 if (unlikely(!buffer_info->page)) {
808 adapter->alloc_rx_buff_failed++;
809 break;
810 }
811 }
812
813 if (!buffer_info->dma)
0be3f55f 814 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 815 buffer_info->page, 0,
816 PAGE_SIZE,
0be3f55f 817 DMA_FROM_DEVICE);
97ac8cae 818
5f450212
BA		 819 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
820 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 821
822 if (unlikely(++i == rx_ring->count))
823 i = 0;
824 buffer_info = &rx_ring->buffer_info[i];
825 }
826
827 if (likely(rx_ring->next_to_use != i)) {
828 rx_ring->next_to_use = i;
829 if (unlikely(i-- == 0))
830 i = (rx_ring->count - 1);
831
832 /* Force memory writes to complete before letting h/w
833 * know there are new descriptors to fetch. (Only
834 * applicable for weak-ordered memory model archs,
835 * such as IA-64). */
836 wmb();
c6e7f51e 837 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 838 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 839 else
c5083cf6 840 writel(i, rx_ring->tail);
97ac8cae
BA		 841 }
842}
843
70495a50
BA		 844static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
845 struct sk_buff *skb)
846{
847 if (netdev->features & NETIF_F_RXHASH)
848 skb->rxhash = le32_to_cpu(rss);
849}
850
bc7f75fa 851/**
55aa6985
BA		 852 * e1000_clean_rx_irq - Send received data up the network stack
853 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 854 *
855 * the return value indicates whether actual cleaning was done, there
856 * is no guarantee that everything was cleaned
857 **/
55aa6985
BA		 858static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
859 int work_to_do)
bc7f75fa 860{
55aa6985 861 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 862 struct net_device *netdev = adapter->netdev;
863 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 864 struct e1000_hw *hw = &adapter->hw;
5f450212 865 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 866 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 867 u32 length, staterr;
bc7f75fa
AK		 868 unsigned int i;
869 int cleaned_count = 0;
3db1cd5c 870 bool cleaned = false;
bc7f75fa
AK		 871 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
872
873 i = rx_ring->next_to_clean;
5f450212
BA		 874 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
875 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 876 buffer_info = &rx_ring->buffer_info[i];
877
5f450212 878 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 879 struct sk_buff *skb;
bc7f75fa
AK		 880
881 if (*work_done >= work_to_do)
882 break;
883 (*work_done)++;
2d0bb1c1 884 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 885
bc7f75fa
AK		 886 skb = buffer_info->skb;
887 buffer_info->skb = NULL;
888
889 prefetch(skb->data - NET_IP_ALIGN);
890
891 i++;
892 if (i == rx_ring->count)
893 i = 0;
5f450212 894 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 895 prefetch(next_rxd);
896
897 next_buffer = &rx_ring->buffer_info[i];
898
3db1cd5c 899 cleaned = true;
bc7f75fa 900 cleaned_count++;
0be3f55f 901 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 902 buffer_info->dma,
903 adapter->rx_buffer_len,
0be3f55f 904 DMA_FROM_DEVICE);
bc7f75fa
AK		 905 buffer_info->dma = 0;
906
5f450212 907 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 908
b94b5028
JB		 909 /*
910 * !EOP means multiple descriptors were used to store a single
911 * packet, if that's the case we need to toss it. In fact, we
912 * need to toss every packet with the EOP bit clear and the
913 * next frame that _does_ have the EOP bit set, as it is by
914 * definition only a frame fragment
915 */
5f450212 916 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 917 adapter->flags2 |= FLAG2_IS_DISCARDING;
918
919 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 920 /* All receives must fit into a single buffer */
3bb99fe2 921 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 922 /* recycle */
923 buffer_info->skb = skb;
5f450212 924 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 925 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 926 goto next_desc;
927 }
928
5f450212 929 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
bc7f75fa
AK		 930 /* recycle */
931 buffer_info->skb = skb;
932 goto next_desc;
933 }
934
eb7c3adb 935 /* adjust length to remove Ethernet CRC */
0184039a
BG		 936 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
937 /* If configured to store CRC, don't subtract FCS,
938 * but keep the FCS bytes out of the total_rx_bytes
939 * counter
940 */
941 if (netdev->features & NETIF_F_RXFCS)
942 total_rx_bytes -= 4;
943 else
944 length -= 4;
945 }
eb7c3adb 946
bc7f75fa
AK		 947 total_rx_bytes += length;
948 total_rx_packets++;
949
ad68076e
BA		 950 /*
951 * code added for copybreak, this should improve
bc7f75fa 952 * performance for small packets with large amounts
ad68076e
BA		 953 * of reassembly being done in the stack
954 */
bc7f75fa
AK		 955 if (length < copybreak) {
956 struct sk_buff *new_skb =
89d71a66 957 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 958 if (new_skb) {
808ff676
BA		 959 skb_copy_to_linear_data_offset(new_skb,
960 -NET_IP_ALIGN,
961 (skb->data -
962 NET_IP_ALIGN),
963 (length +
964 NET_IP_ALIGN));
bc7f75fa
AK		 965 /* save the skb in buffer_info as good */
966 buffer_info->skb = skb;
967 skb = new_skb;
968 }
969 /* else just continue with the old one */
970 }
971 /* end copybreak code */
972 skb_put(skb, length);
973
974 /* Receive Checksum Offload */
5f450212 975 e1000_rx_checksum(adapter, staterr,
afd12939 976 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 977
70495a50
BA		 978 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
979
5f450212
BA		 980 e1000_receive_skb(adapter, netdev, skb, staterr,
981 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 982
983next_desc:
5f450212 984 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 985
986 /* return some buffers to hardware, one at a time is too slow */
987 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 988 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 989 GFP_ATOMIC);
bc7f75fa
AK		 990 cleaned_count = 0;
991 }
992
993 /* use prefetched values */
994 rx_desc = next_rxd;
995 buffer_info = next_buffer;
5f450212
BA		 996
997 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 998 }
999 rx_ring->next_to_clean = i;
1000
1001 cleaned_count = e1000_desc_unused(rx_ring);
1002 if (cleaned_count)
55aa6985 1003 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1004
bc7f75fa 1005 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1006 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1007 return cleaned;
1008}
1009
55aa6985
BA		 1010static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1011 struct e1000_buffer *buffer_info)
bc7f75fa 1012{
55aa6985
BA		 1013 struct e1000_adapter *adapter = tx_ring->adapter;
1014
03b1320d
AD		 1015 if (buffer_info->dma) {
1016 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1017 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1018 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1019 else
0be3f55f
NN		 1020 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1021 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1022 buffer_info->dma = 0;
1023 }
bc7f75fa
AK		 1024 if (buffer_info->skb) {
1025 dev_kfree_skb_any(buffer_info->skb);
1026 buffer_info->skb = NULL;
1027 }
1b7719c4 1028 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1029}
1030
41cec6f1 1031static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1032{
41cec6f1
BA		 1033 struct e1000_adapter *adapter = container_of(work,
1034 struct e1000_adapter,
1035 print_hang_task);
09357b00 1036 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1037 struct e1000_ring *tx_ring = adapter->tx_ring;
1038 unsigned int i = tx_ring->next_to_clean;
1039 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1040 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1041 struct e1000_hw *hw = &adapter->hw;
1042 u16 phy_status, phy_1000t_status, phy_ext_status;
1043 u16 pci_status;
1044
615b32af
JB		 1045 if (test_bit(__E1000_DOWN, &adapter->state))
1046 return;
1047
09357b00
JK		 1048 if (!adapter->tx_hang_recheck &&
1049 (adapter->flags2 & FLAG2_DMA_BURST)) {
1050 /* May be block on write-back, flush and detect again
1051 * flush pending descriptor writebacks to memory
1052 */
1053 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1054 /* execute the writes immediately */
1055 e1e_flush();
1056 adapter->tx_hang_recheck = true;
1057 return;
1058 }
1059 /* Real hang detected */
1060 adapter->tx_hang_recheck = false;
1061 netif_stop_queue(netdev);
1062
41cec6f1
BA		 1063 e1e_rphy(hw, PHY_STATUS, &phy_status);
1064 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1065 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1066
41cec6f1
BA		 1067 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1068
1069 /* detected Hardware unit hang */
1070 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1071 " TDH <%x>\n"
1072 " TDT <%x>\n"
1073 " next_to_use <%x>\n"
1074 " next_to_clean <%x>\n"
1075 "buffer_info[next_to_clean]:\n"
1076 " time_stamp <%lx>\n"
1077 " next_to_watch <%x>\n"
1078 " jiffies <%lx>\n"
41cec6f1
BA		 1079 " next_to_watch.status <%x>\n"
1080 "MAC Status <%x>\n"
1081 "PHY Status <%x>\n"
1082 "PHY 1000BASE-T Status <%x>\n"
1083 "PHY Extended Status <%x>\n"
1084 "PCI Status <%x>\n",
c5083cf6
BA		 1085 readl(tx_ring->head),
1086 readl(tx_ring->tail),
44defeb3
JK		 1087 tx_ring->next_to_use,
1088 tx_ring->next_to_clean,
1089 tx_ring->buffer_info[eop].time_stamp,
1090 eop,
1091 jiffies,
41cec6f1
BA		 1092 eop_desc->upper.fields.status,
1093 er32(STATUS),
1094 phy_status,
1095 phy_1000t_status,
1096 phy_ext_status,
1097 pci_status);
bc7f75fa
AK		 1098}
1099
1100/**
1101 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1102 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1103 *
1104 * the return value indicates whether actual cleaning was done, there
1105 * is no guarantee that everything was cleaned
1106 **/
55aa6985 1107static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1108{
55aa6985 1109 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1110 struct net_device *netdev = adapter->netdev;
1111 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1112 struct e1000_tx_desc *tx_desc, *eop_desc;
1113 struct e1000_buffer *buffer_info;
1114 unsigned int i, eop;
1115 unsigned int count = 0;
bc7f75fa 1116 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1117 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1118
1119 i = tx_ring->next_to_clean;
1120 eop = tx_ring->buffer_info[i].next_to_watch;
1121 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1122
12d04a3c
AD		 1123 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1124 (count < tx_ring->count)) {
a86043c2 1125 bool cleaned = false;
2d0bb1c1 1126 rmb(); /* read buffer_info after eop_desc */
a86043c2 1127 for (; !cleaned; count++) {
bc7f75fa
AK		 1128 tx_desc = E1000_TX_DESC(*tx_ring, i);
1129 buffer_info = &tx_ring->buffer_info[i];
1130 cleaned = (i == eop);
1131
1132 if (cleaned) {
9ed318d5
TH		 1133 total_tx_packets += buffer_info->segs;
1134 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1135 if (buffer_info->skb) {
1136 bytes_compl += buffer_info->skb->len;
1137 pkts_compl++;
1138 }
bc7f75fa
AK		 1139 }
1140
55aa6985 1141 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1142 tx_desc->upper.data = 0;
1143
1144 i++;
1145 if (i == tx_ring->count)
1146 i = 0;
1147 }
1148
dac87619
TL		 1149 if (i == tx_ring->next_to_use)
1150 break;
bc7f75fa
AK		 1151 eop = tx_ring->buffer_info[i].next_to_watch;
1152 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1153 }
1154
1155 tx_ring->next_to_clean = i;
1156
3f0cfa3b
TH		 1157 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1158
bc7f75fa 1159#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1160 if (count && netif_carrier_ok(netdev) &&
1161 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1162 /* Make sure that anybody stopping the queue after this
1163 * sees the new next_to_clean.
1164 */
1165 smp_mb();
1166
1167 if (netif_queue_stopped(netdev) &&
1168 !(test_bit(__E1000_DOWN, &adapter->state))) {
1169 netif_wake_queue(netdev);
1170 ++adapter->restart_queue;
1171 }
1172 }
1173
1174 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1175 /*
1176 * Detect a transmit hang in hardware, this serializes the
1177 * check with the clearing of time_stamp and movement of i
1178 */
3db1cd5c 1179 adapter->detect_tx_hung = false;
12d04a3c
AD		 1180 if (tx_ring->buffer_info[i].time_stamp &&
1181 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1182 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1183 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1184 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1185 else
1186 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1187 }
1188 adapter->total_tx_bytes += total_tx_bytes;
1189 adapter->total_tx_packets += total_tx_packets;
807540ba 1190 return count < tx_ring->count;
bc7f75fa
AK		 1191}
1192
bc7f75fa
AK		 1193/**
1194 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1195 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1196 *
1197 * the return value indicates whether actual cleaning was done, there
1198 * is no guarantee that everything was cleaned
1199 **/
55aa6985
BA		 1200static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1201 int work_to_do)
bc7f75fa 1202{
55aa6985 1203 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1204 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1205 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1206 struct net_device *netdev = adapter->netdev;
1207 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1208 struct e1000_buffer *buffer_info, *next_buffer;
1209 struct e1000_ps_page *ps_page;
1210 struct sk_buff *skb;
1211 unsigned int i, j;
1212 u32 length, staterr;
1213 int cleaned_count = 0;
3db1cd5c 1214 bool cleaned = false;
bc7f75fa
AK		 1215 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1216
1217 i = rx_ring->next_to_clean;
1218 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1219 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1220 buffer_info = &rx_ring->buffer_info[i];
1221
1222 while (staterr & E1000_RXD_STAT_DD) {
1223 if (*work_done >= work_to_do)
1224 break;
1225 (*work_done)++;
1226 skb = buffer_info->skb;
2d0bb1c1 1227 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1228
1229 /* in the packet split case this is header only */
1230 prefetch(skb->data - NET_IP_ALIGN);
1231
1232 i++;
1233 if (i == rx_ring->count)
1234 i = 0;
1235 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1236 prefetch(next_rxd);
1237
1238 next_buffer = &rx_ring->buffer_info[i];
1239
3db1cd5c 1240 cleaned = true;
bc7f75fa 1241 cleaned_count++;
0be3f55f 1242 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1243 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1244 buffer_info->dma = 0;
1245
af667a29 1246 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1247 if (!(staterr & E1000_RXD_STAT_EOP))
1248 adapter->flags2 |= FLAG2_IS_DISCARDING;
1249
1250 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1251 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1252 dev_kfree_skb_irq(skb);
b94b5028
JB		 1253 if (staterr & E1000_RXD_STAT_EOP)
1254 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1255 goto next_desc;
1256 }
1257
1258 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
1259 dev_kfree_skb_irq(skb);
1260 goto next_desc;
1261 }
1262
1263 length = le16_to_cpu(rx_desc->wb.middle.length0);
1264
1265 if (!length) {
ef456f85 1266 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1267 dev_kfree_skb_irq(skb);
1268 goto next_desc;
1269 }
1270
1271 /* Good Receive */
1272 skb_put(skb, length);
1273
1274 {
0e15df49
BA		 1275 /*
1276 * this looks ugly, but it seems compiler issues make
1277 * it more efficient than reusing j
1278 */
1279 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1280
ad68076e 1281 /*
0e15df49
BA		 1282 * page alloc/put takes too long and effects small
1283 * packet throughput, so unsplit small packets and
1284 * save the alloc/put only valid in softirq (napi)
1285 * context to call kmap_*
ad68076e 1286 */
0e15df49
BA		 1287 if (l1 && (l1 <= copybreak) &&
1288 ((length + l1) <= adapter->rx_ps_bsize0)) {
1289 u8 *vaddr;
1290
1291 ps_page = &buffer_info->ps_pages[0];
1292
1293 /*
1294 * there is no documentation about how to call
1295 * kmap_atomic, so we can't hold the mapping
1296 * very long
1297 */
1298 dma_sync_single_for_cpu(&pdev->dev,
1299 ps_page->dma,
1300 PAGE_SIZE,
1301 DMA_FROM_DEVICE);
1302 vaddr = kmap_atomic(ps_page->page,
1303 KM_SKB_DATA_SOFTIRQ);
1304 memcpy(skb_tail_pointer(skb), vaddr, l1);
1305 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
1306 dma_sync_single_for_device(&pdev->dev,
1307 ps_page->dma,
1308 PAGE_SIZE,
1309 DMA_FROM_DEVICE);
1310
1311 /* remove the CRC */
0184039a
BG		 1312 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1313 if (!(netdev->features & NETIF_F_RXFCS))
1314 l1 -= 4;
1315 }
0e15df49
BA		 1316
1317 skb_put(skb, l1);
1318 goto copydone;
1319 } /* if */
bc7f75fa
AK		 1320 }
1321
1322 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1323 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1324 if (!length)
1325 break;
1326
47f44e40 1327 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1328 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1329 DMA_FROM_DEVICE);
bc7f75fa
AK		 1330 ps_page->dma = 0;
1331 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1332 ps_page->page = NULL;
1333 skb->len += length;
1334 skb->data_len += length;
98a045d7 1335 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1336 }
1337
eb7c3adb
JK		 1338 /* strip the ethernet crc, problem is we're using pages now so
1339 * this whole operation can get a little cpu intensive
1340 */
0184039a
BG		 1341 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1342 if (!(netdev->features & NETIF_F_RXFCS))
1343 pskb_trim(skb, skb->len - 4);
1344 }
eb7c3adb 1345
bc7f75fa
AK		 1346copydone:
1347 total_rx_bytes += skb->len;
1348 total_rx_packets++;
1349
afd12939
BA		 1350 e1000_rx_checksum(adapter, staterr,
1351 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1352
70495a50
BA		 1353 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1354
bc7f75fa
AK		 1355 if (rx_desc->wb.upper.header_status &
1356 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1357 adapter->rx_hdr_split++;
1358
1359 e1000_receive_skb(adapter, netdev, skb,
1360 staterr, rx_desc->wb.middle.vlan);
1361
1362next_desc:
1363 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1364 buffer_info->skb = NULL;
1365
1366 /* return some buffers to hardware, one at a time is too slow */
1367 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1368 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1369 GFP_ATOMIC);
bc7f75fa
AK		 1370 cleaned_count = 0;
1371 }
1372
1373 /* use prefetched values */
1374 rx_desc = next_rxd;
1375 buffer_info = next_buffer;
1376
1377 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1378 }
1379 rx_ring->next_to_clean = i;
1380
1381 cleaned_count = e1000_desc_unused(rx_ring);
1382 if (cleaned_count)
55aa6985 1383 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1384
bc7f75fa 1385 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1386 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1387 return cleaned;
1388}
1389
97ac8cae
BA		 1390/**
1391 * e1000_consume_page - helper function
1392 **/
1393static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1394 u16 length)
1395{
1396 bi->page = NULL;
1397 skb->len += length;
1398 skb->data_len += length;
98a045d7 1399 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1400}
1401
1402/**
1403 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1404 * @adapter: board private structure
1405 *
1406 * the return value indicates whether actual cleaning was done, there
1407 * is no guarantee that everything was cleaned
1408 **/
55aa6985
BA		 1409static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1410 int work_to_do)
97ac8cae 1411{
55aa6985 1412 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1413 struct net_device *netdev = adapter->netdev;
1414 struct pci_dev *pdev = adapter->pdev;
5f450212 1415 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1416 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1417 u32 length, staterr;
97ac8cae
BA		 1418 unsigned int i;
1419 int cleaned_count = 0;
1420 bool cleaned = false;
1421 unsigned int total_rx_bytes=0, total_rx_packets=0;
1422
1423 i = rx_ring->next_to_clean;
5f450212
BA		 1424 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1425 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1426 buffer_info = &rx_ring->buffer_info[i];
1427
5f450212 1428 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1429 struct sk_buff *skb;
97ac8cae
BA		 1430
1431 if (*work_done >= work_to_do)
1432 break;
1433 (*work_done)++;
2d0bb1c1 1434 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1435
97ac8cae
BA		 1436 skb = buffer_info->skb;
1437 buffer_info->skb = NULL;
1438
1439 ++i;
1440 if (i == rx_ring->count)
1441 i = 0;
5f450212 1442 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1443 prefetch(next_rxd);
1444
1445 next_buffer = &rx_ring->buffer_info[i];
1446
1447 cleaned = true;
1448 cleaned_count++;
0be3f55f
NN		 1449 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1450 DMA_FROM_DEVICE);
97ac8cae
BA		 1451 buffer_info->dma = 0;
1452
5f450212 1453 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1454
1455 /* errors is only valid for DD + EOP descriptors */
5f450212
BA		 1456 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1457 (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK))) {
1458 /* recycle both page and skb */
1459 buffer_info->skb = skb;
1460 /* an error means any chain goes out the window too */
1461 if (rx_ring->rx_skb_top)
1462 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1463 rx_ring->rx_skb_top = NULL;
1464 goto next_desc;
97ac8cae
BA		 1465 }
1466
f0f1a172 1467#define rxtop (rx_ring->rx_skb_top)
5f450212 1468 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1469 /* this descriptor is only the beginning (or middle) */
1470 if (!rxtop) {
1471 /* this is the beginning of a chain */
1472 rxtop = skb;
1473 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1474 0, length);
1475 } else {
1476 /* this is the middle of a chain */
1477 skb_fill_page_desc(rxtop,
1478 skb_shinfo(rxtop)->nr_frags,
1479 buffer_info->page, 0, length);
1480 /* re-use the skb, only consumed the page */
1481 buffer_info->skb = skb;
1482 }
1483 e1000_consume_page(buffer_info, rxtop, length);
1484 goto next_desc;
1485 } else {
1486 if (rxtop) {
1487 /* end of the chain */
1488 skb_fill_page_desc(rxtop,
1489 skb_shinfo(rxtop)->nr_frags,
1490 buffer_info->page, 0, length);
1491 /* re-use the current skb, we only consumed the
1492 * page */
1493 buffer_info->skb = skb;
1494 skb = rxtop;
1495 rxtop = NULL;
1496 e1000_consume_page(buffer_info, skb, length);
1497 } else {
1498 /* no chain, got EOP, this buf is the packet
1499 * copybreak to save the put_page/alloc_page */
1500 if (length <= copybreak &&
1501 skb_tailroom(skb) >= length) {
1502 u8 *vaddr;
1503 vaddr = kmap_atomic(buffer_info->page,
1504 KM_SKB_DATA_SOFTIRQ);
1505 memcpy(skb_tail_pointer(skb), vaddr,
1506 length);
1507 kunmap_atomic(vaddr,
1508 KM_SKB_DATA_SOFTIRQ);
1509 /* re-use the page, so don't erase
1510 * buffer_info->page */
1511 skb_put(skb, length);
1512 } else {
1513 skb_fill_page_desc(skb, 0,
1514 buffer_info->page, 0,
1515 length);
1516 e1000_consume_page(buffer_info, skb,
1517 length);
1518 }
1519 }
1520 }
1521
1522 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1523 e1000_rx_checksum(adapter, staterr,
afd12939 1524 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1525
70495a50
BA		 1526 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1527
97ac8cae
BA		 1528 /* probably a little skewed due to removing CRC */
1529 total_rx_bytes += skb->len;
1530 total_rx_packets++;
1531
1532 /* eth type trans needs skb->data to point to something */
1533 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1534 e_err("pskb_may_pull failed.\n");
ef5ab89c 1535 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1536 goto next_desc;
1537 }
1538
5f450212
BA		 1539 e1000_receive_skb(adapter, netdev, skb, staterr,
1540 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1541
1542next_desc:
5f450212 1543 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1544
1545 /* return some buffers to hardware, one at a time is too slow */
1546 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1547 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1548 GFP_ATOMIC);
97ac8cae
BA		 1549 cleaned_count = 0;
1550 }
1551
1552 /* use prefetched values */
1553 rx_desc = next_rxd;
1554 buffer_info = next_buffer;
5f450212
BA		 1555
1556 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1557 }
1558 rx_ring->next_to_clean = i;
1559
1560 cleaned_count = e1000_desc_unused(rx_ring);
1561 if (cleaned_count)
55aa6985 1562 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1563
1564 adapter->total_rx_bytes += total_rx_bytes;
1565 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1566 return cleaned;
1567}
1568
bc7f75fa
AK		 1569/**
1570 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1571 * @rx_ring: Rx descriptor ring
bc7f75fa 1572 **/
55aa6985 1573static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1574{
55aa6985 1575 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1576 struct e1000_buffer *buffer_info;
1577 struct e1000_ps_page *ps_page;
1578 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1579 unsigned int i, j;
1580
1581 /* Free all the Rx ring sk_buffs */
1582 for (i = 0; i < rx_ring->count; i++) {
1583 buffer_info = &rx_ring->buffer_info[i];
1584 if (buffer_info->dma) {
1585 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1586 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1587 adapter->rx_buffer_len,
0be3f55f 1588 DMA_FROM_DEVICE);
97ac8cae 1589 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1590 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1591 PAGE_SIZE,
0be3f55f 1592 DMA_FROM_DEVICE);
bc7f75fa 1593 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1594 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1595 adapter->rx_ps_bsize0,
0be3f55f 1596 DMA_FROM_DEVICE);
bc7f75fa
AK		 1597 buffer_info->dma = 0;
1598 }
1599
97ac8cae
BA		 1600 if (buffer_info->page) {
1601 put_page(buffer_info->page);
1602 buffer_info->page = NULL;
1603 }
1604
bc7f75fa
AK		 1605 if (buffer_info->skb) {
1606 dev_kfree_skb(buffer_info->skb);
1607 buffer_info->skb = NULL;
1608 }
1609
1610 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1611 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1612 if (!ps_page->page)
1613 break;
0be3f55f
NN		 1614 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1615 DMA_FROM_DEVICE);
bc7f75fa
AK		 1616 ps_page->dma = 0;
1617 put_page(ps_page->page);
1618 ps_page->page = NULL;
1619 }
1620 }
1621
1622 /* there also may be some cached data from a chained receive */
1623 if (rx_ring->rx_skb_top) {
1624 dev_kfree_skb(rx_ring->rx_skb_top);
1625 rx_ring->rx_skb_top = NULL;
1626 }
1627
bc7f75fa
AK		 1628 /* Zero out the descriptor ring */
1629 memset(rx_ring->desc, 0, rx_ring->size);
1630
1631 rx_ring->next_to_clean = 0;
1632 rx_ring->next_to_use = 0;
b94b5028 1633 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1634
c5083cf6
BA		 1635 writel(0, rx_ring->head);
1636 writel(0, rx_ring->tail);
bc7f75fa
AK		 1637}
1638
a8f88ff5
JB		 1639static void e1000e_downshift_workaround(struct work_struct *work)
1640{
1641 struct e1000_adapter *adapter = container_of(work,
1642 struct e1000_adapter, downshift_task);
1643
615b32af
JB		 1644 if (test_bit(__E1000_DOWN, &adapter->state))
1645 return;
1646
a8f88ff5
JB		 1647 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1648}
1649
bc7f75fa
AK		 1650/**
1651 * e1000_intr_msi - Interrupt Handler
1652 * @irq: interrupt number
1653 * @data: pointer to a network interface device structure
1654 **/
1655static irqreturn_t e1000_intr_msi(int irq, void *data)
1656{
1657 struct net_device *netdev = data;
1658 struct e1000_adapter *adapter = netdev_priv(netdev);
1659 struct e1000_hw *hw = &adapter->hw;
1660 u32 icr = er32(ICR);
1661
ad68076e
BA		 1662 /*
1663 * read ICR disables interrupts using IAM
1664 */
bc7f75fa 1665
573cca8c 1666 if (icr & E1000_ICR_LSC) {
f92518dd 1667 hw->mac.get_link_status = true;
ad68076e
BA		 1668 /*
1669 * ICH8 workaround-- Call gig speed drop workaround on cable
1670 * disconnect (LSC) before accessing any PHY registers
1671 */
bc7f75fa
AK		 1672 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1673 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1674 schedule_work(&adapter->downshift_task);
bc7f75fa 1675
ad68076e
BA		 1676 /*
1677 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1678 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1679 * adapter in watchdog
1680 */
bc7f75fa
AK		 1681 if (netif_carrier_ok(netdev) &&
1682 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1683 /* disable receives */
1684 u32 rctl = er32(RCTL);
1685 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1686 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1687 }
1688 /* guard against interrupt when we're going down */
1689 if (!test_bit(__E1000_DOWN, &adapter->state))
1690 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1691 }
1692
288379f0 1693 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1694 adapter->total_tx_bytes = 0;
1695 adapter->total_tx_packets = 0;
1696 adapter->total_rx_bytes = 0;
1697 adapter->total_rx_packets = 0;
288379f0 1698 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1699 }
1700
1701 return IRQ_HANDLED;
1702}
1703
1704/**
1705 * e1000_intr - Interrupt Handler
1706 * @irq: interrupt number
1707 * @data: pointer to a network interface device structure
1708 **/
1709static irqreturn_t e1000_intr(int irq, void *data)
1710{
1711 struct net_device *netdev = data;
1712 struct e1000_adapter *adapter = netdev_priv(netdev);
1713 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1714 u32 rctl, icr = er32(ICR);
4662e82b 1715
a68ea775 1716 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1717 return IRQ_NONE; /* Not our interrupt */
1718
ad68076e
BA		 1719 /*
1720 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1721 * not set, then the adapter didn't send an interrupt
1722 */
bc7f75fa
AK		 1723 if (!(icr & E1000_ICR_INT_ASSERTED))
1724 return IRQ_NONE;
1725
ad68076e
BA		 1726 /*
1727 * Interrupt Auto-Mask...upon reading ICR,
1728 * interrupts are masked. No need for the
1729 * IMC write
1730 */
bc7f75fa 1731
573cca8c 1732 if (icr & E1000_ICR_LSC) {
f92518dd 1733 hw->mac.get_link_status = true;
ad68076e
BA		 1734 /*
1735 * ICH8 workaround-- Call gig speed drop workaround on cable
1736 * disconnect (LSC) before accessing any PHY registers
1737 */
bc7f75fa
AK		 1738 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1739 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1740 schedule_work(&adapter->downshift_task);
bc7f75fa 1741
ad68076e
BA		 1742 /*
1743 * 80003ES2LAN workaround--
bc7f75fa
AK		 1744 * For packet buffer work-around on link down event;
1745 * disable receives here in the ISR and
1746 * reset adapter in watchdog
1747 */
1748 if (netif_carrier_ok(netdev) &&
1749 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1750 /* disable receives */
1751 rctl = er32(RCTL);
1752 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1753 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1754 }
1755 /* guard against interrupt when we're going down */
1756 if (!test_bit(__E1000_DOWN, &adapter->state))
1757 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1758 }
1759
288379f0 1760 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1761 adapter->total_tx_bytes = 0;
1762 adapter->total_tx_packets = 0;
1763 adapter->total_rx_bytes = 0;
1764 adapter->total_rx_packets = 0;
288379f0 1765 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1766 }
1767
1768 return IRQ_HANDLED;
1769}
1770
4662e82b
BA		 1771static irqreturn_t e1000_msix_other(int irq, void *data)
1772{
1773 struct net_device *netdev = data;
1774 struct e1000_adapter *adapter = netdev_priv(netdev);
1775 struct e1000_hw *hw = &adapter->hw;
1776 u32 icr = er32(ICR);
1777
1778 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1779 if (!test_bit(__E1000_DOWN, &adapter->state))
1780 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1781 return IRQ_NONE;
1782 }
1783
1784 if (icr & adapter->eiac_mask)
1785 ew32(ICS, (icr & adapter->eiac_mask));
1786
1787 if (icr & E1000_ICR_OTHER) {
1788 if (!(icr & E1000_ICR_LSC))
1789 goto no_link_interrupt;
f92518dd 1790 hw->mac.get_link_status = true;
4662e82b
BA		 1791 /* guard against interrupt when we're going down */
1792 if (!test_bit(__E1000_DOWN, &adapter->state))
1793 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1794 }
1795
1796no_link_interrupt:
a3c69fef
JB		 1797 if (!test_bit(__E1000_DOWN, &adapter->state))
1798 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1799
1800 return IRQ_HANDLED;
1801}
1802
1803
1804static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1805{
1806 struct net_device *netdev = data;
1807 struct e1000_adapter *adapter = netdev_priv(netdev);
1808 struct e1000_hw *hw = &adapter->hw;
1809 struct e1000_ring *tx_ring = adapter->tx_ring;
1810
1811
1812 adapter->total_tx_bytes = 0;
1813 adapter->total_tx_packets = 0;
1814
55aa6985 1815 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1816 /* Ring was not completely cleaned, so fire another interrupt */
1817 ew32(ICS, tx_ring->ims_val);
1818
1819 return IRQ_HANDLED;
1820}
1821
1822static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1823{
1824 struct net_device *netdev = data;
1825 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1826 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1827
1828 /* Write the ITR value calculated at the end of the
1829 * previous interrupt.
1830 */
55aa6985
BA		 1831 if (rx_ring->set_itr) {
1832 writel(1000000000 / (rx_ring->itr_val * 256),
1833 rx_ring->itr_register);
1834 rx_ring->set_itr = 0;
4662e82b
BA		 1835 }
1836
288379f0 1837 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1838 adapter->total_rx_bytes = 0;
1839 adapter->total_rx_packets = 0;
288379f0 1840 __napi_schedule(&adapter->napi);
4662e82b
BA		 1841 }
1842 return IRQ_HANDLED;
1843}
1844
1845/**
1846 * e1000_configure_msix - Configure MSI-X hardware
1847 *
1848 * e1000_configure_msix sets up the hardware to properly
1849 * generate MSI-X interrupts.
1850 **/
1851static void e1000_configure_msix(struct e1000_adapter *adapter)
1852{
1853 struct e1000_hw *hw = &adapter->hw;
1854 struct e1000_ring *rx_ring = adapter->rx_ring;
1855 struct e1000_ring *tx_ring = adapter->tx_ring;
1856 int vector = 0;
1857 u32 ctrl_ext, ivar = 0;
1858
1859 adapter->eiac_mask = 0;
1860
1861 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1862 if (hw->mac.type == e1000_82574) {
1863 u32 rfctl = er32(RFCTL);
1864 rfctl |= E1000_RFCTL_ACK_DIS;
1865 ew32(RFCTL, rfctl);
1866 }
1867
1868#define E1000_IVAR_INT_ALLOC_VALID 0x8
1869 /* Configure Rx vector */
1870 rx_ring->ims_val = E1000_IMS_RXQ0;
1871 adapter->eiac_mask |= rx_ring->ims_val;
1872 if (rx_ring->itr_val)
1873 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1874 rx_ring->itr_register);
4662e82b 1875 else
c5083cf6 1876 writel(1, rx_ring->itr_register);
4662e82b
BA		 1877 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1878
1879 /* Configure Tx vector */
1880 tx_ring->ims_val = E1000_IMS_TXQ0;
1881 vector++;
1882 if (tx_ring->itr_val)
1883 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1884 tx_ring->itr_register);
4662e82b 1885 else
c5083cf6 1886 writel(1, tx_ring->itr_register);
4662e82b
BA		 1887 adapter->eiac_mask |= tx_ring->ims_val;
1888 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1889
1890 /* set vector for Other Causes, e.g. link changes */
1891 vector++;
1892 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1893 if (rx_ring->itr_val)
1894 writel(1000000000 / (rx_ring->itr_val * 256),
1895 hw->hw_addr + E1000_EITR_82574(vector));
1896 else
1897 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1898
1899 /* Cause Tx interrupts on every write back */
1900 ivar |= (1 << 31);
1901
1902 ew32(IVAR, ivar);
1903
1904 /* enable MSI-X PBA support */
1905 ctrl_ext = er32(CTRL_EXT);
1906 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1907
1908 /* Auto-Mask Other interrupts upon ICR read */
1909#define E1000_EIAC_MASK_82574 0x01F00000
1910 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1911 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1912 ew32(CTRL_EXT, ctrl_ext);
1913 e1e_flush();
1914}
1915
1916void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1917{
1918 if (adapter->msix_entries) {
1919 pci_disable_msix(adapter->pdev);
1920 kfree(adapter->msix_entries);
1921 adapter->msix_entries = NULL;
1922 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1923 pci_disable_msi(adapter->pdev);
1924 adapter->flags &= ~FLAG_MSI_ENABLED;
1925 }
4662e82b
BA		 1926}
1927
1928/**
1929 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1930 *
1931 * Attempt to configure interrupts using the best available
1932 * capabilities of the hardware and kernel.
1933 **/
1934void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1935{
1936 int err;
8e86acd7 1937 int i;
4662e82b
BA		 1938
1939 switch (adapter->int_mode) {
1940 case E1000E_INT_MODE_MSIX:
1941 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1942 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1943 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1944 sizeof(struct msix_entry),
1945 GFP_KERNEL);
1946 if (adapter->msix_entries) {
8e86acd7 1947 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1948 adapter->msix_entries[i].entry = i;
1949
1950 err = pci_enable_msix(adapter->pdev,
1951 adapter->msix_entries,
8e86acd7 1952 adapter->num_vectors);
b1cdfead 1953 if (err == 0)
4662e82b
BA		 1954 return;
1955 }
1956 /* MSI-X failed, so fall through and try MSI */
ef456f85 1957 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1958 e1000e_reset_interrupt_capability(adapter);
1959 }
1960 adapter->int_mode = E1000E_INT_MODE_MSI;
1961 /* Fall through */
1962 case E1000E_INT_MODE_MSI:
1963 if (!pci_enable_msi(adapter->pdev)) {
1964 adapter->flags |= FLAG_MSI_ENABLED;
1965 } else {
1966 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1967 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1968 }
1969 /* Fall through */
1970 case E1000E_INT_MODE_LEGACY:
1971 /* Don't do anything; this is the system default */
1972 break;
1973 }
8e86acd7
JK		 1974
1975 /* store the number of vectors being used */
1976 adapter->num_vectors = 1;
4662e82b
BA		 1977}
1978
1979/**
1980 * e1000_request_msix - Initialize MSI-X interrupts
1981 *
1982 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1983 * kernel.
1984 **/
1985static int e1000_request_msix(struct e1000_adapter *adapter)
1986{
1987 struct net_device *netdev = adapter->netdev;
1988 int err = 0, vector = 0;
1989
1990 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1991 snprintf(adapter->rx_ring->name,
1992 sizeof(adapter->rx_ring->name) - 1,
1993 "%s-rx-0", netdev->name);
4662e82b
BA		 1994 else
1995 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1996 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1997 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1998 netdev);
1999 if (err)
5015e53a 2000 return err;
c5083cf6
BA		 2001 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2002 E1000_EITR_82574(vector);
4662e82b
BA		 2003 adapter->rx_ring->itr_val = adapter->itr;
2004 vector++;
2005
2006 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2007 snprintf(adapter->tx_ring->name,
2008 sizeof(adapter->tx_ring->name) - 1,
2009 "%s-tx-0", netdev->name);
4662e82b
BA		 2010 else
2011 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2012 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2013 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2014 netdev);
2015 if (err)
5015e53a 2016 return err;
c5083cf6
BA		 2017 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2018 E1000_EITR_82574(vector);
4662e82b
BA		 2019 adapter->tx_ring->itr_val = adapter->itr;
2020 vector++;
2021
2022 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2023 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2024 if (err)
5015e53a 2025 return err;
4662e82b
BA		 2026
2027 e1000_configure_msix(adapter);
5015e53a 2028
4662e82b 2029 return 0;
4662e82b
BA		 2030}
2031
f8d59f78
BA		 2032/**
2033 * e1000_request_irq - initialize interrupts
2034 *
2035 * Attempts to configure interrupts using the best available
2036 * capabilities of the hardware and kernel.
2037 **/
bc7f75fa
AK		 2038static int e1000_request_irq(struct e1000_adapter *adapter)
2039{
2040 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2041 int err;
2042
4662e82b
BA		 2043 if (adapter->msix_entries) {
2044 err = e1000_request_msix(adapter);
2045 if (!err)
2046 return err;
2047 /* fall back to MSI */
2048 e1000e_reset_interrupt_capability(adapter);
2049 adapter->int_mode = E1000E_INT_MODE_MSI;
2050 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2051 }
4662e82b 2052 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2053 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2054 netdev->name, netdev);
2055 if (!err)
2056 return err;
bc7f75fa 2057
4662e82b
BA		 2058 /* fall back to legacy interrupt */
2059 e1000e_reset_interrupt_capability(adapter);
2060 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2061 }
2062
a0607fd3 2063 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2064 netdev->name, netdev);
2065 if (err)
2066 e_err("Unable to allocate interrupt, Error: %d\n", err);
2067
bc7f75fa
AK		 2068 return err;
2069}
2070
2071static void e1000_free_irq(struct e1000_adapter *adapter)
2072{
2073 struct net_device *netdev = adapter->netdev;
2074
4662e82b
BA		 2075 if (adapter->msix_entries) {
2076 int vector = 0;
2077
2078 free_irq(adapter->msix_entries[vector].vector, netdev);
2079 vector++;
2080
2081 free_irq(adapter->msix_entries[vector].vector, netdev);
2082 vector++;
2083
2084 /* Other Causes interrupt vector */
2085 free_irq(adapter->msix_entries[vector].vector, netdev);
2086 return;
bc7f75fa 2087 }
4662e82b
BA		 2088
2089 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2090}
2091
2092/**
2093 * e1000_irq_disable - Mask off interrupt generation on the NIC
2094 **/
2095static void e1000_irq_disable(struct e1000_adapter *adapter)
2096{
2097 struct e1000_hw *hw = &adapter->hw;
2098
bc7f75fa 2099 ew32(IMC, ~0);
4662e82b
BA		 2100 if (adapter->msix_entries)
2101 ew32(EIAC_82574, 0);
bc7f75fa 2102 e1e_flush();
8e86acd7
JK		 2103
2104 if (adapter->msix_entries) {
2105 int i;
2106 for (i = 0; i < adapter->num_vectors; i++)
2107 synchronize_irq(adapter->msix_entries[i].vector);
2108 } else {
2109 synchronize_irq(adapter->pdev->irq);
2110 }
bc7f75fa
AK		 2111}
2112
2113/**
2114 * e1000_irq_enable - Enable default interrupt generation settings
2115 **/
2116static void e1000_irq_enable(struct e1000_adapter *adapter)
2117{
2118 struct e1000_hw *hw = &adapter->hw;
2119
4662e82b
BA		 2120 if (adapter->msix_entries) {
2121 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2122 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2123 } else {
2124 ew32(IMS, IMS_ENABLE_MASK);
2125 }
74ef9c39 2126 e1e_flush();
bc7f75fa
AK		 2127}
2128
2129/**
31dbe5b4 2130 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2131 * @adapter: address of board private structure
2132 *
31dbe5b4 2133 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2134 * For ASF and Pass Through versions of f/w this means that
2135 * the driver is loaded. For AMT version (only with 82573)
2136 * of the f/w this means that the network i/f is open.
2137 **/
31dbe5b4 2138void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2139{
2140 struct e1000_hw *hw = &adapter->hw;
2141 u32 ctrl_ext;
2142 u32 swsm;
2143
2144 /* Let firmware know the driver has taken over */
2145 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2146 swsm = er32(SWSM);
2147 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2148 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2149 ctrl_ext = er32(CTRL_EXT);
ad68076e 2150 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2151 }
2152}
2153
2154/**
31dbe5b4 2155 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2156 * @adapter: address of board private structure
2157 *
31dbe5b4 2158 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2159 * For ASF and Pass Through versions of f/w this means that the
2160 * driver is no longer loaded. For AMT version (only with 82573) i
2161 * of the f/w this means that the network i/f is closed.
2162 *
2163 **/
31dbe5b4 2164void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2165{
2166 struct e1000_hw *hw = &adapter->hw;
2167 u32 ctrl_ext;
2168 u32 swsm;
2169
2170 /* Let firmware taken over control of h/w */
2171 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2172 swsm = er32(SWSM);
2173 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2174 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2175 ctrl_ext = er32(CTRL_EXT);
ad68076e 2176 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2177 }
2178}
2179
bc7f75fa
AK		 2180/**
2181 * @e1000_alloc_ring - allocate memory for a ring structure
2182 **/
2183static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2184 struct e1000_ring *ring)
2185{
2186 struct pci_dev *pdev = adapter->pdev;
2187
2188 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2189 GFP_KERNEL);
2190 if (!ring->desc)
2191 return -ENOMEM;
2192
2193 return 0;
2194}
2195
2196/**
2197 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2198 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2199 *
2200 * Return 0 on success, negative on failure
2201 **/
55aa6985 2202int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2203{
55aa6985 2204 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2205 int err = -ENOMEM, size;
2206
2207 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2208 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2209 if (!tx_ring->buffer_info)
2210 goto err;
bc7f75fa
AK		 2211
2212 /* round up to nearest 4K */
2213 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2214 tx_ring->size = ALIGN(tx_ring->size, 4096);
2215
2216 err = e1000_alloc_ring_dma(adapter, tx_ring);
2217 if (err)
2218 goto err;
2219
2220 tx_ring->next_to_use = 0;
2221 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2222
2223 return 0;
2224err:
2225 vfree(tx_ring->buffer_info);
44defeb3 2226 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2227 return err;
2228}
2229
2230/**
2231 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2232 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2233 *
2234 * Returns 0 on success, negative on failure
2235 **/
55aa6985 2236int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2237{
55aa6985 2238 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2239 struct e1000_buffer *buffer_info;
2240 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2241
2242 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2243 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2244 if (!rx_ring->buffer_info)
2245 goto err;
bc7f75fa 2246
47f44e40
AK		 2247 for (i = 0; i < rx_ring->count; i++) {
2248 buffer_info = &rx_ring->buffer_info[i];
2249 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2250 sizeof(struct e1000_ps_page),
2251 GFP_KERNEL);
2252 if (!buffer_info->ps_pages)
2253 goto err_pages;
2254 }
bc7f75fa
AK		 2255
2256 desc_len = sizeof(union e1000_rx_desc_packet_split);
2257
2258 /* Round up to nearest 4K */
2259 rx_ring->size = rx_ring->count * desc_len;
2260 rx_ring->size = ALIGN(rx_ring->size, 4096);
2261
2262 err = e1000_alloc_ring_dma(adapter, rx_ring);
2263 if (err)
47f44e40 2264 goto err_pages;
bc7f75fa
AK		 2265
2266 rx_ring->next_to_clean = 0;
2267 rx_ring->next_to_use = 0;
2268 rx_ring->rx_skb_top = NULL;
2269
2270 return 0;
47f44e40
AK		 2271
2272err_pages:
2273 for (i = 0; i < rx_ring->count; i++) {
2274 buffer_info = &rx_ring->buffer_info[i];
2275 kfree(buffer_info->ps_pages);
2276 }
bc7f75fa
AK		 2277err:
2278 vfree(rx_ring->buffer_info);
e9262447 2279 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2280 return err;
2281}
2282
2283/**
2284 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2285 * @tx_ring: Tx descriptor ring
bc7f75fa 2286 **/
55aa6985 2287static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2288{
55aa6985 2289 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2290 struct e1000_buffer *buffer_info;
2291 unsigned long size;
2292 unsigned int i;
2293
2294 for (i = 0; i < tx_ring->count; i++) {
2295 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2296 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2297 }
2298
3f0cfa3b 2299 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2300 size = sizeof(struct e1000_buffer) * tx_ring->count;
2301 memset(tx_ring->buffer_info, 0, size);
2302
2303 memset(tx_ring->desc, 0, tx_ring->size);
2304
2305 tx_ring->next_to_use = 0;
2306 tx_ring->next_to_clean = 0;
2307
c5083cf6
BA		 2308 writel(0, tx_ring->head);
2309 writel(0, tx_ring->tail);
bc7f75fa
AK		 2310}
2311
2312/**
2313 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2314 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2315 *
2316 * Free all transmit software resources
2317 **/
55aa6985 2318void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2319{
55aa6985 2320 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2321 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2322
55aa6985 2323 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2324
2325 vfree(tx_ring->buffer_info);
2326 tx_ring->buffer_info = NULL;
2327
2328 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2329 tx_ring->dma);
2330 tx_ring->desc = NULL;
2331}
2332
2333/**
2334 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2335 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2336 *
2337 * Free all receive software resources
2338 **/
55aa6985 2339void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2340{
55aa6985 2341 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2342 struct pci_dev *pdev = adapter->pdev;
47f44e40 2343 int i;
bc7f75fa 2344
55aa6985 2345 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2346
b1cdfead 2347 for (i = 0; i < rx_ring->count; i++)
47f44e40 2348 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2349
bc7f75fa
AK		 2350 vfree(rx_ring->buffer_info);
2351 rx_ring->buffer_info = NULL;
2352
bc7f75fa
AK		 2353 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2354 rx_ring->dma);
2355 rx_ring->desc = NULL;
2356}
2357
2358/**
2359 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2360 * @adapter: pointer to adapter
2361 * @itr_setting: current adapter->itr
2362 * @packets: the number of packets during this measurement interval
2363 * @bytes: the number of bytes during this measurement interval
2364 *
bc7f75fa
AK		 2365 * Stores a new ITR value based on packets and byte
2366 * counts during the last interrupt. The advantage of per interrupt
2367 * computation is faster updates and more accurate ITR for the current
2368 * traffic pattern. Constants in this function were computed
2369 * based on theoretical maximum wire speed and thresholds were set based
2370 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2371 * while increasing bulk throughput. This functionality is controlled
2372 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2373 **/
2374static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2375 u16 itr_setting, int packets,
2376 int bytes)
2377{
2378 unsigned int retval = itr_setting;
2379
2380 if (packets == 0)
5015e53a 2381 return itr_setting;
bc7f75fa
AK		 2382
2383 switch (itr_setting) {
2384 case lowest_latency:
2385 /* handle TSO and jumbo frames */
2386 if (bytes/packets > 8000)
2387 retval = bulk_latency;
b1cdfead 2388 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2389 retval = low_latency;
bc7f75fa
AK		 2390 break;
2391 case low_latency: /* 50 usec aka 20000 ints/s */
2392 if (bytes > 10000) {
2393 /* this if handles the TSO accounting */
b1cdfead 2394 if (bytes/packets > 8000)
bc7f75fa 2395 retval = bulk_latency;
b1cdfead 2396 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2397 retval = bulk_latency;
b1cdfead 2398 else if ((packets > 35))
bc7f75fa 2399 retval = lowest_latency;
bc7f75fa
AK		 2400 } else if (bytes/packets > 2000) {
2401 retval = bulk_latency;
2402 } else if (packets <= 2 && bytes < 512) {
2403 retval = lowest_latency;
2404 }
2405 break;
2406 case bulk_latency: /* 250 usec aka 4000 ints/s */
2407 if (bytes > 25000) {
b1cdfead 2408 if (packets > 35)
bc7f75fa 2409 retval = low_latency;
bc7f75fa
AK		 2410 } else if (bytes < 6000) {
2411 retval = low_latency;
2412 }
2413 break;
2414 }
2415
bc7f75fa
AK		 2416 return retval;
2417}
2418
2419static void e1000_set_itr(struct e1000_adapter *adapter)
2420{
2421 struct e1000_hw *hw = &adapter->hw;
2422 u16 current_itr;
2423 u32 new_itr = adapter->itr;
2424
2425 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2426 if (adapter->link_speed != SPEED_1000) {
2427 current_itr = 0;
2428 new_itr = 4000;
2429 goto set_itr_now;
2430 }
2431
828bac87
BA		 2432 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2433 new_itr = 0;
2434 goto set_itr_now;
2435 }
2436
bc7f75fa
AK		 2437 adapter->tx_itr = e1000_update_itr(adapter,
2438 adapter->tx_itr,
2439 adapter->total_tx_packets,
2440 adapter->total_tx_bytes);
2441 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2442 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2443 adapter->tx_itr = low_latency;
2444
2445 adapter->rx_itr = e1000_update_itr(adapter,
2446 adapter->rx_itr,
2447 adapter->total_rx_packets,
2448 adapter->total_rx_bytes);
2449 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2450 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2451 adapter->rx_itr = low_latency;
2452
2453 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2454
2455 switch (current_itr) {
2456 /* counts and packets in update_itr are dependent on these numbers */
2457 case lowest_latency:
2458 new_itr = 70000;
2459 break;
2460 case low_latency:
2461 new_itr = 20000; /* aka hwitr = ~200 */
2462 break;
2463 case bulk_latency:
2464 new_itr = 4000;
2465 break;
2466 default:
2467 break;
2468 }
2469
2470set_itr_now:
2471 if (new_itr != adapter->itr) {
ad68076e
BA		 2472 /*
2473 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2474 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2475 * increasing
2476 */
bc7f75fa
AK		 2477 new_itr = new_itr > adapter->itr ?
2478 min(adapter->itr + (new_itr >> 2), new_itr) :
2479 new_itr;
2480 adapter->itr = new_itr;
4662e82b
BA		 2481 adapter->rx_ring->itr_val = new_itr;
2482 if (adapter->msix_entries)
2483 adapter->rx_ring->set_itr = 1;
2484 else
828bac87
BA		 2485 if (new_itr)
2486 ew32(ITR, 1000000000 / (new_itr * 256));
2487 else
2488 ew32(ITR, 0);
bc7f75fa
AK		 2489 }
2490}
2491
4662e82b
BA		 2492/**
2493 * e1000_alloc_queues - Allocate memory for all rings
2494 * @adapter: board private structure to initialize
2495 **/
2496static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2497{
55aa6985
BA		 2498 int size = sizeof(struct e1000_ring);
2499
2500 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2501 if (!adapter->tx_ring)
2502 goto err;
55aa6985
BA		 2503 adapter->tx_ring->count = adapter->tx_ring_count;
2504 adapter->tx_ring->adapter = adapter;
4662e82b 2505
55aa6985 2506 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2507 if (!adapter->rx_ring)
2508 goto err;
55aa6985
BA		 2509 adapter->rx_ring->count = adapter->rx_ring_count;
2510 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2511
2512 return 0;
2513err:
2514 e_err("Unable to allocate memory for queues\n");
2515 kfree(adapter->rx_ring);
2516 kfree(adapter->tx_ring);
2517 return -ENOMEM;
2518}
2519
bc7f75fa
AK		 2520/**
2521 * e1000_clean - NAPI Rx polling callback
ad68076e 2522 * @napi: struct associated with this polling callback
489815ce 2523 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2524 **/
2525static int e1000_clean(struct napi_struct *napi, int budget)
2526{
2527 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2528 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2529 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2530 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2531
4cf1653a 2532 adapter = netdev_priv(poll_dev);
bc7f75fa 2533
4662e82b
BA		 2534 if (adapter->msix_entries &&
2535 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2536 goto clean_rx;
2537
55aa6985 2538 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
bc7f75fa 2539
4662e82b 2540clean_rx:
55aa6985 2541 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2542
12d04a3c 2543 if (!tx_cleaned)
d2c7ddd6 2544 work_done = budget;
bc7f75fa 2545
53e52c72
DM		 2546 /* If budget not fully consumed, exit the polling mode */
2547 if (work_done < budget) {
bc7f75fa
AK		 2548 if (adapter->itr_setting & 3)
2549 e1000_set_itr(adapter);
288379f0 2550 napi_complete(napi);
a3c69fef
JB		 2551 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2552 if (adapter->msix_entries)
2553 ew32(IMS, adapter->rx_ring->ims_val);
2554 else
2555 e1000_irq_enable(adapter);
2556 }
bc7f75fa
AK		 2557 }
2558
2559 return work_done;
2560}
2561
8e586137 2562static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2563{
2564 struct e1000_adapter *adapter = netdev_priv(netdev);
2565 struct e1000_hw *hw = &adapter->hw;
2566 u32 vfta, index;
2567
2568 /* don't update vlan cookie if already programmed */
2569 if ((adapter->hw.mng_cookie.status &
2570 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2571 (vid == adapter->mng_vlan_id))
8e586137 2572 return 0;
caaddaf8 2573
bc7f75fa 2574 /* add VID to filter table */
caaddaf8
BA		 2575 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2576 index = (vid >> 5) & 0x7F;
2577 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2578 vfta |= (1 << (vid & 0x1F));
2579 hw->mac.ops.write_vfta(hw, index, vfta);
2580 }
86d70e53
JK		 2581
2582 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2583
2584 return 0;
bc7f75fa
AK		 2585}
2586
8e586137 2587static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2588{
2589 struct e1000_adapter *adapter = netdev_priv(netdev);
2590 struct e1000_hw *hw = &adapter->hw;
2591 u32 vfta, index;
2592
bc7f75fa
AK		 2593 if ((adapter->hw.mng_cookie.status &
2594 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2595 (vid == adapter->mng_vlan_id)) {
2596 /* release control to f/w */
31dbe5b4 2597 e1000e_release_hw_control(adapter);
8e586137 2598 return 0;
bc7f75fa
AK		 2599 }
2600
2601 /* remove VID from filter table */
caaddaf8
BA		 2602 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2603 index = (vid >> 5) & 0x7F;
2604 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2605 vfta &= ~(1 << (vid & 0x1F));
2606 hw->mac.ops.write_vfta(hw, index, vfta);
2607 }
86d70e53
JK		 2608
2609 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2610
2611 return 0;
bc7f75fa
AK		 2612}
2613
86d70e53
JK		 2614/**
2615 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2616 * @adapter: board private structure to initialize
2617 **/
2618static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2619{
2620 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2621 struct e1000_hw *hw = &adapter->hw;
2622 u32 rctl;
bc7f75fa 2623
86d70e53
JK		 2624 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2625 /* disable VLAN receive filtering */
2626 rctl = er32(RCTL);
2627 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2628 ew32(RCTL, rctl);
2629
2630 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2631 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2632 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2633 }
bc7f75fa
AK		 2634 }
2635}
2636
86d70e53
JK		 2637/**
2638 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2639 * @adapter: board private structure to initialize
2640 **/
2641static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2642{
2643 struct e1000_hw *hw = &adapter->hw;
2644 u32 rctl;
2645
2646 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2647 /* enable VLAN receive filtering */
2648 rctl = er32(RCTL);
2649 rctl |= E1000_RCTL_VFE;
2650 rctl &= ~E1000_RCTL_CFIEN;
2651 ew32(RCTL, rctl);
2652 }
2653}
bc7f75fa 2654
86d70e53
JK		 2655/**
2656 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2657 * @adapter: board private structure to initialize
2658 **/
2659static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2660{
bc7f75fa 2661 struct e1000_hw *hw = &adapter->hw;
86d70e53 2662 u32 ctrl;
bc7f75fa 2663
86d70e53
JK		 2664 /* disable VLAN tag insert/strip */
2665 ctrl = er32(CTRL);
2666 ctrl &= ~E1000_CTRL_VME;
2667 ew32(CTRL, ctrl);
2668}
bc7f75fa 2669
86d70e53
JK		 2670/**
2671 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2672 * @adapter: board private structure to initialize
2673 **/
2674static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2675{
2676 struct e1000_hw *hw = &adapter->hw;
2677 u32 ctrl;
bc7f75fa 2678
86d70e53
JK		 2679 /* enable VLAN tag insert/strip */
2680 ctrl = er32(CTRL);
2681 ctrl |= E1000_CTRL_VME;
2682 ew32(CTRL, ctrl);
2683}
bc7f75fa 2684
86d70e53
JK		 2685static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2686{
2687 struct net_device *netdev = adapter->netdev;
2688 u16 vid = adapter->hw.mng_cookie.vlan_id;
2689 u16 old_vid = adapter->mng_vlan_id;
2690
2691 if (adapter->hw.mng_cookie.status &
2692 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2693 e1000_vlan_rx_add_vid(netdev, vid);
2694 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2695 }
2696
86d70e53
JK		 2697 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2698 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2699}
2700
2701static void e1000_restore_vlan(struct e1000_adapter *adapter)
2702{
2703 u16 vid;
2704
86d70e53 2705 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2706
86d70e53 2707 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2708 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2709}
2710
cd791618 2711static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2712{
2713 struct e1000_hw *hw = &adapter->hw;
cd791618 2714 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2715
2716 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2717 return;
2718
2719 manc = er32(MANC);
2720
ad68076e
BA		 2721 /*
2722 * enable receiving management packets to the host. this will probably
bc7f75fa 2723 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2724 * the packets will be handled on SMBUS
2725 */
bc7f75fa
AK		 2726 manc |= E1000_MANC_EN_MNG2HOST;
2727 manc2h = er32(MANC2H);
cd791618
BA		 2728
2729 switch (hw->mac.type) {
2730 default:
2731 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2732 break;
2733 case e1000_82574:
2734 case e1000_82583:
2735 /*
2736 * Check if IPMI pass-through decision filter already exists;
2737 * if so, enable it.
2738 */
2739 for (i = 0, j = 0; i < 8; i++) {
2740 mdef = er32(MDEF(i));
2741
2742 /* Ignore filters with anything other than IPMI ports */
3b21b508 2743 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2744 continue;
2745
2746 /* Enable this decision filter in MANC2H */
2747 if (mdef)
2748 manc2h |= (1 << i);
2749
2750 j |= mdef;
2751 }
2752
2753 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2754 break;
2755
2756 /* Create new decision filter in an empty filter */
2757 for (i = 0, j = 0; i < 8; i++)
2758 if (er32(MDEF(i)) == 0) {
2759 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2760 E1000_MDEF_PORT_664));
2761 manc2h |= (1 << 1);
2762 j++;
2763 break;
2764 }
2765
2766 if (!j)
2767 e_warn("Unable to create IPMI pass-through filter\n");
2768 break;
2769 }
2770
bc7f75fa
AK		 2771 ew32(MANC2H, manc2h);
2772 ew32(MANC, manc);
2773}
2774
2775/**
af667a29 2776 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2777 * @adapter: board private structure
2778 *
2779 * Configure the Tx unit of the MAC after a reset.
2780 **/
2781static void e1000_configure_tx(struct e1000_adapter *adapter)
2782{
2783 struct e1000_hw *hw = &adapter->hw;
2784 struct e1000_ring *tx_ring = adapter->tx_ring;
2785 u64 tdba;
c550b121 2786 u32 tdlen, tarc;
bc7f75fa
AK		 2787
2788 /* Setup the HW Tx Head and Tail descriptor pointers */
2789 tdba = tx_ring->dma;
2790 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2791 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2792 ew32(TDBAH, (tdba >> 32));
2793 ew32(TDLEN, tdlen);
2794 ew32(TDH, 0);
2795 ew32(TDT, 0);
c5083cf6
BA		 2796 tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
2797 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
bc7f75fa 2798
bc7f75fa
AK		 2799 /* Set the Tx Interrupt Delay register */
2800 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2801 /* Tx irq moderation */
bc7f75fa
AK		 2802 ew32(TADV, adapter->tx_abs_int_delay);
2803
3a3b7586
JB		 2804 if (adapter->flags2 & FLAG2_DMA_BURST) {
2805 u32 txdctl = er32(TXDCTL(0));
2806 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2807 E1000_TXDCTL_WTHRESH);
2808 /*
2809 * set up some performance related parameters to encourage the
2810 * hardware to use the bus more efficiently in bursts, depends
2811 * on the tx_int_delay to be enabled,
2812 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2813 * hthresh = 1 ==> prefetch when one or more available
2814 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2815 * BEWARE: this seems to work but should be considered first if
af667a29 2816 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2817 */
2818 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2819 ew32(TXDCTL(0), txdctl);
3a3b7586 2820 }
56032be7
BA		 2821 /* erratum work around: set txdctl the same for both queues */
2822 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2823
bc7f75fa 2824 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2825 tarc = er32(TARC(0));
ad68076e
BA		 2826 /*
2827 * set the speed mode bit, we'll clear it if we're not at
2828 * gigabit link later
2829 */
bc7f75fa
AK		 2830#define SPEED_MODE_BIT (1 << 21)
2831 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2832 ew32(TARC(0), tarc);
bc7f75fa
AK		 2833 }
2834
2835 /* errata: program both queues to unweighted RR */
2836 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2837 tarc = er32(TARC(0));
bc7f75fa 2838 tarc |= 1;
e9ec2c0f
JK		 2839 ew32(TARC(0), tarc);
2840 tarc = er32(TARC(1));
bc7f75fa 2841 tarc |= 1;
e9ec2c0f 2842 ew32(TARC(1), tarc);
bc7f75fa
AK		 2843 }
2844
bc7f75fa
AK		 2845 /* Setup Transmit Descriptor Settings for eop descriptor */
2846 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2847
2848 /* only set IDE if we are delaying interrupts using the timers */
2849 if (adapter->tx_int_delay)
2850 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2851
2852 /* enable Report Status bit */
2853 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2854
edfea6e6 2855 e1000e_config_collision_dist(hw);
bc7f75fa
AK		 2856}
2857
2858/**
2859 * e1000_setup_rctl - configure the receive control registers
2860 * @adapter: Board private structure
2861 **/
2862#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2863 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2864static void e1000_setup_rctl(struct e1000_adapter *adapter)
2865{
2866 struct e1000_hw *hw = &adapter->hw;
2867 u32 rctl, rfctl;
bc7f75fa
AK		 2868 u32 pages = 0;
2869
a1ce6473
BA		 2870 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2871 if (hw->mac.type == e1000_pch2lan) {
2872 s32 ret_val;
2873
2874 if (adapter->netdev->mtu > ETH_DATA_LEN)
2875 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2876 else
2877 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2878
2879 if (ret_val)
2880 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2881 }
2882
bc7f75fa
AK		 2883 /* Program MC offset vector base */
2884 rctl = er32(RCTL);
2885 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2886 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2887 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2888 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2889
2890 /* Do not Store bad packets */
2891 rctl &= ~E1000_RCTL_SBP;
2892
2893 /* Enable Long Packet receive */
2894 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2895 rctl &= ~E1000_RCTL_LPE;
2896 else
2897 rctl |= E1000_RCTL_LPE;
2898
eb7c3adb
JK		 2899 /* Some systems expect that the CRC is included in SMBUS traffic. The
2900 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2901 * host memory when this is enabled
2902 */
2903 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2904 rctl |= E1000_RCTL_SECRC;
5918bd88 2905
a4f58f54
BA		 2906 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2907 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2908 u16 phy_data;
2909
2910 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2911 phy_data &= 0xfff8;
2912 phy_data |= (1 << 2);
2913 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2914
2915 e1e_rphy(hw, 22, &phy_data);
2916 phy_data &= 0x0fff;
2917 phy_data |= (1 << 14);
2918 e1e_wphy(hw, 0x10, 0x2823);
2919 e1e_wphy(hw, 0x11, 0x0003);
2920 e1e_wphy(hw, 22, phy_data);
2921 }
2922
bc7f75fa
AK		 2923 /* Setup buffer sizes */
2924 rctl &= ~E1000_RCTL_SZ_4096;
2925 rctl |= E1000_RCTL_BSEX;
2926 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2927 case 2048:
2928 default:
2929 rctl |= E1000_RCTL_SZ_2048;
2930 rctl &= ~E1000_RCTL_BSEX;
2931 break;
2932 case 4096:
2933 rctl |= E1000_RCTL_SZ_4096;
2934 break;
2935 case 8192:
2936 rctl |= E1000_RCTL_SZ_8192;
2937 break;
2938 case 16384:
2939 rctl |= E1000_RCTL_SZ_16384;
2940 break;
2941 }
2942
5f450212
BA		 2943 /* Enable Extended Status in all Receive Descriptors */
2944 rfctl = er32(RFCTL);
2945 rfctl |= E1000_RFCTL_EXTEN;
2946
bc7f75fa
AK		 2947 /*
2948 * 82571 and greater support packet-split where the protocol
2949 * header is placed in skb->data and the packet data is
2950 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2951 * In the case of a non-split, skb->data is linearly filled,
2952 * followed by the page buffers. Therefore, skb->data is
2953 * sized to hold the largest protocol header.
2954 *
2955 * allocations using alloc_page take too long for regular MTU
2956 * so only enable packet split for jumbo frames
2957 *
2958 * Using pages when the page size is greater than 16k wastes
2959 * a lot of memory, since we allocate 3 pages at all times
2960 * per packet.
2961 */
bc7f75fa 2962 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2963 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2964 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2965 else
2966 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2967
2968 if (adapter->rx_ps_pages) {
90da0669
BA		 2969 u32 psrctl = 0;
2970
ad68076e
BA		 2971 /*
2972 * disable packet split support for IPv6 extension headers,
2973 * because some malformed IPv6 headers can hang the Rx
2974 */
bc7f75fa
AK		 2975 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2976 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2977
140a7480
AK		 2978 /* Enable Packet split descriptors */
2979 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2980
2981 psrctl |= adapter->rx_ps_bsize0 >>
2982 E1000_PSRCTL_BSIZE0_SHIFT;
2983
2984 switch (adapter->rx_ps_pages) {
2985 case 3:
2986 psrctl |= PAGE_SIZE <<
2987 E1000_PSRCTL_BSIZE3_SHIFT;
2988 case 2:
2989 psrctl |= PAGE_SIZE <<
2990 E1000_PSRCTL_BSIZE2_SHIFT;
2991 case 1:
2992 psrctl |= PAGE_SIZE >>
2993 E1000_PSRCTL_BSIZE1_SHIFT;
2994 break;
2995 }
2996
2997 ew32(PSRCTL, psrctl);
2998 }
2999
5f450212 3000 ew32(RFCTL, rfctl);
bc7f75fa 3001 ew32(RCTL, rctl);
318a94d6
JK		 3002 /* just started the receive unit, no need to restart */
3003 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3004}
3005
3006/**
3007 * e1000_configure_rx - Configure Receive Unit after Reset
3008 * @adapter: board private structure
3009 *
3010 * Configure the Rx unit of the MAC after a reset.
3011 **/
3012static void e1000_configure_rx(struct e1000_adapter *adapter)
3013{
3014 struct e1000_hw *hw = &adapter->hw;
3015 struct e1000_ring *rx_ring = adapter->rx_ring;
3016 u64 rdba;
3017 u32 rdlen, rctl, rxcsum, ctrl_ext;
3018
3019 if (adapter->rx_ps_pages) {
3020 /* this is a 32 byte descriptor */
3021 rdlen = rx_ring->count *
af667a29 3022 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3023 adapter->clean_rx = e1000_clean_rx_irq_ps;
3024 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3025 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3026 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3027 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3028 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3029 } else {
5f450212 3030 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3031 adapter->clean_rx = e1000_clean_rx_irq;
3032 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3033 }
3034
3035 /* disable receives while setting up the descriptors */
3036 rctl = er32(RCTL);
7f99ae63
BA		 3037 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3038 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3039 e1e_flush();
1bba4386 3040 usleep_range(10000, 20000);
bc7f75fa 3041
3a3b7586
JB		 3042 if (adapter->flags2 & FLAG2_DMA_BURST) {
3043 /*
3044 * set the writeback threshold (only takes effect if the RDTR
3045 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3046 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3047 * granularity = 01
3048 * wthresh = 04,
3049 * hthresh = 04,
3050 * pthresh = 0x20
3051 */
3052 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3053 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3054
3055 /*
3056 * override the delay timers for enabling bursting, only if
3057 * the value was not set by the user via module options
3058 */
3059 if (adapter->rx_int_delay == DEFAULT_RDTR)
3060 adapter->rx_int_delay = BURST_RDTR;
3061 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3062 adapter->rx_abs_int_delay = BURST_RADV;
3063 }
3064
bc7f75fa
AK		 3065 /* set the Receive Delay Timer Register */
3066 ew32(RDTR, adapter->rx_int_delay);
3067
3068 /* irq moderation */
3069 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3070 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3071 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3072
3073 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3074 /* Auto-Mask interrupts upon ICR access */
3075 ctrl_ext |= E1000_CTRL_EXT_IAME;
3076 ew32(IAM, 0xffffffff);
3077 ew32(CTRL_EXT, ctrl_ext);
3078 e1e_flush();
3079
ad68076e
BA		 3080 /*
3081 * Setup the HW Rx Head and Tail Descriptor Pointers and
3082 * the Base and Length of the Rx Descriptor Ring
3083 */
bc7f75fa 3084 rdba = rx_ring->dma;
284901a9 3085 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3086 ew32(RDBAH, (rdba >> 32));
3087 ew32(RDLEN, rdlen);
3088 ew32(RDH, 0);
3089 ew32(RDT, 0);
c5083cf6
BA		 3090 rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
3091 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
bc7f75fa
AK		 3092
3093 /* Enable Receive Checksum Offload for TCP and UDP */
3094 rxcsum = er32(RXCSUM);
dc221294 3095 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3096 rxcsum |= E1000_RXCSUM_TUOFL;
3097
ad68076e
BA		 3098 /*
3099 * IPv4 payload checksum for UDP fragments must be
3100 * used in conjunction with packet-split.
3101 */
bc7f75fa
AK		 3102 if (adapter->rx_ps_pages)
3103 rxcsum |= E1000_RXCSUM_IPPCSE;
3104 } else {
3105 rxcsum &= ~E1000_RXCSUM_TUOFL;
3106 /* no need to clear IPPCSE as it defaults to 0 */
3107 }
3108 ew32(RXCSUM, rxcsum);
3109
79d4e908
BA		 3110 if (adapter->hw.mac.type == e1000_pch2lan) {
3111 /*
3112 * With jumbo frames, excessive C-state transition
3113 * latencies result in dropped transactions.
3114 */
53ec5498
BA		 3115 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3116 u32 rxdctl = er32(RXDCTL(0));
3117 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3118 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3119 } else {
af667a29
BA		 3120 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3121 PM_QOS_DEFAULT_VALUE);
53ec5498 3122 }
97ac8cae 3123 }
bc7f75fa
AK		 3124
3125 /* Enable Receives */
3126 ew32(RCTL, rctl);
3127}
3128
3129/**
ef9b965a
JB		 3130 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3131 * @netdev: network interface device structure
bc7f75fa 3132 *
ef9b965a
JB		 3133 * Writes multicast address list to the MTA hash table.
3134 * Returns: -ENOMEM on failure
3135 * 0 on no addresses written
3136 * X on writing X addresses to MTA
3137 */
3138static int e1000e_write_mc_addr_list(struct net_device *netdev)
3139{
3140 struct e1000_adapter *adapter = netdev_priv(netdev);
3141 struct e1000_hw *hw = &adapter->hw;
3142 struct netdev_hw_addr *ha;
3143 u8 *mta_list;
3144 int i;
3145
3146 if (netdev_mc_empty(netdev)) {
3147 /* nothing to program, so clear mc list */
3148 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3149 return 0;
3150 }
3151
3152 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3153 if (!mta_list)
3154 return -ENOMEM;
3155
3156 /* update_mc_addr_list expects a packed array of only addresses. */
3157 i = 0;
3158 netdev_for_each_mc_addr(ha, netdev)
3159 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3160
3161 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3162 kfree(mta_list);
3163
3164 return netdev_mc_count(netdev);
3165}
3166
3167/**
3168 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3169 * @netdev: network interface device structure
bc7f75fa 3170 *
ef9b965a
JB		 3171 * Writes unicast address list to the RAR table.
3172 * Returns: -ENOMEM on failure/insufficient address space
3173 * 0 on no addresses written
3174 * X on writing X addresses to the RAR table
bc7f75fa 3175 **/
ef9b965a 3176static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3177{
ef9b965a
JB		 3178 struct e1000_adapter *adapter = netdev_priv(netdev);
3179 struct e1000_hw *hw = &adapter->hw;
3180 unsigned int rar_entries = hw->mac.rar_entry_count;
3181 int count = 0;
3182
3183 /* save a rar entry for our hardware address */
3184 rar_entries--;
3185
3186 /* save a rar entry for the LAA workaround */
3187 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3188 rar_entries--;
3189
3190 /* return ENOMEM indicating insufficient memory for addresses */
3191 if (netdev_uc_count(netdev) > rar_entries)
3192 return -ENOMEM;
3193
3194 if (!netdev_uc_empty(netdev) && rar_entries) {
3195 struct netdev_hw_addr *ha;
3196
3197 /*
3198 * write the addresses in reverse order to avoid write
3199 * combining
3200 */
3201 netdev_for_each_uc_addr(ha, netdev) {
3202 if (!rar_entries)
3203 break;
3204 e1000e_rar_set(hw, ha->addr, rar_entries--);
3205 count++;
3206 }
3207 }
3208
3209 /* zero out the remaining RAR entries not used above */
3210 for (; rar_entries > 0; rar_entries--) {
3211 ew32(RAH(rar_entries), 0);
3212 ew32(RAL(rar_entries), 0);
3213 }
3214 e1e_flush();
3215
3216 return count;
bc7f75fa
AK		 3217}
3218
3219/**
ef9b965a 3220 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3221 * @netdev: network interface device structure
3222 *
ef9b965a
JB		 3223 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3224 * address list or the network interface flags are updated. This routine is
3225 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3226 * promiscuous mode, and all-multi behavior.
3227 **/
ef9b965a 3228static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3229{
3230 struct e1000_adapter *adapter = netdev_priv(netdev);
3231 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3232 u32 rctl;
bc7f75fa
AK		 3233
3234 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3235 rctl = er32(RCTL);
3236
ef9b965a
JB		 3237 /* clear the affected bits */
3238 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3239
bc7f75fa
AK		 3240 if (netdev->flags & IFF_PROMISC) {
3241 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3242 /* Do not hardware filter VLANs in promisc mode */
3243 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3244 } else {
ef9b965a 3245 int count;
746b9f02
PM		 3246 if (netdev->flags & IFF_ALLMULTI) {
3247 rctl |= E1000_RCTL_MPE;
746b9f02 3248 } else {
ef9b965a
JB		 3249 /*
3250 * Write addresses to the MTA, if the attempt fails
3251 * then we should just turn on promiscuous mode so
3252 * that we can at least receive multicast traffic
3253 */
3254 count = e1000e_write_mc_addr_list(netdev);
3255 if (count < 0)
3256 rctl |= E1000_RCTL_MPE;
746b9f02 3257 }
86d70e53 3258 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3259 /*
ef9b965a
JB		 3260 * Write addresses to available RAR registers, if there is not
3261 * sufficient space to store all the addresses then enable
3262 * unicast promiscuous mode
bc7f75fa 3263 */
ef9b965a
JB		 3264 count = e1000e_write_uc_addr_list(netdev);
3265 if (count < 0)
3266 rctl |= E1000_RCTL_UPE;
bc7f75fa 3267 }
86d70e53 3268
ef9b965a
JB		 3269 ew32(RCTL, rctl);
3270
86d70e53
JK		 3271 if (netdev->features & NETIF_F_HW_VLAN_RX)
3272 e1000e_vlan_strip_enable(adapter);
3273 else
3274 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3275}
3276
70495a50
BA		 3277static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3278{
3279 struct e1000_hw *hw = &adapter->hw;
3280 u32 mrqc, rxcsum;
3281 int i;
3282 static const u32 rsskey[10] = {
3283 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3284 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3285 };
3286
3287 /* Fill out hash function seed */
3288 for (i = 0; i < 10; i++)
3289 ew32(RSSRK(i), rsskey[i]);
3290
3291 /* Direct all traffic to queue 0 */
3292 for (i = 0; i < 32; i++)
3293 ew32(RETA(i), 0);
3294
3295 /*
3296 * Disable raw packet checksumming so that RSS hash is placed in
3297 * descriptor on writeback.
3298 */
3299 rxcsum = er32(RXCSUM);
3300 rxcsum |= E1000_RXCSUM_PCSD;
3301
3302 ew32(RXCSUM, rxcsum);
3303
3304 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3305 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3306 E1000_MRQC_RSS_FIELD_IPV6 |
3307 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3308 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3309
3310 ew32(MRQC, mrqc);
3311}
3312
bc7f75fa 3313/**
ad68076e 3314 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3315 * @adapter: private board structure
3316 **/
3317static void e1000_configure(struct e1000_adapter *adapter)
3318{
55aa6985
BA		 3319 struct e1000_ring *rx_ring = adapter->rx_ring;
3320
ef9b965a 3321 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3322
3323 e1000_restore_vlan(adapter);
cd791618 3324 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3325
3326 e1000_configure_tx(adapter);
70495a50
BA		 3327
3328 if (adapter->netdev->features & NETIF_F_RXHASH)
3329 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3330 e1000_setup_rctl(adapter);
3331 e1000_configure_rx(adapter);
55aa6985 3332 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3333}
3334
3335/**
3336 * e1000e_power_up_phy - restore link in case the phy was powered down
3337 * @adapter: address of board private structure
3338 *
3339 * The phy may be powered down to save power and turn off link when the
3340 * driver is unloaded and wake on lan is not enabled (among others)
3341 * *** this routine MUST be followed by a call to e1000e_reset ***
3342 **/
3343void e1000e_power_up_phy(struct e1000_adapter *adapter)
3344{
17f208de
BA		 3345 if (adapter->hw.phy.ops.power_up)
3346 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3347
3348 adapter->hw.mac.ops.setup_link(&adapter->hw);
3349}
3350
3351/**
3352 * e1000_power_down_phy - Power down the PHY
3353 *
17f208de
BA		 3354 * Power down the PHY so no link is implied when interface is down.
3355 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3356 */
3357static void e1000_power_down_phy(struct e1000_adapter *adapter)
3358{
bc7f75fa 3359 /* WoL is enabled */
23b66e2b 3360 if (adapter->wol)
bc7f75fa
AK		 3361 return;
3362
17f208de
BA		 3363 if (adapter->hw.phy.ops.power_down)
3364 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3365}
3366
3367/**
3368 * e1000e_reset - bring the hardware into a known good state
3369 *
3370 * This function boots the hardware and enables some settings that
3371 * require a configuration cycle of the hardware - those cannot be
3372 * set/changed during runtime. After reset the device needs to be
ad68076e 3373 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3374 */
3375void e1000e_reset(struct e1000_adapter *adapter)
3376{
3377 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3378 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3379 struct e1000_hw *hw = &adapter->hw;
3380 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3381 u32 pba = adapter->pba;
bc7f75fa
AK		 3382 u16 hwm;
3383
ad68076e 3384 /* reset Packet Buffer Allocation to default */
318a94d6 3385 ew32(PBA, pba);
df762464 3386
318a94d6 3387 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3388 /*
3389 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3390 * large enough to accommodate two full transmit packets,
3391 * rounded up to the next 1KB and expressed in KB. Likewise,
3392 * the Rx FIFO should be large enough to accommodate at least
3393 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3394 * expressed in KB.
3395 */
df762464 3396 pba = er32(PBA);
bc7f75fa 3397 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3398 tx_space = pba >> 16;
bc7f75fa 3399 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3400 pba &= 0xffff;
ad68076e 3401 /*
af667a29 3402 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3403 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3404 */
3405 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3406 sizeof(struct e1000_tx_desc) -
3407 ETH_FCS_LEN) * 2;
3408 min_tx_space = ALIGN(min_tx_space, 1024);
3409 min_tx_space >>= 10;
3410 /* software strips receive CRC, so leave room for it */
318a94d6 3411 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3412 min_rx_space = ALIGN(min_rx_space, 1024);
3413 min_rx_space >>= 10;
3414
ad68076e
BA		 3415 /*
3416 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3417 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3418 * allocation, take space away from current Rx allocation
3419 */
df762464
AK		 3420 if ((tx_space < min_tx_space) &&
3421 ((min_tx_space - tx_space) < pba)) {
3422 pba -= min_tx_space - tx_space;
bc7f75fa 3423
ad68076e 3424 /*
af667a29 3425 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3426 * adjustment or use Early Receive if available
3427 */
79d4e908 3428 if (pba < min_rx_space)
df762464 3429 pba = min_rx_space;
bc7f75fa 3430 }
df762464
AK		 3431
3432 ew32(PBA, pba);
bc7f75fa
AK		 3433 }
3434
ad68076e
BA		 3435 /*
3436 * flow control settings
3437 *
38eb394e 3438 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3439 * (or the size used for early receive) above it in the Rx FIFO.
3440 * Set it to the lower of:
3441 * - 90% of the Rx FIFO size, and
38eb394e 3442 * - the full Rx FIFO size minus one full frame
ad68076e 3443 */
d3738bb8
BA		 3444 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3445 fc->pause_time = 0xFFFF;
3446 else
3447 fc->pause_time = E1000_FC_PAUSE_TIME;
3448 fc->send_xon = 1;
3449 fc->current_mode = fc->requested_mode;
3450
3451 switch (hw->mac.type) {
79d4e908
BA		 3452 case e1000_ich9lan:
3453 case e1000_ich10lan:
3454 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3455 pba = 14;
3456 ew32(PBA, pba);
3457 fc->high_water = 0x2800;
3458 fc->low_water = fc->high_water - 8;
3459 break;
3460 }
3461 /* fall-through */
d3738bb8 3462 default:
79d4e908
BA		 3463 hwm = min(((pba << 10) * 9 / 10),
3464 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3465
3466 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3467 fc->low_water = fc->high_water - 8;
3468 break;
3469 case e1000_pchlan:
38eb394e
BA		 3470 /*
3471 * Workaround PCH LOM adapter hangs with certain network
3472 * loads. If hangs persist, try disabling Tx flow control.
3473 */
3474 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3475 fc->high_water = 0x3500;
3476 fc->low_water = 0x1500;
3477 } else {
3478 fc->high_water = 0x5000;
3479 fc->low_water = 0x3000;
3480 }
a305595b 3481 fc->refresh_time = 0x1000;
d3738bb8
BA		 3482 break;
3483 case e1000_pch2lan:
3484 fc->high_water = 0x05C20;
3485 fc->low_water = 0x05048;
3486 fc->pause_time = 0x0650;
3487 fc->refresh_time = 0x0400;
828bac87
BA		 3488 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3489 pba = 14;
3490 ew32(PBA, pba);
3491 }
d3738bb8 3492 break;
38eb394e 3493 }
bc7f75fa 3494
828bac87
BA		 3495 /*
3496 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3497 * fit in receive buffer.
828bac87
BA		 3498 */
3499 if (adapter->itr_setting & 0x3) {
79d4e908 3500 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3501 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3502 dev_info(&adapter->pdev->dev,
3503 "Interrupt Throttle Rate turned off\n");
3504 adapter->flags2 |= FLAG2_DISABLE_AIM;
3505 ew32(ITR, 0);
3506 }
3507 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3508 dev_info(&adapter->pdev->dev,
3509 "Interrupt Throttle Rate turned on\n");
3510 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3511 adapter->itr = 20000;
3512 ew32(ITR, 1000000000 / (adapter->itr * 256));
3513 }
3514 }
3515
bc7f75fa
AK		 3516 /* Allow time for pending master requests to run */
3517 mac->ops.reset_hw(hw);
97ac8cae
BA		 3518
3519 /*
3520 * For parts with AMT enabled, let the firmware know
3521 * that the network interface is in control
3522 */
c43bc57e 3523 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3524 e1000e_get_hw_control(adapter);
97ac8cae 3525
bc7f75fa
AK		 3526 ew32(WUC, 0);
3527
3528 if (mac->ops.init_hw(hw))
44defeb3 3529 e_err("Hardware Error\n");
bc7f75fa
AK		 3530
3531 e1000_update_mng_vlan(adapter);
3532
3533 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3534 ew32(VET, ETH_P_8021Q);
3535
3536 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3537
3538 if (!netif_running(adapter->netdev) &&
3539 !test_bit(__E1000_TESTING, &adapter->state)) {
3540 e1000_power_down_phy(adapter);
3541 return;
3542 }
3543
bc7f75fa
AK		 3544 e1000_get_phy_info(hw);
3545
918d7197
BA		 3546 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3547 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3548 u16 phy_data = 0;
ad68076e
BA		 3549 /*
3550 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3551 * the return value of this function because there is nothing
ad68076e
BA		 3552 * different we would do if it failed
3553 */
bc7f75fa
AK		 3554 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3555 phy_data &= ~IGP02E1000_PM_SPD;
3556 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3557 }
bc7f75fa
AK		 3558}
3559
3560int e1000e_up(struct e1000_adapter *adapter)
3561{
3562 struct e1000_hw *hw = &adapter->hw;
3563
3564 /* hardware has been reset, we need to reload some things */
3565 e1000_configure(adapter);
3566
3567 clear_bit(__E1000_DOWN, &adapter->state);
3568
4662e82b
BA		 3569 if (adapter->msix_entries)
3570 e1000_configure_msix(adapter);
bc7f75fa
AK		 3571 e1000_irq_enable(adapter);
3572
400484fa 3573 netif_start_queue(adapter->netdev);
4cb9be7a 3574
bc7f75fa 3575 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3576 if (adapter->msix_entries)
3577 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3578 else
3579 ew32(ICS, E1000_ICS_LSC);
3580
bc7f75fa
AK		 3581 return 0;
3582}
3583
713b3c9e
JB		 3584static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3585{
3586 struct e1000_hw *hw = &adapter->hw;
3587
3588 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3589 return;
3590
3591 /* flush pending descriptor writebacks to memory */
3592 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3593 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3594
3595 /* execute the writes immediately */
3596 e1e_flush();
3597}
3598
67fd4fcb
JK		 3599static void e1000e_update_stats(struct e1000_adapter *adapter);
3600
bc7f75fa
AK		 3601void e1000e_down(struct e1000_adapter *adapter)
3602{
3603 struct net_device *netdev = adapter->netdev;
3604 struct e1000_hw *hw = &adapter->hw;
3605 u32 tctl, rctl;
3606
ad68076e
BA		 3607 /*
3608 * signal that we're down so the interrupt handler does not
3609 * reschedule our watchdog timer
3610 */
bc7f75fa
AK		 3611 set_bit(__E1000_DOWN, &adapter->state);
3612
3613 /* disable receives in the hardware */
3614 rctl = er32(RCTL);
7f99ae63
BA		 3615 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3616 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3617 /* flush and sleep below */
3618
4cb9be7a 3619 netif_stop_queue(netdev);
bc7f75fa
AK		 3620
3621 /* disable transmits in the hardware */
3622 tctl = er32(TCTL);
3623 tctl &= ~E1000_TCTL_EN;
3624 ew32(TCTL, tctl);
7f99ae63 3625
bc7f75fa
AK		 3626 /* flush both disables and wait for them to finish */
3627 e1e_flush();
1bba4386 3628 usleep_range(10000, 20000);
bc7f75fa 3629
bc7f75fa
AK		 3630 e1000_irq_disable(adapter);
3631
3632 del_timer_sync(&adapter->watchdog_timer);
3633 del_timer_sync(&adapter->phy_info_timer);
3634
bc7f75fa 3635 netif_carrier_off(netdev);
67fd4fcb
JK		 3636
3637 spin_lock(&adapter->stats64_lock);
3638 e1000e_update_stats(adapter);
3639 spin_unlock(&adapter->stats64_lock);
3640
400484fa 3641 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3642 e1000_clean_tx_ring(adapter->tx_ring);
3643 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3644
bc7f75fa
AK		 3645 adapter->link_speed = 0;
3646 adapter->link_duplex = 0;
3647
52cc3086
JK		 3648 if (!pci_channel_offline(adapter->pdev))
3649 e1000e_reset(adapter);
713b3c9e 3650
bc7f75fa
AK		 3651 /*
3652 * TODO: for power management, we could drop the link and
3653 * pci_disable_device here.
3654 */
3655}
3656
3657void e1000e_reinit_locked(struct e1000_adapter *adapter)
3658{
3659 might_sleep();
3660 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3661 usleep_range(1000, 2000);
bc7f75fa
AK		 3662 e1000e_down(adapter);
3663 e1000e_up(adapter);
3664 clear_bit(__E1000_RESETTING, &adapter->state);
3665}
3666
3667/**
3668 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3669 * @adapter: board private structure to initialize
3670 *
3671 * e1000_sw_init initializes the Adapter private data structure.
3672 * Fields are initialized based on PCI device information and
3673 * OS network device settings (MTU size).
3674 **/
3675static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3676{
bc7f75fa
AK		 3677 struct net_device *netdev = adapter->netdev;
3678
3679 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3680 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3681 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3682 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3683 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3684 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3685
67fd4fcb
JK		 3686 spin_lock_init(&adapter->stats64_lock);
3687
4662e82b 3688 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3689
4662e82b
BA		 3690 if (e1000_alloc_queues(adapter))
3691 return -ENOMEM;
bc7f75fa 3692
bc7f75fa 3693 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3694 e1000_irq_disable(adapter);
3695
bc7f75fa
AK		 3696 set_bit(__E1000_DOWN, &adapter->state);
3697 return 0;
bc7f75fa
AK		 3698}
3699
f8d59f78
BA		 3700/**
3701 * e1000_intr_msi_test - Interrupt Handler
3702 * @irq: interrupt number
3703 * @data: pointer to a network interface device structure
3704 **/
3705static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3706{
3707 struct net_device *netdev = data;
3708 struct e1000_adapter *adapter = netdev_priv(netdev);
3709 struct e1000_hw *hw = &adapter->hw;
3710 u32 icr = er32(ICR);
3711
3bb99fe2 3712 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3713 if (icr & E1000_ICR_RXSEQ) {
3714 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3715 wmb();
3716 }
3717
3718 return IRQ_HANDLED;
3719}
3720
3721/**
3722 * e1000_test_msi_interrupt - Returns 0 for successful test
3723 * @adapter: board private struct
3724 *
3725 * code flow taken from tg3.c
3726 **/
3727static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3728{
3729 struct net_device *netdev = adapter->netdev;
3730 struct e1000_hw *hw = &adapter->hw;
3731 int err;
3732
3733 /* poll_enable hasn't been called yet, so don't need disable */
3734 /* clear any pending events */
3735 er32(ICR);
3736
3737 /* free the real vector and request a test handler */
3738 e1000_free_irq(adapter);
4662e82b 3739 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3740
3741 /* Assume that the test fails, if it succeeds then the test
3742 * MSI irq handler will unset this flag */
3743 adapter->flags |= FLAG_MSI_TEST_FAILED;
3744
3745 err = pci_enable_msi(adapter->pdev);
3746 if (err)
3747 goto msi_test_failed;
3748
a0607fd3 3749 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3750 netdev->name, netdev);
3751 if (err) {
3752 pci_disable_msi(adapter->pdev);
3753 goto msi_test_failed;
3754 }
3755
3756 wmb();
3757
3758 e1000_irq_enable(adapter);
3759
3760 /* fire an unusual interrupt on the test handler */
3761 ew32(ICS, E1000_ICS_RXSEQ);
3762 e1e_flush();
3763 msleep(50);
3764
3765 e1000_irq_disable(adapter);
3766
3767 rmb();
3768
3769 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3770 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3771 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3772 } else {
068e8a30 3773 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3774 }
f8d59f78
BA		 3775
3776 free_irq(adapter->pdev->irq, netdev);
3777 pci_disable_msi(adapter->pdev);
3778
f8d59f78 3779msi_test_failed:
4662e82b 3780 e1000e_set_interrupt_capability(adapter);
068e8a30 3781 return e1000_request_irq(adapter);
f8d59f78
BA		 3782}
3783
3784/**
3785 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3786 * @adapter: board private struct
3787 *
3788 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3789 **/
3790static int e1000_test_msi(struct e1000_adapter *adapter)
3791{
3792 int err;
3793 u16 pci_cmd;
3794
3795 if (!(adapter->flags & FLAG_MSI_ENABLED))
3796 return 0;
3797
3798 /* disable SERR in case the MSI write causes a master abort */
3799 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3800 if (pci_cmd & PCI_COMMAND_SERR)
3801 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3802 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3803
3804 err = e1000_test_msi_interrupt(adapter);
3805
36f2407f
DN		 3806 /* re-enable SERR */
3807 if (pci_cmd & PCI_COMMAND_SERR) {
3808 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3809 pci_cmd |= PCI_COMMAND_SERR;
3810 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3811 }
f8d59f78 3812
f8d59f78
BA		 3813 return err;
3814}
3815
bc7f75fa
AK		 3816/**
3817 * e1000_open - Called when a network interface is made active
3818 * @netdev: network interface device structure
3819 *
3820 * Returns 0 on success, negative value on failure
3821 *
3822 * The open entry point is called when a network interface is made
3823 * active by the system (IFF_UP). At this point all resources needed
3824 * for transmit and receive operations are allocated, the interrupt
3825 * handler is registered with the OS, the watchdog timer is started,
3826 * and the stack is notified that the interface is ready.
3827 **/
3828static int e1000_open(struct net_device *netdev)
3829{
3830 struct e1000_adapter *adapter = netdev_priv(netdev);
3831 struct e1000_hw *hw = &adapter->hw;
23606cf5 3832 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3833 int err;
3834
3835 /* disallow open during test */
3836 if (test_bit(__E1000_TESTING, &adapter->state))
3837 return -EBUSY;
3838
23606cf5
RW		 3839 pm_runtime_get_sync(&pdev->dev);
3840
9c563d20
JB		 3841 netif_carrier_off(netdev);
3842
bc7f75fa 3843 /* allocate transmit descriptors */
55aa6985 3844 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3845 if (err)
3846 goto err_setup_tx;
3847
3848 /* allocate receive descriptors */
55aa6985 3849 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3850 if (err)
3851 goto err_setup_rx;
3852
11b08be8
BA		 3853 /*
3854 * If AMT is enabled, let the firmware know that the network
3855 * interface is now open and reset the part to a known state.
3856 */
3857 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3858 e1000e_get_hw_control(adapter);
11b08be8
BA		 3859 e1000e_reset(adapter);
3860 }
3861
bc7f75fa
AK		 3862 e1000e_power_up_phy(adapter);
3863
3864 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3865 if ((adapter->hw.mng_cookie.status &
3866 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3867 e1000_update_mng_vlan(adapter);
3868
79d4e908
BA		 3869 /* DMA latency requirement to workaround jumbo issue */
3870 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3871 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3872 PM_QOS_CPU_DMA_LATENCY,
3873 PM_QOS_DEFAULT_VALUE);
c128ec29 3874
ad68076e
BA		 3875 /*
3876 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3877 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3878 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3879 * clean_rx handler before we do so.
3880 */
bc7f75fa
AK		 3881 e1000_configure(adapter);
3882
3883 err = e1000_request_irq(adapter);
3884 if (err)
3885 goto err_req_irq;
3886
f8d59f78
BA		 3887 /*
3888 * Work around PCIe errata with MSI interrupts causing some chipsets to
3889 * ignore e1000e MSI messages, which means we need to test our MSI
3890 * interrupt now
3891 */
4662e82b 3892 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3893 err = e1000_test_msi(adapter);
3894 if (err) {
3895 e_err("Interrupt allocation failed\n");
3896 goto err_req_irq;
3897 }
3898 }
3899
bc7f75fa
AK		 3900 /* From here on the code is the same as e1000e_up() */
3901 clear_bit(__E1000_DOWN, &adapter->state);
3902
3903 napi_enable(&adapter->napi);
3904
3905 e1000_irq_enable(adapter);
3906
09357b00 3907 adapter->tx_hang_recheck = false;
4cb9be7a 3908 netif_start_queue(netdev);
d55b53ff 3909
23606cf5
RW		 3910 adapter->idle_check = true;
3911 pm_runtime_put(&pdev->dev);
3912
bc7f75fa 3913 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3914 if (adapter->msix_entries)
3915 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3916 else
3917 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3918
3919 return 0;
3920
3921err_req_irq:
31dbe5b4 3922 e1000e_release_hw_control(adapter);
bc7f75fa 3923 e1000_power_down_phy(adapter);
55aa6985 3924 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3925err_setup_rx:
55aa6985 3926 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3927err_setup_tx:
3928 e1000e_reset(adapter);
23606cf5 3929 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3930
3931 return err;
3932}
3933
3934/**
3935 * e1000_close - Disables a network interface
3936 * @netdev: network interface device structure
3937 *
3938 * Returns 0, this is not allowed to fail
3939 *
3940 * The close entry point is called when an interface is de-activated
3941 * by the OS. The hardware is still under the drivers control, but
3942 * needs to be disabled. A global MAC reset is issued to stop the
3943 * hardware, and all transmit and receive resources are freed.
3944 **/
3945static int e1000_close(struct net_device *netdev)
3946{
3947 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3948 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3949
3950 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3951
3952 pm_runtime_get_sync(&pdev->dev);
3953
5f4a780d
BA		 3954 napi_disable(&adapter->napi);
3955
23606cf5
RW		 3956 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3957 e1000e_down(adapter);
3958 e1000_free_irq(adapter);
3959 }
bc7f75fa 3960 e1000_power_down_phy(adapter);
bc7f75fa 3961
55aa6985
BA		 3962 e1000e_free_tx_resources(adapter->tx_ring);
3963 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3964
ad68076e
BA		 3965 /*
3966 * kill manageability vlan ID if supported, but not if a vlan with
3967 * the same ID is registered on the host OS (let 8021q kill it)
3968 */
86d70e53
JK		 3969 if (adapter->hw.mng_cookie.status &
3970 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3971 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3972
ad68076e
BA		 3973 /*
3974 * If AMT is enabled, let the firmware know that the network
3975 * interface is now closed
3976 */
31dbe5b4
BA		 3977 if ((adapter->flags & FLAG_HAS_AMT) &&
3978 !test_bit(__E1000_TESTING, &adapter->state))
3979 e1000e_release_hw_control(adapter);
bc7f75fa 3980
79d4e908 3981 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 3982 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3983
23606cf5
RW		 3984 pm_runtime_put_sync(&pdev->dev);
3985
bc7f75fa
AK		 3986 return 0;
3987}
3988/**
3989 * e1000_set_mac - Change the Ethernet Address of the NIC
3990 * @netdev: network interface device structure
3991 * @p: pointer to an address structure
3992 *
3993 * Returns 0 on success, negative on failure
3994 **/
3995static int e1000_set_mac(struct net_device *netdev, void *p)
3996{
3997 struct e1000_adapter *adapter = netdev_priv(netdev);
3998 struct sockaddr *addr = p;
3999
4000 if (!is_valid_ether_addr(addr->sa_data))
4001 return -EADDRNOTAVAIL;
4002
4003 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4004 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4005
4006 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4007
4008 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4009 /* activate the work around */
4010 e1000e_set_laa_state_82571(&adapter->hw, 1);
4011
ad68076e
BA		 4012 /*
4013 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4014 * between the time RAR[0] gets clobbered and the time it
4015 * gets fixed (in e1000_watchdog), the actual LAA is in one
4016 * of the RARs and no incoming packets directed to this port
4017 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4018 * RAR[14]
4019 */
bc7f75fa
AK		 4020 e1000e_rar_set(&adapter->hw,
4021 adapter->hw.mac.addr,
4022 adapter->hw.mac.rar_entry_count - 1);
4023 }
4024
4025 return 0;
4026}
4027
a8f88ff5
JB		 4028/**
4029 * e1000e_update_phy_task - work thread to update phy
4030 * @work: pointer to our work struct
4031 *
4032 * this worker thread exists because we must acquire a
4033 * semaphore to read the phy, which we could msleep while
4034 * waiting for it, and we can't msleep in a timer.
4035 **/
4036static void e1000e_update_phy_task(struct work_struct *work)
4037{
4038 struct e1000_adapter *adapter = container_of(work,
4039 struct e1000_adapter, update_phy_task);
615b32af
JB		 4040
4041 if (test_bit(__E1000_DOWN, &adapter->state))
4042 return;
4043
a8f88ff5
JB		 4044 e1000_get_phy_info(&adapter->hw);
4045}
4046
ad68076e
BA		 4047/*
4048 * Need to wait a few seconds after link up to get diagnostic information from
4049 * the phy
4050 */
bc7f75fa
AK		 4051static void e1000_update_phy_info(unsigned long data)
4052{
4053 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4054
4055 if (test_bit(__E1000_DOWN, &adapter->state))
4056 return;
4057
a8f88ff5 4058 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4059}
4060
8c7bbb92
BA		 4061/**
4062 * e1000e_update_phy_stats - Update the PHY statistics counters
4063 * @adapter: board private structure
2b6b168d
BA		 4064 *
4065 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4066 **/
4067static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4068{
4069 struct e1000_hw *hw = &adapter->hw;
4070 s32 ret_val;
4071 u16 phy_data;
4072
4073 ret_val = hw->phy.ops.acquire(hw);
4074 if (ret_val)
4075 return;
4076
8c7bbb92
BA		 4077 /*
4078 * A page set is expensive so check if already on desired page.
4079 * If not, set to the page with the PHY status registers.
4080 */
2b6b168d 4081 hw->phy.addr = 1;
8c7bbb92
BA		 4082 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4083 &phy_data);
4084 if (ret_val)
4085 goto release;
2b6b168d
BA		 4086 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4087 ret_val = hw->phy.ops.set_page(hw,
4088 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4089 if (ret_val)
4090 goto release;
4091 }
4092
8c7bbb92 4093 /* Single Collision Count */
2b6b168d
BA		 4094 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4095 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4096 if (!ret_val)
4097 adapter->stats.scc += phy_data;
4098
4099 /* Excessive Collision Count */
2b6b168d
BA		 4100 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4101 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4102 if (!ret_val)
4103 adapter->stats.ecol += phy_data;
4104
4105 /* Multiple Collision Count */
2b6b168d
BA		 4106 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4107 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4108 if (!ret_val)
4109 adapter->stats.mcc += phy_data;
4110
4111 /* Late Collision Count */
2b6b168d
BA		 4112 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4113 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4114 if (!ret_val)
4115 adapter->stats.latecol += phy_data;
4116
4117 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4118 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4119 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4120 if (!ret_val)
4121 hw->mac.collision_delta = phy_data;
4122
4123 /* Defer Count */
2b6b168d
BA		 4124 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4125 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4126 if (!ret_val)
4127 adapter->stats.dc += phy_data;
4128
4129 /* Transmit with no CRS */
2b6b168d
BA		 4130 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4131 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4132 if (!ret_val)
4133 adapter->stats.tncrs += phy_data;
4134
4135release:
4136 hw->phy.ops.release(hw);
4137}
4138
bc7f75fa
AK		 4139/**
4140 * e1000e_update_stats - Update the board statistics counters
4141 * @adapter: board private structure
4142 **/
67fd4fcb 4143static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4144{
7274c20f 4145 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4146 struct e1000_hw *hw = &adapter->hw;
4147 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4148
4149 /*
4150 * Prevent stats update while adapter is being reset, or if the pci
4151 * connection is down.
4152 */
4153 if (adapter->link_speed == 0)
4154 return;
4155 if (pci_channel_offline(pdev))
4156 return;
4157
bc7f75fa
AK		 4158 adapter->stats.crcerrs += er32(CRCERRS);
4159 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4160 adapter->stats.gorc += er32(GORCL);
4161 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4162 adapter->stats.bprc += er32(BPRC);
4163 adapter->stats.mprc += er32(MPRC);
4164 adapter->stats.roc += er32(ROC);
4165
bc7f75fa 4166 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4167
4168 /* Half-duplex statistics */
4169 if (adapter->link_duplex == HALF_DUPLEX) {
4170 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4171 e1000e_update_phy_stats(adapter);
4172 } else {
4173 adapter->stats.scc += er32(SCC);
4174 adapter->stats.ecol += er32(ECOL);
4175 adapter->stats.mcc += er32(MCC);
4176 adapter->stats.latecol += er32(LATECOL);
4177 adapter->stats.dc += er32(DC);
4178
4179 hw->mac.collision_delta = er32(COLC);
4180
4181 if ((hw->mac.type != e1000_82574) &&
4182 (hw->mac.type != e1000_82583))
4183 adapter->stats.tncrs += er32(TNCRS);
4184 }
4185 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4186 }
8c7bbb92 4187
bc7f75fa
AK		 4188 adapter->stats.xonrxc += er32(XONRXC);
4189 adapter->stats.xontxc += er32(XONTXC);
4190 adapter->stats.xoffrxc += er32(XOFFRXC);
4191 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4192 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4193 adapter->stats.gotc += er32(GOTCL);
4194 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4195 adapter->stats.rnbc += er32(RNBC);
4196 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4197
4198 adapter->stats.mptc += er32(MPTC);
4199 adapter->stats.bptc += er32(BPTC);
4200
4201 /* used for adaptive IFS */
4202
4203 hw->mac.tx_packet_delta = er32(TPT);
4204 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4205
4206 adapter->stats.algnerrc += er32(ALGNERRC);
4207 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4208 adapter->stats.cexterr += er32(CEXTERR);
4209 adapter->stats.tsctc += er32(TSCTC);
4210 adapter->stats.tsctfc += er32(TSCTFC);
4211
bc7f75fa 4212 /* Fill out the OS statistics structure */
7274c20f
AK		 4213 netdev->stats.multicast = adapter->stats.mprc;
4214 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4215
4216 /* Rx Errors */
4217
ad68076e
BA		 4218 /*
4219 * RLEC on some newer hardware can be incorrect so build
4220 * our own version based on RUC and ROC
4221 */
7274c20f 4222 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4223 adapter->stats.crcerrs + adapter->stats.algnerrc +
4224 adapter->stats.ruc + adapter->stats.roc +
4225 adapter->stats.cexterr;
7274c20f 4226 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4227 adapter->stats.roc;
7274c20f
AK		 4228 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4229 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4230 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4231
4232 /* Tx Errors */
7274c20f 4233 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4234 adapter->stats.latecol;
7274c20f
AK		 4235 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4236 netdev->stats.tx_window_errors = adapter->stats.latecol;
4237 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4238
4239 /* Tx Dropped needs to be maintained elsewhere */
4240
bc7f75fa
AK		 4241 /* Management Stats */
4242 adapter->stats.mgptc += er32(MGTPTC);
4243 adapter->stats.mgprc += er32(MGTPRC);
4244 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4245}
4246
7c25769f
BA		 4247/**
4248 * e1000_phy_read_status - Update the PHY register status snapshot
4249 * @adapter: board private structure
4250 **/
4251static void e1000_phy_read_status(struct e1000_adapter *adapter)
4252{
4253 struct e1000_hw *hw = &adapter->hw;
4254 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4255
4256 if ((er32(STATUS) & E1000_STATUS_LU) &&
4257 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4258 int ret_val;
4259
7c25769f
BA		 4260 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4261 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4262 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4263 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4264 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4265 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4266 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4267 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4268 if (ret_val)
44defeb3 4269 e_warn("Error reading PHY register\n");
7c25769f
BA		 4270 } else {
4271 /*
4272 * Do not read PHY registers if link is not up
4273 * Set values to typical power-on defaults
4274 */
4275 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4276 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4277 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4278 BMSR_ERCAP);
4279 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4280 ADVERTISE_ALL | ADVERTISE_CSMA);
4281 phy->lpa = 0;
4282 phy->expansion = EXPANSION_ENABLENPAGE;
4283 phy->ctrl1000 = ADVERTISE_1000FULL;
4284 phy->stat1000 = 0;
4285 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4286 }
7c25769f
BA		 4287}
4288
bc7f75fa
AK		 4289static void e1000_print_link_info(struct e1000_adapter *adapter)
4290{
bc7f75fa
AK		 4291 struct e1000_hw *hw = &adapter->hw;
4292 u32 ctrl = er32(CTRL);
4293
8f12fe86 4294 /* Link status message must follow this format for user tools */
ef456f85
JK		 4295 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4296 adapter->netdev->name,
4297 adapter->link_speed,
4298 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4299 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4300 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4301 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4302}
4303
0c6bdb30 4304static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4305{
4306 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4307 bool link_active = false;
318a94d6
JK		 4308 s32 ret_val = 0;
4309
4310 /*
4311 * get_link_status is set on LSC (link status) interrupt or
4312 * Rx sequence error interrupt. get_link_status will stay
4313 * false until the check_for_link establishes link
4314 * for copper adapters ONLY
4315 */
4316 switch (hw->phy.media_type) {
4317 case e1000_media_type_copper:
4318 if (hw->mac.get_link_status) {
4319 ret_val = hw->mac.ops.check_for_link(hw);
4320 link_active = !hw->mac.get_link_status;
4321 } else {
3db1cd5c 4322 link_active = true;
318a94d6
JK		 4323 }
4324 break;
4325 case e1000_media_type_fiber:
4326 ret_val = hw->mac.ops.check_for_link(hw);
4327 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4328 break;
4329 case e1000_media_type_internal_serdes:
4330 ret_val = hw->mac.ops.check_for_link(hw);
4331 link_active = adapter->hw.mac.serdes_has_link;
4332 break;
4333 default:
4334 case e1000_media_type_unknown:
4335 break;
4336 }
4337
4338 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4339 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4340 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4341 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4342 }
4343
4344 return link_active;
4345}
4346
4347static void e1000e_enable_receives(struct e1000_adapter *adapter)
4348{
4349 /* make sure the receive unit is started */
4350 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4351 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4352 struct e1000_hw *hw = &adapter->hw;
4353 u32 rctl = er32(RCTL);
4354 ew32(RCTL, rctl | E1000_RCTL_EN);
4355 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4356 }
4357}
4358
ff10e13c
CW		 4359static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4360{
4361 struct e1000_hw *hw = &adapter->hw;
4362
4363 /*
4364 * With 82574 controllers, PHY needs to be checked periodically
4365 * for hung state and reset, if two calls return true
4366 */
4367 if (e1000_check_phy_82574(hw))
4368 adapter->phy_hang_count++;
4369 else
4370 adapter->phy_hang_count = 0;
4371
4372 if (adapter->phy_hang_count > 1) {
4373 adapter->phy_hang_count = 0;
4374 schedule_work(&adapter->reset_task);
4375 }
4376}
4377
bc7f75fa
AK		 4378/**
4379 * e1000_watchdog - Timer Call-back
4380 * @data: pointer to adapter cast into an unsigned long
4381 **/
4382static void e1000_watchdog(unsigned long data)
4383{
4384 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4385
4386 /* Do the rest outside of interrupt context */
4387 schedule_work(&adapter->watchdog_task);
4388
4389 /* TODO: make this use queue_delayed_work() */
4390}
4391
4392static void e1000_watchdog_task(struct work_struct *work)
4393{
4394 struct e1000_adapter *adapter = container_of(work,
4395 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4396 struct net_device *netdev = adapter->netdev;
4397 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4398 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4399 struct e1000_ring *tx_ring = adapter->tx_ring;
4400 struct e1000_hw *hw = &adapter->hw;
4401 u32 link, tctl;
bc7f75fa 4402
615b32af
JB		 4403 if (test_bit(__E1000_DOWN, &adapter->state))
4404 return;
4405
b405e8df 4406 link = e1000e_has_link(adapter);
318a94d6 4407 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4408 /* Cancel scheduled suspend requests. */
4409 pm_runtime_resume(netdev->dev.parent);
4410
318a94d6 4411 e1000e_enable_receives(adapter);
bc7f75fa 4412 goto link_up;
bc7f75fa
AK		 4413 }
4414
4415 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4416 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4417 e1000_update_mng_vlan(adapter);
4418
bc7f75fa
AK		 4419 if (link) {
4420 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4421 bool txb2b = true;
23606cf5
RW		 4422
4423 /* Cancel scheduled suspend requests. */
4424 pm_runtime_resume(netdev->dev.parent);
4425
318a94d6 4426 /* update snapshot of PHY registers on LSC */
7c25769f 4427 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4428 mac->ops.get_link_up_info(&adapter->hw,
4429 &adapter->link_speed,
4430 &adapter->link_duplex);
4431 e1000_print_link_info(adapter);
f4187b56
BA		 4432 /*
4433 * On supported PHYs, check for duplex mismatch only
4434 * if link has autonegotiated at 10/100 half
4435 */
4436 if ((hw->phy.type == e1000_phy_igp_3 ||
4437 hw->phy.type == e1000_phy_bm) &&
4438 (hw->mac.autoneg == true) &&
4439 (adapter->link_speed == SPEED_10 ||
4440 adapter->link_speed == SPEED_100) &&
4441 (adapter->link_duplex == HALF_DUPLEX)) {
4442 u16 autoneg_exp;
4443
4444 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4445
4446 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4447 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4448 }
4449
f49c57e1 4450 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4451 adapter->tx_timeout_factor = 1;
4452 switch (adapter->link_speed) {
4453 case SPEED_10:
3db1cd5c 4454 txb2b = false;
10f1b492 4455 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4456 break;
4457 case SPEED_100:
3db1cd5c 4458 txb2b = false;
4c86e0b9 4459 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4460 break;
4461 }
4462
ad68076e
BA		 4463 /*
4464 * workaround: re-program speed mode bit after
4465 * link-up event
4466 */
bc7f75fa
AK		 4467 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4468 !txb2b) {
4469 u32 tarc0;
e9ec2c0f 4470 tarc0 = er32(TARC(0));
bc7f75fa 4471 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4472 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4473 }
4474
ad68076e
BA		 4475 /*
4476 * disable TSO for pcie and 10/100 speeds, to avoid
4477 * some hardware issues
4478 */
bc7f75fa
AK		 4479 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4480 switch (adapter->link_speed) {
4481 case SPEED_10:
4482 case SPEED_100:
44defeb3 4483 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4484 netdev->features &= ~NETIF_F_TSO;
4485 netdev->features &= ~NETIF_F_TSO6;
4486 break;
4487 case SPEED_1000:
4488 netdev->features |= NETIF_F_TSO;
4489 netdev->features |= NETIF_F_TSO6;
4490 break;
4491 default:
4492 /* oops */
4493 break;
4494 }
4495 }
4496
ad68076e
BA		 4497 /*
4498 * enable transmits in the hardware, need to do this
4499 * after setting TARC(0)
4500 */
bc7f75fa
AK		 4501 tctl = er32(TCTL);
4502 tctl |= E1000_TCTL_EN;
4503 ew32(TCTL, tctl);
4504
75eb0fad
BA		 4505 /*
4506 * Perform any post-link-up configuration before
4507 * reporting link up.
4508 */
4509 if (phy->ops.cfg_on_link_up)
4510 phy->ops.cfg_on_link_up(hw);
4511
bc7f75fa 4512 netif_carrier_on(netdev);
bc7f75fa
AK		 4513
4514 if (!test_bit(__E1000_DOWN, &adapter->state))
4515 mod_timer(&adapter->phy_info_timer,
4516 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4517 }
4518 } else {
4519 if (netif_carrier_ok(netdev)) {
4520 adapter->link_speed = 0;
4521 adapter->link_duplex = 0;
8f12fe86
BA		 4522 /* Link status message must follow this format */
4523 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4524 adapter->netdev->name);
bc7f75fa 4525 netif_carrier_off(netdev);
bc7f75fa
AK		 4526 if (!test_bit(__E1000_DOWN, &adapter->state))
4527 mod_timer(&adapter->phy_info_timer,
4528 round_jiffies(jiffies + 2 * HZ));
4529
4530 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4531 schedule_work(&adapter->reset_task);
23606cf5
RW		 4532 else
4533 pm_schedule_suspend(netdev->dev.parent,
4534 LINK_TIMEOUT);
bc7f75fa
AK		 4535 }
4536 }
4537
4538link_up:
67fd4fcb 4539 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4540 e1000e_update_stats(adapter);
4541
4542 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4543 adapter->tpt_old = adapter->stats.tpt;
4544 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4545 adapter->colc_old = adapter->stats.colc;
4546
7c25769f
BA		 4547 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4548 adapter->gorc_old = adapter->stats.gorc;
4549 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4550 adapter->gotc_old = adapter->stats.gotc;
2084b114 4551 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4552
4553 e1000e_update_adaptive(&adapter->hw);
4554
90da0669
BA		 4555 if (!netif_carrier_ok(netdev) &&
4556 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4557 /*
4558 * We've lost link, so the controller stops DMA,
4559 * but we've got queued Tx work that's never going
4560 * to get done, so reset controller to flush Tx.
4561 * (Do the reset outside of interrupt context).
4562 */
90da0669
BA		 4563 schedule_work(&adapter->reset_task);
4564 /* return immediately since reset is imminent */
4565 return;
bc7f75fa
AK		 4566 }
4567
eab2abf5
JB		 4568 /* Simple mode for Interrupt Throttle Rate (ITR) */
4569 if (adapter->itr_setting == 4) {
4570 /*
4571 * Symmetric Tx/Rx gets a reduced ITR=2000;
4572 * Total asymmetrical Tx or Rx gets ITR=8000;
4573 * everyone else is between 2000-8000.
4574 */
4575 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4576 u32 dif = (adapter->gotc > adapter->gorc ?
4577 adapter->gotc - adapter->gorc :
4578 adapter->gorc - adapter->gotc) / 10000;
4579 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4580
4581 ew32(ITR, 1000000000 / (itr * 256));
4582 }
4583
ad68076e 4584 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4585 if (adapter->msix_entries)
4586 ew32(ICS, adapter->rx_ring->ims_val);
4587 else
4588 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4589
713b3c9e
JB		 4590 /* flush pending descriptors to memory before detecting Tx hang */
4591 e1000e_flush_descriptors(adapter);
4592
bc7f75fa 4593 /* Force detection of hung controller every watchdog period */
3db1cd5c 4594 adapter->detect_tx_hung = true;
bc7f75fa 4595
ad68076e
BA		 4596 /*
4597 * With 82571 controllers, LAA may be overwritten due to controller
4598 * reset from the other port. Set the appropriate LAA in RAR[0]
4599 */
bc7f75fa
AK		 4600 if (e1000e_get_laa_state_82571(hw))
4601 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4602
ff10e13c
CW		 4603 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4604 e1000e_check_82574_phy_workaround(adapter);
4605
bc7f75fa
AK		 4606 /* Reset the timer */
4607 if (!test_bit(__E1000_DOWN, &adapter->state))
4608 mod_timer(&adapter->watchdog_timer,
4609 round_jiffies(jiffies + 2 * HZ));
4610}
4611
4612#define E1000_TX_FLAGS_CSUM 0x00000001
4613#define E1000_TX_FLAGS_VLAN 0x00000002
4614#define E1000_TX_FLAGS_TSO 0x00000004
4615#define E1000_TX_FLAGS_IPV4 0x00000008
4616#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4617#define E1000_TX_FLAGS_VLAN_SHIFT 16
4618
55aa6985 4619static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4620{
bc7f75fa
AK		 4621 struct e1000_context_desc *context_desc;
4622 struct e1000_buffer *buffer_info;
4623 unsigned int i;
4624 u32 cmd_length = 0;
4625 u16 ipcse = 0, tucse, mss;
4626 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4627
3d5e33c9
BA		 4628 if (!skb_is_gso(skb))
4629 return 0;
bc7f75fa 4630
3d5e33c9 4631 if (skb_header_cloned(skb)) {
90da0669
BA		 4632 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4633
3d5e33c9
BA		 4634 if (err)
4635 return err;
bc7f75fa
AK		 4636 }
4637
3d5e33c9
BA		 4638 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4639 mss = skb_shinfo(skb)->gso_size;
4640 if (skb->protocol == htons(ETH_P_IP)) {
4641 struct iphdr *iph = ip_hdr(skb);
4642 iph->tot_len = 0;
4643 iph->check = 0;
4644 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4645 0, IPPROTO_TCP, 0);
4646 cmd_length = E1000_TXD_CMD_IP;
4647 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4648 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4649 ipv6_hdr(skb)->payload_len = 0;
4650 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4651 &ipv6_hdr(skb)->daddr,
4652 0, IPPROTO_TCP, 0);
4653 ipcse = 0;
4654 }
4655 ipcss = skb_network_offset(skb);
4656 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4657 tucss = skb_transport_offset(skb);
4658 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4659 tucse = 0;
4660
4661 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4662 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4663
4664 i = tx_ring->next_to_use;
4665 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4666 buffer_info = &tx_ring->buffer_info[i];
4667
4668 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4669 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4670 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4671 context_desc->upper_setup.tcp_fields.tucss = tucss;
4672 context_desc->upper_setup.tcp_fields.tucso = tucso;
4673 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4674 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4675 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4676 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4677
4678 buffer_info->time_stamp = jiffies;
4679 buffer_info->next_to_watch = i;
4680
4681 i++;
4682 if (i == tx_ring->count)
4683 i = 0;
4684 tx_ring->next_to_use = i;
4685
4686 return 1;
bc7f75fa
AK		 4687}
4688
55aa6985 4689static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4690{
55aa6985 4691 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4692 struct e1000_context_desc *context_desc;
4693 struct e1000_buffer *buffer_info;
4694 unsigned int i;
4695 u8 css;
af807c82 4696 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4697 __be16 protocol;
bc7f75fa 4698
af807c82
DG		 4699 if (skb->ip_summed != CHECKSUM_PARTIAL)
4700 return 0;
bc7f75fa 4701
5f66f208
AJ		 4702 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4703 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4704 else
4705 protocol = skb->protocol;
4706
3f518390 4707 switch (protocol) {
09640e63 4708 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4709 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4710 cmd_len |= E1000_TXD_CMD_TCP;
4711 break;
09640e63 4712 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4713 /* XXX not handling all IPV6 headers */
4714 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4715 cmd_len |= E1000_TXD_CMD_TCP;
4716 break;
4717 default:
4718 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4719 e_warn("checksum_partial proto=%x!\n",
4720 be16_to_cpu(protocol));
af807c82 4721 break;
bc7f75fa
AK		 4722 }
4723
0d0b1672 4724 css = skb_checksum_start_offset(skb);
af807c82
DG		 4725
4726 i = tx_ring->next_to_use;
4727 buffer_info = &tx_ring->buffer_info[i];
4728 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4729
4730 context_desc->lower_setup.ip_config = 0;
4731 context_desc->upper_setup.tcp_fields.tucss = css;
4732 context_desc->upper_setup.tcp_fields.tucso =
4733 css + skb->csum_offset;
4734 context_desc->upper_setup.tcp_fields.tucse = 0;
4735 context_desc->tcp_seg_setup.data = 0;
4736 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4737
4738 buffer_info->time_stamp = jiffies;
4739 buffer_info->next_to_watch = i;
4740
4741 i++;
4742 if (i == tx_ring->count)
4743 i = 0;
4744 tx_ring->next_to_use = i;
4745
4746 return 1;
bc7f75fa
AK		 4747}
4748
4749#define E1000_MAX_PER_TXD 8192
4750#define E1000_MAX_TXD_PWR 12
4751
55aa6985
BA		 4752static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4753 unsigned int first, unsigned int max_per_txd,
4754 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4755{
55aa6985 4756 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4757 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4758 struct e1000_buffer *buffer_info;
8ddc951c 4759 unsigned int len = skb_headlen(skb);
03b1320d 4760 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4761 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4762
4763 i = tx_ring->next_to_use;
4764
4765 while (len) {
1b7719c4 4766 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4767 size = min(len, max_per_txd);
4768
bc7f75fa 4769 buffer_info->length = size;
bc7f75fa 4770 buffer_info->time_stamp = jiffies;
bc7f75fa 4771 buffer_info->next_to_watch = i;
0be3f55f
NN		 4772 buffer_info->dma = dma_map_single(&pdev->dev,
4773 skb->data + offset,
af667a29 4774 size, DMA_TO_DEVICE);
03b1320d 4775 buffer_info->mapped_as_page = false;
0be3f55f 4776 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4777 goto dma_error;
bc7f75fa
AK		 4778
4779 len -= size;
4780 offset += size;
03b1320d 4781 count++;
1b7719c4
AD		 4782
4783 if (len) {
4784 i++;
4785 if (i == tx_ring->count)
4786 i = 0;
4787 }
bc7f75fa
AK		 4788 }
4789
4790 for (f = 0; f < nr_frags; f++) {
9e903e08 4791 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4792
4793 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4794 len = skb_frag_size(frag);
877749bf 4795 offset = 0;
bc7f75fa
AK		 4796
4797 while (len) {
1b7719c4
AD		 4798 i++;
4799 if (i == tx_ring->count)
4800 i = 0;
4801
bc7f75fa
AK		 4802 buffer_info = &tx_ring->buffer_info[i];
4803 size = min(len, max_per_txd);
bc7f75fa
AK		 4804
4805 buffer_info->length = size;
4806 buffer_info->time_stamp = jiffies;
bc7f75fa 4807 buffer_info->next_to_watch = i;
877749bf
IC		 4808 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4809 offset, size, DMA_TO_DEVICE);
03b1320d 4810 buffer_info->mapped_as_page = true;
0be3f55f 4811 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4812 goto dma_error;
bc7f75fa
AK		 4813
4814 len -= size;
4815 offset += size;
4816 count++;
bc7f75fa
AK		 4817 }
4818 }
4819
af667a29 4820 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4821 /* multiply data chunks by size of headers */
4822 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4823
bc7f75fa 4824 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4825 tx_ring->buffer_info[i].segs = segs;
4826 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4827 tx_ring->buffer_info[first].next_to_watch = i;
4828
4829 return count;
03b1320d
AD		 4830
4831dma_error:
af667a29 4832 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4833 buffer_info->dma = 0;
c1fa347f 4834 if (count)
03b1320d 4835 count--;
c1fa347f
RK		 4836
4837 while (count--) {
af667a29 4838 if (i == 0)
03b1320d 4839 i += tx_ring->count;
c1fa347f 4840 i--;
03b1320d 4841 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4842 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4843 }
4844
4845 return 0;
bc7f75fa
AK		 4846}
4847
55aa6985 4848static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4849{
55aa6985 4850 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4851 struct e1000_tx_desc *tx_desc = NULL;
4852 struct e1000_buffer *buffer_info;
4853 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4854 unsigned int i;
4855
4856 if (tx_flags & E1000_TX_FLAGS_TSO) {
4857 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4858 E1000_TXD_CMD_TSE;
4859 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4860
4861 if (tx_flags & E1000_TX_FLAGS_IPV4)
4862 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4863 }
4864
4865 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4866 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4867 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4868 }
4869
4870 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4871 txd_lower |= E1000_TXD_CMD_VLE;
4872 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4873 }
4874
4875 i = tx_ring->next_to_use;
4876
36b973df 4877 do {
bc7f75fa
AK		 4878 buffer_info = &tx_ring->buffer_info[i];
4879 tx_desc = E1000_TX_DESC(*tx_ring, i);
4880 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4881 tx_desc->lower.data =
4882 cpu_to_le32(txd_lower | buffer_info->length);
4883 tx_desc->upper.data = cpu_to_le32(txd_upper);
4884
4885 i++;
4886 if (i == tx_ring->count)
4887 i = 0;
36b973df 4888 } while (--count > 0);
bc7f75fa
AK		 4889
4890 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4891
ad68076e
BA		 4892 /*
4893 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4894 * know there are new descriptors to fetch. (Only
4895 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4896 * such as IA-64).
4897 */
bc7f75fa
AK		 4898 wmb();
4899
4900 tx_ring->next_to_use = i;
c6e7f51e
BA		 4901
4902 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4903 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4904 else
c5083cf6 4905 writel(i, tx_ring->tail);
c6e7f51e 4906
ad68076e
BA		 4907 /*
4908 * we need this if more than one processor can write to our tail
4909 * at a time, it synchronizes IO on IA64/Altix systems
4910 */
bc7f75fa
AK		 4911 mmiowb();
4912}
4913
4914#define MINIMUM_DHCP_PACKET_SIZE 282
4915static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4916 struct sk_buff *skb)
4917{
4918 struct e1000_hw *hw = &adapter->hw;
4919 u16 length, offset;
4920
4921 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4922 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4923 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4924 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4925 return 0;
4926 }
4927
4928 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4929 return 0;
4930
4931 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4932 return 0;
4933
4934 {
4935 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4936 struct udphdr *udp;
4937
4938 if (ip->protocol != IPPROTO_UDP)
4939 return 0;
4940
4941 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4942 if (ntohs(udp->dest) != 67)
4943 return 0;
4944
4945 offset = (u8 *)udp + 8 - skb->data;
4946 length = skb->len - offset;
4947 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4948 }
4949
4950 return 0;
4951}
4952
55aa6985 4953static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4954{
55aa6985 4955 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4956
55aa6985 4957 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4958 /*
4959 * Herbert's original patch had:
bc7f75fa 4960 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4961 * but since that doesn't exist yet, just open code it.
4962 */
bc7f75fa
AK		 4963 smp_mb();
4964
ad68076e
BA		 4965 /*
4966 * We need to check again in a case another CPU has just
4967 * made room available.
4968 */
55aa6985 4969 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4970 return -EBUSY;
4971
4972 /* A reprieve! */
55aa6985 4973 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 4974 ++adapter->restart_queue;
4975 return 0;
4976}
4977
55aa6985 4978static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4979{
55aa6985 4980 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 4981 return 0;
55aa6985 4982 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 4983}
4984
0e15df49 4985#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 4986static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4987 struct net_device *netdev)
bc7f75fa
AK		 4988{
4989 struct e1000_adapter *adapter = netdev_priv(netdev);
4990 struct e1000_ring *tx_ring = adapter->tx_ring;
4991 unsigned int first;
4992 unsigned int max_per_txd = E1000_MAX_PER_TXD;
4993 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
4994 unsigned int tx_flags = 0;
e743d313 4995 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4996 unsigned int nr_frags;
4997 unsigned int mss;
bc7f75fa
AK		 4998 int count = 0;
4999 int tso;
5000 unsigned int f;
bc7f75fa
AK		 5001
5002 if (test_bit(__E1000_DOWN, &adapter->state)) {
5003 dev_kfree_skb_any(skb);
5004 return NETDEV_TX_OK;
5005 }
5006
5007 if (skb->len <= 0) {
5008 dev_kfree_skb_any(skb);
5009 return NETDEV_TX_OK;
5010 }
5011
5012 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5013 /*
5014 * The controller does a simple calculation to
bc7f75fa
AK		 5015 * make sure there is enough room in the FIFO before
5016 * initiating the DMA for each buffer. The calc is:
5017 * 4 = ceil(buffer len/mss). To make sure we don't
5018 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5019 * drops.
5020 */
bc7f75fa
AK		 5021 if (mss) {
5022 u8 hdr_len;
5023 max_per_txd = min(mss << 2, max_per_txd);
5024 max_txd_pwr = fls(max_per_txd) - 1;
5025
ad68076e
BA		 5026 /*
5027 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5028 * points to just header, pull a few bytes of payload from
5029 * frags into skb->data
5030 */
bc7f75fa 5031 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5032 /*
5033 * we do this workaround for ES2LAN, but it is un-necessary,
5034 * avoiding it could save a lot of cycles
5035 */
4e6c709c 5036 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5037 unsigned int pull_size;
5038
a2a5b323 5039 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5040 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5041 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5042 dev_kfree_skb_any(skb);
5043 return NETDEV_TX_OK;
5044 }
e743d313 5045 len = skb_headlen(skb);
bc7f75fa
AK		 5046 }
5047 }
5048
5049 /* reserve a descriptor for the offload context */
5050 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5051 count++;
5052 count++;
5053
5054 count += TXD_USE_COUNT(len, max_txd_pwr);
5055
5056 nr_frags = skb_shinfo(skb)->nr_frags;
5057 for (f = 0; f < nr_frags; f++)
9e903e08 5058 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5059 max_txd_pwr);
5060
5061 if (adapter->hw.mac.tx_pkt_filtering)
5062 e1000_transfer_dhcp_info(adapter, skb);
5063
ad68076e
BA		 5064 /*
5065 * need: count + 2 desc gap to keep tail from touching
5066 * head, otherwise try next time
5067 */
55aa6985 5068 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5069 return NETDEV_TX_BUSY;
bc7f75fa 5070
eab6d18d 5071 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5072 tx_flags |= E1000_TX_FLAGS_VLAN;
5073 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5074 }
5075
5076 first = tx_ring->next_to_use;
5077
55aa6985 5078 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5079 if (tso < 0) {
5080 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5081 return NETDEV_TX_OK;
5082 }
5083
5084 if (tso)
5085 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5086 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5087 tx_flags |= E1000_TX_FLAGS_CSUM;
5088
ad68076e
BA		 5089 /*
5090 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5091 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5092 * no longer assume, we must.
5093 */
bc7f75fa
AK		 5094 if (skb->protocol == htons(ETH_P_IP))
5095 tx_flags |= E1000_TX_FLAGS_IPV4;
5096
25985edc 5097 /* if count is 0 then mapping error has occurred */
55aa6985 5098 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5099 if (count) {
3f0cfa3b 5100 netdev_sent_queue(netdev, skb->len);
55aa6985 5101 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5102 /* Make sure there is space in the ring for the next send. */
55aa6985 5103 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5104
5105 } else {
bc7f75fa 5106 dev_kfree_skb_any(skb);
1b7719c4
AD		 5107 tx_ring->buffer_info[first].time_stamp = 0;
5108 tx_ring->next_to_use = first;
bc7f75fa
AK		 5109 }
5110
bc7f75fa
AK		 5111 return NETDEV_TX_OK;
5112}
5113
5114/**
5115 * e1000_tx_timeout - Respond to a Tx Hang
5116 * @netdev: network interface device structure
5117 **/
5118static void e1000_tx_timeout(struct net_device *netdev)
5119{
5120 struct e1000_adapter *adapter = netdev_priv(netdev);
5121
5122 /* Do the reset outside of interrupt context */
5123 adapter->tx_timeout_count++;
5124 schedule_work(&adapter->reset_task);
5125}
5126
5127static void e1000_reset_task(struct work_struct *work)
5128{
5129 struct e1000_adapter *adapter;
5130 adapter = container_of(work, struct e1000_adapter, reset_task);
5131
615b32af
JB		 5132 /* don't run the task if already down */
5133 if (test_bit(__E1000_DOWN, &adapter->state))
5134 return;
5135
affa9dfb
CW		 5136 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5137 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5138 e1000e_dump(adapter);
5139 e_err("Reset adapter\n");
5140 }
bc7f75fa
AK		 5141 e1000e_reinit_locked(adapter);
5142}
5143
5144/**
67fd4fcb 5145 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5146 * @netdev: network interface device structure
67fd4fcb 5147 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5148 *
5149 * Returns the address of the device statistics structure.
bc7f75fa 5150 **/
67fd4fcb
JK		 5151struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5152 struct rtnl_link_stats64 *stats)
bc7f75fa 5153{
67fd4fcb
JK		 5154 struct e1000_adapter *adapter = netdev_priv(netdev);
5155
5156 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5157 spin_lock(&adapter->stats64_lock);
5158 e1000e_update_stats(adapter);
5159 /* Fill out the OS statistics structure */
5160 stats->rx_bytes = adapter->stats.gorc;
5161 stats->rx_packets = adapter->stats.gprc;
5162 stats->tx_bytes = adapter->stats.gotc;
5163 stats->tx_packets = adapter->stats.gptc;
5164 stats->multicast = adapter->stats.mprc;
5165 stats->collisions = adapter->stats.colc;
5166
5167 /* Rx Errors */
5168
5169 /*
5170 * RLEC on some newer hardware can be incorrect so build
5171 * our own version based on RUC and ROC
5172 */
5173 stats->rx_errors = adapter->stats.rxerrc +
5174 adapter->stats.crcerrs + adapter->stats.algnerrc +
5175 adapter->stats.ruc + adapter->stats.roc +
5176 adapter->stats.cexterr;
5177 stats->rx_length_errors = adapter->stats.ruc +
5178 adapter->stats.roc;
5179 stats->rx_crc_errors = adapter->stats.crcerrs;
5180 stats->rx_frame_errors = adapter->stats.algnerrc;
5181 stats->rx_missed_errors = adapter->stats.mpc;
5182
5183 /* Tx Errors */
5184 stats->tx_errors = adapter->stats.ecol +
5185 adapter->stats.latecol;
5186 stats->tx_aborted_errors = adapter->stats.ecol;
5187 stats->tx_window_errors = adapter->stats.latecol;
5188 stats->tx_carrier_errors = adapter->stats.tncrs;
5189
5190 /* Tx Dropped needs to be maintained elsewhere */
5191
5192 spin_unlock(&adapter->stats64_lock);
5193 return stats;
bc7f75fa
AK		 5194}
5195
5196/**
5197 * e1000_change_mtu - Change the Maximum Transfer Unit
5198 * @netdev: network interface device structure
5199 * @new_mtu: new value for maximum frame size
5200 *
5201 * Returns 0 on success, negative on failure
5202 **/
5203static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5204{
5205 struct e1000_adapter *adapter = netdev_priv(netdev);
5206 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5207
2adc55c9 5208 /* Jumbo frame support */
70495a50
BA		 5209 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5210 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5211 e_err("Jumbo Frames not supported.\n");
5212 return -EINVAL;
5213 }
5214
5215 /*
5216 * IP payload checksum (enabled with jumbos/packet-split when
5217 * Rx checksum is enabled) and generation of RSS hash is
5218 * mutually exclusive in the hardware.
5219 */
5220 if ((netdev->features & NETIF_F_RXCSUM) &&
5221 (netdev->features & NETIF_F_RXHASH)) {
5222 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5223 return -EINVAL;
5224 }
bc7f75fa
AK		 5225 }
5226
2adc55c9
BA		 5227 /* Supported frame sizes */
5228 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5229 (max_frame > adapter->max_hw_frame_size)) {
5230 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5231 return -EINVAL;
5232 }
5233
a1ce6473
BA		 5234 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5235 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5236 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5237 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5238 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5239 return -EINVAL;
5240 }
5241
6f461f6c
BA		 5242 /* 82573 Errata 17 */
5243 if (((adapter->hw.mac.type == e1000_82573) ||
5244 (adapter->hw.mac.type == e1000_82574)) &&
5245 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5246 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5247 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5248 }
5249
bc7f75fa 5250 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5251 usleep_range(1000, 2000);
610c9928 5252 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5253 adapter->max_frame_size = max_frame;
610c9928
BA		 5254 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5255 netdev->mtu = new_mtu;
bc7f75fa
AK		 5256 if (netif_running(netdev))
5257 e1000e_down(adapter);
5258
ad68076e
BA		 5259 /*
5260 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5261 * means we reserve 2 more, this pushes us to allocate from the next
5262 * larger slab size.
ad68076e 5263 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5264 * However with the new *_jumbo_rx* routines, jumbo receives will use
5265 * fragmented skbs
ad68076e 5266 */
bc7f75fa 5267
9926146b 5268 if (max_frame <= 2048)
bc7f75fa
AK		 5269 adapter->rx_buffer_len = 2048;
5270 else
5271 adapter->rx_buffer_len = 4096;
5272
5273 /* adjust allocation if LPE protects us, and we aren't using SBP */
5274 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5275 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5276 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5277 + ETH_FCS_LEN;
bc7f75fa 5278
bc7f75fa
AK		 5279 if (netif_running(netdev))
5280 e1000e_up(adapter);
5281 else
5282 e1000e_reset(adapter);
5283
5284 clear_bit(__E1000_RESETTING, &adapter->state);
5285
5286 return 0;
5287}
5288
5289static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5290 int cmd)
5291{
5292 struct e1000_adapter *adapter = netdev_priv(netdev);
5293 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5294
318a94d6 5295 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5296 return -EOPNOTSUPP;
5297
5298 switch (cmd) {
5299 case SIOCGMIIPHY:
5300 data->phy_id = adapter->hw.phy.addr;
5301 break;
5302 case SIOCGMIIREG:
b16a002e
BA		 5303 e1000_phy_read_status(adapter);
5304
7c25769f
BA		 5305 switch (data->reg_num & 0x1F) {
5306 case MII_BMCR:
5307 data->val_out = adapter->phy_regs.bmcr;
5308 break;
5309 case MII_BMSR:
5310 data->val_out = adapter->phy_regs.bmsr;
5311 break;
5312 case MII_PHYSID1:
5313 data->val_out = (adapter->hw.phy.id >> 16);
5314 break;
5315 case MII_PHYSID2:
5316 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5317 break;
5318 case MII_ADVERTISE:
5319 data->val_out = adapter->phy_regs.advertise;
5320 break;
5321 case MII_LPA:
5322 data->val_out = adapter->phy_regs.lpa;
5323 break;
5324 case MII_EXPANSION:
5325 data->val_out = adapter->phy_regs.expansion;
5326 break;
5327 case MII_CTRL1000:
5328 data->val_out = adapter->phy_regs.ctrl1000;
5329 break;
5330 case MII_STAT1000:
5331 data->val_out = adapter->phy_regs.stat1000;
5332 break;
5333 case MII_ESTATUS:
5334 data->val_out = adapter->phy_regs.estatus;
5335 break;
5336 default:
bc7f75fa
AK		 5337 return -EIO;
5338 }
bc7f75fa
AK		 5339 break;
5340 case SIOCSMIIREG:
5341 default:
5342 return -EOPNOTSUPP;
5343 }
5344 return 0;
5345}
5346
5347static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5348{
5349 switch (cmd) {
5350 case SIOCGMIIPHY:
5351 case SIOCGMIIREG:
5352 case SIOCSMIIREG:
5353 return e1000_mii_ioctl(netdev, ifr, cmd);
5354 default:
5355 return -EOPNOTSUPP;
5356 }
5357}
5358
a4f58f54
BA		 5359static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5360{
5361 struct e1000_hw *hw = &adapter->hw;
5362 u32 i, mac_reg;
2b6b168d 5363 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5364 int retval = 0;
5365
5366 /* copy MAC RARs to PHY RARs */
d3738bb8 5367 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5368
2b6b168d
BA		 5369 retval = hw->phy.ops.acquire(hw);
5370 if (retval) {
5371 e_err("Could not acquire PHY\n");
5372 return retval;
5373 }
5374
5375 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5376 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5377 if (retval)
75ce1532 5378 goto release;
2b6b168d
BA		 5379
5380 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5381 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5382 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5383 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5384 (u16)(mac_reg & 0xFFFF));
5385 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5386 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5387 }
5388
5389 /* configure PHY Rx Control register */
2b6b168d 5390 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5391 mac_reg = er32(RCTL);
5392 if (mac_reg & E1000_RCTL_UPE)
5393 phy_reg |= BM_RCTL_UPE;
5394 if (mac_reg & E1000_RCTL_MPE)
5395 phy_reg |= BM_RCTL_MPE;
5396 phy_reg &= ~(BM_RCTL_MO_MASK);
5397 if (mac_reg & E1000_RCTL_MO_3)
5398 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5399 << BM_RCTL_MO_SHIFT);
5400 if (mac_reg & E1000_RCTL_BAM)
5401 phy_reg |= BM_RCTL_BAM;
5402 if (mac_reg & E1000_RCTL_PMCF)
5403 phy_reg |= BM_RCTL_PMCF;
5404 mac_reg = er32(CTRL);
5405 if (mac_reg & E1000_CTRL_RFCE)
5406 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5407 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5408
5409 /* enable PHY wakeup in MAC register */
5410 ew32(WUFC, wufc);
5411 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5412
5413 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5414 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5415 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5416
5417 /* activate PHY wakeup */
2b6b168d
BA		 5418 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5419 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5420 if (retval)
5421 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5422release:
94d8186a 5423 hw->phy.ops.release(hw);
a4f58f54
BA		 5424
5425 return retval;
5426}
5427
23606cf5
RW		 5428static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5429 bool runtime)
bc7f75fa
AK		 5430{
5431 struct net_device *netdev = pci_get_drvdata(pdev);
5432 struct e1000_adapter *adapter = netdev_priv(netdev);
5433 struct e1000_hw *hw = &adapter->hw;
5434 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5435 /* Runtime suspend should only enable wakeup for link changes */
5436 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5437 int retval = 0;
5438
5439 netif_device_detach(netdev);
5440
5441 if (netif_running(netdev)) {
5442 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5443 e1000e_down(adapter);
5444 e1000_free_irq(adapter);
5445 }
4662e82b 5446 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5447
5448 retval = pci_save_state(pdev);
5449 if (retval)
5450 return retval;
5451
5452 status = er32(STATUS);
5453 if (status & E1000_STATUS_LU)
5454 wufc &= ~E1000_WUFC_LNKC;
5455
5456 if (wufc) {
5457 e1000_setup_rctl(adapter);
ef9b965a 5458 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5459
5460 /* turn on all-multi mode if wake on multicast is enabled */
5461 if (wufc & E1000_WUFC_MC) {
5462 rctl = er32(RCTL);
5463 rctl |= E1000_RCTL_MPE;
5464 ew32(RCTL, rctl);
5465 }
5466
5467 ctrl = er32(CTRL);
5468 /* advertise wake from D3Cold */
5469 #define E1000_CTRL_ADVD3WUC 0x00100000
5470 /* phy power management enable */
5471 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5472 ctrl |= E1000_CTRL_ADVD3WUC;
5473 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5474 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5475 ew32(CTRL, ctrl);
5476
318a94d6
JK		 5477 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5478 adapter->hw.phy.media_type ==
5479 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5480 /* keep the laser running in D3 */
5481 ctrl_ext = er32(CTRL_EXT);
93a23f48 5482 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5483 ew32(CTRL_EXT, ctrl_ext);
5484 }
5485
97ac8cae 5486 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5487 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5488
bc7f75fa
AK		 5489 /* Allow time for pending master requests to run */
5490 e1000e_disable_pcie_master(&adapter->hw);
5491
82776a4b 5492 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5493 /* enable wakeup by the PHY */
5494 retval = e1000_init_phy_wakeup(adapter, wufc);
5495 if (retval)
5496 return retval;
5497 } else {
5498 /* enable wakeup by the MAC */
5499 ew32(WUFC, wufc);
5500 ew32(WUC, E1000_WUC_PME_EN);
5501 }
bc7f75fa
AK		 5502 } else {
5503 ew32(WUC, 0);
5504 ew32(WUFC, 0);
bc7f75fa
AK		 5505 }
5506
4f9de721
RW		 5507 *enable_wake = !!wufc;
5508
bc7f75fa 5509 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5510 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5511 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5512 *enable_wake = true;
bc7f75fa
AK		 5513
5514 if (adapter->hw.phy.type == e1000_phy_igp_3)
5515 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5516
ad68076e
BA		 5517 /*
5518 * Release control of h/w to f/w. If f/w is AMT enabled, this
5519 * would have already happened in close and is redundant.
5520 */
31dbe5b4 5521 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5522
5523 pci_disable_device(pdev);
5524
4f9de721
RW		 5525 return 0;
5526}
5527
5528static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5529{
5530 if (sleep && wake) {
5531 pci_prepare_to_sleep(pdev);
5532 return;
5533 }
5534
5535 pci_wake_from_d3(pdev, wake);
5536 pci_set_power_state(pdev, PCI_D3hot);
5537}
5538
5539static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5540 bool wake)
5541{
5542 struct net_device *netdev = pci_get_drvdata(pdev);
5543 struct e1000_adapter *adapter = netdev_priv(netdev);
5544
005cbdfc
AD		 5545 /*
5546 * The pci-e switch on some quad port adapters will report a
5547 * correctable error when the MAC transitions from D0 to D3. To
5548 * prevent this we need to mask off the correctable errors on the
5549 * downstream port of the pci-e switch.
5550 */
5551 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5552 struct pci_dev *us_dev = pdev->bus->self;
353064de 5553 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5554 u16 devctl;
5555
5556 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5557 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5558 (devctl & ~PCI_EXP_DEVCTL_CERE));
5559
4f9de721 5560 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5561
5562 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5563 } else {
4f9de721 5564 e1000_power_off(pdev, sleep, wake);
005cbdfc 5565 }
bc7f75fa
AK		 5566}
5567
6f461f6c
BA		 5568#ifdef CONFIG_PCIEASPM
5569static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5570{
9f728f53 5571 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5572}
5573#else
5574static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5575{
5576 int pos;
6f461f6c 5577 u16 reg16;
1eae4eb2
AK		 5578
5579 /*
6f461f6c
BA		 5580 * Both device and parent should have the same ASPM setting.
5581 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5582 */
6f461f6c
BA		 5583 pos = pci_pcie_cap(pdev);
5584 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5585 reg16 &= ~state;
5586 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5587
0c75ba22
AB		 5588 if (!pdev->bus->self)
5589 return;
5590
6f461f6c
BA		 5591 pos = pci_pcie_cap(pdev->bus->self);
5592 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5593 reg16 &= ~state;
5594 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5595}
5596#endif
78cd29d5 5597static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5598{
5599 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5600 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5601 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5602
5603 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5604}
5605
aa338601 5606#ifdef CONFIG_PM
23606cf5 5607static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5608{
23606cf5 5609 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5610}
5611
23606cf5 5612static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5613{
5614 struct net_device *netdev = pci_get_drvdata(pdev);
5615 struct e1000_adapter *adapter = netdev_priv(netdev);
5616 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5617 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5618 u32 err;
5619
78cd29d5
BA		 5620 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5621 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5622 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5623 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5624 if (aspm_disable_flag)
5625 e1000e_disable_aspm(pdev, aspm_disable_flag);
5626
bc7f75fa
AK		 5627 pci_set_power_state(pdev, PCI_D0);
5628 pci_restore_state(pdev);
28b8f04a 5629 pci_save_state(pdev);
6e4f6f6b 5630
4662e82b 5631 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5632 if (netif_running(netdev)) {
5633 err = e1000_request_irq(adapter);
5634 if (err)
5635 return err;
5636 }
5637
99730e4c
BA		 5638 if (hw->mac.type == e1000_pch2lan)
5639 e1000_resume_workarounds_pchlan(&adapter->hw);
5640
bc7f75fa 5641 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5642
5643 /* report the system wakeup cause from S3/S4 */
5644 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5645 u16 phy_data;
5646
5647 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5648 if (phy_data) {
5649 e_info("PHY Wakeup cause - %s\n",
5650 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5651 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5652 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5653 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5654 phy_data & E1000_WUS_LNKC ?
5655 "Link Status Change" : "other");
a4f58f54
BA		 5656 }
5657 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5658 } else {
5659 u32 wus = er32(WUS);
5660 if (wus) {
5661 e_info("MAC Wakeup cause - %s\n",
5662 wus & E1000_WUS_EX ? "Unicast Packet" :
5663 wus & E1000_WUS_MC ? "Multicast Packet" :
5664 wus & E1000_WUS_BC ? "Broadcast Packet" :
5665 wus & E1000_WUS_MAG ? "Magic Packet" :
5666 wus & E1000_WUS_LNKC ? "Link Status Change" :
5667 "other");
5668 }
5669 ew32(WUS, ~0);
5670 }
5671
bc7f75fa 5672 e1000e_reset(adapter);
bc7f75fa 5673
cd791618 5674 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5675
5676 if (netif_running(netdev))
5677 e1000e_up(adapter);
5678
5679 netif_device_attach(netdev);
5680
ad68076e
BA		 5681 /*
5682 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5683 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5684 * under the control of the driver.
5685 */
c43bc57e 5686 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5687 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5688
5689 return 0;
5690}
23606cf5 5691
a0340162
RW		 5692#ifdef CONFIG_PM_SLEEP
5693static int e1000_suspend(struct device *dev)
5694{
5695 struct pci_dev *pdev = to_pci_dev(dev);
5696 int retval;
5697 bool wake;
5698
5699 retval = __e1000_shutdown(pdev, &wake, false);
5700 if (!retval)
5701 e1000_complete_shutdown(pdev, true, wake);
5702
5703 return retval;
5704}
5705
23606cf5
RW		 5706static int e1000_resume(struct device *dev)
5707{
5708 struct pci_dev *pdev = to_pci_dev(dev);
5709 struct net_device *netdev = pci_get_drvdata(pdev);
5710 struct e1000_adapter *adapter = netdev_priv(netdev);
5711
5712 if (e1000e_pm_ready(adapter))
5713 adapter->idle_check = true;
5714
5715 return __e1000_resume(pdev);
5716}
a0340162
RW		 5717#endif /* CONFIG_PM_SLEEP */
5718
5719#ifdef CONFIG_PM_RUNTIME
5720static int e1000_runtime_suspend(struct device *dev)
5721{
5722 struct pci_dev *pdev = to_pci_dev(dev);
5723 struct net_device *netdev = pci_get_drvdata(pdev);
5724 struct e1000_adapter *adapter = netdev_priv(netdev);
5725
5726 if (e1000e_pm_ready(adapter)) {
5727 bool wake;
5728
5729 __e1000_shutdown(pdev, &wake, true);
5730 }
5731
5732 return 0;
5733}
5734
5735static int e1000_idle(struct device *dev)
5736{
5737 struct pci_dev *pdev = to_pci_dev(dev);
5738 struct net_device *netdev = pci_get_drvdata(pdev);
5739 struct e1000_adapter *adapter = netdev_priv(netdev);
5740
5741 if (!e1000e_pm_ready(adapter))
5742 return 0;
5743
5744 if (adapter->idle_check) {
5745 adapter->idle_check = false;
5746 if (!e1000e_has_link(adapter))
5747 pm_schedule_suspend(dev, MSEC_PER_SEC);
5748 }
5749
5750 return -EBUSY;
5751}
23606cf5
RW		 5752
5753static int e1000_runtime_resume(struct device *dev)
5754{
5755 struct pci_dev *pdev = to_pci_dev(dev);
5756 struct net_device *netdev = pci_get_drvdata(pdev);
5757 struct e1000_adapter *adapter = netdev_priv(netdev);
5758
5759 if (!e1000e_pm_ready(adapter))
5760 return 0;
5761
5762 adapter->idle_check = !dev->power.runtime_auto;
5763 return __e1000_resume(pdev);
5764}
a0340162 5765#endif /* CONFIG_PM_RUNTIME */
aa338601 5766#endif /* CONFIG_PM */
bc7f75fa
AK		 5767
5768static void e1000_shutdown(struct pci_dev *pdev)
5769{
4f9de721
RW		 5770 bool wake = false;
5771
23606cf5 5772 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5773
5774 if (system_state == SYSTEM_POWER_OFF)
5775 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5776}
5777
5778#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5779
5780static irqreturn_t e1000_intr_msix(int irq, void *data)
5781{
5782 struct net_device *netdev = data;
5783 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5784
5785 if (adapter->msix_entries) {
90da0669
BA		 5786 int vector, msix_irq;
5787
147b2c8c
DD		 5788 vector = 0;
5789 msix_irq = adapter->msix_entries[vector].vector;
5790 disable_irq(msix_irq);
5791 e1000_intr_msix_rx(msix_irq, netdev);
5792 enable_irq(msix_irq);
5793
5794 vector++;
5795 msix_irq = adapter->msix_entries[vector].vector;
5796 disable_irq(msix_irq);
5797 e1000_intr_msix_tx(msix_irq, netdev);
5798 enable_irq(msix_irq);
5799
5800 vector++;
5801 msix_irq = adapter->msix_entries[vector].vector;
5802 disable_irq(msix_irq);
5803 e1000_msix_other(msix_irq, netdev);
5804 enable_irq(msix_irq);
5805 }
5806
5807 return IRQ_HANDLED;
5808}
5809
bc7f75fa
AK		 5810/*
5811 * Polling 'interrupt' - used by things like netconsole to send skbs
5812 * without having to re-enable interrupts. It's not called while
5813 * the interrupt routine is executing.
5814 */
5815static void e1000_netpoll(struct net_device *netdev)
5816{
5817 struct e1000_adapter *adapter = netdev_priv(netdev);
5818
147b2c8c
DD		 5819 switch (adapter->int_mode) {
5820 case E1000E_INT_MODE_MSIX:
5821 e1000_intr_msix(adapter->pdev->irq, netdev);
5822 break;
5823 case E1000E_INT_MODE_MSI:
5824 disable_irq(adapter->pdev->irq);
5825 e1000_intr_msi(adapter->pdev->irq, netdev);
5826 enable_irq(adapter->pdev->irq);
5827 break;
5828 default: /* E1000E_INT_MODE_LEGACY */
5829 disable_irq(adapter->pdev->irq);
5830 e1000_intr(adapter->pdev->irq, netdev);
5831 enable_irq(adapter->pdev->irq);
5832 break;
5833 }
bc7f75fa
AK		 5834}
5835#endif
5836
5837/**
5838 * e1000_io_error_detected - called when PCI error is detected
5839 * @pdev: Pointer to PCI device
5840 * @state: The current pci connection state
5841 *
5842 * This function is called after a PCI bus error affecting
5843 * this device has been detected.
5844 */
5845static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5846 pci_channel_state_t state)
5847{
5848 struct net_device *netdev = pci_get_drvdata(pdev);
5849 struct e1000_adapter *adapter = netdev_priv(netdev);
5850
5851 netif_device_detach(netdev);
5852
c93b5a76
MM		 5853 if (state == pci_channel_io_perm_failure)
5854 return PCI_ERS_RESULT_DISCONNECT;
5855
bc7f75fa
AK		 5856 if (netif_running(netdev))
5857 e1000e_down(adapter);
5858 pci_disable_device(pdev);
5859
5860 /* Request a slot slot reset. */
5861 return PCI_ERS_RESULT_NEED_RESET;
5862}
5863
5864/**
5865 * e1000_io_slot_reset - called after the pci bus has been reset.
5866 * @pdev: Pointer to PCI device
5867 *
5868 * Restart the card from scratch, as if from a cold-boot. Implementation
5869 * resembles the first-half of the e1000_resume routine.
5870 */
5871static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5872{
5873 struct net_device *netdev = pci_get_drvdata(pdev);
5874 struct e1000_adapter *adapter = netdev_priv(netdev);
5875 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5876 u16 aspm_disable_flag = 0;
6e4f6f6b 5877 int err;
111b9dc5 5878 pci_ers_result_t result;
bc7f75fa 5879
78cd29d5
BA		 5880 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5881 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5882 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5883 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5884 if (aspm_disable_flag)
5885 e1000e_disable_aspm(pdev, aspm_disable_flag);
5886
f0f422e5 5887 err = pci_enable_device_mem(pdev);
6e4f6f6b 5888 if (err) {
bc7f75fa
AK		 5889 dev_err(&pdev->dev,
5890 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5891 result = PCI_ERS_RESULT_DISCONNECT;
5892 } else {
5893 pci_set_master(pdev);
23606cf5 5894 pdev->state_saved = true;
111b9dc5 5895 pci_restore_state(pdev);
bc7f75fa 5896
111b9dc5
JB		 5897 pci_enable_wake(pdev, PCI_D3hot, 0);
5898 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5899
111b9dc5
JB		 5900 e1000e_reset(adapter);
5901 ew32(WUS, ~0);
5902 result = PCI_ERS_RESULT_RECOVERED;
5903 }
bc7f75fa 5904
111b9dc5
JB		 5905 pci_cleanup_aer_uncorrect_error_status(pdev);
5906
5907 return result;
bc7f75fa
AK		 5908}
5909
5910/**
5911 * e1000_io_resume - called when traffic can start flowing again.
5912 * @pdev: Pointer to PCI device
5913 *
5914 * This callback is called when the error recovery driver tells us that
5915 * its OK to resume normal operation. Implementation resembles the
5916 * second-half of the e1000_resume routine.
5917 */
5918static void e1000_io_resume(struct pci_dev *pdev)
5919{
5920 struct net_device *netdev = pci_get_drvdata(pdev);
5921 struct e1000_adapter *adapter = netdev_priv(netdev);
5922
cd791618 5923 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5924
5925 if (netif_running(netdev)) {
5926 if (e1000e_up(adapter)) {
5927 dev_err(&pdev->dev,
5928 "can't bring device back up after reset\n");
5929 return;
5930 }
5931 }
5932
5933 netif_device_attach(netdev);
5934
ad68076e
BA		 5935 /*
5936 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5937 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5938 * under the control of the driver.
5939 */
c43bc57e 5940 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5941 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5942
5943}
5944
5945static void e1000_print_device_info(struct e1000_adapter *adapter)
5946{
5947 struct e1000_hw *hw = &adapter->hw;
5948 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5949 u32 ret_val;
5950 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5951
5952 /* print bus type/speed/width info */
a5cc7642 5953 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5954 /* bus width */
5955 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5956 "Width x1"),
5957 /* MAC address */
7c510e4b 5958 netdev->dev_addr);
44defeb3
JK		 5959 e_info("Intel(R) PRO/%s Network Connection\n",
5960 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5961 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5962 E1000_PBANUM_LENGTH);
5963 if (ret_val)
f2315bf1 5964 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5965 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5966 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5967}
5968
10aa4c04
AK		 5969static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5970{
5971 struct e1000_hw *hw = &adapter->hw;
5972 int ret_val;
5973 u16 buf = 0;
5974
5975 if (hw->mac.type != e1000_82573)
5976 return;
5977
5978 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 5979 le16_to_cpus(&buf);
5980 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 5981 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5982 dev_warn(&adapter->pdev->dev,
5983 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5984 }
10aa4c04
AK		 5985}
5986
c8f44aff 5987static int e1000_set_features(struct net_device *netdev,
70495a50 5988 netdev_features_t features)
dc221294
BA		 5989{
5990 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5991 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5992
5993 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5994 adapter->flags |= FLAG_TSO_FORCE;
5995
5996 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
0184039a 5997 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS)))
dc221294
BA		 5998 return 0;
5999
70495a50
BA		 6000 /*
6001 * IP payload checksum (enabled with jumbos/packet-split when Rx
6002 * checksum is enabled) and generation of RSS hash is mutually
6003 * exclusive in the hardware.
6004 */
6005 if (adapter->rx_ps_pages &&
6006 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6007 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6008 return -EINVAL;
6009 }
6010
0184039a
BG		 6011 if (changed & NETIF_F_RXFCS) {
6012 if (features & NETIF_F_RXFCS) {
6013 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6014 } else {
6015 /* We need to take it back to defaults, which might mean
6016 * stripping is still disabled at the adapter level.
6017 */
6018 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6019 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6020 else
6021 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6022 }
6023 }
6024
70495a50
BA		 6025 netdev->features = features;
6026
dc221294
BA		 6027 if (netif_running(netdev))
6028 e1000e_reinit_locked(adapter);
6029 else
6030 e1000e_reset(adapter);
6031
6032 return 0;
6033}
6034
651c2466
SH		 6035static const struct net_device_ops e1000e_netdev_ops = {
6036 .ndo_open = e1000_open,
6037 .ndo_stop = e1000_close,
00829823 6038 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6039 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6040 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6041 .ndo_set_mac_address = e1000_set_mac,
6042 .ndo_change_mtu = e1000_change_mtu,
6043 .ndo_do_ioctl = e1000_ioctl,
6044 .ndo_tx_timeout = e1000_tx_timeout,
6045 .ndo_validate_addr = eth_validate_addr,
6046
651c2466
SH		 6047 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6048 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6049#ifdef CONFIG_NET_POLL_CONTROLLER
6050 .ndo_poll_controller = e1000_netpoll,
6051#endif
dc221294 6052 .ndo_set_features = e1000_set_features,
651c2466
SH		 6053};
6054
bc7f75fa
AK		 6055/**
6056 * e1000_probe - Device Initialization Routine
6057 * @pdev: PCI device information struct
6058 * @ent: entry in e1000_pci_tbl
6059 *
6060 * Returns 0 on success, negative on failure
6061 *
6062 * e1000_probe initializes an adapter identified by a pci_dev structure.
6063 * The OS initialization, configuring of the adapter private structure,
6064 * and a hardware reset occur.
6065 **/
6066static int __devinit e1000_probe(struct pci_dev *pdev,
6067 const struct pci_device_id *ent)
6068{
6069 struct net_device *netdev;
6070 struct e1000_adapter *adapter;
6071 struct e1000_hw *hw;
6072 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6073 resource_size_t mmio_start, mmio_len;
6074 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 6075
6076 static int cards_found;
78cd29d5 6077 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6078 int i, err, pci_using_dac;
6079 u16 eeprom_data = 0;
6080 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6081
78cd29d5
BA		 6082 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6083 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6084 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6085 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6086 if (aspm_disable_flag)
6087 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6088
f0f422e5 6089 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6090 if (err)
6091 return err;
6092
6093 pci_using_dac = 0;
0be3f55f 6094 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6095 if (!err) {
0be3f55f 6096 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6097 if (!err)
6098 pci_using_dac = 1;
6099 } else {
0be3f55f 6100 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6101 if (err) {
0be3f55f
NN		 6102 err = dma_set_coherent_mask(&pdev->dev,
6103 DMA_BIT_MASK(32));
bc7f75fa 6104 if (err) {
ef456f85 6105 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6106 goto err_dma;
6107 }
6108 }
6109 }
6110
e8de1481 6111 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6112 pci_select_bars(pdev, IORESOURCE_MEM),
6113 e1000e_driver_name);
bc7f75fa
AK		 6114 if (err)
6115 goto err_pci_reg;
6116
68eac460 6117 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6118 pci_enable_pcie_error_reporting(pdev);
68eac460 6119
bc7f75fa 6120 pci_set_master(pdev);
438b365a
BA		 6121 /* PCI config space info */
6122 err = pci_save_state(pdev);
6123 if (err)
6124 goto err_alloc_etherdev;
bc7f75fa
AK		 6125
6126 err = -ENOMEM;
6127 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6128 if (!netdev)
6129 goto err_alloc_etherdev;
6130
bc7f75fa
AK		 6131 SET_NETDEV_DEV(netdev, &pdev->dev);
6132
f85e4dfa
TH		 6133 netdev->irq = pdev->irq;
6134
bc7f75fa
AK		 6135 pci_set_drvdata(pdev, netdev);
6136 adapter = netdev_priv(netdev);
6137 hw = &adapter->hw;
6138 adapter->netdev = netdev;
6139 adapter->pdev = pdev;
6140 adapter->ei = ei;
6141 adapter->pba = ei->pba;
6142 adapter->flags = ei->flags;
eb7c3adb 6143 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6144 adapter->hw.adapter = adapter;
6145 adapter->hw.mac.type = ei->mac;
2adc55c9 6146 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6147 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6148
6149 mmio_start = pci_resource_start(pdev, 0);
6150 mmio_len = pci_resource_len(pdev, 0);
6151
6152 err = -EIO;
6153 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6154 if (!adapter->hw.hw_addr)
6155 goto err_ioremap;
6156
6157 if ((adapter->flags & FLAG_HAS_FLASH) &&
6158 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6159 flash_start = pci_resource_start(pdev, 1);
6160 flash_len = pci_resource_len(pdev, 1);
6161 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6162 if (!adapter->hw.flash_address)
6163 goto err_flashmap;
6164 }
6165
6166 /* construct the net_device struct */
651c2466 6167 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6168 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6169 netdev->watchdog_timeo = 5 * HZ;
6170 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
f2315bf1 6171 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6172
6173 netdev->mem_start = mmio_start;
6174 netdev->mem_end = mmio_start + mmio_len;
6175
6176 adapter->bd_number = cards_found++;
6177
4662e82b
BA		 6178 e1000e_check_options(adapter);
6179
bc7f75fa
AK		 6180 /* setup adapter struct */
6181 err = e1000_sw_init(adapter);
6182 if (err)
6183 goto err_sw_init;
6184
bc7f75fa
AK		 6185 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6186 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6187 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6188
69e3fd8c 6189 err = ei->get_variants(adapter);
bc7f75fa
AK		 6190 if (err)
6191 goto err_hw_init;
6192
4a770358
BA		 6193 if ((adapter->flags & FLAG_IS_ICH) &&
6194 (adapter->flags & FLAG_READ_ONLY_NVM))
6195 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6196
bc7f75fa
AK		 6197 hw->mac.ops.get_bus_info(&adapter->hw);
6198
318a94d6 6199 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6200
6201 /* Copper options */
318a94d6 6202 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6203 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6204 adapter->hw.phy.disable_polarity_correction = 0;
6205 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6206 }
6207
6208 if (e1000_check_reset_block(&adapter->hw))
44defeb3 6209 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6210
dc221294
BA		 6211 /* Set initial default active device features */
6212 netdev->features = (NETIF_F_SG |
6213 NETIF_F_HW_VLAN_RX |
6214 NETIF_F_HW_VLAN_TX |
6215 NETIF_F_TSO |
6216 NETIF_F_TSO6 |
70495a50 6217 NETIF_F_RXHASH |
dc221294
BA		 6218 NETIF_F_RXCSUM |
6219 NETIF_F_HW_CSUM);
6220
6221 /* Set user-changeable features (subset of all device features) */
6222 netdev->hw_features = netdev->features;
0184039a 6223 netdev->hw_features |= NETIF_F_RXFCS;
bc7f75fa
AK		 6224
6225 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6226 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6227
dc221294
BA		 6228 netdev->vlan_features |= (NETIF_F_SG |
6229 NETIF_F_TSO |
6230 NETIF_F_TSO6 |
6231 NETIF_F_HW_CSUM);
a5136e23 6232
ef9b965a
JB		 6233 netdev->priv_flags |= IFF_UNICAST_FLT;
6234
7b872a55 6235 if (pci_using_dac) {
bc7f75fa 6236 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6237 netdev->vlan_features |= NETIF_F_HIGHDMA;
6238 }
bc7f75fa 6239
bc7f75fa
AK		 6240 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6241 adapter->flags |= FLAG_MNG_PT_ENABLED;
6242
ad68076e
BA		 6243 /*
6244 * before reading the NVM, reset the controller to
6245 * put the device in a known good starting state
6246 */
bc7f75fa
AK		 6247 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6248
6249 /*
6250 * systems with ASPM and others may see the checksum fail on the first
6251 * attempt. Let's give it a few tries
6252 */
6253 for (i = 0;; i++) {
6254 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6255 break;
6256 if (i == 2) {
44defeb3 6257 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6258 err = -EIO;
6259 goto err_eeprom;
6260 }
6261 }
6262
10aa4c04
AK		 6263 e1000_eeprom_checks(adapter);
6264
608f8a0d 6265 /* copy the MAC address */
bc7f75fa 6266 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6267 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6268
6269 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6270 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6271
6272 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6273 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6274 err = -EIO;
6275 goto err_eeprom;
6276 }
6277
6278 init_timer(&adapter->watchdog_timer);
c061b18d 6279 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6280 adapter->watchdog_timer.data = (unsigned long) adapter;
6281
6282 init_timer(&adapter->phy_info_timer);
c061b18d 6283 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6284 adapter->phy_info_timer.data = (unsigned long) adapter;
6285
6286 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6287 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6288 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6289 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6290 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6291
bc7f75fa
AK		 6292 /* Initialize link parameters. User can change them with ethtool */
6293 adapter->hw.mac.autoneg = 1;
3db1cd5c 6294 adapter->fc_autoneg = true;
5c48ef3e
BA		 6295 adapter->hw.fc.requested_mode = e1000_fc_default;
6296 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6297 adapter->hw.phy.autoneg_advertised = 0x2f;
6298
6299 /* ring size defaults */
6300 adapter->rx_ring->count = 256;
6301 adapter->tx_ring->count = 256;
6302
6303 /*
6304 * Initial Wake on LAN setting - If APM wake is enabled in
6305 * the EEPROM, enable the ACPI Magic Packet filter
6306 */
6307 if (adapter->flags & FLAG_APME_IN_WUC) {
6308 /* APME bit in EEPROM is mapped to WUC.APME */
6309 eeprom_data = er32(WUC);
6310 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6311 if ((hw->mac.type > e1000_ich10lan) &&
6312 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6313 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6314 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6315 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6316 (adapter->hw.bus.func == 1))
6317 e1000_read_nvm(&adapter->hw,
6318 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6319 else
6320 e1000_read_nvm(&adapter->hw,
6321 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6322 }
6323
6324 /* fetch WoL from EEPROM */
6325 if (eeprom_data & eeprom_apme_mask)
6326 adapter->eeprom_wol |= E1000_WUFC_MAG;
6327
6328 /*
6329 * now that we have the eeprom settings, apply the special cases
6330 * where the eeprom may be wrong or the board simply won't support
6331 * wake on lan on a particular port
6332 */
6333 if (!(adapter->flags & FLAG_HAS_WOL))
6334 adapter->eeprom_wol = 0;
6335
6336 /* initialize the wol settings based on the eeprom settings */
6337 adapter->wol = adapter->eeprom_wol;
6ff68026 6338 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6339
84527590
BA		 6340 /* save off EEPROM version number */
6341 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6342
bc7f75fa
AK		 6343 /* reset the hardware with the new settings */
6344 e1000e_reset(adapter);
6345
ad68076e
BA		 6346 /*
6347 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6348 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6349 * under the control of the driver.
6350 */
c43bc57e 6351 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6352 e1000e_get_hw_control(adapter);
bc7f75fa 6353
f2315bf1 6354 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6355 err = register_netdev(netdev);
6356 if (err)
6357 goto err_register;
6358
9c563d20
JB		 6359 /* carrier off reporting is important to ethtool even BEFORE open */
6360 netif_carrier_off(netdev);
6361
bc7f75fa
AK		 6362 e1000_print_device_info(adapter);
6363
f3ec4f87
AS		 6364 if (pci_dev_run_wake(pdev))
6365 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6366
bc7f75fa
AK		 6367 return 0;
6368
6369err_register:
c43bc57e 6370 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6371 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 6372err_eeprom:
6373 if (!e1000_check_reset_block(&adapter->hw))
6374 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6375err_hw_init:
bc7f75fa
AK		 6376 kfree(adapter->tx_ring);
6377 kfree(adapter->rx_ring);
6378err_sw_init:
c43bc57e
JB		 6379 if (adapter->hw.flash_address)
6380 iounmap(adapter->hw.flash_address);
e82f54ba 6381 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6382err_flashmap:
bc7f75fa
AK		 6383 iounmap(adapter->hw.hw_addr);
6384err_ioremap:
6385 free_netdev(netdev);
6386err_alloc_etherdev:
f0f422e5
BA		 6387 pci_release_selected_regions(pdev,
6388 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6389err_pci_reg:
6390err_dma:
6391 pci_disable_device(pdev);
6392 return err;
6393}
6394
6395/**
6396 * e1000_remove - Device Removal Routine
6397 * @pdev: PCI device information struct
6398 *
6399 * e1000_remove is called by the PCI subsystem to alert the driver
6400 * that it should release a PCI device. The could be caused by a
6401 * Hot-Plug event, or because the driver is going to be removed from
6402 * memory.
6403 **/
6404static void __devexit e1000_remove(struct pci_dev *pdev)
6405{
6406 struct net_device *netdev = pci_get_drvdata(pdev);
6407 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6408 bool down = test_bit(__E1000_DOWN, &adapter->state);
6409
ad68076e 6410 /*
23f333a2
TH		 6411 * The timers may be rescheduled, so explicitly disable them
6412 * from being rescheduled.
ad68076e 6413 */
23606cf5
RW		 6414 if (!down)
6415 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6416 del_timer_sync(&adapter->watchdog_timer);
6417 del_timer_sync(&adapter->phy_info_timer);
6418
41cec6f1
BA		 6419 cancel_work_sync(&adapter->reset_task);
6420 cancel_work_sync(&adapter->watchdog_task);
6421 cancel_work_sync(&adapter->downshift_task);
6422 cancel_work_sync(&adapter->update_phy_task);
6423 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6424
17f208de
BA		 6425 if (!(netdev->flags & IFF_UP))
6426 e1000_power_down_phy(adapter);
6427
23606cf5
RW		 6428 /* Don't lie to e1000_close() down the road. */
6429 if (!down)
6430 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6431 unregister_netdev(netdev);
6432
f3ec4f87
AS		 6433 if (pci_dev_run_wake(pdev))
6434 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6435
ad68076e
BA		 6436 /*
6437 * Release control of h/w to f/w. If f/w is AMT enabled, this
6438 * would have already happened in close and is redundant.
6439 */
31dbe5b4 6440 e1000e_release_hw_control(adapter);
bc7f75fa 6441
4662e82b 6442 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6443 kfree(adapter->tx_ring);
6444 kfree(adapter->rx_ring);
6445
6446 iounmap(adapter->hw.hw_addr);
6447 if (adapter->hw.flash_address)
6448 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6449 pci_release_selected_regions(pdev,
6450 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6451
6452 free_netdev(netdev);
6453
111b9dc5 6454 /* AER disable */
19d5afd4 6455 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6456
bc7f75fa
AK		 6457 pci_disable_device(pdev);
6458}
6459
6460/* PCI Error Recovery (ERS) */
6461static struct pci_error_handlers e1000_err_handler = {
6462 .error_detected = e1000_io_error_detected,
6463 .slot_reset = e1000_io_slot_reset,
6464 .resume = e1000_io_resume,
6465};
6466
a3aa1884 6467static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6477
bc7f75fa
AK		 6478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6482
bc7f75fa
AK		 6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6486
4662e82b 6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6490
bc7f75fa
AK		 6491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6492 board_80003es2lan },
6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6494 board_80003es2lan },
6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6496 board_80003es2lan },
6497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6498 board_80003es2lan },
ad68076e 6499
bc7f75fa
AK		 6500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6508
bc7f75fa
AK		 6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6518
6519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6522
f4187b56
BA		 6523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6526
a4f58f54
BA		 6527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6531
d3738bb8
BA		 6532 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6534
f36bb6ca 6535 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6536};
6537MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6538
aa338601 6539#ifdef CONFIG_PM
23606cf5 6540static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6541 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6542 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6543 e1000_runtime_resume, e1000_idle)
23606cf5 6544};
e50208a0 6545#endif
23606cf5 6546
bc7f75fa
AK		 6547/* PCI Device API Driver */
6548static struct pci_driver e1000_driver = {
6549 .name = e1000e_driver_name,
6550 .id_table = e1000_pci_tbl,
6551 .probe = e1000_probe,
6552 .remove = __devexit_p(e1000_remove),
aa338601 6553#ifdef CONFIG_PM
f36bb6ca
BA		 6554 .driver = {
6555 .pm = &e1000_pm_ops,
6556 },
bc7f75fa
AK		 6557#endif
6558 .shutdown = e1000_shutdown,
6559 .err_handler = &e1000_err_handler
6560};
6561
6562/**
6563 * e1000_init_module - Driver Registration Routine
6564 *
6565 * e1000_init_module is the first routine called when the driver is
6566 * loaded. All it does is register with the PCI subsystem.
6567 **/
6568static int __init e1000_init_module(void)
6569{
6570 int ret;
8544b9f7
BA		 6571 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6572 e1000e_driver_version);
f5e261e6 6573 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6574 ret = pci_register_driver(&e1000_driver);
53ec5498 6575
bc7f75fa
AK		 6576 return ret;
6577}
6578module_init(e1000_init_module);
6579
6580/**
6581 * e1000_exit_module - Driver Exit Cleanup Routine
6582 *
6583 * e1000_exit_module is called just before the driver is removed
6584 * from memory.
6585 **/
6586static void __exit e1000_exit_module(void)
6587{
6588 pci_unregister_driver(&e1000_driver);
6589}
6590module_exit(e1000_exit_module);
6591
6592
6593MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6594MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6595MODULE_LICENSE("GPL");
6596MODULE_VERSION(DRV_VERSION);
6597
6598/* e1000_main.c */
Linux kernel - Deliverables
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