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e1000e: cleanup formatting of static structs
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
bc7f75fa
AK		 45#include <linux/ethtool.h>
46#include <linux/if_vlan.h>
47#include <linux/cpu.h>
48#include <linux/smp.h>
e8db0be1 49#include <linux/pm_qos.h>
23606cf5 50#include <linux/pm_runtime.h>
111b9dc5 51#include <linux/aer.h>
70c71606 52#include <linux/prefetch.h>
bc7f75fa
AK		 53
54#include "e1000.h"
55
b3ccf267 56#define DRV_EXTRAVERSION "-k"
c14c643b 57
9e019901 58#define DRV_VERSION "2.2.14" DRV_EXTRAVERSION
bc7f75fa
AK		 59char e1000e_driver_name[] = "e1000e";
60const char e1000e_driver_version[] = DRV_VERSION;
61
b3f4d599 62#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
63static int debug = -1;
64module_param(debug, int, 0);
65MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66
78cd29d5
BA		 67static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
68
bc7f75fa
AK		 69static const struct e1000_info *e1000_info_tbl[] = {
70 [board_82571] = &e1000_82571_info,
71 [board_82572] = &e1000_82572_info,
72 [board_82573] = &e1000_82573_info,
4662e82b 73 [board_82574] = &e1000_82574_info,
8c81c9c3 74 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 75 [board_80003es2lan] = &e1000_es2_info,
76 [board_ich8lan] = &e1000_ich8_info,
77 [board_ich9lan] = &e1000_ich9_info,
f4187b56 78 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 79 [board_pchlan] = &e1000_pch_info,
d3738bb8 80 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 81 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
84f4ee90 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 90 /* General Registers */
91 {E1000_CTRL, "CTRL"},
92 {E1000_STATUS, "STATUS"},
93 {E1000_CTRL_EXT, "CTRL_EXT"},
94
95 /* Interrupt Registers */
96 {E1000_ICR, "ICR"},
97
af667a29 98 /* Rx Registers */
84f4ee90 99 {E1000_RCTL, "RCTL"},
1e36052e
BA		 100 {E1000_RDLEN(0), "RDLEN"},
101 {E1000_RDH(0), "RDH"},
102 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 103 {E1000_RDTR, "RDTR"},
104 {E1000_RXDCTL(0), "RXDCTL"},
105 {E1000_ERT, "ERT"},
1e36052e
BA		 106 {E1000_RDBAL(0), "RDBAL"},
107 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 108 {E1000_RDFH, "RDFH"},
109 {E1000_RDFT, "RDFT"},
110 {E1000_RDFHS, "RDFHS"},
111 {E1000_RDFTS, "RDFTS"},
112 {E1000_RDFPC, "RDFPC"},
113
af667a29 114 /* Tx Registers */
84f4ee90 115 {E1000_TCTL, "TCTL"},
1e36052e
BA		 116 {E1000_TDBAL(0), "TDBAL"},
117 {E1000_TDBAH(0), "TDBAH"},
118 {E1000_TDLEN(0), "TDLEN"},
119 {E1000_TDH(0), "TDH"},
120 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 121 {E1000_TIDV, "TIDV"},
122 {E1000_TXDCTL(0), "TXDCTL"},
123 {E1000_TADV, "TADV"},
124 {E1000_TARC(0), "TARC"},
125 {E1000_TDFH, "TDFH"},
126 {E1000_TDFT, "TDFT"},
127 {E1000_TDFHS, "TDFHS"},
128 {E1000_TDFTS, "TDFTS"},
129 {E1000_TDFPC, "TDFPC"},
130
131 /* List Terminator */
f36bb6ca 132 {0, NULL}
84f4ee90
TI		 133};
134
e921eb1a 135/**
84f4ee90 136 * e1000_regdump - register printout routine
e921eb1a
BA		 137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
84f4ee90
TI		 140static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
141{
142 int n = 0;
143 char rname[16];
144 u32 regs[8];
145
146 switch (reginfo->ofs) {
147 case E1000_RXDCTL(0):
148 for (n = 0; n < 2; n++)
149 regs[n] = __er32(hw, E1000_RXDCTL(n));
150 break;
151 case E1000_TXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_TXDCTL(n));
154 break;
155 case E1000_TARC(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TARC(n));
158 break;
159 default:
ef456f85
JK		 160 pr_info("%-15s %08x\n",
161 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 162 return;
163 }
164
165 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 166 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 167}
168
f0c5dadf
ET		 169static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
170 struct e1000_buffer *bi)
171{
172 int i;
173 struct e1000_ps_page *ps_page;
174
175 for (i = 0; i < adapter->rx_ps_pages; i++) {
176 ps_page = &bi->ps_pages[i];
177
178 if (ps_page->page) {
179 pr_info("packet dump for ps_page %d:\n", i);
180 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
181 16, 1, page_address(ps_page->page),
182 PAGE_SIZE, true);
183 }
184 }
185}
186
e921eb1a 187/**
af667a29 188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 189 * @adapter: board private structure
190 **/
84f4ee90
TI		 191static void e1000e_dump(struct e1000_adapter *adapter)
192{
193 struct net_device *netdev = adapter->netdev;
194 struct e1000_hw *hw = &adapter->hw;
195 struct e1000_reg_info *reginfo;
196 struct e1000_ring *tx_ring = adapter->tx_ring;
197 struct e1000_tx_desc *tx_desc;
af667a29 198 struct my_u0 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
af667a29 201 } *u0;
84f4ee90
TI		 202 struct e1000_buffer *buffer_info;
203 struct e1000_ring *rx_ring = adapter->rx_ring;
204 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 205 union e1000_rx_desc_extended *rx_desc;
af667a29 206 struct my_u1 {
e885d762
BA		 207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
af667a29 211 } *u1;
84f4ee90
TI		 212 u32 staterr;
213 int i = 0;
214
215 if (!netif_msg_hw(adapter))
216 return;
217
218 /* Print netdevice Info */
219 if (netdev) {
220 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 221 pr_info("Device Name state trans_start last_rx\n");
222 pr_info("%-15s %016lX %016lX %016lX\n",
223 netdev->name, netdev->state, netdev->trans_start,
224 netdev->last_rx);
84f4ee90
TI		 225 }
226
227 /* Print Registers */
228 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 229 pr_info(" Register Name Value\n");
84f4ee90
TI		 230 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
231 reginfo->name; reginfo++) {
232 e1000_regdump(hw, reginfo);
233 }
234
af667a29 235 /* Print Tx Ring Summary */
84f4ee90 236 if (!netdev || !netif_running(netdev))
fe1e980f 237 return;
84f4ee90 238
af667a29 239 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 240 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 241 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 242 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
243 0, tx_ring->next_to_use, tx_ring->next_to_clean,
244 (unsigned long long)buffer_info->dma,
245 buffer_info->length,
246 buffer_info->next_to_watch,
247 (unsigned long long)buffer_info->time_stamp);
84f4ee90 248
af667a29 249 /* Print Tx Ring */
84f4ee90
TI		 250 if (!netif_msg_tx_done(adapter))
251 goto rx_ring_summary;
252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 254
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
256 *
257 * Legacy Transmit Descriptor
258 * +--------------------------------------------------------------+
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
260 * +--------------------------------------------------------------+
261 * 8 | Special | CSS | Status | CMD | CSO | Length |
262 * +--------------------------------------------------------------+
263 * 63 48 47 36 35 32 31 24 23 16 15 0
264 *
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
266 * 63 48 47 40 39 32 31 16 15 8 7 0
267 * +----------------------------------------------------------------+
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
269 * +----------------------------------------------------------------+
270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 *
274 * Extended Data Descriptor (DTYP=0x1)
275 * +----------------------------------------------------------------+
276 * 0 | Buffer Address [63:0] |
277 * +----------------------------------------------------------------+
278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
279 * +----------------------------------------------------------------+
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
281 */
ef456f85
JK		 282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 286 const char *next_desc;
84f4ee90
TI		 287 tx_desc = E1000_TX_DESC(*tx_ring, i);
288 buffer_info = &tx_ring->buffer_info[i];
289 u0 = (struct my_u0 *)tx_desc;
84f4ee90 290 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 291 next_desc = " NTC/U";
84f4ee90 292 else if (i == tx_ring->next_to_use)
ef456f85 293 next_desc = " NTU";
84f4ee90 294 else if (i == tx_ring->next_to_clean)
ef456f85 295 next_desc = " NTC";
84f4ee90 296 else
ef456f85
JK		 297 next_desc = "";
298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
299 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
300 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
301 i,
302 (unsigned long long)le64_to_cpu(u0->a),
303 (unsigned long long)le64_to_cpu(u0->b),
304 (unsigned long long)buffer_info->dma,
305 buffer_info->length, buffer_info->next_to_watch,
306 (unsigned long long)buffer_info->time_stamp,
307 buffer_info->skb, next_desc);
84f4ee90 308
f0c5dadf 309 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 310 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 311 16, 1, buffer_info->skb->data,
312 buffer_info->skb->len, true);
84f4ee90
TI		 313 }
314
af667a29 315 /* Print Rx Ring Summary */
84f4ee90 316rx_ring_summary:
af667a29 317 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 318 pr_info("Queue [NTU] [NTC]\n");
319 pr_info(" %5d %5X %5X\n",
320 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 321
af667a29 322 /* Print Rx Ring */
84f4ee90 323 if (!netif_msg_rx_status(adapter))
fe1e980f 324 return;
84f4ee90 325
af667a29 326 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 327 switch (adapter->rx_ps_pages) {
328 case 1:
329 case 2:
330 case 3:
331 /* [Extended] Packet Split Receive Descriptor Format
332 *
333 * +-----------------------------------------------------+
334 * 0 | Buffer Address 0 [63:0] |
335 * +-----------------------------------------------------+
336 * 8 | Buffer Address 1 [63:0] |
337 * +-----------------------------------------------------+
338 * 16 | Buffer Address 2 [63:0] |
339 * +-----------------------------------------------------+
340 * 24 | Buffer Address 3 [63:0] |
341 * +-----------------------------------------------------+
342 */
ef456f85 343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 344 /* [Extended] Receive Descriptor (Write-Back) Format
345 *
346 * 63 48 47 32 31 13 12 8 7 4 3 0
347 * +------------------------------------------------------+
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
349 * | Checksum | Ident | | Queue | | Type |
350 * +------------------------------------------------------+
351 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
352 * +------------------------------------------------------+
353 * 63 48 47 32 31 20 19 0
354 */
ef456f85 355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 356 for (i = 0; i < rx_ring->count; i++) {
ef456f85 357 const char *next_desc;
84f4ee90
TI		 358 buffer_info = &rx_ring->buffer_info[i];
359 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
360 u1 = (struct my_u1 *)rx_desc_ps;
361 staterr =
af667a29 362 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 363
364 if (i == rx_ring->next_to_use)
365 next_desc = " NTU";
366 else if (i == rx_ring->next_to_clean)
367 next_desc = " NTC";
368 else
369 next_desc = "";
370
84f4ee90
TI		 371 if (staterr & E1000_RXD_STAT_DD) {
372 /* Descriptor Done */
ef456f85
JK		 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
374 "RWB", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 buffer_info->skb, next_desc);
84f4ee90 380 } else {
ef456f85
JK		 381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
382 "R ", i,
383 (unsigned long long)le64_to_cpu(u1->a),
384 (unsigned long long)le64_to_cpu(u1->b),
385 (unsigned long long)le64_to_cpu(u1->c),
386 (unsigned long long)le64_to_cpu(u1->d),
387 (unsigned long long)buffer_info->dma,
388 buffer_info->skb, next_desc);
84f4ee90
TI		 389
390 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 391 e1000e_dump_ps_pages(adapter,
392 buffer_info);
84f4ee90 393 }
84f4ee90
TI		 394 }
395 break;
396 default:
397 case 0:
5f450212 398 /* Extended Receive Descriptor (Read) Format
84f4ee90 399 *
5f450212
BA		 400 * +-----------------------------------------------------+
401 * 0 | Buffer Address [63:0] |
402 * +-----------------------------------------------------+
403 * 8 | Reserved |
404 * +-----------------------------------------------------+
84f4ee90 405 */
ef456f85 406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 407 /* Extended Receive Descriptor (Write-Back) Format
408 *
409 * 63 48 47 32 31 24 23 4 3 0
410 * +------------------------------------------------------+
411 * | RSS Hash | | | |
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
413 * | Packet | IP | | | Type |
414 * | Checksum | Ident | | | |
415 * +------------------------------------------------------+
416 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
417 * +------------------------------------------------------+
418 * 63 48 47 32 31 20 19 0
419 */
ef456f85 420 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 421
422 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 423 const char *next_desc;
424
84f4ee90 425 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
427 u1 = (struct my_u1 *)rx_desc;
428 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 429
430 if (i == rx_ring->next_to_use)
431 next_desc = " NTU";
432 else if (i == rx_ring->next_to_clean)
433 next_desc = " NTC";
434 else
435 next_desc = "";
436
5f450212
BA		 437 if (staterr & E1000_RXD_STAT_DD) {
438 /* Descriptor Done */
ef456f85
JK		 439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
440 "RWB", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 buffer_info->skb, next_desc);
5f450212 444 } else {
ef456f85
JK		 445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
446 "R ", i,
447 (unsigned long long)le64_to_cpu(u1->a),
448 (unsigned long long)le64_to_cpu(u1->b),
449 (unsigned long long)buffer_info->dma,
450 buffer_info->skb, next_desc);
5f450212 451
f0c5dadf
ET		 452 if (netif_msg_pktdata(adapter) &&
453 buffer_info->skb)
5f450212
BA		 454 print_hex_dump(KERN_INFO, "",
455 DUMP_PREFIX_ADDRESS, 16,
456 1,
f0c5dadf 457 buffer_info->skb->data,
5f450212
BA		 458 adapter->rx_buffer_len,
459 true);
460 }
84f4ee90
TI		 461 }
462 }
84f4ee90
TI		 463}
464
bc7f75fa
AK		 465/**
466 * e1000_desc_unused - calculate if we have unused descriptors
467 **/
468static int e1000_desc_unused(struct e1000_ring *ring)
469{
470 if (ring->next_to_clean > ring->next_to_use)
471 return ring->next_to_clean - ring->next_to_use - 1;
472
473 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
474}
475
b67e1913
BA		 476/**
477 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
478 * @adapter: board private structure
479 * @hwtstamps: time stamp structure to update
480 * @systim: unsigned 64bit system time value.
481 *
482 * Convert the system time value stored in the RX/TXSTMP registers into a
483 * hwtstamp which can be used by the upper level time stamping functions.
484 *
485 * The 'systim_lock' spinlock is used to protect the consistency of the
486 * system time value. This is needed because reading the 64 bit time
487 * value involves reading two 32 bit registers. The first read latches the
488 * value.
489 **/
490static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
491 struct skb_shared_hwtstamps *hwtstamps,
492 u64 systim)
493{
494 u64 ns;
495 unsigned long flags;
496
497 spin_lock_irqsave(&adapter->systim_lock, flags);
498 ns = timecounter_cyc2time(&adapter->tc, systim);
499 spin_unlock_irqrestore(&adapter->systim_lock, flags);
500
501 memset(hwtstamps, 0, sizeof(*hwtstamps));
502 hwtstamps->hwtstamp = ns_to_ktime(ns);
503}
504
505/**
506 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
507 * @adapter: board private structure
508 * @status: descriptor extended error and status field
509 * @skb: particular skb to include time stamp
510 *
511 * If the time stamp is valid, convert it into the timecounter ns value
512 * and store that result into the shhwtstamps structure which is passed
513 * up the network stack.
514 **/
515static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
516 struct sk_buff *skb)
517{
518 struct e1000_hw *hw = &adapter->hw;
519 u64 rxstmp;
520
521 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
522 !(status & E1000_RXDEXT_STATERR_TST) ||
523 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
524 return;
525
526 /* The Rx time stamp registers contain the time stamp. No other
527 * received packet will be time stamped until the Rx time stamp
528 * registers are read. Because only one packet can be time stamped
529 * at a time, the register values must belong to this packet and
530 * therefore none of the other additional attributes need to be
531 * compared.
532 */
533 rxstmp = (u64)er32(RXSTMPL);
534 rxstmp |= (u64)er32(RXSTMPH) << 32;
535 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
536
537 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
538}
539
bc7f75fa 540/**
ad68076e 541 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 542 * @adapter: board private structure
b67e1913 543 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
545 * @skb: pointer to sk_buff to be indicated to stack
546 **/
547static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 548 struct net_device *netdev, struct sk_buff *skb,
b67e1913 549 u32 staterr, __le16 vlan)
bc7f75fa 550{
86d70e53 551 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 552
553 e1000e_rx_hwtstamp(adapter, staterr, skb);
554
bc7f75fa
AK		 555 skb->protocol = eth_type_trans(skb, netdev);
556
b67e1913 557 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 558 __vlan_hwaccel_put_tag(skb, tag);
559
560 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 561}
562
563/**
af667a29 564 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 565 * @adapter: board private structure
566 * @status_err: receive descriptor status and error fields
567 * @csum: receive descriptor csum field
568 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 569 **/
570static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 571 struct sk_buff *skb)
bc7f75fa
AK		 572{
573 u16 status = (u16)status_err;
574 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 575
576 skb_checksum_none_assert(skb);
bc7f75fa 577
afd12939
BA		 578 /* Rx checksum disabled */
579 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
580 return;
581
bc7f75fa
AK		 582 /* Ignore Checksum bit is set */
583 if (status & E1000_RXD_STAT_IXSM)
584 return;
afd12939 585
2e1706f2
BA		 586 /* TCP/UDP checksum error bit or IP checksum error bit is set */
587 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 588 /* let the stack verify checksum errors */
589 adapter->hw_csum_err++;
590 return;
591 }
592
593 /* TCP/UDP Checksum has not been calculated */
594 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
595 return;
596
597 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 598 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 599 adapter->hw_csum_good++;
600}
601
55aa6985 602static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 603{
55aa6985 604 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 605 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 606 s32 ret_val = __ew32_prepare(hw);
607
608 writel(i, rx_ring->tail);
c6e7f51e 609
bdc125f7 610 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 611 u32 rctl = er32(RCTL);
612 ew32(RCTL, rctl & ~E1000_RCTL_EN);
613 e_err("ME firmware caused invalid RDT - resetting\n");
614 schedule_work(&adapter->reset_task);
615 }
616}
617
55aa6985 618static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 619{
55aa6985 620 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 621 struct e1000_hw *hw = &adapter->hw;
bdc125f7 622 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 623
bdc125f7
BA		 624 writel(i, tx_ring->tail);
625
626 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 627 u32 tctl = er32(TCTL);
628 ew32(TCTL, tctl & ~E1000_TCTL_EN);
629 e_err("ME firmware caused invalid TDT - resetting\n");
630 schedule_work(&adapter->reset_task);
631 }
632}
633
bc7f75fa 634/**
5f450212 635 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 636 * @rx_ring: Rx descriptor ring
bc7f75fa 637 **/
55aa6985 638static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 639 int cleaned_count, gfp_t gfp)
bc7f75fa 640{
55aa6985 641 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 642 struct net_device *netdev = adapter->netdev;
643 struct pci_dev *pdev = adapter->pdev;
5f450212 644 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 645 struct e1000_buffer *buffer_info;
646 struct sk_buff *skb;
647 unsigned int i;
89d71a66 648 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 649
650 i = rx_ring->next_to_use;
651 buffer_info = &rx_ring->buffer_info[i];
652
653 while (cleaned_count--) {
654 skb = buffer_info->skb;
655 if (skb) {
656 skb_trim(skb, 0);
657 goto map_skb;
658 }
659
c2fed996 660 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 661 if (!skb) {
662 /* Better luck next round */
663 adapter->alloc_rx_buff_failed++;
664 break;
665 }
666
bc7f75fa
AK		 667 buffer_info->skb = skb;
668map_skb:
0be3f55f 669 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 670 adapter->rx_buffer_len,
0be3f55f
NN		 671 DMA_FROM_DEVICE);
672 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 673 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 674 adapter->rx_dma_failed++;
675 break;
676 }
677
5f450212
BA		 678 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
679 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 680
50849d79 681 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 682 /* Force memory writes to complete before letting h/w
50849d79
TH		 683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
c6e7f51e 688 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 689 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 690 else
c5083cf6 691 writel(i, rx_ring->tail);
50849d79 692 }
bc7f75fa
AK		 693 i++;
694 if (i == rx_ring->count)
695 i = 0;
696 buffer_info = &rx_ring->buffer_info[i];
697 }
698
50849d79 699 rx_ring->next_to_use = i;
bc7f75fa
AK		 700}
701
702/**
703 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 704 * @rx_ring: Rx descriptor ring
bc7f75fa 705 **/
55aa6985 706static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 707 int cleaned_count, gfp_t gfp)
bc7f75fa 708{
55aa6985 709 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 710 struct net_device *netdev = adapter->netdev;
711 struct pci_dev *pdev = adapter->pdev;
712 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 713 struct e1000_buffer *buffer_info;
714 struct e1000_ps_page *ps_page;
715 struct sk_buff *skb;
716 unsigned int i, j;
717
718 i = rx_ring->next_to_use;
719 buffer_info = &rx_ring->buffer_info[i];
720
721 while (cleaned_count--) {
722 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
723
724 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 725 ps_page = &buffer_info->ps_pages[j];
726 if (j >= adapter->rx_ps_pages) {
727 /* all unused desc entries get hw null ptr */
af667a29
BA		 728 rx_desc->read.buffer_addr[j + 1] =
729 ~cpu_to_le64(0);
47f44e40
AK		 730 continue;
731 }
732 if (!ps_page->page) {
c2fed996 733 ps_page->page = alloc_page(gfp);
bc7f75fa 734 if (!ps_page->page) {
47f44e40
AK		 735 adapter->alloc_rx_buff_failed++;
736 goto no_buffers;
737 }
0be3f55f
NN		 738 ps_page->dma = dma_map_page(&pdev->dev,
739 ps_page->page,
740 0, PAGE_SIZE,
741 DMA_FROM_DEVICE);
742 if (dma_mapping_error(&pdev->dev,
743 ps_page->dma)) {
47f44e40 744 dev_err(&adapter->pdev->dev,
af667a29 745 "Rx DMA page map failed\n");
47f44e40
AK		 746 adapter->rx_dma_failed++;
747 goto no_buffers;
bc7f75fa 748 }
bc7f75fa 749 }
e921eb1a 750 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 751 * didn't change because each write-back
752 * erases this info.
753 */
af667a29
BA		 754 rx_desc->read.buffer_addr[j + 1] =
755 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 756 }
757
c2fed996
JK		 758 skb = __netdev_alloc_skb_ip_align(netdev,
759 adapter->rx_ps_bsize0,
760 gfp);
bc7f75fa
AK		 761
762 if (!skb) {
763 adapter->alloc_rx_buff_failed++;
764 break;
765 }
766
bc7f75fa 767 buffer_info->skb = skb;
0be3f55f 768 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 769 adapter->rx_ps_bsize0,
0be3f55f
NN		 770 DMA_FROM_DEVICE);
771 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 772 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 773 adapter->rx_dma_failed++;
774 /* cleanup skb */
775 dev_kfree_skb_any(skb);
776 buffer_info->skb = NULL;
777 break;
778 }
779
780 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
781
50849d79 782 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 783 /* Force memory writes to complete before letting h/w
50849d79
TH		 784 * know there are new descriptors to fetch. (Only
785 * applicable for weak-ordered memory model archs,
786 * such as IA-64).
787 */
788 wmb();
c6e7f51e 789 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 790 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 791 else
c5083cf6 792 writel(i << 1, rx_ring->tail);
50849d79
TH		 793 }
794
bc7f75fa
AK		 795 i++;
796 if (i == rx_ring->count)
797 i = 0;
798 buffer_info = &rx_ring->buffer_info[i];
799 }
800
801no_buffers:
50849d79 802 rx_ring->next_to_use = i;
bc7f75fa
AK		 803}
804
97ac8cae
BA		 805/**
806 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 807 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 808 * @cleaned_count: number of buffers to allocate this pass
809 **/
810
55aa6985 811static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 812 int cleaned_count, gfp_t gfp)
97ac8cae 813{
55aa6985 814 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 815 struct net_device *netdev = adapter->netdev;
816 struct pci_dev *pdev = adapter->pdev;
5f450212 817 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 818 struct e1000_buffer *buffer_info;
819 struct sk_buff *skb;
820 unsigned int i;
2a2293b9 821 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 822
823 i = rx_ring->next_to_use;
824 buffer_info = &rx_ring->buffer_info[i];
825
826 while (cleaned_count--) {
827 skb = buffer_info->skb;
828 if (skb) {
829 skb_trim(skb, 0);
830 goto check_page;
831 }
832
c2fed996 833 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 834 if (unlikely(!skb)) {
835 /* Better luck next round */
836 adapter->alloc_rx_buff_failed++;
837 break;
838 }
839
97ac8cae
BA		 840 buffer_info->skb = skb;
841check_page:
842 /* allocate a new page if necessary */
843 if (!buffer_info->page) {
c2fed996 844 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 845 if (unlikely(!buffer_info->page)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
850
851 if (!buffer_info->dma)
0be3f55f 852 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 853 buffer_info->page, 0,
854 PAGE_SIZE,
0be3f55f 855 DMA_FROM_DEVICE);
97ac8cae 856
5f450212
BA		 857 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
858 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 859
860 if (unlikely(++i == rx_ring->count))
861 i = 0;
862 buffer_info = &rx_ring->buffer_info[i];
863 }
864
865 if (likely(rx_ring->next_to_use != i)) {
866 rx_ring->next_to_use = i;
867 if (unlikely(i-- == 0))
868 i = (rx_ring->count - 1);
869
870 /* Force memory writes to complete before letting h/w
871 * know there are new descriptors to fetch. (Only
872 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 873 * such as IA-64).
874 */
97ac8cae 875 wmb();
c6e7f51e 876 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 877 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 878 else
c5083cf6 879 writel(i, rx_ring->tail);
97ac8cae
BA		 880 }
881}
882
70495a50
BA		 883static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
884 struct sk_buff *skb)
885{
886 if (netdev->features & NETIF_F_RXHASH)
887 skb->rxhash = le32_to_cpu(rss);
888}
889
bc7f75fa 890/**
55aa6985
BA		 891 * e1000_clean_rx_irq - Send received data up the network stack
892 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 893 *
894 * the return value indicates whether actual cleaning was done, there
895 * is no guarantee that everything was cleaned
896 **/
55aa6985
BA		 897static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
898 int work_to_do)
bc7f75fa 899{
55aa6985 900 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 901 struct net_device *netdev = adapter->netdev;
902 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 903 struct e1000_hw *hw = &adapter->hw;
5f450212 904 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 905 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 906 u32 length, staterr;
bc7f75fa
AK		 907 unsigned int i;
908 int cleaned_count = 0;
3db1cd5c 909 bool cleaned = false;
bc7f75fa
AK		 910 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
911
912 i = rx_ring->next_to_clean;
5f450212
BA		 913 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
914 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 915 buffer_info = &rx_ring->buffer_info[i];
916
5f450212 917 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 918 struct sk_buff *skb;
bc7f75fa
AK		 919
920 if (*work_done >= work_to_do)
921 break;
922 (*work_done)++;
2d0bb1c1 923 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 924
bc7f75fa
AK		 925 skb = buffer_info->skb;
926 buffer_info->skb = NULL;
927
928 prefetch(skb->data - NET_IP_ALIGN);
929
930 i++;
931 if (i == rx_ring->count)
932 i = 0;
5f450212 933 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 934 prefetch(next_rxd);
935
936 next_buffer = &rx_ring->buffer_info[i];
937
3db1cd5c 938 cleaned = true;
bc7f75fa 939 cleaned_count++;
0be3f55f 940 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 941 buffer_info->dma,
942 adapter->rx_buffer_len,
0be3f55f 943 DMA_FROM_DEVICE);
bc7f75fa
AK		 944 buffer_info->dma = 0;
945
5f450212 946 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 947
e921eb1a 948 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 949 * packet, if that's the case we need to toss it. In fact, we
950 * need to toss every packet with the EOP bit clear and the
951 * next frame that _does_ have the EOP bit set, as it is by
952 * definition only a frame fragment
953 */
5f450212 954 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 955 adapter->flags2 |= FLAG2_IS_DISCARDING;
956
957 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 958 /* All receives must fit into a single buffer */
3bb99fe2 959 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 960 /* recycle */
961 buffer_info->skb = skb;
5f450212 962 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 963 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 964 goto next_desc;
965 }
966
cf955e6c
BG		 967 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
968 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 969 /* recycle */
970 buffer_info->skb = skb;
971 goto next_desc;
972 }
973
eb7c3adb 974 /* adjust length to remove Ethernet CRC */
0184039a
BG		 975 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
976 /* If configured to store CRC, don't subtract FCS,
977 * but keep the FCS bytes out of the total_rx_bytes
978 * counter
979 */
980 if (netdev->features & NETIF_F_RXFCS)
981 total_rx_bytes -= 4;
982 else
983 length -= 4;
984 }
eb7c3adb 985
bc7f75fa
AK		 986 total_rx_bytes += length;
987 total_rx_packets++;
988
e921eb1a 989 /* code added for copybreak, this should improve
bc7f75fa 990 * performance for small packets with large amounts
ad68076e
BA		 991 * of reassembly being done in the stack
992 */
bc7f75fa
AK		 993 if (length < copybreak) {
994 struct sk_buff *new_skb =
89d71a66 995 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 996 if (new_skb) {
808ff676
BA		 997 skb_copy_to_linear_data_offset(new_skb,
998 -NET_IP_ALIGN,
999 (skb->data -
1000 NET_IP_ALIGN),
1001 (length +
1002 NET_IP_ALIGN));
bc7f75fa
AK		 1003 /* save the skb in buffer_info as good */
1004 buffer_info->skb = skb;
1005 skb = new_skb;
1006 }
1007 /* else just continue with the old one */
1008 }
1009 /* end copybreak code */
1010 skb_put(skb, length);
1011
1012 /* Receive Checksum Offload */
2e1706f2 1013 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1014
70495a50
BA		 1015 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1016
5f450212
BA		 1017 e1000_receive_skb(adapter, netdev, skb, staterr,
1018 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1019
1020next_desc:
5f450212 1021 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1022
1023 /* return some buffers to hardware, one at a time is too slow */
1024 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1025 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1026 GFP_ATOMIC);
bc7f75fa
AK		 1027 cleaned_count = 0;
1028 }
1029
1030 /* use prefetched values */
1031 rx_desc = next_rxd;
1032 buffer_info = next_buffer;
5f450212
BA		 1033
1034 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1035 }
1036 rx_ring->next_to_clean = i;
1037
1038 cleaned_count = e1000_desc_unused(rx_ring);
1039 if (cleaned_count)
55aa6985 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1041
bc7f75fa 1042 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1043 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1044 return cleaned;
1045}
1046
55aa6985
BA		 1047static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1048 struct e1000_buffer *buffer_info)
bc7f75fa 1049{
55aa6985
BA		 1050 struct e1000_adapter *adapter = tx_ring->adapter;
1051
03b1320d
AD		 1052 if (buffer_info->dma) {
1053 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1054 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1055 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1056 else
0be3f55f
NN		 1057 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1058 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1059 buffer_info->dma = 0;
1060 }
bc7f75fa
AK		 1061 if (buffer_info->skb) {
1062 dev_kfree_skb_any(buffer_info->skb);
1063 buffer_info->skb = NULL;
1064 }
1b7719c4 1065 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1066}
1067
41cec6f1 1068static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1069{
41cec6f1 1070 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1071 struct e1000_adapter,
1072 print_hang_task);
09357b00 1073 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1074 struct e1000_ring *tx_ring = adapter->tx_ring;
1075 unsigned int i = tx_ring->next_to_clean;
1076 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1077 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1078 struct e1000_hw *hw = &adapter->hw;
1079 u16 phy_status, phy_1000t_status, phy_ext_status;
1080 u16 pci_status;
1081
615b32af
JB		 1082 if (test_bit(__E1000_DOWN, &adapter->state))
1083 return;
1084
09357b00
JK		 1085 if (!adapter->tx_hang_recheck &&
1086 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1087 /* May be block on write-back, flush and detect again
09357b00
JK		 1088 * flush pending descriptor writebacks to memory
1089 */
1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1091 /* execute the writes immediately */
1092 e1e_flush();
e921eb1a 1093 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1094 * the write is successful
1095 */
1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1097 /* execute the writes immediately */
1098 e1e_flush();
09357b00
JK		 1099 adapter->tx_hang_recheck = true;
1100 return;
1101 }
1102 /* Real hang detected */
1103 adapter->tx_hang_recheck = false;
1104 netif_stop_queue(netdev);
1105
c2ade1a4
BA		 1106 e1e_rphy(hw, MII_BMSR, &phy_status);
1107 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1108 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1109
41cec6f1
BA		 1110 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1111
1112 /* detected Hardware unit hang */
1113 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1114 " TDH <%x>\n"
1115 " TDT <%x>\n"
1116 " next_to_use <%x>\n"
1117 " next_to_clean <%x>\n"
1118 "buffer_info[next_to_clean]:\n"
1119 " time_stamp <%lx>\n"
1120 " next_to_watch <%x>\n"
1121 " jiffies <%lx>\n"
41cec6f1
BA		 1122 " next_to_watch.status <%x>\n"
1123 "MAC Status <%x>\n"
1124 "PHY Status <%x>\n"
1125 "PHY 1000BASE-T Status <%x>\n"
1126 "PHY Extended Status <%x>\n"
1127 "PCI Status <%x>\n",
c5083cf6
BA		 1128 readl(tx_ring->head),
1129 readl(tx_ring->tail),
44defeb3
JK		 1130 tx_ring->next_to_use,
1131 tx_ring->next_to_clean,
1132 tx_ring->buffer_info[eop].time_stamp,
1133 eop,
1134 jiffies,
41cec6f1
BA		 1135 eop_desc->upper.fields.status,
1136 er32(STATUS),
1137 phy_status,
1138 phy_1000t_status,
1139 phy_ext_status,
1140 pci_status);
7c0427ee
BA		 1141
1142 /* Suggest workaround for known h/w issue */
1143 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1144 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1145}
1146
b67e1913
BA		 1147/**
1148 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1149 * @work: pointer to work struct
1150 *
1151 * This work function polls the TSYNCTXCTL valid bit to determine when a
1152 * timestamp has been taken for the current stored skb. The timestamp must
1153 * be for this skb because only one such packet is allowed in the queue.
1154 */
1155static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1156{
1157 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1158 tx_hwtstamp_work);
1159 struct e1000_hw *hw = &adapter->hw;
1160
1161 if (!adapter->tx_hwtstamp_skb)
1162 return;
1163
1164 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1165 struct skb_shared_hwtstamps shhwtstamps;
1166 u64 txstmp;
1167
1168 txstmp = er32(TXSTMPL);
1169 txstmp |= (u64)er32(TXSTMPH) << 32;
1170
1171 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1172
1173 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1174 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1175 adapter->tx_hwtstamp_skb = NULL;
1176 } else {
1177 /* reschedule to check later */
1178 schedule_work(&adapter->tx_hwtstamp_work);
1179 }
1180}
1181
bc7f75fa
AK		 1182/**
1183 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1184 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1185 *
1186 * the return value indicates whether actual cleaning was done, there
1187 * is no guarantee that everything was cleaned
1188 **/
55aa6985 1189static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1190{
55aa6985 1191 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1192 struct net_device *netdev = adapter->netdev;
1193 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1194 struct e1000_tx_desc *tx_desc, *eop_desc;
1195 struct e1000_buffer *buffer_info;
1196 unsigned int i, eop;
1197 unsigned int count = 0;
bc7f75fa 1198 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1199 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1200
1201 i = tx_ring->next_to_clean;
1202 eop = tx_ring->buffer_info[i].next_to_watch;
1203 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1204
12d04a3c
AD		 1205 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1206 (count < tx_ring->count)) {
a86043c2 1207 bool cleaned = false;
2d0bb1c1 1208 rmb(); /* read buffer_info after eop_desc */
a86043c2 1209 for (; !cleaned; count++) {
bc7f75fa
AK		 1210 tx_desc = E1000_TX_DESC(*tx_ring, i);
1211 buffer_info = &tx_ring->buffer_info[i];
1212 cleaned = (i == eop);
1213
1214 if (cleaned) {
9ed318d5
TH		 1215 total_tx_packets += buffer_info->segs;
1216 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1217 if (buffer_info->skb) {
1218 bytes_compl += buffer_info->skb->len;
1219 pkts_compl++;
1220 }
bc7f75fa
AK		 1221 }
1222
55aa6985 1223 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1224 tx_desc->upper.data = 0;
1225
1226 i++;
1227 if (i == tx_ring->count)
1228 i = 0;
1229 }
1230
dac87619
TL		 1231 if (i == tx_ring->next_to_use)
1232 break;
bc7f75fa
AK		 1233 eop = tx_ring->buffer_info[i].next_to_watch;
1234 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1235 }
1236
1237 tx_ring->next_to_clean = i;
1238
3f0cfa3b
TH		 1239 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1240
bc7f75fa 1241#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1242 if (count && netif_carrier_ok(netdev) &&
1243 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1244 /* Make sure that anybody stopping the queue after this
1245 * sees the new next_to_clean.
1246 */
1247 smp_mb();
1248
1249 if (netif_queue_stopped(netdev) &&
1250 !(test_bit(__E1000_DOWN, &adapter->state))) {
1251 netif_wake_queue(netdev);
1252 ++adapter->restart_queue;
1253 }
1254 }
1255
1256 if (adapter->detect_tx_hung) {
e921eb1a 1257 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1258 * check with the clearing of time_stamp and movement of i
1259 */
3db1cd5c 1260 adapter->detect_tx_hung = false;
12d04a3c
AD		 1261 if (tx_ring->buffer_info[i].time_stamp &&
1262 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1263 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1264 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1265 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1266 else
1267 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1268 }
1269 adapter->total_tx_bytes += total_tx_bytes;
1270 adapter->total_tx_packets += total_tx_packets;
807540ba 1271 return count < tx_ring->count;
bc7f75fa
AK		 1272}
1273
bc7f75fa
AK		 1274/**
1275 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1276 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1277 *
1278 * the return value indicates whether actual cleaning was done, there
1279 * is no guarantee that everything was cleaned
1280 **/
55aa6985
BA		 1281static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1282 int work_to_do)
bc7f75fa 1283{
55aa6985 1284 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1285 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1286 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1287 struct net_device *netdev = adapter->netdev;
1288 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1289 struct e1000_buffer *buffer_info, *next_buffer;
1290 struct e1000_ps_page *ps_page;
1291 struct sk_buff *skb;
1292 unsigned int i, j;
1293 u32 length, staterr;
1294 int cleaned_count = 0;
3db1cd5c 1295 bool cleaned = false;
bc7f75fa
AK		 1296 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1297
1298 i = rx_ring->next_to_clean;
1299 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1300 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1301 buffer_info = &rx_ring->buffer_info[i];
1302
1303 while (staterr & E1000_RXD_STAT_DD) {
1304 if (*work_done >= work_to_do)
1305 break;
1306 (*work_done)++;
1307 skb = buffer_info->skb;
2d0bb1c1 1308 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1309
1310 /* in the packet split case this is header only */
1311 prefetch(skb->data - NET_IP_ALIGN);
1312
1313 i++;
1314 if (i == rx_ring->count)
1315 i = 0;
1316 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1317 prefetch(next_rxd);
1318
1319 next_buffer = &rx_ring->buffer_info[i];
1320
3db1cd5c 1321 cleaned = true;
bc7f75fa 1322 cleaned_count++;
0be3f55f 1323 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1324 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1325 buffer_info->dma = 0;
1326
af667a29 1327 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1328 if (!(staterr & E1000_RXD_STAT_EOP))
1329 adapter->flags2 |= FLAG2_IS_DISCARDING;
1330
1331 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1332 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1333 dev_kfree_skb_irq(skb);
b94b5028
JB		 1334 if (staterr & E1000_RXD_STAT_EOP)
1335 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1336 goto next_desc;
1337 }
1338
cf955e6c
BG		 1339 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1340 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1341 dev_kfree_skb_irq(skb);
1342 goto next_desc;
1343 }
1344
1345 length = le16_to_cpu(rx_desc->wb.middle.length0);
1346
1347 if (!length) {
ef456f85 1348 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1349 dev_kfree_skb_irq(skb);
1350 goto next_desc;
1351 }
1352
1353 /* Good Receive */
1354 skb_put(skb, length);
1355
1356 {
e921eb1a 1357 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1358 * it more efficient than reusing j
1359 */
1360 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1361
e921eb1a 1362 /* page alloc/put takes too long and effects small
0e15df49
BA		 1363 * packet throughput, so unsplit small packets and
1364 * save the alloc/put only valid in softirq (napi)
1365 * context to call kmap_*
ad68076e 1366 */
0e15df49
BA		 1367 if (l1 && (l1 <= copybreak) &&
1368 ((length + l1) <= adapter->rx_ps_bsize0)) {
1369 u8 *vaddr;
1370
1371 ps_page = &buffer_info->ps_pages[0];
1372
e921eb1a 1373 /* there is no documentation about how to call
0e15df49
BA		 1374 * kmap_atomic, so we can't hold the mapping
1375 * very long
1376 */
1377 dma_sync_single_for_cpu(&pdev->dev,
1378 ps_page->dma,
1379 PAGE_SIZE,
1380 DMA_FROM_DEVICE);
9f393834 1381 vaddr = kmap_atomic(ps_page->page);
0e15df49 1382 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1383 kunmap_atomic(vaddr);
0e15df49
BA		 1384 dma_sync_single_for_device(&pdev->dev,
1385 ps_page->dma,
1386 PAGE_SIZE,
1387 DMA_FROM_DEVICE);
1388
1389 /* remove the CRC */
0184039a
BG		 1390 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1391 if (!(netdev->features & NETIF_F_RXFCS))
1392 l1 -= 4;
1393 }
0e15df49
BA		 1394
1395 skb_put(skb, l1);
1396 goto copydone;
1397 } /* if */
bc7f75fa
AK		 1398 }
1399
1400 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1401 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1402 if (!length)
1403 break;
1404
47f44e40 1405 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1406 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1407 DMA_FROM_DEVICE);
bc7f75fa
AK		 1408 ps_page->dma = 0;
1409 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1410 ps_page->page = NULL;
1411 skb->len += length;
1412 skb->data_len += length;
98a045d7 1413 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1414 }
1415
eb7c3adb
JK		 1416 /* strip the ethernet crc, problem is we're using pages now so
1417 * this whole operation can get a little cpu intensive
1418 */
0184039a
BG		 1419 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1420 if (!(netdev->features & NETIF_F_RXFCS))
1421 pskb_trim(skb, skb->len - 4);
1422 }
eb7c3adb 1423
bc7f75fa
AK		 1424copydone:
1425 total_rx_bytes += skb->len;
1426 total_rx_packets++;
1427
2e1706f2 1428 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1429
70495a50
BA		 1430 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1431
bc7f75fa 1432 if (rx_desc->wb.upper.header_status &
17e813ec 1433 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1434 adapter->rx_hdr_split++;
1435
b67e1913
BA		 1436 e1000_receive_skb(adapter, netdev, skb, staterr,
1437 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1438
1439next_desc:
1440 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1441 buffer_info->skb = NULL;
1442
1443 /* return some buffers to hardware, one at a time is too slow */
1444 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1445 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1446 GFP_ATOMIC);
bc7f75fa
AK		 1447 cleaned_count = 0;
1448 }
1449
1450 /* use prefetched values */
1451 rx_desc = next_rxd;
1452 buffer_info = next_buffer;
1453
1454 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1455 }
1456 rx_ring->next_to_clean = i;
1457
1458 cleaned_count = e1000_desc_unused(rx_ring);
1459 if (cleaned_count)
55aa6985 1460 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1461
bc7f75fa 1462 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1463 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1464 return cleaned;
1465}
1466
97ac8cae
BA		 1467/**
1468 * e1000_consume_page - helper function
1469 **/
1470static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1471 u16 length)
97ac8cae
BA		 1472{
1473 bi->page = NULL;
1474 skb->len += length;
1475 skb->data_len += length;
98a045d7 1476 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1477}
1478
1479/**
1480 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1481 * @adapter: board private structure
1482 *
1483 * the return value indicates whether actual cleaning was done, there
1484 * is no guarantee that everything was cleaned
1485 **/
55aa6985
BA		 1486static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1487 int work_to_do)
97ac8cae 1488{
55aa6985 1489 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1490 struct net_device *netdev = adapter->netdev;
1491 struct pci_dev *pdev = adapter->pdev;
5f450212 1492 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1493 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1494 u32 length, staterr;
97ac8cae
BA		 1495 unsigned int i;
1496 int cleaned_count = 0;
1497 bool cleaned = false;
362e20ca 1498 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1499 struct skb_shared_info *shinfo;
97ac8cae
BA		 1500
1501 i = rx_ring->next_to_clean;
5f450212
BA		 1502 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1503 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1504 buffer_info = &rx_ring->buffer_info[i];
1505
5f450212 1506 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1507 struct sk_buff *skb;
97ac8cae
BA		 1508
1509 if (*work_done >= work_to_do)
1510 break;
1511 (*work_done)++;
2d0bb1c1 1512 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1513
97ac8cae
BA		 1514 skb = buffer_info->skb;
1515 buffer_info->skb = NULL;
1516
1517 ++i;
1518 if (i == rx_ring->count)
1519 i = 0;
5f450212 1520 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1521 prefetch(next_rxd);
1522
1523 next_buffer = &rx_ring->buffer_info[i];
1524
1525 cleaned = true;
1526 cleaned_count++;
0be3f55f
NN		 1527 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1528 DMA_FROM_DEVICE);
97ac8cae
BA		 1529 buffer_info->dma = 0;
1530
5f450212 1531 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1532
1533 /* errors is only valid for DD + EOP descriptors */
5f450212 1534 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1535 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1536 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1537 /* recycle both page and skb */
1538 buffer_info->skb = skb;
1539 /* an error means any chain goes out the window too */
1540 if (rx_ring->rx_skb_top)
1541 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1542 rx_ring->rx_skb_top = NULL;
1543 goto next_desc;
97ac8cae 1544 }
f0f1a172 1545#define rxtop (rx_ring->rx_skb_top)
5f450212 1546 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1547 /* this descriptor is only the beginning (or middle) */
1548 if (!rxtop) {
1549 /* this is the beginning of a chain */
1550 rxtop = skb;
1551 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1552 0, length);
97ac8cae
BA		 1553 } else {
1554 /* this is the middle of a chain */
17e813ec
BA		 1555 shinfo = skb_shinfo(rxtop);
1556 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1557 buffer_info->page, 0,
1558 length);
97ac8cae
BA		 1559 /* re-use the skb, only consumed the page */
1560 buffer_info->skb = skb;
1561 }
1562 e1000_consume_page(buffer_info, rxtop, length);
1563 goto next_desc;
1564 } else {
1565 if (rxtop) {
1566 /* end of the chain */
17e813ec
BA		 1567 shinfo = skb_shinfo(rxtop);
1568 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1569 buffer_info->page, 0,
1570 length);
97ac8cae 1571 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1572 * page
1573 */
97ac8cae
BA		 1574 buffer_info->skb = skb;
1575 skb = rxtop;
1576 rxtop = NULL;
1577 e1000_consume_page(buffer_info, skb, length);
1578 } else {
1579 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1580 * copybreak to save the put_page/alloc_page
1581 */
97ac8cae
BA		 1582 if (length <= copybreak &&
1583 skb_tailroom(skb) >= length) {
1584 u8 *vaddr;
4679026d 1585 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1586 memcpy(skb_tail_pointer(skb), vaddr,
1587 length);
4679026d 1588 kunmap_atomic(vaddr);
97ac8cae 1589 /* re-use the page, so don't erase
e921eb1a
BA		 1590 * buffer_info->page
1591 */
97ac8cae
BA		 1592 skb_put(skb, length);
1593 } else {
1594 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1595 buffer_info->page, 0,
1596 length);
97ac8cae 1597 e1000_consume_page(buffer_info, skb,
f0ff4398 1598 length);
97ac8cae
BA		 1599 }
1600 }
1601 }
1602
2e1706f2
BA		 1603 /* Receive Checksum Offload */
1604 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1605
70495a50
BA		 1606 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1607
97ac8cae
BA		 1608 /* probably a little skewed due to removing CRC */
1609 total_rx_bytes += skb->len;
1610 total_rx_packets++;
1611
1612 /* eth type trans needs skb->data to point to something */
1613 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1614 e_err("pskb_may_pull failed.\n");
ef5ab89c 1615 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1616 goto next_desc;
1617 }
1618
5f450212
BA		 1619 e1000_receive_skb(adapter, netdev, skb, staterr,
1620 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1621
1622next_desc:
5f450212 1623 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1624
1625 /* return some buffers to hardware, one at a time is too slow */
1626 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1627 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1628 GFP_ATOMIC);
97ac8cae
BA		 1629 cleaned_count = 0;
1630 }
1631
1632 /* use prefetched values */
1633 rx_desc = next_rxd;
1634 buffer_info = next_buffer;
5f450212
BA		 1635
1636 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1637 }
1638 rx_ring->next_to_clean = i;
1639
1640 cleaned_count = e1000_desc_unused(rx_ring);
1641 if (cleaned_count)
55aa6985 1642 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1643
1644 adapter->total_rx_bytes += total_rx_bytes;
1645 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1646 return cleaned;
1647}
1648
bc7f75fa
AK		 1649/**
1650 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1651 * @rx_ring: Rx descriptor ring
bc7f75fa 1652 **/
55aa6985 1653static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1654{
55aa6985 1655 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1656 struct e1000_buffer *buffer_info;
1657 struct e1000_ps_page *ps_page;
1658 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1659 unsigned int i, j;
1660
1661 /* Free all the Rx ring sk_buffs */
1662 for (i = 0; i < rx_ring->count; i++) {
1663 buffer_info = &rx_ring->buffer_info[i];
1664 if (buffer_info->dma) {
1665 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1666 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1667 adapter->rx_buffer_len,
0be3f55f 1668 DMA_FROM_DEVICE);
97ac8cae 1669 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1670 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1671 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1672 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1673 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1674 adapter->rx_ps_bsize0,
0be3f55f 1675 DMA_FROM_DEVICE);
bc7f75fa
AK		 1676 buffer_info->dma = 0;
1677 }
1678
97ac8cae
BA		 1679 if (buffer_info->page) {
1680 put_page(buffer_info->page);
1681 buffer_info->page = NULL;
1682 }
1683
bc7f75fa
AK		 1684 if (buffer_info->skb) {
1685 dev_kfree_skb(buffer_info->skb);
1686 buffer_info->skb = NULL;
1687 }
1688
1689 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1690 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1691 if (!ps_page->page)
1692 break;
0be3f55f
NN		 1693 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1694 DMA_FROM_DEVICE);
bc7f75fa
AK		 1695 ps_page->dma = 0;
1696 put_page(ps_page->page);
1697 ps_page->page = NULL;
1698 }
1699 }
1700
1701 /* there also may be some cached data from a chained receive */
1702 if (rx_ring->rx_skb_top) {
1703 dev_kfree_skb(rx_ring->rx_skb_top);
1704 rx_ring->rx_skb_top = NULL;
1705 }
1706
bc7f75fa
AK		 1707 /* Zero out the descriptor ring */
1708 memset(rx_ring->desc, 0, rx_ring->size);
1709
1710 rx_ring->next_to_clean = 0;
1711 rx_ring->next_to_use = 0;
b94b5028 1712 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1713
c5083cf6 1714 writel(0, rx_ring->head);
bdc125f7
BA		 1715 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1716 e1000e_update_rdt_wa(rx_ring, 0);
1717 else
1718 writel(0, rx_ring->tail);
bc7f75fa
AK		 1719}
1720
a8f88ff5
JB		 1721static void e1000e_downshift_workaround(struct work_struct *work)
1722{
1723 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1724 struct e1000_adapter,
1725 downshift_task);
a8f88ff5 1726
615b32af
JB		 1727 if (test_bit(__E1000_DOWN, &adapter->state))
1728 return;
1729
a8f88ff5
JB		 1730 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1731}
1732
bc7f75fa
AK		 1733/**
1734 * e1000_intr_msi - Interrupt Handler
1735 * @irq: interrupt number
1736 * @data: pointer to a network interface device structure
1737 **/
8bb62869 1738static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1739{
1740 struct net_device *netdev = data;
1741 struct e1000_adapter *adapter = netdev_priv(netdev);
1742 struct e1000_hw *hw = &adapter->hw;
1743 u32 icr = er32(ICR);
1744
e921eb1a 1745 /* read ICR disables interrupts using IAM */
573cca8c 1746 if (icr & E1000_ICR_LSC) {
f92518dd 1747 hw->mac.get_link_status = true;
e921eb1a 1748 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1749 * disconnect (LSC) before accessing any PHY registers
1750 */
bc7f75fa
AK		 1751 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1752 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1753 schedule_work(&adapter->downshift_task);
bc7f75fa 1754
e921eb1a 1755 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1756 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1757 * adapter in watchdog
1758 */
bc7f75fa
AK		 1759 if (netif_carrier_ok(netdev) &&
1760 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1761 /* disable receives */
1762 u32 rctl = er32(RCTL);
1763 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1764 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1765 }
1766 /* guard against interrupt when we're going down */
1767 if (!test_bit(__E1000_DOWN, &adapter->state))
1768 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1769 }
1770
94fb848b
BA		 1771 /* Reset on uncorrectable ECC error */
1772 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1773 u32 pbeccsts = er32(PBECCSTS);
1774
1775 adapter->corr_errors +=
1776 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1777 adapter->uncorr_errors +=
1778 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1779 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1780
1781 /* Do the reset outside of interrupt context */
1782 schedule_work(&adapter->reset_task);
1783
1784 /* return immediately since reset is imminent */
1785 return IRQ_HANDLED;
1786 }
1787
288379f0 1788 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1789 adapter->total_tx_bytes = 0;
1790 adapter->total_tx_packets = 0;
1791 adapter->total_rx_bytes = 0;
1792 adapter->total_rx_packets = 0;
288379f0 1793 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1794 }
1795
1796 return IRQ_HANDLED;
1797}
1798
1799/**
1800 * e1000_intr - Interrupt Handler
1801 * @irq: interrupt number
1802 * @data: pointer to a network interface device structure
1803 **/
8bb62869 1804static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1805{
1806 struct net_device *netdev = data;
1807 struct e1000_adapter *adapter = netdev_priv(netdev);
1808 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1809 u32 rctl, icr = er32(ICR);
4662e82b 1810
a68ea775 1811 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1812 return IRQ_NONE; /* Not our interrupt */
1813
e921eb1a 1814 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1815 * not set, then the adapter didn't send an interrupt
1816 */
bc7f75fa
AK		 1817 if (!(icr & E1000_ICR_INT_ASSERTED))
1818 return IRQ_NONE;
1819
e921eb1a 1820 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1821 * interrupts are masked. No need for the
1822 * IMC write
1823 */
bc7f75fa 1824
573cca8c 1825 if (icr & E1000_ICR_LSC) {
f92518dd 1826 hw->mac.get_link_status = true;
e921eb1a 1827 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1828 * disconnect (LSC) before accessing any PHY registers
1829 */
bc7f75fa
AK		 1830 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1831 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1832 schedule_work(&adapter->downshift_task);
bc7f75fa 1833
e921eb1a 1834 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1835 * For packet buffer work-around on link down event;
1836 * disable receives here in the ISR and
1837 * reset adapter in watchdog
1838 */
1839 if (netif_carrier_ok(netdev) &&
1840 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1841 /* disable receives */
1842 rctl = er32(RCTL);
1843 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1844 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1845 }
1846 /* guard against interrupt when we're going down */
1847 if (!test_bit(__E1000_DOWN, &adapter->state))
1848 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1849 }
1850
94fb848b
BA		 1851 /* Reset on uncorrectable ECC error */
1852 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1853 u32 pbeccsts = er32(PBECCSTS);
1854
1855 adapter->corr_errors +=
1856 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1857 adapter->uncorr_errors +=
1858 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1859 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1860
1861 /* Do the reset outside of interrupt context */
1862 schedule_work(&adapter->reset_task);
1863
1864 /* return immediately since reset is imminent */
1865 return IRQ_HANDLED;
1866 }
1867
288379f0 1868 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1869 adapter->total_tx_bytes = 0;
1870 adapter->total_tx_packets = 0;
1871 adapter->total_rx_bytes = 0;
1872 adapter->total_rx_packets = 0;
288379f0 1873 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1874 }
1875
1876 return IRQ_HANDLED;
1877}
1878
8bb62869 1879static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1880{
1881 struct net_device *netdev = data;
1882 struct e1000_adapter *adapter = netdev_priv(netdev);
1883 struct e1000_hw *hw = &adapter->hw;
1884 u32 icr = er32(ICR);
1885
1886 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1887 if (!test_bit(__E1000_DOWN, &adapter->state))
1888 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1889 return IRQ_NONE;
1890 }
1891
1892 if (icr & adapter->eiac_mask)
1893 ew32(ICS, (icr & adapter->eiac_mask));
1894
1895 if (icr & E1000_ICR_OTHER) {
1896 if (!(icr & E1000_ICR_LSC))
1897 goto no_link_interrupt;
f92518dd 1898 hw->mac.get_link_status = true;
4662e82b
BA		 1899 /* guard against interrupt when we're going down */
1900 if (!test_bit(__E1000_DOWN, &adapter->state))
1901 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1902 }
1903
1904no_link_interrupt:
a3c69fef
JB		 1905 if (!test_bit(__E1000_DOWN, &adapter->state))
1906 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1907
1908 return IRQ_HANDLED;
1909}
1910
8bb62869 1911static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1912{
1913 struct net_device *netdev = data;
1914 struct e1000_adapter *adapter = netdev_priv(netdev);
1915 struct e1000_hw *hw = &adapter->hw;
1916 struct e1000_ring *tx_ring = adapter->tx_ring;
1917
4662e82b
BA		 1918 adapter->total_tx_bytes = 0;
1919 adapter->total_tx_packets = 0;
1920
55aa6985 1921 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1922 /* Ring was not completely cleaned, so fire another interrupt */
1923 ew32(ICS, tx_ring->ims_val);
1924
1925 return IRQ_HANDLED;
1926}
1927
8bb62869 1928static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1929{
1930 struct net_device *netdev = data;
1931 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1932 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1933
1934 /* Write the ITR value calculated at the end of the
1935 * previous interrupt.
1936 */
55aa6985
BA		 1937 if (rx_ring->set_itr) {
1938 writel(1000000000 / (rx_ring->itr_val * 256),
1939 rx_ring->itr_register);
1940 rx_ring->set_itr = 0;
4662e82b
BA		 1941 }
1942
288379f0 1943 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1944 adapter->total_rx_bytes = 0;
1945 adapter->total_rx_packets = 0;
288379f0 1946 __napi_schedule(&adapter->napi);
4662e82b
BA		 1947 }
1948 return IRQ_HANDLED;
1949}
1950
1951/**
1952 * e1000_configure_msix - Configure MSI-X hardware
1953 *
1954 * e1000_configure_msix sets up the hardware to properly
1955 * generate MSI-X interrupts.
1956 **/
1957static void e1000_configure_msix(struct e1000_adapter *adapter)
1958{
1959 struct e1000_hw *hw = &adapter->hw;
1960 struct e1000_ring *rx_ring = adapter->rx_ring;
1961 struct e1000_ring *tx_ring = adapter->tx_ring;
1962 int vector = 0;
1963 u32 ctrl_ext, ivar = 0;
1964
1965 adapter->eiac_mask = 0;
1966
1967 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1968 if (hw->mac.type == e1000_82574) {
1969 u32 rfctl = er32(RFCTL);
1970 rfctl |= E1000_RFCTL_ACK_DIS;
1971 ew32(RFCTL, rfctl);
1972 }
1973
1974#define E1000_IVAR_INT_ALLOC_VALID 0x8
1975 /* Configure Rx vector */
1976 rx_ring->ims_val = E1000_IMS_RXQ0;
1977 adapter->eiac_mask |= rx_ring->ims_val;
1978 if (rx_ring->itr_val)
1979 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1980 rx_ring->itr_register);
4662e82b 1981 else
c5083cf6 1982 writel(1, rx_ring->itr_register);
4662e82b
BA		 1983 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1984
1985 /* Configure Tx vector */
1986 tx_ring->ims_val = E1000_IMS_TXQ0;
1987 vector++;
1988 if (tx_ring->itr_val)
1989 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1990 tx_ring->itr_register);
4662e82b 1991 else
c5083cf6 1992 writel(1, tx_ring->itr_register);
4662e82b
BA		 1993 adapter->eiac_mask |= tx_ring->ims_val;
1994 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1995
1996 /* set vector for Other Causes, e.g. link changes */
1997 vector++;
1998 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1999 if (rx_ring->itr_val)
2000 writel(1000000000 / (rx_ring->itr_val * 256),
2001 hw->hw_addr + E1000_EITR_82574(vector));
2002 else
2003 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2004
2005 /* Cause Tx interrupts on every write back */
2006 ivar |= (1 << 31);
2007
2008 ew32(IVAR, ivar);
2009
2010 /* enable MSI-X PBA support */
2011 ctrl_ext = er32(CTRL_EXT);
2012 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2013
2014 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2015 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2016 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2017 ew32(CTRL_EXT, ctrl_ext);
2018 e1e_flush();
2019}
2020
2021void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2022{
2023 if (adapter->msix_entries) {
2024 pci_disable_msix(adapter->pdev);
2025 kfree(adapter->msix_entries);
2026 adapter->msix_entries = NULL;
2027 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2028 pci_disable_msi(adapter->pdev);
2029 adapter->flags &= ~FLAG_MSI_ENABLED;
2030 }
4662e82b
BA		 2031}
2032
2033/**
2034 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2035 *
2036 * Attempt to configure interrupts using the best available
2037 * capabilities of the hardware and kernel.
2038 **/
2039void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2040{
2041 int err;
8e86acd7 2042 int i;
4662e82b
BA		 2043
2044 switch (adapter->int_mode) {
2045 case E1000E_INT_MODE_MSIX:
2046 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2047 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2048 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2049 sizeof(struct
2050 msix_entry),
2051 GFP_KERNEL);
4662e82b 2052 if (adapter->msix_entries) {
8e86acd7 2053 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2054 adapter->msix_entries[i].entry = i;
2055
2056 err = pci_enable_msix(adapter->pdev,
2057 adapter->msix_entries,
8e86acd7 2058 adapter->num_vectors);
b1cdfead 2059 if (err == 0)
4662e82b
BA		 2060 return;
2061 }
2062 /* MSI-X failed, so fall through and try MSI */
ef456f85 2063 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2064 e1000e_reset_interrupt_capability(adapter);
2065 }
2066 adapter->int_mode = E1000E_INT_MODE_MSI;
2067 /* Fall through */
2068 case E1000E_INT_MODE_MSI:
2069 if (!pci_enable_msi(adapter->pdev)) {
2070 adapter->flags |= FLAG_MSI_ENABLED;
2071 } else {
2072 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2073 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2074 }
2075 /* Fall through */
2076 case E1000E_INT_MODE_LEGACY:
2077 /* Don't do anything; this is the system default */
2078 break;
2079 }
8e86acd7
JK		 2080
2081 /* store the number of vectors being used */
2082 adapter->num_vectors = 1;
4662e82b
BA		 2083}
2084
2085/**
2086 * e1000_request_msix - Initialize MSI-X interrupts
2087 *
2088 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2089 * kernel.
2090 **/
2091static int e1000_request_msix(struct e1000_adapter *adapter)
2092{
2093 struct net_device *netdev = adapter->netdev;
2094 int err = 0, vector = 0;
2095
2096 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2097 snprintf(adapter->rx_ring->name,
2098 sizeof(adapter->rx_ring->name) - 1,
2099 "%s-rx-0", netdev->name);
4662e82b
BA		 2100 else
2101 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2102 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2103 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2104 netdev);
2105 if (err)
5015e53a 2106 return err;
c5083cf6
BA		 2107 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2108 E1000_EITR_82574(vector);
4662e82b
BA		 2109 adapter->rx_ring->itr_val = adapter->itr;
2110 vector++;
2111
2112 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2113 snprintf(adapter->tx_ring->name,
2114 sizeof(adapter->tx_ring->name) - 1,
2115 "%s-tx-0", netdev->name);
4662e82b
BA		 2116 else
2117 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2118 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2119 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2120 netdev);
2121 if (err)
5015e53a 2122 return err;
c5083cf6
BA		 2123 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2124 E1000_EITR_82574(vector);
4662e82b
BA		 2125 adapter->tx_ring->itr_val = adapter->itr;
2126 vector++;
2127
2128 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2129 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2130 if (err)
5015e53a 2131 return err;
4662e82b
BA		 2132
2133 e1000_configure_msix(adapter);
5015e53a 2134
4662e82b 2135 return 0;
4662e82b
BA		 2136}
2137
f8d59f78
BA		 2138/**
2139 * e1000_request_irq - initialize interrupts
2140 *
2141 * Attempts to configure interrupts using the best available
2142 * capabilities of the hardware and kernel.
2143 **/
bc7f75fa
AK		 2144static int e1000_request_irq(struct e1000_adapter *adapter)
2145{
2146 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2147 int err;
2148
4662e82b
BA		 2149 if (adapter->msix_entries) {
2150 err = e1000_request_msix(adapter);
2151 if (!err)
2152 return err;
2153 /* fall back to MSI */
2154 e1000e_reset_interrupt_capability(adapter);
2155 adapter->int_mode = E1000E_INT_MODE_MSI;
2156 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2157 }
4662e82b 2158 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2159 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2160 netdev->name, netdev);
2161 if (!err)
2162 return err;
bc7f75fa 2163
4662e82b
BA		 2164 /* fall back to legacy interrupt */
2165 e1000e_reset_interrupt_capability(adapter);
2166 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2167 }
2168
a0607fd3 2169 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2170 netdev->name, netdev);
2171 if (err)
2172 e_err("Unable to allocate interrupt, Error: %d\n", err);
2173
bc7f75fa
AK		 2174 return err;
2175}
2176
2177static void e1000_free_irq(struct e1000_adapter *adapter)
2178{
2179 struct net_device *netdev = adapter->netdev;
2180
4662e82b
BA		 2181 if (adapter->msix_entries) {
2182 int vector = 0;
2183
2184 free_irq(adapter->msix_entries[vector].vector, netdev);
2185 vector++;
2186
2187 free_irq(adapter->msix_entries[vector].vector, netdev);
2188 vector++;
2189
2190 /* Other Causes interrupt vector */
2191 free_irq(adapter->msix_entries[vector].vector, netdev);
2192 return;
bc7f75fa 2193 }
4662e82b
BA		 2194
2195 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2196}
2197
2198/**
2199 * e1000_irq_disable - Mask off interrupt generation on the NIC
2200 **/
2201static void e1000_irq_disable(struct e1000_adapter *adapter)
2202{
2203 struct e1000_hw *hw = &adapter->hw;
2204
bc7f75fa 2205 ew32(IMC, ~0);
4662e82b
BA		 2206 if (adapter->msix_entries)
2207 ew32(EIAC_82574, 0);
bc7f75fa 2208 e1e_flush();
8e86acd7
JK		 2209
2210 if (adapter->msix_entries) {
2211 int i;
2212 for (i = 0; i < adapter->num_vectors; i++)
2213 synchronize_irq(adapter->msix_entries[i].vector);
2214 } else {
2215 synchronize_irq(adapter->pdev->irq);
2216 }
bc7f75fa
AK		 2217}
2218
2219/**
2220 * e1000_irq_enable - Enable default interrupt generation settings
2221 **/
2222static void e1000_irq_enable(struct e1000_adapter *adapter)
2223{
2224 struct e1000_hw *hw = &adapter->hw;
2225
4662e82b
BA		 2226 if (adapter->msix_entries) {
2227 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2228 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2229 } else if (hw->mac.type == e1000_pch_lpt) {
2230 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2231 } else {
2232 ew32(IMS, IMS_ENABLE_MASK);
2233 }
74ef9c39 2234 e1e_flush();
bc7f75fa
AK		 2235}
2236
2237/**
31dbe5b4 2238 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2239 * @adapter: address of board private structure
2240 *
31dbe5b4 2241 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2242 * For ASF and Pass Through versions of f/w this means that
2243 * the driver is loaded. For AMT version (only with 82573)
2244 * of the f/w this means that the network i/f is open.
2245 **/
31dbe5b4 2246void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2247{
2248 struct e1000_hw *hw = &adapter->hw;
2249 u32 ctrl_ext;
2250 u32 swsm;
2251
2252 /* Let firmware know the driver has taken over */
2253 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2254 swsm = er32(SWSM);
2255 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2256 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2257 ctrl_ext = er32(CTRL_EXT);
ad68076e 2258 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2259 }
2260}
2261
2262/**
31dbe5b4 2263 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2264 * @adapter: address of board private structure
2265 *
31dbe5b4 2266 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2267 * For ASF and Pass Through versions of f/w this means that the
2268 * driver is no longer loaded. For AMT version (only with 82573) i
2269 * of the f/w this means that the network i/f is closed.
2270 *
2271 **/
31dbe5b4 2272void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2273{
2274 struct e1000_hw *hw = &adapter->hw;
2275 u32 ctrl_ext;
2276 u32 swsm;
2277
2278 /* Let firmware taken over control of h/w */
2279 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2280 swsm = er32(SWSM);
2281 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2282 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2283 ctrl_ext = er32(CTRL_EXT);
ad68076e 2284 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2285 }
2286}
2287
bc7f75fa 2288/**
49ce9c2c 2289 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2290 **/
2291static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2292 struct e1000_ring *ring)
2293{
2294 struct pci_dev *pdev = adapter->pdev;
2295
2296 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2297 GFP_KERNEL);
2298 if (!ring->desc)
2299 return -ENOMEM;
2300
2301 return 0;
2302}
2303
2304/**
2305 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2306 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2307 *
2308 * Return 0 on success, negative on failure
2309 **/
55aa6985 2310int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2311{
55aa6985 2312 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2313 int err = -ENOMEM, size;
2314
2315 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2316 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2317 if (!tx_ring->buffer_info)
2318 goto err;
bc7f75fa
AK		 2319
2320 /* round up to nearest 4K */
2321 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2322 tx_ring->size = ALIGN(tx_ring->size, 4096);
2323
2324 err = e1000_alloc_ring_dma(adapter, tx_ring);
2325 if (err)
2326 goto err;
2327
2328 tx_ring->next_to_use = 0;
2329 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2330
2331 return 0;
2332err:
2333 vfree(tx_ring->buffer_info);
44defeb3 2334 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2335 return err;
2336}
2337
2338/**
2339 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2340 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2341 *
2342 * Returns 0 on success, negative on failure
2343 **/
55aa6985 2344int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2345{
55aa6985 2346 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2347 struct e1000_buffer *buffer_info;
2348 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2349
2350 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2351 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2352 if (!rx_ring->buffer_info)
2353 goto err;
bc7f75fa 2354
47f44e40
AK		 2355 for (i = 0; i < rx_ring->count; i++) {
2356 buffer_info = &rx_ring->buffer_info[i];
2357 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2358 sizeof(struct e1000_ps_page),
2359 GFP_KERNEL);
2360 if (!buffer_info->ps_pages)
2361 goto err_pages;
2362 }
bc7f75fa
AK		 2363
2364 desc_len = sizeof(union e1000_rx_desc_packet_split);
2365
2366 /* Round up to nearest 4K */
2367 rx_ring->size = rx_ring->count * desc_len;
2368 rx_ring->size = ALIGN(rx_ring->size, 4096);
2369
2370 err = e1000_alloc_ring_dma(adapter, rx_ring);
2371 if (err)
47f44e40 2372 goto err_pages;
bc7f75fa
AK		 2373
2374 rx_ring->next_to_clean = 0;
2375 rx_ring->next_to_use = 0;
2376 rx_ring->rx_skb_top = NULL;
2377
2378 return 0;
47f44e40
AK		 2379
2380err_pages:
2381 for (i = 0; i < rx_ring->count; i++) {
2382 buffer_info = &rx_ring->buffer_info[i];
2383 kfree(buffer_info->ps_pages);
2384 }
bc7f75fa
AK		 2385err:
2386 vfree(rx_ring->buffer_info);
e9262447 2387 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2388 return err;
2389}
2390
2391/**
2392 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2393 * @tx_ring: Tx descriptor ring
bc7f75fa 2394 **/
55aa6985 2395static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2396{
55aa6985 2397 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2398 struct e1000_buffer *buffer_info;
2399 unsigned long size;
2400 unsigned int i;
2401
2402 for (i = 0; i < tx_ring->count; i++) {
2403 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2404 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2405 }
2406
3f0cfa3b 2407 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2408 size = sizeof(struct e1000_buffer) * tx_ring->count;
2409 memset(tx_ring->buffer_info, 0, size);
2410
2411 memset(tx_ring->desc, 0, tx_ring->size);
2412
2413 tx_ring->next_to_use = 0;
2414 tx_ring->next_to_clean = 0;
2415
c5083cf6 2416 writel(0, tx_ring->head);
bdc125f7
BA		 2417 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2418 e1000e_update_tdt_wa(tx_ring, 0);
2419 else
2420 writel(0, tx_ring->tail);
bc7f75fa
AK		 2421}
2422
2423/**
2424 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2425 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2426 *
2427 * Free all transmit software resources
2428 **/
55aa6985 2429void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2430{
55aa6985 2431 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2432 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2433
55aa6985 2434 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2435
2436 vfree(tx_ring->buffer_info);
2437 tx_ring->buffer_info = NULL;
2438
2439 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2440 tx_ring->dma);
2441 tx_ring->desc = NULL;
2442}
2443
2444/**
2445 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2446 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2447 *
2448 * Free all receive software resources
2449 **/
55aa6985 2450void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2451{
55aa6985 2452 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2453 struct pci_dev *pdev = adapter->pdev;
47f44e40 2454 int i;
bc7f75fa 2455
55aa6985 2456 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2457
b1cdfead 2458 for (i = 0; i < rx_ring->count; i++)
47f44e40 2459 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2460
bc7f75fa
AK		 2461 vfree(rx_ring->buffer_info);
2462 rx_ring->buffer_info = NULL;
2463
bc7f75fa
AK		 2464 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2465 rx_ring->dma);
2466 rx_ring->desc = NULL;
2467}
2468
2469/**
2470 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2471 * @adapter: pointer to adapter
2472 * @itr_setting: current adapter->itr
2473 * @packets: the number of packets during this measurement interval
2474 * @bytes: the number of bytes during this measurement interval
2475 *
bc7f75fa
AK		 2476 * Stores a new ITR value based on packets and byte
2477 * counts during the last interrupt. The advantage of per interrupt
2478 * computation is faster updates and more accurate ITR for the current
2479 * traffic pattern. Constants in this function were computed
2480 * based on theoretical maximum wire speed and thresholds were set based
2481 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2482 * while increasing bulk throughput. This functionality is controlled
2483 * by the InterruptThrottleRate module parameter.
bc7f75fa 2484 **/
8bb62869 2485static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2486{
2487 unsigned int retval = itr_setting;
2488
2489 if (packets == 0)
5015e53a 2490 return itr_setting;
bc7f75fa
AK		 2491
2492 switch (itr_setting) {
2493 case lowest_latency:
2494 /* handle TSO and jumbo frames */
362e20ca 2495 if (bytes / packets > 8000)
bc7f75fa 2496 retval = bulk_latency;
b1cdfead 2497 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2498 retval = low_latency;
bc7f75fa
AK		 2499 break;
2500 case low_latency: /* 50 usec aka 20000 ints/s */
2501 if (bytes > 10000) {
2502 /* this if handles the TSO accounting */
362e20ca 2503 if (bytes / packets > 8000)
bc7f75fa 2504 retval = bulk_latency;
362e20ca 2505 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2506 retval = bulk_latency;
b1cdfead 2507 else if ((packets > 35))
bc7f75fa 2508 retval = lowest_latency;
362e20ca 2509 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2510 retval = bulk_latency;
2511 } else if (packets <= 2 && bytes < 512) {
2512 retval = lowest_latency;
2513 }
2514 break;
2515 case bulk_latency: /* 250 usec aka 4000 ints/s */
2516 if (bytes > 25000) {
b1cdfead 2517 if (packets > 35)
bc7f75fa 2518 retval = low_latency;
bc7f75fa
AK		 2519 } else if (bytes < 6000) {
2520 retval = low_latency;
2521 }
2522 break;
2523 }
2524
bc7f75fa
AK		 2525 return retval;
2526}
2527
2528static void e1000_set_itr(struct e1000_adapter *adapter)
2529{
bc7f75fa
AK		 2530 u16 current_itr;
2531 u32 new_itr = adapter->itr;
2532
2533 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2534 if (adapter->link_speed != SPEED_1000) {
2535 current_itr = 0;
2536 new_itr = 4000;
2537 goto set_itr_now;
2538 }
2539
828bac87
BA		 2540 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2541 new_itr = 0;
2542 goto set_itr_now;
2543 }
2544
8bb62869
BA		 2545 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2546 adapter->total_tx_packets,
2547 adapter->total_tx_bytes);
bc7f75fa
AK		 2548 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2549 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2550 adapter->tx_itr = low_latency;
2551
8bb62869
BA		 2552 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2553 adapter->total_rx_packets,
2554 adapter->total_rx_bytes);
bc7f75fa
AK		 2555 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2556 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2557 adapter->rx_itr = low_latency;
2558
2559 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2560
bc7f75fa 2561 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2562 switch (current_itr) {
bc7f75fa
AK		 2563 case lowest_latency:
2564 new_itr = 70000;
2565 break;
2566 case low_latency:
2567 new_itr = 20000; /* aka hwitr = ~200 */
2568 break;
2569 case bulk_latency:
2570 new_itr = 4000;
2571 break;
2572 default:
2573 break;
2574 }
2575
2576set_itr_now:
2577 if (new_itr != adapter->itr) {
e921eb1a 2578 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2579 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2580 * increasing
2581 */
bc7f75fa 2582 new_itr = new_itr > adapter->itr ?
f0ff4398 2583 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2584 adapter->itr = new_itr;
4662e82b
BA		 2585 adapter->rx_ring->itr_val = new_itr;
2586 if (adapter->msix_entries)
2587 adapter->rx_ring->set_itr = 1;
2588 else
e3d14b08 2589 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2590 }
2591}
2592
22a4cca2
MV		 2593/**
2594 * e1000e_write_itr - write the ITR value to the appropriate registers
2595 * @adapter: address of board private structure
2596 * @itr: new ITR value to program
2597 *
2598 * e1000e_write_itr determines if the adapter is in MSI-X mode
2599 * and, if so, writes the EITR registers with the ITR value.
2600 * Otherwise, it writes the ITR value into the ITR register.
2601 **/
2602void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2603{
2604 struct e1000_hw *hw = &adapter->hw;
2605 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2606
2607 if (adapter->msix_entries) {
2608 int vector;
2609
2610 for (vector = 0; vector < adapter->num_vectors; vector++)
2611 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2612 } else {
2613 ew32(ITR, new_itr);
2614 }
2615}
2616
4662e82b
BA		 2617/**
2618 * e1000_alloc_queues - Allocate memory for all rings
2619 * @adapter: board private structure to initialize
2620 **/
9f9a12f8 2621static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2622{
55aa6985
BA		 2623 int size = sizeof(struct e1000_ring);
2624
2625 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2626 if (!adapter->tx_ring)
2627 goto err;
55aa6985
BA		 2628 adapter->tx_ring->count = adapter->tx_ring_count;
2629 adapter->tx_ring->adapter = adapter;
4662e82b 2630
55aa6985 2631 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2632 if (!adapter->rx_ring)
2633 goto err;
55aa6985
BA		 2634 adapter->rx_ring->count = adapter->rx_ring_count;
2635 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2636
2637 return 0;
2638err:
2639 e_err("Unable to allocate memory for queues\n");
2640 kfree(adapter->rx_ring);
2641 kfree(adapter->tx_ring);
2642 return -ENOMEM;
2643}
2644
bc7f75fa 2645/**
c58c8a78 2646 * e1000e_poll - NAPI Rx polling callback
ad68076e 2647 * @napi: struct associated with this polling callback
c58c8a78 2648 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2649 **/
c58c8a78 2650static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2651{
c58c8a78
BA		 2652 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2653 napi);
4662e82b 2654 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2655 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2656 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2657
4cf1653a 2658 adapter = netdev_priv(poll_dev);
bc7f75fa 2659
c58c8a78
BA		 2660 if (!adapter->msix_entries ||
2661 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2662 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2663
c58c8a78 2664 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2665
12d04a3c 2666 if (!tx_cleaned)
c58c8a78 2667 work_done = weight;
bc7f75fa 2668
c58c8a78
BA		 2669 /* If weight not fully consumed, exit the polling mode */
2670 if (work_done < weight) {
bc7f75fa
AK		 2671 if (adapter->itr_setting & 3)
2672 e1000_set_itr(adapter);
288379f0 2673 napi_complete(napi);
a3c69fef
JB		 2674 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2675 if (adapter->msix_entries)
2676 ew32(IMS, adapter->rx_ring->ims_val);
2677 else
2678 e1000_irq_enable(adapter);
2679 }
bc7f75fa
AK		 2680 }
2681
2682 return work_done;
2683}
2684
8e586137 2685static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2686{
2687 struct e1000_adapter *adapter = netdev_priv(netdev);
2688 struct e1000_hw *hw = &adapter->hw;
2689 u32 vfta, index;
2690
2691 /* don't update vlan cookie if already programmed */
2692 if ((adapter->hw.mng_cookie.status &
2693 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2694 (vid == adapter->mng_vlan_id))
8e586137 2695 return 0;
caaddaf8 2696
bc7f75fa 2697 /* add VID to filter table */
caaddaf8
BA		 2698 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2699 index = (vid >> 5) & 0x7F;
2700 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2701 vfta |= (1 << (vid & 0x1F));
2702 hw->mac.ops.write_vfta(hw, index, vfta);
2703 }
86d70e53
JK		 2704
2705 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2706
2707 return 0;
bc7f75fa
AK		 2708}
2709
8e586137 2710static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2711{
2712 struct e1000_adapter *adapter = netdev_priv(netdev);
2713 struct e1000_hw *hw = &adapter->hw;
2714 u32 vfta, index;
2715
bc7f75fa
AK		 2716 if ((adapter->hw.mng_cookie.status &
2717 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2718 (vid == adapter->mng_vlan_id)) {
2719 /* release control to f/w */
31dbe5b4 2720 e1000e_release_hw_control(adapter);
8e586137 2721 return 0;
bc7f75fa
AK		 2722 }
2723
2724 /* remove VID from filter table */
caaddaf8
BA		 2725 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2726 index = (vid >> 5) & 0x7F;
2727 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2728 vfta &= ~(1 << (vid & 0x1F));
2729 hw->mac.ops.write_vfta(hw, index, vfta);
2730 }
86d70e53
JK		 2731
2732 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2733
2734 return 0;
bc7f75fa
AK		 2735}
2736
86d70e53
JK		 2737/**
2738 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2739 * @adapter: board private structure to initialize
2740 **/
2741static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2742{
2743 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2744 struct e1000_hw *hw = &adapter->hw;
2745 u32 rctl;
bc7f75fa 2746
86d70e53
JK		 2747 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2748 /* disable VLAN receive filtering */
2749 rctl = er32(RCTL);
2750 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2751 ew32(RCTL, rctl);
2752
2753 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2754 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2755 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2756 }
bc7f75fa
AK		 2757 }
2758}
2759
86d70e53
JK		 2760/**
2761 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2762 * @adapter: board private structure to initialize
2763 **/
2764static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2765{
2766 struct e1000_hw *hw = &adapter->hw;
2767 u32 rctl;
2768
2769 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2770 /* enable VLAN receive filtering */
2771 rctl = er32(RCTL);
2772 rctl |= E1000_RCTL_VFE;
2773 rctl &= ~E1000_RCTL_CFIEN;
2774 ew32(RCTL, rctl);
2775 }
2776}
bc7f75fa 2777
86d70e53
JK		 2778/**
2779 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2780 * @adapter: board private structure to initialize
2781 **/
2782static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2783{
bc7f75fa 2784 struct e1000_hw *hw = &adapter->hw;
86d70e53 2785 u32 ctrl;
bc7f75fa 2786
86d70e53
JK		 2787 /* disable VLAN tag insert/strip */
2788 ctrl = er32(CTRL);
2789 ctrl &= ~E1000_CTRL_VME;
2790 ew32(CTRL, ctrl);
2791}
bc7f75fa 2792
86d70e53
JK		 2793/**
2794 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2795 * @adapter: board private structure to initialize
2796 **/
2797static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2798{
2799 struct e1000_hw *hw = &adapter->hw;
2800 u32 ctrl;
bc7f75fa 2801
86d70e53
JK		 2802 /* enable VLAN tag insert/strip */
2803 ctrl = er32(CTRL);
2804 ctrl |= E1000_CTRL_VME;
2805 ew32(CTRL, ctrl);
2806}
bc7f75fa 2807
86d70e53
JK		 2808static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2809{
2810 struct net_device *netdev = adapter->netdev;
2811 u16 vid = adapter->hw.mng_cookie.vlan_id;
2812 u16 old_vid = adapter->mng_vlan_id;
2813
2814 if (adapter->hw.mng_cookie.status &
2815 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2816 e1000_vlan_rx_add_vid(netdev, vid);
2817 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2818 }
2819
86d70e53
JK		 2820 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2821 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2822}
2823
2824static void e1000_restore_vlan(struct e1000_adapter *adapter)
2825{
2826 u16 vid;
2827
86d70e53 2828 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2829
86d70e53 2830 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
f0ff4398 2831 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2832}
2833
cd791618 2834static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2835{
2836 struct e1000_hw *hw = &adapter->hw;
cd791618 2837 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2838
2839 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2840 return;
2841
2842 manc = er32(MANC);
2843
e921eb1a 2844 /* enable receiving management packets to the host. this will probably
bc7f75fa 2845 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2846 * the packets will be handled on SMBUS
2847 */
bc7f75fa
AK		 2848 manc |= E1000_MANC_EN_MNG2HOST;
2849 manc2h = er32(MANC2H);
cd791618
BA		 2850
2851 switch (hw->mac.type) {
2852 default:
2853 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2854 break;
2855 case e1000_82574:
2856 case e1000_82583:
e921eb1a 2857 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2858 * if so, enable it.
2859 */
2860 for (i = 0, j = 0; i < 8; i++) {
2861 mdef = er32(MDEF(i));
2862
2863 /* Ignore filters with anything other than IPMI ports */
3b21b508 2864 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2865 continue;
2866
2867 /* Enable this decision filter in MANC2H */
2868 if (mdef)
2869 manc2h |= (1 << i);
2870
2871 j |= mdef;
2872 }
2873
2874 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2875 break;
2876
2877 /* Create new decision filter in an empty filter */
2878 for (i = 0, j = 0; i < 8; i++)
2879 if (er32(MDEF(i)) == 0) {
2880 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2881 E1000_MDEF_PORT_664));
2882 manc2h |= (1 << 1);
2883 j++;
2884 break;
2885 }
2886
2887 if (!j)
2888 e_warn("Unable to create IPMI pass-through filter\n");
2889 break;
2890 }
2891
bc7f75fa
AK		 2892 ew32(MANC2H, manc2h);
2893 ew32(MANC, manc);
2894}
2895
2896/**
af667a29 2897 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2898 * @adapter: board private structure
2899 *
2900 * Configure the Tx unit of the MAC after a reset.
2901 **/
2902static void e1000_configure_tx(struct e1000_adapter *adapter)
2903{
2904 struct e1000_hw *hw = &adapter->hw;
2905 struct e1000_ring *tx_ring = adapter->tx_ring;
2906 u64 tdba;
c550b121 2907 u32 tdlen, tarc;
bc7f75fa
AK		 2908
2909 /* Setup the HW Tx Head and Tail descriptor pointers */
2910 tdba = tx_ring->dma;
2911 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2912 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2913 ew32(TDBAH(0), (tdba >> 32));
2914 ew32(TDLEN(0), tdlen);
2915 ew32(TDH(0), 0);
2916 ew32(TDT(0), 0);
2917 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2918 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2919
bc7f75fa
AK		 2920 /* Set the Tx Interrupt Delay register */
2921 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2922 /* Tx irq moderation */
bc7f75fa
AK		 2923 ew32(TADV, adapter->tx_abs_int_delay);
2924
3a3b7586
JB		 2925 if (adapter->flags2 & FLAG2_DMA_BURST) {
2926 u32 txdctl = er32(TXDCTL(0));
2927 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2928 E1000_TXDCTL_WTHRESH);
e921eb1a 2929 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2930 * hardware to use the bus more efficiently in bursts, depends
2931 * on the tx_int_delay to be enabled,
8edc0e62 2932 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2933 * hthresh = 1 ==> prefetch when one or more available
2934 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2935 * BEWARE: this seems to work but should be considered first if
af667a29 2936 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2937 */
2938 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2939 ew32(TXDCTL(0), txdctl);
3a3b7586 2940 }
56032be7
BA		 2941 /* erratum work around: set txdctl the same for both queues */
2942 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2943
bc7f75fa 2944 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2945 tarc = er32(TARC(0));
e921eb1a 2946 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2947 * gigabit link later
2948 */
bc7f75fa
AK		 2949#define SPEED_MODE_BIT (1 << 21)
2950 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2951 ew32(TARC(0), tarc);
bc7f75fa
AK		 2952 }
2953
2954 /* errata: program both queues to unweighted RR */
2955 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2956 tarc = er32(TARC(0));
bc7f75fa 2957 tarc |= 1;
e9ec2c0f
JK		 2958 ew32(TARC(0), tarc);
2959 tarc = er32(TARC(1));
bc7f75fa 2960 tarc |= 1;
e9ec2c0f 2961 ew32(TARC(1), tarc);
bc7f75fa
AK		 2962 }
2963
bc7f75fa
AK		 2964 /* Setup Transmit Descriptor Settings for eop descriptor */
2965 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2966
2967 /* only set IDE if we are delaying interrupts using the timers */
2968 if (adapter->tx_int_delay)
2969 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2970
2971 /* enable Report Status bit */
2972 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2973
57cde763 2974 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2975}
2976
2977/**
2978 * e1000_setup_rctl - configure the receive control registers
2979 * @adapter: Board private structure
2980 **/
2981#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2982 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2983static void e1000_setup_rctl(struct e1000_adapter *adapter)
2984{
2985 struct e1000_hw *hw = &adapter->hw;
2986 u32 rctl, rfctl;
bc7f75fa
AK		 2987 u32 pages = 0;
2988
2fbe4526
BA		 2989 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2990 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2991 s32 ret_val;
2992
2993 if (adapter->netdev->mtu > ETH_DATA_LEN)
2994 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2995 else
2996 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2997
2998 if (ret_val)
2999 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 3000 }
3001
bc7f75fa
AK		 3002 /* Program MC offset vector base */
3003 rctl = er32(RCTL);
3004 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3005 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3006 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3007 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3008
3009 /* Do not Store bad packets */
3010 rctl &= ~E1000_RCTL_SBP;
3011
3012 /* Enable Long Packet receive */
3013 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3014 rctl &= ~E1000_RCTL_LPE;
3015 else
3016 rctl |= E1000_RCTL_LPE;
3017
eb7c3adb
JK		 3018 /* Some systems expect that the CRC is included in SMBUS traffic. The
3019 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3020 * host memory when this is enabled
3021 */
3022 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3023 rctl |= E1000_RCTL_SECRC;
5918bd88 3024
a4f58f54
BA		 3025 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3026 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3027 u16 phy_data;
3028
3029 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3030 phy_data &= 0xfff8;
3031 phy_data |= (1 << 2);
3032 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3033
3034 e1e_rphy(hw, 22, &phy_data);
3035 phy_data &= 0x0fff;
3036 phy_data |= (1 << 14);
3037 e1e_wphy(hw, 0x10, 0x2823);
3038 e1e_wphy(hw, 0x11, 0x0003);
3039 e1e_wphy(hw, 22, phy_data);
3040 }
3041
bc7f75fa
AK		 3042 /* Setup buffer sizes */
3043 rctl &= ~E1000_RCTL_SZ_4096;
3044 rctl |= E1000_RCTL_BSEX;
3045 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3046 case 2048:
3047 default:
3048 rctl |= E1000_RCTL_SZ_2048;
3049 rctl &= ~E1000_RCTL_BSEX;
3050 break;
3051 case 4096:
3052 rctl |= E1000_RCTL_SZ_4096;
3053 break;
3054 case 8192:
3055 rctl |= E1000_RCTL_SZ_8192;
3056 break;
3057 case 16384:
3058 rctl |= E1000_RCTL_SZ_16384;
3059 break;
3060 }
3061
5f450212
BA		 3062 /* Enable Extended Status in all Receive Descriptors */
3063 rfctl = er32(RFCTL);
3064 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3065 ew32(RFCTL, rfctl);
5f450212 3066
e921eb1a 3067 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3068 * header is placed in skb->data and the packet data is
3069 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3070 * In the case of a non-split, skb->data is linearly filled,
3071 * followed by the page buffers. Therefore, skb->data is
3072 * sized to hold the largest protocol header.
3073 *
3074 * allocations using alloc_page take too long for regular MTU
3075 * so only enable packet split for jumbo frames
3076 *
3077 * Using pages when the page size is greater than 16k wastes
3078 * a lot of memory, since we allocate 3 pages at all times
3079 * per packet.
3080 */
bc7f75fa 3081 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3082 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3083 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3084 else
3085 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3086
3087 if (adapter->rx_ps_pages) {
90da0669
BA		 3088 u32 psrctl = 0;
3089
140a7480
AK		 3090 /* Enable Packet split descriptors */
3091 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 3092
3093 psrctl |= adapter->rx_ps_bsize0 >>
3094 E1000_PSRCTL_BSIZE0_SHIFT;
3095
3096 switch (adapter->rx_ps_pages) {
3097 case 3:
3098 psrctl |= PAGE_SIZE <<
3099 E1000_PSRCTL_BSIZE3_SHIFT;
3100 case 2:
3101 psrctl |= PAGE_SIZE <<
3102 E1000_PSRCTL_BSIZE2_SHIFT;
3103 case 1:
3104 psrctl |= PAGE_SIZE >>
3105 E1000_PSRCTL_BSIZE1_SHIFT;
3106 break;
3107 }
3108
3109 ew32(PSRCTL, psrctl);
3110 }
3111
cf955e6c
BG		 3112 /* This is useful for sniffing bad packets. */
3113 if (adapter->netdev->features & NETIF_F_RXALL) {
3114 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3115 * in e1000e_set_rx_mode
3116 */
cf955e6c
BG		 3117 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3118 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3119 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3120
3121 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3122 E1000_RCTL_DPF | /* Allow filtered pause */
3123 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3124 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3125 * and that breaks VLANs.
3126 */
3127 }
3128
bc7f75fa 3129 ew32(RCTL, rctl);
318a94d6 3130 /* just started the receive unit, no need to restart */
12d43f7d 3131 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3132}
3133
3134/**
3135 * e1000_configure_rx - Configure Receive Unit after Reset
3136 * @adapter: board private structure
3137 *
3138 * Configure the Rx unit of the MAC after a reset.
3139 **/
3140static void e1000_configure_rx(struct e1000_adapter *adapter)
3141{
3142 struct e1000_hw *hw = &adapter->hw;
3143 struct e1000_ring *rx_ring = adapter->rx_ring;
3144 u64 rdba;
3145 u32 rdlen, rctl, rxcsum, ctrl_ext;
3146
3147 if (adapter->rx_ps_pages) {
3148 /* this is a 32 byte descriptor */
3149 rdlen = rx_ring->count *
af667a29 3150 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3151 adapter->clean_rx = e1000_clean_rx_irq_ps;
3152 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3153 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3154 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3155 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3156 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3157 } else {
5f450212 3158 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3159 adapter->clean_rx = e1000_clean_rx_irq;
3160 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3161 }
3162
3163 /* disable receives while setting up the descriptors */
3164 rctl = er32(RCTL);
7f99ae63
BA		 3165 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3166 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3167 e1e_flush();
1bba4386 3168 usleep_range(10000, 20000);
bc7f75fa 3169
3a3b7586 3170 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3171 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3172 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3173 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3174 * granularity = 01
3175 * wthresh = 04,
3176 * hthresh = 04,
3177 * pthresh = 0x20
3178 */
3179 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3180 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3181
e921eb1a 3182 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3183 * the value was not set by the user via module options
3184 */
3185 if (adapter->rx_int_delay == DEFAULT_RDTR)
3186 adapter->rx_int_delay = BURST_RDTR;
3187 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3188 adapter->rx_abs_int_delay = BURST_RADV;
3189 }
3190
bc7f75fa
AK		 3191 /* set the Receive Delay Timer Register */
3192 ew32(RDTR, adapter->rx_int_delay);
3193
3194 /* irq moderation */
3195 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3196 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3197 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3198
3199 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3200 /* Auto-Mask interrupts upon ICR access */
3201 ctrl_ext |= E1000_CTRL_EXT_IAME;
3202 ew32(IAM, 0xffffffff);
3203 ew32(CTRL_EXT, ctrl_ext);
3204 e1e_flush();
3205
e921eb1a 3206 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3207 * the Base and Length of the Rx Descriptor Ring
3208 */
bc7f75fa 3209 rdba = rx_ring->dma;
1e36052e
BA		 3210 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3211 ew32(RDBAH(0), (rdba >> 32));
3212 ew32(RDLEN(0), rdlen);
3213 ew32(RDH(0), 0);
3214 ew32(RDT(0), 0);
3215 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3216 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3217
3218 /* Enable Receive Checksum Offload for TCP and UDP */
3219 rxcsum = er32(RXCSUM);
2e1706f2 3220 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3221 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3222 else
bc7f75fa 3223 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3224 ew32(RXCSUM, rxcsum);
3225
3e35d991
BA		 3226 /* With jumbo frames, excessive C-state transition latencies result
3227 * in dropped transactions.
3228 */
3229 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3230 u32 lat =
3231 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3232 adapter->max_frame_size) * 8 / 1000;
3233
3234 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3235 u32 rxdctl = er32(RXDCTL(0));
3236 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3237 }
3e35d991
BA		 3238
3239 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3240 } else {
3241 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3242 PM_QOS_DEFAULT_VALUE);
97ac8cae 3243 }
bc7f75fa
AK		 3244
3245 /* Enable Receives */
3246 ew32(RCTL, rctl);
3247}
3248
3249/**
ef9b965a
JB		 3250 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3251 * @netdev: network interface device structure
bc7f75fa 3252 *
ef9b965a
JB		 3253 * Writes multicast address list to the MTA hash table.
3254 * Returns: -ENOMEM on failure
3255 * 0 on no addresses written
3256 * X on writing X addresses to MTA
3257 */
3258static int e1000e_write_mc_addr_list(struct net_device *netdev)
3259{
3260 struct e1000_adapter *adapter = netdev_priv(netdev);
3261 struct e1000_hw *hw = &adapter->hw;
3262 struct netdev_hw_addr *ha;
3263 u8 *mta_list;
3264 int i;
3265
3266 if (netdev_mc_empty(netdev)) {
3267 /* nothing to program, so clear mc list */
3268 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3269 return 0;
3270 }
3271
3272 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3273 if (!mta_list)
3274 return -ENOMEM;
3275
3276 /* update_mc_addr_list expects a packed array of only addresses. */
3277 i = 0;
3278 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3279 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3280
3281 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3282 kfree(mta_list);
3283
3284 return netdev_mc_count(netdev);
3285}
3286
3287/**
3288 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3289 * @netdev: network interface device structure
bc7f75fa 3290 *
ef9b965a
JB		 3291 * Writes unicast address list to the RAR table.
3292 * Returns: -ENOMEM on failure/insufficient address space
3293 * 0 on no addresses written
3294 * X on writing X addresses to the RAR table
bc7f75fa 3295 **/
ef9b965a 3296static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3297{
ef9b965a
JB		 3298 struct e1000_adapter *adapter = netdev_priv(netdev);
3299 struct e1000_hw *hw = &adapter->hw;
3300 unsigned int rar_entries = hw->mac.rar_entry_count;
3301 int count = 0;
3302
3303 /* save a rar entry for our hardware address */
3304 rar_entries--;
3305
3306 /* save a rar entry for the LAA workaround */
3307 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3308 rar_entries--;
3309
3310 /* return ENOMEM indicating insufficient memory for addresses */
3311 if (netdev_uc_count(netdev) > rar_entries)
3312 return -ENOMEM;
3313
3314 if (!netdev_uc_empty(netdev) && rar_entries) {
3315 struct netdev_hw_addr *ha;
3316
e921eb1a 3317 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3318 * combining
3319 */
3320 netdev_for_each_uc_addr(ha, netdev) {
3321 if (!rar_entries)
3322 break;
69e1e019 3323 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3324 count++;
3325 }
3326 }
3327
3328 /* zero out the remaining RAR entries not used above */
3329 for (; rar_entries > 0; rar_entries--) {
3330 ew32(RAH(rar_entries), 0);
3331 ew32(RAL(rar_entries), 0);
3332 }
3333 e1e_flush();
3334
3335 return count;
bc7f75fa
AK		 3336}
3337
3338/**
ef9b965a 3339 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3340 * @netdev: network interface device structure
3341 *
ef9b965a
JB		 3342 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3343 * address list or the network interface flags are updated. This routine is
3344 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3345 * promiscuous mode, and all-multi behavior.
3346 **/
ef9b965a 3347static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3348{
3349 struct e1000_adapter *adapter = netdev_priv(netdev);
3350 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3351 u32 rctl;
bc7f75fa
AK		 3352
3353 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3354 rctl = er32(RCTL);
3355
ef9b965a
JB		 3356 /* clear the affected bits */
3357 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3358
bc7f75fa
AK		 3359 if (netdev->flags & IFF_PROMISC) {
3360 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3361 /* Do not hardware filter VLANs in promisc mode */
3362 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3363 } else {
ef9b965a 3364 int count;
3d3a1676 3365
746b9f02
PM		 3366 if (netdev->flags & IFF_ALLMULTI) {
3367 rctl |= E1000_RCTL_MPE;
746b9f02 3368 } else {
e921eb1a 3369 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3370 * then we should just turn on promiscuous mode so
3371 * that we can at least receive multicast traffic
3372 */
3373 count = e1000e_write_mc_addr_list(netdev);
3374 if (count < 0)
3375 rctl |= E1000_RCTL_MPE;
746b9f02 3376 }
86d70e53 3377 e1000e_vlan_filter_enable(adapter);
e921eb1a 3378 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3379 * sufficient space to store all the addresses then enable
3380 * unicast promiscuous mode
bc7f75fa 3381 */
ef9b965a
JB		 3382 count = e1000e_write_uc_addr_list(netdev);
3383 if (count < 0)
3384 rctl |= E1000_RCTL_UPE;
bc7f75fa 3385 }
86d70e53 3386
ef9b965a
JB		 3387 ew32(RCTL, rctl);
3388
86d70e53
JK		 3389 if (netdev->features & NETIF_F_HW_VLAN_RX)
3390 e1000e_vlan_strip_enable(adapter);
3391 else
3392 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3393}
3394
70495a50
BA		 3395static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3396{
3397 struct e1000_hw *hw = &adapter->hw;
3398 u32 mrqc, rxcsum;
3399 int i;
3400 static const u32 rsskey[10] = {
3401 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3402 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3403 };
3404
3405 /* Fill out hash function seed */
3406 for (i = 0; i < 10; i++)
3407 ew32(RSSRK(i), rsskey[i]);
3408
3409 /* Direct all traffic to queue 0 */
3410 for (i = 0; i < 32; i++)
3411 ew32(RETA(i), 0);
3412
e921eb1a 3413 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3414 * descriptor on writeback.
3415 */
3416 rxcsum = er32(RXCSUM);
3417 rxcsum |= E1000_RXCSUM_PCSD;
3418
3419 ew32(RXCSUM, rxcsum);
3420
3421 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3422 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6 |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3426
3427 ew32(MRQC, mrqc);
3428}
3429
b67e1913
BA		 3430/**
3431 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3432 * @adapter: board private structure
3433 * @timinca: pointer to returned time increment attributes
3434 *
3435 * Get attributes for incrementing the System Time Register SYSTIML/H at
3436 * the default base frequency, and set the cyclecounter shift value.
3437 **/
d89777bf 3438s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3439{
3440 struct e1000_hw *hw = &adapter->hw;
3441 u32 incvalue, incperiod, shift;
3442
3443 /* Make sure clock is enabled on I217 before checking the frequency */
3444 if ((hw->mac.type == e1000_pch_lpt) &&
3445 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3446 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3447 u32 fextnvm7 = er32(FEXTNVM7);
3448
3449 if (!(fextnvm7 & (1 << 0))) {
3450 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3451 e1e_flush();
3452 }
3453 }
3454
3455 switch (hw->mac.type) {
3456 case e1000_pch2lan:
3457 case e1000_pch_lpt:
3458 /* On I217, the clock frequency is 25MHz or 96MHz as
3459 * indicated by the System Clock Frequency Indication
3460 */
3461 if ((hw->mac.type != e1000_pch_lpt) ||
3462 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3463 /* Stable 96MHz frequency */
3464 incperiod = INCPERIOD_96MHz;
3465 incvalue = INCVALUE_96MHz;
3466 shift = INCVALUE_SHIFT_96MHz;
3467 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3468 break;
3469 }
3470 /* fall-through */
3471 case e1000_82574:
3472 case e1000_82583:
3473 /* Stable 25MHz frequency */
3474 incperiod = INCPERIOD_25MHz;
3475 incvalue = INCVALUE_25MHz;
3476 shift = INCVALUE_SHIFT_25MHz;
3477 adapter->cc.shift = shift;
3478 break;
3479 default:
3480 return -EINVAL;
3481 }
3482
3483 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3484 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3485
3486 return 0;
3487}
3488
3489/**
3490 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3491 * @adapter: board private structure
3492 *
3493 * Outgoing time stamping can be enabled and disabled. Play nice and
3494 * disable it when requested, although it shouldn't cause any overhead
3495 * when no packet needs it. At most one packet in the queue may be
3496 * marked for time stamping, otherwise it would be impossible to tell
3497 * for sure to which packet the hardware time stamp belongs.
3498 *
3499 * Incoming time stamping has to be configured via the hardware filters.
3500 * Not all combinations are supported, in particular event type has to be
3501 * specified. Matching the kind of event packet is not supported, with the
3502 * exception of "all V2 events regardless of level 2 or 4".
3503 **/
3504static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3505{
3506 struct e1000_hw *hw = &adapter->hw;
3507 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3508 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3509 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3510 u32 rxmtrl = 0;
3511 u16 rxudp = 0;
3512 bool is_l4 = false;
3513 bool is_l2 = false;
b67e1913
BA		 3514 u32 regval;
3515 s32 ret_val;
3516
3517 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3518 return -EINVAL;
3519
3520 /* flags reserved for future extensions - must be zero */
3521 if (config->flags)
3522 return -EINVAL;
3523
3524 switch (config->tx_type) {
3525 case HWTSTAMP_TX_OFF:
3526 tsync_tx_ctl = 0;
3527 break;
3528 case HWTSTAMP_TX_ON:
3529 break;
3530 default:
3531 return -ERANGE;
3532 }
3533
3534 switch (config->rx_filter) {
3535 case HWTSTAMP_FILTER_NONE:
3536 tsync_rx_ctl = 0;
3537 break;
d89777bf
BA		 3538 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3539 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3540 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3541 is_l4 = true;
3542 break;
3543 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3544 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3545 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3546 is_l4 = true;
3547 break;
3548 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3549 /* Also time stamps V2 L2 Path Delay Request/Response */
3550 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3551 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3552 is_l2 = true;
3553 break;
3554 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3555 /* Also time stamps V2 L2 Path Delay Request/Response. */
3556 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3557 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3558 is_l2 = true;
3559 break;
3560 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3561 /* Hardware cannot filter just V2 L4 Sync messages;
3562 * fall-through to V2 (both L2 and L4) Sync.
3563 */
3564 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3565 /* Also time stamps V2 Path Delay Request/Response. */
3566 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3567 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3568 is_l2 = true;
3569 is_l4 = true;
3570 break;
3571 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3572 /* Hardware cannot filter just V2 L4 Delay Request messages;
3573 * fall-through to V2 (both L2 and L4) Delay Request.
3574 */
3575 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3576 /* Also time stamps V2 Path Delay Request/Response. */
3577 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3578 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3579 is_l2 = true;
3580 is_l4 = true;
3581 break;
3582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3583 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3584 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3585 * fall-through to all V2 (both L2 and L4) Events.
3586 */
3587 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3588 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3589 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3590 is_l2 = true;
3591 is_l4 = true;
3592 break;
3593 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3594 /* For V1, the hardware can only filter Sync messages or
3595 * Delay Request messages but not both so fall-through to
3596 * time stamp all packets.
3597 */
b67e1913 3598 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3599 is_l2 = true;
3600 is_l4 = true;
b67e1913
BA		 3601 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3602 config->rx_filter = HWTSTAMP_FILTER_ALL;
3603 break;
3604 default:
3605 return -ERANGE;
3606 }
3607
3608 /* enable/disable Tx h/w time stamping */
3609 regval = er32(TSYNCTXCTL);
3610 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3611 regval |= tsync_tx_ctl;
3612 ew32(TSYNCTXCTL, regval);
3613 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3614 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3615 e_err("Timesync Tx Control register not set as expected\n");
3616 return -EAGAIN;
3617 }
3618
3619 /* enable/disable Rx h/w time stamping */
3620 regval = er32(TSYNCRXCTL);
3621 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3622 regval |= tsync_rx_ctl;
3623 ew32(TSYNCRXCTL, regval);
3624 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3625 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3626 (regval & (E1000_TSYNCRXCTL_ENABLED |
3627 E1000_TSYNCRXCTL_TYPE_MASK))) {
3628 e_err("Timesync Rx Control register not set as expected\n");
3629 return -EAGAIN;
3630 }
3631
d89777bf
BA		 3632 /* L2: define ethertype filter for time stamped packets */
3633 if (is_l2)
3634 rxmtrl |= ETH_P_1588;
3635
3636 /* define which PTP packets get time stamped */
3637 ew32(RXMTRL, rxmtrl);
3638
3639 /* Filter by destination port */
3640 if (is_l4) {
3641 rxudp = PTP_EV_PORT;
3642 cpu_to_be16s(&rxudp);
3643 }
3644 ew32(RXUDP, rxudp);
3645
3646 e1e_flush();
3647
b67e1913 3648 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3649 er32(RXSTMPH);
3650 er32(TXSTMPH);
b67e1913
BA		 3651
3652 /* Get and set the System Time Register SYSTIM base frequency */
3653 ret_val = e1000e_get_base_timinca(adapter, &regval);
3654 if (ret_val)
3655 return ret_val;
3656 ew32(TIMINCA, regval);
3657
3658 /* reset the ns time counter */
3659 timecounter_init(&adapter->tc, &adapter->cc,
3660 ktime_to_ns(ktime_get_real()));
3661
3662 return 0;
3663}
3664
bc7f75fa 3665/**
ad68076e 3666 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3667 * @adapter: private board structure
3668 **/
3669static void e1000_configure(struct e1000_adapter *adapter)
3670{
55aa6985
BA		 3671 struct e1000_ring *rx_ring = adapter->rx_ring;
3672
ef9b965a 3673 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3674
3675 e1000_restore_vlan(adapter);
cd791618 3676 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3677
3678 e1000_configure_tx(adapter);
70495a50
BA		 3679
3680 if (adapter->netdev->features & NETIF_F_RXHASH)
3681 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3682 e1000_setup_rctl(adapter);
3683 e1000_configure_rx(adapter);
55aa6985 3684 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3685}
3686
3687/**
3688 * e1000e_power_up_phy - restore link in case the phy was powered down
3689 * @adapter: address of board private structure
3690 *
3691 * The phy may be powered down to save power and turn off link when the
3692 * driver is unloaded and wake on lan is not enabled (among others)
3693 * *** this routine MUST be followed by a call to e1000e_reset ***
3694 **/
3695void e1000e_power_up_phy(struct e1000_adapter *adapter)
3696{
17f208de
BA		 3697 if (adapter->hw.phy.ops.power_up)
3698 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3699
3700 adapter->hw.mac.ops.setup_link(&adapter->hw);
3701}
3702
3703/**
3704 * e1000_power_down_phy - Power down the PHY
3705 *
17f208de
BA		 3706 * Power down the PHY so no link is implied when interface is down.
3707 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3708 */
3709static void e1000_power_down_phy(struct e1000_adapter *adapter)
3710{
bc7f75fa 3711 /* WoL is enabled */
23b66e2b 3712 if (adapter->wol)
bc7f75fa
AK		 3713 return;
3714
17f208de
BA		 3715 if (adapter->hw.phy.ops.power_down)
3716 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3717}
3718
3719/**
3720 * e1000e_reset - bring the hardware into a known good state
3721 *
3722 * This function boots the hardware and enables some settings that
3723 * require a configuration cycle of the hardware - those cannot be
3724 * set/changed during runtime. After reset the device needs to be
ad68076e 3725 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3726 */
3727void e1000e_reset(struct e1000_adapter *adapter)
3728{
3729 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3730 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3731 struct e1000_hw *hw = &adapter->hw;
3732 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3733 u32 pba = adapter->pba;
bc7f75fa
AK		 3734 u16 hwm;
3735
ad68076e 3736 /* reset Packet Buffer Allocation to default */
318a94d6 3737 ew32(PBA, pba);
df762464 3738
318a94d6 3739 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3740 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3741 * large enough to accommodate two full transmit packets,
3742 * rounded up to the next 1KB and expressed in KB. Likewise,
3743 * the Rx FIFO should be large enough to accommodate at least
3744 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3745 * expressed in KB.
3746 */
df762464 3747 pba = er32(PBA);
bc7f75fa 3748 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3749 tx_space = pba >> 16;
bc7f75fa 3750 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3751 pba &= 0xffff;
e921eb1a 3752 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3753 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3754 */
3755 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3756 sizeof(struct e1000_tx_desc) -
3757 ETH_FCS_LEN) * 2;
3758 min_tx_space = ALIGN(min_tx_space, 1024);
3759 min_tx_space >>= 10;
3760 /* software strips receive CRC, so leave room for it */
318a94d6 3761 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3762 min_rx_space = ALIGN(min_rx_space, 1024);
3763 min_rx_space >>= 10;
3764
e921eb1a 3765 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3766 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3767 * allocation, take space away from current Rx allocation
3768 */
df762464
AK		 3769 if ((tx_space < min_tx_space) &&
3770 ((min_tx_space - tx_space) < pba)) {
3771 pba -= min_tx_space - tx_space;
bc7f75fa 3772
e921eb1a 3773 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3774 * adjustment
ad68076e 3775 */
79d4e908 3776 if (pba < min_rx_space)
df762464 3777 pba = min_rx_space;
bc7f75fa 3778 }
df762464
AK		 3779
3780 ew32(PBA, pba);
bc7f75fa
AK		 3781 }
3782
e921eb1a 3783 /* flow control settings
ad68076e 3784 *
38eb394e 3785 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3786 * (or the size used for early receive) above it in the Rx FIFO.
3787 * Set it to the lower of:
3788 * - 90% of the Rx FIFO size, and
38eb394e 3789 * - the full Rx FIFO size minus one full frame
ad68076e 3790 */
d3738bb8
BA		 3791 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3792 fc->pause_time = 0xFFFF;
3793 else
3794 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3795 fc->send_xon = true;
d3738bb8
BA		 3796 fc->current_mode = fc->requested_mode;
3797
3798 switch (hw->mac.type) {
79d4e908
BA		 3799 case e1000_ich9lan:
3800 case e1000_ich10lan:
3801 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3802 pba = 14;
3803 ew32(PBA, pba);
3804 fc->high_water = 0x2800;
3805 fc->low_water = fc->high_water - 8;
3806 break;
3807 }
3808 /* fall-through */
d3738bb8 3809 default:
79d4e908
BA		 3810 hwm = min(((pba << 10) * 9 / 10),
3811 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3812
3813 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3814 fc->low_water = fc->high_water - 8;
3815 break;
3816 case e1000_pchlan:
e921eb1a 3817 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3818 * loads. If hangs persist, try disabling Tx flow control.
3819 */
3820 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3821 fc->high_water = 0x3500;
3822 fc->low_water = 0x1500;
3823 } else {
3824 fc->high_water = 0x5000;
3825 fc->low_water = 0x3000;
3826 }
a305595b 3827 fc->refresh_time = 0x1000;
d3738bb8
BA		 3828 break;
3829 case e1000_pch2lan:
2fbe4526 3830 case e1000_pch_lpt:
d3738bb8 3831 fc->refresh_time = 0x0400;
347b5201
BA		 3832
3833 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3834 fc->high_water = 0x05C20;
3835 fc->low_water = 0x05048;
3836 fc->pause_time = 0x0650;
3837 break;
828bac87 3838 }
347b5201
BA		 3839
3840 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3841 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3842 break;
38eb394e 3843 }
bc7f75fa 3844
e921eb1a 3845 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3846 * maximum size per Tx descriptor limited only to the transmit
3847 * allocation of the packet buffer minus 96 bytes with an upper
3848 * limit of 24KB due to receive synchronization limitations.
3849 */
3850 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3851 24 << 10);
3852
e921eb1a 3853 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3854 * fit in receive buffer.
828bac87
BA		 3855 */
3856 if (adapter->itr_setting & 0x3) {
79d4e908 3857 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3858 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3859 dev_info(&adapter->pdev->dev,
17e813ec 3860 "Interrupt Throttle Rate off\n");
828bac87 3861 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3862 e1000e_write_itr(adapter, 0);
828bac87
BA		 3863 }
3864 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3865 dev_info(&adapter->pdev->dev,
17e813ec 3866 "Interrupt Throttle Rate on\n");
828bac87
BA		 3867 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3868 adapter->itr = 20000;
22a4cca2 3869 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3870 }
3871 }
3872
bc7f75fa
AK		 3873 /* Allow time for pending master requests to run */
3874 mac->ops.reset_hw(hw);
97ac8cae 3875
e921eb1a 3876 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3877 * that the network interface is in control
3878 */
c43bc57e 3879 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3880 e1000e_get_hw_control(adapter);
97ac8cae 3881
bc7f75fa
AK		 3882 ew32(WUC, 0);
3883
3884 if (mac->ops.init_hw(hw))
44defeb3 3885 e_err("Hardware Error\n");
bc7f75fa
AK		 3886
3887 e1000_update_mng_vlan(adapter);
3888
3889 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3890 ew32(VET, ETH_P_8021Q);
3891
3892 e1000e_reset_adaptive(hw);
31dbe5b4 3893
b67e1913
BA		 3894 /* initialize systim and reset the ns time counter */
3895 e1000e_config_hwtstamp(adapter);
3896
31dbe5b4
BA		 3897 if (!netif_running(adapter->netdev) &&
3898 !test_bit(__E1000_TESTING, &adapter->state)) {
3899 e1000_power_down_phy(adapter);
3900 return;
3901 }
3902
bc7f75fa
AK		 3903 e1000_get_phy_info(hw);
3904
918d7197
BA		 3905 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3906 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3907 u16 phy_data = 0;
e921eb1a 3908 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3909 * the return value of this function because there is nothing
ad68076e
BA		 3910 * different we would do if it failed
3911 */
bc7f75fa
AK		 3912 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3913 phy_data &= ~IGP02E1000_PM_SPD;
3914 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3915 }
bc7f75fa
AK		 3916}
3917
3918int e1000e_up(struct e1000_adapter *adapter)
3919{
3920 struct e1000_hw *hw = &adapter->hw;
3921
3922 /* hardware has been reset, we need to reload some things */
3923 e1000_configure(adapter);
3924
3925 clear_bit(__E1000_DOWN, &adapter->state);
3926
4662e82b
BA		 3927 if (adapter->msix_entries)
3928 e1000_configure_msix(adapter);
bc7f75fa
AK		 3929 e1000_irq_enable(adapter);
3930
400484fa 3931 netif_start_queue(adapter->netdev);
4cb9be7a 3932
bc7f75fa 3933 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3934 if (adapter->msix_entries)
3935 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3936 else
3937 ew32(ICS, E1000_ICS_LSC);
3938
bc7f75fa
AK		 3939 return 0;
3940}
3941
713b3c9e
JB		 3942static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3943{
3944 struct e1000_hw *hw = &adapter->hw;
3945
3946 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3947 return;
3948
3949 /* flush pending descriptor writebacks to memory */
3950 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3951 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3952
3953 /* execute the writes immediately */
3954 e1e_flush();
bf03085f 3955
e921eb1a 3956 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3957 * write is successful
3958 */
3959 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3960 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3961
3962 /* execute the writes immediately */
3963 e1e_flush();
3964}
3965
67fd4fcb
JK		 3966static void e1000e_update_stats(struct e1000_adapter *adapter);
3967
bc7f75fa
AK		 3968void e1000e_down(struct e1000_adapter *adapter)
3969{
3970 struct net_device *netdev = adapter->netdev;
3971 struct e1000_hw *hw = &adapter->hw;
3972 u32 tctl, rctl;
3973
e921eb1a 3974 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3975 * reschedule our watchdog timer
3976 */
bc7f75fa
AK		 3977 set_bit(__E1000_DOWN, &adapter->state);
3978
3979 /* disable receives in the hardware */
3980 rctl = er32(RCTL);
7f99ae63
BA		 3981 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3982 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3983 /* flush and sleep below */
3984
4cb9be7a 3985 netif_stop_queue(netdev);
bc7f75fa
AK		 3986
3987 /* disable transmits in the hardware */
3988 tctl = er32(TCTL);
3989 tctl &= ~E1000_TCTL_EN;
3990 ew32(TCTL, tctl);
7f99ae63 3991
bc7f75fa
AK		 3992 /* flush both disables and wait for them to finish */
3993 e1e_flush();
1bba4386 3994 usleep_range(10000, 20000);
bc7f75fa 3995
bc7f75fa
AK		 3996 e1000_irq_disable(adapter);
3997
3998 del_timer_sync(&adapter->watchdog_timer);
3999 del_timer_sync(&adapter->phy_info_timer);
4000
bc7f75fa 4001 netif_carrier_off(netdev);
67fd4fcb
JK		 4002
4003 spin_lock(&adapter->stats64_lock);
4004 e1000e_update_stats(adapter);
4005 spin_unlock(&adapter->stats64_lock);
4006
400484fa 4007 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4008 e1000_clean_tx_ring(adapter->tx_ring);
4009 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4010
bc7f75fa
AK		 4011 adapter->link_speed = 0;
4012 adapter->link_duplex = 0;
4013
52cc3086
JK		 4014 if (!pci_channel_offline(adapter->pdev))
4015 e1000e_reset(adapter);
713b3c9e 4016
e921eb1a 4017 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 4018 * pci_disable_device here.
4019 */
4020}
4021
4022void e1000e_reinit_locked(struct e1000_adapter *adapter)
4023{
4024 might_sleep();
4025 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4026 usleep_range(1000, 2000);
bc7f75fa
AK		 4027 e1000e_down(adapter);
4028 e1000e_up(adapter);
4029 clear_bit(__E1000_RESETTING, &adapter->state);
4030}
4031
b67e1913
BA		 4032/**
4033 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4034 * @cc: cyclecounter structure
4035 **/
4036static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4037{
4038 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4039 cc);
4040 struct e1000_hw *hw = &adapter->hw;
4041 cycle_t systim;
4042
4043 /* latch SYSTIMH on read of SYSTIML */
4044 systim = (cycle_t)er32(SYSTIML);
4045 systim |= (cycle_t)er32(SYSTIMH) << 32;
4046
4047 return systim;
4048}
4049
bc7f75fa
AK		 4050/**
4051 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4052 * @adapter: board private structure to initialize
4053 *
4054 * e1000_sw_init initializes the Adapter private data structure.
4055 * Fields are initialized based on PCI device information and
4056 * OS network device settings (MTU size).
4057 **/
9f9a12f8 4058static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4059{
bc7f75fa
AK		 4060 struct net_device *netdev = adapter->netdev;
4061
4062 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4063 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4064 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4065 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4066 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4067 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4068
67fd4fcb
JK		 4069 spin_lock_init(&adapter->stats64_lock);
4070
4662e82b 4071 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4072
4662e82b
BA		 4073 if (e1000_alloc_queues(adapter))
4074 return -ENOMEM;
bc7f75fa 4075
b67e1913
BA		 4076 /* Setup hardware time stamping cyclecounter */
4077 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4078 adapter->cc.read = e1000e_cyclecounter_read;
4079 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4080 adapter->cc.mult = 1;
4081 /* cc.shift set in e1000e_get_base_tininca() */
4082
4083 spin_lock_init(&adapter->systim_lock);
4084 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4085 }
4086
bc7f75fa 4087 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4088 e1000_irq_disable(adapter);
4089
bc7f75fa
AK		 4090 set_bit(__E1000_DOWN, &adapter->state);
4091 return 0;
bc7f75fa
AK		 4092}
4093
f8d59f78
BA		 4094/**
4095 * e1000_intr_msi_test - Interrupt Handler
4096 * @irq: interrupt number
4097 * @data: pointer to a network interface device structure
4098 **/
8bb62869 4099static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4100{
4101 struct net_device *netdev = data;
4102 struct e1000_adapter *adapter = netdev_priv(netdev);
4103 struct e1000_hw *hw = &adapter->hw;
4104 u32 icr = er32(ICR);
4105
3bb99fe2 4106 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4107 if (icr & E1000_ICR_RXSEQ) {
4108 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4109 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4110 * interrupt is handled.
4111 */
f8d59f78
BA		 4112 wmb();
4113 }
4114
4115 return IRQ_HANDLED;
4116}
4117
4118/**
4119 * e1000_test_msi_interrupt - Returns 0 for successful test
4120 * @adapter: board private struct
4121 *
4122 * code flow taken from tg3.c
4123 **/
4124static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4125{
4126 struct net_device *netdev = adapter->netdev;
4127 struct e1000_hw *hw = &adapter->hw;
4128 int err;
4129
4130 /* poll_enable hasn't been called yet, so don't need disable */
4131 /* clear any pending events */
4132 er32(ICR);
4133
4134 /* free the real vector and request a test handler */
4135 e1000_free_irq(adapter);
4662e82b 4136 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4137
4138 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4139 * MSI irq handler will unset this flag
4140 */
f8d59f78
BA		 4141 adapter->flags |= FLAG_MSI_TEST_FAILED;
4142
4143 err = pci_enable_msi(adapter->pdev);
4144 if (err)
4145 goto msi_test_failed;
4146
a0607fd3 4147 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4148 netdev->name, netdev);
4149 if (err) {
4150 pci_disable_msi(adapter->pdev);
4151 goto msi_test_failed;
4152 }
4153
e921eb1a 4154 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4155 * interrupt.
4156 */
f8d59f78
BA		 4157 wmb();
4158
4159 e1000_irq_enable(adapter);
4160
4161 /* fire an unusual interrupt on the test handler */
4162 ew32(ICS, E1000_ICS_RXSEQ);
4163 e1e_flush();
569a3aff 4164 msleep(100);
f8d59f78
BA		 4165
4166 e1000_irq_disable(adapter);
4167
bc76329d 4168 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4169
4170 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4171 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4172 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4173 } else {
068e8a30 4174 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4175 }
f8d59f78
BA		 4176
4177 free_irq(adapter->pdev->irq, netdev);
4178 pci_disable_msi(adapter->pdev);
4179
f8d59f78 4180msi_test_failed:
4662e82b 4181 e1000e_set_interrupt_capability(adapter);
068e8a30 4182 return e1000_request_irq(adapter);
f8d59f78
BA		 4183}
4184
4185/**
4186 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4187 * @adapter: board private struct
4188 *
4189 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4190 **/
4191static int e1000_test_msi(struct e1000_adapter *adapter)
4192{
4193 int err;
4194 u16 pci_cmd;
4195
4196 if (!(adapter->flags & FLAG_MSI_ENABLED))
4197 return 0;
4198
4199 /* disable SERR in case the MSI write causes a master abort */
4200 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4201 if (pci_cmd & PCI_COMMAND_SERR)
4202 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4203 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4204
4205 err = e1000_test_msi_interrupt(adapter);
4206
36f2407f
DN		 4207 /* re-enable SERR */
4208 if (pci_cmd & PCI_COMMAND_SERR) {
4209 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4210 pci_cmd |= PCI_COMMAND_SERR;
4211 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4212 }
f8d59f78 4213
f8d59f78
BA		 4214 return err;
4215}
4216
bc7f75fa
AK		 4217/**
4218 * e1000_open - Called when a network interface is made active
4219 * @netdev: network interface device structure
4220 *
4221 * Returns 0 on success, negative value on failure
4222 *
4223 * The open entry point is called when a network interface is made
4224 * active by the system (IFF_UP). At this point all resources needed
4225 * for transmit and receive operations are allocated, the interrupt
4226 * handler is registered with the OS, the watchdog timer is started,
4227 * and the stack is notified that the interface is ready.
4228 **/
4229static int e1000_open(struct net_device *netdev)
4230{
4231 struct e1000_adapter *adapter = netdev_priv(netdev);
4232 struct e1000_hw *hw = &adapter->hw;
23606cf5 4233 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4234 int err;
4235
4236 /* disallow open during test */
4237 if (test_bit(__E1000_TESTING, &adapter->state))
4238 return -EBUSY;
4239
23606cf5
RW		 4240 pm_runtime_get_sync(&pdev->dev);
4241
9c563d20
JB		 4242 netif_carrier_off(netdev);
4243
bc7f75fa 4244 /* allocate transmit descriptors */
55aa6985 4245 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4246 if (err)
4247 goto err_setup_tx;
4248
4249 /* allocate receive descriptors */
55aa6985 4250 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4251 if (err)
4252 goto err_setup_rx;
4253
e921eb1a 4254 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4255 * interface is now open and reset the part to a known state.
4256 */
4257 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4258 e1000e_get_hw_control(adapter);
11b08be8
BA		 4259 e1000e_reset(adapter);
4260 }
4261
bc7f75fa
AK		 4262 e1000e_power_up_phy(adapter);
4263
4264 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4265 if ((adapter->hw.mng_cookie.status &
4266 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4267 e1000_update_mng_vlan(adapter);
4268
79d4e908 4269 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4270 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4271 PM_QOS_DEFAULT_VALUE);
c128ec29 4272
e921eb1a 4273 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4274 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4275 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4276 * clean_rx handler before we do so.
4277 */
bc7f75fa
AK		 4278 e1000_configure(adapter);
4279
4280 err = e1000_request_irq(adapter);
4281 if (err)
4282 goto err_req_irq;
4283
e921eb1a 4284 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4285 * ignore e1000e MSI messages, which means we need to test our MSI
4286 * interrupt now
4287 */
4662e82b 4288 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4289 err = e1000_test_msi(adapter);
4290 if (err) {
4291 e_err("Interrupt allocation failed\n");
4292 goto err_req_irq;
4293 }
4294 }
4295
bc7f75fa
AK		 4296 /* From here on the code is the same as e1000e_up() */
4297 clear_bit(__E1000_DOWN, &adapter->state);
4298
4299 napi_enable(&adapter->napi);
4300
4301 e1000_irq_enable(adapter);
4302
09357b00 4303 adapter->tx_hang_recheck = false;
4cb9be7a 4304 netif_start_queue(netdev);
d55b53ff 4305
23606cf5
RW		 4306 adapter->idle_check = true;
4307 pm_runtime_put(&pdev->dev);
4308
bc7f75fa 4309 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4310 if (adapter->msix_entries)
4311 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4312 else
4313 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4314
4315 return 0;
4316
4317err_req_irq:
31dbe5b4 4318 e1000e_release_hw_control(adapter);
bc7f75fa 4319 e1000_power_down_phy(adapter);
55aa6985 4320 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4321err_setup_rx:
55aa6985 4322 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4323err_setup_tx:
4324 e1000e_reset(adapter);
23606cf5 4325 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4326
4327 return err;
4328}
4329
4330/**
4331 * e1000_close - Disables a network interface
4332 * @netdev: network interface device structure
4333 *
4334 * Returns 0, this is not allowed to fail
4335 *
4336 * The close entry point is called when an interface is de-activated
4337 * by the OS. The hardware is still under the drivers control, but
4338 * needs to be disabled. A global MAC reset is issued to stop the
4339 * hardware, and all transmit and receive resources are freed.
4340 **/
4341static int e1000_close(struct net_device *netdev)
4342{
4343 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4344 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4345 int count = E1000_CHECK_RESET_COUNT;
4346
4347 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4348 usleep_range(10000, 20000);
bc7f75fa
AK		 4349
4350 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4351
4352 pm_runtime_get_sync(&pdev->dev);
4353
5f4a780d
BA		 4354 napi_disable(&adapter->napi);
4355
23606cf5
RW		 4356 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4357 e1000e_down(adapter);
4358 e1000_free_irq(adapter);
4359 }
bc7f75fa 4360 e1000_power_down_phy(adapter);
bc7f75fa 4361
55aa6985
BA		 4362 e1000e_free_tx_resources(adapter->tx_ring);
4363 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4364
e921eb1a 4365 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4366 * the same ID is registered on the host OS (let 8021q kill it)
4367 */
86d70e53
JK		 4368 if (adapter->hw.mng_cookie.status &
4369 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4370 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4371
e921eb1a 4372 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4373 * interface is now closed
4374 */
31dbe5b4
BA		 4375 if ((adapter->flags & FLAG_HAS_AMT) &&
4376 !test_bit(__E1000_TESTING, &adapter->state))
4377 e1000e_release_hw_control(adapter);
bc7f75fa 4378
3e35d991 4379 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4380
23606cf5
RW		 4381 pm_runtime_put_sync(&pdev->dev);
4382
bc7f75fa
AK		 4383 return 0;
4384}
fc830b78 4385
bc7f75fa
AK		 4386/**
4387 * e1000_set_mac - Change the Ethernet Address of the NIC
4388 * @netdev: network interface device structure
4389 * @p: pointer to an address structure
4390 *
4391 * Returns 0 on success, negative on failure
4392 **/
4393static int e1000_set_mac(struct net_device *netdev, void *p)
4394{
4395 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4396 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4397 struct sockaddr *addr = p;
4398
4399 if (!is_valid_ether_addr(addr->sa_data))
4400 return -EADDRNOTAVAIL;
4401
4402 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4403 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4404
69e1e019 4405 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4406
4407 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4408 /* activate the work around */
4409 e1000e_set_laa_state_82571(&adapter->hw, 1);
4410
e921eb1a 4411 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4412 * between the time RAR[0] gets clobbered and the time it
4413 * gets fixed (in e1000_watchdog), the actual LAA is in one
4414 * of the RARs and no incoming packets directed to this port
4415 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4416 * RAR[14]
4417 */
69e1e019
BA		 4418 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4419 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4420 }
4421
4422 return 0;
4423}
4424
a8f88ff5
JB		 4425/**
4426 * e1000e_update_phy_task - work thread to update phy
4427 * @work: pointer to our work struct
4428 *
4429 * this worker thread exists because we must acquire a
4430 * semaphore to read the phy, which we could msleep while
4431 * waiting for it, and we can't msleep in a timer.
4432 **/
4433static void e1000e_update_phy_task(struct work_struct *work)
4434{
4435 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4436 struct e1000_adapter,
4437 update_phy_task);
615b32af
JB		 4438
4439 if (test_bit(__E1000_DOWN, &adapter->state))
4440 return;
4441
a8f88ff5
JB		 4442 e1000_get_phy_info(&adapter->hw);
4443}
4444
e921eb1a
BA		 4445/**
4446 * e1000_update_phy_info - timre call-back to update PHY info
4447 * @data: pointer to adapter cast into an unsigned long
4448 *
ad68076e
BA		 4449 * Need to wait a few seconds after link up to get diagnostic information from
4450 * the phy
e921eb1a 4451 **/
bc7f75fa
AK		 4452static void e1000_update_phy_info(unsigned long data)
4453{
53aa82da 4454 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4455
4456 if (test_bit(__E1000_DOWN, &adapter->state))
4457 return;
4458
a8f88ff5 4459 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4460}
4461
8c7bbb92
BA		 4462/**
4463 * e1000e_update_phy_stats - Update the PHY statistics counters
4464 * @adapter: board private structure
2b6b168d
BA		 4465 *
4466 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4467 **/
4468static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4469{
4470 struct e1000_hw *hw = &adapter->hw;
4471 s32 ret_val;
4472 u16 phy_data;
4473
4474 ret_val = hw->phy.ops.acquire(hw);
4475 if (ret_val)
4476 return;
4477
e921eb1a 4478 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4479 * If not, set to the page with the PHY status registers.
4480 */
2b6b168d 4481 hw->phy.addr = 1;
8c7bbb92
BA		 4482 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4483 &phy_data);
4484 if (ret_val)
4485 goto release;
2b6b168d
BA		 4486 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4487 ret_val = hw->phy.ops.set_page(hw,
4488 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4489 if (ret_val)
4490 goto release;
4491 }
4492
8c7bbb92 4493 /* Single Collision Count */
2b6b168d
BA		 4494 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4495 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4496 if (!ret_val)
4497 adapter->stats.scc += phy_data;
4498
4499 /* Excessive Collision Count */
2b6b168d
BA		 4500 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4501 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4502 if (!ret_val)
4503 adapter->stats.ecol += phy_data;
4504
4505 /* Multiple Collision Count */
2b6b168d
BA		 4506 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4507 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4508 if (!ret_val)
4509 adapter->stats.mcc += phy_data;
4510
4511 /* Late Collision Count */
2b6b168d
BA		 4512 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4513 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4514 if (!ret_val)
4515 adapter->stats.latecol += phy_data;
4516
4517 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4518 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4519 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4520 if (!ret_val)
4521 hw->mac.collision_delta = phy_data;
4522
4523 /* Defer Count */
2b6b168d
BA		 4524 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4525 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4526 if (!ret_val)
4527 adapter->stats.dc += phy_data;
4528
4529 /* Transmit with no CRS */
2b6b168d
BA		 4530 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4531 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4532 if (!ret_val)
4533 adapter->stats.tncrs += phy_data;
4534
4535release:
4536 hw->phy.ops.release(hw);
4537}
4538
bc7f75fa
AK		 4539/**
4540 * e1000e_update_stats - Update the board statistics counters
4541 * @adapter: board private structure
4542 **/
67fd4fcb 4543static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4544{
7274c20f 4545 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4546 struct e1000_hw *hw = &adapter->hw;
4547 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4548
e921eb1a 4549 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4550 * connection is down.
4551 */
4552 if (adapter->link_speed == 0)
4553 return;
4554 if (pci_channel_offline(pdev))
4555 return;
4556
bc7f75fa
AK		 4557 adapter->stats.crcerrs += er32(CRCERRS);
4558 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4559 adapter->stats.gorc += er32(GORCL);
4560 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4561 adapter->stats.bprc += er32(BPRC);
4562 adapter->stats.mprc += er32(MPRC);
4563 adapter->stats.roc += er32(ROC);
4564
bc7f75fa 4565 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4566
4567 /* Half-duplex statistics */
4568 if (adapter->link_duplex == HALF_DUPLEX) {
4569 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4570 e1000e_update_phy_stats(adapter);
4571 } else {
4572 adapter->stats.scc += er32(SCC);
4573 adapter->stats.ecol += er32(ECOL);
4574 adapter->stats.mcc += er32(MCC);
4575 adapter->stats.latecol += er32(LATECOL);
4576 adapter->stats.dc += er32(DC);
4577
4578 hw->mac.collision_delta = er32(COLC);
4579
4580 if ((hw->mac.type != e1000_82574) &&
4581 (hw->mac.type != e1000_82583))
4582 adapter->stats.tncrs += er32(TNCRS);
4583 }
4584 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4585 }
8c7bbb92 4586
bc7f75fa
AK		 4587 adapter->stats.xonrxc += er32(XONRXC);
4588 adapter->stats.xontxc += er32(XONTXC);
4589 adapter->stats.xoffrxc += er32(XOFFRXC);
4590 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4591 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4592 adapter->stats.gotc += er32(GOTCL);
4593 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4594 adapter->stats.rnbc += er32(RNBC);
4595 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4596
4597 adapter->stats.mptc += er32(MPTC);
4598 adapter->stats.bptc += er32(BPTC);
4599
4600 /* used for adaptive IFS */
4601
4602 hw->mac.tx_packet_delta = er32(TPT);
4603 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4604
4605 adapter->stats.algnerrc += er32(ALGNERRC);
4606 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4607 adapter->stats.cexterr += er32(CEXTERR);
4608 adapter->stats.tsctc += er32(TSCTC);
4609 adapter->stats.tsctfc += er32(TSCTFC);
4610
bc7f75fa 4611 /* Fill out the OS statistics structure */
7274c20f
AK		 4612 netdev->stats.multicast = adapter->stats.mprc;
4613 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4614
4615 /* Rx Errors */
4616
e921eb1a 4617 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4618 * our own version based on RUC and ROC
4619 */
7274c20f 4620 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4621 adapter->stats.crcerrs + adapter->stats.algnerrc +
4622 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4623 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4624 adapter->stats.roc;
7274c20f
AK		 4625 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4626 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4627 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4628
4629 /* Tx Errors */
f0ff4398 4630 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4631 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4632 netdev->stats.tx_window_errors = adapter->stats.latecol;
4633 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4634
4635 /* Tx Dropped needs to be maintained elsewhere */
4636
bc7f75fa
AK		 4637 /* Management Stats */
4638 adapter->stats.mgptc += er32(MGTPTC);
4639 adapter->stats.mgprc += er32(MGTPRC);
4640 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4641
4642 /* Correctable ECC Errors */
4643 if (hw->mac.type == e1000_pch_lpt) {
4644 u32 pbeccsts = er32(PBECCSTS);
4645 adapter->corr_errors +=
4646 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4647 adapter->uncorr_errors +=
4648 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4649 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4650 }
bc7f75fa
AK		 4651}
4652
7c25769f
BA		 4653/**
4654 * e1000_phy_read_status - Update the PHY register status snapshot
4655 * @adapter: board private structure
4656 **/
4657static void e1000_phy_read_status(struct e1000_adapter *adapter)
4658{
4659 struct e1000_hw *hw = &adapter->hw;
4660 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4661
4662 if ((er32(STATUS) & E1000_STATUS_LU) &&
4663 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4664 int ret_val;
4665
c2ade1a4
BA		 4666 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4667 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4668 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4669 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4670 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4671 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4672 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4673 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4674 if (ret_val)
44defeb3 4675 e_warn("Error reading PHY register\n");
7c25769f 4676 } else {
e921eb1a 4677 /* Do not read PHY registers if link is not up
7c25769f
BA		 4678 * Set values to typical power-on defaults
4679 */
4680 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4681 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4682 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4683 BMSR_ERCAP);
4684 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4685 ADVERTISE_ALL | ADVERTISE_CSMA);
4686 phy->lpa = 0;
4687 phy->expansion = EXPANSION_ENABLENPAGE;
4688 phy->ctrl1000 = ADVERTISE_1000FULL;
4689 phy->stat1000 = 0;
4690 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4691 }
7c25769f
BA		 4692}
4693
bc7f75fa
AK		 4694static void e1000_print_link_info(struct e1000_adapter *adapter)
4695{
bc7f75fa
AK		 4696 struct e1000_hw *hw = &adapter->hw;
4697 u32 ctrl = er32(CTRL);
4698
8f12fe86 4699 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4700 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4701 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4702 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4703 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4704 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4705 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4706}
4707
0c6bdb30 4708static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4709{
4710 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4711 bool link_active = false;
318a94d6
JK		 4712 s32 ret_val = 0;
4713
e921eb1a 4714 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4715 * Rx sequence error interrupt. get_link_status will stay
4716 * false until the check_for_link establishes link
4717 * for copper adapters ONLY
4718 */
4719 switch (hw->phy.media_type) {
4720 case e1000_media_type_copper:
4721 if (hw->mac.get_link_status) {
4722 ret_val = hw->mac.ops.check_for_link(hw);
4723 link_active = !hw->mac.get_link_status;
4724 } else {
3db1cd5c 4725 link_active = true;
318a94d6
JK		 4726 }
4727 break;
4728 case e1000_media_type_fiber:
4729 ret_val = hw->mac.ops.check_for_link(hw);
4730 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4731 break;
4732 case e1000_media_type_internal_serdes:
4733 ret_val = hw->mac.ops.check_for_link(hw);
4734 link_active = adapter->hw.mac.serdes_has_link;
4735 break;
4736 default:
4737 case e1000_media_type_unknown:
4738 break;
4739 }
4740
4741 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4742 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4743 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4744 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4745 }
4746
4747 return link_active;
4748}
4749
4750static void e1000e_enable_receives(struct e1000_adapter *adapter)
4751{
4752 /* make sure the receive unit is started */
4753 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4754 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4755 struct e1000_hw *hw = &adapter->hw;
4756 u32 rctl = er32(RCTL);
4757 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4758 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4759 }
4760}
4761
ff10e13c
CW		 4762static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4763{
4764 struct e1000_hw *hw = &adapter->hw;
4765
e921eb1a 4766 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4767 * for hung state and reset, if two calls return true
4768 */
4769 if (e1000_check_phy_82574(hw))
4770 adapter->phy_hang_count++;
4771 else
4772 adapter->phy_hang_count = 0;
4773
4774 if (adapter->phy_hang_count > 1) {
4775 adapter->phy_hang_count = 0;
4776 schedule_work(&adapter->reset_task);
4777 }
4778}
4779
bc7f75fa
AK		 4780/**
4781 * e1000_watchdog - Timer Call-back
4782 * @data: pointer to adapter cast into an unsigned long
4783 **/
4784static void e1000_watchdog(unsigned long data)
4785{
53aa82da 4786 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4787
4788 /* Do the rest outside of interrupt context */
4789 schedule_work(&adapter->watchdog_task);
4790
4791 /* TODO: make this use queue_delayed_work() */
4792}
4793
4794static void e1000_watchdog_task(struct work_struct *work)
4795{
4796 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4797 struct e1000_adapter,
4798 watchdog_task);
bc7f75fa
AK		 4799 struct net_device *netdev = adapter->netdev;
4800 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4801 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4802 struct e1000_ring *tx_ring = adapter->tx_ring;
4803 struct e1000_hw *hw = &adapter->hw;
4804 u32 link, tctl;
bc7f75fa 4805
615b32af
JB		 4806 if (test_bit(__E1000_DOWN, &adapter->state))
4807 return;
4808
b405e8df 4809 link = e1000e_has_link(adapter);
318a94d6 4810 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4811 /* Cancel scheduled suspend requests. */
4812 pm_runtime_resume(netdev->dev.parent);
4813
318a94d6 4814 e1000e_enable_receives(adapter);
bc7f75fa 4815 goto link_up;
bc7f75fa
AK		 4816 }
4817
4818 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4819 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4820 e1000_update_mng_vlan(adapter);
4821
bc7f75fa
AK		 4822 if (link) {
4823 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4824 bool txb2b = true;
23606cf5
RW		 4825
4826 /* Cancel scheduled suspend requests. */
4827 pm_runtime_resume(netdev->dev.parent);
4828
318a94d6 4829 /* update snapshot of PHY registers on LSC */
7c25769f 4830 e1000_phy_read_status(adapter);
bc7f75fa 4831 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4832 &adapter->link_speed,
4833 &adapter->link_duplex);
bc7f75fa 4834 e1000_print_link_info(adapter);
e792cd91
KS		 4835
4836 /* check if SmartSpeed worked */
4837 e1000e_check_downshift(hw);
4838 if (phy->speed_downgraded)
4839 netdev_warn(netdev,
4840 "Link Speed was downgraded by SmartSpeed\n");
4841
e921eb1a 4842 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4843 * if link has autonegotiated at 10/100 half
4844 */
4845 if ((hw->phy.type == e1000_phy_igp_3 ||
4846 hw->phy.type == e1000_phy_bm) &&
4847 (hw->mac.autoneg == true) &&
4848 (adapter->link_speed == SPEED_10 ||
4849 adapter->link_speed == SPEED_100) &&
4850 (adapter->link_duplex == HALF_DUPLEX)) {
4851 u16 autoneg_exp;
4852
c2ade1a4 4853 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4854
c2ade1a4 4855 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4856 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4857 }
4858
f49c57e1 4859 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4860 adapter->tx_timeout_factor = 1;
4861 switch (adapter->link_speed) {
4862 case SPEED_10:
3db1cd5c 4863 txb2b = false;
10f1b492 4864 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4865 break;
4866 case SPEED_100:
3db1cd5c 4867 txb2b = false;
4c86e0b9 4868 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4869 break;
4870 }
4871
e921eb1a 4872 /* workaround: re-program speed mode bit after
ad68076e
BA		 4873 * link-up event
4874 */
bc7f75fa
AK		 4875 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4876 !txb2b) {
4877 u32 tarc0;
e9ec2c0f 4878 tarc0 = er32(TARC(0));
bc7f75fa 4879 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4880 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4881 }
4882
e921eb1a 4883 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4884 * some hardware issues
4885 */
bc7f75fa
AK		 4886 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4887 switch (adapter->link_speed) {
4888 case SPEED_10:
4889 case SPEED_100:
44defeb3 4890 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4891 netdev->features &= ~NETIF_F_TSO;
4892 netdev->features &= ~NETIF_F_TSO6;
4893 break;
4894 case SPEED_1000:
4895 netdev->features |= NETIF_F_TSO;
4896 netdev->features |= NETIF_F_TSO6;
4897 break;
4898 default:
4899 /* oops */
4900 break;
4901 }
4902 }
4903
e921eb1a 4904 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4905 * after setting TARC(0)
4906 */
bc7f75fa
AK		 4907 tctl = er32(TCTL);
4908 tctl |= E1000_TCTL_EN;
4909 ew32(TCTL, tctl);
4910
e921eb1a 4911 /* Perform any post-link-up configuration before
75eb0fad
BA		 4912 * reporting link up.
4913 */
4914 if (phy->ops.cfg_on_link_up)
4915 phy->ops.cfg_on_link_up(hw);
4916
bc7f75fa 4917 netif_carrier_on(netdev);
bc7f75fa
AK		 4918
4919 if (!test_bit(__E1000_DOWN, &adapter->state))
4920 mod_timer(&adapter->phy_info_timer,
4921 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4922 }
4923 } else {
4924 if (netif_carrier_ok(netdev)) {
4925 adapter->link_speed = 0;
4926 adapter->link_duplex = 0;
8f12fe86 4927 /* Link status message must follow this format */
7dbc1672 4928 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4929 netif_carrier_off(netdev);
bc7f75fa
AK		 4930 if (!test_bit(__E1000_DOWN, &adapter->state))
4931 mod_timer(&adapter->phy_info_timer,
4932 round_jiffies(jiffies + 2 * HZ));
4933
12d43f7d
BA		 4934 /* The link is lost so the controller stops DMA.
4935 * If there is queued Tx work that cannot be done
4936 * or if on an 8000ES2LAN which requires a Rx packet
4937 * buffer work-around on link down event, reset the
4938 * controller to flush the Tx/Rx packet buffers.
4939 * (Do the reset outside of interrupt context).
4940 */
4941 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4942 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4943 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4944 else
4945 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4946 LINK_TIMEOUT);
bc7f75fa
AK		 4947 }
4948 }
4949
4950link_up:
67fd4fcb 4951 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4952 e1000e_update_stats(adapter);
4953
4954 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4955 adapter->tpt_old = adapter->stats.tpt;
4956 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4957 adapter->colc_old = adapter->stats.colc;
4958
7c25769f
BA		 4959 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4960 adapter->gorc_old = adapter->stats.gorc;
4961 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4962 adapter->gotc_old = adapter->stats.gotc;
2084b114 4963 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4964
12d43f7d 4965 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4966 schedule_work(&adapter->reset_task);
4967 /* return immediately since reset is imminent */
4968 return;
bc7f75fa
AK		 4969 }
4970
12d43f7d
BA		 4971 e1000e_update_adaptive(&adapter->hw);
4972
eab2abf5
JB		 4973 /* Simple mode for Interrupt Throttle Rate (ITR) */
4974 if (adapter->itr_setting == 4) {
e921eb1a 4975 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4976 * Total asymmetrical Tx or Rx gets ITR=8000;
4977 * everyone else is between 2000-8000.
4978 */
4979 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4980 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 4981 adapter->gotc - adapter->gorc :
4982 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 4983 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4984
22a4cca2 4985 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4986 }
4987
ad68076e 4988 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4989 if (adapter->msix_entries)
4990 ew32(ICS, adapter->rx_ring->ims_val);
4991 else
4992 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4993
713b3c9e
JB		 4994 /* flush pending descriptors to memory before detecting Tx hang */
4995 e1000e_flush_descriptors(adapter);
4996
bc7f75fa 4997 /* Force detection of hung controller every watchdog period */
3db1cd5c 4998 adapter->detect_tx_hung = true;
bc7f75fa 4999
e921eb1a 5000 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5001 * reset from the other port. Set the appropriate LAA in RAR[0]
5002 */
bc7f75fa 5003 if (e1000e_get_laa_state_82571(hw))
69e1e019 5004 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5005
ff10e13c
CW		 5006 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5007 e1000e_check_82574_phy_workaround(adapter);
5008
b67e1913
BA		 5009 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5010 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5011 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5012 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5013 er32(RXSTMPH);
5014 adapter->rx_hwtstamp_cleared++;
5015 } else {
5016 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5017 }
5018 }
5019
bc7f75fa
AK		 5020 /* Reset the timer */
5021 if (!test_bit(__E1000_DOWN, &adapter->state))
5022 mod_timer(&adapter->watchdog_timer,
5023 round_jiffies(jiffies + 2 * HZ));
5024}
5025
5026#define E1000_TX_FLAGS_CSUM 0x00000001
5027#define E1000_TX_FLAGS_VLAN 0x00000002
5028#define E1000_TX_FLAGS_TSO 0x00000004
5029#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5030#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5031#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5032#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5033#define E1000_TX_FLAGS_VLAN_SHIFT 16
5034
55aa6985 5035static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5036{
bc7f75fa
AK		 5037 struct e1000_context_desc *context_desc;
5038 struct e1000_buffer *buffer_info;
5039 unsigned int i;
5040 u32 cmd_length = 0;
70443ae9 5041 u16 ipcse = 0, mss;
bc7f75fa 5042 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5043
3d5e33c9
BA		 5044 if (!skb_is_gso(skb))
5045 return 0;
bc7f75fa 5046
3d5e33c9 5047 if (skb_header_cloned(skb)) {
90da0669
BA		 5048 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5049
3d5e33c9
BA		 5050 if (err)
5051 return err;
bc7f75fa
AK		 5052 }
5053
3d5e33c9
BA		 5054 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5055 mss = skb_shinfo(skb)->gso_size;
5056 if (skb->protocol == htons(ETH_P_IP)) {
5057 struct iphdr *iph = ip_hdr(skb);
5058 iph->tot_len = 0;
5059 iph->check = 0;
5060 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5061 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5062 cmd_length = E1000_TXD_CMD_IP;
5063 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5064 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5065 ipv6_hdr(skb)->payload_len = 0;
5066 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5067 &ipv6_hdr(skb)->daddr,
5068 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5069 ipcse = 0;
5070 }
5071 ipcss = skb_network_offset(skb);
5072 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5073 tucss = skb_transport_offset(skb);
5074 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5075
5076 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5077 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5078
5079 i = tx_ring->next_to_use;
5080 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5081 buffer_info = &tx_ring->buffer_info[i];
5082
5083 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5084 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5085 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5086 context_desc->upper_setup.tcp_fields.tucss = tucss;
5087 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5088 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 5089 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5090 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5091 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5092
5093 buffer_info->time_stamp = jiffies;
5094 buffer_info->next_to_watch = i;
5095
5096 i++;
5097 if (i == tx_ring->count)
5098 i = 0;
5099 tx_ring->next_to_use = i;
5100
5101 return 1;
bc7f75fa
AK		 5102}
5103
55aa6985 5104static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5105{
55aa6985 5106 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5107 struct e1000_context_desc *context_desc;
5108 struct e1000_buffer *buffer_info;
5109 unsigned int i;
5110 u8 css;
af807c82 5111 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5112 __be16 protocol;
bc7f75fa 5113
af807c82
DG		 5114 if (skb->ip_summed != CHECKSUM_PARTIAL)
5115 return 0;
bc7f75fa 5116
5f66f208
AJ		 5117 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5118 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5119 else
5120 protocol = skb->protocol;
5121
3f518390 5122 switch (protocol) {
09640e63 5123 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5124 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5125 cmd_len |= E1000_TXD_CMD_TCP;
5126 break;
09640e63 5127 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5128 /* XXX not handling all IPV6 headers */
5129 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5130 cmd_len |= E1000_TXD_CMD_TCP;
5131 break;
5132 default:
5133 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5134 e_warn("checksum_partial proto=%x!\n",
5135 be16_to_cpu(protocol));
af807c82 5136 break;
bc7f75fa
AK		 5137 }
5138
0d0b1672 5139 css = skb_checksum_start_offset(skb);
af807c82
DG		 5140
5141 i = tx_ring->next_to_use;
5142 buffer_info = &tx_ring->buffer_info[i];
5143 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5144
5145 context_desc->lower_setup.ip_config = 0;
5146 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5147 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5148 context_desc->upper_setup.tcp_fields.tucse = 0;
5149 context_desc->tcp_seg_setup.data = 0;
5150 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5151
5152 buffer_info->time_stamp = jiffies;
5153 buffer_info->next_to_watch = i;
5154
5155 i++;
5156 if (i == tx_ring->count)
5157 i = 0;
5158 tx_ring->next_to_use = i;
5159
5160 return 1;
bc7f75fa
AK		 5161}
5162
55aa6985
BA		 5163static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5164 unsigned int first, unsigned int max_per_txd,
d821a4c4 5165 unsigned int nr_frags)
bc7f75fa 5166{
55aa6985 5167 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5168 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5169 struct e1000_buffer *buffer_info;
8ddc951c 5170 unsigned int len = skb_headlen(skb);
03b1320d 5171 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5172 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5173
5174 i = tx_ring->next_to_use;
5175
5176 while (len) {
1b7719c4 5177 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5178 size = min(len, max_per_txd);
5179
bc7f75fa 5180 buffer_info->length = size;
bc7f75fa 5181 buffer_info->time_stamp = jiffies;
bc7f75fa 5182 buffer_info->next_to_watch = i;
0be3f55f
NN		 5183 buffer_info->dma = dma_map_single(&pdev->dev,
5184 skb->data + offset,
af667a29 5185 size, DMA_TO_DEVICE);
03b1320d 5186 buffer_info->mapped_as_page = false;
0be3f55f 5187 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5188 goto dma_error;
bc7f75fa
AK		 5189
5190 len -= size;
5191 offset += size;
03b1320d 5192 count++;
1b7719c4
AD		 5193
5194 if (len) {
5195 i++;
5196 if (i == tx_ring->count)
5197 i = 0;
5198 }
bc7f75fa
AK		 5199 }
5200
5201 for (f = 0; f < nr_frags; f++) {
9e903e08 5202 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5203
5204 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5205 len = skb_frag_size(frag);
877749bf 5206 offset = 0;
bc7f75fa
AK		 5207
5208 while (len) {
1b7719c4
AD		 5209 i++;
5210 if (i == tx_ring->count)
5211 i = 0;
5212
bc7f75fa
AK		 5213 buffer_info = &tx_ring->buffer_info[i];
5214 size = min(len, max_per_txd);
bc7f75fa
AK		 5215
5216 buffer_info->length = size;
5217 buffer_info->time_stamp = jiffies;
bc7f75fa 5218 buffer_info->next_to_watch = i;
877749bf 5219 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5220 offset, size,
5221 DMA_TO_DEVICE);
03b1320d 5222 buffer_info->mapped_as_page = true;
0be3f55f 5223 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5224 goto dma_error;
bc7f75fa
AK		 5225
5226 len -= size;
5227 offset += size;
5228 count++;
bc7f75fa
AK		 5229 }
5230 }
5231
af667a29 5232 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5233 /* multiply data chunks by size of headers */
5234 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5235
bc7f75fa 5236 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5237 tx_ring->buffer_info[i].segs = segs;
5238 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5239 tx_ring->buffer_info[first].next_to_watch = i;
5240
5241 return count;
03b1320d
AD		 5242
5243dma_error:
af667a29 5244 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5245 buffer_info->dma = 0;
c1fa347f 5246 if (count)
03b1320d 5247 count--;
c1fa347f
RK		 5248
5249 while (count--) {
af667a29 5250 if (i == 0)
03b1320d 5251 i += tx_ring->count;
c1fa347f 5252 i--;
03b1320d 5253 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5254 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5255 }
5256
5257 return 0;
bc7f75fa
AK		 5258}
5259
55aa6985 5260static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5261{
55aa6985 5262 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5263 struct e1000_tx_desc *tx_desc = NULL;
5264 struct e1000_buffer *buffer_info;
5265 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5266 unsigned int i;
5267
5268 if (tx_flags & E1000_TX_FLAGS_TSO) {
5269 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5270 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5271 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5272
5273 if (tx_flags & E1000_TX_FLAGS_IPV4)
5274 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5275 }
5276
5277 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5278 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5279 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5280 }
5281
5282 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5283 txd_lower |= E1000_TXD_CMD_VLE;
5284 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5285 }
5286
943146de
BG		 5287 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5288 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5289
b67e1913
BA		 5290 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5291 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5292 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5293 }
5294
bc7f75fa
AK		 5295 i = tx_ring->next_to_use;
5296
36b973df 5297 do {
bc7f75fa
AK		 5298 buffer_info = &tx_ring->buffer_info[i];
5299 tx_desc = E1000_TX_DESC(*tx_ring, i);
5300 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5301 tx_desc->lower.data = cpu_to_le32(txd_lower |
5302 buffer_info->length);
bc7f75fa
AK		 5303 tx_desc->upper.data = cpu_to_le32(txd_upper);
5304
5305 i++;
5306 if (i == tx_ring->count)
5307 i = 0;
36b973df 5308 } while (--count > 0);
bc7f75fa
AK		 5309
5310 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5311
943146de
BG		 5312 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5313 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5314 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5315
e921eb1a 5316 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5317 * know there are new descriptors to fetch. (Only
5318 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5319 * such as IA-64).
5320 */
bc7f75fa
AK		 5321 wmb();
5322
5323 tx_ring->next_to_use = i;
c6e7f51e
BA		 5324
5325 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5326 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5327 else
c5083cf6 5328 writel(i, tx_ring->tail);
c6e7f51e 5329
e921eb1a 5330 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5331 * at a time, it synchronizes IO on IA64/Altix systems
5332 */
bc7f75fa
AK		 5333 mmiowb();
5334}
5335
5336#define MINIMUM_DHCP_PACKET_SIZE 282
5337static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5338 struct sk_buff *skb)
5339{
5340 struct e1000_hw *hw = &adapter->hw;
5341 u16 length, offset;
5342
d60923c4
BA		 5343 if (vlan_tx_tag_present(skb) &&
5344 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5345 (adapter->hw.mng_cookie.status &
5346 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5347 return 0;
bc7f75fa
AK		 5348
5349 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5350 return 0;
5351
53aa82da 5352 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5353 return 0;
5354
5355 {
362e20ca 5356 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5357 struct udphdr *udp;
5358
5359 if (ip->protocol != IPPROTO_UDP)
5360 return 0;
5361
5362 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5363 if (ntohs(udp->dest) != 67)
5364 return 0;
5365
5366 offset = (u8 *)udp + 8 - skb->data;
5367 length = skb->len - offset;
5368 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5369 }
5370
5371 return 0;
5372}
5373
55aa6985 5374static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5375{
55aa6985 5376 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5377
55aa6985 5378 netif_stop_queue(adapter->netdev);
e921eb1a 5379 /* Herbert's original patch had:
bc7f75fa 5380 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5381 * but since that doesn't exist yet, just open code it.
5382 */
bc7f75fa
AK		 5383 smp_mb();
5384
e921eb1a 5385 /* We need to check again in a case another CPU has just
ad68076e
BA		 5386 * made room available.
5387 */
55aa6985 5388 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5389 return -EBUSY;
5390
5391 /* A reprieve! */
55aa6985 5392 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5393 ++adapter->restart_queue;
5394 return 0;
5395}
5396
55aa6985 5397static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5398{
d821a4c4
BA		 5399 BUG_ON(size > tx_ring->count);
5400
55aa6985 5401 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5402 return 0;
55aa6985 5403 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5404}
5405
3b29a56d
SH		 5406static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5407 struct net_device *netdev)
bc7f75fa
AK		 5408{
5409 struct e1000_adapter *adapter = netdev_priv(netdev);
5410 struct e1000_ring *tx_ring = adapter->tx_ring;
5411 unsigned int first;
bc7f75fa 5412 unsigned int tx_flags = 0;
e743d313 5413 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5414 unsigned int nr_frags;
5415 unsigned int mss;
bc7f75fa
AK		 5416 int count = 0;
5417 int tso;
5418 unsigned int f;
bc7f75fa
AK		 5419
5420 if (test_bit(__E1000_DOWN, &adapter->state)) {
5421 dev_kfree_skb_any(skb);
5422 return NETDEV_TX_OK;
5423 }
5424
5425 if (skb->len <= 0) {
5426 dev_kfree_skb_any(skb);
5427 return NETDEV_TX_OK;
5428 }
5429
e921eb1a 5430 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5431 * pad skb in order to meet this minimum size requirement
5432 */
5433 if (unlikely(skb->len < 17)) {
5434 if (skb_pad(skb, 17 - skb->len))
5435 return NETDEV_TX_OK;
5436 skb->len = 17;
5437 skb_set_tail_pointer(skb, 17);
5438 }
5439
bc7f75fa 5440 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5441 if (mss) {
5442 u8 hdr_len;
bc7f75fa 5443
e921eb1a 5444 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5445 * points to just header, pull a few bytes of payload from
5446 * frags into skb->data
5447 */
bc7f75fa 5448 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5449 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5450 * avoiding it could save a lot of cycles
5451 */
4e6c709c 5452 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5453 unsigned int pull_size;
5454
a2a5b323 5455 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5456 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5457 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5458 dev_kfree_skb_any(skb);
5459 return NETDEV_TX_OK;
5460 }
e743d313 5461 len = skb_headlen(skb);
bc7f75fa
AK		 5462 }
5463 }
5464
5465 /* reserve a descriptor for the offload context */
5466 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5467 count++;
5468 count++;
5469
d821a4c4 5470 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5471
5472 nr_frags = skb_shinfo(skb)->nr_frags;
5473 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5474 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5475 adapter->tx_fifo_limit);
bc7f75fa
AK		 5476
5477 if (adapter->hw.mac.tx_pkt_filtering)
5478 e1000_transfer_dhcp_info(adapter, skb);
5479
e921eb1a 5480 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5481 * head, otherwise try next time
5482 */
55aa6985 5483 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5484 return NETDEV_TX_BUSY;
bc7f75fa 5485
eab6d18d 5486 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5487 tx_flags |= E1000_TX_FLAGS_VLAN;
5488 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5489 }
5490
5491 first = tx_ring->next_to_use;
5492
55aa6985 5493 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5494 if (tso < 0) {
5495 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5496 return NETDEV_TX_OK;
5497 }
5498
5499 if (tso)
5500 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5501 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5502 tx_flags |= E1000_TX_FLAGS_CSUM;
5503
e921eb1a 5504 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5505 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5506 * no longer assume, we must.
5507 */
bc7f75fa
AK		 5508 if (skb->protocol == htons(ETH_P_IP))
5509 tx_flags |= E1000_TX_FLAGS_IPV4;
5510
943146de
BG		 5511 if (unlikely(skb->no_fcs))
5512 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5513
25985edc 5514 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5515 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5516 nr_frags);
1b7719c4 5517 if (count) {
b67e1913
BA		 5518 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5519 !adapter->tx_hwtstamp_skb)) {
5520 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5521 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5522 adapter->tx_hwtstamp_skb = skb_get(skb);
5523 schedule_work(&adapter->tx_hwtstamp_work);
5524 } else {
5525 skb_tx_timestamp(skb);
5526 }
80be3129 5527
3f0cfa3b 5528 netdev_sent_queue(netdev, skb->len);
55aa6985 5529 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5530 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5531 e1000_maybe_stop_tx(tx_ring,
5532 (MAX_SKB_FRAGS *
5533 DIV_ROUND_UP(PAGE_SIZE,
5534 adapter->tx_fifo_limit) + 2));
1b7719c4 5535 } else {
bc7f75fa 5536 dev_kfree_skb_any(skb);
1b7719c4
AD		 5537 tx_ring->buffer_info[first].time_stamp = 0;
5538 tx_ring->next_to_use = first;
bc7f75fa
AK		 5539 }
5540
bc7f75fa
AK		 5541 return NETDEV_TX_OK;
5542}
5543
5544/**
5545 * e1000_tx_timeout - Respond to a Tx Hang
5546 * @netdev: network interface device structure
5547 **/
5548static void e1000_tx_timeout(struct net_device *netdev)
5549{
5550 struct e1000_adapter *adapter = netdev_priv(netdev);
5551
5552 /* Do the reset outside of interrupt context */
5553 adapter->tx_timeout_count++;
5554 schedule_work(&adapter->reset_task);
5555}
5556
5557static void e1000_reset_task(struct work_struct *work)
5558{
5559 struct e1000_adapter *adapter;
5560 adapter = container_of(work, struct e1000_adapter, reset_task);
5561
615b32af
JB		 5562 /* don't run the task if already down */
5563 if (test_bit(__E1000_DOWN, &adapter->state))
5564 return;
5565
12d43f7d 5566 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5567 e1000e_dump(adapter);
12d43f7d 5568 e_err("Reset adapter unexpectedly\n");
affa9dfb 5569 }
bc7f75fa
AK		 5570 e1000e_reinit_locked(adapter);
5571}
5572
5573/**
67fd4fcb 5574 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5575 * @netdev: network interface device structure
67fd4fcb 5576 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5577 *
5578 * Returns the address of the device statistics structure.
bc7f75fa 5579 **/
67fd4fcb 5580struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5581 struct rtnl_link_stats64 *stats)
bc7f75fa 5582{
67fd4fcb
JK		 5583 struct e1000_adapter *adapter = netdev_priv(netdev);
5584
5585 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5586 spin_lock(&adapter->stats64_lock);
5587 e1000e_update_stats(adapter);
5588 /* Fill out the OS statistics structure */
5589 stats->rx_bytes = adapter->stats.gorc;
5590 stats->rx_packets = adapter->stats.gprc;
5591 stats->tx_bytes = adapter->stats.gotc;
5592 stats->tx_packets = adapter->stats.gptc;
5593 stats->multicast = adapter->stats.mprc;
5594 stats->collisions = adapter->stats.colc;
5595
5596 /* Rx Errors */
5597
e921eb1a 5598 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5599 * our own version based on RUC and ROC
5600 */
5601 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5602 adapter->stats.crcerrs + adapter->stats.algnerrc +
5603 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5604 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5605 stats->rx_crc_errors = adapter->stats.crcerrs;
5606 stats->rx_frame_errors = adapter->stats.algnerrc;
5607 stats->rx_missed_errors = adapter->stats.mpc;
5608
5609 /* Tx Errors */
f0ff4398 5610 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5611 stats->tx_aborted_errors = adapter->stats.ecol;
5612 stats->tx_window_errors = adapter->stats.latecol;
5613 stats->tx_carrier_errors = adapter->stats.tncrs;
5614
5615 /* Tx Dropped needs to be maintained elsewhere */
5616
5617 spin_unlock(&adapter->stats64_lock);
5618 return stats;
bc7f75fa
AK		 5619}
5620
5621/**
5622 * e1000_change_mtu - Change the Maximum Transfer Unit
5623 * @netdev: network interface device structure
5624 * @new_mtu: new value for maximum frame size
5625 *
5626 * Returns 0 on success, negative on failure
5627 **/
5628static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5629{
5630 struct e1000_adapter *adapter = netdev_priv(netdev);
5631 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5632
2adc55c9 5633 /* Jumbo frame support */
2e1706f2
BA		 5634 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5635 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5636 e_err("Jumbo Frames not supported.\n");
5637 return -EINVAL;
bc7f75fa
AK		 5638 }
5639
2adc55c9
BA		 5640 /* Supported frame sizes */
5641 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5642 (max_frame > adapter->max_hw_frame_size)) {
5643 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5644 return -EINVAL;
5645 }
5646
2fbe4526
BA		 5647 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5648 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5649 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5650 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5651 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5652 return -EINVAL;
5653 }
5654
bc7f75fa 5655 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5656 usleep_range(1000, 2000);
610c9928 5657 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5658 adapter->max_frame_size = max_frame;
610c9928
BA		 5659 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5660 netdev->mtu = new_mtu;
bc7f75fa
AK		 5661 if (netif_running(netdev))
5662 e1000e_down(adapter);
5663
e921eb1a 5664 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5665 * means we reserve 2 more, this pushes us to allocate from the next
5666 * larger slab size.
ad68076e 5667 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5668 * However with the new *_jumbo_rx* routines, jumbo receives will use
5669 * fragmented skbs
ad68076e 5670 */
bc7f75fa 5671
9926146b 5672 if (max_frame <= 2048)
bc7f75fa
AK		 5673 adapter->rx_buffer_len = 2048;
5674 else
5675 adapter->rx_buffer_len = 4096;
5676
5677 /* adjust allocation if LPE protects us, and we aren't using SBP */
5678 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5679 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5680 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5681 + ETH_FCS_LEN;
bc7f75fa 5682
bc7f75fa
AK		 5683 if (netif_running(netdev))
5684 e1000e_up(adapter);
5685 else
5686 e1000e_reset(adapter);
5687
5688 clear_bit(__E1000_RESETTING, &adapter->state);
5689
5690 return 0;
5691}
5692
5693static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5694 int cmd)
5695{
5696 struct e1000_adapter *adapter = netdev_priv(netdev);
5697 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5698
318a94d6 5699 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5700 return -EOPNOTSUPP;
5701
5702 switch (cmd) {
5703 case SIOCGMIIPHY:
5704 data->phy_id = adapter->hw.phy.addr;
5705 break;
5706 case SIOCGMIIREG:
b16a002e
BA		 5707 e1000_phy_read_status(adapter);
5708
7c25769f
BA		 5709 switch (data->reg_num & 0x1F) {
5710 case MII_BMCR:
5711 data->val_out = adapter->phy_regs.bmcr;
5712 break;
5713 case MII_BMSR:
5714 data->val_out = adapter->phy_regs.bmsr;
5715 break;
5716 case MII_PHYSID1:
5717 data->val_out = (adapter->hw.phy.id >> 16);
5718 break;
5719 case MII_PHYSID2:
5720 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5721 break;
5722 case MII_ADVERTISE:
5723 data->val_out = adapter->phy_regs.advertise;
5724 break;
5725 case MII_LPA:
5726 data->val_out = adapter->phy_regs.lpa;
5727 break;
5728 case MII_EXPANSION:
5729 data->val_out = adapter->phy_regs.expansion;
5730 break;
5731 case MII_CTRL1000:
5732 data->val_out = adapter->phy_regs.ctrl1000;
5733 break;
5734 case MII_STAT1000:
5735 data->val_out = adapter->phy_regs.stat1000;
5736 break;
5737 case MII_ESTATUS:
5738 data->val_out = adapter->phy_regs.estatus;
5739 break;
5740 default:
bc7f75fa
AK		 5741 return -EIO;
5742 }
bc7f75fa
AK		 5743 break;
5744 case SIOCSMIIREG:
5745 default:
5746 return -EOPNOTSUPP;
5747 }
5748 return 0;
5749}
5750
b67e1913
BA		 5751/**
5752 * e1000e_hwtstamp_ioctl - control hardware time stamping
5753 * @netdev: network interface device structure
5754 * @ifreq: interface request
5755 *
5756 * Outgoing time stamping can be enabled and disabled. Play nice and
5757 * disable it when requested, although it shouldn't cause any overhead
5758 * when no packet needs it. At most one packet in the queue may be
5759 * marked for time stamping, otherwise it would be impossible to tell
5760 * for sure to which packet the hardware time stamp belongs.
5761 *
5762 * Incoming time stamping has to be configured via the hardware filters.
5763 * Not all combinations are supported, in particular event type has to be
5764 * specified. Matching the kind of event packet is not supported, with the
5765 * exception of "all V2 events regardless of level 2 or 4".
5766 **/
5767static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5768{
5769 struct e1000_adapter *adapter = netdev_priv(netdev);
5770 struct hwtstamp_config config;
5771 int ret_val;
5772
5773 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5774 return -EFAULT;
5775
5776 adapter->hwtstamp_config = config;
5777
5778 ret_val = e1000e_config_hwtstamp(adapter);
5779 if (ret_val)
5780 return ret_val;
5781
5782 config = adapter->hwtstamp_config;
5783
d89777bf
BA		 5784 switch (config.rx_filter) {
5785 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5786 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5787 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5788 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5789 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5790 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5791 /* With V2 type filters which specify a Sync or Delay Request,
5792 * Path Delay Request/Response messages are also time stamped
5793 * by hardware so notify the caller the requested packets plus
5794 * some others are time stamped.
5795 */
5796 config.rx_filter = HWTSTAMP_FILTER_SOME;
5797 break;
5798 default:
5799 break;
5800 }
5801
b67e1913
BA		 5802 return copy_to_user(ifr->ifr_data, &config,
5803 sizeof(config)) ? -EFAULT : 0;
5804}
5805
bc7f75fa
AK		 5806static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5807{
5808 switch (cmd) {
5809 case SIOCGMIIPHY:
5810 case SIOCGMIIREG:
5811 case SIOCSMIIREG:
5812 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5813 case SIOCSHWTSTAMP:
5814 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5815 default:
5816 return -EOPNOTSUPP;
5817 }
5818}
5819
a4f58f54
BA		 5820static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5821{
5822 struct e1000_hw *hw = &adapter->hw;
5823 u32 i, mac_reg;
2b6b168d 5824 u16 phy_reg, wuc_enable;
70806a7f 5825 int retval;
a4f58f54
BA		 5826
5827 /* copy MAC RARs to PHY RARs */
d3738bb8 5828 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5829
2b6b168d
BA		 5830 retval = hw->phy.ops.acquire(hw);
5831 if (retval) {
5832 e_err("Could not acquire PHY\n");
5833 return retval;
5834 }
5835
5836 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5837 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5838 if (retval)
75ce1532 5839 goto release;
2b6b168d
BA		 5840
5841 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5842 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5843 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5844 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5845 (u16)(mac_reg & 0xFFFF));
5846 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5847 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5848 }
5849
5850 /* configure PHY Rx Control register */
2b6b168d 5851 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5852 mac_reg = er32(RCTL);
5853 if (mac_reg & E1000_RCTL_UPE)
5854 phy_reg |= BM_RCTL_UPE;
5855 if (mac_reg & E1000_RCTL_MPE)
5856 phy_reg |= BM_RCTL_MPE;
5857 phy_reg &= ~(BM_RCTL_MO_MASK);
5858 if (mac_reg & E1000_RCTL_MO_3)
5859 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5860 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5861 if (mac_reg & E1000_RCTL_BAM)
5862 phy_reg |= BM_RCTL_BAM;
5863 if (mac_reg & E1000_RCTL_PMCF)
5864 phy_reg |= BM_RCTL_PMCF;
5865 mac_reg = er32(CTRL);
5866 if (mac_reg & E1000_CTRL_RFCE)
5867 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5868 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5869
5870 /* enable PHY wakeup in MAC register */
5871 ew32(WUFC, wufc);
5872 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5873
5874 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5875 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5876 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5877
5878 /* activate PHY wakeup */
2b6b168d
BA		 5879 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5880 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5881 if (retval)
5882 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5883release:
94d8186a 5884 hw->phy.ops.release(hw);
a4f58f54
BA		 5885
5886 return retval;
5887}
5888
23606cf5
RW		 5889static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5890 bool runtime)
bc7f75fa
AK		 5891{
5892 struct net_device *netdev = pci_get_drvdata(pdev);
5893 struct e1000_adapter *adapter = netdev_priv(netdev);
5894 struct e1000_hw *hw = &adapter->hw;
5895 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5896 /* Runtime suspend should only enable wakeup for link changes */
5897 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5898 int retval = 0;
5899
5900 netif_device_detach(netdev);
5901
5902 if (netif_running(netdev)) {
bb9e44d0
BA		 5903 int count = E1000_CHECK_RESET_COUNT;
5904
5905 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5906 usleep_range(10000, 20000);
5907
bc7f75fa
AK		 5908 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5909 e1000e_down(adapter);
5910 e1000_free_irq(adapter);
5911 }
4662e82b 5912 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5913
5914 retval = pci_save_state(pdev);
5915 if (retval)
5916 return retval;
5917
5918 status = er32(STATUS);
5919 if (status & E1000_STATUS_LU)
5920 wufc &= ~E1000_WUFC_LNKC;
5921
5922 if (wufc) {
5923 e1000_setup_rctl(adapter);
ef9b965a 5924 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5925
5926 /* turn on all-multi mode if wake on multicast is enabled */
5927 if (wufc & E1000_WUFC_MC) {
5928 rctl = er32(RCTL);
5929 rctl |= E1000_RCTL_MPE;
5930 ew32(RCTL, rctl);
5931 }
5932
5933 ctrl = er32(CTRL);
5934 /* advertise wake from D3Cold */
5935 #define E1000_CTRL_ADVD3WUC 0x00100000
5936 /* phy power management enable */
5937 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5938 ctrl |= E1000_CTRL_ADVD3WUC;
5939 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5940 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5941 ew32(CTRL, ctrl);
5942
318a94d6
JK		 5943 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5944 adapter->hw.phy.media_type ==
5945 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5946 /* keep the laser running in D3 */
5947 ctrl_ext = er32(CTRL_EXT);
93a23f48 5948 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5949 ew32(CTRL_EXT, ctrl_ext);
5950 }
5951
97ac8cae 5952 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5953 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5954
bc7f75fa
AK		 5955 /* Allow time for pending master requests to run */
5956 e1000e_disable_pcie_master(&adapter->hw);
5957
82776a4b 5958 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5959 /* enable wakeup by the PHY */
5960 retval = e1000_init_phy_wakeup(adapter, wufc);
5961 if (retval)
5962 return retval;
5963 } else {
5964 /* enable wakeup by the MAC */
5965 ew32(WUFC, wufc);
5966 ew32(WUC, E1000_WUC_PME_EN);
5967 }
bc7f75fa
AK		 5968 } else {
5969 ew32(WUC, 0);
5970 ew32(WUFC, 0);
bc7f75fa
AK		 5971 }
5972
4f9de721
RW		 5973 *enable_wake = !!wufc;
5974
bc7f75fa 5975 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5976 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5977 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5978 *enable_wake = true;
bc7f75fa
AK		 5979
5980 if (adapter->hw.phy.type == e1000_phy_igp_3)
5981 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5982
e921eb1a 5983 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5984 * would have already happened in close and is redundant.
5985 */
31dbe5b4 5986 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5987
5988 pci_disable_device(pdev);
5989
4f9de721
RW		 5990 return 0;
5991}
5992
5993static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5994{
5995 if (sleep && wake) {
5996 pci_prepare_to_sleep(pdev);
5997 return;
5998 }
5999
6000 pci_wake_from_d3(pdev, wake);
6001 pci_set_power_state(pdev, PCI_D3hot);
6002}
6003
f0ff4398 6004static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep, bool wake)
4f9de721
RW		 6005{
6006 struct net_device *netdev = pci_get_drvdata(pdev);
6007 struct e1000_adapter *adapter = netdev_priv(netdev);
6008
e921eb1a 6009 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6010 * correctable error when the MAC transitions from D0 to D3. To
6011 * prevent this we need to mask off the correctable errors on the
6012 * downstream port of the pci-e switch.
6013 */
6014 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6015 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6016 u16 devctl;
6017
f8c0fcac
JL		 6018 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6019 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6020 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6021
4f9de721 6022 e1000_power_off(pdev, sleep, wake);
005cbdfc 6023
f8c0fcac 6024 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6025 } else {
4f9de721 6026 e1000_power_off(pdev, sleep, wake);
005cbdfc 6027 }
bc7f75fa
AK		 6028}
6029
6f461f6c
BA		 6030#ifdef CONFIG_PCIEASPM
6031static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6032{
9f728f53 6033 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 6034}
6035#else
6036static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 6037{
ffe0b2ff
BH		 6038 u16 aspm_ctl = 0;
6039
6040 if (state & PCIE_LINK_STATE_L0S)
6041 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6042 if (state & PCIE_LINK_STATE_L1)
6043 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6044
e921eb1a 6045 /* Both device and parent should have the same ASPM setting.
6f461f6c 6046 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6047 */
ffe0b2ff 6048 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 6049
f8c0fcac
JL		 6050 if (pdev->bus->self)
6051 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 6052 aspm_ctl);
6f461f6c
BA		 6053}
6054#endif
78cd29d5 6055static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 6056{
6057 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6058 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6059 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6060
6061 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 6062}
6063
aa338601 6064#ifdef CONFIG_PM
23606cf5 6065static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6066{
23606cf5 6067 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6068}
6069
23606cf5 6070static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6071{
6072 struct net_device *netdev = pci_get_drvdata(pdev);
6073 struct e1000_adapter *adapter = netdev_priv(netdev);
6074 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6075 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6076 u32 err;
6077
78cd29d5
BA		 6078 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6079 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6080 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6081 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6082 if (aspm_disable_flag)
6083 e1000e_disable_aspm(pdev, aspm_disable_flag);
6084
bc7f75fa
AK		 6085 pci_set_power_state(pdev, PCI_D0);
6086 pci_restore_state(pdev);
28b8f04a 6087 pci_save_state(pdev);
6e4f6f6b 6088
4662e82b 6089 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 6090 if (netif_running(netdev)) {
6091 err = e1000_request_irq(adapter);
6092 if (err)
6093 return err;
6094 }
6095
2fbe4526 6096 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6097 e1000_resume_workarounds_pchlan(&adapter->hw);
6098
bc7f75fa 6099 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6100
6101 /* report the system wakeup cause from S3/S4 */
6102 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6103 u16 phy_data;
6104
6105 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6106 if (phy_data) {
6107 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6108 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6109 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6110 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6111 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6112 phy_data & E1000_WUS_LNKC ?
6113 "Link Status Change" : "other");
a4f58f54
BA		 6114 }
6115 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6116 } else {
6117 u32 wus = er32(WUS);
6118 if (wus) {
6119 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6120 wus & E1000_WUS_EX ? "Unicast Packet" :
6121 wus & E1000_WUS_MC ? "Multicast Packet" :
6122 wus & E1000_WUS_BC ? "Broadcast Packet" :
6123 wus & E1000_WUS_MAG ? "Magic Packet" :
6124 wus & E1000_WUS_LNKC ? "Link Status Change" :
6125 "other");
a4f58f54
BA		 6126 }
6127 ew32(WUS, ~0);
6128 }
6129
bc7f75fa 6130 e1000e_reset(adapter);
bc7f75fa 6131
cd791618 6132 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6133
6134 if (netif_running(netdev))
6135 e1000e_up(adapter);
6136
6137 netif_device_attach(netdev);
6138
e921eb1a 6139 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6140 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6141 * under the control of the driver.
6142 */
c43bc57e 6143 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6144 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6145
6146 return 0;
6147}
23606cf5 6148
a0340162
RW		 6149#ifdef CONFIG_PM_SLEEP
6150static int e1000_suspend(struct device *dev)
6151{
6152 struct pci_dev *pdev = to_pci_dev(dev);
6153 int retval;
6154 bool wake;
6155
6156 retval = __e1000_shutdown(pdev, &wake, false);
6157 if (!retval)
6158 e1000_complete_shutdown(pdev, true, wake);
6159
6160 return retval;
6161}
6162
23606cf5
RW		 6163static int e1000_resume(struct device *dev)
6164{
6165 struct pci_dev *pdev = to_pci_dev(dev);
6166 struct net_device *netdev = pci_get_drvdata(pdev);
6167 struct e1000_adapter *adapter = netdev_priv(netdev);
6168
6169 if (e1000e_pm_ready(adapter))
6170 adapter->idle_check = true;
6171
6172 return __e1000_resume(pdev);
6173}
a0340162
RW		 6174#endif /* CONFIG_PM_SLEEP */
6175
6176#ifdef CONFIG_PM_RUNTIME
6177static int e1000_runtime_suspend(struct device *dev)
6178{
6179 struct pci_dev *pdev = to_pci_dev(dev);
6180 struct net_device *netdev = pci_get_drvdata(pdev);
6181 struct e1000_adapter *adapter = netdev_priv(netdev);
6182
6183 if (e1000e_pm_ready(adapter)) {
6184 bool wake;
6185
6186 __e1000_shutdown(pdev, &wake, true);
6187 }
6188
6189 return 0;
6190}
6191
6192static int e1000_idle(struct device *dev)
6193{
6194 struct pci_dev *pdev = to_pci_dev(dev);
6195 struct net_device *netdev = pci_get_drvdata(pdev);
6196 struct e1000_adapter *adapter = netdev_priv(netdev);
6197
6198 if (!e1000e_pm_ready(adapter))
6199 return 0;
6200
6201 if (adapter->idle_check) {
6202 adapter->idle_check = false;
6203 if (!e1000e_has_link(adapter))
6204 pm_schedule_suspend(dev, MSEC_PER_SEC);
6205 }
6206
6207 return -EBUSY;
6208}
23606cf5
RW		 6209
6210static int e1000_runtime_resume(struct device *dev)
6211{
6212 struct pci_dev *pdev = to_pci_dev(dev);
6213 struct net_device *netdev = pci_get_drvdata(pdev);
6214 struct e1000_adapter *adapter = netdev_priv(netdev);
6215
6216 if (!e1000e_pm_ready(adapter))
6217 return 0;
6218
6219 adapter->idle_check = !dev->power.runtime_auto;
6220 return __e1000_resume(pdev);
6221}
a0340162 6222#endif /* CONFIG_PM_RUNTIME */
aa338601 6223#endif /* CONFIG_PM */
bc7f75fa
AK		 6224
6225static void e1000_shutdown(struct pci_dev *pdev)
6226{
4f9de721
RW		 6227 bool wake = false;
6228
23606cf5 6229 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 6230
6231 if (system_state == SYSTEM_POWER_OFF)
6232 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 6233}
6234
6235#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6236
8bb62869 6237static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6238{
6239 struct net_device *netdev = data;
6240 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6241
6242 if (adapter->msix_entries) {
90da0669
BA		 6243 int vector, msix_irq;
6244
147b2c8c
DD		 6245 vector = 0;
6246 msix_irq = adapter->msix_entries[vector].vector;
6247 disable_irq(msix_irq);
6248 e1000_intr_msix_rx(msix_irq, netdev);
6249 enable_irq(msix_irq);
6250
6251 vector++;
6252 msix_irq = adapter->msix_entries[vector].vector;
6253 disable_irq(msix_irq);
6254 e1000_intr_msix_tx(msix_irq, netdev);
6255 enable_irq(msix_irq);
6256
6257 vector++;
6258 msix_irq = adapter->msix_entries[vector].vector;
6259 disable_irq(msix_irq);
6260 e1000_msix_other(msix_irq, netdev);
6261 enable_irq(msix_irq);
6262 }
6263
6264 return IRQ_HANDLED;
6265}
6266
e921eb1a
BA		 6267/**
6268 * e1000_netpoll
6269 * @netdev: network interface device structure
6270 *
bc7f75fa
AK		 6271 * Polling 'interrupt' - used by things like netconsole to send skbs
6272 * without having to re-enable interrupts. It's not called while
6273 * the interrupt routine is executing.
6274 */
6275static void e1000_netpoll(struct net_device *netdev)
6276{
6277 struct e1000_adapter *adapter = netdev_priv(netdev);
6278
147b2c8c
DD		 6279 switch (adapter->int_mode) {
6280 case E1000E_INT_MODE_MSIX:
6281 e1000_intr_msix(adapter->pdev->irq, netdev);
6282 break;
6283 case E1000E_INT_MODE_MSI:
6284 disable_irq(adapter->pdev->irq);
6285 e1000_intr_msi(adapter->pdev->irq, netdev);
6286 enable_irq(adapter->pdev->irq);
6287 break;
6288 default: /* E1000E_INT_MODE_LEGACY */
6289 disable_irq(adapter->pdev->irq);
6290 e1000_intr(adapter->pdev->irq, netdev);
6291 enable_irq(adapter->pdev->irq);
6292 break;
6293 }
bc7f75fa
AK		 6294}
6295#endif
6296
6297/**
6298 * e1000_io_error_detected - called when PCI error is detected
6299 * @pdev: Pointer to PCI device
6300 * @state: The current pci connection state
6301 *
6302 * This function is called after a PCI bus error affecting
6303 * this device has been detected.
6304 */
6305static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6306 pci_channel_state_t state)
6307{
6308 struct net_device *netdev = pci_get_drvdata(pdev);
6309 struct e1000_adapter *adapter = netdev_priv(netdev);
6310
6311 netif_device_detach(netdev);
6312
c93b5a76
MM		 6313 if (state == pci_channel_io_perm_failure)
6314 return PCI_ERS_RESULT_DISCONNECT;
6315
bc7f75fa
AK		 6316 if (netif_running(netdev))
6317 e1000e_down(adapter);
6318 pci_disable_device(pdev);
6319
6320 /* Request a slot slot reset. */
6321 return PCI_ERS_RESULT_NEED_RESET;
6322}
6323
6324/**
6325 * e1000_io_slot_reset - called after the pci bus has been reset.
6326 * @pdev: Pointer to PCI device
6327 *
6328 * Restart the card from scratch, as if from a cold-boot. Implementation
6329 * resembles the first-half of the e1000_resume routine.
6330 */
6331static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6332{
6333 struct net_device *netdev = pci_get_drvdata(pdev);
6334 struct e1000_adapter *adapter = netdev_priv(netdev);
6335 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6336 u16 aspm_disable_flag = 0;
6e4f6f6b 6337 int err;
111b9dc5 6338 pci_ers_result_t result;
bc7f75fa 6339
78cd29d5
BA		 6340 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6341 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6342 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6343 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6344 if (aspm_disable_flag)
6345 e1000e_disable_aspm(pdev, aspm_disable_flag);
6346
f0f422e5 6347 err = pci_enable_device_mem(pdev);
6e4f6f6b 6348 if (err) {
bc7f75fa
AK		 6349 dev_err(&pdev->dev,
6350 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6351 result = PCI_ERS_RESULT_DISCONNECT;
6352 } else {
6353 pci_set_master(pdev);
23606cf5 6354 pdev->state_saved = true;
111b9dc5 6355 pci_restore_state(pdev);
bc7f75fa 6356
111b9dc5
JB		 6357 pci_enable_wake(pdev, PCI_D3hot, 0);
6358 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6359
111b9dc5
JB		 6360 e1000e_reset(adapter);
6361 ew32(WUS, ~0);
6362 result = PCI_ERS_RESULT_RECOVERED;
6363 }
bc7f75fa 6364
111b9dc5
JB		 6365 pci_cleanup_aer_uncorrect_error_status(pdev);
6366
6367 return result;
bc7f75fa
AK		 6368}
6369
6370/**
6371 * e1000_io_resume - called when traffic can start flowing again.
6372 * @pdev: Pointer to PCI device
6373 *
6374 * This callback is called when the error recovery driver tells us that
6375 * its OK to resume normal operation. Implementation resembles the
6376 * second-half of the e1000_resume routine.
6377 */
6378static void e1000_io_resume(struct pci_dev *pdev)
6379{
6380 struct net_device *netdev = pci_get_drvdata(pdev);
6381 struct e1000_adapter *adapter = netdev_priv(netdev);
6382
cd791618 6383 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6384
6385 if (netif_running(netdev)) {
6386 if (e1000e_up(adapter)) {
6387 dev_err(&pdev->dev,
6388 "can't bring device back up after reset\n");
6389 return;
6390 }
6391 }
6392
6393 netif_device_attach(netdev);
6394
e921eb1a 6395 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6396 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6397 * under the control of the driver.
6398 */
c43bc57e 6399 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6400 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6401}
6402
6403static void e1000_print_device_info(struct e1000_adapter *adapter)
6404{
6405 struct e1000_hw *hw = &adapter->hw;
6406 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6407 u32 ret_val;
6408 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6409
6410 /* print bus type/speed/width info */
a5cc7642 6411 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6412 /* bus width */
6413 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6414 "Width x1"),
44defeb3 6415 /* MAC address */
7c510e4b 6416 netdev->dev_addr);
44defeb3
JK		 6417 e_info("Intel(R) PRO/%s Network Connection\n",
6418 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6419 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6420 E1000_PBANUM_LENGTH);
6421 if (ret_val)
f2315bf1 6422 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6423 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6424 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6425}
6426
10aa4c04
AK		 6427static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6428{
6429 struct e1000_hw *hw = &adapter->hw;
6430 int ret_val;
6431 u16 buf = 0;
6432
6433 if (hw->mac.type != e1000_82573)
6434 return;
6435
6436 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6437 le16_to_cpus(&buf);
6438 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6439 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6440 dev_warn(&adapter->pdev->dev,
6441 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6442 }
10aa4c04
AK		 6443}
6444
c8f44aff 6445static int e1000_set_features(struct net_device *netdev,
70495a50 6446 netdev_features_t features)
dc221294
BA		 6447{
6448 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6449 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6450
6451 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6452 adapter->flags |= FLAG_TSO_FORCE;
6453
6454 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6455 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6456 NETIF_F_RXALL)))
dc221294
BA		 6457 return 0;
6458
0184039a
BG		 6459 if (changed & NETIF_F_RXFCS) {
6460 if (features & NETIF_F_RXFCS) {
6461 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6462 } else {
6463 /* We need to take it back to defaults, which might mean
6464 * stripping is still disabled at the adapter level.
6465 */
6466 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6467 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6468 else
6469 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6470 }
6471 }
6472
70495a50
BA		 6473 netdev->features = features;
6474
dc221294
BA		 6475 if (netif_running(netdev))
6476 e1000e_reinit_locked(adapter);
6477 else
6478 e1000e_reset(adapter);
6479
6480 return 0;
6481}
6482
651c2466
SH		 6483static const struct net_device_ops e1000e_netdev_ops = {
6484 .ndo_open = e1000_open,
6485 .ndo_stop = e1000_close,
00829823 6486 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6487 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6488 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6489 .ndo_set_mac_address = e1000_set_mac,
6490 .ndo_change_mtu = e1000_change_mtu,
6491 .ndo_do_ioctl = e1000_ioctl,
6492 .ndo_tx_timeout = e1000_tx_timeout,
6493 .ndo_validate_addr = eth_validate_addr,
6494
651c2466
SH		 6495 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6496 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6497#ifdef CONFIG_NET_POLL_CONTROLLER
6498 .ndo_poll_controller = e1000_netpoll,
6499#endif
dc221294 6500 .ndo_set_features = e1000_set_features,
651c2466
SH		 6501};
6502
bc7f75fa
AK		 6503/**
6504 * e1000_probe - Device Initialization Routine
6505 * @pdev: PCI device information struct
6506 * @ent: entry in e1000_pci_tbl
6507 *
6508 * Returns 0 on success, negative on failure
6509 *
6510 * e1000_probe initializes an adapter identified by a pci_dev structure.
6511 * The OS initialization, configuring of the adapter private structure,
6512 * and a hardware reset occur.
6513 **/
1dd06ae8 6514static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6515{
6516 struct net_device *netdev;
6517 struct e1000_adapter *adapter;
6518 struct e1000_hw *hw;
6519 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6520 resource_size_t mmio_start, mmio_len;
6521 resource_size_t flash_start, flash_len;
bc7f75fa 6522 static int cards_found;
78cd29d5 6523 u16 aspm_disable_flag = 0;
17e813ec 6524 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6525 u16 eeprom_data = 0;
6526 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6527
78cd29d5
BA		 6528 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6529 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6530 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6531 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6532 if (aspm_disable_flag)
6533 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6534
f0f422e5 6535 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6536 if (err)
6537 return err;
6538
6539 pci_using_dac = 0;
0be3f55f 6540 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6541 if (!err) {
0be3f55f 6542 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6543 if (!err)
6544 pci_using_dac = 1;
6545 } else {
0be3f55f 6546 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6547 if (err) {
0be3f55f
NN		 6548 err = dma_set_coherent_mask(&pdev->dev,
6549 DMA_BIT_MASK(32));
bc7f75fa 6550 if (err) {
f0ff4398
BA		 6551 dev_err(&pdev->dev,
6552 "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6553 goto err_dma;
6554 }
6555 }
6556 }
6557
17e813ec
BA		 6558 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6559 err = pci_request_selected_regions_exclusive(pdev, bars,
6560 e1000e_driver_name);
bc7f75fa
AK		 6561 if (err)
6562 goto err_pci_reg;
6563
68eac460 6564 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6565 pci_enable_pcie_error_reporting(pdev);
68eac460 6566
bc7f75fa 6567 pci_set_master(pdev);
438b365a
BA		 6568 /* PCI config space info */
6569 err = pci_save_state(pdev);
6570 if (err)
6571 goto err_alloc_etherdev;
bc7f75fa
AK		 6572
6573 err = -ENOMEM;
6574 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6575 if (!netdev)
6576 goto err_alloc_etherdev;
6577
bc7f75fa
AK		 6578 SET_NETDEV_DEV(netdev, &pdev->dev);
6579
f85e4dfa
TH		 6580 netdev->irq = pdev->irq;
6581
bc7f75fa
AK		 6582 pci_set_drvdata(pdev, netdev);
6583 adapter = netdev_priv(netdev);
6584 hw = &adapter->hw;
6585 adapter->netdev = netdev;
6586 adapter->pdev = pdev;
6587 adapter->ei = ei;
6588 adapter->pba = ei->pba;
6589 adapter->flags = ei->flags;
eb7c3adb 6590 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6591 adapter->hw.adapter = adapter;
6592 adapter->hw.mac.type = ei->mac;
2adc55c9 6593 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6594 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6595
6596 mmio_start = pci_resource_start(pdev, 0);
6597 mmio_len = pci_resource_len(pdev, 0);
6598
6599 err = -EIO;
6600 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6601 if (!adapter->hw.hw_addr)
6602 goto err_ioremap;
6603
6604 if ((adapter->flags & FLAG_HAS_FLASH) &&
6605 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6606 flash_start = pci_resource_start(pdev, 1);
6607 flash_len = pci_resource_len(pdev, 1);
6608 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6609 if (!adapter->hw.flash_address)
6610 goto err_flashmap;
6611 }
6612
6613 /* construct the net_device struct */
651c2466 6614 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6615 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6616 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6617 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6618 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6619
6620 netdev->mem_start = mmio_start;
6621 netdev->mem_end = mmio_start + mmio_len;
6622
6623 adapter->bd_number = cards_found++;
6624
4662e82b
BA		 6625 e1000e_check_options(adapter);
6626
bc7f75fa
AK		 6627 /* setup adapter struct */
6628 err = e1000_sw_init(adapter);
6629 if (err)
6630 goto err_sw_init;
6631
bc7f75fa
AK		 6632 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6633 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6634 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6635
69e3fd8c 6636 err = ei->get_variants(adapter);
bc7f75fa
AK		 6637 if (err)
6638 goto err_hw_init;
6639
4a770358
BA		 6640 if ((adapter->flags & FLAG_IS_ICH) &&
6641 (adapter->flags & FLAG_READ_ONLY_NVM))
6642 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6643
bc7f75fa
AK		 6644 hw->mac.ops.get_bus_info(&adapter->hw);
6645
318a94d6 6646 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6647
6648 /* Copper options */
318a94d6 6649 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6650 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6651 adapter->hw.phy.disable_polarity_correction = 0;
6652 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6653 }
6654
470a5420 6655 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6656 dev_info(&pdev->dev,
6657 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6658
dc221294
BA		 6659 /* Set initial default active device features */
6660 netdev->features = (NETIF_F_SG |
6661 NETIF_F_HW_VLAN_RX |
6662 NETIF_F_HW_VLAN_TX |
6663 NETIF_F_TSO |
6664 NETIF_F_TSO6 |
70495a50 6665 NETIF_F_RXHASH |
dc221294
BA		 6666 NETIF_F_RXCSUM |
6667 NETIF_F_HW_CSUM);
6668
6669 /* Set user-changeable features (subset of all device features) */
6670 netdev->hw_features = netdev->features;
0184039a 6671 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6672 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6673 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6674
6675 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6676 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6677
dc221294
BA		 6678 netdev->vlan_features |= (NETIF_F_SG |
6679 NETIF_F_TSO |
6680 NETIF_F_TSO6 |
6681 NETIF_F_HW_CSUM);
a5136e23 6682
ef9b965a
JB		 6683 netdev->priv_flags |= IFF_UNICAST_FLT;
6684
7b872a55 6685 if (pci_using_dac) {
bc7f75fa 6686 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6687 netdev->vlan_features |= NETIF_F_HIGHDMA;
6688 }
bc7f75fa 6689
bc7f75fa
AK		 6690 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6691 adapter->flags |= FLAG_MNG_PT_ENABLED;
6692
e921eb1a 6693 /* before reading the NVM, reset the controller to
ad68076e
BA		 6694 * put the device in a known good starting state
6695 */
bc7f75fa
AK		 6696 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6697
e921eb1a 6698 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6699 * attempt. Let's give it a few tries
6700 */
6701 for (i = 0;; i++) {
6702 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6703 break;
6704 if (i == 2) {
185095fb 6705 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6706 err = -EIO;
6707 goto err_eeprom;
6708 }
6709 }
6710
10aa4c04
AK		 6711 e1000_eeprom_checks(adapter);
6712
608f8a0d 6713 /* copy the MAC address */
bc7f75fa 6714 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6715 dev_err(&pdev->dev,
6716 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6717
6718 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6719
aaeb6cdf 6720 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6721 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6722 netdev->dev_addr);
bc7f75fa
AK		 6723 err = -EIO;
6724 goto err_eeprom;
6725 }
6726
6727 init_timer(&adapter->watchdog_timer);
c061b18d 6728 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6729 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6730
6731 init_timer(&adapter->phy_info_timer);
c061b18d 6732 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6733 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6734
6735 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6736 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6737 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6738 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6739 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6740
bc7f75fa
AK		 6741 /* Initialize link parameters. User can change them with ethtool */
6742 adapter->hw.mac.autoneg = 1;
3db1cd5c 6743 adapter->fc_autoneg = true;
5c48ef3e
BA		 6744 adapter->hw.fc.requested_mode = e1000_fc_default;
6745 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6746 adapter->hw.phy.autoneg_advertised = 0x2f;
6747
6748 /* ring size defaults */
d821a4c4
BA		 6749 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6750 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6751
e921eb1a 6752 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6753 * the EEPROM, enable the ACPI Magic Packet filter
6754 */
6755 if (adapter->flags & FLAG_APME_IN_WUC) {
6756 /* APME bit in EEPROM is mapped to WUC.APME */
6757 eeprom_data = er32(WUC);
6758 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6759 if ((hw->mac.type > e1000_ich10lan) &&
6760 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6761 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6762 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6763 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6764 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6765 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6766 1, &eeprom_data);
bc7f75fa 6767 else
3d3a1676
BA		 6768 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6769 1, &eeprom_data);
bc7f75fa
AK		 6770 }
6771
6772 /* fetch WoL from EEPROM */
6773 if (eeprom_data & eeprom_apme_mask)
6774 adapter->eeprom_wol |= E1000_WUFC_MAG;
6775
e921eb1a 6776 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6777 * where the eeprom may be wrong or the board simply won't support
6778 * wake on lan on a particular port
6779 */
6780 if (!(adapter->flags & FLAG_HAS_WOL))
6781 adapter->eeprom_wol = 0;
6782
6783 /* initialize the wol settings based on the eeprom settings */
6784 adapter->wol = adapter->eeprom_wol;
6ff68026 6785 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6786
84527590
BA		 6787 /* save off EEPROM version number */
6788 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6789
bc7f75fa
AK		 6790 /* reset the hardware with the new settings */
6791 e1000e_reset(adapter);
6792
e921eb1a 6793 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6794 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6795 * under the control of the driver.
6796 */
c43bc57e 6797 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6798 e1000e_get_hw_control(adapter);
bc7f75fa 6799
f2315bf1 6800 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6801 err = register_netdev(netdev);
6802 if (err)
6803 goto err_register;
6804
9c563d20
JB		 6805 /* carrier off reporting is important to ethtool even BEFORE open */
6806 netif_carrier_off(netdev);
6807
d89777bf
BA		 6808 /* init PTP hardware clock */
6809 e1000e_ptp_init(adapter);
6810
bc7f75fa
AK		 6811 e1000_print_device_info(adapter);
6812
f3ec4f87
AS		 6813 if (pci_dev_run_wake(pdev))
6814 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6815
bc7f75fa
AK		 6816 return 0;
6817
6818err_register:
c43bc57e 6819 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6820 e1000e_release_hw_control(adapter);
bc7f75fa 6821err_eeprom:
470a5420 6822 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6823 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6824err_hw_init:
bc7f75fa
AK		 6825 kfree(adapter->tx_ring);
6826 kfree(adapter->rx_ring);
6827err_sw_init:
c43bc57e
JB		 6828 if (adapter->hw.flash_address)
6829 iounmap(adapter->hw.flash_address);
e82f54ba 6830 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6831err_flashmap:
bc7f75fa
AK		 6832 iounmap(adapter->hw.hw_addr);
6833err_ioremap:
6834 free_netdev(netdev);
6835err_alloc_etherdev:
f0f422e5 6836 pci_release_selected_regions(pdev,
f0ff4398 6837 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6838err_pci_reg:
6839err_dma:
6840 pci_disable_device(pdev);
6841 return err;
6842}
6843
6844/**
6845 * e1000_remove - Device Removal Routine
6846 * @pdev: PCI device information struct
6847 *
6848 * e1000_remove is called by the PCI subsystem to alert the driver
6849 * that it should release a PCI device. The could be caused by a
6850 * Hot-Plug event, or because the driver is going to be removed from
6851 * memory.
6852 **/
9f9a12f8 6853static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6854{
6855 struct net_device *netdev = pci_get_drvdata(pdev);
6856 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6857 bool down = test_bit(__E1000_DOWN, &adapter->state);
6858
d89777bf
BA		 6859 e1000e_ptp_remove(adapter);
6860
e921eb1a 6861 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6862 * from being rescheduled.
ad68076e 6863 */
23606cf5
RW		 6864 if (!down)
6865 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6866 del_timer_sync(&adapter->watchdog_timer);
6867 del_timer_sync(&adapter->phy_info_timer);
6868
41cec6f1
BA		 6869 cancel_work_sync(&adapter->reset_task);
6870 cancel_work_sync(&adapter->watchdog_task);
6871 cancel_work_sync(&adapter->downshift_task);
6872 cancel_work_sync(&adapter->update_phy_task);
6873 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6874
b67e1913
BA		 6875 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6876 cancel_work_sync(&adapter->tx_hwtstamp_work);
6877 if (adapter->tx_hwtstamp_skb) {
6878 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6879 adapter->tx_hwtstamp_skb = NULL;
6880 }
6881 }
6882
17f208de
BA		 6883 if (!(netdev->flags & IFF_UP))
6884 e1000_power_down_phy(adapter);
6885
23606cf5
RW		 6886 /* Don't lie to e1000_close() down the road. */
6887 if (!down)
6888 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6889 unregister_netdev(netdev);
6890
f3ec4f87
AS		 6891 if (pci_dev_run_wake(pdev))
6892 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6893
e921eb1a 6894 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6895 * would have already happened in close and is redundant.
6896 */
31dbe5b4 6897 e1000e_release_hw_control(adapter);
bc7f75fa 6898
4662e82b 6899 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6900 kfree(adapter->tx_ring);
6901 kfree(adapter->rx_ring);
6902
6903 iounmap(adapter->hw.hw_addr);
6904 if (adapter->hw.flash_address)
6905 iounmap(adapter->hw.flash_address);
f0f422e5 6906 pci_release_selected_regions(pdev,
f0ff4398 6907 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6908
6909 free_netdev(netdev);
6910
111b9dc5 6911 /* AER disable */
19d5afd4 6912 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6913
bc7f75fa
AK		 6914 pci_disable_device(pdev);
6915}
6916
6917/* PCI Error Recovery (ERS) */
3646f0e5 6918static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6919 .error_detected = e1000_io_error_detected,
6920 .slot_reset = e1000_io_slot_reset,
6921 .resume = e1000_io_resume,
6922};
6923
a3aa1884 6924static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 6928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
6929 board_82571 },
bc7f75fa
AK		 6930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6935
bc7f75fa
AK		 6936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6937 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6940
bc7f75fa
AK		 6941 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6943 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6944
4662e82b 6945 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6947 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6948
bc7f75fa
AK		 6949 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6950 board_80003es2lan },
6951 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6952 board_80003es2lan },
6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6954 board_80003es2lan },
6955 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6956 board_80003es2lan },
ad68076e 6957
bc7f75fa
AK		 6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6959 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6964 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6966
bc7f75fa
AK		 6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6969 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6976
6977 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6978 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6979 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6980
f4187b56
BA		 6981 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6982 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6984
a4f58f54
BA		 6985 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6987 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6988 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6989
d3738bb8
BA		 6990 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6991 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6992
2fbe4526
BA		 6993 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6994 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6995 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6996 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6997
f36bb6ca 6998 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6999};
7000MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7001
aa338601 7002#ifdef CONFIG_PM
23606cf5 7003static const struct dev_pm_ops e1000_pm_ops = {
a0340162 7004 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
17e813ec
BA		 7005 SET_RUNTIME_PM_OPS(e1000_runtime_suspend, e1000_runtime_resume,
7006 e1000_idle)
23606cf5 7007};
e50208a0 7008#endif
23606cf5 7009
bc7f75fa
AK		 7010/* PCI Device API Driver */
7011static struct pci_driver e1000_driver = {
7012 .name = e1000e_driver_name,
7013 .id_table = e1000_pci_tbl,
7014 .probe = e1000_probe,
9f9a12f8 7015 .remove = e1000_remove,
aa338601 7016#ifdef CONFIG_PM
f36bb6ca
BA		 7017 .driver = {
7018 .pm = &e1000_pm_ops,
7019 },
bc7f75fa
AK		 7020#endif
7021 .shutdown = e1000_shutdown,
7022 .err_handler = &e1000_err_handler
7023};
7024
7025/**
7026 * e1000_init_module - Driver Registration Routine
7027 *
7028 * e1000_init_module is the first routine called when the driver is
7029 * loaded. All it does is register with the PCI subsystem.
7030 **/
7031static int __init e1000_init_module(void)
7032{
7033 int ret;
8544b9f7
BA		 7034 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7035 e1000e_driver_version);
bf67044b 7036 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
bc7f75fa 7037 ret = pci_register_driver(&e1000_driver);
53ec5498 7038
bc7f75fa
AK		 7039 return ret;
7040}
7041module_init(e1000_init_module);
7042
7043/**
7044 * e1000_exit_module - Driver Exit Cleanup Routine
7045 *
7046 * e1000_exit_module is called just before the driver is removed
7047 * from memory.
7048 **/
7049static void __exit e1000_exit_module(void)
7050{
7051 pci_unregister_driver(&e1000_driver);
7052}
7053module_exit(e1000_exit_module);
7054
7055
7056MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7057MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7058MODULE_LICENSE("GPL");
7059MODULE_VERSION(DRV_VERSION);
7060
06c24b91 7061/* netdev.c */
Linux kernel - Deliverables
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