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e1000e: cleanup incorrect filename in comment
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
058e8edd 59#define DRV_VERSION "1.9.5" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
f36bb6ca 140 {0, NULL}
84f4ee90
TI		 141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29 185 struct my_u0 {
e885d762
BA		 186 __le64 a;
187 __le64 b;
af667a29 188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29 193 struct my_u1 {
e885d762
BA		 194 __le64 a;
195 __le64 b;
196 __le64 c;
197 __le64 d;
af667a29 198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90 223 if (!netdev || !netif_running(netdev))
fe1e980f 224 return;
84f4ee90 225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90 310 if (!netif_msg_rx_status(adapter))
fe1e980f 311 return;
84f4ee90 312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
84f4ee90
TI		 452}
453
bc7f75fa
AK		 454/**
455 * e1000_desc_unused - calculate if we have unused descriptors
456 **/
457static int e1000_desc_unused(struct e1000_ring *ring)
458{
459 if (ring->next_to_clean > ring->next_to_use)
460 return ring->next_to_clean - ring->next_to_use - 1;
461
462 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
463}
464
465/**
ad68076e 466 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 467 * @adapter: board private structure
468 * @status: descriptor status field as written by hardware
469 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
470 * @skb: pointer to sk_buff to be indicated to stack
471 **/
472static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 473 struct net_device *netdev, struct sk_buff *skb,
a39fe742 474 u8 status, __le16 vlan)
bc7f75fa 475{
86d70e53 476 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 477 skb->protocol = eth_type_trans(skb, netdev);
478
86d70e53
JK		 479 if (status & E1000_RXD_STAT_VP)
480 __vlan_hwaccel_put_tag(skb, tag);
481
482 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 483}
484
485/**
af667a29 486 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 487 * @adapter: board private structure
488 * @status_err: receive descriptor status and error fields
489 * @csum: receive descriptor csum field
490 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 491 **/
492static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 493 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 494{
495 u16 status = (u16)status_err;
496 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 497
498 skb_checksum_none_assert(skb);
bc7f75fa 499
afd12939
BA		 500 /* Rx checksum disabled */
501 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
502 return;
503
bc7f75fa
AK		 504 /* Ignore Checksum bit is set */
505 if (status & E1000_RXD_STAT_IXSM)
506 return;
afd12939 507
bc7f75fa
AK		 508 /* TCP/UDP checksum error bit is set */
509 if (errors & E1000_RXD_ERR_TCPE) {
510 /* let the stack verify checksum errors */
511 adapter->hw_csum_err++;
512 return;
513 }
514
515 /* TCP/UDP Checksum has not been calculated */
516 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
517 return;
518
519 /* It must be a TCP or UDP packet with a valid checksum */
520 if (status & E1000_RXD_STAT_TCPCS) {
521 /* TCP checksum is good */
522 skb->ip_summed = CHECKSUM_UNNECESSARY;
523 } else {
ad68076e
BA		 524 /*
525 * IP fragment with UDP payload
526 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 527 * and then put the value in host order for further stack use.
528 */
afd12939 529 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 530 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 531 skb->ip_summed = CHECKSUM_COMPLETE;
532 }
533 adapter->hw_csum_good++;
534}
535
c6e7f51e
BA		 536/**
537 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
538 * @hw: pointer to the HW structure
539 * @tail: address of tail descriptor register
540 * @i: value to write to tail descriptor register
541 *
542 * When updating the tail register, the ME could be accessing Host CSR
543 * registers at the same time. Normally, this is handled in h/w by an
544 * arbiter but on some parts there is a bug that acknowledges Host accesses
545 * later than it should which could result in the descriptor register to
546 * have an incorrect value. Workaround this by checking the FWSM register
547 * which has bit 24 set while ME is accessing Host CSR registers, wait
548 * if it is set and try again a number of times.
549 **/
c5083cf6 550static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 551 unsigned int i)
552{
553 unsigned int j = 0;
554
555 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
556 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
557 udelay(50);
558
559 writel(i, tail);
560
561 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
562 return E1000_ERR_SWFW_SYNC;
563
564 return 0;
565}
566
55aa6985 567static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 568{
55aa6985 569 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 570 struct e1000_hw *hw = &adapter->hw;
571
55aa6985 572 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 573 u32 rctl = er32(RCTL);
574 ew32(RCTL, rctl & ~E1000_RCTL_EN);
575 e_err("ME firmware caused invalid RDT - resetting\n");
576 schedule_work(&adapter->reset_task);
577 }
578}
579
55aa6985 580static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 581{
55aa6985 582 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 583 struct e1000_hw *hw = &adapter->hw;
584
55aa6985 585 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 586 u32 tctl = er32(TCTL);
587 ew32(TCTL, tctl & ~E1000_TCTL_EN);
588 e_err("ME firmware caused invalid TDT - resetting\n");
589 schedule_work(&adapter->reset_task);
590 }
591}
592
bc7f75fa 593/**
5f450212 594 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 595 * @rx_ring: Rx descriptor ring
bc7f75fa 596 **/
55aa6985 597static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 598 int cleaned_count, gfp_t gfp)
bc7f75fa 599{
55aa6985 600 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 601 struct net_device *netdev = adapter->netdev;
602 struct pci_dev *pdev = adapter->pdev;
5f450212 603 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 604 struct e1000_buffer *buffer_info;
605 struct sk_buff *skb;
606 unsigned int i;
89d71a66 607 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 608
609 i = rx_ring->next_to_use;
610 buffer_info = &rx_ring->buffer_info[i];
611
612 while (cleaned_count--) {
613 skb = buffer_info->skb;
614 if (skb) {
615 skb_trim(skb, 0);
616 goto map_skb;
617 }
618
c2fed996 619 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 620 if (!skb) {
621 /* Better luck next round */
622 adapter->alloc_rx_buff_failed++;
623 break;
624 }
625
bc7f75fa
AK		 626 buffer_info->skb = skb;
627map_skb:
0be3f55f 628 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 629 adapter->rx_buffer_len,
0be3f55f
NN		 630 DMA_FROM_DEVICE);
631 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 632 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 633 adapter->rx_dma_failed++;
634 break;
635 }
636
5f450212
BA		 637 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
638 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 639
50849d79
TH		 640 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
641 /*
642 * Force memory writes to complete before letting h/w
643 * know there are new descriptors to fetch. (Only
644 * applicable for weak-ordered memory model archs,
645 * such as IA-64).
646 */
647 wmb();
c6e7f51e 648 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 649 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 650 else
c5083cf6 651 writel(i, rx_ring->tail);
50849d79 652 }
bc7f75fa
AK		 653 i++;
654 if (i == rx_ring->count)
655 i = 0;
656 buffer_info = &rx_ring->buffer_info[i];
657 }
658
50849d79 659 rx_ring->next_to_use = i;
bc7f75fa
AK		 660}
661
662/**
663 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 664 * @rx_ring: Rx descriptor ring
bc7f75fa 665 **/
55aa6985 666static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 667 int cleaned_count, gfp_t gfp)
bc7f75fa 668{
55aa6985 669 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 670 struct net_device *netdev = adapter->netdev;
671 struct pci_dev *pdev = adapter->pdev;
672 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 673 struct e1000_buffer *buffer_info;
674 struct e1000_ps_page *ps_page;
675 struct sk_buff *skb;
676 unsigned int i, j;
677
678 i = rx_ring->next_to_use;
679 buffer_info = &rx_ring->buffer_info[i];
680
681 while (cleaned_count--) {
682 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683
684 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 685 ps_page = &buffer_info->ps_pages[j];
686 if (j >= adapter->rx_ps_pages) {
687 /* all unused desc entries get hw null ptr */
af667a29
BA		 688 rx_desc->read.buffer_addr[j + 1] =
689 ~cpu_to_le64(0);
47f44e40
AK		 690 continue;
691 }
692 if (!ps_page->page) {
c2fed996 693 ps_page->page = alloc_page(gfp);
bc7f75fa 694 if (!ps_page->page) {
47f44e40
AK		 695 adapter->alloc_rx_buff_failed++;
696 goto no_buffers;
697 }
0be3f55f
NN		 698 ps_page->dma = dma_map_page(&pdev->dev,
699 ps_page->page,
700 0, PAGE_SIZE,
701 DMA_FROM_DEVICE);
702 if (dma_mapping_error(&pdev->dev,
703 ps_page->dma)) {
47f44e40 704 dev_err(&adapter->pdev->dev,
af667a29 705 "Rx DMA page map failed\n");
47f44e40
AK		 706 adapter->rx_dma_failed++;
707 goto no_buffers;
bc7f75fa 708 }
bc7f75fa 709 }
47f44e40
AK		 710 /*
711 * Refresh the desc even if buffer_addrs
712 * didn't change because each write-back
713 * erases this info.
714 */
af667a29
BA		 715 rx_desc->read.buffer_addr[j + 1] =
716 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 717 }
718
c2fed996
JK		 719 skb = __netdev_alloc_skb_ip_align(netdev,
720 adapter->rx_ps_bsize0,
721 gfp);
bc7f75fa
AK		 722
723 if (!skb) {
724 adapter->alloc_rx_buff_failed++;
725 break;
726 }
727
bc7f75fa 728 buffer_info->skb = skb;
0be3f55f 729 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 730 adapter->rx_ps_bsize0,
0be3f55f
NN		 731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 733 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 734 adapter->rx_dma_failed++;
735 /* cleanup skb */
736 dev_kfree_skb_any(skb);
737 buffer_info->skb = NULL;
738 break;
739 }
740
741 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
742
50849d79
TH		 743 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
744 /*
745 * Force memory writes to complete before letting h/w
746 * know there are new descriptors to fetch. (Only
747 * applicable for weak-ordered memory model archs,
748 * such as IA-64).
749 */
750 wmb();
c6e7f51e 751 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 752 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 753 else
c5083cf6 754 writel(i << 1, rx_ring->tail);
50849d79
TH		 755 }
756
bc7f75fa
AK		 757 i++;
758 if (i == rx_ring->count)
759 i = 0;
760 buffer_info = &rx_ring->buffer_info[i];
761 }
762
763no_buffers:
50849d79 764 rx_ring->next_to_use = i;
bc7f75fa
AK		 765}
766
97ac8cae
BA		 767/**
768 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 769 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 770 * @cleaned_count: number of buffers to allocate this pass
771 **/
772
55aa6985 773static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 774 int cleaned_count, gfp_t gfp)
97ac8cae 775{
55aa6985 776 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 777 struct net_device *netdev = adapter->netdev;
778 struct pci_dev *pdev = adapter->pdev;
5f450212 779 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 780 struct e1000_buffer *buffer_info;
781 struct sk_buff *skb;
782 unsigned int i;
89d71a66 783 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 784
785 i = rx_ring->next_to_use;
786 buffer_info = &rx_ring->buffer_info[i];
787
788 while (cleaned_count--) {
789 skb = buffer_info->skb;
790 if (skb) {
791 skb_trim(skb, 0);
792 goto check_page;
793 }
794
c2fed996 795 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 796 if (unlikely(!skb)) {
797 /* Better luck next round */
798 adapter->alloc_rx_buff_failed++;
799 break;
800 }
801
97ac8cae
BA		 802 buffer_info->skb = skb;
803check_page:
804 /* allocate a new page if necessary */
805 if (!buffer_info->page) {
c2fed996 806 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 807 if (unlikely(!buffer_info->page)) {
808 adapter->alloc_rx_buff_failed++;
809 break;
810 }
811 }
812
813 if (!buffer_info->dma)
0be3f55f 814 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 815 buffer_info->page, 0,
816 PAGE_SIZE,
0be3f55f 817 DMA_FROM_DEVICE);
97ac8cae 818
5f450212
BA		 819 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
820 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 821
822 if (unlikely(++i == rx_ring->count))
823 i = 0;
824 buffer_info = &rx_ring->buffer_info[i];
825 }
826
827 if (likely(rx_ring->next_to_use != i)) {
828 rx_ring->next_to_use = i;
829 if (unlikely(i-- == 0))
830 i = (rx_ring->count - 1);
831
832 /* Force memory writes to complete before letting h/w
833 * know there are new descriptors to fetch. (Only
834 * applicable for weak-ordered memory model archs,
835 * such as IA-64). */
836 wmb();
c6e7f51e 837 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 838 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 839 else
c5083cf6 840 writel(i, rx_ring->tail);
97ac8cae
BA		 841 }
842}
843
70495a50
BA		 844static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
845 struct sk_buff *skb)
846{
847 if (netdev->features & NETIF_F_RXHASH)
848 skb->rxhash = le32_to_cpu(rss);
849}
850
bc7f75fa 851/**
55aa6985
BA		 852 * e1000_clean_rx_irq - Send received data up the network stack
853 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 854 *
855 * the return value indicates whether actual cleaning was done, there
856 * is no guarantee that everything was cleaned
857 **/
55aa6985
BA		 858static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
859 int work_to_do)
bc7f75fa 860{
55aa6985 861 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 862 struct net_device *netdev = adapter->netdev;
863 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 864 struct e1000_hw *hw = &adapter->hw;
5f450212 865 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 866 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 867 u32 length, staterr;
bc7f75fa
AK		 868 unsigned int i;
869 int cleaned_count = 0;
3db1cd5c 870 bool cleaned = false;
bc7f75fa
AK		 871 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
872
873 i = rx_ring->next_to_clean;
5f450212
BA		 874 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
875 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 876 buffer_info = &rx_ring->buffer_info[i];
877
5f450212 878 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 879 struct sk_buff *skb;
bc7f75fa
AK		 880
881 if (*work_done >= work_to_do)
882 break;
883 (*work_done)++;
2d0bb1c1 884 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 885
bc7f75fa
AK		 886 skb = buffer_info->skb;
887 buffer_info->skb = NULL;
888
889 prefetch(skb->data - NET_IP_ALIGN);
890
891 i++;
892 if (i == rx_ring->count)
893 i = 0;
5f450212 894 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 895 prefetch(next_rxd);
896
897 next_buffer = &rx_ring->buffer_info[i];
898
3db1cd5c 899 cleaned = true;
bc7f75fa 900 cleaned_count++;
0be3f55f 901 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 902 buffer_info->dma,
903 adapter->rx_buffer_len,
0be3f55f 904 DMA_FROM_DEVICE);
bc7f75fa
AK		 905 buffer_info->dma = 0;
906
5f450212 907 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 908
b94b5028
JB		 909 /*
910 * !EOP means multiple descriptors were used to store a single
911 * packet, if that's the case we need to toss it. In fact, we
912 * need to toss every packet with the EOP bit clear and the
913 * next frame that _does_ have the EOP bit set, as it is by
914 * definition only a frame fragment
915 */
5f450212 916 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 917 adapter->flags2 |= FLAG2_IS_DISCARDING;
918
919 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 920 /* All receives must fit into a single buffer */
3bb99fe2 921 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 922 /* recycle */
923 buffer_info->skb = skb;
5f450212 924 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 925 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 926 goto next_desc;
927 }
928
cf955e6c
BG		 929 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
930 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 931 /* recycle */
932 buffer_info->skb = skb;
933 goto next_desc;
934 }
935
eb7c3adb 936 /* adjust length to remove Ethernet CRC */
0184039a
BG		 937 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
938 /* If configured to store CRC, don't subtract FCS,
939 * but keep the FCS bytes out of the total_rx_bytes
940 * counter
941 */
942 if (netdev->features & NETIF_F_RXFCS)
943 total_rx_bytes -= 4;
944 else
945 length -= 4;
946 }
eb7c3adb 947
bc7f75fa
AK		 948 total_rx_bytes += length;
949 total_rx_packets++;
950
ad68076e
BA		 951 /*
952 * code added for copybreak, this should improve
bc7f75fa 953 * performance for small packets with large amounts
ad68076e
BA		 954 * of reassembly being done in the stack
955 */
bc7f75fa
AK		 956 if (length < copybreak) {
957 struct sk_buff *new_skb =
89d71a66 958 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 959 if (new_skb) {
808ff676
BA		 960 skb_copy_to_linear_data_offset(new_skb,
961 -NET_IP_ALIGN,
962 (skb->data -
963 NET_IP_ALIGN),
964 (length +
965 NET_IP_ALIGN));
bc7f75fa
AK		 966 /* save the skb in buffer_info as good */
967 buffer_info->skb = skb;
968 skb = new_skb;
969 }
970 /* else just continue with the old one */
971 }
972 /* end copybreak code */
973 skb_put(skb, length);
974
975 /* Receive Checksum Offload */
5f450212 976 e1000_rx_checksum(adapter, staterr,
afd12939 977 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 978
70495a50
BA		 979 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
980
5f450212
BA		 981 e1000_receive_skb(adapter, netdev, skb, staterr,
982 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 983
984next_desc:
5f450212 985 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 986
987 /* return some buffers to hardware, one at a time is too slow */
988 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 989 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 990 GFP_ATOMIC);
bc7f75fa
AK		 991 cleaned_count = 0;
992 }
993
994 /* use prefetched values */
995 rx_desc = next_rxd;
996 buffer_info = next_buffer;
5f450212
BA		 997
998 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 999 }
1000 rx_ring->next_to_clean = i;
1001
1002 cleaned_count = e1000_desc_unused(rx_ring);
1003 if (cleaned_count)
55aa6985 1004 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1005
bc7f75fa 1006 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1007 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1008 return cleaned;
1009}
1010
55aa6985
BA		 1011static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1012 struct e1000_buffer *buffer_info)
bc7f75fa 1013{
55aa6985
BA		 1014 struct e1000_adapter *adapter = tx_ring->adapter;
1015
03b1320d
AD		 1016 if (buffer_info->dma) {
1017 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1018 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1019 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1020 else
0be3f55f
NN		 1021 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1022 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1023 buffer_info->dma = 0;
1024 }
bc7f75fa
AK		 1025 if (buffer_info->skb) {
1026 dev_kfree_skb_any(buffer_info->skb);
1027 buffer_info->skb = NULL;
1028 }
1b7719c4 1029 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1030}
1031
41cec6f1 1032static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1033{
41cec6f1
BA		 1034 struct e1000_adapter *adapter = container_of(work,
1035 struct e1000_adapter,
1036 print_hang_task);
09357b00 1037 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1038 struct e1000_ring *tx_ring = adapter->tx_ring;
1039 unsigned int i = tx_ring->next_to_clean;
1040 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1041 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1042 struct e1000_hw *hw = &adapter->hw;
1043 u16 phy_status, phy_1000t_status, phy_ext_status;
1044 u16 pci_status;
1045
615b32af
JB		 1046 if (test_bit(__E1000_DOWN, &adapter->state))
1047 return;
1048
09357b00
JK		 1049 if (!adapter->tx_hang_recheck &&
1050 (adapter->flags2 & FLAG2_DMA_BURST)) {
1051 /* May be block on write-back, flush and detect again
1052 * flush pending descriptor writebacks to memory
1053 */
1054 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1055 /* execute the writes immediately */
1056 e1e_flush();
1057 adapter->tx_hang_recheck = true;
1058 return;
1059 }
1060 /* Real hang detected */
1061 adapter->tx_hang_recheck = false;
1062 netif_stop_queue(netdev);
1063
41cec6f1
BA		 1064 e1e_rphy(hw, PHY_STATUS, &phy_status);
1065 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1066 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1067
41cec6f1
BA		 1068 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1069
1070 /* detected Hardware unit hang */
1071 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1072 " TDH <%x>\n"
1073 " TDT <%x>\n"
1074 " next_to_use <%x>\n"
1075 " next_to_clean <%x>\n"
1076 "buffer_info[next_to_clean]:\n"
1077 " time_stamp <%lx>\n"
1078 " next_to_watch <%x>\n"
1079 " jiffies <%lx>\n"
41cec6f1
BA		 1080 " next_to_watch.status <%x>\n"
1081 "MAC Status <%x>\n"
1082 "PHY Status <%x>\n"
1083 "PHY 1000BASE-T Status <%x>\n"
1084 "PHY Extended Status <%x>\n"
1085 "PCI Status <%x>\n",
c5083cf6
BA		 1086 readl(tx_ring->head),
1087 readl(tx_ring->tail),
44defeb3
JK		 1088 tx_ring->next_to_use,
1089 tx_ring->next_to_clean,
1090 tx_ring->buffer_info[eop].time_stamp,
1091 eop,
1092 jiffies,
41cec6f1
BA		 1093 eop_desc->upper.fields.status,
1094 er32(STATUS),
1095 phy_status,
1096 phy_1000t_status,
1097 phy_ext_status,
1098 pci_status);
bc7f75fa
AK		 1099}
1100
1101/**
1102 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1103 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1104 *
1105 * the return value indicates whether actual cleaning was done, there
1106 * is no guarantee that everything was cleaned
1107 **/
55aa6985 1108static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1109{
55aa6985 1110 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1111 struct net_device *netdev = adapter->netdev;
1112 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1113 struct e1000_tx_desc *tx_desc, *eop_desc;
1114 struct e1000_buffer *buffer_info;
1115 unsigned int i, eop;
1116 unsigned int count = 0;
bc7f75fa 1117 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1118 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1119
1120 i = tx_ring->next_to_clean;
1121 eop = tx_ring->buffer_info[i].next_to_watch;
1122 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1123
12d04a3c
AD		 1124 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1125 (count < tx_ring->count)) {
a86043c2 1126 bool cleaned = false;
2d0bb1c1 1127 rmb(); /* read buffer_info after eop_desc */
a86043c2 1128 for (; !cleaned; count++) {
bc7f75fa
AK		 1129 tx_desc = E1000_TX_DESC(*tx_ring, i);
1130 buffer_info = &tx_ring->buffer_info[i];
1131 cleaned = (i == eop);
1132
1133 if (cleaned) {
9ed318d5
TH		 1134 total_tx_packets += buffer_info->segs;
1135 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1136 if (buffer_info->skb) {
1137 bytes_compl += buffer_info->skb->len;
1138 pkts_compl++;
1139 }
bc7f75fa
AK		 1140 }
1141
55aa6985 1142 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1143 tx_desc->upper.data = 0;
1144
1145 i++;
1146 if (i == tx_ring->count)
1147 i = 0;
1148 }
1149
dac87619
TL		 1150 if (i == tx_ring->next_to_use)
1151 break;
bc7f75fa
AK		 1152 eop = tx_ring->buffer_info[i].next_to_watch;
1153 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1154 }
1155
1156 tx_ring->next_to_clean = i;
1157
3f0cfa3b
TH		 1158 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1159
bc7f75fa 1160#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1161 if (count && netif_carrier_ok(netdev) &&
1162 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1163 /* Make sure that anybody stopping the queue after this
1164 * sees the new next_to_clean.
1165 */
1166 smp_mb();
1167
1168 if (netif_queue_stopped(netdev) &&
1169 !(test_bit(__E1000_DOWN, &adapter->state))) {
1170 netif_wake_queue(netdev);
1171 ++adapter->restart_queue;
1172 }
1173 }
1174
1175 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1176 /*
1177 * Detect a transmit hang in hardware, this serializes the
1178 * check with the clearing of time_stamp and movement of i
1179 */
3db1cd5c 1180 adapter->detect_tx_hung = false;
12d04a3c
AD		 1181 if (tx_ring->buffer_info[i].time_stamp &&
1182 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1183 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1184 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1185 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1186 else
1187 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1188 }
1189 adapter->total_tx_bytes += total_tx_bytes;
1190 adapter->total_tx_packets += total_tx_packets;
807540ba 1191 return count < tx_ring->count;
bc7f75fa
AK		 1192}
1193
bc7f75fa
AK		 1194/**
1195 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1196 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1197 *
1198 * the return value indicates whether actual cleaning was done, there
1199 * is no guarantee that everything was cleaned
1200 **/
55aa6985
BA		 1201static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1202 int work_to_do)
bc7f75fa 1203{
55aa6985 1204 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1205 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1206 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1207 struct net_device *netdev = adapter->netdev;
1208 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1209 struct e1000_buffer *buffer_info, *next_buffer;
1210 struct e1000_ps_page *ps_page;
1211 struct sk_buff *skb;
1212 unsigned int i, j;
1213 u32 length, staterr;
1214 int cleaned_count = 0;
3db1cd5c 1215 bool cleaned = false;
bc7f75fa
AK		 1216 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1217
1218 i = rx_ring->next_to_clean;
1219 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1220 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1221 buffer_info = &rx_ring->buffer_info[i];
1222
1223 while (staterr & E1000_RXD_STAT_DD) {
1224 if (*work_done >= work_to_do)
1225 break;
1226 (*work_done)++;
1227 skb = buffer_info->skb;
2d0bb1c1 1228 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1229
1230 /* in the packet split case this is header only */
1231 prefetch(skb->data - NET_IP_ALIGN);
1232
1233 i++;
1234 if (i == rx_ring->count)
1235 i = 0;
1236 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1237 prefetch(next_rxd);
1238
1239 next_buffer = &rx_ring->buffer_info[i];
1240
3db1cd5c 1241 cleaned = true;
bc7f75fa 1242 cleaned_count++;
0be3f55f 1243 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1244 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1245 buffer_info->dma = 0;
1246
af667a29 1247 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1248 if (!(staterr & E1000_RXD_STAT_EOP))
1249 adapter->flags2 |= FLAG2_IS_DISCARDING;
1250
1251 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1252 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1253 dev_kfree_skb_irq(skb);
b94b5028
JB		 1254 if (staterr & E1000_RXD_STAT_EOP)
1255 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1256 goto next_desc;
1257 }
1258
cf955e6c
BG		 1259 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1260 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1261 dev_kfree_skb_irq(skb);
1262 goto next_desc;
1263 }
1264
1265 length = le16_to_cpu(rx_desc->wb.middle.length0);
1266
1267 if (!length) {
ef456f85 1268 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1269 dev_kfree_skb_irq(skb);
1270 goto next_desc;
1271 }
1272
1273 /* Good Receive */
1274 skb_put(skb, length);
1275
1276 {
0e15df49
BA		 1277 /*
1278 * this looks ugly, but it seems compiler issues make
1279 * it more efficient than reusing j
1280 */
1281 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1282
ad68076e 1283 /*
0e15df49
BA		 1284 * page alloc/put takes too long and effects small
1285 * packet throughput, so unsplit small packets and
1286 * save the alloc/put only valid in softirq (napi)
1287 * context to call kmap_*
ad68076e 1288 */
0e15df49
BA		 1289 if (l1 && (l1 <= copybreak) &&
1290 ((length + l1) <= adapter->rx_ps_bsize0)) {
1291 u8 *vaddr;
1292
1293 ps_page = &buffer_info->ps_pages[0];
1294
1295 /*
1296 * there is no documentation about how to call
1297 * kmap_atomic, so we can't hold the mapping
1298 * very long
1299 */
1300 dma_sync_single_for_cpu(&pdev->dev,
1301 ps_page->dma,
1302 PAGE_SIZE,
1303 DMA_FROM_DEVICE);
1304 vaddr = kmap_atomic(ps_page->page,
1305 KM_SKB_DATA_SOFTIRQ);
1306 memcpy(skb_tail_pointer(skb), vaddr, l1);
1307 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
1308 dma_sync_single_for_device(&pdev->dev,
1309 ps_page->dma,
1310 PAGE_SIZE,
1311 DMA_FROM_DEVICE);
1312
1313 /* remove the CRC */
0184039a
BG		 1314 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1315 if (!(netdev->features & NETIF_F_RXFCS))
1316 l1 -= 4;
1317 }
0e15df49
BA		 1318
1319 skb_put(skb, l1);
1320 goto copydone;
1321 } /* if */
bc7f75fa
AK		 1322 }
1323
1324 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1325 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1326 if (!length)
1327 break;
1328
47f44e40 1329 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1330 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1331 DMA_FROM_DEVICE);
bc7f75fa
AK		 1332 ps_page->dma = 0;
1333 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1334 ps_page->page = NULL;
1335 skb->len += length;
1336 skb->data_len += length;
98a045d7 1337 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1338 }
1339
eb7c3adb
JK		 1340 /* strip the ethernet crc, problem is we're using pages now so
1341 * this whole operation can get a little cpu intensive
1342 */
0184039a
BG		 1343 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1344 if (!(netdev->features & NETIF_F_RXFCS))
1345 pskb_trim(skb, skb->len - 4);
1346 }
eb7c3adb 1347
bc7f75fa
AK		 1348copydone:
1349 total_rx_bytes += skb->len;
1350 total_rx_packets++;
1351
afd12939
BA		 1352 e1000_rx_checksum(adapter, staterr,
1353 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1354
70495a50
BA		 1355 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1356
bc7f75fa
AK		 1357 if (rx_desc->wb.upper.header_status &
1358 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1359 adapter->rx_hdr_split++;
1360
1361 e1000_receive_skb(adapter, netdev, skb,
1362 staterr, rx_desc->wb.middle.vlan);
1363
1364next_desc:
1365 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1366 buffer_info->skb = NULL;
1367
1368 /* return some buffers to hardware, one at a time is too slow */
1369 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1370 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1371 GFP_ATOMIC);
bc7f75fa
AK		 1372 cleaned_count = 0;
1373 }
1374
1375 /* use prefetched values */
1376 rx_desc = next_rxd;
1377 buffer_info = next_buffer;
1378
1379 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1380 }
1381 rx_ring->next_to_clean = i;
1382
1383 cleaned_count = e1000_desc_unused(rx_ring);
1384 if (cleaned_count)
55aa6985 1385 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1386
bc7f75fa 1387 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1388 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1389 return cleaned;
1390}
1391
97ac8cae
BA		 1392/**
1393 * e1000_consume_page - helper function
1394 **/
1395static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1396 u16 length)
1397{
1398 bi->page = NULL;
1399 skb->len += length;
1400 skb->data_len += length;
98a045d7 1401 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1402}
1403
1404/**
1405 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1406 * @adapter: board private structure
1407 *
1408 * the return value indicates whether actual cleaning was done, there
1409 * is no guarantee that everything was cleaned
1410 **/
55aa6985
BA		 1411static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1412 int work_to_do)
97ac8cae 1413{
55aa6985 1414 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1415 struct net_device *netdev = adapter->netdev;
1416 struct pci_dev *pdev = adapter->pdev;
5f450212 1417 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1418 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1419 u32 length, staterr;
97ac8cae
BA		 1420 unsigned int i;
1421 int cleaned_count = 0;
1422 bool cleaned = false;
1423 unsigned int total_rx_bytes=0, total_rx_packets=0;
1424
1425 i = rx_ring->next_to_clean;
5f450212
BA		 1426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1427 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1428 buffer_info = &rx_ring->buffer_info[i];
1429
5f450212 1430 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1431 struct sk_buff *skb;
97ac8cae
BA		 1432
1433 if (*work_done >= work_to_do)
1434 break;
1435 (*work_done)++;
2d0bb1c1 1436 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1437
97ac8cae
BA		 1438 skb = buffer_info->skb;
1439 buffer_info->skb = NULL;
1440
1441 ++i;
1442 if (i == rx_ring->count)
1443 i = 0;
5f450212 1444 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1445 prefetch(next_rxd);
1446
1447 next_buffer = &rx_ring->buffer_info[i];
1448
1449 cleaned = true;
1450 cleaned_count++;
0be3f55f
NN		 1451 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1452 DMA_FROM_DEVICE);
97ac8cae
BA		 1453 buffer_info->dma = 0;
1454
5f450212 1455 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1456
1457 /* errors is only valid for DD + EOP descriptors */
5f450212 1458 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1459 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1460 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1461 /* recycle both page and skb */
1462 buffer_info->skb = skb;
1463 /* an error means any chain goes out the window too */
1464 if (rx_ring->rx_skb_top)
1465 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1466 rx_ring->rx_skb_top = NULL;
1467 goto next_desc;
97ac8cae
BA		 1468 }
1469
f0f1a172 1470#define rxtop (rx_ring->rx_skb_top)
5f450212 1471 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1472 /* this descriptor is only the beginning (or middle) */
1473 if (!rxtop) {
1474 /* this is the beginning of a chain */
1475 rxtop = skb;
1476 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1477 0, length);
1478 } else {
1479 /* this is the middle of a chain */
1480 skb_fill_page_desc(rxtop,
1481 skb_shinfo(rxtop)->nr_frags,
1482 buffer_info->page, 0, length);
1483 /* re-use the skb, only consumed the page */
1484 buffer_info->skb = skb;
1485 }
1486 e1000_consume_page(buffer_info, rxtop, length);
1487 goto next_desc;
1488 } else {
1489 if (rxtop) {
1490 /* end of the chain */
1491 skb_fill_page_desc(rxtop,
1492 skb_shinfo(rxtop)->nr_frags,
1493 buffer_info->page, 0, length);
1494 /* re-use the current skb, we only consumed the
1495 * page */
1496 buffer_info->skb = skb;
1497 skb = rxtop;
1498 rxtop = NULL;
1499 e1000_consume_page(buffer_info, skb, length);
1500 } else {
1501 /* no chain, got EOP, this buf is the packet
1502 * copybreak to save the put_page/alloc_page */
1503 if (length <= copybreak &&
1504 skb_tailroom(skb) >= length) {
1505 u8 *vaddr;
1506 vaddr = kmap_atomic(buffer_info->page,
1507 KM_SKB_DATA_SOFTIRQ);
1508 memcpy(skb_tail_pointer(skb), vaddr,
1509 length);
1510 kunmap_atomic(vaddr,
1511 KM_SKB_DATA_SOFTIRQ);
1512 /* re-use the page, so don't erase
1513 * buffer_info->page */
1514 skb_put(skb, length);
1515 } else {
1516 skb_fill_page_desc(skb, 0,
1517 buffer_info->page, 0,
1518 length);
1519 e1000_consume_page(buffer_info, skb,
1520 length);
1521 }
1522 }
1523 }
1524
1525 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1526 e1000_rx_checksum(adapter, staterr,
afd12939 1527 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1528
70495a50
BA		 1529 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1530
97ac8cae
BA		 1531 /* probably a little skewed due to removing CRC */
1532 total_rx_bytes += skb->len;
1533 total_rx_packets++;
1534
1535 /* eth type trans needs skb->data to point to something */
1536 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1537 e_err("pskb_may_pull failed.\n");
ef5ab89c 1538 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1539 goto next_desc;
1540 }
1541
5f450212
BA		 1542 e1000_receive_skb(adapter, netdev, skb, staterr,
1543 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1544
1545next_desc:
5f450212 1546 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1547
1548 /* return some buffers to hardware, one at a time is too slow */
1549 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1550 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1551 GFP_ATOMIC);
97ac8cae
BA		 1552 cleaned_count = 0;
1553 }
1554
1555 /* use prefetched values */
1556 rx_desc = next_rxd;
1557 buffer_info = next_buffer;
5f450212
BA		 1558
1559 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1560 }
1561 rx_ring->next_to_clean = i;
1562
1563 cleaned_count = e1000_desc_unused(rx_ring);
1564 if (cleaned_count)
55aa6985 1565 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1566
1567 adapter->total_rx_bytes += total_rx_bytes;
1568 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1569 return cleaned;
1570}
1571
bc7f75fa
AK		 1572/**
1573 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1574 * @rx_ring: Rx descriptor ring
bc7f75fa 1575 **/
55aa6985 1576static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1577{
55aa6985 1578 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1579 struct e1000_buffer *buffer_info;
1580 struct e1000_ps_page *ps_page;
1581 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1582 unsigned int i, j;
1583
1584 /* Free all the Rx ring sk_buffs */
1585 for (i = 0; i < rx_ring->count; i++) {
1586 buffer_info = &rx_ring->buffer_info[i];
1587 if (buffer_info->dma) {
1588 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1589 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1590 adapter->rx_buffer_len,
0be3f55f 1591 DMA_FROM_DEVICE);
97ac8cae 1592 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1593 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1594 PAGE_SIZE,
0be3f55f 1595 DMA_FROM_DEVICE);
bc7f75fa 1596 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1597 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1598 adapter->rx_ps_bsize0,
0be3f55f 1599 DMA_FROM_DEVICE);
bc7f75fa
AK		 1600 buffer_info->dma = 0;
1601 }
1602
97ac8cae
BA		 1603 if (buffer_info->page) {
1604 put_page(buffer_info->page);
1605 buffer_info->page = NULL;
1606 }
1607
bc7f75fa
AK		 1608 if (buffer_info->skb) {
1609 dev_kfree_skb(buffer_info->skb);
1610 buffer_info->skb = NULL;
1611 }
1612
1613 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1614 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1615 if (!ps_page->page)
1616 break;
0be3f55f
NN		 1617 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1618 DMA_FROM_DEVICE);
bc7f75fa
AK		 1619 ps_page->dma = 0;
1620 put_page(ps_page->page);
1621 ps_page->page = NULL;
1622 }
1623 }
1624
1625 /* there also may be some cached data from a chained receive */
1626 if (rx_ring->rx_skb_top) {
1627 dev_kfree_skb(rx_ring->rx_skb_top);
1628 rx_ring->rx_skb_top = NULL;
1629 }
1630
bc7f75fa
AK		 1631 /* Zero out the descriptor ring */
1632 memset(rx_ring->desc, 0, rx_ring->size);
1633
1634 rx_ring->next_to_clean = 0;
1635 rx_ring->next_to_use = 0;
b94b5028 1636 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1637
c5083cf6
BA		 1638 writel(0, rx_ring->head);
1639 writel(0, rx_ring->tail);
bc7f75fa
AK		 1640}
1641
a8f88ff5
JB		 1642static void e1000e_downshift_workaround(struct work_struct *work)
1643{
1644 struct e1000_adapter *adapter = container_of(work,
1645 struct e1000_adapter, downshift_task);
1646
615b32af
JB		 1647 if (test_bit(__E1000_DOWN, &adapter->state))
1648 return;
1649
a8f88ff5
JB		 1650 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1651}
1652
bc7f75fa
AK		 1653/**
1654 * e1000_intr_msi - Interrupt Handler
1655 * @irq: interrupt number
1656 * @data: pointer to a network interface device structure
1657 **/
1658static irqreturn_t e1000_intr_msi(int irq, void *data)
1659{
1660 struct net_device *netdev = data;
1661 struct e1000_adapter *adapter = netdev_priv(netdev);
1662 struct e1000_hw *hw = &adapter->hw;
1663 u32 icr = er32(ICR);
1664
ad68076e
BA		 1665 /*
1666 * read ICR disables interrupts using IAM
1667 */
bc7f75fa 1668
573cca8c 1669 if (icr & E1000_ICR_LSC) {
f92518dd 1670 hw->mac.get_link_status = true;
ad68076e
BA		 1671 /*
1672 * ICH8 workaround-- Call gig speed drop workaround on cable
1673 * disconnect (LSC) before accessing any PHY registers
1674 */
bc7f75fa
AK		 1675 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1676 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1677 schedule_work(&adapter->downshift_task);
bc7f75fa 1678
ad68076e
BA		 1679 /*
1680 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1681 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1682 * adapter in watchdog
1683 */
bc7f75fa
AK		 1684 if (netif_carrier_ok(netdev) &&
1685 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1686 /* disable receives */
1687 u32 rctl = er32(RCTL);
1688 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1689 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1690 }
1691 /* guard against interrupt when we're going down */
1692 if (!test_bit(__E1000_DOWN, &adapter->state))
1693 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1694 }
1695
288379f0 1696 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1697 adapter->total_tx_bytes = 0;
1698 adapter->total_tx_packets = 0;
1699 adapter->total_rx_bytes = 0;
1700 adapter->total_rx_packets = 0;
288379f0 1701 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1702 }
1703
1704 return IRQ_HANDLED;
1705}
1706
1707/**
1708 * e1000_intr - Interrupt Handler
1709 * @irq: interrupt number
1710 * @data: pointer to a network interface device structure
1711 **/
1712static irqreturn_t e1000_intr(int irq, void *data)
1713{
1714 struct net_device *netdev = data;
1715 struct e1000_adapter *adapter = netdev_priv(netdev);
1716 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1717 u32 rctl, icr = er32(ICR);
4662e82b 1718
a68ea775 1719 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1720 return IRQ_NONE; /* Not our interrupt */
1721
ad68076e
BA		 1722 /*
1723 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1724 * not set, then the adapter didn't send an interrupt
1725 */
bc7f75fa
AK		 1726 if (!(icr & E1000_ICR_INT_ASSERTED))
1727 return IRQ_NONE;
1728
ad68076e
BA		 1729 /*
1730 * Interrupt Auto-Mask...upon reading ICR,
1731 * interrupts are masked. No need for the
1732 * IMC write
1733 */
bc7f75fa 1734
573cca8c 1735 if (icr & E1000_ICR_LSC) {
f92518dd 1736 hw->mac.get_link_status = true;
ad68076e
BA		 1737 /*
1738 * ICH8 workaround-- Call gig speed drop workaround on cable
1739 * disconnect (LSC) before accessing any PHY registers
1740 */
bc7f75fa
AK		 1741 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1742 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1743 schedule_work(&adapter->downshift_task);
bc7f75fa 1744
ad68076e
BA		 1745 /*
1746 * 80003ES2LAN workaround--
bc7f75fa
AK		 1747 * For packet buffer work-around on link down event;
1748 * disable receives here in the ISR and
1749 * reset adapter in watchdog
1750 */
1751 if (netif_carrier_ok(netdev) &&
1752 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1753 /* disable receives */
1754 rctl = er32(RCTL);
1755 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1756 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1757 }
1758 /* guard against interrupt when we're going down */
1759 if (!test_bit(__E1000_DOWN, &adapter->state))
1760 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1761 }
1762
288379f0 1763 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1764 adapter->total_tx_bytes = 0;
1765 adapter->total_tx_packets = 0;
1766 adapter->total_rx_bytes = 0;
1767 adapter->total_rx_packets = 0;
288379f0 1768 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1769 }
1770
1771 return IRQ_HANDLED;
1772}
1773
4662e82b
BA		 1774static irqreturn_t e1000_msix_other(int irq, void *data)
1775{
1776 struct net_device *netdev = data;
1777 struct e1000_adapter *adapter = netdev_priv(netdev);
1778 struct e1000_hw *hw = &adapter->hw;
1779 u32 icr = er32(ICR);
1780
1781 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1784 return IRQ_NONE;
1785 }
1786
1787 if (icr & adapter->eiac_mask)
1788 ew32(ICS, (icr & adapter->eiac_mask));
1789
1790 if (icr & E1000_ICR_OTHER) {
1791 if (!(icr & E1000_ICR_LSC))
1792 goto no_link_interrupt;
f92518dd 1793 hw->mac.get_link_status = true;
4662e82b
BA		 1794 /* guard against interrupt when we're going down */
1795 if (!test_bit(__E1000_DOWN, &adapter->state))
1796 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1797 }
1798
1799no_link_interrupt:
a3c69fef
JB		 1800 if (!test_bit(__E1000_DOWN, &adapter->state))
1801 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1802
1803 return IRQ_HANDLED;
1804}
1805
1806
1807static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1808{
1809 struct net_device *netdev = data;
1810 struct e1000_adapter *adapter = netdev_priv(netdev);
1811 struct e1000_hw *hw = &adapter->hw;
1812 struct e1000_ring *tx_ring = adapter->tx_ring;
1813
1814
1815 adapter->total_tx_bytes = 0;
1816 adapter->total_tx_packets = 0;
1817
55aa6985 1818 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1819 /* Ring was not completely cleaned, so fire another interrupt */
1820 ew32(ICS, tx_ring->ims_val);
1821
1822 return IRQ_HANDLED;
1823}
1824
1825static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1826{
1827 struct net_device *netdev = data;
1828 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1829 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1830
1831 /* Write the ITR value calculated at the end of the
1832 * previous interrupt.
1833 */
55aa6985
BA		 1834 if (rx_ring->set_itr) {
1835 writel(1000000000 / (rx_ring->itr_val * 256),
1836 rx_ring->itr_register);
1837 rx_ring->set_itr = 0;
4662e82b
BA		 1838 }
1839
288379f0 1840 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1841 adapter->total_rx_bytes = 0;
1842 adapter->total_rx_packets = 0;
288379f0 1843 __napi_schedule(&adapter->napi);
4662e82b
BA		 1844 }
1845 return IRQ_HANDLED;
1846}
1847
1848/**
1849 * e1000_configure_msix - Configure MSI-X hardware
1850 *
1851 * e1000_configure_msix sets up the hardware to properly
1852 * generate MSI-X interrupts.
1853 **/
1854static void e1000_configure_msix(struct e1000_adapter *adapter)
1855{
1856 struct e1000_hw *hw = &adapter->hw;
1857 struct e1000_ring *rx_ring = adapter->rx_ring;
1858 struct e1000_ring *tx_ring = adapter->tx_ring;
1859 int vector = 0;
1860 u32 ctrl_ext, ivar = 0;
1861
1862 adapter->eiac_mask = 0;
1863
1864 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1865 if (hw->mac.type == e1000_82574) {
1866 u32 rfctl = er32(RFCTL);
1867 rfctl |= E1000_RFCTL_ACK_DIS;
1868 ew32(RFCTL, rfctl);
1869 }
1870
1871#define E1000_IVAR_INT_ALLOC_VALID 0x8
1872 /* Configure Rx vector */
1873 rx_ring->ims_val = E1000_IMS_RXQ0;
1874 adapter->eiac_mask |= rx_ring->ims_val;
1875 if (rx_ring->itr_val)
1876 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1877 rx_ring->itr_register);
4662e82b 1878 else
c5083cf6 1879 writel(1, rx_ring->itr_register);
4662e82b
BA		 1880 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1881
1882 /* Configure Tx vector */
1883 tx_ring->ims_val = E1000_IMS_TXQ0;
1884 vector++;
1885 if (tx_ring->itr_val)
1886 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1887 tx_ring->itr_register);
4662e82b 1888 else
c5083cf6 1889 writel(1, tx_ring->itr_register);
4662e82b
BA		 1890 adapter->eiac_mask |= tx_ring->ims_val;
1891 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1892
1893 /* set vector for Other Causes, e.g. link changes */
1894 vector++;
1895 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1896 if (rx_ring->itr_val)
1897 writel(1000000000 / (rx_ring->itr_val * 256),
1898 hw->hw_addr + E1000_EITR_82574(vector));
1899 else
1900 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1901
1902 /* Cause Tx interrupts on every write back */
1903 ivar |= (1 << 31);
1904
1905 ew32(IVAR, ivar);
1906
1907 /* enable MSI-X PBA support */
1908 ctrl_ext = er32(CTRL_EXT);
1909 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1910
1911 /* Auto-Mask Other interrupts upon ICR read */
1912#define E1000_EIAC_MASK_82574 0x01F00000
1913 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1914 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1915 ew32(CTRL_EXT, ctrl_ext);
1916 e1e_flush();
1917}
1918
1919void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1920{
1921 if (adapter->msix_entries) {
1922 pci_disable_msix(adapter->pdev);
1923 kfree(adapter->msix_entries);
1924 adapter->msix_entries = NULL;
1925 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1926 pci_disable_msi(adapter->pdev);
1927 adapter->flags &= ~FLAG_MSI_ENABLED;
1928 }
4662e82b
BA		 1929}
1930
1931/**
1932 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1933 *
1934 * Attempt to configure interrupts using the best available
1935 * capabilities of the hardware and kernel.
1936 **/
1937void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1938{
1939 int err;
8e86acd7 1940 int i;
4662e82b
BA		 1941
1942 switch (adapter->int_mode) {
1943 case E1000E_INT_MODE_MSIX:
1944 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1945 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1946 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1947 sizeof(struct msix_entry),
1948 GFP_KERNEL);
1949 if (adapter->msix_entries) {
8e86acd7 1950 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1951 adapter->msix_entries[i].entry = i;
1952
1953 err = pci_enable_msix(adapter->pdev,
1954 adapter->msix_entries,
8e86acd7 1955 adapter->num_vectors);
b1cdfead 1956 if (err == 0)
4662e82b
BA		 1957 return;
1958 }
1959 /* MSI-X failed, so fall through and try MSI */
ef456f85 1960 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1961 e1000e_reset_interrupt_capability(adapter);
1962 }
1963 adapter->int_mode = E1000E_INT_MODE_MSI;
1964 /* Fall through */
1965 case E1000E_INT_MODE_MSI:
1966 if (!pci_enable_msi(adapter->pdev)) {
1967 adapter->flags |= FLAG_MSI_ENABLED;
1968 } else {
1969 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1970 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1971 }
1972 /* Fall through */
1973 case E1000E_INT_MODE_LEGACY:
1974 /* Don't do anything; this is the system default */
1975 break;
1976 }
8e86acd7
JK		 1977
1978 /* store the number of vectors being used */
1979 adapter->num_vectors = 1;
4662e82b
BA		 1980}
1981
1982/**
1983 * e1000_request_msix - Initialize MSI-X interrupts
1984 *
1985 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1986 * kernel.
1987 **/
1988static int e1000_request_msix(struct e1000_adapter *adapter)
1989{
1990 struct net_device *netdev = adapter->netdev;
1991 int err = 0, vector = 0;
1992
1993 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1994 snprintf(adapter->rx_ring->name,
1995 sizeof(adapter->rx_ring->name) - 1,
1996 "%s-rx-0", netdev->name);
4662e82b
BA		 1997 else
1998 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1999 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2000 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2001 netdev);
2002 if (err)
5015e53a 2003 return err;
c5083cf6
BA		 2004 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2005 E1000_EITR_82574(vector);
4662e82b
BA		 2006 adapter->rx_ring->itr_val = adapter->itr;
2007 vector++;
2008
2009 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2010 snprintf(adapter->tx_ring->name,
2011 sizeof(adapter->tx_ring->name) - 1,
2012 "%s-tx-0", netdev->name);
4662e82b
BA		 2013 else
2014 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2015 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2016 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2017 netdev);
2018 if (err)
5015e53a 2019 return err;
c5083cf6
BA		 2020 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2021 E1000_EITR_82574(vector);
4662e82b
BA		 2022 adapter->tx_ring->itr_val = adapter->itr;
2023 vector++;
2024
2025 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2026 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2027 if (err)
5015e53a 2028 return err;
4662e82b
BA		 2029
2030 e1000_configure_msix(adapter);
5015e53a 2031
4662e82b 2032 return 0;
4662e82b
BA		 2033}
2034
f8d59f78
BA		 2035/**
2036 * e1000_request_irq - initialize interrupts
2037 *
2038 * Attempts to configure interrupts using the best available
2039 * capabilities of the hardware and kernel.
2040 **/
bc7f75fa
AK		 2041static int e1000_request_irq(struct e1000_adapter *adapter)
2042{
2043 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2044 int err;
2045
4662e82b
BA		 2046 if (adapter->msix_entries) {
2047 err = e1000_request_msix(adapter);
2048 if (!err)
2049 return err;
2050 /* fall back to MSI */
2051 e1000e_reset_interrupt_capability(adapter);
2052 adapter->int_mode = E1000E_INT_MODE_MSI;
2053 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2054 }
4662e82b 2055 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2056 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2057 netdev->name, netdev);
2058 if (!err)
2059 return err;
bc7f75fa 2060
4662e82b
BA		 2061 /* fall back to legacy interrupt */
2062 e1000e_reset_interrupt_capability(adapter);
2063 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2064 }
2065
a0607fd3 2066 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2067 netdev->name, netdev);
2068 if (err)
2069 e_err("Unable to allocate interrupt, Error: %d\n", err);
2070
bc7f75fa
AK		 2071 return err;
2072}
2073
2074static void e1000_free_irq(struct e1000_adapter *adapter)
2075{
2076 struct net_device *netdev = adapter->netdev;
2077
4662e82b
BA		 2078 if (adapter->msix_entries) {
2079 int vector = 0;
2080
2081 free_irq(adapter->msix_entries[vector].vector, netdev);
2082 vector++;
2083
2084 free_irq(adapter->msix_entries[vector].vector, netdev);
2085 vector++;
2086
2087 /* Other Causes interrupt vector */
2088 free_irq(adapter->msix_entries[vector].vector, netdev);
2089 return;
bc7f75fa 2090 }
4662e82b
BA		 2091
2092 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2093}
2094
2095/**
2096 * e1000_irq_disable - Mask off interrupt generation on the NIC
2097 **/
2098static void e1000_irq_disable(struct e1000_adapter *adapter)
2099{
2100 struct e1000_hw *hw = &adapter->hw;
2101
bc7f75fa 2102 ew32(IMC, ~0);
4662e82b
BA		 2103 if (adapter->msix_entries)
2104 ew32(EIAC_82574, 0);
bc7f75fa 2105 e1e_flush();
8e86acd7
JK		 2106
2107 if (adapter->msix_entries) {
2108 int i;
2109 for (i = 0; i < adapter->num_vectors; i++)
2110 synchronize_irq(adapter->msix_entries[i].vector);
2111 } else {
2112 synchronize_irq(adapter->pdev->irq);
2113 }
bc7f75fa
AK		 2114}
2115
2116/**
2117 * e1000_irq_enable - Enable default interrupt generation settings
2118 **/
2119static void e1000_irq_enable(struct e1000_adapter *adapter)
2120{
2121 struct e1000_hw *hw = &adapter->hw;
2122
4662e82b
BA		 2123 if (adapter->msix_entries) {
2124 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2125 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2126 } else {
2127 ew32(IMS, IMS_ENABLE_MASK);
2128 }
74ef9c39 2129 e1e_flush();
bc7f75fa
AK		 2130}
2131
2132/**
31dbe5b4 2133 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2134 * @adapter: address of board private structure
2135 *
31dbe5b4 2136 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2137 * For ASF and Pass Through versions of f/w this means that
2138 * the driver is loaded. For AMT version (only with 82573)
2139 * of the f/w this means that the network i/f is open.
2140 **/
31dbe5b4 2141void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2142{
2143 struct e1000_hw *hw = &adapter->hw;
2144 u32 ctrl_ext;
2145 u32 swsm;
2146
2147 /* Let firmware know the driver has taken over */
2148 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2149 swsm = er32(SWSM);
2150 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2151 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2152 ctrl_ext = er32(CTRL_EXT);
ad68076e 2153 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2154 }
2155}
2156
2157/**
31dbe5b4 2158 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2159 * @adapter: address of board private structure
2160 *
31dbe5b4 2161 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2162 * For ASF and Pass Through versions of f/w this means that the
2163 * driver is no longer loaded. For AMT version (only with 82573) i
2164 * of the f/w this means that the network i/f is closed.
2165 *
2166 **/
31dbe5b4 2167void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2168{
2169 struct e1000_hw *hw = &adapter->hw;
2170 u32 ctrl_ext;
2171 u32 swsm;
2172
2173 /* Let firmware taken over control of h/w */
2174 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2175 swsm = er32(SWSM);
2176 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2177 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2178 ctrl_ext = er32(CTRL_EXT);
ad68076e 2179 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2180 }
2181}
2182
bc7f75fa
AK		 2183/**
2184 * @e1000_alloc_ring - allocate memory for a ring structure
2185 **/
2186static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2187 struct e1000_ring *ring)
2188{
2189 struct pci_dev *pdev = adapter->pdev;
2190
2191 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2192 GFP_KERNEL);
2193 if (!ring->desc)
2194 return -ENOMEM;
2195
2196 return 0;
2197}
2198
2199/**
2200 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2201 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2202 *
2203 * Return 0 on success, negative on failure
2204 **/
55aa6985 2205int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2206{
55aa6985 2207 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2208 int err = -ENOMEM, size;
2209
2210 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2211 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2212 if (!tx_ring->buffer_info)
2213 goto err;
bc7f75fa
AK		 2214
2215 /* round up to nearest 4K */
2216 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2217 tx_ring->size = ALIGN(tx_ring->size, 4096);
2218
2219 err = e1000_alloc_ring_dma(adapter, tx_ring);
2220 if (err)
2221 goto err;
2222
2223 tx_ring->next_to_use = 0;
2224 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2225
2226 return 0;
2227err:
2228 vfree(tx_ring->buffer_info);
44defeb3 2229 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2230 return err;
2231}
2232
2233/**
2234 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2235 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2236 *
2237 * Returns 0 on success, negative on failure
2238 **/
55aa6985 2239int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2240{
55aa6985 2241 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2242 struct e1000_buffer *buffer_info;
2243 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2244
2245 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2246 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2247 if (!rx_ring->buffer_info)
2248 goto err;
bc7f75fa 2249
47f44e40
AK		 2250 for (i = 0; i < rx_ring->count; i++) {
2251 buffer_info = &rx_ring->buffer_info[i];
2252 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2253 sizeof(struct e1000_ps_page),
2254 GFP_KERNEL);
2255 if (!buffer_info->ps_pages)
2256 goto err_pages;
2257 }
bc7f75fa
AK		 2258
2259 desc_len = sizeof(union e1000_rx_desc_packet_split);
2260
2261 /* Round up to nearest 4K */
2262 rx_ring->size = rx_ring->count * desc_len;
2263 rx_ring->size = ALIGN(rx_ring->size, 4096);
2264
2265 err = e1000_alloc_ring_dma(adapter, rx_ring);
2266 if (err)
47f44e40 2267 goto err_pages;
bc7f75fa
AK		 2268
2269 rx_ring->next_to_clean = 0;
2270 rx_ring->next_to_use = 0;
2271 rx_ring->rx_skb_top = NULL;
2272
2273 return 0;
47f44e40
AK		 2274
2275err_pages:
2276 for (i = 0; i < rx_ring->count; i++) {
2277 buffer_info = &rx_ring->buffer_info[i];
2278 kfree(buffer_info->ps_pages);
2279 }
bc7f75fa
AK		 2280err:
2281 vfree(rx_ring->buffer_info);
e9262447 2282 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2283 return err;
2284}
2285
2286/**
2287 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2288 * @tx_ring: Tx descriptor ring
bc7f75fa 2289 **/
55aa6985 2290static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2291{
55aa6985 2292 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2293 struct e1000_buffer *buffer_info;
2294 unsigned long size;
2295 unsigned int i;
2296
2297 for (i = 0; i < tx_ring->count; i++) {
2298 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2299 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2300 }
2301
3f0cfa3b 2302 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2303 size = sizeof(struct e1000_buffer) * tx_ring->count;
2304 memset(tx_ring->buffer_info, 0, size);
2305
2306 memset(tx_ring->desc, 0, tx_ring->size);
2307
2308 tx_ring->next_to_use = 0;
2309 tx_ring->next_to_clean = 0;
2310
c5083cf6
BA		 2311 writel(0, tx_ring->head);
2312 writel(0, tx_ring->tail);
bc7f75fa
AK		 2313}
2314
2315/**
2316 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2317 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2318 *
2319 * Free all transmit software resources
2320 **/
55aa6985 2321void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2322{
55aa6985 2323 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2324 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2325
55aa6985 2326 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2327
2328 vfree(tx_ring->buffer_info);
2329 tx_ring->buffer_info = NULL;
2330
2331 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2332 tx_ring->dma);
2333 tx_ring->desc = NULL;
2334}
2335
2336/**
2337 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2338 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2339 *
2340 * Free all receive software resources
2341 **/
55aa6985 2342void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2343{
55aa6985 2344 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2345 struct pci_dev *pdev = adapter->pdev;
47f44e40 2346 int i;
bc7f75fa 2347
55aa6985 2348 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2349
b1cdfead 2350 for (i = 0; i < rx_ring->count; i++)
47f44e40 2351 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2352
bc7f75fa
AK		 2353 vfree(rx_ring->buffer_info);
2354 rx_ring->buffer_info = NULL;
2355
bc7f75fa
AK		 2356 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2357 rx_ring->dma);
2358 rx_ring->desc = NULL;
2359}
2360
2361/**
2362 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2363 * @adapter: pointer to adapter
2364 * @itr_setting: current adapter->itr
2365 * @packets: the number of packets during this measurement interval
2366 * @bytes: the number of bytes during this measurement interval
2367 *
bc7f75fa
AK		 2368 * Stores a new ITR value based on packets and byte
2369 * counts during the last interrupt. The advantage of per interrupt
2370 * computation is faster updates and more accurate ITR for the current
2371 * traffic pattern. Constants in this function were computed
2372 * based on theoretical maximum wire speed and thresholds were set based
2373 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2374 * while increasing bulk throughput. This functionality is controlled
2375 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2376 **/
2377static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2378 u16 itr_setting, int packets,
2379 int bytes)
2380{
2381 unsigned int retval = itr_setting;
2382
2383 if (packets == 0)
5015e53a 2384 return itr_setting;
bc7f75fa
AK		 2385
2386 switch (itr_setting) {
2387 case lowest_latency:
2388 /* handle TSO and jumbo frames */
2389 if (bytes/packets > 8000)
2390 retval = bulk_latency;
b1cdfead 2391 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2392 retval = low_latency;
bc7f75fa
AK		 2393 break;
2394 case low_latency: /* 50 usec aka 20000 ints/s */
2395 if (bytes > 10000) {
2396 /* this if handles the TSO accounting */
b1cdfead 2397 if (bytes/packets > 8000)
bc7f75fa 2398 retval = bulk_latency;
b1cdfead 2399 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2400 retval = bulk_latency;
b1cdfead 2401 else if ((packets > 35))
bc7f75fa 2402 retval = lowest_latency;
bc7f75fa
AK		 2403 } else if (bytes/packets > 2000) {
2404 retval = bulk_latency;
2405 } else if (packets <= 2 && bytes < 512) {
2406 retval = lowest_latency;
2407 }
2408 break;
2409 case bulk_latency: /* 250 usec aka 4000 ints/s */
2410 if (bytes > 25000) {
b1cdfead 2411 if (packets > 35)
bc7f75fa 2412 retval = low_latency;
bc7f75fa
AK		 2413 } else if (bytes < 6000) {
2414 retval = low_latency;
2415 }
2416 break;
2417 }
2418
bc7f75fa
AK		 2419 return retval;
2420}
2421
2422static void e1000_set_itr(struct e1000_adapter *adapter)
2423{
2424 struct e1000_hw *hw = &adapter->hw;
2425 u16 current_itr;
2426 u32 new_itr = adapter->itr;
2427
2428 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2429 if (adapter->link_speed != SPEED_1000) {
2430 current_itr = 0;
2431 new_itr = 4000;
2432 goto set_itr_now;
2433 }
2434
828bac87
BA		 2435 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2436 new_itr = 0;
2437 goto set_itr_now;
2438 }
2439
bc7f75fa
AK		 2440 adapter->tx_itr = e1000_update_itr(adapter,
2441 adapter->tx_itr,
2442 adapter->total_tx_packets,
2443 adapter->total_tx_bytes);
2444 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2445 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2446 adapter->tx_itr = low_latency;
2447
2448 adapter->rx_itr = e1000_update_itr(adapter,
2449 adapter->rx_itr,
2450 adapter->total_rx_packets,
2451 adapter->total_rx_bytes);
2452 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2453 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2454 adapter->rx_itr = low_latency;
2455
2456 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2457
2458 switch (current_itr) {
2459 /* counts and packets in update_itr are dependent on these numbers */
2460 case lowest_latency:
2461 new_itr = 70000;
2462 break;
2463 case low_latency:
2464 new_itr = 20000; /* aka hwitr = ~200 */
2465 break;
2466 case bulk_latency:
2467 new_itr = 4000;
2468 break;
2469 default:
2470 break;
2471 }
2472
2473set_itr_now:
2474 if (new_itr != adapter->itr) {
ad68076e
BA		 2475 /*
2476 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2477 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2478 * increasing
2479 */
bc7f75fa
AK		 2480 new_itr = new_itr > adapter->itr ?
2481 min(adapter->itr + (new_itr >> 2), new_itr) :
2482 new_itr;
2483 adapter->itr = new_itr;
4662e82b
BA		 2484 adapter->rx_ring->itr_val = new_itr;
2485 if (adapter->msix_entries)
2486 adapter->rx_ring->set_itr = 1;
2487 else
828bac87
BA		 2488 if (new_itr)
2489 ew32(ITR, 1000000000 / (new_itr * 256));
2490 else
2491 ew32(ITR, 0);
bc7f75fa
AK		 2492 }
2493}
2494
4662e82b
BA		 2495/**
2496 * e1000_alloc_queues - Allocate memory for all rings
2497 * @adapter: board private structure to initialize
2498 **/
2499static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2500{
55aa6985
BA		 2501 int size = sizeof(struct e1000_ring);
2502
2503 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2504 if (!adapter->tx_ring)
2505 goto err;
55aa6985
BA		 2506 adapter->tx_ring->count = adapter->tx_ring_count;
2507 adapter->tx_ring->adapter = adapter;
4662e82b 2508
55aa6985 2509 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2510 if (!adapter->rx_ring)
2511 goto err;
55aa6985
BA		 2512 adapter->rx_ring->count = adapter->rx_ring_count;
2513 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2514
2515 return 0;
2516err:
2517 e_err("Unable to allocate memory for queues\n");
2518 kfree(adapter->rx_ring);
2519 kfree(adapter->tx_ring);
2520 return -ENOMEM;
2521}
2522
bc7f75fa
AK		 2523/**
2524 * e1000_clean - NAPI Rx polling callback
ad68076e 2525 * @napi: struct associated with this polling callback
489815ce 2526 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2527 **/
2528static int e1000_clean(struct napi_struct *napi, int budget)
2529{
2530 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2531 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2532 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2533 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2534
4cf1653a 2535 adapter = netdev_priv(poll_dev);
bc7f75fa 2536
4662e82b
BA		 2537 if (adapter->msix_entries &&
2538 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2539 goto clean_rx;
2540
55aa6985 2541 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
bc7f75fa 2542
4662e82b 2543clean_rx:
55aa6985 2544 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2545
12d04a3c 2546 if (!tx_cleaned)
d2c7ddd6 2547 work_done = budget;
bc7f75fa 2548
53e52c72
DM		 2549 /* If budget not fully consumed, exit the polling mode */
2550 if (work_done < budget) {
bc7f75fa
AK		 2551 if (adapter->itr_setting & 3)
2552 e1000_set_itr(adapter);
288379f0 2553 napi_complete(napi);
a3c69fef
JB		 2554 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2555 if (adapter->msix_entries)
2556 ew32(IMS, adapter->rx_ring->ims_val);
2557 else
2558 e1000_irq_enable(adapter);
2559 }
bc7f75fa
AK		 2560 }
2561
2562 return work_done;
2563}
2564
8e586137 2565static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2566{
2567 struct e1000_adapter *adapter = netdev_priv(netdev);
2568 struct e1000_hw *hw = &adapter->hw;
2569 u32 vfta, index;
2570
2571 /* don't update vlan cookie if already programmed */
2572 if ((adapter->hw.mng_cookie.status &
2573 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2574 (vid == adapter->mng_vlan_id))
8e586137 2575 return 0;
caaddaf8 2576
bc7f75fa 2577 /* add VID to filter table */
caaddaf8
BA		 2578 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2579 index = (vid >> 5) & 0x7F;
2580 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2581 vfta |= (1 << (vid & 0x1F));
2582 hw->mac.ops.write_vfta(hw, index, vfta);
2583 }
86d70e53
JK		 2584
2585 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2586
2587 return 0;
bc7f75fa
AK		 2588}
2589
8e586137 2590static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2591{
2592 struct e1000_adapter *adapter = netdev_priv(netdev);
2593 struct e1000_hw *hw = &adapter->hw;
2594 u32 vfta, index;
2595
bc7f75fa
AK		 2596 if ((adapter->hw.mng_cookie.status &
2597 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2598 (vid == adapter->mng_vlan_id)) {
2599 /* release control to f/w */
31dbe5b4 2600 e1000e_release_hw_control(adapter);
8e586137 2601 return 0;
bc7f75fa
AK		 2602 }
2603
2604 /* remove VID from filter table */
caaddaf8
BA		 2605 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2606 index = (vid >> 5) & 0x7F;
2607 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2608 vfta &= ~(1 << (vid & 0x1F));
2609 hw->mac.ops.write_vfta(hw, index, vfta);
2610 }
86d70e53
JK		 2611
2612 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2613
2614 return 0;
bc7f75fa
AK		 2615}
2616
86d70e53
JK		 2617/**
2618 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2619 * @adapter: board private structure to initialize
2620 **/
2621static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2622{
2623 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2624 struct e1000_hw *hw = &adapter->hw;
2625 u32 rctl;
bc7f75fa 2626
86d70e53
JK		 2627 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2628 /* disable VLAN receive filtering */
2629 rctl = er32(RCTL);
2630 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2631 ew32(RCTL, rctl);
2632
2633 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2634 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2635 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2636 }
bc7f75fa
AK		 2637 }
2638}
2639
86d70e53
JK		 2640/**
2641 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2642 * @adapter: board private structure to initialize
2643 **/
2644static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2645{
2646 struct e1000_hw *hw = &adapter->hw;
2647 u32 rctl;
2648
2649 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2650 /* enable VLAN receive filtering */
2651 rctl = er32(RCTL);
2652 rctl |= E1000_RCTL_VFE;
2653 rctl &= ~E1000_RCTL_CFIEN;
2654 ew32(RCTL, rctl);
2655 }
2656}
bc7f75fa 2657
86d70e53
JK		 2658/**
2659 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2660 * @adapter: board private structure to initialize
2661 **/
2662static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2663{
bc7f75fa 2664 struct e1000_hw *hw = &adapter->hw;
86d70e53 2665 u32 ctrl;
bc7f75fa 2666
86d70e53
JK		 2667 /* disable VLAN tag insert/strip */
2668 ctrl = er32(CTRL);
2669 ctrl &= ~E1000_CTRL_VME;
2670 ew32(CTRL, ctrl);
2671}
bc7f75fa 2672
86d70e53
JK		 2673/**
2674 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2675 * @adapter: board private structure to initialize
2676 **/
2677static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2678{
2679 struct e1000_hw *hw = &adapter->hw;
2680 u32 ctrl;
bc7f75fa 2681
86d70e53
JK		 2682 /* enable VLAN tag insert/strip */
2683 ctrl = er32(CTRL);
2684 ctrl |= E1000_CTRL_VME;
2685 ew32(CTRL, ctrl);
2686}
bc7f75fa 2687
86d70e53
JK		 2688static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2689{
2690 struct net_device *netdev = adapter->netdev;
2691 u16 vid = adapter->hw.mng_cookie.vlan_id;
2692 u16 old_vid = adapter->mng_vlan_id;
2693
2694 if (adapter->hw.mng_cookie.status &
2695 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2696 e1000_vlan_rx_add_vid(netdev, vid);
2697 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2698 }
2699
86d70e53
JK		 2700 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2701 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2702}
2703
2704static void e1000_restore_vlan(struct e1000_adapter *adapter)
2705{
2706 u16 vid;
2707
86d70e53 2708 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2709
86d70e53 2710 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2711 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2712}
2713
cd791618 2714static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2715{
2716 struct e1000_hw *hw = &adapter->hw;
cd791618 2717 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2718
2719 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2720 return;
2721
2722 manc = er32(MANC);
2723
ad68076e
BA		 2724 /*
2725 * enable receiving management packets to the host. this will probably
bc7f75fa 2726 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2727 * the packets will be handled on SMBUS
2728 */
bc7f75fa
AK		 2729 manc |= E1000_MANC_EN_MNG2HOST;
2730 manc2h = er32(MANC2H);
cd791618
BA		 2731
2732 switch (hw->mac.type) {
2733 default:
2734 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2735 break;
2736 case e1000_82574:
2737 case e1000_82583:
2738 /*
2739 * Check if IPMI pass-through decision filter already exists;
2740 * if so, enable it.
2741 */
2742 for (i = 0, j = 0; i < 8; i++) {
2743 mdef = er32(MDEF(i));
2744
2745 /* Ignore filters with anything other than IPMI ports */
3b21b508 2746 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2747 continue;
2748
2749 /* Enable this decision filter in MANC2H */
2750 if (mdef)
2751 manc2h |= (1 << i);
2752
2753 j |= mdef;
2754 }
2755
2756 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2757 break;
2758
2759 /* Create new decision filter in an empty filter */
2760 for (i = 0, j = 0; i < 8; i++)
2761 if (er32(MDEF(i)) == 0) {
2762 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2763 E1000_MDEF_PORT_664));
2764 manc2h |= (1 << 1);
2765 j++;
2766 break;
2767 }
2768
2769 if (!j)
2770 e_warn("Unable to create IPMI pass-through filter\n");
2771 break;
2772 }
2773
bc7f75fa
AK		 2774 ew32(MANC2H, manc2h);
2775 ew32(MANC, manc);
2776}
2777
2778/**
af667a29 2779 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2780 * @adapter: board private structure
2781 *
2782 * Configure the Tx unit of the MAC after a reset.
2783 **/
2784static void e1000_configure_tx(struct e1000_adapter *adapter)
2785{
2786 struct e1000_hw *hw = &adapter->hw;
2787 struct e1000_ring *tx_ring = adapter->tx_ring;
2788 u64 tdba;
c550b121 2789 u32 tdlen, tarc;
bc7f75fa
AK		 2790
2791 /* Setup the HW Tx Head and Tail descriptor pointers */
2792 tdba = tx_ring->dma;
2793 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2794 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2795 ew32(TDBAH, (tdba >> 32));
2796 ew32(TDLEN, tdlen);
2797 ew32(TDH, 0);
2798 ew32(TDT, 0);
c5083cf6
BA		 2799 tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
2800 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
bc7f75fa 2801
bc7f75fa
AK		 2802 /* Set the Tx Interrupt Delay register */
2803 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2804 /* Tx irq moderation */
bc7f75fa
AK		 2805 ew32(TADV, adapter->tx_abs_int_delay);
2806
3a3b7586
JB		 2807 if (adapter->flags2 & FLAG2_DMA_BURST) {
2808 u32 txdctl = er32(TXDCTL(0));
2809 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2810 E1000_TXDCTL_WTHRESH);
2811 /*
2812 * set up some performance related parameters to encourage the
2813 * hardware to use the bus more efficiently in bursts, depends
2814 * on the tx_int_delay to be enabled,
2815 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2816 * hthresh = 1 ==> prefetch when one or more available
2817 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2818 * BEWARE: this seems to work but should be considered first if
af667a29 2819 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2820 */
2821 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2822 ew32(TXDCTL(0), txdctl);
3a3b7586 2823 }
56032be7
BA		 2824 /* erratum work around: set txdctl the same for both queues */
2825 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2826
bc7f75fa 2827 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2828 tarc = er32(TARC(0));
ad68076e
BA		 2829 /*
2830 * set the speed mode bit, we'll clear it if we're not at
2831 * gigabit link later
2832 */
bc7f75fa
AK		 2833#define SPEED_MODE_BIT (1 << 21)
2834 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2835 ew32(TARC(0), tarc);
bc7f75fa
AK		 2836 }
2837
2838 /* errata: program both queues to unweighted RR */
2839 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2840 tarc = er32(TARC(0));
bc7f75fa 2841 tarc |= 1;
e9ec2c0f
JK		 2842 ew32(TARC(0), tarc);
2843 tarc = er32(TARC(1));
bc7f75fa 2844 tarc |= 1;
e9ec2c0f 2845 ew32(TARC(1), tarc);
bc7f75fa
AK		 2846 }
2847
bc7f75fa
AK		 2848 /* Setup Transmit Descriptor Settings for eop descriptor */
2849 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2850
2851 /* only set IDE if we are delaying interrupts using the timers */
2852 if (adapter->tx_int_delay)
2853 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2854
2855 /* enable Report Status bit */
2856 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2857
57cde763 2858 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2859}
2860
2861/**
2862 * e1000_setup_rctl - configure the receive control registers
2863 * @adapter: Board private structure
2864 **/
2865#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2866 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2867static void e1000_setup_rctl(struct e1000_adapter *adapter)
2868{
2869 struct e1000_hw *hw = &adapter->hw;
2870 u32 rctl, rfctl;
bc7f75fa
AK		 2871 u32 pages = 0;
2872
a1ce6473
BA		 2873 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2874 if (hw->mac.type == e1000_pch2lan) {
2875 s32 ret_val;
2876
2877 if (adapter->netdev->mtu > ETH_DATA_LEN)
2878 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2879 else
2880 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2881
2882 if (ret_val)
2883 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2884 }
2885
bc7f75fa
AK		 2886 /* Program MC offset vector base */
2887 rctl = er32(RCTL);
2888 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2889 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2890 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2891 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2892
2893 /* Do not Store bad packets */
2894 rctl &= ~E1000_RCTL_SBP;
2895
2896 /* Enable Long Packet receive */
2897 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2898 rctl &= ~E1000_RCTL_LPE;
2899 else
2900 rctl |= E1000_RCTL_LPE;
2901
eb7c3adb
JK		 2902 /* Some systems expect that the CRC is included in SMBUS traffic. The
2903 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2904 * host memory when this is enabled
2905 */
2906 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2907 rctl |= E1000_RCTL_SECRC;
5918bd88 2908
a4f58f54
BA		 2909 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2910 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2911 u16 phy_data;
2912
2913 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2914 phy_data &= 0xfff8;
2915 phy_data |= (1 << 2);
2916 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2917
2918 e1e_rphy(hw, 22, &phy_data);
2919 phy_data &= 0x0fff;
2920 phy_data |= (1 << 14);
2921 e1e_wphy(hw, 0x10, 0x2823);
2922 e1e_wphy(hw, 0x11, 0x0003);
2923 e1e_wphy(hw, 22, phy_data);
2924 }
2925
bc7f75fa
AK		 2926 /* Setup buffer sizes */
2927 rctl &= ~E1000_RCTL_SZ_4096;
2928 rctl |= E1000_RCTL_BSEX;
2929 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2930 case 2048:
2931 default:
2932 rctl |= E1000_RCTL_SZ_2048;
2933 rctl &= ~E1000_RCTL_BSEX;
2934 break;
2935 case 4096:
2936 rctl |= E1000_RCTL_SZ_4096;
2937 break;
2938 case 8192:
2939 rctl |= E1000_RCTL_SZ_8192;
2940 break;
2941 case 16384:
2942 rctl |= E1000_RCTL_SZ_16384;
2943 break;
2944 }
2945
5f450212
BA		 2946 /* Enable Extended Status in all Receive Descriptors */
2947 rfctl = er32(RFCTL);
2948 rfctl |= E1000_RFCTL_EXTEN;
2949
bc7f75fa
AK		 2950 /*
2951 * 82571 and greater support packet-split where the protocol
2952 * header is placed in skb->data and the packet data is
2953 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2954 * In the case of a non-split, skb->data is linearly filled,
2955 * followed by the page buffers. Therefore, skb->data is
2956 * sized to hold the largest protocol header.
2957 *
2958 * allocations using alloc_page take too long for regular MTU
2959 * so only enable packet split for jumbo frames
2960 *
2961 * Using pages when the page size is greater than 16k wastes
2962 * a lot of memory, since we allocate 3 pages at all times
2963 * per packet.
2964 */
bc7f75fa 2965 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2966 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2967 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2968 else
2969 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2970
2971 if (adapter->rx_ps_pages) {
90da0669
BA		 2972 u32 psrctl = 0;
2973
ad68076e
BA		 2974 /*
2975 * disable packet split support for IPv6 extension headers,
2976 * because some malformed IPv6 headers can hang the Rx
2977 */
bc7f75fa
AK		 2978 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2979 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2980
140a7480
AK		 2981 /* Enable Packet split descriptors */
2982 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2983
2984 psrctl |= adapter->rx_ps_bsize0 >>
2985 E1000_PSRCTL_BSIZE0_SHIFT;
2986
2987 switch (adapter->rx_ps_pages) {
2988 case 3:
2989 psrctl |= PAGE_SIZE <<
2990 E1000_PSRCTL_BSIZE3_SHIFT;
2991 case 2:
2992 psrctl |= PAGE_SIZE <<
2993 E1000_PSRCTL_BSIZE2_SHIFT;
2994 case 1:
2995 psrctl |= PAGE_SIZE >>
2996 E1000_PSRCTL_BSIZE1_SHIFT;
2997 break;
2998 }
2999
3000 ew32(PSRCTL, psrctl);
3001 }
3002
cf955e6c
BG		 3003 /* This is useful for sniffing bad packets. */
3004 if (adapter->netdev->features & NETIF_F_RXALL) {
3005 /* UPE and MPE will be handled by normal PROMISC logic
3006 * in e1000e_set_rx_mode */
3007 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3008 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3009 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3010
3011 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3012 E1000_RCTL_DPF | /* Allow filtered pause */
3013 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3014 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3015 * and that breaks VLANs.
3016 */
3017 }
3018
5f450212 3019 ew32(RFCTL, rfctl);
bc7f75fa 3020 ew32(RCTL, rctl);
318a94d6
JK		 3021 /* just started the receive unit, no need to restart */
3022 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3023}
3024
3025/**
3026 * e1000_configure_rx - Configure Receive Unit after Reset
3027 * @adapter: board private structure
3028 *
3029 * Configure the Rx unit of the MAC after a reset.
3030 **/
3031static void e1000_configure_rx(struct e1000_adapter *adapter)
3032{
3033 struct e1000_hw *hw = &adapter->hw;
3034 struct e1000_ring *rx_ring = adapter->rx_ring;
3035 u64 rdba;
3036 u32 rdlen, rctl, rxcsum, ctrl_ext;
3037
3038 if (adapter->rx_ps_pages) {
3039 /* this is a 32 byte descriptor */
3040 rdlen = rx_ring->count *
af667a29 3041 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3042 adapter->clean_rx = e1000_clean_rx_irq_ps;
3043 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3044 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3045 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3046 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3047 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3048 } else {
5f450212 3049 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3050 adapter->clean_rx = e1000_clean_rx_irq;
3051 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3052 }
3053
3054 /* disable receives while setting up the descriptors */
3055 rctl = er32(RCTL);
7f99ae63
BA		 3056 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3057 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3058 e1e_flush();
1bba4386 3059 usleep_range(10000, 20000);
bc7f75fa 3060
3a3b7586
JB		 3061 if (adapter->flags2 & FLAG2_DMA_BURST) {
3062 /*
3063 * set the writeback threshold (only takes effect if the RDTR
3064 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3065 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3066 * granularity = 01
3067 * wthresh = 04,
3068 * hthresh = 04,
3069 * pthresh = 0x20
3070 */
3071 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3072 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3073
3074 /*
3075 * override the delay timers for enabling bursting, only if
3076 * the value was not set by the user via module options
3077 */
3078 if (adapter->rx_int_delay == DEFAULT_RDTR)
3079 adapter->rx_int_delay = BURST_RDTR;
3080 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3081 adapter->rx_abs_int_delay = BURST_RADV;
3082 }
3083
bc7f75fa
AK		 3084 /* set the Receive Delay Timer Register */
3085 ew32(RDTR, adapter->rx_int_delay);
3086
3087 /* irq moderation */
3088 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3089 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3090 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3091
3092 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3093 /* Auto-Mask interrupts upon ICR access */
3094 ctrl_ext |= E1000_CTRL_EXT_IAME;
3095 ew32(IAM, 0xffffffff);
3096 ew32(CTRL_EXT, ctrl_ext);
3097 e1e_flush();
3098
ad68076e
BA		 3099 /*
3100 * Setup the HW Rx Head and Tail Descriptor Pointers and
3101 * the Base and Length of the Rx Descriptor Ring
3102 */
bc7f75fa 3103 rdba = rx_ring->dma;
284901a9 3104 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3105 ew32(RDBAH, (rdba >> 32));
3106 ew32(RDLEN, rdlen);
3107 ew32(RDH, 0);
3108 ew32(RDT, 0);
c5083cf6
BA		 3109 rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
3110 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
bc7f75fa
AK		 3111
3112 /* Enable Receive Checksum Offload for TCP and UDP */
3113 rxcsum = er32(RXCSUM);
dc221294 3114 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3115 rxcsum |= E1000_RXCSUM_TUOFL;
3116
ad68076e
BA		 3117 /*
3118 * IPv4 payload checksum for UDP fragments must be
3119 * used in conjunction with packet-split.
3120 */
bc7f75fa
AK		 3121 if (adapter->rx_ps_pages)
3122 rxcsum |= E1000_RXCSUM_IPPCSE;
3123 } else {
3124 rxcsum &= ~E1000_RXCSUM_TUOFL;
3125 /* no need to clear IPPCSE as it defaults to 0 */
3126 }
3127 ew32(RXCSUM, rxcsum);
3128
79d4e908
BA		 3129 if (adapter->hw.mac.type == e1000_pch2lan) {
3130 /*
3131 * With jumbo frames, excessive C-state transition
3132 * latencies result in dropped transactions.
3133 */
53ec5498
BA		 3134 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3135 u32 rxdctl = er32(RXDCTL(0));
3136 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3137 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3138 } else {
af667a29
BA		 3139 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3140 PM_QOS_DEFAULT_VALUE);
53ec5498 3141 }
97ac8cae 3142 }
bc7f75fa
AK		 3143
3144 /* Enable Receives */
3145 ew32(RCTL, rctl);
3146}
3147
3148/**
ef9b965a
JB		 3149 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3150 * @netdev: network interface device structure
bc7f75fa 3151 *
ef9b965a
JB		 3152 * Writes multicast address list to the MTA hash table.
3153 * Returns: -ENOMEM on failure
3154 * 0 on no addresses written
3155 * X on writing X addresses to MTA
3156 */
3157static int e1000e_write_mc_addr_list(struct net_device *netdev)
3158{
3159 struct e1000_adapter *adapter = netdev_priv(netdev);
3160 struct e1000_hw *hw = &adapter->hw;
3161 struct netdev_hw_addr *ha;
3162 u8 *mta_list;
3163 int i;
3164
3165 if (netdev_mc_empty(netdev)) {
3166 /* nothing to program, so clear mc list */
3167 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3168 return 0;
3169 }
3170
3171 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3172 if (!mta_list)
3173 return -ENOMEM;
3174
3175 /* update_mc_addr_list expects a packed array of only addresses. */
3176 i = 0;
3177 netdev_for_each_mc_addr(ha, netdev)
3178 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3179
3180 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3181 kfree(mta_list);
3182
3183 return netdev_mc_count(netdev);
3184}
3185
3186/**
3187 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3188 * @netdev: network interface device structure
bc7f75fa 3189 *
ef9b965a
JB		 3190 * Writes unicast address list to the RAR table.
3191 * Returns: -ENOMEM on failure/insufficient address space
3192 * 0 on no addresses written
3193 * X on writing X addresses to the RAR table
bc7f75fa 3194 **/
ef9b965a 3195static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3196{
ef9b965a
JB		 3197 struct e1000_adapter *adapter = netdev_priv(netdev);
3198 struct e1000_hw *hw = &adapter->hw;
3199 unsigned int rar_entries = hw->mac.rar_entry_count;
3200 int count = 0;
3201
3202 /* save a rar entry for our hardware address */
3203 rar_entries--;
3204
3205 /* save a rar entry for the LAA workaround */
3206 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3207 rar_entries--;
3208
3209 /* return ENOMEM indicating insufficient memory for addresses */
3210 if (netdev_uc_count(netdev) > rar_entries)
3211 return -ENOMEM;
3212
3213 if (!netdev_uc_empty(netdev) && rar_entries) {
3214 struct netdev_hw_addr *ha;
3215
3216 /*
3217 * write the addresses in reverse order to avoid write
3218 * combining
3219 */
3220 netdev_for_each_uc_addr(ha, netdev) {
3221 if (!rar_entries)
3222 break;
3223 e1000e_rar_set(hw, ha->addr, rar_entries--);
3224 count++;
3225 }
3226 }
3227
3228 /* zero out the remaining RAR entries not used above */
3229 for (; rar_entries > 0; rar_entries--) {
3230 ew32(RAH(rar_entries), 0);
3231 ew32(RAL(rar_entries), 0);
3232 }
3233 e1e_flush();
3234
3235 return count;
bc7f75fa
AK		 3236}
3237
3238/**
ef9b965a 3239 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3240 * @netdev: network interface device structure
3241 *
ef9b965a
JB		 3242 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3243 * address list or the network interface flags are updated. This routine is
3244 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3245 * promiscuous mode, and all-multi behavior.
3246 **/
ef9b965a 3247static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3248{
3249 struct e1000_adapter *adapter = netdev_priv(netdev);
3250 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3251 u32 rctl;
bc7f75fa
AK		 3252
3253 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3254 rctl = er32(RCTL);
3255
ef9b965a
JB		 3256 /* clear the affected bits */
3257 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3258
bc7f75fa
AK		 3259 if (netdev->flags & IFF_PROMISC) {
3260 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3261 /* Do not hardware filter VLANs in promisc mode */
3262 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3263 } else {
ef9b965a 3264 int count;
746b9f02
PM		 3265 if (netdev->flags & IFF_ALLMULTI) {
3266 rctl |= E1000_RCTL_MPE;
746b9f02 3267 } else {
ef9b965a
JB		 3268 /*
3269 * Write addresses to the MTA, if the attempt fails
3270 * then we should just turn on promiscuous mode so
3271 * that we can at least receive multicast traffic
3272 */
3273 count = e1000e_write_mc_addr_list(netdev);
3274 if (count < 0)
3275 rctl |= E1000_RCTL_MPE;
746b9f02 3276 }
86d70e53 3277 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3278 /*
ef9b965a
JB		 3279 * Write addresses to available RAR registers, if there is not
3280 * sufficient space to store all the addresses then enable
3281 * unicast promiscuous mode
bc7f75fa 3282 */
ef9b965a
JB		 3283 count = e1000e_write_uc_addr_list(netdev);
3284 if (count < 0)
3285 rctl |= E1000_RCTL_UPE;
bc7f75fa 3286 }
86d70e53 3287
ef9b965a
JB		 3288 ew32(RCTL, rctl);
3289
86d70e53
JK		 3290 if (netdev->features & NETIF_F_HW_VLAN_RX)
3291 e1000e_vlan_strip_enable(adapter);
3292 else
3293 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3294}
3295
70495a50
BA		 3296static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3297{
3298 struct e1000_hw *hw = &adapter->hw;
3299 u32 mrqc, rxcsum;
3300 int i;
3301 static const u32 rsskey[10] = {
3302 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3303 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3304 };
3305
3306 /* Fill out hash function seed */
3307 for (i = 0; i < 10; i++)
3308 ew32(RSSRK(i), rsskey[i]);
3309
3310 /* Direct all traffic to queue 0 */
3311 for (i = 0; i < 32; i++)
3312 ew32(RETA(i), 0);
3313
3314 /*
3315 * Disable raw packet checksumming so that RSS hash is placed in
3316 * descriptor on writeback.
3317 */
3318 rxcsum = er32(RXCSUM);
3319 rxcsum |= E1000_RXCSUM_PCSD;
3320
3321 ew32(RXCSUM, rxcsum);
3322
3323 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3324 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3325 E1000_MRQC_RSS_FIELD_IPV6 |
3326 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3327 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3328
3329 ew32(MRQC, mrqc);
3330}
3331
bc7f75fa 3332/**
ad68076e 3333 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3334 * @adapter: private board structure
3335 **/
3336static void e1000_configure(struct e1000_adapter *adapter)
3337{
55aa6985
BA		 3338 struct e1000_ring *rx_ring = adapter->rx_ring;
3339
ef9b965a 3340 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3341
3342 e1000_restore_vlan(adapter);
cd791618 3343 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3344
3345 e1000_configure_tx(adapter);
70495a50
BA		 3346
3347 if (adapter->netdev->features & NETIF_F_RXHASH)
3348 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3349 e1000_setup_rctl(adapter);
3350 e1000_configure_rx(adapter);
55aa6985 3351 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3352}
3353
3354/**
3355 * e1000e_power_up_phy - restore link in case the phy was powered down
3356 * @adapter: address of board private structure
3357 *
3358 * The phy may be powered down to save power and turn off link when the
3359 * driver is unloaded and wake on lan is not enabled (among others)
3360 * *** this routine MUST be followed by a call to e1000e_reset ***
3361 **/
3362void e1000e_power_up_phy(struct e1000_adapter *adapter)
3363{
17f208de
BA		 3364 if (adapter->hw.phy.ops.power_up)
3365 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3366
3367 adapter->hw.mac.ops.setup_link(&adapter->hw);
3368}
3369
3370/**
3371 * e1000_power_down_phy - Power down the PHY
3372 *
17f208de
BA		 3373 * Power down the PHY so no link is implied when interface is down.
3374 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3375 */
3376static void e1000_power_down_phy(struct e1000_adapter *adapter)
3377{
bc7f75fa 3378 /* WoL is enabled */
23b66e2b 3379 if (adapter->wol)
bc7f75fa
AK		 3380 return;
3381
17f208de
BA		 3382 if (adapter->hw.phy.ops.power_down)
3383 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3384}
3385
3386/**
3387 * e1000e_reset - bring the hardware into a known good state
3388 *
3389 * This function boots the hardware and enables some settings that
3390 * require a configuration cycle of the hardware - those cannot be
3391 * set/changed during runtime. After reset the device needs to be
ad68076e 3392 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3393 */
3394void e1000e_reset(struct e1000_adapter *adapter)
3395{
3396 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3397 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3398 struct e1000_hw *hw = &adapter->hw;
3399 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3400 u32 pba = adapter->pba;
bc7f75fa
AK		 3401 u16 hwm;
3402
ad68076e 3403 /* reset Packet Buffer Allocation to default */
318a94d6 3404 ew32(PBA, pba);
df762464 3405
318a94d6 3406 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3407 /*
3408 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3409 * large enough to accommodate two full transmit packets,
3410 * rounded up to the next 1KB and expressed in KB. Likewise,
3411 * the Rx FIFO should be large enough to accommodate at least
3412 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3413 * expressed in KB.
3414 */
df762464 3415 pba = er32(PBA);
bc7f75fa 3416 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3417 tx_space = pba >> 16;
bc7f75fa 3418 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3419 pba &= 0xffff;
ad68076e 3420 /*
af667a29 3421 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3422 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3423 */
3424 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3425 sizeof(struct e1000_tx_desc) -
3426 ETH_FCS_LEN) * 2;
3427 min_tx_space = ALIGN(min_tx_space, 1024);
3428 min_tx_space >>= 10;
3429 /* software strips receive CRC, so leave room for it */
318a94d6 3430 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3431 min_rx_space = ALIGN(min_rx_space, 1024);
3432 min_rx_space >>= 10;
3433
ad68076e
BA		 3434 /*
3435 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3436 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3437 * allocation, take space away from current Rx allocation
3438 */
df762464
AK		 3439 if ((tx_space < min_tx_space) &&
3440 ((min_tx_space - tx_space) < pba)) {
3441 pba -= min_tx_space - tx_space;
bc7f75fa 3442
ad68076e 3443 /*
af667a29 3444 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3445 * adjustment or use Early Receive if available
3446 */
79d4e908 3447 if (pba < min_rx_space)
df762464 3448 pba = min_rx_space;
bc7f75fa 3449 }
df762464
AK		 3450
3451 ew32(PBA, pba);
bc7f75fa
AK		 3452 }
3453
ad68076e
BA		 3454 /*
3455 * flow control settings
3456 *
38eb394e 3457 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3458 * (or the size used for early receive) above it in the Rx FIFO.
3459 * Set it to the lower of:
3460 * - 90% of the Rx FIFO size, and
38eb394e 3461 * - the full Rx FIFO size minus one full frame
ad68076e 3462 */
d3738bb8
BA		 3463 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3464 fc->pause_time = 0xFFFF;
3465 else
3466 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3467 fc->send_xon = true;
d3738bb8
BA		 3468 fc->current_mode = fc->requested_mode;
3469
3470 switch (hw->mac.type) {
79d4e908
BA		 3471 case e1000_ich9lan:
3472 case e1000_ich10lan:
3473 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3474 pba = 14;
3475 ew32(PBA, pba);
3476 fc->high_water = 0x2800;
3477 fc->low_water = fc->high_water - 8;
3478 break;
3479 }
3480 /* fall-through */
d3738bb8 3481 default:
79d4e908
BA		 3482 hwm = min(((pba << 10) * 9 / 10),
3483 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3484
3485 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3486 fc->low_water = fc->high_water - 8;
3487 break;
3488 case e1000_pchlan:
38eb394e
BA		 3489 /*
3490 * Workaround PCH LOM adapter hangs with certain network
3491 * loads. If hangs persist, try disabling Tx flow control.
3492 */
3493 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3494 fc->high_water = 0x3500;
3495 fc->low_water = 0x1500;
3496 } else {
3497 fc->high_water = 0x5000;
3498 fc->low_water = 0x3000;
3499 }
a305595b 3500 fc->refresh_time = 0x1000;
d3738bb8
BA		 3501 break;
3502 case e1000_pch2lan:
3503 fc->high_water = 0x05C20;
3504 fc->low_water = 0x05048;
3505 fc->pause_time = 0x0650;
3506 fc->refresh_time = 0x0400;
828bac87
BA		 3507 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3508 pba = 14;
3509 ew32(PBA, pba);
3510 }
d3738bb8 3511 break;
38eb394e 3512 }
bc7f75fa 3513
828bac87
BA		 3514 /*
3515 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3516 * fit in receive buffer.
828bac87
BA		 3517 */
3518 if (adapter->itr_setting & 0x3) {
79d4e908 3519 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3520 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3521 dev_info(&adapter->pdev->dev,
3522 "Interrupt Throttle Rate turned off\n");
3523 adapter->flags2 |= FLAG2_DISABLE_AIM;
3524 ew32(ITR, 0);
3525 }
3526 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3527 dev_info(&adapter->pdev->dev,
3528 "Interrupt Throttle Rate turned on\n");
3529 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3530 adapter->itr = 20000;
3531 ew32(ITR, 1000000000 / (adapter->itr * 256));
3532 }
3533 }
3534
bc7f75fa
AK		 3535 /* Allow time for pending master requests to run */
3536 mac->ops.reset_hw(hw);
97ac8cae
BA		 3537
3538 /*
3539 * For parts with AMT enabled, let the firmware know
3540 * that the network interface is in control
3541 */
c43bc57e 3542 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3543 e1000e_get_hw_control(adapter);
97ac8cae 3544
bc7f75fa
AK		 3545 ew32(WUC, 0);
3546
3547 if (mac->ops.init_hw(hw))
44defeb3 3548 e_err("Hardware Error\n");
bc7f75fa
AK		 3549
3550 e1000_update_mng_vlan(adapter);
3551
3552 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3553 ew32(VET, ETH_P_8021Q);
3554
3555 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3556
3557 if (!netif_running(adapter->netdev) &&
3558 !test_bit(__E1000_TESTING, &adapter->state)) {
3559 e1000_power_down_phy(adapter);
3560 return;
3561 }
3562
bc7f75fa
AK		 3563 e1000_get_phy_info(hw);
3564
918d7197
BA		 3565 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3566 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3567 u16 phy_data = 0;
ad68076e
BA		 3568 /*
3569 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3570 * the return value of this function because there is nothing
ad68076e
BA		 3571 * different we would do if it failed
3572 */
bc7f75fa
AK		 3573 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3574 phy_data &= ~IGP02E1000_PM_SPD;
3575 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3576 }
bc7f75fa
AK		 3577}
3578
3579int e1000e_up(struct e1000_adapter *adapter)
3580{
3581 struct e1000_hw *hw = &adapter->hw;
3582
3583 /* hardware has been reset, we need to reload some things */
3584 e1000_configure(adapter);
3585
3586 clear_bit(__E1000_DOWN, &adapter->state);
3587
4662e82b
BA		 3588 if (adapter->msix_entries)
3589 e1000_configure_msix(adapter);
bc7f75fa
AK		 3590 e1000_irq_enable(adapter);
3591
400484fa 3592 netif_start_queue(adapter->netdev);
4cb9be7a 3593
bc7f75fa 3594 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3595 if (adapter->msix_entries)
3596 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3597 else
3598 ew32(ICS, E1000_ICS_LSC);
3599
bc7f75fa
AK		 3600 return 0;
3601}
3602
713b3c9e
JB		 3603static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3604{
3605 struct e1000_hw *hw = &adapter->hw;
3606
3607 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3608 return;
3609
3610 /* flush pending descriptor writebacks to memory */
3611 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3612 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3613
3614 /* execute the writes immediately */
3615 e1e_flush();
3616}
3617
67fd4fcb
JK		 3618static void e1000e_update_stats(struct e1000_adapter *adapter);
3619
bc7f75fa
AK		 3620void e1000e_down(struct e1000_adapter *adapter)
3621{
3622 struct net_device *netdev = adapter->netdev;
3623 struct e1000_hw *hw = &adapter->hw;
3624 u32 tctl, rctl;
3625
ad68076e
BA		 3626 /*
3627 * signal that we're down so the interrupt handler does not
3628 * reschedule our watchdog timer
3629 */
bc7f75fa
AK		 3630 set_bit(__E1000_DOWN, &adapter->state);
3631
3632 /* disable receives in the hardware */
3633 rctl = er32(RCTL);
7f99ae63
BA		 3634 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3635 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3636 /* flush and sleep below */
3637
4cb9be7a 3638 netif_stop_queue(netdev);
bc7f75fa
AK		 3639
3640 /* disable transmits in the hardware */
3641 tctl = er32(TCTL);
3642 tctl &= ~E1000_TCTL_EN;
3643 ew32(TCTL, tctl);
7f99ae63 3644
bc7f75fa
AK		 3645 /* flush both disables and wait for them to finish */
3646 e1e_flush();
1bba4386 3647 usleep_range(10000, 20000);
bc7f75fa 3648
bc7f75fa
AK		 3649 e1000_irq_disable(adapter);
3650
3651 del_timer_sync(&adapter->watchdog_timer);
3652 del_timer_sync(&adapter->phy_info_timer);
3653
bc7f75fa 3654 netif_carrier_off(netdev);
67fd4fcb
JK		 3655
3656 spin_lock(&adapter->stats64_lock);
3657 e1000e_update_stats(adapter);
3658 spin_unlock(&adapter->stats64_lock);
3659
400484fa 3660 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3661 e1000_clean_tx_ring(adapter->tx_ring);
3662 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3663
bc7f75fa
AK		 3664 adapter->link_speed = 0;
3665 adapter->link_duplex = 0;
3666
52cc3086
JK		 3667 if (!pci_channel_offline(adapter->pdev))
3668 e1000e_reset(adapter);
713b3c9e 3669
bc7f75fa
AK		 3670 /*
3671 * TODO: for power management, we could drop the link and
3672 * pci_disable_device here.
3673 */
3674}
3675
3676void e1000e_reinit_locked(struct e1000_adapter *adapter)
3677{
3678 might_sleep();
3679 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3680 usleep_range(1000, 2000);
bc7f75fa
AK		 3681 e1000e_down(adapter);
3682 e1000e_up(adapter);
3683 clear_bit(__E1000_RESETTING, &adapter->state);
3684}
3685
3686/**
3687 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3688 * @adapter: board private structure to initialize
3689 *
3690 * e1000_sw_init initializes the Adapter private data structure.
3691 * Fields are initialized based on PCI device information and
3692 * OS network device settings (MTU size).
3693 **/
3694static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3695{
bc7f75fa
AK		 3696 struct net_device *netdev = adapter->netdev;
3697
3698 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3699 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3700 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3701 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3702 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3703 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3704
67fd4fcb
JK		 3705 spin_lock_init(&adapter->stats64_lock);
3706
4662e82b 3707 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3708
4662e82b
BA		 3709 if (e1000_alloc_queues(adapter))
3710 return -ENOMEM;
bc7f75fa 3711
bc7f75fa 3712 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3713 e1000_irq_disable(adapter);
3714
bc7f75fa
AK		 3715 set_bit(__E1000_DOWN, &adapter->state);
3716 return 0;
bc7f75fa
AK		 3717}
3718
f8d59f78
BA		 3719/**
3720 * e1000_intr_msi_test - Interrupt Handler
3721 * @irq: interrupt number
3722 * @data: pointer to a network interface device structure
3723 **/
3724static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3725{
3726 struct net_device *netdev = data;
3727 struct e1000_adapter *adapter = netdev_priv(netdev);
3728 struct e1000_hw *hw = &adapter->hw;
3729 u32 icr = er32(ICR);
3730
3bb99fe2 3731 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3732 if (icr & E1000_ICR_RXSEQ) {
3733 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3734 wmb();
3735 }
3736
3737 return IRQ_HANDLED;
3738}
3739
3740/**
3741 * e1000_test_msi_interrupt - Returns 0 for successful test
3742 * @adapter: board private struct
3743 *
3744 * code flow taken from tg3.c
3745 **/
3746static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3747{
3748 struct net_device *netdev = adapter->netdev;
3749 struct e1000_hw *hw = &adapter->hw;
3750 int err;
3751
3752 /* poll_enable hasn't been called yet, so don't need disable */
3753 /* clear any pending events */
3754 er32(ICR);
3755
3756 /* free the real vector and request a test handler */
3757 e1000_free_irq(adapter);
4662e82b 3758 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3759
3760 /* Assume that the test fails, if it succeeds then the test
3761 * MSI irq handler will unset this flag */
3762 adapter->flags |= FLAG_MSI_TEST_FAILED;
3763
3764 err = pci_enable_msi(adapter->pdev);
3765 if (err)
3766 goto msi_test_failed;
3767
a0607fd3 3768 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3769 netdev->name, netdev);
3770 if (err) {
3771 pci_disable_msi(adapter->pdev);
3772 goto msi_test_failed;
3773 }
3774
3775 wmb();
3776
3777 e1000_irq_enable(adapter);
3778
3779 /* fire an unusual interrupt on the test handler */
3780 ew32(ICS, E1000_ICS_RXSEQ);
3781 e1e_flush();
3782 msleep(50);
3783
3784 e1000_irq_disable(adapter);
3785
3786 rmb();
3787
3788 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3789 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3790 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3791 } else {
068e8a30 3792 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3793 }
f8d59f78
BA		 3794
3795 free_irq(adapter->pdev->irq, netdev);
3796 pci_disable_msi(adapter->pdev);
3797
f8d59f78 3798msi_test_failed:
4662e82b 3799 e1000e_set_interrupt_capability(adapter);
068e8a30 3800 return e1000_request_irq(adapter);
f8d59f78
BA		 3801}
3802
3803/**
3804 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3805 * @adapter: board private struct
3806 *
3807 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3808 **/
3809static int e1000_test_msi(struct e1000_adapter *adapter)
3810{
3811 int err;
3812 u16 pci_cmd;
3813
3814 if (!(adapter->flags & FLAG_MSI_ENABLED))
3815 return 0;
3816
3817 /* disable SERR in case the MSI write causes a master abort */
3818 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3819 if (pci_cmd & PCI_COMMAND_SERR)
3820 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3821 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3822
3823 err = e1000_test_msi_interrupt(adapter);
3824
36f2407f
DN		 3825 /* re-enable SERR */
3826 if (pci_cmd & PCI_COMMAND_SERR) {
3827 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3828 pci_cmd |= PCI_COMMAND_SERR;
3829 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3830 }
f8d59f78 3831
f8d59f78
BA		 3832 return err;
3833}
3834
bc7f75fa
AK		 3835/**
3836 * e1000_open - Called when a network interface is made active
3837 * @netdev: network interface device structure
3838 *
3839 * Returns 0 on success, negative value on failure
3840 *
3841 * The open entry point is called when a network interface is made
3842 * active by the system (IFF_UP). At this point all resources needed
3843 * for transmit and receive operations are allocated, the interrupt
3844 * handler is registered with the OS, the watchdog timer is started,
3845 * and the stack is notified that the interface is ready.
3846 **/
3847static int e1000_open(struct net_device *netdev)
3848{
3849 struct e1000_adapter *adapter = netdev_priv(netdev);
3850 struct e1000_hw *hw = &adapter->hw;
23606cf5 3851 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3852 int err;
3853
3854 /* disallow open during test */
3855 if (test_bit(__E1000_TESTING, &adapter->state))
3856 return -EBUSY;
3857
23606cf5
RW		 3858 pm_runtime_get_sync(&pdev->dev);
3859
9c563d20
JB		 3860 netif_carrier_off(netdev);
3861
bc7f75fa 3862 /* allocate transmit descriptors */
55aa6985 3863 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3864 if (err)
3865 goto err_setup_tx;
3866
3867 /* allocate receive descriptors */
55aa6985 3868 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3869 if (err)
3870 goto err_setup_rx;
3871
11b08be8
BA		 3872 /*
3873 * If AMT is enabled, let the firmware know that the network
3874 * interface is now open and reset the part to a known state.
3875 */
3876 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3877 e1000e_get_hw_control(adapter);
11b08be8
BA		 3878 e1000e_reset(adapter);
3879 }
3880
bc7f75fa
AK		 3881 e1000e_power_up_phy(adapter);
3882
3883 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3884 if ((adapter->hw.mng_cookie.status &
3885 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3886 e1000_update_mng_vlan(adapter);
3887
79d4e908
BA		 3888 /* DMA latency requirement to workaround jumbo issue */
3889 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3890 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3891 PM_QOS_CPU_DMA_LATENCY,
3892 PM_QOS_DEFAULT_VALUE);
c128ec29 3893
ad68076e
BA		 3894 /*
3895 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3896 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3897 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3898 * clean_rx handler before we do so.
3899 */
bc7f75fa
AK		 3900 e1000_configure(adapter);
3901
3902 err = e1000_request_irq(adapter);
3903 if (err)
3904 goto err_req_irq;
3905
f8d59f78
BA		 3906 /*
3907 * Work around PCIe errata with MSI interrupts causing some chipsets to
3908 * ignore e1000e MSI messages, which means we need to test our MSI
3909 * interrupt now
3910 */
4662e82b 3911 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3912 err = e1000_test_msi(adapter);
3913 if (err) {
3914 e_err("Interrupt allocation failed\n");
3915 goto err_req_irq;
3916 }
3917 }
3918
bc7f75fa
AK		 3919 /* From here on the code is the same as e1000e_up() */
3920 clear_bit(__E1000_DOWN, &adapter->state);
3921
3922 napi_enable(&adapter->napi);
3923
3924 e1000_irq_enable(adapter);
3925
09357b00 3926 adapter->tx_hang_recheck = false;
4cb9be7a 3927 netif_start_queue(netdev);
d55b53ff 3928
23606cf5
RW		 3929 adapter->idle_check = true;
3930 pm_runtime_put(&pdev->dev);
3931
bc7f75fa 3932 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3933 if (adapter->msix_entries)
3934 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3935 else
3936 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3937
3938 return 0;
3939
3940err_req_irq:
31dbe5b4 3941 e1000e_release_hw_control(adapter);
bc7f75fa 3942 e1000_power_down_phy(adapter);
55aa6985 3943 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3944err_setup_rx:
55aa6985 3945 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3946err_setup_tx:
3947 e1000e_reset(adapter);
23606cf5 3948 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3949
3950 return err;
3951}
3952
3953/**
3954 * e1000_close - Disables a network interface
3955 * @netdev: network interface device structure
3956 *
3957 * Returns 0, this is not allowed to fail
3958 *
3959 * The close entry point is called when an interface is de-activated
3960 * by the OS. The hardware is still under the drivers control, but
3961 * needs to be disabled. A global MAC reset is issued to stop the
3962 * hardware, and all transmit and receive resources are freed.
3963 **/
3964static int e1000_close(struct net_device *netdev)
3965{
3966 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3967 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3968
3969 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3970
3971 pm_runtime_get_sync(&pdev->dev);
3972
5f4a780d
BA		 3973 napi_disable(&adapter->napi);
3974
23606cf5
RW		 3975 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3976 e1000e_down(adapter);
3977 e1000_free_irq(adapter);
3978 }
bc7f75fa 3979 e1000_power_down_phy(adapter);
bc7f75fa 3980
55aa6985
BA		 3981 e1000e_free_tx_resources(adapter->tx_ring);
3982 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3983
ad68076e
BA		 3984 /*
3985 * kill manageability vlan ID if supported, but not if a vlan with
3986 * the same ID is registered on the host OS (let 8021q kill it)
3987 */
86d70e53
JK		 3988 if (adapter->hw.mng_cookie.status &
3989 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3990 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3991
ad68076e
BA		 3992 /*
3993 * If AMT is enabled, let the firmware know that the network
3994 * interface is now closed
3995 */
31dbe5b4
BA		 3996 if ((adapter->flags & FLAG_HAS_AMT) &&
3997 !test_bit(__E1000_TESTING, &adapter->state))
3998 e1000e_release_hw_control(adapter);
bc7f75fa 3999
79d4e908 4000 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4001 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4002
23606cf5
RW		 4003 pm_runtime_put_sync(&pdev->dev);
4004
bc7f75fa
AK		 4005 return 0;
4006}
4007/**
4008 * e1000_set_mac - Change the Ethernet Address of the NIC
4009 * @netdev: network interface device structure
4010 * @p: pointer to an address structure
4011 *
4012 * Returns 0 on success, negative on failure
4013 **/
4014static int e1000_set_mac(struct net_device *netdev, void *p)
4015{
4016 struct e1000_adapter *adapter = netdev_priv(netdev);
4017 struct sockaddr *addr = p;
4018
4019 if (!is_valid_ether_addr(addr->sa_data))
4020 return -EADDRNOTAVAIL;
4021
4022 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4023 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4024
4025 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4026
4027 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4028 /* activate the work around */
4029 e1000e_set_laa_state_82571(&adapter->hw, 1);
4030
ad68076e
BA		 4031 /*
4032 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4033 * between the time RAR[0] gets clobbered and the time it
4034 * gets fixed (in e1000_watchdog), the actual LAA is in one
4035 * of the RARs and no incoming packets directed to this port
4036 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4037 * RAR[14]
4038 */
bc7f75fa
AK		 4039 e1000e_rar_set(&adapter->hw,
4040 adapter->hw.mac.addr,
4041 adapter->hw.mac.rar_entry_count - 1);
4042 }
4043
4044 return 0;
4045}
4046
a8f88ff5
JB		 4047/**
4048 * e1000e_update_phy_task - work thread to update phy
4049 * @work: pointer to our work struct
4050 *
4051 * this worker thread exists because we must acquire a
4052 * semaphore to read the phy, which we could msleep while
4053 * waiting for it, and we can't msleep in a timer.
4054 **/
4055static void e1000e_update_phy_task(struct work_struct *work)
4056{
4057 struct e1000_adapter *adapter = container_of(work,
4058 struct e1000_adapter, update_phy_task);
615b32af
JB		 4059
4060 if (test_bit(__E1000_DOWN, &adapter->state))
4061 return;
4062
a8f88ff5
JB		 4063 e1000_get_phy_info(&adapter->hw);
4064}
4065
ad68076e
BA		 4066/*
4067 * Need to wait a few seconds after link up to get diagnostic information from
4068 * the phy
4069 */
bc7f75fa
AK		 4070static void e1000_update_phy_info(unsigned long data)
4071{
4072 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4073
4074 if (test_bit(__E1000_DOWN, &adapter->state))
4075 return;
4076
a8f88ff5 4077 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4078}
4079
8c7bbb92
BA		 4080/**
4081 * e1000e_update_phy_stats - Update the PHY statistics counters
4082 * @adapter: board private structure
2b6b168d
BA		 4083 *
4084 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4085 **/
4086static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4087{
4088 struct e1000_hw *hw = &adapter->hw;
4089 s32 ret_val;
4090 u16 phy_data;
4091
4092 ret_val = hw->phy.ops.acquire(hw);
4093 if (ret_val)
4094 return;
4095
8c7bbb92
BA		 4096 /*
4097 * A page set is expensive so check if already on desired page.
4098 * If not, set to the page with the PHY status registers.
4099 */
2b6b168d 4100 hw->phy.addr = 1;
8c7bbb92
BA		 4101 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4102 &phy_data);
4103 if (ret_val)
4104 goto release;
2b6b168d
BA		 4105 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4106 ret_val = hw->phy.ops.set_page(hw,
4107 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4108 if (ret_val)
4109 goto release;
4110 }
4111
8c7bbb92 4112 /* Single Collision Count */
2b6b168d
BA		 4113 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4114 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4115 if (!ret_val)
4116 adapter->stats.scc += phy_data;
4117
4118 /* Excessive Collision Count */
2b6b168d
BA		 4119 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4120 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4121 if (!ret_val)
4122 adapter->stats.ecol += phy_data;
4123
4124 /* Multiple Collision Count */
2b6b168d
BA		 4125 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4126 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4127 if (!ret_val)
4128 adapter->stats.mcc += phy_data;
4129
4130 /* Late Collision Count */
2b6b168d
BA		 4131 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4132 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4133 if (!ret_val)
4134 adapter->stats.latecol += phy_data;
4135
4136 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4137 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4138 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4139 if (!ret_val)
4140 hw->mac.collision_delta = phy_data;
4141
4142 /* Defer Count */
2b6b168d
BA		 4143 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4144 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4145 if (!ret_val)
4146 adapter->stats.dc += phy_data;
4147
4148 /* Transmit with no CRS */
2b6b168d
BA		 4149 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4150 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4151 if (!ret_val)
4152 adapter->stats.tncrs += phy_data;
4153
4154release:
4155 hw->phy.ops.release(hw);
4156}
4157
bc7f75fa
AK		 4158/**
4159 * e1000e_update_stats - Update the board statistics counters
4160 * @adapter: board private structure
4161 **/
67fd4fcb 4162static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4163{
7274c20f 4164 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4165 struct e1000_hw *hw = &adapter->hw;
4166 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4167
4168 /*
4169 * Prevent stats update while adapter is being reset, or if the pci
4170 * connection is down.
4171 */
4172 if (adapter->link_speed == 0)
4173 return;
4174 if (pci_channel_offline(pdev))
4175 return;
4176
bc7f75fa
AK		 4177 adapter->stats.crcerrs += er32(CRCERRS);
4178 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4179 adapter->stats.gorc += er32(GORCL);
4180 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4181 adapter->stats.bprc += er32(BPRC);
4182 adapter->stats.mprc += er32(MPRC);
4183 adapter->stats.roc += er32(ROC);
4184
bc7f75fa 4185 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4186
4187 /* Half-duplex statistics */
4188 if (adapter->link_duplex == HALF_DUPLEX) {
4189 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4190 e1000e_update_phy_stats(adapter);
4191 } else {
4192 adapter->stats.scc += er32(SCC);
4193 adapter->stats.ecol += er32(ECOL);
4194 adapter->stats.mcc += er32(MCC);
4195 adapter->stats.latecol += er32(LATECOL);
4196 adapter->stats.dc += er32(DC);
4197
4198 hw->mac.collision_delta = er32(COLC);
4199
4200 if ((hw->mac.type != e1000_82574) &&
4201 (hw->mac.type != e1000_82583))
4202 adapter->stats.tncrs += er32(TNCRS);
4203 }
4204 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4205 }
8c7bbb92 4206
bc7f75fa
AK		 4207 adapter->stats.xonrxc += er32(XONRXC);
4208 adapter->stats.xontxc += er32(XONTXC);
4209 adapter->stats.xoffrxc += er32(XOFFRXC);
4210 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4211 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4212 adapter->stats.gotc += er32(GOTCL);
4213 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4214 adapter->stats.rnbc += er32(RNBC);
4215 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4216
4217 adapter->stats.mptc += er32(MPTC);
4218 adapter->stats.bptc += er32(BPTC);
4219
4220 /* used for adaptive IFS */
4221
4222 hw->mac.tx_packet_delta = er32(TPT);
4223 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4224
4225 adapter->stats.algnerrc += er32(ALGNERRC);
4226 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4227 adapter->stats.cexterr += er32(CEXTERR);
4228 adapter->stats.tsctc += er32(TSCTC);
4229 adapter->stats.tsctfc += er32(TSCTFC);
4230
bc7f75fa 4231 /* Fill out the OS statistics structure */
7274c20f
AK		 4232 netdev->stats.multicast = adapter->stats.mprc;
4233 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4234
4235 /* Rx Errors */
4236
ad68076e
BA		 4237 /*
4238 * RLEC on some newer hardware can be incorrect so build
4239 * our own version based on RUC and ROC
4240 */
7274c20f 4241 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4242 adapter->stats.crcerrs + adapter->stats.algnerrc +
4243 adapter->stats.ruc + adapter->stats.roc +
4244 adapter->stats.cexterr;
7274c20f 4245 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4246 adapter->stats.roc;
7274c20f
AK		 4247 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4248 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4249 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4250
4251 /* Tx Errors */
7274c20f 4252 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4253 adapter->stats.latecol;
7274c20f
AK		 4254 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4255 netdev->stats.tx_window_errors = adapter->stats.latecol;
4256 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4257
4258 /* Tx Dropped needs to be maintained elsewhere */
4259
bc7f75fa
AK		 4260 /* Management Stats */
4261 adapter->stats.mgptc += er32(MGTPTC);
4262 adapter->stats.mgprc += er32(MGTPRC);
4263 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4264}
4265
7c25769f
BA		 4266/**
4267 * e1000_phy_read_status - Update the PHY register status snapshot
4268 * @adapter: board private structure
4269 **/
4270static void e1000_phy_read_status(struct e1000_adapter *adapter)
4271{
4272 struct e1000_hw *hw = &adapter->hw;
4273 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4274
4275 if ((er32(STATUS) & E1000_STATUS_LU) &&
4276 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4277 int ret_val;
4278
7c25769f
BA		 4279 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4280 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4281 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4282 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4283 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4284 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4285 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4286 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4287 if (ret_val)
44defeb3 4288 e_warn("Error reading PHY register\n");
7c25769f
BA		 4289 } else {
4290 /*
4291 * Do not read PHY registers if link is not up
4292 * Set values to typical power-on defaults
4293 */
4294 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4295 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4296 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4297 BMSR_ERCAP);
4298 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4299 ADVERTISE_ALL | ADVERTISE_CSMA);
4300 phy->lpa = 0;
4301 phy->expansion = EXPANSION_ENABLENPAGE;
4302 phy->ctrl1000 = ADVERTISE_1000FULL;
4303 phy->stat1000 = 0;
4304 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4305 }
7c25769f
BA		 4306}
4307
bc7f75fa
AK		 4308static void e1000_print_link_info(struct e1000_adapter *adapter)
4309{
bc7f75fa
AK		 4310 struct e1000_hw *hw = &adapter->hw;
4311 u32 ctrl = er32(CTRL);
4312
8f12fe86 4313 /* Link status message must follow this format for user tools */
ef456f85
JK		 4314 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4315 adapter->netdev->name,
4316 adapter->link_speed,
4317 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4318 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4319 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4320 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4321}
4322
0c6bdb30 4323static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4324{
4325 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4326 bool link_active = false;
318a94d6
JK		 4327 s32 ret_val = 0;
4328
4329 /*
4330 * get_link_status is set on LSC (link status) interrupt or
4331 * Rx sequence error interrupt. get_link_status will stay
4332 * false until the check_for_link establishes link
4333 * for copper adapters ONLY
4334 */
4335 switch (hw->phy.media_type) {
4336 case e1000_media_type_copper:
4337 if (hw->mac.get_link_status) {
4338 ret_val = hw->mac.ops.check_for_link(hw);
4339 link_active = !hw->mac.get_link_status;
4340 } else {
3db1cd5c 4341 link_active = true;
318a94d6
JK		 4342 }
4343 break;
4344 case e1000_media_type_fiber:
4345 ret_val = hw->mac.ops.check_for_link(hw);
4346 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4347 break;
4348 case e1000_media_type_internal_serdes:
4349 ret_val = hw->mac.ops.check_for_link(hw);
4350 link_active = adapter->hw.mac.serdes_has_link;
4351 break;
4352 default:
4353 case e1000_media_type_unknown:
4354 break;
4355 }
4356
4357 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4358 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4359 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4360 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4361 }
4362
4363 return link_active;
4364}
4365
4366static void e1000e_enable_receives(struct e1000_adapter *adapter)
4367{
4368 /* make sure the receive unit is started */
4369 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4370 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4371 struct e1000_hw *hw = &adapter->hw;
4372 u32 rctl = er32(RCTL);
4373 ew32(RCTL, rctl | E1000_RCTL_EN);
4374 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4375 }
4376}
4377
ff10e13c
CW		 4378static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4379{
4380 struct e1000_hw *hw = &adapter->hw;
4381
4382 /*
4383 * With 82574 controllers, PHY needs to be checked periodically
4384 * for hung state and reset, if two calls return true
4385 */
4386 if (e1000_check_phy_82574(hw))
4387 adapter->phy_hang_count++;
4388 else
4389 adapter->phy_hang_count = 0;
4390
4391 if (adapter->phy_hang_count > 1) {
4392 adapter->phy_hang_count = 0;
4393 schedule_work(&adapter->reset_task);
4394 }
4395}
4396
bc7f75fa
AK		 4397/**
4398 * e1000_watchdog - Timer Call-back
4399 * @data: pointer to adapter cast into an unsigned long
4400 **/
4401static void e1000_watchdog(unsigned long data)
4402{
4403 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4404
4405 /* Do the rest outside of interrupt context */
4406 schedule_work(&adapter->watchdog_task);
4407
4408 /* TODO: make this use queue_delayed_work() */
4409}
4410
4411static void e1000_watchdog_task(struct work_struct *work)
4412{
4413 struct e1000_adapter *adapter = container_of(work,
4414 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4415 struct net_device *netdev = adapter->netdev;
4416 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4417 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4418 struct e1000_ring *tx_ring = adapter->tx_ring;
4419 struct e1000_hw *hw = &adapter->hw;
4420 u32 link, tctl;
bc7f75fa 4421
615b32af
JB		 4422 if (test_bit(__E1000_DOWN, &adapter->state))
4423 return;
4424
b405e8df 4425 link = e1000e_has_link(adapter);
318a94d6 4426 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4427 /* Cancel scheduled suspend requests. */
4428 pm_runtime_resume(netdev->dev.parent);
4429
318a94d6 4430 e1000e_enable_receives(adapter);
bc7f75fa 4431 goto link_up;
bc7f75fa
AK		 4432 }
4433
4434 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4435 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4436 e1000_update_mng_vlan(adapter);
4437
bc7f75fa
AK		 4438 if (link) {
4439 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4440 bool txb2b = true;
23606cf5
RW		 4441
4442 /* Cancel scheduled suspend requests. */
4443 pm_runtime_resume(netdev->dev.parent);
4444
318a94d6 4445 /* update snapshot of PHY registers on LSC */
7c25769f 4446 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4447 mac->ops.get_link_up_info(&adapter->hw,
4448 &adapter->link_speed,
4449 &adapter->link_duplex);
4450 e1000_print_link_info(adapter);
f4187b56
BA		 4451 /*
4452 * On supported PHYs, check for duplex mismatch only
4453 * if link has autonegotiated at 10/100 half
4454 */
4455 if ((hw->phy.type == e1000_phy_igp_3 ||
4456 hw->phy.type == e1000_phy_bm) &&
4457 (hw->mac.autoneg == true) &&
4458 (adapter->link_speed == SPEED_10 ||
4459 adapter->link_speed == SPEED_100) &&
4460 (adapter->link_duplex == HALF_DUPLEX)) {
4461 u16 autoneg_exp;
4462
4463 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4464
4465 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4466 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4467 }
4468
f49c57e1 4469 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4470 adapter->tx_timeout_factor = 1;
4471 switch (adapter->link_speed) {
4472 case SPEED_10:
3db1cd5c 4473 txb2b = false;
10f1b492 4474 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4475 break;
4476 case SPEED_100:
3db1cd5c 4477 txb2b = false;
4c86e0b9 4478 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4479 break;
4480 }
4481
ad68076e
BA		 4482 /*
4483 * workaround: re-program speed mode bit after
4484 * link-up event
4485 */
bc7f75fa
AK		 4486 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4487 !txb2b) {
4488 u32 tarc0;
e9ec2c0f 4489 tarc0 = er32(TARC(0));
bc7f75fa 4490 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4491 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4492 }
4493
ad68076e
BA		 4494 /*
4495 * disable TSO for pcie and 10/100 speeds, to avoid
4496 * some hardware issues
4497 */
bc7f75fa
AK		 4498 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4499 switch (adapter->link_speed) {
4500 case SPEED_10:
4501 case SPEED_100:
44defeb3 4502 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4503 netdev->features &= ~NETIF_F_TSO;
4504 netdev->features &= ~NETIF_F_TSO6;
4505 break;
4506 case SPEED_1000:
4507 netdev->features |= NETIF_F_TSO;
4508 netdev->features |= NETIF_F_TSO6;
4509 break;
4510 default:
4511 /* oops */
4512 break;
4513 }
4514 }
4515
ad68076e
BA		 4516 /*
4517 * enable transmits in the hardware, need to do this
4518 * after setting TARC(0)
4519 */
bc7f75fa
AK		 4520 tctl = er32(TCTL);
4521 tctl |= E1000_TCTL_EN;
4522 ew32(TCTL, tctl);
4523
75eb0fad
BA		 4524 /*
4525 * Perform any post-link-up configuration before
4526 * reporting link up.
4527 */
4528 if (phy->ops.cfg_on_link_up)
4529 phy->ops.cfg_on_link_up(hw);
4530
bc7f75fa 4531 netif_carrier_on(netdev);
bc7f75fa
AK		 4532
4533 if (!test_bit(__E1000_DOWN, &adapter->state))
4534 mod_timer(&adapter->phy_info_timer,
4535 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4536 }
4537 } else {
4538 if (netif_carrier_ok(netdev)) {
4539 adapter->link_speed = 0;
4540 adapter->link_duplex = 0;
8f12fe86
BA		 4541 /* Link status message must follow this format */
4542 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4543 adapter->netdev->name);
bc7f75fa 4544 netif_carrier_off(netdev);
bc7f75fa
AK		 4545 if (!test_bit(__E1000_DOWN, &adapter->state))
4546 mod_timer(&adapter->phy_info_timer,
4547 round_jiffies(jiffies + 2 * HZ));
4548
4549 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4550 schedule_work(&adapter->reset_task);
23606cf5
RW		 4551 else
4552 pm_schedule_suspend(netdev->dev.parent,
4553 LINK_TIMEOUT);
bc7f75fa
AK		 4554 }
4555 }
4556
4557link_up:
67fd4fcb 4558 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4559 e1000e_update_stats(adapter);
4560
4561 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4562 adapter->tpt_old = adapter->stats.tpt;
4563 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4564 adapter->colc_old = adapter->stats.colc;
4565
7c25769f
BA		 4566 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4567 adapter->gorc_old = adapter->stats.gorc;
4568 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4569 adapter->gotc_old = adapter->stats.gotc;
2084b114 4570 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4571
4572 e1000e_update_adaptive(&adapter->hw);
4573
90da0669
BA		 4574 if (!netif_carrier_ok(netdev) &&
4575 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4576 /*
4577 * We've lost link, so the controller stops DMA,
4578 * but we've got queued Tx work that's never going
4579 * to get done, so reset controller to flush Tx.
4580 * (Do the reset outside of interrupt context).
4581 */
90da0669
BA		 4582 schedule_work(&adapter->reset_task);
4583 /* return immediately since reset is imminent */
4584 return;
bc7f75fa
AK		 4585 }
4586
eab2abf5
JB		 4587 /* Simple mode for Interrupt Throttle Rate (ITR) */
4588 if (adapter->itr_setting == 4) {
4589 /*
4590 * Symmetric Tx/Rx gets a reduced ITR=2000;
4591 * Total asymmetrical Tx or Rx gets ITR=8000;
4592 * everyone else is between 2000-8000.
4593 */
4594 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4595 u32 dif = (adapter->gotc > adapter->gorc ?
4596 adapter->gotc - adapter->gorc :
4597 adapter->gorc - adapter->gotc) / 10000;
4598 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4599
4600 ew32(ITR, 1000000000 / (itr * 256));
4601 }
4602
ad68076e 4603 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4604 if (adapter->msix_entries)
4605 ew32(ICS, adapter->rx_ring->ims_val);
4606 else
4607 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4608
713b3c9e
JB		 4609 /* flush pending descriptors to memory before detecting Tx hang */
4610 e1000e_flush_descriptors(adapter);
4611
bc7f75fa 4612 /* Force detection of hung controller every watchdog period */
3db1cd5c 4613 adapter->detect_tx_hung = true;
bc7f75fa 4614
ad68076e
BA		 4615 /*
4616 * With 82571 controllers, LAA may be overwritten due to controller
4617 * reset from the other port. Set the appropriate LAA in RAR[0]
4618 */
bc7f75fa
AK		 4619 if (e1000e_get_laa_state_82571(hw))
4620 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4621
ff10e13c
CW		 4622 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4623 e1000e_check_82574_phy_workaround(adapter);
4624
bc7f75fa
AK		 4625 /* Reset the timer */
4626 if (!test_bit(__E1000_DOWN, &adapter->state))
4627 mod_timer(&adapter->watchdog_timer,
4628 round_jiffies(jiffies + 2 * HZ));
4629}
4630
4631#define E1000_TX_FLAGS_CSUM 0x00000001
4632#define E1000_TX_FLAGS_VLAN 0x00000002
4633#define E1000_TX_FLAGS_TSO 0x00000004
4634#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4635#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4636#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4637#define E1000_TX_FLAGS_VLAN_SHIFT 16
4638
55aa6985 4639static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4640{
bc7f75fa
AK		 4641 struct e1000_context_desc *context_desc;
4642 struct e1000_buffer *buffer_info;
4643 unsigned int i;
4644 u32 cmd_length = 0;
4645 u16 ipcse = 0, tucse, mss;
4646 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4647
3d5e33c9
BA		 4648 if (!skb_is_gso(skb))
4649 return 0;
bc7f75fa 4650
3d5e33c9 4651 if (skb_header_cloned(skb)) {
90da0669
BA		 4652 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4653
3d5e33c9
BA		 4654 if (err)
4655 return err;
bc7f75fa
AK		 4656 }
4657
3d5e33c9
BA		 4658 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4659 mss = skb_shinfo(skb)->gso_size;
4660 if (skb->protocol == htons(ETH_P_IP)) {
4661 struct iphdr *iph = ip_hdr(skb);
4662 iph->tot_len = 0;
4663 iph->check = 0;
4664 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4665 0, IPPROTO_TCP, 0);
4666 cmd_length = E1000_TXD_CMD_IP;
4667 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4668 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4669 ipv6_hdr(skb)->payload_len = 0;
4670 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4671 &ipv6_hdr(skb)->daddr,
4672 0, IPPROTO_TCP, 0);
4673 ipcse = 0;
4674 }
4675 ipcss = skb_network_offset(skb);
4676 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4677 tucss = skb_transport_offset(skb);
4678 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4679 tucse = 0;
4680
4681 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4682 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4683
4684 i = tx_ring->next_to_use;
4685 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4686 buffer_info = &tx_ring->buffer_info[i];
4687
4688 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4689 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4690 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4691 context_desc->upper_setup.tcp_fields.tucss = tucss;
4692 context_desc->upper_setup.tcp_fields.tucso = tucso;
4693 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4694 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4695 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4696 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4697
4698 buffer_info->time_stamp = jiffies;
4699 buffer_info->next_to_watch = i;
4700
4701 i++;
4702 if (i == tx_ring->count)
4703 i = 0;
4704 tx_ring->next_to_use = i;
4705
4706 return 1;
bc7f75fa
AK		 4707}
4708
55aa6985 4709static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4710{
55aa6985 4711 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4712 struct e1000_context_desc *context_desc;
4713 struct e1000_buffer *buffer_info;
4714 unsigned int i;
4715 u8 css;
af807c82 4716 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4717 __be16 protocol;
bc7f75fa 4718
af807c82
DG		 4719 if (skb->ip_summed != CHECKSUM_PARTIAL)
4720 return 0;
bc7f75fa 4721
5f66f208
AJ		 4722 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4723 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4724 else
4725 protocol = skb->protocol;
4726
3f518390 4727 switch (protocol) {
09640e63 4728 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4729 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4730 cmd_len |= E1000_TXD_CMD_TCP;
4731 break;
09640e63 4732 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4733 /* XXX not handling all IPV6 headers */
4734 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4735 cmd_len |= E1000_TXD_CMD_TCP;
4736 break;
4737 default:
4738 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4739 e_warn("checksum_partial proto=%x!\n",
4740 be16_to_cpu(protocol));
af807c82 4741 break;
bc7f75fa
AK		 4742 }
4743
0d0b1672 4744 css = skb_checksum_start_offset(skb);
af807c82
DG		 4745
4746 i = tx_ring->next_to_use;
4747 buffer_info = &tx_ring->buffer_info[i];
4748 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4749
4750 context_desc->lower_setup.ip_config = 0;
4751 context_desc->upper_setup.tcp_fields.tucss = css;
4752 context_desc->upper_setup.tcp_fields.tucso =
4753 css + skb->csum_offset;
4754 context_desc->upper_setup.tcp_fields.tucse = 0;
4755 context_desc->tcp_seg_setup.data = 0;
4756 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4757
4758 buffer_info->time_stamp = jiffies;
4759 buffer_info->next_to_watch = i;
4760
4761 i++;
4762 if (i == tx_ring->count)
4763 i = 0;
4764 tx_ring->next_to_use = i;
4765
4766 return 1;
bc7f75fa
AK		 4767}
4768
4769#define E1000_MAX_PER_TXD 8192
4770#define E1000_MAX_TXD_PWR 12
4771
55aa6985
BA		 4772static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4773 unsigned int first, unsigned int max_per_txd,
4774 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4775{
55aa6985 4776 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4777 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4778 struct e1000_buffer *buffer_info;
8ddc951c 4779 unsigned int len = skb_headlen(skb);
03b1320d 4780 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4781 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4782
4783 i = tx_ring->next_to_use;
4784
4785 while (len) {
1b7719c4 4786 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4787 size = min(len, max_per_txd);
4788
bc7f75fa 4789 buffer_info->length = size;
bc7f75fa 4790 buffer_info->time_stamp = jiffies;
bc7f75fa 4791 buffer_info->next_to_watch = i;
0be3f55f
NN		 4792 buffer_info->dma = dma_map_single(&pdev->dev,
4793 skb->data + offset,
af667a29 4794 size, DMA_TO_DEVICE);
03b1320d 4795 buffer_info->mapped_as_page = false;
0be3f55f 4796 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4797 goto dma_error;
bc7f75fa
AK		 4798
4799 len -= size;
4800 offset += size;
03b1320d 4801 count++;
1b7719c4
AD		 4802
4803 if (len) {
4804 i++;
4805 if (i == tx_ring->count)
4806 i = 0;
4807 }
bc7f75fa
AK		 4808 }
4809
4810 for (f = 0; f < nr_frags; f++) {
9e903e08 4811 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4812
4813 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4814 len = skb_frag_size(frag);
877749bf 4815 offset = 0;
bc7f75fa
AK		 4816
4817 while (len) {
1b7719c4
AD		 4818 i++;
4819 if (i == tx_ring->count)
4820 i = 0;
4821
bc7f75fa
AK		 4822 buffer_info = &tx_ring->buffer_info[i];
4823 size = min(len, max_per_txd);
bc7f75fa
AK		 4824
4825 buffer_info->length = size;
4826 buffer_info->time_stamp = jiffies;
bc7f75fa 4827 buffer_info->next_to_watch = i;
877749bf
IC		 4828 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4829 offset, size, DMA_TO_DEVICE);
03b1320d 4830 buffer_info->mapped_as_page = true;
0be3f55f 4831 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4832 goto dma_error;
bc7f75fa
AK		 4833
4834 len -= size;
4835 offset += size;
4836 count++;
bc7f75fa
AK		 4837 }
4838 }
4839
af667a29 4840 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4841 /* multiply data chunks by size of headers */
4842 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4843
bc7f75fa 4844 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4845 tx_ring->buffer_info[i].segs = segs;
4846 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4847 tx_ring->buffer_info[first].next_to_watch = i;
4848
4849 return count;
03b1320d
AD		 4850
4851dma_error:
af667a29 4852 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4853 buffer_info->dma = 0;
c1fa347f 4854 if (count)
03b1320d 4855 count--;
c1fa347f
RK		 4856
4857 while (count--) {
af667a29 4858 if (i == 0)
03b1320d 4859 i += tx_ring->count;
c1fa347f 4860 i--;
03b1320d 4861 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4862 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4863 }
4864
4865 return 0;
bc7f75fa
AK		 4866}
4867
55aa6985 4868static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4869{
55aa6985 4870 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4871 struct e1000_tx_desc *tx_desc = NULL;
4872 struct e1000_buffer *buffer_info;
4873 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4874 unsigned int i;
4875
4876 if (tx_flags & E1000_TX_FLAGS_TSO) {
4877 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4878 E1000_TXD_CMD_TSE;
4879 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4880
4881 if (tx_flags & E1000_TX_FLAGS_IPV4)
4882 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4883 }
4884
4885 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4886 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4887 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4888 }
4889
4890 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4891 txd_lower |= E1000_TXD_CMD_VLE;
4892 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4893 }
4894
943146de
BG		 4895 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4896 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4897
bc7f75fa
AK		 4898 i = tx_ring->next_to_use;
4899
36b973df 4900 do {
bc7f75fa
AK		 4901 buffer_info = &tx_ring->buffer_info[i];
4902 tx_desc = E1000_TX_DESC(*tx_ring, i);
4903 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4904 tx_desc->lower.data =
4905 cpu_to_le32(txd_lower | buffer_info->length);
4906 tx_desc->upper.data = cpu_to_le32(txd_upper);
4907
4908 i++;
4909 if (i == tx_ring->count)
4910 i = 0;
36b973df 4911 } while (--count > 0);
bc7f75fa
AK		 4912
4913 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4914
943146de
BG		 4915 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4916 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4917 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4918
ad68076e
BA		 4919 /*
4920 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4921 * know there are new descriptors to fetch. (Only
4922 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4923 * such as IA-64).
4924 */
bc7f75fa
AK		 4925 wmb();
4926
4927 tx_ring->next_to_use = i;
c6e7f51e
BA		 4928
4929 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4930 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4931 else
c5083cf6 4932 writel(i, tx_ring->tail);
c6e7f51e 4933
ad68076e
BA		 4934 /*
4935 * we need this if more than one processor can write to our tail
4936 * at a time, it synchronizes IO on IA64/Altix systems
4937 */
bc7f75fa
AK		 4938 mmiowb();
4939}
4940
4941#define MINIMUM_DHCP_PACKET_SIZE 282
4942static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4943 struct sk_buff *skb)
4944{
4945 struct e1000_hw *hw = &adapter->hw;
4946 u16 length, offset;
4947
4948 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4949 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4950 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4951 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4952 return 0;
4953 }
4954
4955 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4956 return 0;
4957
4958 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4959 return 0;
4960
4961 {
4962 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4963 struct udphdr *udp;
4964
4965 if (ip->protocol != IPPROTO_UDP)
4966 return 0;
4967
4968 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4969 if (ntohs(udp->dest) != 67)
4970 return 0;
4971
4972 offset = (u8 *)udp + 8 - skb->data;
4973 length = skb->len - offset;
4974 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4975 }
4976
4977 return 0;
4978}
4979
55aa6985 4980static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4981{
55aa6985 4982 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4983
55aa6985 4984 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4985 /*
4986 * Herbert's original patch had:
bc7f75fa 4987 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4988 * but since that doesn't exist yet, just open code it.
4989 */
bc7f75fa
AK		 4990 smp_mb();
4991
ad68076e
BA		 4992 /*
4993 * We need to check again in a case another CPU has just
4994 * made room available.
4995 */
55aa6985 4996 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4997 return -EBUSY;
4998
4999 /* A reprieve! */
55aa6985 5000 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5001 ++adapter->restart_queue;
5002 return 0;
5003}
5004
55aa6985 5005static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5006{
55aa6985 5007 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5008 return 0;
55aa6985 5009 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5010}
5011
0e15df49 5012#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 5013static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5014 struct net_device *netdev)
bc7f75fa
AK		 5015{
5016 struct e1000_adapter *adapter = netdev_priv(netdev);
5017 struct e1000_ring *tx_ring = adapter->tx_ring;
5018 unsigned int first;
5019 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5020 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5021 unsigned int tx_flags = 0;
e743d313 5022 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5023 unsigned int nr_frags;
5024 unsigned int mss;
bc7f75fa
AK		 5025 int count = 0;
5026 int tso;
5027 unsigned int f;
bc7f75fa
AK		 5028
5029 if (test_bit(__E1000_DOWN, &adapter->state)) {
5030 dev_kfree_skb_any(skb);
5031 return NETDEV_TX_OK;
5032 }
5033
5034 if (skb->len <= 0) {
5035 dev_kfree_skb_any(skb);
5036 return NETDEV_TX_OK;
5037 }
5038
5039 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5040 /*
5041 * The controller does a simple calculation to
bc7f75fa
AK		 5042 * make sure there is enough room in the FIFO before
5043 * initiating the DMA for each buffer. The calc is:
5044 * 4 = ceil(buffer len/mss). To make sure we don't
5045 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5046 * drops.
5047 */
bc7f75fa
AK		 5048 if (mss) {
5049 u8 hdr_len;
5050 max_per_txd = min(mss << 2, max_per_txd);
5051 max_txd_pwr = fls(max_per_txd) - 1;
5052
ad68076e
BA		 5053 /*
5054 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5055 * points to just header, pull a few bytes of payload from
5056 * frags into skb->data
5057 */
bc7f75fa 5058 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5059 /*
5060 * we do this workaround for ES2LAN, but it is un-necessary,
5061 * avoiding it could save a lot of cycles
5062 */
4e6c709c 5063 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5064 unsigned int pull_size;
5065
a2a5b323 5066 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5067 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5068 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5069 dev_kfree_skb_any(skb);
5070 return NETDEV_TX_OK;
5071 }
e743d313 5072 len = skb_headlen(skb);
bc7f75fa
AK		 5073 }
5074 }
5075
5076 /* reserve a descriptor for the offload context */
5077 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5078 count++;
5079 count++;
5080
5081 count += TXD_USE_COUNT(len, max_txd_pwr);
5082
5083 nr_frags = skb_shinfo(skb)->nr_frags;
5084 for (f = 0; f < nr_frags; f++)
9e903e08 5085 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5086 max_txd_pwr);
5087
5088 if (adapter->hw.mac.tx_pkt_filtering)
5089 e1000_transfer_dhcp_info(adapter, skb);
5090
ad68076e
BA		 5091 /*
5092 * need: count + 2 desc gap to keep tail from touching
5093 * head, otherwise try next time
5094 */
55aa6985 5095 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5096 return NETDEV_TX_BUSY;
bc7f75fa 5097
eab6d18d 5098 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5099 tx_flags |= E1000_TX_FLAGS_VLAN;
5100 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5101 }
5102
5103 first = tx_ring->next_to_use;
5104
55aa6985 5105 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5106 if (tso < 0) {
5107 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5108 return NETDEV_TX_OK;
5109 }
5110
5111 if (tso)
5112 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5113 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5114 tx_flags |= E1000_TX_FLAGS_CSUM;
5115
ad68076e
BA		 5116 /*
5117 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5118 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5119 * no longer assume, we must.
5120 */
bc7f75fa
AK		 5121 if (skb->protocol == htons(ETH_P_IP))
5122 tx_flags |= E1000_TX_FLAGS_IPV4;
5123
943146de
BG		 5124 if (unlikely(skb->no_fcs))
5125 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5126
25985edc 5127 /* if count is 0 then mapping error has occurred */
55aa6985 5128 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5129 if (count) {
3f0cfa3b 5130 netdev_sent_queue(netdev, skb->len);
55aa6985 5131 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5132 /* Make sure there is space in the ring for the next send. */
55aa6985 5133 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5134
5135 } else {
bc7f75fa 5136 dev_kfree_skb_any(skb);
1b7719c4
AD		 5137 tx_ring->buffer_info[first].time_stamp = 0;
5138 tx_ring->next_to_use = first;
bc7f75fa
AK		 5139 }
5140
bc7f75fa
AK		 5141 return NETDEV_TX_OK;
5142}
5143
5144/**
5145 * e1000_tx_timeout - Respond to a Tx Hang
5146 * @netdev: network interface device structure
5147 **/
5148static void e1000_tx_timeout(struct net_device *netdev)
5149{
5150 struct e1000_adapter *adapter = netdev_priv(netdev);
5151
5152 /* Do the reset outside of interrupt context */
5153 adapter->tx_timeout_count++;
5154 schedule_work(&adapter->reset_task);
5155}
5156
5157static void e1000_reset_task(struct work_struct *work)
5158{
5159 struct e1000_adapter *adapter;
5160 adapter = container_of(work, struct e1000_adapter, reset_task);
5161
615b32af
JB		 5162 /* don't run the task if already down */
5163 if (test_bit(__E1000_DOWN, &adapter->state))
5164 return;
5165
affa9dfb
CW		 5166 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5167 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5168 e1000e_dump(adapter);
5169 e_err("Reset adapter\n");
5170 }
bc7f75fa
AK		 5171 e1000e_reinit_locked(adapter);
5172}
5173
5174/**
67fd4fcb 5175 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5176 * @netdev: network interface device structure
67fd4fcb 5177 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5178 *
5179 * Returns the address of the device statistics structure.
bc7f75fa 5180 **/
67fd4fcb
JK		 5181struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5182 struct rtnl_link_stats64 *stats)
bc7f75fa 5183{
67fd4fcb
JK		 5184 struct e1000_adapter *adapter = netdev_priv(netdev);
5185
5186 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5187 spin_lock(&adapter->stats64_lock);
5188 e1000e_update_stats(adapter);
5189 /* Fill out the OS statistics structure */
5190 stats->rx_bytes = adapter->stats.gorc;
5191 stats->rx_packets = adapter->stats.gprc;
5192 stats->tx_bytes = adapter->stats.gotc;
5193 stats->tx_packets = adapter->stats.gptc;
5194 stats->multicast = adapter->stats.mprc;
5195 stats->collisions = adapter->stats.colc;
5196
5197 /* Rx Errors */
5198
5199 /*
5200 * RLEC on some newer hardware can be incorrect so build
5201 * our own version based on RUC and ROC
5202 */
5203 stats->rx_errors = adapter->stats.rxerrc +
5204 adapter->stats.crcerrs + adapter->stats.algnerrc +
5205 adapter->stats.ruc + adapter->stats.roc +
5206 adapter->stats.cexterr;
5207 stats->rx_length_errors = adapter->stats.ruc +
5208 adapter->stats.roc;
5209 stats->rx_crc_errors = adapter->stats.crcerrs;
5210 stats->rx_frame_errors = adapter->stats.algnerrc;
5211 stats->rx_missed_errors = adapter->stats.mpc;
5212
5213 /* Tx Errors */
5214 stats->tx_errors = adapter->stats.ecol +
5215 adapter->stats.latecol;
5216 stats->tx_aborted_errors = adapter->stats.ecol;
5217 stats->tx_window_errors = adapter->stats.latecol;
5218 stats->tx_carrier_errors = adapter->stats.tncrs;
5219
5220 /* Tx Dropped needs to be maintained elsewhere */
5221
5222 spin_unlock(&adapter->stats64_lock);
5223 return stats;
bc7f75fa
AK		 5224}
5225
5226/**
5227 * e1000_change_mtu - Change the Maximum Transfer Unit
5228 * @netdev: network interface device structure
5229 * @new_mtu: new value for maximum frame size
5230 *
5231 * Returns 0 on success, negative on failure
5232 **/
5233static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5234{
5235 struct e1000_adapter *adapter = netdev_priv(netdev);
5236 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5237
2adc55c9 5238 /* Jumbo frame support */
70495a50
BA		 5239 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5240 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5241 e_err("Jumbo Frames not supported.\n");
5242 return -EINVAL;
5243 }
5244
5245 /*
5246 * IP payload checksum (enabled with jumbos/packet-split when
5247 * Rx checksum is enabled) and generation of RSS hash is
5248 * mutually exclusive in the hardware.
5249 */
5250 if ((netdev->features & NETIF_F_RXCSUM) &&
5251 (netdev->features & NETIF_F_RXHASH)) {
5252 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5253 return -EINVAL;
5254 }
bc7f75fa
AK		 5255 }
5256
2adc55c9
BA		 5257 /* Supported frame sizes */
5258 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5259 (max_frame > adapter->max_hw_frame_size)) {
5260 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5261 return -EINVAL;
5262 }
5263
a1ce6473
BA		 5264 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5265 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5266 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5267 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5268 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5269 return -EINVAL;
5270 }
5271
6f461f6c
BA		 5272 /* 82573 Errata 17 */
5273 if (((adapter->hw.mac.type == e1000_82573) ||
5274 (adapter->hw.mac.type == e1000_82574)) &&
5275 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5276 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5277 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5278 }
5279
bc7f75fa 5280 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5281 usleep_range(1000, 2000);
610c9928 5282 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5283 adapter->max_frame_size = max_frame;
610c9928
BA		 5284 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5285 netdev->mtu = new_mtu;
bc7f75fa
AK		 5286 if (netif_running(netdev))
5287 e1000e_down(adapter);
5288
ad68076e
BA		 5289 /*
5290 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5291 * means we reserve 2 more, this pushes us to allocate from the next
5292 * larger slab size.
ad68076e 5293 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5294 * However with the new *_jumbo_rx* routines, jumbo receives will use
5295 * fragmented skbs
ad68076e 5296 */
bc7f75fa 5297
9926146b 5298 if (max_frame <= 2048)
bc7f75fa
AK		 5299 adapter->rx_buffer_len = 2048;
5300 else
5301 adapter->rx_buffer_len = 4096;
5302
5303 /* adjust allocation if LPE protects us, and we aren't using SBP */
5304 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5305 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5306 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5307 + ETH_FCS_LEN;
bc7f75fa 5308
bc7f75fa
AK		 5309 if (netif_running(netdev))
5310 e1000e_up(adapter);
5311 else
5312 e1000e_reset(adapter);
5313
5314 clear_bit(__E1000_RESETTING, &adapter->state);
5315
5316 return 0;
5317}
5318
5319static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5320 int cmd)
5321{
5322 struct e1000_adapter *adapter = netdev_priv(netdev);
5323 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5324
318a94d6 5325 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5326 return -EOPNOTSUPP;
5327
5328 switch (cmd) {
5329 case SIOCGMIIPHY:
5330 data->phy_id = adapter->hw.phy.addr;
5331 break;
5332 case SIOCGMIIREG:
b16a002e
BA		 5333 e1000_phy_read_status(adapter);
5334
7c25769f
BA		 5335 switch (data->reg_num & 0x1F) {
5336 case MII_BMCR:
5337 data->val_out = adapter->phy_regs.bmcr;
5338 break;
5339 case MII_BMSR:
5340 data->val_out = adapter->phy_regs.bmsr;
5341 break;
5342 case MII_PHYSID1:
5343 data->val_out = (adapter->hw.phy.id >> 16);
5344 break;
5345 case MII_PHYSID2:
5346 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5347 break;
5348 case MII_ADVERTISE:
5349 data->val_out = adapter->phy_regs.advertise;
5350 break;
5351 case MII_LPA:
5352 data->val_out = adapter->phy_regs.lpa;
5353 break;
5354 case MII_EXPANSION:
5355 data->val_out = adapter->phy_regs.expansion;
5356 break;
5357 case MII_CTRL1000:
5358 data->val_out = adapter->phy_regs.ctrl1000;
5359 break;
5360 case MII_STAT1000:
5361 data->val_out = adapter->phy_regs.stat1000;
5362 break;
5363 case MII_ESTATUS:
5364 data->val_out = adapter->phy_regs.estatus;
5365 break;
5366 default:
bc7f75fa
AK		 5367 return -EIO;
5368 }
bc7f75fa
AK		 5369 break;
5370 case SIOCSMIIREG:
5371 default:
5372 return -EOPNOTSUPP;
5373 }
5374 return 0;
5375}
5376
5377static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5378{
5379 switch (cmd) {
5380 case SIOCGMIIPHY:
5381 case SIOCGMIIREG:
5382 case SIOCSMIIREG:
5383 return e1000_mii_ioctl(netdev, ifr, cmd);
5384 default:
5385 return -EOPNOTSUPP;
5386 }
5387}
5388
a4f58f54
BA		 5389static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5390{
5391 struct e1000_hw *hw = &adapter->hw;
5392 u32 i, mac_reg;
2b6b168d 5393 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5394 int retval = 0;
5395
5396 /* copy MAC RARs to PHY RARs */
d3738bb8 5397 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5398
2b6b168d
BA		 5399 retval = hw->phy.ops.acquire(hw);
5400 if (retval) {
5401 e_err("Could not acquire PHY\n");
5402 return retval;
5403 }
5404
5405 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5406 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5407 if (retval)
75ce1532 5408 goto release;
2b6b168d
BA		 5409
5410 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5411 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5412 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5413 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5414 (u16)(mac_reg & 0xFFFF));
5415 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5416 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5417 }
5418
5419 /* configure PHY Rx Control register */
2b6b168d 5420 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5421 mac_reg = er32(RCTL);
5422 if (mac_reg & E1000_RCTL_UPE)
5423 phy_reg |= BM_RCTL_UPE;
5424 if (mac_reg & E1000_RCTL_MPE)
5425 phy_reg |= BM_RCTL_MPE;
5426 phy_reg &= ~(BM_RCTL_MO_MASK);
5427 if (mac_reg & E1000_RCTL_MO_3)
5428 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5429 << BM_RCTL_MO_SHIFT);
5430 if (mac_reg & E1000_RCTL_BAM)
5431 phy_reg |= BM_RCTL_BAM;
5432 if (mac_reg & E1000_RCTL_PMCF)
5433 phy_reg |= BM_RCTL_PMCF;
5434 mac_reg = er32(CTRL);
5435 if (mac_reg & E1000_CTRL_RFCE)
5436 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5437 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5438
5439 /* enable PHY wakeup in MAC register */
5440 ew32(WUFC, wufc);
5441 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5442
5443 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5444 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5445 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5446
5447 /* activate PHY wakeup */
2b6b168d
BA		 5448 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5449 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5450 if (retval)
5451 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5452release:
94d8186a 5453 hw->phy.ops.release(hw);
a4f58f54
BA		 5454
5455 return retval;
5456}
5457
23606cf5
RW		 5458static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5459 bool runtime)
bc7f75fa
AK		 5460{
5461 struct net_device *netdev = pci_get_drvdata(pdev);
5462 struct e1000_adapter *adapter = netdev_priv(netdev);
5463 struct e1000_hw *hw = &adapter->hw;
5464 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5465 /* Runtime suspend should only enable wakeup for link changes */
5466 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5467 int retval = 0;
5468
5469 netif_device_detach(netdev);
5470
5471 if (netif_running(netdev)) {
5472 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5473 e1000e_down(adapter);
5474 e1000_free_irq(adapter);
5475 }
4662e82b 5476 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5477
5478 retval = pci_save_state(pdev);
5479 if (retval)
5480 return retval;
5481
5482 status = er32(STATUS);
5483 if (status & E1000_STATUS_LU)
5484 wufc &= ~E1000_WUFC_LNKC;
5485
5486 if (wufc) {
5487 e1000_setup_rctl(adapter);
ef9b965a 5488 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5489
5490 /* turn on all-multi mode if wake on multicast is enabled */
5491 if (wufc & E1000_WUFC_MC) {
5492 rctl = er32(RCTL);
5493 rctl |= E1000_RCTL_MPE;
5494 ew32(RCTL, rctl);
5495 }
5496
5497 ctrl = er32(CTRL);
5498 /* advertise wake from D3Cold */
5499 #define E1000_CTRL_ADVD3WUC 0x00100000
5500 /* phy power management enable */
5501 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5502 ctrl |= E1000_CTRL_ADVD3WUC;
5503 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5504 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5505 ew32(CTRL, ctrl);
5506
318a94d6
JK		 5507 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5508 adapter->hw.phy.media_type ==
5509 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5510 /* keep the laser running in D3 */
5511 ctrl_ext = er32(CTRL_EXT);
93a23f48 5512 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5513 ew32(CTRL_EXT, ctrl_ext);
5514 }
5515
97ac8cae 5516 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5517 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5518
bc7f75fa
AK		 5519 /* Allow time for pending master requests to run */
5520 e1000e_disable_pcie_master(&adapter->hw);
5521
82776a4b 5522 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5523 /* enable wakeup by the PHY */
5524 retval = e1000_init_phy_wakeup(adapter, wufc);
5525 if (retval)
5526 return retval;
5527 } else {
5528 /* enable wakeup by the MAC */
5529 ew32(WUFC, wufc);
5530 ew32(WUC, E1000_WUC_PME_EN);
5531 }
bc7f75fa
AK		 5532 } else {
5533 ew32(WUC, 0);
5534 ew32(WUFC, 0);
bc7f75fa
AK		 5535 }
5536
4f9de721
RW		 5537 *enable_wake = !!wufc;
5538
bc7f75fa 5539 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5540 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5541 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5542 *enable_wake = true;
bc7f75fa
AK		 5543
5544 if (adapter->hw.phy.type == e1000_phy_igp_3)
5545 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5546
ad68076e
BA		 5547 /*
5548 * Release control of h/w to f/w. If f/w is AMT enabled, this
5549 * would have already happened in close and is redundant.
5550 */
31dbe5b4 5551 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5552
5553 pci_disable_device(pdev);
5554
4f9de721
RW		 5555 return 0;
5556}
5557
5558static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5559{
5560 if (sleep && wake) {
5561 pci_prepare_to_sleep(pdev);
5562 return;
5563 }
5564
5565 pci_wake_from_d3(pdev, wake);
5566 pci_set_power_state(pdev, PCI_D3hot);
5567}
5568
5569static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5570 bool wake)
5571{
5572 struct net_device *netdev = pci_get_drvdata(pdev);
5573 struct e1000_adapter *adapter = netdev_priv(netdev);
5574
005cbdfc
AD		 5575 /*
5576 * The pci-e switch on some quad port adapters will report a
5577 * correctable error when the MAC transitions from D0 to D3. To
5578 * prevent this we need to mask off the correctable errors on the
5579 * downstream port of the pci-e switch.
5580 */
5581 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5582 struct pci_dev *us_dev = pdev->bus->self;
353064de 5583 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5584 u16 devctl;
5585
5586 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5587 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5588 (devctl & ~PCI_EXP_DEVCTL_CERE));
5589
4f9de721 5590 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5591
5592 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5593 } else {
4f9de721 5594 e1000_power_off(pdev, sleep, wake);
005cbdfc 5595 }
bc7f75fa
AK		 5596}
5597
6f461f6c
BA		 5598#ifdef CONFIG_PCIEASPM
5599static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5600{
9f728f53 5601 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5602}
5603#else
5604static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5605{
5606 int pos;
6f461f6c 5607 u16 reg16;
1eae4eb2
AK		 5608
5609 /*
6f461f6c
BA		 5610 * Both device and parent should have the same ASPM setting.
5611 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5612 */
6f461f6c
BA		 5613 pos = pci_pcie_cap(pdev);
5614 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5615 reg16 &= ~state;
5616 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5617
0c75ba22
AB		 5618 if (!pdev->bus->self)
5619 return;
5620
6f461f6c
BA		 5621 pos = pci_pcie_cap(pdev->bus->self);
5622 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5623 reg16 &= ~state;
5624 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5625}
5626#endif
78cd29d5 5627static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5628{
5629 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5630 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5631 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5632
5633 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5634}
5635
aa338601 5636#ifdef CONFIG_PM
23606cf5 5637static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5638{
23606cf5 5639 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5640}
5641
23606cf5 5642static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5643{
5644 struct net_device *netdev = pci_get_drvdata(pdev);
5645 struct e1000_adapter *adapter = netdev_priv(netdev);
5646 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5647 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5648 u32 err;
5649
78cd29d5
BA		 5650 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5651 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5652 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5653 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5654 if (aspm_disable_flag)
5655 e1000e_disable_aspm(pdev, aspm_disable_flag);
5656
bc7f75fa
AK		 5657 pci_set_power_state(pdev, PCI_D0);
5658 pci_restore_state(pdev);
28b8f04a 5659 pci_save_state(pdev);
6e4f6f6b 5660
4662e82b 5661 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5662 if (netif_running(netdev)) {
5663 err = e1000_request_irq(adapter);
5664 if (err)
5665 return err;
5666 }
5667
99730e4c
BA		 5668 if (hw->mac.type == e1000_pch2lan)
5669 e1000_resume_workarounds_pchlan(&adapter->hw);
5670
bc7f75fa 5671 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5672
5673 /* report the system wakeup cause from S3/S4 */
5674 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5675 u16 phy_data;
5676
5677 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5678 if (phy_data) {
5679 e_info("PHY Wakeup cause - %s\n",
5680 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5681 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5682 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5683 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5684 phy_data & E1000_WUS_LNKC ?
5685 "Link Status Change" : "other");
a4f58f54
BA		 5686 }
5687 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5688 } else {
5689 u32 wus = er32(WUS);
5690 if (wus) {
5691 e_info("MAC Wakeup cause - %s\n",
5692 wus & E1000_WUS_EX ? "Unicast Packet" :
5693 wus & E1000_WUS_MC ? "Multicast Packet" :
5694 wus & E1000_WUS_BC ? "Broadcast Packet" :
5695 wus & E1000_WUS_MAG ? "Magic Packet" :
5696 wus & E1000_WUS_LNKC ? "Link Status Change" :
5697 "other");
5698 }
5699 ew32(WUS, ~0);
5700 }
5701
bc7f75fa 5702 e1000e_reset(adapter);
bc7f75fa 5703
cd791618 5704 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5705
5706 if (netif_running(netdev))
5707 e1000e_up(adapter);
5708
5709 netif_device_attach(netdev);
5710
ad68076e
BA		 5711 /*
5712 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5713 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5714 * under the control of the driver.
5715 */
c43bc57e 5716 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5717 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5718
5719 return 0;
5720}
23606cf5 5721
a0340162
RW		 5722#ifdef CONFIG_PM_SLEEP
5723static int e1000_suspend(struct device *dev)
5724{
5725 struct pci_dev *pdev = to_pci_dev(dev);
5726 int retval;
5727 bool wake;
5728
5729 retval = __e1000_shutdown(pdev, &wake, false);
5730 if (!retval)
5731 e1000_complete_shutdown(pdev, true, wake);
5732
5733 return retval;
5734}
5735
23606cf5
RW		 5736static int e1000_resume(struct device *dev)
5737{
5738 struct pci_dev *pdev = to_pci_dev(dev);
5739 struct net_device *netdev = pci_get_drvdata(pdev);
5740 struct e1000_adapter *adapter = netdev_priv(netdev);
5741
5742 if (e1000e_pm_ready(adapter))
5743 adapter->idle_check = true;
5744
5745 return __e1000_resume(pdev);
5746}
a0340162
RW		 5747#endif /* CONFIG_PM_SLEEP */
5748
5749#ifdef CONFIG_PM_RUNTIME
5750static int e1000_runtime_suspend(struct device *dev)
5751{
5752 struct pci_dev *pdev = to_pci_dev(dev);
5753 struct net_device *netdev = pci_get_drvdata(pdev);
5754 struct e1000_adapter *adapter = netdev_priv(netdev);
5755
5756 if (e1000e_pm_ready(adapter)) {
5757 bool wake;
5758
5759 __e1000_shutdown(pdev, &wake, true);
5760 }
5761
5762 return 0;
5763}
5764
5765static int e1000_idle(struct device *dev)
5766{
5767 struct pci_dev *pdev = to_pci_dev(dev);
5768 struct net_device *netdev = pci_get_drvdata(pdev);
5769 struct e1000_adapter *adapter = netdev_priv(netdev);
5770
5771 if (!e1000e_pm_ready(adapter))
5772 return 0;
5773
5774 if (adapter->idle_check) {
5775 adapter->idle_check = false;
5776 if (!e1000e_has_link(adapter))
5777 pm_schedule_suspend(dev, MSEC_PER_SEC);
5778 }
5779
5780 return -EBUSY;
5781}
23606cf5
RW		 5782
5783static int e1000_runtime_resume(struct device *dev)
5784{
5785 struct pci_dev *pdev = to_pci_dev(dev);
5786 struct net_device *netdev = pci_get_drvdata(pdev);
5787 struct e1000_adapter *adapter = netdev_priv(netdev);
5788
5789 if (!e1000e_pm_ready(adapter))
5790 return 0;
5791
5792 adapter->idle_check = !dev->power.runtime_auto;
5793 return __e1000_resume(pdev);
5794}
a0340162 5795#endif /* CONFIG_PM_RUNTIME */
aa338601 5796#endif /* CONFIG_PM */
bc7f75fa
AK		 5797
5798static void e1000_shutdown(struct pci_dev *pdev)
5799{
4f9de721
RW		 5800 bool wake = false;
5801
23606cf5 5802 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5803
5804 if (system_state == SYSTEM_POWER_OFF)
5805 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5806}
5807
5808#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5809
5810static irqreturn_t e1000_intr_msix(int irq, void *data)
5811{
5812 struct net_device *netdev = data;
5813 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5814
5815 if (adapter->msix_entries) {
90da0669
BA		 5816 int vector, msix_irq;
5817
147b2c8c
DD		 5818 vector = 0;
5819 msix_irq = adapter->msix_entries[vector].vector;
5820 disable_irq(msix_irq);
5821 e1000_intr_msix_rx(msix_irq, netdev);
5822 enable_irq(msix_irq);
5823
5824 vector++;
5825 msix_irq = adapter->msix_entries[vector].vector;
5826 disable_irq(msix_irq);
5827 e1000_intr_msix_tx(msix_irq, netdev);
5828 enable_irq(msix_irq);
5829
5830 vector++;
5831 msix_irq = adapter->msix_entries[vector].vector;
5832 disable_irq(msix_irq);
5833 e1000_msix_other(msix_irq, netdev);
5834 enable_irq(msix_irq);
5835 }
5836
5837 return IRQ_HANDLED;
5838}
5839
bc7f75fa
AK		 5840/*
5841 * Polling 'interrupt' - used by things like netconsole to send skbs
5842 * without having to re-enable interrupts. It's not called while
5843 * the interrupt routine is executing.
5844 */
5845static void e1000_netpoll(struct net_device *netdev)
5846{
5847 struct e1000_adapter *adapter = netdev_priv(netdev);
5848
147b2c8c
DD		 5849 switch (adapter->int_mode) {
5850 case E1000E_INT_MODE_MSIX:
5851 e1000_intr_msix(adapter->pdev->irq, netdev);
5852 break;
5853 case E1000E_INT_MODE_MSI:
5854 disable_irq(adapter->pdev->irq);
5855 e1000_intr_msi(adapter->pdev->irq, netdev);
5856 enable_irq(adapter->pdev->irq);
5857 break;
5858 default: /* E1000E_INT_MODE_LEGACY */
5859 disable_irq(adapter->pdev->irq);
5860 e1000_intr(adapter->pdev->irq, netdev);
5861 enable_irq(adapter->pdev->irq);
5862 break;
5863 }
bc7f75fa
AK		 5864}
5865#endif
5866
5867/**
5868 * e1000_io_error_detected - called when PCI error is detected
5869 * @pdev: Pointer to PCI device
5870 * @state: The current pci connection state
5871 *
5872 * This function is called after a PCI bus error affecting
5873 * this device has been detected.
5874 */
5875static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5876 pci_channel_state_t state)
5877{
5878 struct net_device *netdev = pci_get_drvdata(pdev);
5879 struct e1000_adapter *adapter = netdev_priv(netdev);
5880
5881 netif_device_detach(netdev);
5882
c93b5a76
MM		 5883 if (state == pci_channel_io_perm_failure)
5884 return PCI_ERS_RESULT_DISCONNECT;
5885
bc7f75fa
AK		 5886 if (netif_running(netdev))
5887 e1000e_down(adapter);
5888 pci_disable_device(pdev);
5889
5890 /* Request a slot slot reset. */
5891 return PCI_ERS_RESULT_NEED_RESET;
5892}
5893
5894/**
5895 * e1000_io_slot_reset - called after the pci bus has been reset.
5896 * @pdev: Pointer to PCI device
5897 *
5898 * Restart the card from scratch, as if from a cold-boot. Implementation
5899 * resembles the first-half of the e1000_resume routine.
5900 */
5901static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5902{
5903 struct net_device *netdev = pci_get_drvdata(pdev);
5904 struct e1000_adapter *adapter = netdev_priv(netdev);
5905 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5906 u16 aspm_disable_flag = 0;
6e4f6f6b 5907 int err;
111b9dc5 5908 pci_ers_result_t result;
bc7f75fa 5909
78cd29d5
BA		 5910 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5911 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5912 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5913 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5914 if (aspm_disable_flag)
5915 e1000e_disable_aspm(pdev, aspm_disable_flag);
5916
f0f422e5 5917 err = pci_enable_device_mem(pdev);
6e4f6f6b 5918 if (err) {
bc7f75fa
AK		 5919 dev_err(&pdev->dev,
5920 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5921 result = PCI_ERS_RESULT_DISCONNECT;
5922 } else {
5923 pci_set_master(pdev);
23606cf5 5924 pdev->state_saved = true;
111b9dc5 5925 pci_restore_state(pdev);
bc7f75fa 5926
111b9dc5
JB		 5927 pci_enable_wake(pdev, PCI_D3hot, 0);
5928 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5929
111b9dc5
JB		 5930 e1000e_reset(adapter);
5931 ew32(WUS, ~0);
5932 result = PCI_ERS_RESULT_RECOVERED;
5933 }
bc7f75fa 5934
111b9dc5
JB		 5935 pci_cleanup_aer_uncorrect_error_status(pdev);
5936
5937 return result;
bc7f75fa
AK		 5938}
5939
5940/**
5941 * e1000_io_resume - called when traffic can start flowing again.
5942 * @pdev: Pointer to PCI device
5943 *
5944 * This callback is called when the error recovery driver tells us that
5945 * its OK to resume normal operation. Implementation resembles the
5946 * second-half of the e1000_resume routine.
5947 */
5948static void e1000_io_resume(struct pci_dev *pdev)
5949{
5950 struct net_device *netdev = pci_get_drvdata(pdev);
5951 struct e1000_adapter *adapter = netdev_priv(netdev);
5952
cd791618 5953 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5954
5955 if (netif_running(netdev)) {
5956 if (e1000e_up(adapter)) {
5957 dev_err(&pdev->dev,
5958 "can't bring device back up after reset\n");
5959 return;
5960 }
5961 }
5962
5963 netif_device_attach(netdev);
5964
ad68076e
BA		 5965 /*
5966 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5967 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5968 * under the control of the driver.
5969 */
c43bc57e 5970 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5971 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5972
5973}
5974
5975static void e1000_print_device_info(struct e1000_adapter *adapter)
5976{
5977 struct e1000_hw *hw = &adapter->hw;
5978 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5979 u32 ret_val;
5980 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5981
5982 /* print bus type/speed/width info */
a5cc7642 5983 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5984 /* bus width */
5985 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5986 "Width x1"),
5987 /* MAC address */
7c510e4b 5988 netdev->dev_addr);
44defeb3
JK		 5989 e_info("Intel(R) PRO/%s Network Connection\n",
5990 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5991 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5992 E1000_PBANUM_LENGTH);
5993 if (ret_val)
f2315bf1 5994 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5995 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5996 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5997}
5998
10aa4c04
AK		 5999static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6000{
6001 struct e1000_hw *hw = &adapter->hw;
6002 int ret_val;
6003 u16 buf = 0;
6004
6005 if (hw->mac.type != e1000_82573)
6006 return;
6007
6008 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6009 le16_to_cpus(&buf);
6010 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6011 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6012 dev_warn(&adapter->pdev->dev,
6013 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6014 }
10aa4c04
AK		 6015}
6016
c8f44aff 6017static int e1000_set_features(struct net_device *netdev,
70495a50 6018 netdev_features_t features)
dc221294
BA		 6019{
6020 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6021 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6022
6023 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6024 adapter->flags |= FLAG_TSO_FORCE;
6025
6026 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6027 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6028 NETIF_F_RXALL)))
dc221294
BA		 6029 return 0;
6030
70495a50
BA		 6031 /*
6032 * IP payload checksum (enabled with jumbos/packet-split when Rx
6033 * checksum is enabled) and generation of RSS hash is mutually
6034 * exclusive in the hardware.
6035 */
6036 if (adapter->rx_ps_pages &&
6037 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6038 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6039 return -EINVAL;
6040 }
6041
0184039a
BG		 6042 if (changed & NETIF_F_RXFCS) {
6043 if (features & NETIF_F_RXFCS) {
6044 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6045 } else {
6046 /* We need to take it back to defaults, which might mean
6047 * stripping is still disabled at the adapter level.
6048 */
6049 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6050 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6051 else
6052 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6053 }
6054 }
6055
70495a50
BA		 6056 netdev->features = features;
6057
dc221294
BA		 6058 if (netif_running(netdev))
6059 e1000e_reinit_locked(adapter);
6060 else
6061 e1000e_reset(adapter);
6062
6063 return 0;
6064}
6065
651c2466
SH		 6066static const struct net_device_ops e1000e_netdev_ops = {
6067 .ndo_open = e1000_open,
6068 .ndo_stop = e1000_close,
00829823 6069 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6070 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6071 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6072 .ndo_set_mac_address = e1000_set_mac,
6073 .ndo_change_mtu = e1000_change_mtu,
6074 .ndo_do_ioctl = e1000_ioctl,
6075 .ndo_tx_timeout = e1000_tx_timeout,
6076 .ndo_validate_addr = eth_validate_addr,
6077
651c2466
SH		 6078 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6079 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6080#ifdef CONFIG_NET_POLL_CONTROLLER
6081 .ndo_poll_controller = e1000_netpoll,
6082#endif
dc221294 6083 .ndo_set_features = e1000_set_features,
651c2466
SH		 6084};
6085
bc7f75fa
AK		 6086/**
6087 * e1000_probe - Device Initialization Routine
6088 * @pdev: PCI device information struct
6089 * @ent: entry in e1000_pci_tbl
6090 *
6091 * Returns 0 on success, negative on failure
6092 *
6093 * e1000_probe initializes an adapter identified by a pci_dev structure.
6094 * The OS initialization, configuring of the adapter private structure,
6095 * and a hardware reset occur.
6096 **/
6097static int __devinit e1000_probe(struct pci_dev *pdev,
6098 const struct pci_device_id *ent)
6099{
6100 struct net_device *netdev;
6101 struct e1000_adapter *adapter;
6102 struct e1000_hw *hw;
6103 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6104 resource_size_t mmio_start, mmio_len;
6105 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 6106
6107 static int cards_found;
78cd29d5 6108 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6109 int i, err, pci_using_dac;
6110 u16 eeprom_data = 0;
6111 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6112
78cd29d5
BA		 6113 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6114 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6115 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6116 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6117 if (aspm_disable_flag)
6118 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6119
f0f422e5 6120 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6121 if (err)
6122 return err;
6123
6124 pci_using_dac = 0;
0be3f55f 6125 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6126 if (!err) {
0be3f55f 6127 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6128 if (!err)
6129 pci_using_dac = 1;
6130 } else {
0be3f55f 6131 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6132 if (err) {
0be3f55f
NN		 6133 err = dma_set_coherent_mask(&pdev->dev,
6134 DMA_BIT_MASK(32));
bc7f75fa 6135 if (err) {
ef456f85 6136 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6137 goto err_dma;
6138 }
6139 }
6140 }
6141
e8de1481 6142 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6143 pci_select_bars(pdev, IORESOURCE_MEM),
6144 e1000e_driver_name);
bc7f75fa
AK		 6145 if (err)
6146 goto err_pci_reg;
6147
68eac460 6148 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6149 pci_enable_pcie_error_reporting(pdev);
68eac460 6150
bc7f75fa 6151 pci_set_master(pdev);
438b365a
BA		 6152 /* PCI config space info */
6153 err = pci_save_state(pdev);
6154 if (err)
6155 goto err_alloc_etherdev;
bc7f75fa
AK		 6156
6157 err = -ENOMEM;
6158 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6159 if (!netdev)
6160 goto err_alloc_etherdev;
6161
bc7f75fa
AK		 6162 SET_NETDEV_DEV(netdev, &pdev->dev);
6163
f85e4dfa
TH		 6164 netdev->irq = pdev->irq;
6165
bc7f75fa
AK		 6166 pci_set_drvdata(pdev, netdev);
6167 adapter = netdev_priv(netdev);
6168 hw = &adapter->hw;
6169 adapter->netdev = netdev;
6170 adapter->pdev = pdev;
6171 adapter->ei = ei;
6172 adapter->pba = ei->pba;
6173 adapter->flags = ei->flags;
eb7c3adb 6174 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6175 adapter->hw.adapter = adapter;
6176 adapter->hw.mac.type = ei->mac;
2adc55c9 6177 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6178 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6179
6180 mmio_start = pci_resource_start(pdev, 0);
6181 mmio_len = pci_resource_len(pdev, 0);
6182
6183 err = -EIO;
6184 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6185 if (!adapter->hw.hw_addr)
6186 goto err_ioremap;
6187
6188 if ((adapter->flags & FLAG_HAS_FLASH) &&
6189 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6190 flash_start = pci_resource_start(pdev, 1);
6191 flash_len = pci_resource_len(pdev, 1);
6192 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6193 if (!adapter->hw.flash_address)
6194 goto err_flashmap;
6195 }
6196
6197 /* construct the net_device struct */
651c2466 6198 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6199 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6200 netdev->watchdog_timeo = 5 * HZ;
6201 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
f2315bf1 6202 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6203
6204 netdev->mem_start = mmio_start;
6205 netdev->mem_end = mmio_start + mmio_len;
6206
6207 adapter->bd_number = cards_found++;
6208
4662e82b
BA		 6209 e1000e_check_options(adapter);
6210
bc7f75fa
AK		 6211 /* setup adapter struct */
6212 err = e1000_sw_init(adapter);
6213 if (err)
6214 goto err_sw_init;
6215
bc7f75fa
AK		 6216 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6217 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6218 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6219
69e3fd8c 6220 err = ei->get_variants(adapter);
bc7f75fa
AK		 6221 if (err)
6222 goto err_hw_init;
6223
4a770358
BA		 6224 if ((adapter->flags & FLAG_IS_ICH) &&
6225 (adapter->flags & FLAG_READ_ONLY_NVM))
6226 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6227
bc7f75fa
AK		 6228 hw->mac.ops.get_bus_info(&adapter->hw);
6229
318a94d6 6230 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6231
6232 /* Copper options */
318a94d6 6233 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6234 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6235 adapter->hw.phy.disable_polarity_correction = 0;
6236 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6237 }
6238
44abd5c1 6239 if (hw->phy.ops.check_reset_block(hw))
44defeb3 6240 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6241
dc221294
BA		 6242 /* Set initial default active device features */
6243 netdev->features = (NETIF_F_SG |
6244 NETIF_F_HW_VLAN_RX |
6245 NETIF_F_HW_VLAN_TX |
6246 NETIF_F_TSO |
6247 NETIF_F_TSO6 |
70495a50 6248 NETIF_F_RXHASH |
dc221294
BA		 6249 NETIF_F_RXCSUM |
6250 NETIF_F_HW_CSUM);
6251
6252 /* Set user-changeable features (subset of all device features) */
6253 netdev->hw_features = netdev->features;
0184039a 6254 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6255 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6256 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6257
6258 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6259 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6260
dc221294
BA		 6261 netdev->vlan_features |= (NETIF_F_SG |
6262 NETIF_F_TSO |
6263 NETIF_F_TSO6 |
6264 NETIF_F_HW_CSUM);
a5136e23 6265
ef9b965a
JB		 6266 netdev->priv_flags |= IFF_UNICAST_FLT;
6267
7b872a55 6268 if (pci_using_dac) {
bc7f75fa 6269 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6270 netdev->vlan_features |= NETIF_F_HIGHDMA;
6271 }
bc7f75fa 6272
bc7f75fa
AK		 6273 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6274 adapter->flags |= FLAG_MNG_PT_ENABLED;
6275
ad68076e
BA		 6276 /*
6277 * before reading the NVM, reset the controller to
6278 * put the device in a known good starting state
6279 */
bc7f75fa
AK		 6280 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6281
6282 /*
6283 * systems with ASPM and others may see the checksum fail on the first
6284 * attempt. Let's give it a few tries
6285 */
6286 for (i = 0;; i++) {
6287 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6288 break;
6289 if (i == 2) {
44defeb3 6290 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6291 err = -EIO;
6292 goto err_eeprom;
6293 }
6294 }
6295
10aa4c04
AK		 6296 e1000_eeprom_checks(adapter);
6297
608f8a0d 6298 /* copy the MAC address */
bc7f75fa 6299 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6300 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6301
6302 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6303 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6304
6305 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6306 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6307 err = -EIO;
6308 goto err_eeprom;
6309 }
6310
6311 init_timer(&adapter->watchdog_timer);
c061b18d 6312 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6313 adapter->watchdog_timer.data = (unsigned long) adapter;
6314
6315 init_timer(&adapter->phy_info_timer);
c061b18d 6316 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6317 adapter->phy_info_timer.data = (unsigned long) adapter;
6318
6319 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6320 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6321 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6322 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6323 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6324
bc7f75fa
AK		 6325 /* Initialize link parameters. User can change them with ethtool */
6326 adapter->hw.mac.autoneg = 1;
3db1cd5c 6327 adapter->fc_autoneg = true;
5c48ef3e
BA		 6328 adapter->hw.fc.requested_mode = e1000_fc_default;
6329 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6330 adapter->hw.phy.autoneg_advertised = 0x2f;
6331
6332 /* ring size defaults */
6333 adapter->rx_ring->count = 256;
6334 adapter->tx_ring->count = 256;
6335
6336 /*
6337 * Initial Wake on LAN setting - If APM wake is enabled in
6338 * the EEPROM, enable the ACPI Magic Packet filter
6339 */
6340 if (adapter->flags & FLAG_APME_IN_WUC) {
6341 /* APME bit in EEPROM is mapped to WUC.APME */
6342 eeprom_data = er32(WUC);
6343 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6344 if ((hw->mac.type > e1000_ich10lan) &&
6345 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6346 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6347 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6348 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6349 (adapter->hw.bus.func == 1))
6350 e1000_read_nvm(&adapter->hw,
6351 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6352 else
6353 e1000_read_nvm(&adapter->hw,
6354 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6355 }
6356
6357 /* fetch WoL from EEPROM */
6358 if (eeprom_data & eeprom_apme_mask)
6359 adapter->eeprom_wol |= E1000_WUFC_MAG;
6360
6361 /*
6362 * now that we have the eeprom settings, apply the special cases
6363 * where the eeprom may be wrong or the board simply won't support
6364 * wake on lan on a particular port
6365 */
6366 if (!(adapter->flags & FLAG_HAS_WOL))
6367 adapter->eeprom_wol = 0;
6368
6369 /* initialize the wol settings based on the eeprom settings */
6370 adapter->wol = adapter->eeprom_wol;
6ff68026 6371 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6372
84527590
BA		 6373 /* save off EEPROM version number */
6374 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6375
bc7f75fa
AK		 6376 /* reset the hardware with the new settings */
6377 e1000e_reset(adapter);
6378
ad68076e
BA		 6379 /*
6380 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6381 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6382 * under the control of the driver.
6383 */
c43bc57e 6384 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6385 e1000e_get_hw_control(adapter);
bc7f75fa 6386
f2315bf1 6387 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6388 err = register_netdev(netdev);
6389 if (err)
6390 goto err_register;
6391
9c563d20
JB		 6392 /* carrier off reporting is important to ethtool even BEFORE open */
6393 netif_carrier_off(netdev);
6394
bc7f75fa
AK		 6395 e1000_print_device_info(adapter);
6396
f3ec4f87
AS		 6397 if (pci_dev_run_wake(pdev))
6398 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6399
bc7f75fa
AK		 6400 return 0;
6401
6402err_register:
c43bc57e 6403 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6404 e1000e_release_hw_control(adapter);
bc7f75fa 6405err_eeprom:
44abd5c1 6406 if (!hw->phy.ops.check_reset_block(hw))
bc7f75fa 6407 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6408err_hw_init:
bc7f75fa
AK		 6409 kfree(adapter->tx_ring);
6410 kfree(adapter->rx_ring);
6411err_sw_init:
c43bc57e
JB		 6412 if (adapter->hw.flash_address)
6413 iounmap(adapter->hw.flash_address);
e82f54ba 6414 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6415err_flashmap:
bc7f75fa
AK		 6416 iounmap(adapter->hw.hw_addr);
6417err_ioremap:
6418 free_netdev(netdev);
6419err_alloc_etherdev:
f0f422e5
BA		 6420 pci_release_selected_regions(pdev,
6421 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6422err_pci_reg:
6423err_dma:
6424 pci_disable_device(pdev);
6425 return err;
6426}
6427
6428/**
6429 * e1000_remove - Device Removal Routine
6430 * @pdev: PCI device information struct
6431 *
6432 * e1000_remove is called by the PCI subsystem to alert the driver
6433 * that it should release a PCI device. The could be caused by a
6434 * Hot-Plug event, or because the driver is going to be removed from
6435 * memory.
6436 **/
6437static void __devexit e1000_remove(struct pci_dev *pdev)
6438{
6439 struct net_device *netdev = pci_get_drvdata(pdev);
6440 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6441 bool down = test_bit(__E1000_DOWN, &adapter->state);
6442
ad68076e 6443 /*
23f333a2
TH		 6444 * The timers may be rescheduled, so explicitly disable them
6445 * from being rescheduled.
ad68076e 6446 */
23606cf5
RW		 6447 if (!down)
6448 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6449 del_timer_sync(&adapter->watchdog_timer);
6450 del_timer_sync(&adapter->phy_info_timer);
6451
41cec6f1
BA		 6452 cancel_work_sync(&adapter->reset_task);
6453 cancel_work_sync(&adapter->watchdog_task);
6454 cancel_work_sync(&adapter->downshift_task);
6455 cancel_work_sync(&adapter->update_phy_task);
6456 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6457
17f208de
BA		 6458 if (!(netdev->flags & IFF_UP))
6459 e1000_power_down_phy(adapter);
6460
23606cf5
RW		 6461 /* Don't lie to e1000_close() down the road. */
6462 if (!down)
6463 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6464 unregister_netdev(netdev);
6465
f3ec4f87
AS		 6466 if (pci_dev_run_wake(pdev))
6467 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6468
ad68076e
BA		 6469 /*
6470 * Release control of h/w to f/w. If f/w is AMT enabled, this
6471 * would have already happened in close and is redundant.
6472 */
31dbe5b4 6473 e1000e_release_hw_control(adapter);
bc7f75fa 6474
4662e82b 6475 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6476 kfree(adapter->tx_ring);
6477 kfree(adapter->rx_ring);
6478
6479 iounmap(adapter->hw.hw_addr);
6480 if (adapter->hw.flash_address)
6481 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6482 pci_release_selected_regions(pdev,
6483 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6484
6485 free_netdev(netdev);
6486
111b9dc5 6487 /* AER disable */
19d5afd4 6488 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6489
bc7f75fa
AK		 6490 pci_disable_device(pdev);
6491}
6492
6493/* PCI Error Recovery (ERS) */
6494static struct pci_error_handlers e1000_err_handler = {
6495 .error_detected = e1000_io_error_detected,
6496 .slot_reset = e1000_io_slot_reset,
6497 .resume = e1000_io_resume,
6498};
6499
a3aa1884 6500static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6510
bc7f75fa
AK		 6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6515
bc7f75fa
AK		 6516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6519
4662e82b 6520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6523
bc7f75fa
AK		 6524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6525 board_80003es2lan },
6526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6527 board_80003es2lan },
6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6529 board_80003es2lan },
6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6531 board_80003es2lan },
ad68076e 6532
bc7f75fa
AK		 6533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6537 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6541
bc7f75fa
AK		 6542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6551
6552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6555
f4187b56
BA		 6556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6559
a4f58f54
BA		 6560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6561 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6564
d3738bb8
BA		 6565 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6566 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6567
f36bb6ca 6568 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6569};
6570MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6571
aa338601 6572#ifdef CONFIG_PM
23606cf5 6573static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6574 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6575 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6576 e1000_runtime_resume, e1000_idle)
23606cf5 6577};
e50208a0 6578#endif
23606cf5 6579
bc7f75fa
AK		 6580/* PCI Device API Driver */
6581static struct pci_driver e1000_driver = {
6582 .name = e1000e_driver_name,
6583 .id_table = e1000_pci_tbl,
6584 .probe = e1000_probe,
6585 .remove = __devexit_p(e1000_remove),
aa338601 6586#ifdef CONFIG_PM
f36bb6ca
BA		 6587 .driver = {
6588 .pm = &e1000_pm_ops,
6589 },
bc7f75fa
AK		 6590#endif
6591 .shutdown = e1000_shutdown,
6592 .err_handler = &e1000_err_handler
6593};
6594
6595/**
6596 * e1000_init_module - Driver Registration Routine
6597 *
6598 * e1000_init_module is the first routine called when the driver is
6599 * loaded. All it does is register with the PCI subsystem.
6600 **/
6601static int __init e1000_init_module(void)
6602{
6603 int ret;
8544b9f7
BA		 6604 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6605 e1000e_driver_version);
f5e261e6 6606 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6607 ret = pci_register_driver(&e1000_driver);
53ec5498 6608
bc7f75fa
AK		 6609 return ret;
6610}
6611module_init(e1000_init_module);
6612
6613/**
6614 * e1000_exit_module - Driver Exit Cleanup Routine
6615 *
6616 * e1000_exit_module is called just before the driver is removed
6617 * from memory.
6618 **/
6619static void __exit e1000_exit_module(void)
6620{
6621 pci_unregister_driver(&e1000_driver);
6622}
6623module_exit(e1000_exit_module);
6624
6625
6626MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6627MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6628MODULE_LICENSE("GPL");
6629MODULE_VERSION(DRV_VERSION);
6630
06c24b91 6631/* netdev.c */
Linux kernel - Deliverables
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