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i40e: Use DEBUG_FD message level for an FD message
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
8defe713 51#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 73};
74
84f4ee90
TI		 75struct e1000_reg_info {
76 u32 ofs;
77 char *name;
78};
79
84f4ee90 80static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 81 /* General Registers */
82 {E1000_CTRL, "CTRL"},
83 {E1000_STATUS, "STATUS"},
84 {E1000_CTRL_EXT, "CTRL_EXT"},
85
86 /* Interrupt Registers */
87 {E1000_ICR, "ICR"},
88
af667a29 89 /* Rx Registers */
84f4ee90 90 {E1000_RCTL, "RCTL"},
1e36052e
BA		 91 {E1000_RDLEN(0), "RDLEN"},
92 {E1000_RDH(0), "RDH"},
93 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 94 {E1000_RDTR, "RDTR"},
95 {E1000_RXDCTL(0), "RXDCTL"},
96 {E1000_ERT, "ERT"},
1e36052e
BA		 97 {E1000_RDBAL(0), "RDBAL"},
98 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 99 {E1000_RDFH, "RDFH"},
100 {E1000_RDFT, "RDFT"},
101 {E1000_RDFHS, "RDFHS"},
102 {E1000_RDFTS, "RDFTS"},
103 {E1000_RDFPC, "RDFPC"},
104
af667a29 105 /* Tx Registers */
84f4ee90 106 {E1000_TCTL, "TCTL"},
1e36052e
BA		 107 {E1000_TDBAL(0), "TDBAL"},
108 {E1000_TDBAH(0), "TDBAH"},
109 {E1000_TDLEN(0), "TDLEN"},
110 {E1000_TDH(0), "TDH"},
111 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 112 {E1000_TIDV, "TIDV"},
113 {E1000_TXDCTL(0), "TXDCTL"},
114 {E1000_TADV, "TADV"},
115 {E1000_TARC(0), "TARC"},
116 {E1000_TDFH, "TDFH"},
117 {E1000_TDFT, "TDFT"},
118 {E1000_TDFHS, "TDFHS"},
119 {E1000_TDFTS, "TDFTS"},
120 {E1000_TDFPC, "TDFPC"},
121
122 /* List Terminator */
f36bb6ca 123 {0, NULL}
84f4ee90
TI		 124};
125
e921eb1a 126/**
84f4ee90 127 * e1000_regdump - register printout routine
e921eb1a
BA		 128 * @hw: pointer to the HW structure
129 * @reginfo: pointer to the register info table
130 **/
84f4ee90
TI		 131static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
132{
133 int n = 0;
134 char rname[16];
135 u32 regs[8];
136
137 switch (reginfo->ofs) {
138 case E1000_RXDCTL(0):
139 for (n = 0; n < 2; n++)
140 regs[n] = __er32(hw, E1000_RXDCTL(n));
141 break;
142 case E1000_TXDCTL(0):
143 for (n = 0; n < 2; n++)
144 regs[n] = __er32(hw, E1000_TXDCTL(n));
145 break;
146 case E1000_TARC(0):
147 for (n = 0; n < 2; n++)
148 regs[n] = __er32(hw, E1000_TARC(n));
149 break;
150 default:
ef456f85
JK		 151 pr_info("%-15s %08x\n",
152 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 153 return;
154 }
155
156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 158}
159
f0c5dadf
ET		 160static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
161 struct e1000_buffer *bi)
162{
163 int i;
164 struct e1000_ps_page *ps_page;
165
166 for (i = 0; i < adapter->rx_ps_pages; i++) {
167 ps_page = &bi->ps_pages[i];
168
169 if (ps_page->page) {
170 pr_info("packet dump for ps_page %d:\n", i);
171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
172 16, 1, page_address(ps_page->page),
173 PAGE_SIZE, true);
174 }
175 }
176}
177
e921eb1a 178/**
af667a29 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 180 * @adapter: board private structure
181 **/
84f4ee90
TI		 182static void e1000e_dump(struct e1000_adapter *adapter)
183{
184 struct net_device *netdev = adapter->netdev;
185 struct e1000_hw *hw = &adapter->hw;
186 struct e1000_reg_info *reginfo;
187 struct e1000_ring *tx_ring = adapter->tx_ring;
188 struct e1000_tx_desc *tx_desc;
af667a29 189 struct my_u0 {
e885d762
BA		 190 __le64 a;
191 __le64 b;
af667a29 192 } *u0;
84f4ee90
TI		 193 struct e1000_buffer *buffer_info;
194 struct e1000_ring *rx_ring = adapter->rx_ring;
195 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 196 union e1000_rx_desc_extended *rx_desc;
af667a29 197 struct my_u1 {
e885d762
BA		 198 __le64 a;
199 __le64 b;
200 __le64 c;
201 __le64 d;
af667a29 202 } *u1;
84f4ee90
TI		 203 u32 staterr;
204 int i = 0;
205
206 if (!netif_msg_hw(adapter))
207 return;
208
209 /* Print netdevice Info */
210 if (netdev) {
211 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 212 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
214 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 215 }
216
217 /* Print Registers */
218 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 219 pr_info(" Register Name Value\n");
84f4ee90
TI		 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
221 reginfo->name; reginfo++) {
222 e1000_regdump(hw, reginfo);
223 }
224
af667a29 225 /* Print Tx Ring Summary */
84f4ee90 226 if (!netdev || !netif_running(netdev))
fe1e980f 227 return;
84f4ee90 228
af667a29 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
233 0, tx_ring->next_to_use, tx_ring->next_to_clean,
234 (unsigned long long)buffer_info->dma,
235 buffer_info->length,
236 buffer_info->next_to_watch,
237 (unsigned long long)buffer_info->time_stamp);
84f4ee90 238
af667a29 239 /* Print Tx Ring */
84f4ee90
TI		 240 if (!netif_msg_tx_done(adapter))
241 goto rx_ring_summary;
242
af667a29 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 244
245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
246 *
247 * Legacy Transmit Descriptor
248 * +--------------------------------------------------------------+
249 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
250 * +--------------------------------------------------------------+
251 * 8 | Special | CSS | Status | CMD | CSO | Length |
252 * +--------------------------------------------------------------+
253 * 63 48 47 36 35 32 31 24 23 16 15 0
254 *
255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
256 * 63 48 47 40 39 32 31 16 15 8 7 0
257 * +----------------------------------------------------------------+
258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
259 * +----------------------------------------------------------------+
260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
261 * +----------------------------------------------------------------+
262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
263 *
264 * Extended Data Descriptor (DTYP=0x1)
265 * +----------------------------------------------------------------+
266 * 0 | Buffer Address [63:0] |
267 * +----------------------------------------------------------------+
268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 */
ef456f85
JK		 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 276 const char *next_desc;
84f4ee90
TI		 277 tx_desc = E1000_TX_DESC(*tx_ring, i);
278 buffer_info = &tx_ring->buffer_info[i];
279 u0 = (struct my_u0 *)tx_desc;
84f4ee90 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 281 next_desc = " NTC/U";
84f4ee90 282 else if (i == tx_ring->next_to_use)
ef456f85 283 next_desc = " NTU";
84f4ee90 284 else if (i == tx_ring->next_to_clean)
ef456f85 285 next_desc = " NTC";
84f4ee90 286 else
ef456f85
JK		 287 next_desc = "";
288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
291 i,
292 (unsigned long long)le64_to_cpu(u0->a),
293 (unsigned long long)le64_to_cpu(u0->b),
294 (unsigned long long)buffer_info->dma,
295 buffer_info->length, buffer_info->next_to_watch,
296 (unsigned long long)buffer_info->time_stamp,
297 buffer_info->skb, next_desc);
84f4ee90 298
f0c5dadf 299 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 301 16, 1, buffer_info->skb->data,
302 buffer_info->skb->len, true);
84f4ee90
TI		 303 }
304
af667a29 305 /* Print Rx Ring Summary */
84f4ee90 306rx_ring_summary:
af667a29 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 308 pr_info("Queue [NTU] [NTC]\n");
309 pr_info(" %5d %5X %5X\n",
310 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 311
af667a29 312 /* Print Rx Ring */
84f4ee90 313 if (!netif_msg_rx_status(adapter))
fe1e980f 314 return;
84f4ee90 315
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 317 switch (adapter->rx_ps_pages) {
318 case 1:
319 case 2:
320 case 3:
321 /* [Extended] Packet Split Receive Descriptor Format
322 *
323 * +-----------------------------------------------------+
324 * 0 | Buffer Address 0 [63:0] |
325 * +-----------------------------------------------------+
326 * 8 | Buffer Address 1 [63:0] |
327 * +-----------------------------------------------------+
328 * 16 | Buffer Address 2 [63:0] |
329 * +-----------------------------------------------------+
330 * 24 | Buffer Address 3 [63:0] |
331 * +-----------------------------------------------------+
332 */
ef456f85 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 334 /* [Extended] Receive Descriptor (Write-Back) Format
335 *
336 * 63 48 47 32 31 13 12 8 7 4 3 0
337 * +------------------------------------------------------+
338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
339 * | Checksum | Ident | | Queue | | Type |
340 * +------------------------------------------------------+
341 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
342 * +------------------------------------------------------+
343 * 63 48 47 32 31 20 19 0
344 */
ef456f85 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 346 for (i = 0; i < rx_ring->count; i++) {
ef456f85 347 const char *next_desc;
84f4ee90
TI		 348 buffer_info = &rx_ring->buffer_info[i];
349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
350 u1 = (struct my_u1 *)rx_desc_ps;
351 staterr =
af667a29 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 353
354 if (i == rx_ring->next_to_use)
355 next_desc = " NTU";
356 else if (i == rx_ring->next_to_clean)
357 next_desc = " NTC";
358 else
359 next_desc = "";
360
84f4ee90
TI		 361 if (staterr & E1000_RXD_STAT_DD) {
362 /* Descriptor Done */
ef456f85
JK		 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
364 "RWB", i,
365 (unsigned long long)le64_to_cpu(u1->a),
366 (unsigned long long)le64_to_cpu(u1->b),
367 (unsigned long long)le64_to_cpu(u1->c),
368 (unsigned long long)le64_to_cpu(u1->d),
369 buffer_info->skb, next_desc);
84f4ee90 370 } else {
ef456f85
JK		 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
372 "R ", i,
373 (unsigned long long)le64_to_cpu(u1->a),
374 (unsigned long long)le64_to_cpu(u1->b),
375 (unsigned long long)le64_to_cpu(u1->c),
376 (unsigned long long)le64_to_cpu(u1->d),
377 (unsigned long long)buffer_info->dma,
378 buffer_info->skb, next_desc);
84f4ee90
TI		 379
380 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 381 e1000e_dump_ps_pages(adapter,
382 buffer_info);
84f4ee90 383 }
84f4ee90
TI		 384 }
385 break;
386 default:
387 case 0:
5f450212 388 /* Extended Receive Descriptor (Read) Format
84f4ee90 389 *
5f450212
BA		 390 * +-----------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +-----------------------------------------------------+
393 * 8 | Reserved |
394 * +-----------------------------------------------------+
84f4ee90 395 */
ef456f85 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 397 /* Extended Receive Descriptor (Write-Back) Format
398 *
399 * 63 48 47 32 31 24 23 4 3 0
400 * +------------------------------------------------------+
401 * | RSS Hash | | | |
402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
403 * | Packet | IP | | | Type |
404 * | Checksum | Ident | | | |
405 * +------------------------------------------------------+
406 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
407 * +------------------------------------------------------+
408 * 63 48 47 32 31 20 19 0
409 */
ef456f85 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 411
412 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 413 const char *next_desc;
414
84f4ee90 415 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
417 u1 = (struct my_u1 *)rx_desc;
418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 419
420 if (i == rx_ring->next_to_use)
421 next_desc = " NTU";
422 else if (i == rx_ring->next_to_clean)
423 next_desc = " NTC";
424 else
425 next_desc = "";
426
5f450212
BA		 427 if (staterr & E1000_RXD_STAT_DD) {
428 /* Descriptor Done */
ef456f85
JK		 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
430 "RWB", i,
431 (unsigned long long)le64_to_cpu(u1->a),
432 (unsigned long long)le64_to_cpu(u1->b),
433 buffer_info->skb, next_desc);
5f450212 434 } else {
ef456f85
JK		 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
436 "R ", i,
437 (unsigned long long)le64_to_cpu(u1->a),
438 (unsigned long long)le64_to_cpu(u1->b),
439 (unsigned long long)buffer_info->dma,
440 buffer_info->skb, next_desc);
5f450212 441
f0c5dadf
ET		 442 if (netif_msg_pktdata(adapter) &&
443 buffer_info->skb)
5f450212
BA		 444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16,
446 1,
f0c5dadf 447 buffer_info->skb->data,
5f450212
BA		 448 adapter->rx_buffer_len,
449 true);
450 }
84f4ee90
TI		 451 }
452 }
84f4ee90
TI		 453}
454
bc7f75fa
AK		 455/**
456 * e1000_desc_unused - calculate if we have unused descriptors
457 **/
458static int e1000_desc_unused(struct e1000_ring *ring)
459{
460 if (ring->next_to_clean > ring->next_to_use)
461 return ring->next_to_clean - ring->next_to_use - 1;
462
463 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
464}
465
b67e1913
BA		 466/**
467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
468 * @adapter: board private structure
469 * @hwtstamps: time stamp structure to update
470 * @systim: unsigned 64bit system time value.
471 *
472 * Convert the system time value stored in the RX/TXSTMP registers into a
473 * hwtstamp which can be used by the upper level time stamping functions.
474 *
475 * The 'systim_lock' spinlock is used to protect the consistency of the
476 * system time value. This is needed because reading the 64 bit time
477 * value involves reading two 32 bit registers. The first read latches the
478 * value.
479 **/
480static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
481 struct skb_shared_hwtstamps *hwtstamps,
482 u64 systim)
483{
484 u64 ns;
485 unsigned long flags;
486
487 spin_lock_irqsave(&adapter->systim_lock, flags);
488 ns = timecounter_cyc2time(&adapter->tc, systim);
489 spin_unlock_irqrestore(&adapter->systim_lock, flags);
490
491 memset(hwtstamps, 0, sizeof(*hwtstamps));
492 hwtstamps->hwtstamp = ns_to_ktime(ns);
493}
494
495/**
496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
497 * @adapter: board private structure
498 * @status: descriptor extended error and status field
499 * @skb: particular skb to include time stamp
500 *
501 * If the time stamp is valid, convert it into the timecounter ns value
502 * and store that result into the shhwtstamps structure which is passed
503 * up the network stack.
504 **/
505static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
506 struct sk_buff *skb)
507{
508 struct e1000_hw *hw = &adapter->hw;
509 u64 rxstmp;
510
511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
512 !(status & E1000_RXDEXT_STATERR_TST) ||
513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
514 return;
515
516 /* The Rx time stamp registers contain the time stamp. No other
517 * received packet will be time stamped until the Rx time stamp
518 * registers are read. Because only one packet can be time stamped
519 * at a time, the register values must belong to this packet and
520 * therefore none of the other additional attributes need to be
521 * compared.
522 */
523 rxstmp = (u64)er32(RXSTMPL);
524 rxstmp |= (u64)er32(RXSTMPH) << 32;
525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
526
527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
528}
529
bc7f75fa 530/**
ad68076e 531 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 532 * @adapter: board private structure
b67e1913 533 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
535 * @skb: pointer to sk_buff to be indicated to stack
536 **/
537static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 538 struct net_device *netdev, struct sk_buff *skb,
b67e1913 539 u32 staterr, __le16 vlan)
bc7f75fa 540{
86d70e53 541 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 542
543 e1000e_rx_hwtstamp(adapter, staterr, skb);
544
bc7f75fa
AK		 545 skb->protocol = eth_type_trans(skb, netdev);
546
b67e1913 547 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 549
550 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 551}
552
553/**
af667a29 554 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 555 * @adapter: board private structure
556 * @status_err: receive descriptor status and error fields
557 * @csum: receive descriptor csum field
558 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 559 **/
560static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 561 struct sk_buff *skb)
bc7f75fa
AK		 562{
563 u16 status = (u16)status_err;
564 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 565
566 skb_checksum_none_assert(skb);
bc7f75fa 567
afd12939
BA		 568 /* Rx checksum disabled */
569 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
570 return;
571
bc7f75fa
AK		 572 /* Ignore Checksum bit is set */
573 if (status & E1000_RXD_STAT_IXSM)
574 return;
afd12939 575
2e1706f2
BA		 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */
577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 578 /* let the stack verify checksum errors */
579 adapter->hw_csum_err++;
580 return;
581 }
582
583 /* TCP/UDP Checksum has not been calculated */
584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
585 return;
586
587 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 588 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 589 adapter->hw_csum_good++;
590}
591
55aa6985 592static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 593{
55aa6985 594 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 595 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 596 s32 ret_val = __ew32_prepare(hw);
597
598 writel(i, rx_ring->tail);
c6e7f51e 599
bdc125f7 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 601 u32 rctl = er32(RCTL);
602 ew32(RCTL, rctl & ~E1000_RCTL_EN);
603 e_err("ME firmware caused invalid RDT - resetting\n");
604 schedule_work(&adapter->reset_task);
605 }
606}
607
55aa6985 608static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 609{
55aa6985 610 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 611 struct e1000_hw *hw = &adapter->hw;
bdc125f7 612 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 613
bdc125f7
BA		 614 writel(i, tx_ring->tail);
615
616 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 617 u32 tctl = er32(TCTL);
618 ew32(TCTL, tctl & ~E1000_TCTL_EN);
619 e_err("ME firmware caused invalid TDT - resetting\n");
620 schedule_work(&adapter->reset_task);
621 }
622}
623
bc7f75fa 624/**
5f450212 625 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 626 * @rx_ring: Rx descriptor ring
bc7f75fa 627 **/
55aa6985 628static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 629 int cleaned_count, gfp_t gfp)
bc7f75fa 630{
55aa6985 631 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 632 struct net_device *netdev = adapter->netdev;
633 struct pci_dev *pdev = adapter->pdev;
5f450212 634 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 635 struct e1000_buffer *buffer_info;
636 struct sk_buff *skb;
637 unsigned int i;
89d71a66 638 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 639
640 i = rx_ring->next_to_use;
641 buffer_info = &rx_ring->buffer_info[i];
642
643 while (cleaned_count--) {
644 skb = buffer_info->skb;
645 if (skb) {
646 skb_trim(skb, 0);
647 goto map_skb;
648 }
649
c2fed996 650 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 651 if (!skb) {
652 /* Better luck next round */
653 adapter->alloc_rx_buff_failed++;
654 break;
655 }
656
bc7f75fa
AK		 657 buffer_info->skb = skb;
658map_skb:
0be3f55f 659 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 660 adapter->rx_buffer_len,
0be3f55f
NN		 661 DMA_FROM_DEVICE);
662 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 663 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 664 adapter->rx_dma_failed++;
665 break;
666 }
667
5f450212
BA		 668 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
669 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 670
50849d79 671 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 672 /* Force memory writes to complete before letting h/w
50849d79
TH		 673 * know there are new descriptors to fetch. (Only
674 * applicable for weak-ordered memory model archs,
675 * such as IA-64).
676 */
677 wmb();
c6e7f51e 678 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 679 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 680 else
c5083cf6 681 writel(i, rx_ring->tail);
50849d79 682 }
bc7f75fa
AK		 683 i++;
684 if (i == rx_ring->count)
685 i = 0;
686 buffer_info = &rx_ring->buffer_info[i];
687 }
688
50849d79 689 rx_ring->next_to_use = i;
bc7f75fa
AK		 690}
691
692/**
693 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 694 * @rx_ring: Rx descriptor ring
bc7f75fa 695 **/
55aa6985 696static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 697 int cleaned_count, gfp_t gfp)
bc7f75fa 698{
55aa6985 699 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 700 struct net_device *netdev = adapter->netdev;
701 struct pci_dev *pdev = adapter->pdev;
702 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 703 struct e1000_buffer *buffer_info;
704 struct e1000_ps_page *ps_page;
705 struct sk_buff *skb;
706 unsigned int i, j;
707
708 i = rx_ring->next_to_use;
709 buffer_info = &rx_ring->buffer_info[i];
710
711 while (cleaned_count--) {
712 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
713
714 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 715 ps_page = &buffer_info->ps_pages[j];
716 if (j >= adapter->rx_ps_pages) {
717 /* all unused desc entries get hw null ptr */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 ~cpu_to_le64(0);
47f44e40
AK		 720 continue;
721 }
722 if (!ps_page->page) {
c2fed996 723 ps_page->page = alloc_page(gfp);
bc7f75fa 724 if (!ps_page->page) {
47f44e40
AK		 725 adapter->alloc_rx_buff_failed++;
726 goto no_buffers;
727 }
0be3f55f
NN		 728 ps_page->dma = dma_map_page(&pdev->dev,
729 ps_page->page,
730 0, PAGE_SIZE,
731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev,
733 ps_page->dma)) {
47f44e40 734 dev_err(&adapter->pdev->dev,
af667a29 735 "Rx DMA page map failed\n");
47f44e40
AK		 736 adapter->rx_dma_failed++;
737 goto no_buffers;
bc7f75fa 738 }
bc7f75fa 739 }
e921eb1a 740 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 741 * didn't change because each write-back
742 * erases this info.
743 */
af667a29
BA		 744 rx_desc->read.buffer_addr[j + 1] =
745 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 746 }
747
e5fe2541 748 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 749 gfp);
bc7f75fa
AK		 750
751 if (!skb) {
752 adapter->alloc_rx_buff_failed++;
753 break;
754 }
755
bc7f75fa 756 buffer_info->skb = skb;
0be3f55f 757 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 758 adapter->rx_ps_bsize0,
0be3f55f
NN		 759 DMA_FROM_DEVICE);
760 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 761 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 762 adapter->rx_dma_failed++;
763 /* cleanup skb */
764 dev_kfree_skb_any(skb);
765 buffer_info->skb = NULL;
766 break;
767 }
768
769 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
770
50849d79 771 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 772 /* Force memory writes to complete before letting h/w
50849d79
TH		 773 * know there are new descriptors to fetch. (Only
774 * applicable for weak-ordered memory model archs,
775 * such as IA-64).
776 */
777 wmb();
c6e7f51e 778 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 779 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 780 else
c5083cf6 781 writel(i << 1, rx_ring->tail);
50849d79
TH		 782 }
783
bc7f75fa
AK		 784 i++;
785 if (i == rx_ring->count)
786 i = 0;
787 buffer_info = &rx_ring->buffer_info[i];
788 }
789
790no_buffers:
50849d79 791 rx_ring->next_to_use = i;
bc7f75fa
AK		 792}
793
97ac8cae
BA		 794/**
795 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 796 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 797 * @cleaned_count: number of buffers to allocate this pass
798 **/
799
55aa6985 800static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 801 int cleaned_count, gfp_t gfp)
97ac8cae 802{
55aa6985 803 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 804 struct net_device *netdev = adapter->netdev;
805 struct pci_dev *pdev = adapter->pdev;
5f450212 806 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 807 struct e1000_buffer *buffer_info;
808 struct sk_buff *skb;
809 unsigned int i;
2a2293b9 810 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 811
812 i = rx_ring->next_to_use;
813 buffer_info = &rx_ring->buffer_info[i];
814
815 while (cleaned_count--) {
816 skb = buffer_info->skb;
817 if (skb) {
818 skb_trim(skb, 0);
819 goto check_page;
820 }
821
c2fed996 822 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 823 if (unlikely(!skb)) {
824 /* Better luck next round */
825 adapter->alloc_rx_buff_failed++;
826 break;
827 }
828
97ac8cae
BA		 829 buffer_info->skb = skb;
830check_page:
831 /* allocate a new page if necessary */
832 if (!buffer_info->page) {
c2fed996 833 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 834 if (unlikely(!buffer_info->page)) {
835 adapter->alloc_rx_buff_failed++;
836 break;
837 }
838 }
839
37287fae 840 if (!buffer_info->dma) {
0be3f55f 841 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 842 buffer_info->page, 0,
843 PAGE_SIZE,
0be3f55f 844 DMA_FROM_DEVICE);
37287fae
CP		 845 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
97ac8cae 850
5f450212
BA		 851 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
852 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 853
854 if (unlikely(++i == rx_ring->count))
855 i = 0;
856 buffer_info = &rx_ring->buffer_info[i];
857 }
858
859 if (likely(rx_ring->next_to_use != i)) {
860 rx_ring->next_to_use = i;
861 if (unlikely(i-- == 0))
862 i = (rx_ring->count - 1);
863
864 /* Force memory writes to complete before letting h/w
865 * know there are new descriptors to fetch. (Only
866 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 867 * such as IA-64).
868 */
97ac8cae 869 wmb();
c6e7f51e 870 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 871 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 872 else
c5083cf6 873 writel(i, rx_ring->tail);
97ac8cae
BA		 874 }
875}
876
70495a50
BA		 877static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
878 struct sk_buff *skb)
879{
880 if (netdev->features & NETIF_F_RXHASH)
e25909bc 881 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 882}
883
bc7f75fa 884/**
55aa6985
BA		 885 * e1000_clean_rx_irq - Send received data up the network stack
886 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 887 *
888 * the return value indicates whether actual cleaning was done, there
889 * is no guarantee that everything was cleaned
890 **/
55aa6985
BA		 891static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
892 int work_to_do)
bc7f75fa 893{
55aa6985 894 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 895 struct net_device *netdev = adapter->netdev;
896 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 897 struct e1000_hw *hw = &adapter->hw;
5f450212 898 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 899 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 900 u32 length, staterr;
bc7f75fa
AK		 901 unsigned int i;
902 int cleaned_count = 0;
3db1cd5c 903 bool cleaned = false;
bc7f75fa
AK		 904 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
905
906 i = rx_ring->next_to_clean;
5f450212
BA		 907 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
908 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 909 buffer_info = &rx_ring->buffer_info[i];
910
5f450212 911 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 912 struct sk_buff *skb;
bc7f75fa
AK		 913
914 if (*work_done >= work_to_do)
915 break;
916 (*work_done)++;
2d0bb1c1 917 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 918
bc7f75fa
AK		 919 skb = buffer_info->skb;
920 buffer_info->skb = NULL;
921
922 prefetch(skb->data - NET_IP_ALIGN);
923
924 i++;
925 if (i == rx_ring->count)
926 i = 0;
5f450212 927 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 928 prefetch(next_rxd);
929
930 next_buffer = &rx_ring->buffer_info[i];
931
3db1cd5c 932 cleaned = true;
bc7f75fa 933 cleaned_count++;
e5fe2541
BA		 934 dma_unmap_single(&pdev->dev, buffer_info->dma,
935 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 936 buffer_info->dma = 0;
937
5f450212 938 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 939
e921eb1a 940 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 941 * packet, if that's the case we need to toss it. In fact, we
942 * need to toss every packet with the EOP bit clear and the
943 * next frame that _does_ have the EOP bit set, as it is by
944 * definition only a frame fragment
945 */
5f450212 946 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 947 adapter->flags2 |= FLAG2_IS_DISCARDING;
948
949 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 950 /* All receives must fit into a single buffer */
3bb99fe2 951 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 952 /* recycle */
953 buffer_info->skb = skb;
5f450212 954 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 955 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 956 goto next_desc;
957 }
958
cf955e6c
BG		 959 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
960 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
963 goto next_desc;
964 }
965
eb7c3adb 966 /* adjust length to remove Ethernet CRC */
0184039a
BG		 967 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
968 /* If configured to store CRC, don't subtract FCS,
969 * but keep the FCS bytes out of the total_rx_bytes
970 * counter
971 */
972 if (netdev->features & NETIF_F_RXFCS)
973 total_rx_bytes -= 4;
974 else
975 length -= 4;
976 }
eb7c3adb 977
bc7f75fa
AK		 978 total_rx_bytes += length;
979 total_rx_packets++;
980
e921eb1a 981 /* code added for copybreak, this should improve
bc7f75fa 982 * performance for small packets with large amounts
ad68076e
BA		 983 * of reassembly being done in the stack
984 */
bc7f75fa
AK		 985 if (length < copybreak) {
986 struct sk_buff *new_skb =
89d71a66 987 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 988 if (new_skb) {
808ff676
BA		 989 skb_copy_to_linear_data_offset(new_skb,
990 -NET_IP_ALIGN,
991 (skb->data -
992 NET_IP_ALIGN),
993 (length +
994 NET_IP_ALIGN));
bc7f75fa
AK		 995 /* save the skb in buffer_info as good */
996 buffer_info->skb = skb;
997 skb = new_skb;
998 }
999 /* else just continue with the old one */
1000 }
1001 /* end copybreak code */
1002 skb_put(skb, length);
1003
1004 /* Receive Checksum Offload */
2e1706f2 1005 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1006
70495a50
BA		 1007 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1008
5f450212
BA		 1009 e1000_receive_skb(adapter, netdev, skb, staterr,
1010 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1011
1012next_desc:
5f450212 1013 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1014
1015 /* return some buffers to hardware, one at a time is too slow */
1016 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1017 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1018 GFP_ATOMIC);
bc7f75fa
AK		 1019 cleaned_count = 0;
1020 }
1021
1022 /* use prefetched values */
1023 rx_desc = next_rxd;
1024 buffer_info = next_buffer;
5f450212
BA		 1025
1026 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1027 }
1028 rx_ring->next_to_clean = i;
1029
1030 cleaned_count = e1000_desc_unused(rx_ring);
1031 if (cleaned_count)
55aa6985 1032 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1033
bc7f75fa 1034 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1035 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1036 return cleaned;
1037}
1038
55aa6985
BA		 1039static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1040 struct e1000_buffer *buffer_info)
bc7f75fa 1041{
55aa6985
BA		 1042 struct e1000_adapter *adapter = tx_ring->adapter;
1043
03b1320d
AD		 1044 if (buffer_info->dma) {
1045 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1046 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1047 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1048 else
0be3f55f
NN		 1049 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1050 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1051 buffer_info->dma = 0;
1052 }
bc7f75fa
AK		 1053 if (buffer_info->skb) {
1054 dev_kfree_skb_any(buffer_info->skb);
1055 buffer_info->skb = NULL;
1056 }
1b7719c4 1057 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1058}
1059
41cec6f1 1060static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1061{
41cec6f1 1062 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1063 struct e1000_adapter,
1064 print_hang_task);
09357b00 1065 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1066 struct e1000_ring *tx_ring = adapter->tx_ring;
1067 unsigned int i = tx_ring->next_to_clean;
1068 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1069 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1070 struct e1000_hw *hw = &adapter->hw;
1071 u16 phy_status, phy_1000t_status, phy_ext_status;
1072 u16 pci_status;
1073
615b32af
JB		 1074 if (test_bit(__E1000_DOWN, &adapter->state))
1075 return;
1076
e5fe2541 1077 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1078 /* May be block on write-back, flush and detect again
09357b00
JK		 1079 * flush pending descriptor writebacks to memory
1080 */
1081 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1082 /* execute the writes immediately */
1083 e1e_flush();
e921eb1a 1084 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1085 * the write is successful
1086 */
1087 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1088 /* execute the writes immediately */
1089 e1e_flush();
09357b00
JK		 1090 adapter->tx_hang_recheck = true;
1091 return;
1092 }
09357b00 1093 adapter->tx_hang_recheck = false;
d9554e96
DE		 1094
1095 if (er32(TDH(0)) == er32(TDT(0))) {
1096 e_dbg("false hang detected, ignoring\n");
1097 return;
1098 }
1099
1100 /* Real hang detected */
09357b00
JK		 1101 netif_stop_queue(netdev);
1102
c2ade1a4
BA		 1103 e1e_rphy(hw, MII_BMSR, &phy_status);
1104 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1105 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1106
41cec6f1
BA		 1107 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1108
1109 /* detected Hardware unit hang */
1110 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1111 " TDH <%x>\n"
1112 " TDT <%x>\n"
1113 " next_to_use <%x>\n"
1114 " next_to_clean <%x>\n"
1115 "buffer_info[next_to_clean]:\n"
1116 " time_stamp <%lx>\n"
1117 " next_to_watch <%x>\n"
1118 " jiffies <%lx>\n"
41cec6f1
BA		 1119 " next_to_watch.status <%x>\n"
1120 "MAC Status <%x>\n"
1121 "PHY Status <%x>\n"
1122 "PHY 1000BASE-T Status <%x>\n"
1123 "PHY Extended Status <%x>\n"
1124 "PCI Status <%x>\n",
e5fe2541
BA		 1125 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1126 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1127 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1128 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1129
d9554e96
DE		 1130 e1000e_dump(adapter);
1131
7c0427ee
BA		 1132 /* Suggest workaround for known h/w issue */
1133 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1134 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1135}
1136
b67e1913
BA		 1137/**
1138 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1139 * @work: pointer to work struct
1140 *
1141 * This work function polls the TSYNCTXCTL valid bit to determine when a
1142 * timestamp has been taken for the current stored skb. The timestamp must
1143 * be for this skb because only one such packet is allowed in the queue.
1144 */
1145static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1146{
1147 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1148 tx_hwtstamp_work);
1149 struct e1000_hw *hw = &adapter->hw;
1150
1151 if (!adapter->tx_hwtstamp_skb)
1152 return;
1153
1154 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1155 struct skb_shared_hwtstamps shhwtstamps;
1156 u64 txstmp;
1157
1158 txstmp = er32(TXSTMPL);
1159 txstmp |= (u64)er32(TXSTMPH) << 32;
1160
1161 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1162
1163 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1164 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1165 adapter->tx_hwtstamp_skb = NULL;
1166 } else {
1167 /* reschedule to check later */
1168 schedule_work(&adapter->tx_hwtstamp_work);
1169 }
1170}
1171
bc7f75fa
AK		 1172/**
1173 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1174 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1175 *
1176 * the return value indicates whether actual cleaning was done, there
1177 * is no guarantee that everything was cleaned
1178 **/
55aa6985 1179static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1180{
55aa6985 1181 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1182 struct net_device *netdev = adapter->netdev;
1183 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1184 struct e1000_tx_desc *tx_desc, *eop_desc;
1185 struct e1000_buffer *buffer_info;
1186 unsigned int i, eop;
1187 unsigned int count = 0;
bc7f75fa 1188 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1189 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1190
1191 i = tx_ring->next_to_clean;
1192 eop = tx_ring->buffer_info[i].next_to_watch;
1193 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1194
12d04a3c
AD		 1195 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1196 (count < tx_ring->count)) {
a86043c2 1197 bool cleaned = false;
e80bd1d1 1198 rmb(); /* read buffer_info after eop_desc */
a86043c2 1199 for (; !cleaned; count++) {
bc7f75fa
AK		 1200 tx_desc = E1000_TX_DESC(*tx_ring, i);
1201 buffer_info = &tx_ring->buffer_info[i];
1202 cleaned = (i == eop);
1203
1204 if (cleaned) {
9ed318d5
TH		 1205 total_tx_packets += buffer_info->segs;
1206 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1207 if (buffer_info->skb) {
1208 bytes_compl += buffer_info->skb->len;
1209 pkts_compl++;
1210 }
bc7f75fa
AK		 1211 }
1212
55aa6985 1213 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1214 tx_desc->upper.data = 0;
1215
1216 i++;
1217 if (i == tx_ring->count)
1218 i = 0;
1219 }
1220
dac87619
TL		 1221 if (i == tx_ring->next_to_use)
1222 break;
bc7f75fa
AK		 1223 eop = tx_ring->buffer_info[i].next_to_watch;
1224 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1225 }
1226
1227 tx_ring->next_to_clean = i;
1228
3f0cfa3b
TH		 1229 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1230
bc7f75fa 1231#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1232 if (count && netif_carrier_ok(netdev) &&
1233 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1234 /* Make sure that anybody stopping the queue after this
1235 * sees the new next_to_clean.
1236 */
1237 smp_mb();
1238
1239 if (netif_queue_stopped(netdev) &&
1240 !(test_bit(__E1000_DOWN, &adapter->state))) {
1241 netif_wake_queue(netdev);
1242 ++adapter->restart_queue;
1243 }
1244 }
1245
1246 if (adapter->detect_tx_hung) {
e921eb1a 1247 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1248 * check with the clearing of time_stamp and movement of i
1249 */
3db1cd5c 1250 adapter->detect_tx_hung = false;
12d04a3c
AD		 1251 if (tx_ring->buffer_info[i].time_stamp &&
1252 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1253 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1254 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1255 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1256 else
1257 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1258 }
1259 adapter->total_tx_bytes += total_tx_bytes;
1260 adapter->total_tx_packets += total_tx_packets;
807540ba 1261 return count < tx_ring->count;
bc7f75fa
AK		 1262}
1263
bc7f75fa
AK		 1264/**
1265 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1266 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1267 *
1268 * the return value indicates whether actual cleaning was done, there
1269 * is no guarantee that everything was cleaned
1270 **/
55aa6985
BA		 1271static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1272 int work_to_do)
bc7f75fa 1273{
55aa6985 1274 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1275 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1276 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1277 struct net_device *netdev = adapter->netdev;
1278 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1279 struct e1000_buffer *buffer_info, *next_buffer;
1280 struct e1000_ps_page *ps_page;
1281 struct sk_buff *skb;
1282 unsigned int i, j;
1283 u32 length, staterr;
1284 int cleaned_count = 0;
3db1cd5c 1285 bool cleaned = false;
bc7f75fa
AK		 1286 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1287
1288 i = rx_ring->next_to_clean;
1289 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1290 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1291 buffer_info = &rx_ring->buffer_info[i];
1292
1293 while (staterr & E1000_RXD_STAT_DD) {
1294 if (*work_done >= work_to_do)
1295 break;
1296 (*work_done)++;
1297 skb = buffer_info->skb;
2d0bb1c1 1298 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1299
1300 /* in the packet split case this is header only */
1301 prefetch(skb->data - NET_IP_ALIGN);
1302
1303 i++;
1304 if (i == rx_ring->count)
1305 i = 0;
1306 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1307 prefetch(next_rxd);
1308
1309 next_buffer = &rx_ring->buffer_info[i];
1310
3db1cd5c 1311 cleaned = true;
bc7f75fa 1312 cleaned_count++;
0be3f55f 1313 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1314 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1315 buffer_info->dma = 0;
1316
af667a29 1317 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1318 if (!(staterr & E1000_RXD_STAT_EOP))
1319 adapter->flags2 |= FLAG2_IS_DISCARDING;
1320
1321 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1322 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1323 dev_kfree_skb_irq(skb);
b94b5028
JB		 1324 if (staterr & E1000_RXD_STAT_EOP)
1325 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1326 goto next_desc;
1327 }
1328
cf955e6c
BG		 1329 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1330 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1331 dev_kfree_skb_irq(skb);
1332 goto next_desc;
1333 }
1334
1335 length = le16_to_cpu(rx_desc->wb.middle.length0);
1336
1337 if (!length) {
ef456f85 1338 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1339 dev_kfree_skb_irq(skb);
1340 goto next_desc;
1341 }
1342
1343 /* Good Receive */
1344 skb_put(skb, length);
1345
1346 {
e921eb1a 1347 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1348 * it more efficient than reusing j
1349 */
1350 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1351
e921eb1a 1352 /* page alloc/put takes too long and effects small
0e15df49
BA		 1353 * packet throughput, so unsplit small packets and
1354 * save the alloc/put only valid in softirq (napi)
1355 * context to call kmap_*
ad68076e 1356 */
0e15df49
BA		 1357 if (l1 && (l1 <= copybreak) &&
1358 ((length + l1) <= adapter->rx_ps_bsize0)) {
1359 u8 *vaddr;
1360
1361 ps_page = &buffer_info->ps_pages[0];
1362
e921eb1a 1363 /* there is no documentation about how to call
0e15df49
BA		 1364 * kmap_atomic, so we can't hold the mapping
1365 * very long
1366 */
1367 dma_sync_single_for_cpu(&pdev->dev,
1368 ps_page->dma,
1369 PAGE_SIZE,
1370 DMA_FROM_DEVICE);
9f393834 1371 vaddr = kmap_atomic(ps_page->page);
0e15df49 1372 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1373 kunmap_atomic(vaddr);
0e15df49
BA		 1374 dma_sync_single_for_device(&pdev->dev,
1375 ps_page->dma,
1376 PAGE_SIZE,
1377 DMA_FROM_DEVICE);
1378
1379 /* remove the CRC */
0184039a
BG		 1380 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1381 if (!(netdev->features & NETIF_F_RXFCS))
1382 l1 -= 4;
1383 }
0e15df49
BA		 1384
1385 skb_put(skb, l1);
1386 goto copydone;
e80bd1d1 1387 } /* if */
bc7f75fa
AK		 1388 }
1389
1390 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1391 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1392 if (!length)
1393 break;
1394
47f44e40 1395 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1396 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1397 DMA_FROM_DEVICE);
bc7f75fa
AK		 1398 ps_page->dma = 0;
1399 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1400 ps_page->page = NULL;
1401 skb->len += length;
1402 skb->data_len += length;
98a045d7 1403 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1404 }
1405
eb7c3adb
JK		 1406 /* strip the ethernet crc, problem is we're using pages now so
1407 * this whole operation can get a little cpu intensive
1408 */
0184039a
BG		 1409 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1410 if (!(netdev->features & NETIF_F_RXFCS))
1411 pskb_trim(skb, skb->len - 4);
1412 }
eb7c3adb 1413
bc7f75fa
AK		 1414copydone:
1415 total_rx_bytes += skb->len;
1416 total_rx_packets++;
1417
2e1706f2 1418 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1419
70495a50
BA		 1420 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1421
bc7f75fa 1422 if (rx_desc->wb.upper.header_status &
17e813ec 1423 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1424 adapter->rx_hdr_split++;
1425
b67e1913
BA		 1426 e1000_receive_skb(adapter, netdev, skb, staterr,
1427 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1428
1429next_desc:
1430 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1431 buffer_info->skb = NULL;
1432
1433 /* return some buffers to hardware, one at a time is too slow */
1434 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1435 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1436 GFP_ATOMIC);
bc7f75fa
AK		 1437 cleaned_count = 0;
1438 }
1439
1440 /* use prefetched values */
1441 rx_desc = next_rxd;
1442 buffer_info = next_buffer;
1443
1444 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1445 }
1446 rx_ring->next_to_clean = i;
1447
1448 cleaned_count = e1000_desc_unused(rx_ring);
1449 if (cleaned_count)
55aa6985 1450 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1451
bc7f75fa 1452 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1453 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1454 return cleaned;
1455}
1456
97ac8cae
BA		 1457/**
1458 * e1000_consume_page - helper function
1459 **/
1460static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1461 u16 length)
97ac8cae
BA		 1462{
1463 bi->page = NULL;
1464 skb->len += length;
1465 skb->data_len += length;
98a045d7 1466 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1467}
1468
1469/**
1470 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1471 * @adapter: board private structure
1472 *
1473 * the return value indicates whether actual cleaning was done, there
1474 * is no guarantee that everything was cleaned
1475 **/
55aa6985
BA		 1476static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1477 int work_to_do)
97ac8cae 1478{
55aa6985 1479 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1480 struct net_device *netdev = adapter->netdev;
1481 struct pci_dev *pdev = adapter->pdev;
5f450212 1482 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1483 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1484 u32 length, staterr;
97ac8cae
BA		 1485 unsigned int i;
1486 int cleaned_count = 0;
1487 bool cleaned = false;
362e20ca 1488 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1489 struct skb_shared_info *shinfo;
97ac8cae
BA		 1490
1491 i = rx_ring->next_to_clean;
5f450212
BA		 1492 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1493 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1494 buffer_info = &rx_ring->buffer_info[i];
1495
5f450212 1496 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1497 struct sk_buff *skb;
97ac8cae
BA		 1498
1499 if (*work_done >= work_to_do)
1500 break;
1501 (*work_done)++;
2d0bb1c1 1502 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1503
97ac8cae
BA		 1504 skb = buffer_info->skb;
1505 buffer_info->skb = NULL;
1506
1507 ++i;
1508 if (i == rx_ring->count)
1509 i = 0;
5f450212 1510 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1511 prefetch(next_rxd);
1512
1513 next_buffer = &rx_ring->buffer_info[i];
1514
1515 cleaned = true;
1516 cleaned_count++;
0be3f55f
NN		 1517 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1518 DMA_FROM_DEVICE);
97ac8cae
BA		 1519 buffer_info->dma = 0;
1520
5f450212 1521 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1522
1523 /* errors is only valid for DD + EOP descriptors */
5f450212 1524 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1525 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1526 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1527 /* recycle both page and skb */
1528 buffer_info->skb = skb;
1529 /* an error means any chain goes out the window too */
1530 if (rx_ring->rx_skb_top)
1531 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1532 rx_ring->rx_skb_top = NULL;
1533 goto next_desc;
97ac8cae 1534 }
f0f1a172 1535#define rxtop (rx_ring->rx_skb_top)
5f450212 1536 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1537 /* this descriptor is only the beginning (or middle) */
1538 if (!rxtop) {
1539 /* this is the beginning of a chain */
1540 rxtop = skb;
1541 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1542 0, length);
97ac8cae
BA		 1543 } else {
1544 /* this is the middle of a chain */
17e813ec
BA		 1545 shinfo = skb_shinfo(rxtop);
1546 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1547 buffer_info->page, 0,
1548 length);
97ac8cae
BA		 1549 /* re-use the skb, only consumed the page */
1550 buffer_info->skb = skb;
1551 }
1552 e1000_consume_page(buffer_info, rxtop, length);
1553 goto next_desc;
1554 } else {
1555 if (rxtop) {
1556 /* end of the chain */
17e813ec
BA		 1557 shinfo = skb_shinfo(rxtop);
1558 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1559 buffer_info->page, 0,
1560 length);
97ac8cae 1561 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1562 * page
1563 */
97ac8cae
BA		 1564 buffer_info->skb = skb;
1565 skb = rxtop;
1566 rxtop = NULL;
1567 e1000_consume_page(buffer_info, skb, length);
1568 } else {
1569 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1570 * copybreak to save the put_page/alloc_page
1571 */
97ac8cae
BA		 1572 if (length <= copybreak &&
1573 skb_tailroom(skb) >= length) {
1574 u8 *vaddr;
4679026d 1575 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1576 memcpy(skb_tail_pointer(skb), vaddr,
1577 length);
4679026d 1578 kunmap_atomic(vaddr);
97ac8cae 1579 /* re-use the page, so don't erase
e921eb1a
BA		 1580 * buffer_info->page
1581 */
97ac8cae
BA		 1582 skb_put(skb, length);
1583 } else {
1584 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1585 buffer_info->page, 0,
1586 length);
97ac8cae 1587 e1000_consume_page(buffer_info, skb,
f0ff4398 1588 length);
97ac8cae
BA		 1589 }
1590 }
1591 }
1592
2e1706f2
BA		 1593 /* Receive Checksum Offload */
1594 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1595
70495a50
BA		 1596 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1597
97ac8cae
BA		 1598 /* probably a little skewed due to removing CRC */
1599 total_rx_bytes += skb->len;
1600 total_rx_packets++;
1601
1602 /* eth type trans needs skb->data to point to something */
1603 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1604 e_err("pskb_may_pull failed.\n");
ef5ab89c 1605 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1606 goto next_desc;
1607 }
1608
5f450212
BA		 1609 e1000_receive_skb(adapter, netdev, skb, staterr,
1610 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1611
1612next_desc:
5f450212 1613 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1614
1615 /* return some buffers to hardware, one at a time is too slow */
1616 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1617 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1618 GFP_ATOMIC);
97ac8cae
BA		 1619 cleaned_count = 0;
1620 }
1621
1622 /* use prefetched values */
1623 rx_desc = next_rxd;
1624 buffer_info = next_buffer;
5f450212
BA		 1625
1626 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1627 }
1628 rx_ring->next_to_clean = i;
1629
1630 cleaned_count = e1000_desc_unused(rx_ring);
1631 if (cleaned_count)
55aa6985 1632 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1633
1634 adapter->total_rx_bytes += total_rx_bytes;
1635 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1636 return cleaned;
1637}
1638
bc7f75fa
AK		 1639/**
1640 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1641 * @rx_ring: Rx descriptor ring
bc7f75fa 1642 **/
55aa6985 1643static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1644{
55aa6985 1645 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1646 struct e1000_buffer *buffer_info;
1647 struct e1000_ps_page *ps_page;
1648 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1649 unsigned int i, j;
1650
1651 /* Free all the Rx ring sk_buffs */
1652 for (i = 0; i < rx_ring->count; i++) {
1653 buffer_info = &rx_ring->buffer_info[i];
1654 if (buffer_info->dma) {
1655 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1656 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1657 adapter->rx_buffer_len,
0be3f55f 1658 DMA_FROM_DEVICE);
97ac8cae 1659 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1660 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1661 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1662 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1663 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1664 adapter->rx_ps_bsize0,
0be3f55f 1665 DMA_FROM_DEVICE);
bc7f75fa
AK		 1666 buffer_info->dma = 0;
1667 }
1668
97ac8cae
BA		 1669 if (buffer_info->page) {
1670 put_page(buffer_info->page);
1671 buffer_info->page = NULL;
1672 }
1673
bc7f75fa
AK		 1674 if (buffer_info->skb) {
1675 dev_kfree_skb(buffer_info->skb);
1676 buffer_info->skb = NULL;
1677 }
1678
1679 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1680 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1681 if (!ps_page->page)
1682 break;
0be3f55f
NN		 1683 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1684 DMA_FROM_DEVICE);
bc7f75fa
AK		 1685 ps_page->dma = 0;
1686 put_page(ps_page->page);
1687 ps_page->page = NULL;
1688 }
1689 }
1690
1691 /* there also may be some cached data from a chained receive */
1692 if (rx_ring->rx_skb_top) {
1693 dev_kfree_skb(rx_ring->rx_skb_top);
1694 rx_ring->rx_skb_top = NULL;
1695 }
1696
bc7f75fa
AK		 1697 /* Zero out the descriptor ring */
1698 memset(rx_ring->desc, 0, rx_ring->size);
1699
1700 rx_ring->next_to_clean = 0;
1701 rx_ring->next_to_use = 0;
b94b5028 1702 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1703
c5083cf6 1704 writel(0, rx_ring->head);
b485dbae 1705 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 1706 e1000e_update_rdt_wa(rx_ring, 0);
1707 else
1708 writel(0, rx_ring->tail);
bc7f75fa
AK		 1709}
1710
a8f88ff5
JB		 1711static void e1000e_downshift_workaround(struct work_struct *work)
1712{
1713 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1714 struct e1000_adapter,
1715 downshift_task);
a8f88ff5 1716
615b32af
JB		 1717 if (test_bit(__E1000_DOWN, &adapter->state))
1718 return;
1719
a8f88ff5
JB		 1720 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1721}
1722
bc7f75fa
AK		 1723/**
1724 * e1000_intr_msi - Interrupt Handler
1725 * @irq: interrupt number
1726 * @data: pointer to a network interface device structure
1727 **/
8bb62869 1728static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1729{
1730 struct net_device *netdev = data;
1731 struct e1000_adapter *adapter = netdev_priv(netdev);
1732 struct e1000_hw *hw = &adapter->hw;
1733 u32 icr = er32(ICR);
1734
e921eb1a 1735 /* read ICR disables interrupts using IAM */
573cca8c 1736 if (icr & E1000_ICR_LSC) {
f92518dd 1737 hw->mac.get_link_status = true;
e921eb1a 1738 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1739 * disconnect (LSC) before accessing any PHY registers
1740 */
bc7f75fa
AK		 1741 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1742 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1743 schedule_work(&adapter->downshift_task);
bc7f75fa 1744
e921eb1a 1745 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1746 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1747 * adapter in watchdog
1748 */
bc7f75fa
AK		 1749 if (netif_carrier_ok(netdev) &&
1750 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1751 /* disable receives */
1752 u32 rctl = er32(RCTL);
1753 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1754 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1755 }
1756 /* guard against interrupt when we're going down */
1757 if (!test_bit(__E1000_DOWN, &adapter->state))
1758 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1759 }
1760
94fb848b
BA		 1761 /* Reset on uncorrectable ECC error */
1762 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1763 u32 pbeccsts = er32(PBECCSTS);
1764
1765 adapter->corr_errors +=
1766 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1767 adapter->uncorr_errors +=
1768 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1769 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1770
1771 /* Do the reset outside of interrupt context */
1772 schedule_work(&adapter->reset_task);
1773
1774 /* return immediately since reset is imminent */
1775 return IRQ_HANDLED;
1776 }
1777
288379f0 1778 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1779 adapter->total_tx_bytes = 0;
1780 adapter->total_tx_packets = 0;
1781 adapter->total_rx_bytes = 0;
1782 adapter->total_rx_packets = 0;
288379f0 1783 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1784 }
1785
1786 return IRQ_HANDLED;
1787}
1788
1789/**
1790 * e1000_intr - Interrupt Handler
1791 * @irq: interrupt number
1792 * @data: pointer to a network interface device structure
1793 **/
8bb62869 1794static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1795{
1796 struct net_device *netdev = data;
1797 struct e1000_adapter *adapter = netdev_priv(netdev);
1798 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1799 u32 rctl, icr = er32(ICR);
4662e82b 1800
a68ea775 1801 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1802 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1803
e921eb1a 1804 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1805 * not set, then the adapter didn't send an interrupt
1806 */
bc7f75fa
AK		 1807 if (!(icr & E1000_ICR_INT_ASSERTED))
1808 return IRQ_NONE;
1809
e921eb1a 1810 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1811 * interrupts are masked. No need for the
1812 * IMC write
1813 */
bc7f75fa 1814
573cca8c 1815 if (icr & E1000_ICR_LSC) {
f92518dd 1816 hw->mac.get_link_status = true;
e921eb1a 1817 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1818 * disconnect (LSC) before accessing any PHY registers
1819 */
bc7f75fa
AK		 1820 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1821 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1822 schedule_work(&adapter->downshift_task);
bc7f75fa 1823
e921eb1a 1824 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1825 * For packet buffer work-around on link down event;
1826 * disable receives here in the ISR and
1827 * reset adapter in watchdog
1828 */
1829 if (netif_carrier_ok(netdev) &&
1830 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1831 /* disable receives */
1832 rctl = er32(RCTL);
1833 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1834 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1835 }
1836 /* guard against interrupt when we're going down */
1837 if (!test_bit(__E1000_DOWN, &adapter->state))
1838 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1839 }
1840
94fb848b
BA		 1841 /* Reset on uncorrectable ECC error */
1842 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1843 u32 pbeccsts = er32(PBECCSTS);
1844
1845 adapter->corr_errors +=
1846 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1847 adapter->uncorr_errors +=
1848 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1849 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1850
1851 /* Do the reset outside of interrupt context */
1852 schedule_work(&adapter->reset_task);
1853
1854 /* return immediately since reset is imminent */
1855 return IRQ_HANDLED;
1856 }
1857
288379f0 1858 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1859 adapter->total_tx_bytes = 0;
1860 adapter->total_tx_packets = 0;
1861 adapter->total_rx_bytes = 0;
1862 adapter->total_rx_packets = 0;
288379f0 1863 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1864 }
1865
1866 return IRQ_HANDLED;
1867}
1868
8bb62869 1869static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1870{
1871 struct net_device *netdev = data;
1872 struct e1000_adapter *adapter = netdev_priv(netdev);
1873 struct e1000_hw *hw = &adapter->hw;
1874 u32 icr = er32(ICR);
1875
1876 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1877 if (!test_bit(__E1000_DOWN, &adapter->state))
1878 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1879 return IRQ_NONE;
1880 }
1881
1882 if (icr & adapter->eiac_mask)
1883 ew32(ICS, (icr & adapter->eiac_mask));
1884
1885 if (icr & E1000_ICR_OTHER) {
1886 if (!(icr & E1000_ICR_LSC))
1887 goto no_link_interrupt;
f92518dd 1888 hw->mac.get_link_status = true;
4662e82b
BA		 1889 /* guard against interrupt when we're going down */
1890 if (!test_bit(__E1000_DOWN, &adapter->state))
1891 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1892 }
1893
1894no_link_interrupt:
a3c69fef
JB		 1895 if (!test_bit(__E1000_DOWN, &adapter->state))
1896 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1897
1898 return IRQ_HANDLED;
1899}
1900
8bb62869 1901static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1902{
1903 struct net_device *netdev = data;
1904 struct e1000_adapter *adapter = netdev_priv(netdev);
1905 struct e1000_hw *hw = &adapter->hw;
1906 struct e1000_ring *tx_ring = adapter->tx_ring;
1907
4662e82b
BA		 1908 adapter->total_tx_bytes = 0;
1909 adapter->total_tx_packets = 0;
1910
55aa6985 1911 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1912 /* Ring was not completely cleaned, so fire another interrupt */
1913 ew32(ICS, tx_ring->ims_val);
1914
1915 return IRQ_HANDLED;
1916}
1917
8bb62869 1918static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1919{
1920 struct net_device *netdev = data;
1921 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1922 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1923
1924 /* Write the ITR value calculated at the end of the
1925 * previous interrupt.
1926 */
55aa6985
BA		 1927 if (rx_ring->set_itr) {
1928 writel(1000000000 / (rx_ring->itr_val * 256),
1929 rx_ring->itr_register);
1930 rx_ring->set_itr = 0;
4662e82b
BA		 1931 }
1932
288379f0 1933 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1934 adapter->total_rx_bytes = 0;
1935 adapter->total_rx_packets = 0;
288379f0 1936 __napi_schedule(&adapter->napi);
4662e82b
BA		 1937 }
1938 return IRQ_HANDLED;
1939}
1940
1941/**
1942 * e1000_configure_msix - Configure MSI-X hardware
1943 *
1944 * e1000_configure_msix sets up the hardware to properly
1945 * generate MSI-X interrupts.
1946 **/
1947static void e1000_configure_msix(struct e1000_adapter *adapter)
1948{
1949 struct e1000_hw *hw = &adapter->hw;
1950 struct e1000_ring *rx_ring = adapter->rx_ring;
1951 struct e1000_ring *tx_ring = adapter->tx_ring;
1952 int vector = 0;
1953 u32 ctrl_ext, ivar = 0;
1954
1955 adapter->eiac_mask = 0;
1956
1957 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1958 if (hw->mac.type == e1000_82574) {
1959 u32 rfctl = er32(RFCTL);
1960 rfctl |= E1000_RFCTL_ACK_DIS;
1961 ew32(RFCTL, rfctl);
1962 }
1963
4662e82b
BA		 1964 /* Configure Rx vector */
1965 rx_ring->ims_val = E1000_IMS_RXQ0;
1966 adapter->eiac_mask |= rx_ring->ims_val;
1967 if (rx_ring->itr_val)
1968 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1969 rx_ring->itr_register);
4662e82b 1970 else
c5083cf6 1971 writel(1, rx_ring->itr_register);
4662e82b
BA		 1972 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1973
1974 /* Configure Tx vector */
1975 tx_ring->ims_val = E1000_IMS_TXQ0;
1976 vector++;
1977 if (tx_ring->itr_val)
1978 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1979 tx_ring->itr_register);
4662e82b 1980 else
c5083cf6 1981 writel(1, tx_ring->itr_register);
4662e82b
BA		 1982 adapter->eiac_mask |= tx_ring->ims_val;
1983 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1984
1985 /* set vector for Other Causes, e.g. link changes */
1986 vector++;
1987 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1988 if (rx_ring->itr_val)
1989 writel(1000000000 / (rx_ring->itr_val * 256),
1990 hw->hw_addr + E1000_EITR_82574(vector));
1991 else
1992 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1993
1994 /* Cause Tx interrupts on every write back */
1995 ivar |= (1 << 31);
1996
1997 ew32(IVAR, ivar);
1998
1999 /* enable MSI-X PBA support */
2000 ctrl_ext = er32(CTRL_EXT);
2001 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2002
2003 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2004 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2005 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2006 ew32(CTRL_EXT, ctrl_ext);
2007 e1e_flush();
2008}
2009
2010void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2011{
2012 if (adapter->msix_entries) {
2013 pci_disable_msix(adapter->pdev);
2014 kfree(adapter->msix_entries);
2015 adapter->msix_entries = NULL;
2016 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2017 pci_disable_msi(adapter->pdev);
2018 adapter->flags &= ~FLAG_MSI_ENABLED;
2019 }
4662e82b
BA		 2020}
2021
2022/**
2023 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2024 *
2025 * Attempt to configure interrupts using the best available
2026 * capabilities of the hardware and kernel.
2027 **/
2028void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2029{
2030 int err;
8e86acd7 2031 int i;
4662e82b
BA		 2032
2033 switch (adapter->int_mode) {
2034 case E1000E_INT_MODE_MSIX:
2035 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2036 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2037 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2038 sizeof(struct
2039 msix_entry),
2040 GFP_KERNEL);
4662e82b 2041 if (adapter->msix_entries) {
0cc7c959
AG		 2042 struct e1000_adapter *a = adapter;
2043
8e86acd7 2044 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2045 adapter->msix_entries[i].entry = i;
2046
0cc7c959
AG		 2047 err = pci_enable_msix_range(a->pdev,
2048 a->msix_entries,
2049 a->num_vectors,
2050 a->num_vectors);
2051 if (err > 0)
4662e82b
BA		 2052 return;
2053 }
2054 /* MSI-X failed, so fall through and try MSI */
ef456f85 2055 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2056 e1000e_reset_interrupt_capability(adapter);
2057 }
2058 adapter->int_mode = E1000E_INT_MODE_MSI;
2059 /* Fall through */
2060 case E1000E_INT_MODE_MSI:
2061 if (!pci_enable_msi(adapter->pdev)) {
2062 adapter->flags |= FLAG_MSI_ENABLED;
2063 } else {
2064 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2065 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2066 }
2067 /* Fall through */
2068 case E1000E_INT_MODE_LEGACY:
2069 /* Don't do anything; this is the system default */
2070 break;
2071 }
8e86acd7
JK		 2072
2073 /* store the number of vectors being used */
2074 adapter->num_vectors = 1;
4662e82b
BA		 2075}
2076
2077/**
2078 * e1000_request_msix - Initialize MSI-X interrupts
2079 *
2080 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2081 * kernel.
2082 **/
2083static int e1000_request_msix(struct e1000_adapter *adapter)
2084{
2085 struct net_device *netdev = adapter->netdev;
2086 int err = 0, vector = 0;
2087
2088 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2089 snprintf(adapter->rx_ring->name,
2090 sizeof(adapter->rx_ring->name) - 1,
2091 "%s-rx-0", netdev->name);
4662e82b
BA		 2092 else
2093 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2094 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2095 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2096 netdev);
2097 if (err)
5015e53a 2098 return err;
c5083cf6
BA		 2099 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2100 E1000_EITR_82574(vector);
4662e82b
BA		 2101 adapter->rx_ring->itr_val = adapter->itr;
2102 vector++;
2103
2104 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2105 snprintf(adapter->tx_ring->name,
2106 sizeof(adapter->tx_ring->name) - 1,
2107 "%s-tx-0", netdev->name);
4662e82b
BA		 2108 else
2109 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2110 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2111 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2112 netdev);
2113 if (err)
5015e53a 2114 return err;
c5083cf6
BA		 2115 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2116 E1000_EITR_82574(vector);
4662e82b
BA		 2117 adapter->tx_ring->itr_val = adapter->itr;
2118 vector++;
2119
2120 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2121 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2122 if (err)
5015e53a 2123 return err;
4662e82b
BA		 2124
2125 e1000_configure_msix(adapter);
5015e53a 2126
4662e82b 2127 return 0;
4662e82b
BA		 2128}
2129
f8d59f78
BA		 2130/**
2131 * e1000_request_irq - initialize interrupts
2132 *
2133 * Attempts to configure interrupts using the best available
2134 * capabilities of the hardware and kernel.
2135 **/
bc7f75fa
AK		 2136static int e1000_request_irq(struct e1000_adapter *adapter)
2137{
2138 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2139 int err;
2140
4662e82b
BA		 2141 if (adapter->msix_entries) {
2142 err = e1000_request_msix(adapter);
2143 if (!err)
2144 return err;
2145 /* fall back to MSI */
2146 e1000e_reset_interrupt_capability(adapter);
2147 adapter->int_mode = E1000E_INT_MODE_MSI;
2148 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2149 }
4662e82b 2150 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2151 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2152 netdev->name, netdev);
2153 if (!err)
2154 return err;
bc7f75fa 2155
4662e82b
BA		 2156 /* fall back to legacy interrupt */
2157 e1000e_reset_interrupt_capability(adapter);
2158 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2159 }
2160
a0607fd3 2161 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2162 netdev->name, netdev);
2163 if (err)
2164 e_err("Unable to allocate interrupt, Error: %d\n", err);
2165
bc7f75fa
AK		 2166 return err;
2167}
2168
2169static void e1000_free_irq(struct e1000_adapter *adapter)
2170{
2171 struct net_device *netdev = adapter->netdev;
2172
4662e82b
BA		 2173 if (adapter->msix_entries) {
2174 int vector = 0;
2175
2176 free_irq(adapter->msix_entries[vector].vector, netdev);
2177 vector++;
2178
2179 free_irq(adapter->msix_entries[vector].vector, netdev);
2180 vector++;
2181
2182 /* Other Causes interrupt vector */
2183 free_irq(adapter->msix_entries[vector].vector, netdev);
2184 return;
bc7f75fa 2185 }
4662e82b
BA		 2186
2187 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2188}
2189
2190/**
2191 * e1000_irq_disable - Mask off interrupt generation on the NIC
2192 **/
2193static void e1000_irq_disable(struct e1000_adapter *adapter)
2194{
2195 struct e1000_hw *hw = &adapter->hw;
2196
bc7f75fa 2197 ew32(IMC, ~0);
4662e82b
BA		 2198 if (adapter->msix_entries)
2199 ew32(EIAC_82574, 0);
bc7f75fa 2200 e1e_flush();
8e86acd7
JK		 2201
2202 if (adapter->msix_entries) {
2203 int i;
2204 for (i = 0; i < adapter->num_vectors; i++)
2205 synchronize_irq(adapter->msix_entries[i].vector);
2206 } else {
2207 synchronize_irq(adapter->pdev->irq);
2208 }
bc7f75fa
AK		 2209}
2210
2211/**
2212 * e1000_irq_enable - Enable default interrupt generation settings
2213 **/
2214static void e1000_irq_enable(struct e1000_adapter *adapter)
2215{
2216 struct e1000_hw *hw = &adapter->hw;
2217
4662e82b
BA		 2218 if (adapter->msix_entries) {
2219 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2220 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2221 } else if (hw->mac.type == e1000_pch_lpt) {
2222 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2223 } else {
2224 ew32(IMS, IMS_ENABLE_MASK);
2225 }
74ef9c39 2226 e1e_flush();
bc7f75fa
AK		 2227}
2228
2229/**
31dbe5b4 2230 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2231 * @adapter: address of board private structure
2232 *
31dbe5b4 2233 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2234 * For ASF and Pass Through versions of f/w this means that
2235 * the driver is loaded. For AMT version (only with 82573)
2236 * of the f/w this means that the network i/f is open.
2237 **/
31dbe5b4 2238void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2239{
2240 struct e1000_hw *hw = &adapter->hw;
2241 u32 ctrl_ext;
2242 u32 swsm;
2243
2244 /* Let firmware know the driver has taken over */
2245 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2246 swsm = er32(SWSM);
2247 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2248 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2249 ctrl_ext = er32(CTRL_EXT);
ad68076e 2250 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2251 }
2252}
2253
2254/**
31dbe5b4 2255 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2256 * @adapter: address of board private structure
2257 *
31dbe5b4 2258 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2259 * For ASF and Pass Through versions of f/w this means that the
2260 * driver is no longer loaded. For AMT version (only with 82573) i
2261 * of the f/w this means that the network i/f is closed.
2262 *
2263 **/
31dbe5b4 2264void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2265{
2266 struct e1000_hw *hw = &adapter->hw;
2267 u32 ctrl_ext;
2268 u32 swsm;
2269
2270 /* Let firmware taken over control of h/w */
2271 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2272 swsm = er32(SWSM);
2273 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2274 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2275 ctrl_ext = er32(CTRL_EXT);
ad68076e 2276 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2277 }
2278}
2279
bc7f75fa 2280/**
49ce9c2c 2281 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2282 **/
2283static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2284 struct e1000_ring *ring)
2285{
2286 struct pci_dev *pdev = adapter->pdev;
2287
2288 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2289 GFP_KERNEL);
2290 if (!ring->desc)
2291 return -ENOMEM;
2292
2293 return 0;
2294}
2295
2296/**
2297 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2298 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2299 *
2300 * Return 0 on success, negative on failure
2301 **/
55aa6985 2302int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2303{
55aa6985 2304 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2305 int err = -ENOMEM, size;
2306
2307 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2308 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2309 if (!tx_ring->buffer_info)
2310 goto err;
bc7f75fa
AK		 2311
2312 /* round up to nearest 4K */
2313 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2314 tx_ring->size = ALIGN(tx_ring->size, 4096);
2315
2316 err = e1000_alloc_ring_dma(adapter, tx_ring);
2317 if (err)
2318 goto err;
2319
2320 tx_ring->next_to_use = 0;
2321 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2322
2323 return 0;
2324err:
2325 vfree(tx_ring->buffer_info);
44defeb3 2326 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2327 return err;
2328}
2329
2330/**
2331 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2332 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2333 *
2334 * Returns 0 on success, negative on failure
2335 **/
55aa6985 2336int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2337{
55aa6985 2338 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2339 struct e1000_buffer *buffer_info;
2340 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2341
2342 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2343 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2344 if (!rx_ring->buffer_info)
2345 goto err;
bc7f75fa 2346
47f44e40
AK		 2347 for (i = 0; i < rx_ring->count; i++) {
2348 buffer_info = &rx_ring->buffer_info[i];
2349 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2350 sizeof(struct e1000_ps_page),
2351 GFP_KERNEL);
2352 if (!buffer_info->ps_pages)
2353 goto err_pages;
2354 }
bc7f75fa
AK		 2355
2356 desc_len = sizeof(union e1000_rx_desc_packet_split);
2357
2358 /* Round up to nearest 4K */
2359 rx_ring->size = rx_ring->count * desc_len;
2360 rx_ring->size = ALIGN(rx_ring->size, 4096);
2361
2362 err = e1000_alloc_ring_dma(adapter, rx_ring);
2363 if (err)
47f44e40 2364 goto err_pages;
bc7f75fa
AK		 2365
2366 rx_ring->next_to_clean = 0;
2367 rx_ring->next_to_use = 0;
2368 rx_ring->rx_skb_top = NULL;
2369
2370 return 0;
47f44e40
AK		 2371
2372err_pages:
2373 for (i = 0; i < rx_ring->count; i++) {
2374 buffer_info = &rx_ring->buffer_info[i];
2375 kfree(buffer_info->ps_pages);
2376 }
bc7f75fa
AK		 2377err:
2378 vfree(rx_ring->buffer_info);
e9262447 2379 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2380 return err;
2381}
2382
2383/**
2384 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2385 * @tx_ring: Tx descriptor ring
bc7f75fa 2386 **/
55aa6985 2387static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2388{
55aa6985 2389 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2390 struct e1000_buffer *buffer_info;
2391 unsigned long size;
2392 unsigned int i;
2393
2394 for (i = 0; i < tx_ring->count; i++) {
2395 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2396 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2397 }
2398
3f0cfa3b 2399 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2400 size = sizeof(struct e1000_buffer) * tx_ring->count;
2401 memset(tx_ring->buffer_info, 0, size);
2402
2403 memset(tx_ring->desc, 0, tx_ring->size);
2404
2405 tx_ring->next_to_use = 0;
2406 tx_ring->next_to_clean = 0;
2407
c5083cf6 2408 writel(0, tx_ring->head);
b485dbae 2409 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 2410 e1000e_update_tdt_wa(tx_ring, 0);
2411 else
2412 writel(0, tx_ring->tail);
bc7f75fa
AK		 2413}
2414
2415/**
2416 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2417 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2418 *
2419 * Free all transmit software resources
2420 **/
55aa6985 2421void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2422{
55aa6985 2423 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2424 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2425
55aa6985 2426 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2427
2428 vfree(tx_ring->buffer_info);
2429 tx_ring->buffer_info = NULL;
2430
2431 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2432 tx_ring->dma);
2433 tx_ring->desc = NULL;
2434}
2435
2436/**
2437 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2438 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2439 *
2440 * Free all receive software resources
2441 **/
55aa6985 2442void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2443{
55aa6985 2444 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2445 struct pci_dev *pdev = adapter->pdev;
47f44e40 2446 int i;
bc7f75fa 2447
55aa6985 2448 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2449
b1cdfead 2450 for (i = 0; i < rx_ring->count; i++)
47f44e40 2451 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2452
bc7f75fa
AK		 2453 vfree(rx_ring->buffer_info);
2454 rx_ring->buffer_info = NULL;
2455
bc7f75fa
AK		 2456 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2457 rx_ring->dma);
2458 rx_ring->desc = NULL;
2459}
2460
2461/**
2462 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2463 * @adapter: pointer to adapter
2464 * @itr_setting: current adapter->itr
2465 * @packets: the number of packets during this measurement interval
2466 * @bytes: the number of bytes during this measurement interval
2467 *
bc7f75fa
AK		 2468 * Stores a new ITR value based on packets and byte
2469 * counts during the last interrupt. The advantage of per interrupt
2470 * computation is faster updates and more accurate ITR for the current
2471 * traffic pattern. Constants in this function were computed
2472 * based on theoretical maximum wire speed and thresholds were set based
2473 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2474 * while increasing bulk throughput. This functionality is controlled
2475 * by the InterruptThrottleRate module parameter.
bc7f75fa 2476 **/
8bb62869 2477static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2478{
2479 unsigned int retval = itr_setting;
2480
2481 if (packets == 0)
5015e53a 2482 return itr_setting;
bc7f75fa
AK		 2483
2484 switch (itr_setting) {
2485 case lowest_latency:
2486 /* handle TSO and jumbo frames */
362e20ca 2487 if (bytes / packets > 8000)
bc7f75fa 2488 retval = bulk_latency;
b1cdfead 2489 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2490 retval = low_latency;
bc7f75fa 2491 break;
e80bd1d1 2492 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2493 if (bytes > 10000) {
2494 /* this if handles the TSO accounting */
362e20ca 2495 if (bytes / packets > 8000)
bc7f75fa 2496 retval = bulk_latency;
362e20ca 2497 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2498 retval = bulk_latency;
b1cdfead 2499 else if ((packets > 35))
bc7f75fa 2500 retval = lowest_latency;
362e20ca 2501 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2502 retval = bulk_latency;
2503 } else if (packets <= 2 && bytes < 512) {
2504 retval = lowest_latency;
2505 }
2506 break;
e80bd1d1 2507 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2508 if (bytes > 25000) {
b1cdfead 2509 if (packets > 35)
bc7f75fa 2510 retval = low_latency;
bc7f75fa
AK		 2511 } else if (bytes < 6000) {
2512 retval = low_latency;
2513 }
2514 break;
2515 }
2516
bc7f75fa
AK		 2517 return retval;
2518}
2519
2520static void e1000_set_itr(struct e1000_adapter *adapter)
2521{
bc7f75fa
AK		 2522 u16 current_itr;
2523 u32 new_itr = adapter->itr;
2524
2525 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2526 if (adapter->link_speed != SPEED_1000) {
2527 current_itr = 0;
2528 new_itr = 4000;
2529 goto set_itr_now;
2530 }
2531
828bac87
BA		 2532 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2533 new_itr = 0;
2534 goto set_itr_now;
2535 }
2536
8bb62869
BA		 2537 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2538 adapter->total_tx_packets,
2539 adapter->total_tx_bytes);
bc7f75fa
AK		 2540 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2541 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2542 adapter->tx_itr = low_latency;
2543
8bb62869
BA		 2544 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2545 adapter->total_rx_packets,
2546 adapter->total_rx_bytes);
bc7f75fa
AK		 2547 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2548 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2549 adapter->rx_itr = low_latency;
2550
2551 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2552
bc7f75fa 2553 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2554 switch (current_itr) {
bc7f75fa
AK		 2555 case lowest_latency:
2556 new_itr = 70000;
2557 break;
2558 case low_latency:
e80bd1d1 2559 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2560 break;
2561 case bulk_latency:
2562 new_itr = 4000;
2563 break;
2564 default:
2565 break;
2566 }
2567
2568set_itr_now:
2569 if (new_itr != adapter->itr) {
e921eb1a 2570 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2571 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2572 * increasing
2573 */
bc7f75fa 2574 new_itr = new_itr > adapter->itr ?
f0ff4398 2575 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2576 adapter->itr = new_itr;
4662e82b
BA		 2577 adapter->rx_ring->itr_val = new_itr;
2578 if (adapter->msix_entries)
2579 adapter->rx_ring->set_itr = 1;
2580 else
e3d14b08 2581 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2582 }
2583}
2584
22a4cca2
MV		 2585/**
2586 * e1000e_write_itr - write the ITR value to the appropriate registers
2587 * @adapter: address of board private structure
2588 * @itr: new ITR value to program
2589 *
2590 * e1000e_write_itr determines if the adapter is in MSI-X mode
2591 * and, if so, writes the EITR registers with the ITR value.
2592 * Otherwise, it writes the ITR value into the ITR register.
2593 **/
2594void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2595{
2596 struct e1000_hw *hw = &adapter->hw;
2597 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2598
2599 if (adapter->msix_entries) {
2600 int vector;
2601
2602 for (vector = 0; vector < adapter->num_vectors; vector++)
2603 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2604 } else {
2605 ew32(ITR, new_itr);
2606 }
2607}
2608
4662e82b
BA		 2609/**
2610 * e1000_alloc_queues - Allocate memory for all rings
2611 * @adapter: board private structure to initialize
2612 **/
9f9a12f8 2613static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2614{
55aa6985
BA		 2615 int size = sizeof(struct e1000_ring);
2616
2617 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2618 if (!adapter->tx_ring)
2619 goto err;
55aa6985
BA		 2620 adapter->tx_ring->count = adapter->tx_ring_count;
2621 adapter->tx_ring->adapter = adapter;
4662e82b 2622
55aa6985 2623 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2624 if (!adapter->rx_ring)
2625 goto err;
55aa6985
BA		 2626 adapter->rx_ring->count = adapter->rx_ring_count;
2627 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2628
2629 return 0;
2630err:
2631 e_err("Unable to allocate memory for queues\n");
2632 kfree(adapter->rx_ring);
2633 kfree(adapter->tx_ring);
2634 return -ENOMEM;
2635}
2636
bc7f75fa 2637/**
c58c8a78 2638 * e1000e_poll - NAPI Rx polling callback
ad68076e 2639 * @napi: struct associated with this polling callback
c58c8a78 2640 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2641 **/
c58c8a78 2642static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2643{
c58c8a78
BA		 2644 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2645 napi);
4662e82b 2646 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2647 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2648 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2649
4cf1653a 2650 adapter = netdev_priv(poll_dev);
bc7f75fa 2651
c58c8a78
BA		 2652 if (!adapter->msix_entries ||
2653 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2654 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2655
c58c8a78 2656 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2657
12d04a3c 2658 if (!tx_cleaned)
c58c8a78 2659 work_done = weight;
bc7f75fa 2660
c58c8a78
BA		 2661 /* If weight not fully consumed, exit the polling mode */
2662 if (work_done < weight) {
bc7f75fa
AK		 2663 if (adapter->itr_setting & 3)
2664 e1000_set_itr(adapter);
288379f0 2665 napi_complete(napi);
a3c69fef
JB		 2666 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2667 if (adapter->msix_entries)
2668 ew32(IMS, adapter->rx_ring->ims_val);
2669 else
2670 e1000_irq_enable(adapter);
2671 }
bc7f75fa
AK		 2672 }
2673
2674 return work_done;
2675}
2676
80d5c368 2677static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2678 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2679{
2680 struct e1000_adapter *adapter = netdev_priv(netdev);
2681 struct e1000_hw *hw = &adapter->hw;
2682 u32 vfta, index;
2683
2684 /* don't update vlan cookie if already programmed */
2685 if ((adapter->hw.mng_cookie.status &
2686 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2687 (vid == adapter->mng_vlan_id))
8e586137 2688 return 0;
caaddaf8 2689
bc7f75fa 2690 /* add VID to filter table */
caaddaf8
BA		 2691 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2692 index = (vid >> 5) & 0x7F;
2693 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2694 vfta |= (1 << (vid & 0x1F));
2695 hw->mac.ops.write_vfta(hw, index, vfta);
2696 }
86d70e53
JK		 2697
2698 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2699
2700 return 0;
bc7f75fa
AK		 2701}
2702
80d5c368 2703static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2704 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2705{
2706 struct e1000_adapter *adapter = netdev_priv(netdev);
2707 struct e1000_hw *hw = &adapter->hw;
2708 u32 vfta, index;
2709
bc7f75fa
AK		 2710 if ((adapter->hw.mng_cookie.status &
2711 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2712 (vid == adapter->mng_vlan_id)) {
2713 /* release control to f/w */
31dbe5b4 2714 e1000e_release_hw_control(adapter);
8e586137 2715 return 0;
bc7f75fa
AK		 2716 }
2717
2718 /* remove VID from filter table */
caaddaf8
BA		 2719 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2720 index = (vid >> 5) & 0x7F;
2721 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2722 vfta &= ~(1 << (vid & 0x1F));
2723 hw->mac.ops.write_vfta(hw, index, vfta);
2724 }
86d70e53
JK		 2725
2726 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2727
2728 return 0;
bc7f75fa
AK		 2729}
2730
86d70e53
JK		 2731/**
2732 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2733 * @adapter: board private structure to initialize
2734 **/
2735static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2736{
2737 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2738 struct e1000_hw *hw = &adapter->hw;
2739 u32 rctl;
bc7f75fa 2740
86d70e53
JK		 2741 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2742 /* disable VLAN receive filtering */
2743 rctl = er32(RCTL);
2744 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2745 ew32(RCTL, rctl);
2746
2747 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2748 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2749 adapter->mng_vlan_id);
86d70e53 2750 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2751 }
bc7f75fa
AK		 2752 }
2753}
2754
86d70e53
JK		 2755/**
2756 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2757 * @adapter: board private structure to initialize
2758 **/
2759static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2760{
2761 struct e1000_hw *hw = &adapter->hw;
2762 u32 rctl;
2763
2764 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2765 /* enable VLAN receive filtering */
2766 rctl = er32(RCTL);
2767 rctl |= E1000_RCTL_VFE;
2768 rctl &= ~E1000_RCTL_CFIEN;
2769 ew32(RCTL, rctl);
2770 }
2771}
bc7f75fa 2772
86d70e53
JK		 2773/**
2774 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2775 * @adapter: board private structure to initialize
2776 **/
2777static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2778{
bc7f75fa 2779 struct e1000_hw *hw = &adapter->hw;
86d70e53 2780 u32 ctrl;
bc7f75fa 2781
86d70e53
JK		 2782 /* disable VLAN tag insert/strip */
2783 ctrl = er32(CTRL);
2784 ctrl &= ~E1000_CTRL_VME;
2785 ew32(CTRL, ctrl);
2786}
bc7f75fa 2787
86d70e53
JK		 2788/**
2789 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2790 * @adapter: board private structure to initialize
2791 **/
2792static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2793{
2794 struct e1000_hw *hw = &adapter->hw;
2795 u32 ctrl;
bc7f75fa 2796
86d70e53
JK		 2797 /* enable VLAN tag insert/strip */
2798 ctrl = er32(CTRL);
2799 ctrl |= E1000_CTRL_VME;
2800 ew32(CTRL, ctrl);
2801}
bc7f75fa 2802
86d70e53
JK		 2803static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2804{
2805 struct net_device *netdev = adapter->netdev;
2806 u16 vid = adapter->hw.mng_cookie.vlan_id;
2807 u16 old_vid = adapter->mng_vlan_id;
2808
e5fe2541 2809 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2810 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2811 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2812 }
2813
86d70e53 2814 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2815 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2816}
2817
2818static void e1000_restore_vlan(struct e1000_adapter *adapter)
2819{
2820 u16 vid;
2821
80d5c368 2822 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2823
86d70e53 2824 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2825 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2826}
2827
cd791618 2828static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2829{
2830 struct e1000_hw *hw = &adapter->hw;
cd791618 2831 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2832
2833 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2834 return;
2835
2836 manc = er32(MANC);
2837
e921eb1a 2838 /* enable receiving management packets to the host. this will probably
bc7f75fa 2839 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2840 * the packets will be handled on SMBUS
2841 */
bc7f75fa
AK		 2842 manc |= E1000_MANC_EN_MNG2HOST;
2843 manc2h = er32(MANC2H);
cd791618
BA		 2844
2845 switch (hw->mac.type) {
2846 default:
2847 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2848 break;
2849 case e1000_82574:
2850 case e1000_82583:
e921eb1a 2851 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2852 * if so, enable it.
2853 */
2854 for (i = 0, j = 0; i < 8; i++) {
2855 mdef = er32(MDEF(i));
2856
2857 /* Ignore filters with anything other than IPMI ports */
3b21b508 2858 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2859 continue;
2860
2861 /* Enable this decision filter in MANC2H */
2862 if (mdef)
2863 manc2h |= (1 << i);
2864
2865 j |= mdef;
2866 }
2867
2868 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2869 break;
2870
2871 /* Create new decision filter in an empty filter */
2872 for (i = 0, j = 0; i < 8; i++)
2873 if (er32(MDEF(i)) == 0) {
2874 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2875 E1000_MDEF_PORT_664));
2876 manc2h |= (1 << 1);
2877 j++;
2878 break;
2879 }
2880
2881 if (!j)
2882 e_warn("Unable to create IPMI pass-through filter\n");
2883 break;
2884 }
2885
bc7f75fa
AK		 2886 ew32(MANC2H, manc2h);
2887 ew32(MANC, manc);
2888}
2889
2890/**
af667a29 2891 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2892 * @adapter: board private structure
2893 *
2894 * Configure the Tx unit of the MAC after a reset.
2895 **/
2896static void e1000_configure_tx(struct e1000_adapter *adapter)
2897{
2898 struct e1000_hw *hw = &adapter->hw;
2899 struct e1000_ring *tx_ring = adapter->tx_ring;
2900 u64 tdba;
e7e834aa 2901 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2902
2903 /* Setup the HW Tx Head and Tail descriptor pointers */
2904 tdba = tx_ring->dma;
2905 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2906 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2907 ew32(TDBAH(0), (tdba >> 32));
2908 ew32(TDLEN(0), tdlen);
2909 ew32(TDH(0), 0);
2910 ew32(TDT(0), 0);
2911 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2912 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2913
bc7f75fa
AK		 2914 /* Set the Tx Interrupt Delay register */
2915 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2916 /* Tx irq moderation */
bc7f75fa
AK		 2917 ew32(TADV, adapter->tx_abs_int_delay);
2918
3a3b7586
JB		 2919 if (adapter->flags2 & FLAG2_DMA_BURST) {
2920 u32 txdctl = er32(TXDCTL(0));
2921 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2922 E1000_TXDCTL_WTHRESH);
e921eb1a 2923 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2924 * hardware to use the bus more efficiently in bursts, depends
2925 * on the tx_int_delay to be enabled,
8edc0e62 2926 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2927 * hthresh = 1 ==> prefetch when one or more available
2928 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2929 * BEWARE: this seems to work but should be considered first if
af667a29 2930 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2931 */
2932 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2933 ew32(TXDCTL(0), txdctl);
3a3b7586 2934 }
56032be7
BA		 2935 /* erratum work around: set txdctl the same for both queues */
2936 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2937
e7e834aa
DE		 2938 /* Program the Transmit Control Register */
2939 tctl = er32(TCTL);
2940 tctl &= ~E1000_TCTL_CT;
2941 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2942 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2943
bc7f75fa 2944 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2945 tarc = er32(TARC(0));
e921eb1a 2946 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2947 * gigabit link later
2948 */
bc7f75fa
AK		 2949#define SPEED_MODE_BIT (1 << 21)
2950 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2951 ew32(TARC(0), tarc);
bc7f75fa
AK		 2952 }
2953
2954 /* errata: program both queues to unweighted RR */
2955 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2956 tarc = er32(TARC(0));
bc7f75fa 2957 tarc |= 1;
e9ec2c0f
JK		 2958 ew32(TARC(0), tarc);
2959 tarc = er32(TARC(1));
bc7f75fa 2960 tarc |= 1;
e9ec2c0f 2961 ew32(TARC(1), tarc);
bc7f75fa
AK		 2962 }
2963
bc7f75fa
AK		 2964 /* Setup Transmit Descriptor Settings for eop descriptor */
2965 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2966
2967 /* only set IDE if we are delaying interrupts using the timers */
2968 if (adapter->tx_int_delay)
2969 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2970
2971 /* enable Report Status bit */
2972 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2973
e7e834aa
DE		 2974 ew32(TCTL, tctl);
2975
57cde763 2976 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2977}
2978
2979/**
2980 * e1000_setup_rctl - configure the receive control registers
2981 * @adapter: Board private structure
2982 **/
2983#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2984 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2985static void e1000_setup_rctl(struct e1000_adapter *adapter)
2986{
2987 struct e1000_hw *hw = &adapter->hw;
2988 u32 rctl, rfctl;
bc7f75fa
AK		 2989 u32 pages = 0;
2990
2fbe4526 2991 /* Workaround Si errata on PCHx - configure jumbo frame flow */
da1e2046
BA		 2992 if ((hw->mac.type >= e1000_pch2lan) &&
2993 (adapter->netdev->mtu > ETH_DATA_LEN) &&
2994 e1000_lv_jumbo_workaround_ich8lan(hw, true))
2995 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473 2996
bc7f75fa
AK		 2997 /* Program MC offset vector base */
2998 rctl = er32(RCTL);
2999 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3000 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3001 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3002 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3003
3004 /* Do not Store bad packets */
3005 rctl &= ~E1000_RCTL_SBP;
3006
3007 /* Enable Long Packet receive */
3008 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3009 rctl &= ~E1000_RCTL_LPE;
3010 else
3011 rctl |= E1000_RCTL_LPE;
3012
eb7c3adb
JK		 3013 /* Some systems expect that the CRC is included in SMBUS traffic. The
3014 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3015 * host memory when this is enabled
3016 */
3017 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3018 rctl |= E1000_RCTL_SECRC;
5918bd88 3019
a4f58f54
BA		 3020 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3021 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3022 u16 phy_data;
3023
3024 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3025 phy_data &= 0xfff8;
3026 phy_data |= (1 << 2);
3027 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3028
3029 e1e_rphy(hw, 22, &phy_data);
3030 phy_data &= 0x0fff;
3031 phy_data |= (1 << 14);
3032 e1e_wphy(hw, 0x10, 0x2823);
3033 e1e_wphy(hw, 0x11, 0x0003);
3034 e1e_wphy(hw, 22, phy_data);
3035 }
3036
bc7f75fa
AK		 3037 /* Setup buffer sizes */
3038 rctl &= ~E1000_RCTL_SZ_4096;
3039 rctl |= E1000_RCTL_BSEX;
3040 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3041 case 2048:
3042 default:
3043 rctl |= E1000_RCTL_SZ_2048;
3044 rctl &= ~E1000_RCTL_BSEX;
3045 break;
3046 case 4096:
3047 rctl |= E1000_RCTL_SZ_4096;
3048 break;
3049 case 8192:
3050 rctl |= E1000_RCTL_SZ_8192;
3051 break;
3052 case 16384:
3053 rctl |= E1000_RCTL_SZ_16384;
3054 break;
3055 }
3056
5f450212
BA		 3057 /* Enable Extended Status in all Receive Descriptors */
3058 rfctl = er32(RFCTL);
3059 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3060 ew32(RFCTL, rfctl);
5f450212 3061
e921eb1a 3062 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3063 * header is placed in skb->data and the packet data is
3064 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3065 * In the case of a non-split, skb->data is linearly filled,
3066 * followed by the page buffers. Therefore, skb->data is
3067 * sized to hold the largest protocol header.
3068 *
3069 * allocations using alloc_page take too long for regular MTU
3070 * so only enable packet split for jumbo frames
3071 *
3072 * Using pages when the page size is greater than 16k wastes
3073 * a lot of memory, since we allocate 3 pages at all times
3074 * per packet.
3075 */
bc7f75fa 3076 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3077 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3078 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3079 else
3080 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3081
3082 if (adapter->rx_ps_pages) {
90da0669
BA		 3083 u32 psrctl = 0;
3084
140a7480
AK		 3085 /* Enable Packet split descriptors */
3086 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3087
e5fe2541 3088 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3089
3090 switch (adapter->rx_ps_pages) {
3091 case 3:
e5fe2541
BA		 3092 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3093 /* fall-through */
bc7f75fa 3094 case 2:
e5fe2541
BA		 3095 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3096 /* fall-through */
bc7f75fa 3097 case 1:
e5fe2541 3098 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3099 break;
3100 }
3101
3102 ew32(PSRCTL, psrctl);
3103 }
3104
cf955e6c
BG		 3105 /* This is useful for sniffing bad packets. */
3106 if (adapter->netdev->features & NETIF_F_RXALL) {
3107 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3108 * in e1000e_set_rx_mode
3109 */
e80bd1d1
BA		 3110 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3111 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3112 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3113
e80bd1d1
BA		 3114 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3115 E1000_RCTL_DPF | /* Allow filtered pause */
3116 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3117 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3118 * and that breaks VLANs.
3119 */
3120 }
3121
bc7f75fa 3122 ew32(RCTL, rctl);
318a94d6 3123 /* just started the receive unit, no need to restart */
12d43f7d 3124 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3125}
3126
3127/**
3128 * e1000_configure_rx - Configure Receive Unit after Reset
3129 * @adapter: board private structure
3130 *
3131 * Configure the Rx unit of the MAC after a reset.
3132 **/
3133static void e1000_configure_rx(struct e1000_adapter *adapter)
3134{
3135 struct e1000_hw *hw = &adapter->hw;
3136 struct e1000_ring *rx_ring = adapter->rx_ring;
3137 u64 rdba;
3138 u32 rdlen, rctl, rxcsum, ctrl_ext;
3139
3140 if (adapter->rx_ps_pages) {
3141 /* this is a 32 byte descriptor */
3142 rdlen = rx_ring->count *
af667a29 3143 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3144 adapter->clean_rx = e1000_clean_rx_irq_ps;
3145 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3146 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3147 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3148 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3149 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3150 } else {
5f450212 3151 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3152 adapter->clean_rx = e1000_clean_rx_irq;
3153 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3154 }
3155
3156 /* disable receives while setting up the descriptors */
3157 rctl = er32(RCTL);
7f99ae63
BA		 3158 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3159 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3160 e1e_flush();
1bba4386 3161 usleep_range(10000, 20000);
bc7f75fa 3162
3a3b7586 3163 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3164 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3165 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3166 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3167 * granularity = 01
3168 * wthresh = 04,
3169 * hthresh = 04,
3170 * pthresh = 0x20
3171 */
3172 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3173 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3174
e921eb1a 3175 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3176 * the value was not set by the user via module options
3177 */
3178 if (adapter->rx_int_delay == DEFAULT_RDTR)
3179 adapter->rx_int_delay = BURST_RDTR;
3180 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3181 adapter->rx_abs_int_delay = BURST_RADV;
3182 }
3183
bc7f75fa
AK		 3184 /* set the Receive Delay Timer Register */
3185 ew32(RDTR, adapter->rx_int_delay);
3186
3187 /* irq moderation */
3188 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3189 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3190 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3191
3192 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3193 /* Auto-Mask interrupts upon ICR access */
3194 ctrl_ext |= E1000_CTRL_EXT_IAME;
3195 ew32(IAM, 0xffffffff);
3196 ew32(CTRL_EXT, ctrl_ext);
3197 e1e_flush();
3198
e921eb1a 3199 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3200 * the Base and Length of the Rx Descriptor Ring
3201 */
bc7f75fa 3202 rdba = rx_ring->dma;
1e36052e
BA		 3203 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3204 ew32(RDBAH(0), (rdba >> 32));
3205 ew32(RDLEN(0), rdlen);
3206 ew32(RDH(0), 0);
3207 ew32(RDT(0), 0);
3208 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3209 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3210
3211 /* Enable Receive Checksum Offload for TCP and UDP */
3212 rxcsum = er32(RXCSUM);
2e1706f2 3213 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3214 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3215 else
bc7f75fa 3216 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3217 ew32(RXCSUM, rxcsum);
3218
3e35d991
BA		 3219 /* With jumbo frames, excessive C-state transition latencies result
3220 * in dropped transactions.
3221 */
3222 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3223 u32 lat =
3224 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3225 adapter->max_frame_size) * 8 / 1000;
3226
3227 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3228 u32 rxdctl = er32(RXDCTL(0));
3229 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3230 }
3e35d991
BA		 3231
3232 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3233 } else {
3234 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3235 PM_QOS_DEFAULT_VALUE);
97ac8cae 3236 }
bc7f75fa
AK		 3237
3238 /* Enable Receives */
3239 ew32(RCTL, rctl);
3240}
3241
3242/**
ef9b965a
JB		 3243 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3244 * @netdev: network interface device structure
bc7f75fa 3245 *
ef9b965a
JB		 3246 * Writes multicast address list to the MTA hash table.
3247 * Returns: -ENOMEM on failure
3248 * 0 on no addresses written
3249 * X on writing X addresses to MTA
3250 */
3251static int e1000e_write_mc_addr_list(struct net_device *netdev)
3252{
3253 struct e1000_adapter *adapter = netdev_priv(netdev);
3254 struct e1000_hw *hw = &adapter->hw;
3255 struct netdev_hw_addr *ha;
3256 u8 *mta_list;
3257 int i;
3258
3259 if (netdev_mc_empty(netdev)) {
3260 /* nothing to program, so clear mc list */
3261 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3262 return 0;
3263 }
3264
3265 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3266 if (!mta_list)
3267 return -ENOMEM;
3268
3269 /* update_mc_addr_list expects a packed array of only addresses. */
3270 i = 0;
3271 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3272 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3273
3274 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3275 kfree(mta_list);
3276
3277 return netdev_mc_count(netdev);
3278}
3279
3280/**
3281 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3282 * @netdev: network interface device structure
bc7f75fa 3283 *
ef9b965a
JB		 3284 * Writes unicast address list to the RAR table.
3285 * Returns: -ENOMEM on failure/insufficient address space
3286 * 0 on no addresses written
3287 * X on writing X addresses to the RAR table
bc7f75fa 3288 **/
ef9b965a 3289static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3290{
ef9b965a
JB		 3291 struct e1000_adapter *adapter = netdev_priv(netdev);
3292 struct e1000_hw *hw = &adapter->hw;
3293 unsigned int rar_entries = hw->mac.rar_entry_count;
3294 int count = 0;
3295
3296 /* save a rar entry for our hardware address */
3297 rar_entries--;
3298
3299 /* save a rar entry for the LAA workaround */
3300 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3301 rar_entries--;
3302
3303 /* return ENOMEM indicating insufficient memory for addresses */
3304 if (netdev_uc_count(netdev) > rar_entries)
3305 return -ENOMEM;
3306
3307 if (!netdev_uc_empty(netdev) && rar_entries) {
3308 struct netdev_hw_addr *ha;
3309
e921eb1a 3310 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3311 * combining
3312 */
3313 netdev_for_each_uc_addr(ha, netdev) {
3314 if (!rar_entries)
3315 break;
69e1e019 3316 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3317 count++;
3318 }
3319 }
3320
3321 /* zero out the remaining RAR entries not used above */
3322 for (; rar_entries > 0; rar_entries--) {
3323 ew32(RAH(rar_entries), 0);
3324 ew32(RAL(rar_entries), 0);
3325 }
3326 e1e_flush();
3327
3328 return count;
bc7f75fa
AK		 3329}
3330
3331/**
ef9b965a 3332 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3333 * @netdev: network interface device structure
3334 *
ef9b965a
JB		 3335 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3336 * address list or the network interface flags are updated. This routine is
3337 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3338 * promiscuous mode, and all-multi behavior.
3339 **/
ef9b965a 3340static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3341{
3342 struct e1000_adapter *adapter = netdev_priv(netdev);
3343 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3344 u32 rctl;
bc7f75fa 3345
63eb48f1
DE		 3346 if (pm_runtime_suspended(netdev->dev.parent))
3347 return;
3348
bc7f75fa 3349 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3350 rctl = er32(RCTL);
3351
ef9b965a
JB		 3352 /* clear the affected bits */
3353 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3354
bc7f75fa
AK		 3355 if (netdev->flags & IFF_PROMISC) {
3356 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3357 /* Do not hardware filter VLANs in promisc mode */
3358 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3359 } else {
ef9b965a 3360 int count;
3d3a1676 3361
746b9f02
PM		 3362 if (netdev->flags & IFF_ALLMULTI) {
3363 rctl |= E1000_RCTL_MPE;
746b9f02 3364 } else {
e921eb1a 3365 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3366 * then we should just turn on promiscuous mode so
3367 * that we can at least receive multicast traffic
3368 */
3369 count = e1000e_write_mc_addr_list(netdev);
3370 if (count < 0)
3371 rctl |= E1000_RCTL_MPE;
746b9f02 3372 }
86d70e53 3373 e1000e_vlan_filter_enable(adapter);
e921eb1a 3374 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3375 * sufficient space to store all the addresses then enable
3376 * unicast promiscuous mode
bc7f75fa 3377 */
ef9b965a
JB		 3378 count = e1000e_write_uc_addr_list(netdev);
3379 if (count < 0)
3380 rctl |= E1000_RCTL_UPE;
bc7f75fa 3381 }
86d70e53 3382
ef9b965a
JB		 3383 ew32(RCTL, rctl);
3384
f646968f 3385 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3386 e1000e_vlan_strip_enable(adapter);
3387 else
3388 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3389}
3390
70495a50
BA		 3391static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3392{
3393 struct e1000_hw *hw = &adapter->hw;
3394 u32 mrqc, rxcsum;
3395 int i;
3396 static const u32 rsskey[10] = {
3397 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3398 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3399 };
3400
3401 /* Fill out hash function seed */
3402 for (i = 0; i < 10; i++)
3403 ew32(RSSRK(i), rsskey[i]);
3404
3405 /* Direct all traffic to queue 0 */
3406 for (i = 0; i < 32; i++)
3407 ew32(RETA(i), 0);
3408
e921eb1a 3409 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3410 * descriptor on writeback.
3411 */
3412 rxcsum = er32(RXCSUM);
3413 rxcsum |= E1000_RXCSUM_PCSD;
3414
3415 ew32(RXCSUM, rxcsum);
3416
3417 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3418 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3419 E1000_MRQC_RSS_FIELD_IPV6 |
3420 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3422
3423 ew32(MRQC, mrqc);
3424}
3425
b67e1913
BA		 3426/**
3427 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3428 * @adapter: board private structure
3429 * @timinca: pointer to returned time increment attributes
3430 *
3431 * Get attributes for incrementing the System Time Register SYSTIML/H at
3432 * the default base frequency, and set the cyclecounter shift value.
3433 **/
d89777bf 3434s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3435{
3436 struct e1000_hw *hw = &adapter->hw;
3437 u32 incvalue, incperiod, shift;
3438
3439 /* Make sure clock is enabled on I217 before checking the frequency */
3440 if ((hw->mac.type == e1000_pch_lpt) &&
3441 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3442 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3443 u32 fextnvm7 = er32(FEXTNVM7);
3444
3445 if (!(fextnvm7 & (1 << 0))) {
3446 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3447 e1e_flush();
3448 }
3449 }
3450
3451 switch (hw->mac.type) {
3452 case e1000_pch2lan:
3453 case e1000_pch_lpt:
3454 /* On I217, the clock frequency is 25MHz or 96MHz as
3455 * indicated by the System Clock Frequency Indication
3456 */
3457 if ((hw->mac.type != e1000_pch_lpt) ||
3458 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3459 /* Stable 96MHz frequency */
3460 incperiod = INCPERIOD_96MHz;
3461 incvalue = INCVALUE_96MHz;
3462 shift = INCVALUE_SHIFT_96MHz;
3463 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3464 break;
3465 }
3466 /* fall-through */
3467 case e1000_82574:
3468 case e1000_82583:
3469 /* Stable 25MHz frequency */
3470 incperiod = INCPERIOD_25MHz;
3471 incvalue = INCVALUE_25MHz;
3472 shift = INCVALUE_SHIFT_25MHz;
3473 adapter->cc.shift = shift;
3474 break;
3475 default:
3476 return -EINVAL;
3477 }
3478
3479 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3480 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3481
3482 return 0;
3483}
3484
3485/**
3486 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3487 * @adapter: board private structure
3488 *
3489 * Outgoing time stamping can be enabled and disabled. Play nice and
3490 * disable it when requested, although it shouldn't cause any overhead
3491 * when no packet needs it. At most one packet in the queue may be
3492 * marked for time stamping, otherwise it would be impossible to tell
3493 * for sure to which packet the hardware time stamp belongs.
3494 *
3495 * Incoming time stamping has to be configured via the hardware filters.
3496 * Not all combinations are supported, in particular event type has to be
3497 * specified. Matching the kind of event packet is not supported, with the
3498 * exception of "all V2 events regardless of level 2 or 4".
3499 **/
62d7e3a2
BH		 3500static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3501 struct hwtstamp_config *config)
b67e1913
BA		 3502{
3503 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3504 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3505 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3506 u32 rxmtrl = 0;
3507 u16 rxudp = 0;
3508 bool is_l4 = false;
3509 bool is_l2 = false;
b67e1913
BA		 3510 u32 regval;
3511 s32 ret_val;
3512
3513 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3514 return -EINVAL;
3515
3516 /* flags reserved for future extensions - must be zero */
3517 if (config->flags)
3518 return -EINVAL;
3519
3520 switch (config->tx_type) {
3521 case HWTSTAMP_TX_OFF:
3522 tsync_tx_ctl = 0;
3523 break;
3524 case HWTSTAMP_TX_ON:
3525 break;
3526 default:
3527 return -ERANGE;
3528 }
3529
3530 switch (config->rx_filter) {
3531 case HWTSTAMP_FILTER_NONE:
3532 tsync_rx_ctl = 0;
3533 break;
d89777bf
BA		 3534 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3535 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3536 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3537 is_l4 = true;
3538 break;
3539 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3540 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3541 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3542 is_l4 = true;
3543 break;
3544 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3545 /* Also time stamps V2 L2 Path Delay Request/Response */
3546 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3547 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3548 is_l2 = true;
3549 break;
3550 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3551 /* Also time stamps V2 L2 Path Delay Request/Response. */
3552 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3553 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3554 is_l2 = true;
3555 break;
3556 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3557 /* Hardware cannot filter just V2 L4 Sync messages;
3558 * fall-through to V2 (both L2 and L4) Sync.
3559 */
3560 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3561 /* Also time stamps V2 Path Delay Request/Response. */
3562 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3563 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3564 is_l2 = true;
3565 is_l4 = true;
3566 break;
3567 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3568 /* Hardware cannot filter just V2 L4 Delay Request messages;
3569 * fall-through to V2 (both L2 and L4) Delay Request.
3570 */
3571 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3572 /* Also time stamps V2 Path Delay Request/Response. */
3573 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3574 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3575 is_l2 = true;
3576 is_l4 = true;
3577 break;
3578 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3579 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3580 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3581 * fall-through to all V2 (both L2 and L4) Events.
3582 */
3583 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3584 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3585 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3586 is_l2 = true;
3587 is_l4 = true;
3588 break;
3589 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3590 /* For V1, the hardware can only filter Sync messages or
3591 * Delay Request messages but not both so fall-through to
3592 * time stamp all packets.
3593 */
b67e1913 3594 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3595 is_l2 = true;
3596 is_l4 = true;
b67e1913
BA		 3597 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3598 config->rx_filter = HWTSTAMP_FILTER_ALL;
3599 break;
3600 default:
3601 return -ERANGE;
3602 }
3603
62d7e3a2
BH		 3604 adapter->hwtstamp_config = *config;
3605
b67e1913
BA		 3606 /* enable/disable Tx h/w time stamping */
3607 regval = er32(TSYNCTXCTL);
3608 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3609 regval |= tsync_tx_ctl;
3610 ew32(TSYNCTXCTL, regval);
3611 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3612 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3613 e_err("Timesync Tx Control register not set as expected\n");
3614 return -EAGAIN;
3615 }
3616
3617 /* enable/disable Rx h/w time stamping */
3618 regval = er32(TSYNCRXCTL);
3619 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3620 regval |= tsync_rx_ctl;
3621 ew32(TSYNCRXCTL, regval);
3622 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3623 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3624 (regval & (E1000_TSYNCRXCTL_ENABLED |
3625 E1000_TSYNCRXCTL_TYPE_MASK))) {
3626 e_err("Timesync Rx Control register not set as expected\n");
3627 return -EAGAIN;
3628 }
3629
d89777bf
BA		 3630 /* L2: define ethertype filter for time stamped packets */
3631 if (is_l2)
3632 rxmtrl |= ETH_P_1588;
3633
3634 /* define which PTP packets get time stamped */
3635 ew32(RXMTRL, rxmtrl);
3636
3637 /* Filter by destination port */
3638 if (is_l4) {
3639 rxudp = PTP_EV_PORT;
3640 cpu_to_be16s(&rxudp);
3641 }
3642 ew32(RXUDP, rxudp);
3643
3644 e1e_flush();
3645
b67e1913 3646 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3647 er32(RXSTMPH);
3648 er32(TXSTMPH);
b67e1913
BA		 3649
3650 /* Get and set the System Time Register SYSTIM base frequency */
3651 ret_val = e1000e_get_base_timinca(adapter, &regval);
3652 if (ret_val)
3653 return ret_val;
3654 ew32(TIMINCA, regval);
3655
3656 /* reset the ns time counter */
3657 timecounter_init(&adapter->tc, &adapter->cc,
3658 ktime_to_ns(ktime_get_real()));
3659
3660 return 0;
3661}
3662
bc7f75fa 3663/**
ad68076e 3664 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3665 * @adapter: private board structure
3666 **/
3667static void e1000_configure(struct e1000_adapter *adapter)
3668{
55aa6985
BA		 3669 struct e1000_ring *rx_ring = adapter->rx_ring;
3670
ef9b965a 3671 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3672
3673 e1000_restore_vlan(adapter);
cd791618 3674 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3675
3676 e1000_configure_tx(adapter);
70495a50
BA		 3677
3678 if (adapter->netdev->features & NETIF_F_RXHASH)
3679 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3680 e1000_setup_rctl(adapter);
3681 e1000_configure_rx(adapter);
55aa6985 3682 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3683}
3684
3685/**
3686 * e1000e_power_up_phy - restore link in case the phy was powered down
3687 * @adapter: address of board private structure
3688 *
3689 * The phy may be powered down to save power and turn off link when the
3690 * driver is unloaded and wake on lan is not enabled (among others)
3691 * *** this routine MUST be followed by a call to e1000e_reset ***
3692 **/
3693void e1000e_power_up_phy(struct e1000_adapter *adapter)
3694{
17f208de
BA		 3695 if (adapter->hw.phy.ops.power_up)
3696 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3697
3698 adapter->hw.mac.ops.setup_link(&adapter->hw);
3699}
3700
3701/**
3702 * e1000_power_down_phy - Power down the PHY
3703 *
17f208de
BA		 3704 * Power down the PHY so no link is implied when interface is down.
3705 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3706 */
3707static void e1000_power_down_phy(struct e1000_adapter *adapter)
3708{
17f208de
BA		 3709 if (adapter->hw.phy.ops.power_down)
3710 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3711}
3712
3713/**
3714 * e1000e_reset - bring the hardware into a known good state
3715 *
3716 * This function boots the hardware and enables some settings that
3717 * require a configuration cycle of the hardware - those cannot be
3718 * set/changed during runtime. After reset the device needs to be
ad68076e 3719 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3720 */
3721void e1000e_reset(struct e1000_adapter *adapter)
3722{
3723 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3724 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3725 struct e1000_hw *hw = &adapter->hw;
3726 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3727 u32 pba = adapter->pba;
bc7f75fa
AK		 3728 u16 hwm;
3729
ad68076e 3730 /* reset Packet Buffer Allocation to default */
318a94d6 3731 ew32(PBA, pba);
df762464 3732
318a94d6 3733 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3734 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3735 * large enough to accommodate two full transmit packets,
3736 * rounded up to the next 1KB and expressed in KB. Likewise,
3737 * the Rx FIFO should be large enough to accommodate at least
3738 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3739 * expressed in KB.
3740 */
df762464 3741 pba = er32(PBA);
bc7f75fa 3742 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3743 tx_space = pba >> 16;
bc7f75fa 3744 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3745 pba &= 0xffff;
e921eb1a 3746 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3747 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3748 */
3749 min_tx_space = (adapter->max_frame_size +
e5fe2541 3750 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3751 min_tx_space = ALIGN(min_tx_space, 1024);
3752 min_tx_space >>= 10;
3753 /* software strips receive CRC, so leave room for it */
318a94d6 3754 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3755 min_rx_space = ALIGN(min_rx_space, 1024);
3756 min_rx_space >>= 10;
3757
e921eb1a 3758 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3759 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3760 * allocation, take space away from current Rx allocation
3761 */
df762464
AK		 3762 if ((tx_space < min_tx_space) &&
3763 ((min_tx_space - tx_space) < pba)) {
3764 pba -= min_tx_space - tx_space;
bc7f75fa 3765
e921eb1a 3766 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3767 * adjustment
ad68076e 3768 */
79d4e908 3769 if (pba < min_rx_space)
df762464 3770 pba = min_rx_space;
bc7f75fa 3771 }
df762464
AK		 3772
3773 ew32(PBA, pba);
bc7f75fa
AK		 3774 }
3775
e921eb1a 3776 /* flow control settings
ad68076e 3777 *
38eb394e 3778 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3779 * (or the size used for early receive) above it in the Rx FIFO.
3780 * Set it to the lower of:
3781 * - 90% of the Rx FIFO size, and
38eb394e 3782 * - the full Rx FIFO size minus one full frame
ad68076e 3783 */
d3738bb8
BA		 3784 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3785 fc->pause_time = 0xFFFF;
3786 else
3787 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3788 fc->send_xon = true;
d3738bb8
BA		 3789 fc->current_mode = fc->requested_mode;
3790
3791 switch (hw->mac.type) {
79d4e908
BA		 3792 case e1000_ich9lan:
3793 case e1000_ich10lan:
3794 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3795 pba = 14;
3796 ew32(PBA, pba);
3797 fc->high_water = 0x2800;
3798 fc->low_water = fc->high_water - 8;
3799 break;
3800 }
3801 /* fall-through */
d3738bb8 3802 default:
79d4e908
BA		 3803 hwm = min(((pba << 10) * 9 / 10),
3804 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3805
e80bd1d1 3806 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3807 fc->low_water = fc->high_water - 8;
3808 break;
3809 case e1000_pchlan:
e921eb1a 3810 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3811 * loads. If hangs persist, try disabling Tx flow control.
3812 */
3813 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3814 fc->high_water = 0x3500;
e80bd1d1 3815 fc->low_water = 0x1500;
38eb394e
BA		 3816 } else {
3817 fc->high_water = 0x5000;
e80bd1d1 3818 fc->low_water = 0x3000;
38eb394e 3819 }
a305595b 3820 fc->refresh_time = 0x1000;
d3738bb8
BA		 3821 break;
3822 case e1000_pch2lan:
2fbe4526 3823 case e1000_pch_lpt:
d3738bb8 3824 fc->refresh_time = 0x0400;
347b5201
BA		 3825
3826 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3827 fc->high_water = 0x05C20;
3828 fc->low_water = 0x05048;
3829 fc->pause_time = 0x0650;
3830 break;
828bac87 3831 }
347b5201 3832
ce345e08
BA		 3833 pba = 14;
3834 ew32(PBA, pba);
347b5201
BA		 3835 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3836 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3837 break;
38eb394e 3838 }
bc7f75fa 3839
e921eb1a 3840 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3841 * maximum size per Tx descriptor limited only to the transmit
3842 * allocation of the packet buffer minus 96 bytes with an upper
3843 * limit of 24KB due to receive synchronization limitations.
3844 */
3845 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3846 24 << 10);
3847
e921eb1a 3848 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3849 * fit in receive buffer.
828bac87
BA		 3850 */
3851 if (adapter->itr_setting & 0x3) {
79d4e908 3852 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3853 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3854 dev_info(&adapter->pdev->dev,
17e813ec 3855 "Interrupt Throttle Rate off\n");
828bac87 3856 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3857 e1000e_write_itr(adapter, 0);
828bac87
BA		 3858 }
3859 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3860 dev_info(&adapter->pdev->dev,
17e813ec 3861 "Interrupt Throttle Rate on\n");
828bac87
BA		 3862 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3863 adapter->itr = 20000;
22a4cca2 3864 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3865 }
3866 }
3867
bc7f75fa
AK		 3868 /* Allow time for pending master requests to run */
3869 mac->ops.reset_hw(hw);
97ac8cae 3870
e921eb1a 3871 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3872 * that the network interface is in control
3873 */
c43bc57e 3874 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3875 e1000e_get_hw_control(adapter);
97ac8cae 3876
bc7f75fa
AK		 3877 ew32(WUC, 0);
3878
3879 if (mac->ops.init_hw(hw))
44defeb3 3880 e_err("Hardware Error\n");
bc7f75fa
AK		 3881
3882 e1000_update_mng_vlan(adapter);
3883
3884 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3885 ew32(VET, ETH_P_8021Q);
3886
3887 e1000e_reset_adaptive(hw);
31dbe5b4 3888
b67e1913 3889 /* initialize systim and reset the ns time counter */
62d7e3a2 3890 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 3891
d495bcb8
BA		 3892 /* Set EEE advertisement as appropriate */
3893 if (adapter->flags2 & FLAG2_HAS_EEE) {
3894 s32 ret_val;
3895 u16 adv_addr;
3896
3897 switch (hw->phy.type) {
3898 case e1000_phy_82579:
3899 adv_addr = I82579_EEE_ADVERTISEMENT;
3900 break;
3901 case e1000_phy_i217:
3902 adv_addr = I217_EEE_ADVERTISEMENT;
3903 break;
3904 default:
3905 dev_err(&adapter->pdev->dev,
3906 "Invalid PHY type setting EEE advertisement\n");
3907 return;
3908 }
3909
3910 ret_val = hw->phy.ops.acquire(hw);
3911 if (ret_val) {
3912 dev_err(&adapter->pdev->dev,
3913 "EEE advertisement - unable to acquire PHY\n");
3914 return;
3915 }
3916
3917 e1000_write_emi_reg_locked(hw, adv_addr,
3918 hw->dev_spec.ich8lan.eee_disable ?
3919 0 : adapter->eee_advert);
3920
3921 hw->phy.ops.release(hw);
3922 }
3923
31dbe5b4 3924 if (!netif_running(adapter->netdev) &&
28002099 3925 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 3926 e1000_power_down_phy(adapter);
31dbe5b4 3927
bc7f75fa
AK		 3928 e1000_get_phy_info(hw);
3929
918d7197
BA		 3930 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3931 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3932 u16 phy_data = 0;
e921eb1a 3933 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3934 * the return value of this function because there is nothing
ad68076e
BA		 3935 * different we would do if it failed
3936 */
bc7f75fa
AK		 3937 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3938 phy_data &= ~IGP02E1000_PM_SPD;
3939 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3940 }
bc7f75fa
AK		 3941}
3942
3943int e1000e_up(struct e1000_adapter *adapter)
3944{
3945 struct e1000_hw *hw = &adapter->hw;
3946
3947 /* hardware has been reset, we need to reload some things */
3948 e1000_configure(adapter);
3949
3950 clear_bit(__E1000_DOWN, &adapter->state);
3951
4662e82b
BA		 3952 if (adapter->msix_entries)
3953 e1000_configure_msix(adapter);
bc7f75fa
AK		 3954 e1000_irq_enable(adapter);
3955
400484fa 3956 netif_start_queue(adapter->netdev);
4cb9be7a 3957
bc7f75fa 3958 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3959 if (adapter->msix_entries)
3960 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3961 else
3962 ew32(ICS, E1000_ICS_LSC);
3963
bc7f75fa
AK		 3964 return 0;
3965}
3966
713b3c9e
JB		 3967static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3968{
3969 struct e1000_hw *hw = &adapter->hw;
3970
3971 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3972 return;
3973
3974 /* flush pending descriptor writebacks to memory */
3975 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3976 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3977
3978 /* execute the writes immediately */
3979 e1e_flush();
bf03085f 3980
e921eb1a 3981 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3982 * write is successful
3983 */
3984 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3985 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3986
3987 /* execute the writes immediately */
3988 e1e_flush();
3989}
3990
67fd4fcb
JK		 3991static void e1000e_update_stats(struct e1000_adapter *adapter);
3992
28002099
DE		 3993/**
3994 * e1000e_down - quiesce the device and optionally reset the hardware
3995 * @adapter: board private structure
3996 * @reset: boolean flag to reset the hardware or not
3997 */
3998void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 3999{
4000 struct net_device *netdev = adapter->netdev;
4001 struct e1000_hw *hw = &adapter->hw;
4002 u32 tctl, rctl;
4003
e921eb1a 4004 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4005 * reschedule our watchdog timer
4006 */
bc7f75fa
AK		 4007 set_bit(__E1000_DOWN, &adapter->state);
4008
4009 /* disable receives in the hardware */
4010 rctl = er32(RCTL);
7f99ae63
BA		 4011 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4012 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4013 /* flush and sleep below */
4014
4cb9be7a 4015 netif_stop_queue(netdev);
bc7f75fa
AK		 4016
4017 /* disable transmits in the hardware */
4018 tctl = er32(TCTL);
4019 tctl &= ~E1000_TCTL_EN;
4020 ew32(TCTL, tctl);
7f99ae63 4021
bc7f75fa
AK		 4022 /* flush both disables and wait for them to finish */
4023 e1e_flush();
1bba4386 4024 usleep_range(10000, 20000);
bc7f75fa 4025
bc7f75fa
AK		 4026 e1000_irq_disable(adapter);
4027
a3b87a4c
BA		 4028 napi_synchronize(&adapter->napi);
4029
bc7f75fa
AK		 4030 del_timer_sync(&adapter->watchdog_timer);
4031 del_timer_sync(&adapter->phy_info_timer);
4032
bc7f75fa 4033 netif_carrier_off(netdev);
67fd4fcb
JK		 4034
4035 spin_lock(&adapter->stats64_lock);
4036 e1000e_update_stats(adapter);
4037 spin_unlock(&adapter->stats64_lock);
4038
400484fa 4039 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4040 e1000_clean_tx_ring(adapter->tx_ring);
4041 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4042
bc7f75fa
AK		 4043 adapter->link_speed = 0;
4044 adapter->link_duplex = 0;
4045
da1e2046
BA		 4046 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4047 if ((hw->mac.type >= e1000_pch2lan) &&
4048 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4049 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4050 e_dbg("failed to disable jumbo frame workaround mode\n");
4051
28002099 4052 if (reset && !pci_channel_offline(adapter->pdev))
52cc3086 4053 e1000e_reset(adapter);
bc7f75fa
AK		 4054}
4055
4056void e1000e_reinit_locked(struct e1000_adapter *adapter)
4057{
4058 might_sleep();
4059 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4060 usleep_range(1000, 2000);
28002099 4061 e1000e_down(adapter, true);
bc7f75fa
AK		 4062 e1000e_up(adapter);
4063 clear_bit(__E1000_RESETTING, &adapter->state);
4064}
4065
b67e1913
BA		 4066/**
4067 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4068 * @cc: cyclecounter structure
4069 **/
4070static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4071{
4072 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4073 cc);
4074 struct e1000_hw *hw = &adapter->hw;
4075 cycle_t systim;
4076
4077 /* latch SYSTIMH on read of SYSTIML */
4078 systim = (cycle_t)er32(SYSTIML);
4079 systim |= (cycle_t)er32(SYSTIMH) << 32;
4080
4081 return systim;
4082}
4083
bc7f75fa
AK		 4084/**
4085 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4086 * @adapter: board private structure to initialize
4087 *
4088 * e1000_sw_init initializes the Adapter private data structure.
4089 * Fields are initialized based on PCI device information and
4090 * OS network device settings (MTU size).
4091 **/
9f9a12f8 4092static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4093{
bc7f75fa
AK		 4094 struct net_device *netdev = adapter->netdev;
4095
4096 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4097 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4098 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4099 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4100 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4101 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4102
67fd4fcb
JK		 4103 spin_lock_init(&adapter->stats64_lock);
4104
4662e82b 4105 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4106
4662e82b
BA		 4107 if (e1000_alloc_queues(adapter))
4108 return -ENOMEM;
bc7f75fa 4109
b67e1913
BA		 4110 /* Setup hardware time stamping cyclecounter */
4111 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4112 adapter->cc.read = e1000e_cyclecounter_read;
4113 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4114 adapter->cc.mult = 1;
4115 /* cc.shift set in e1000e_get_base_tininca() */
4116
4117 spin_lock_init(&adapter->systim_lock);
4118 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4119 }
4120
bc7f75fa 4121 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4122 e1000_irq_disable(adapter);
4123
bc7f75fa
AK		 4124 set_bit(__E1000_DOWN, &adapter->state);
4125 return 0;
bc7f75fa
AK		 4126}
4127
f8d59f78
BA		 4128/**
4129 * e1000_intr_msi_test - Interrupt Handler
4130 * @irq: interrupt number
4131 * @data: pointer to a network interface device structure
4132 **/
8bb62869 4133static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4134{
4135 struct net_device *netdev = data;
4136 struct e1000_adapter *adapter = netdev_priv(netdev);
4137 struct e1000_hw *hw = &adapter->hw;
4138 u32 icr = er32(ICR);
4139
3bb99fe2 4140 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4141 if (icr & E1000_ICR_RXSEQ) {
4142 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4143 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4144 * interrupt is handled.
4145 */
f8d59f78
BA		 4146 wmb();
4147 }
4148
4149 return IRQ_HANDLED;
4150}
4151
4152/**
4153 * e1000_test_msi_interrupt - Returns 0 for successful test
4154 * @adapter: board private struct
4155 *
4156 * code flow taken from tg3.c
4157 **/
4158static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4159{
4160 struct net_device *netdev = adapter->netdev;
4161 struct e1000_hw *hw = &adapter->hw;
4162 int err;
4163
4164 /* poll_enable hasn't been called yet, so don't need disable */
4165 /* clear any pending events */
4166 er32(ICR);
4167
4168 /* free the real vector and request a test handler */
4169 e1000_free_irq(adapter);
4662e82b 4170 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4171
4172 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4173 * MSI irq handler will unset this flag
4174 */
f8d59f78
BA		 4175 adapter->flags |= FLAG_MSI_TEST_FAILED;
4176
4177 err = pci_enable_msi(adapter->pdev);
4178 if (err)
4179 goto msi_test_failed;
4180
a0607fd3 4181 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4182 netdev->name, netdev);
4183 if (err) {
4184 pci_disable_msi(adapter->pdev);
4185 goto msi_test_failed;
4186 }
4187
e921eb1a 4188 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4189 * interrupt.
4190 */
f8d59f78
BA		 4191 wmb();
4192
4193 e1000_irq_enable(adapter);
4194
4195 /* fire an unusual interrupt on the test handler */
4196 ew32(ICS, E1000_ICS_RXSEQ);
4197 e1e_flush();
569a3aff 4198 msleep(100);
f8d59f78
BA		 4199
4200 e1000_irq_disable(adapter);
4201
bc76329d 4202 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4203
4204 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4205 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4206 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4207 } else {
068e8a30 4208 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4209 }
f8d59f78
BA		 4210
4211 free_irq(adapter->pdev->irq, netdev);
4212 pci_disable_msi(adapter->pdev);
4213
f8d59f78 4214msi_test_failed:
4662e82b 4215 e1000e_set_interrupt_capability(adapter);
068e8a30 4216 return e1000_request_irq(adapter);
f8d59f78
BA		 4217}
4218
4219/**
4220 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4221 * @adapter: board private struct
4222 *
4223 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4224 **/
4225static int e1000_test_msi(struct e1000_adapter *adapter)
4226{
4227 int err;
4228 u16 pci_cmd;
4229
4230 if (!(adapter->flags & FLAG_MSI_ENABLED))
4231 return 0;
4232
4233 /* disable SERR in case the MSI write causes a master abort */
4234 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4235 if (pci_cmd & PCI_COMMAND_SERR)
4236 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4237 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4238
4239 err = e1000_test_msi_interrupt(adapter);
4240
36f2407f
DN		 4241 /* re-enable SERR */
4242 if (pci_cmd & PCI_COMMAND_SERR) {
4243 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4244 pci_cmd |= PCI_COMMAND_SERR;
4245 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4246 }
f8d59f78 4247
f8d59f78
BA		 4248 return err;
4249}
4250
bc7f75fa
AK		 4251/**
4252 * e1000_open - Called when a network interface is made active
4253 * @netdev: network interface device structure
4254 *
4255 * Returns 0 on success, negative value on failure
4256 *
4257 * The open entry point is called when a network interface is made
4258 * active by the system (IFF_UP). At this point all resources needed
4259 * for transmit and receive operations are allocated, the interrupt
4260 * handler is registered with the OS, the watchdog timer is started,
4261 * and the stack is notified that the interface is ready.
4262 **/
4263static int e1000_open(struct net_device *netdev)
4264{
4265 struct e1000_adapter *adapter = netdev_priv(netdev);
4266 struct e1000_hw *hw = &adapter->hw;
23606cf5 4267 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4268 int err;
4269
4270 /* disallow open during test */
4271 if (test_bit(__E1000_TESTING, &adapter->state))
4272 return -EBUSY;
4273
23606cf5
RW		 4274 pm_runtime_get_sync(&pdev->dev);
4275
9c563d20
JB		 4276 netif_carrier_off(netdev);
4277
bc7f75fa 4278 /* allocate transmit descriptors */
55aa6985 4279 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4280 if (err)
4281 goto err_setup_tx;
4282
4283 /* allocate receive descriptors */
55aa6985 4284 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4285 if (err)
4286 goto err_setup_rx;
4287
e921eb1a 4288 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4289 * interface is now open and reset the part to a known state.
4290 */
4291 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4292 e1000e_get_hw_control(adapter);
11b08be8
BA		 4293 e1000e_reset(adapter);
4294 }
4295
bc7f75fa
AK		 4296 e1000e_power_up_phy(adapter);
4297
4298 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4299 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4300 e1000_update_mng_vlan(adapter);
4301
79d4e908 4302 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4303 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4304 PM_QOS_DEFAULT_VALUE);
c128ec29 4305
e921eb1a 4306 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4307 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4308 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4309 * clean_rx handler before we do so.
4310 */
bc7f75fa
AK		 4311 e1000_configure(adapter);
4312
4313 err = e1000_request_irq(adapter);
4314 if (err)
4315 goto err_req_irq;
4316
e921eb1a 4317 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4318 * ignore e1000e MSI messages, which means we need to test our MSI
4319 * interrupt now
4320 */
4662e82b 4321 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4322 err = e1000_test_msi(adapter);
4323 if (err) {
4324 e_err("Interrupt allocation failed\n");
4325 goto err_req_irq;
4326 }
4327 }
4328
bc7f75fa
AK		 4329 /* From here on the code is the same as e1000e_up() */
4330 clear_bit(__E1000_DOWN, &adapter->state);
4331
4332 napi_enable(&adapter->napi);
4333
4334 e1000_irq_enable(adapter);
4335
09357b00 4336 adapter->tx_hang_recheck = false;
4cb9be7a 4337 netif_start_queue(netdev);
d55b53ff 4338
66148bab 4339 hw->mac.get_link_status = true;
23606cf5
RW		 4340 pm_runtime_put(&pdev->dev);
4341
bc7f75fa 4342 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4343 if (adapter->msix_entries)
4344 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4345 else
4346 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4347
4348 return 0;
4349
4350err_req_irq:
31dbe5b4 4351 e1000e_release_hw_control(adapter);
bc7f75fa 4352 e1000_power_down_phy(adapter);
55aa6985 4353 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4354err_setup_rx:
55aa6985 4355 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4356err_setup_tx:
4357 e1000e_reset(adapter);
23606cf5 4358 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4359
4360 return err;
4361}
4362
4363/**
4364 * e1000_close - Disables a network interface
4365 * @netdev: network interface device structure
4366 *
4367 * Returns 0, this is not allowed to fail
4368 *
4369 * The close entry point is called when an interface is de-activated
4370 * by the OS. The hardware is still under the drivers control, but
4371 * needs to be disabled. A global MAC reset is issued to stop the
4372 * hardware, and all transmit and receive resources are freed.
4373 **/
4374static int e1000_close(struct net_device *netdev)
4375{
4376 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4377 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4378 int count = E1000_CHECK_RESET_COUNT;
4379
4380 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4381 usleep_range(10000, 20000);
bc7f75fa
AK		 4382
4383 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4384
4385 pm_runtime_get_sync(&pdev->dev);
4386
4387 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4388 e1000e_down(adapter, true);
23606cf5 4389 e1000_free_irq(adapter);
63eb48f1
DE		 4390
4391 /* Link status message must follow this format */
4392 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4393 }
a3b87a4c
BA		 4394
4395 napi_disable(&adapter->napi);
4396
55aa6985
BA		 4397 e1000e_free_tx_resources(adapter->tx_ring);
4398 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4399
e921eb1a 4400 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4401 * the same ID is registered on the host OS (let 8021q kill it)
4402 */
e5fe2541 4403 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4404 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4405 adapter->mng_vlan_id);
bc7f75fa 4406
e921eb1a 4407 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4408 * interface is now closed
4409 */
31dbe5b4
BA		 4410 if ((adapter->flags & FLAG_HAS_AMT) &&
4411 !test_bit(__E1000_TESTING, &adapter->state))
4412 e1000e_release_hw_control(adapter);
bc7f75fa 4413
3e35d991 4414 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4415
23606cf5
RW		 4416 pm_runtime_put_sync(&pdev->dev);
4417
bc7f75fa
AK		 4418 return 0;
4419}
fc830b78 4420
bc7f75fa
AK		 4421/**
4422 * e1000_set_mac - Change the Ethernet Address of the NIC
4423 * @netdev: network interface device structure
4424 * @p: pointer to an address structure
4425 *
4426 * Returns 0 on success, negative on failure
4427 **/
4428static int e1000_set_mac(struct net_device *netdev, void *p)
4429{
4430 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4431 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4432 struct sockaddr *addr = p;
4433
4434 if (!is_valid_ether_addr(addr->sa_data))
4435 return -EADDRNOTAVAIL;
4436
4437 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4438 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4439
69e1e019 4440 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4441
4442 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4443 /* activate the work around */
4444 e1000e_set_laa_state_82571(&adapter->hw, 1);
4445
e921eb1a 4446 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4447 * between the time RAR[0] gets clobbered and the time it
4448 * gets fixed (in e1000_watchdog), the actual LAA is in one
4449 * of the RARs and no incoming packets directed to this port
4450 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4451 * RAR[14]
4452 */
69e1e019
BA		 4453 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4454 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4455 }
4456
4457 return 0;
4458}
4459
a8f88ff5
JB		 4460/**
4461 * e1000e_update_phy_task - work thread to update phy
4462 * @work: pointer to our work struct
4463 *
4464 * this worker thread exists because we must acquire a
4465 * semaphore to read the phy, which we could msleep while
4466 * waiting for it, and we can't msleep in a timer.
4467 **/
4468static void e1000e_update_phy_task(struct work_struct *work)
4469{
4470 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4471 struct e1000_adapter,
4472 update_phy_task);
a03206ed 4473 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4474
4475 if (test_bit(__E1000_DOWN, &adapter->state))
4476 return;
4477
a03206ed
DE		 4478 e1000_get_phy_info(hw);
4479
4480 /* Enable EEE on 82579 after link up */
4481 if (hw->phy.type == e1000_phy_82579)
4482 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4483}
4484
e921eb1a
BA		 4485/**
4486 * e1000_update_phy_info - timre call-back to update PHY info
4487 * @data: pointer to adapter cast into an unsigned long
4488 *
ad68076e
BA		 4489 * Need to wait a few seconds after link up to get diagnostic information from
4490 * the phy
e921eb1a 4491 **/
bc7f75fa
AK		 4492static void e1000_update_phy_info(unsigned long data)
4493{
53aa82da 4494 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4495
4496 if (test_bit(__E1000_DOWN, &adapter->state))
4497 return;
4498
a8f88ff5 4499 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4500}
4501
8c7bbb92
BA		 4502/**
4503 * e1000e_update_phy_stats - Update the PHY statistics counters
4504 * @adapter: board private structure
2b6b168d
BA		 4505 *
4506 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4507 **/
4508static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4509{
4510 struct e1000_hw *hw = &adapter->hw;
4511 s32 ret_val;
4512 u16 phy_data;
4513
4514 ret_val = hw->phy.ops.acquire(hw);
4515 if (ret_val)
4516 return;
4517
e921eb1a 4518 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4519 * If not, set to the page with the PHY status registers.
4520 */
2b6b168d 4521 hw->phy.addr = 1;
8c7bbb92
BA		 4522 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4523 &phy_data);
4524 if (ret_val)
4525 goto release;
2b6b168d
BA		 4526 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4527 ret_val = hw->phy.ops.set_page(hw,
4528 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4529 if (ret_val)
4530 goto release;
4531 }
4532
8c7bbb92 4533 /* Single Collision Count */
2b6b168d
BA		 4534 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4535 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4536 if (!ret_val)
4537 adapter->stats.scc += phy_data;
4538
4539 /* Excessive Collision Count */
2b6b168d
BA		 4540 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4541 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4542 if (!ret_val)
4543 adapter->stats.ecol += phy_data;
4544
4545 /* Multiple Collision Count */
2b6b168d
BA		 4546 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4547 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4548 if (!ret_val)
4549 adapter->stats.mcc += phy_data;
4550
4551 /* Late Collision Count */
2b6b168d
BA		 4552 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4553 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4554 if (!ret_val)
4555 adapter->stats.latecol += phy_data;
4556
4557 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4558 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4559 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4560 if (!ret_val)
4561 hw->mac.collision_delta = phy_data;
4562
4563 /* Defer Count */
2b6b168d
BA		 4564 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4565 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4566 if (!ret_val)
4567 adapter->stats.dc += phy_data;
4568
4569 /* Transmit with no CRS */
2b6b168d
BA		 4570 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4571 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4572 if (!ret_val)
4573 adapter->stats.tncrs += phy_data;
4574
4575release:
4576 hw->phy.ops.release(hw);
4577}
4578
bc7f75fa
AK		 4579/**
4580 * e1000e_update_stats - Update the board statistics counters
4581 * @adapter: board private structure
4582 **/
67fd4fcb 4583static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4584{
7274c20f 4585 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4586 struct e1000_hw *hw = &adapter->hw;
4587 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4588
e921eb1a 4589 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4590 * connection is down.
4591 */
4592 if (adapter->link_speed == 0)
4593 return;
4594 if (pci_channel_offline(pdev))
4595 return;
4596
bc7f75fa
AK		 4597 adapter->stats.crcerrs += er32(CRCERRS);
4598 adapter->stats.gprc += er32(GPRC);
7c25769f 4599 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4600 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4601 adapter->stats.bprc += er32(BPRC);
4602 adapter->stats.mprc += er32(MPRC);
4603 adapter->stats.roc += er32(ROC);
4604
bc7f75fa 4605 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4606
4607 /* Half-duplex statistics */
4608 if (adapter->link_duplex == HALF_DUPLEX) {
4609 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4610 e1000e_update_phy_stats(adapter);
4611 } else {
4612 adapter->stats.scc += er32(SCC);
4613 adapter->stats.ecol += er32(ECOL);
4614 adapter->stats.mcc += er32(MCC);
4615 adapter->stats.latecol += er32(LATECOL);
4616 adapter->stats.dc += er32(DC);
4617
4618 hw->mac.collision_delta = er32(COLC);
4619
4620 if ((hw->mac.type != e1000_82574) &&
4621 (hw->mac.type != e1000_82583))
4622 adapter->stats.tncrs += er32(TNCRS);
4623 }
4624 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4625 }
8c7bbb92 4626
bc7f75fa
AK		 4627 adapter->stats.xonrxc += er32(XONRXC);
4628 adapter->stats.xontxc += er32(XONTXC);
4629 adapter->stats.xoffrxc += er32(XOFFRXC);
4630 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4631 adapter->stats.gptc += er32(GPTC);
7c25769f 4632 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4633 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4634 adapter->stats.rnbc += er32(RNBC);
4635 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4636
4637 adapter->stats.mptc += er32(MPTC);
4638 adapter->stats.bptc += er32(BPTC);
4639
4640 /* used for adaptive IFS */
4641
4642 hw->mac.tx_packet_delta = er32(TPT);
4643 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4644
4645 adapter->stats.algnerrc += er32(ALGNERRC);
4646 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4647 adapter->stats.cexterr += er32(CEXTERR);
4648 adapter->stats.tsctc += er32(TSCTC);
4649 adapter->stats.tsctfc += er32(TSCTFC);
4650
bc7f75fa 4651 /* Fill out the OS statistics structure */
7274c20f
AK		 4652 netdev->stats.multicast = adapter->stats.mprc;
4653 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4654
4655 /* Rx Errors */
4656
e921eb1a 4657 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4658 * our own version based on RUC and ROC
4659 */
7274c20f 4660 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4661 adapter->stats.crcerrs + adapter->stats.algnerrc +
4662 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4663 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4664 adapter->stats.roc;
7274c20f
AK		 4665 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4666 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4667 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4668
4669 /* Tx Errors */
f0ff4398 4670 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4671 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4672 netdev->stats.tx_window_errors = adapter->stats.latecol;
4673 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4674
4675 /* Tx Dropped needs to be maintained elsewhere */
4676
bc7f75fa
AK		 4677 /* Management Stats */
4678 adapter->stats.mgptc += er32(MGTPTC);
4679 adapter->stats.mgprc += er32(MGTPRC);
4680 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4681
4682 /* Correctable ECC Errors */
4683 if (hw->mac.type == e1000_pch_lpt) {
4684 u32 pbeccsts = er32(PBECCSTS);
4685 adapter->corr_errors +=
4686 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4687 adapter->uncorr_errors +=
4688 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4689 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4690 }
bc7f75fa
AK		 4691}
4692
7c25769f
BA		 4693/**
4694 * e1000_phy_read_status - Update the PHY register status snapshot
4695 * @adapter: board private structure
4696 **/
4697static void e1000_phy_read_status(struct e1000_adapter *adapter)
4698{
4699 struct e1000_hw *hw = &adapter->hw;
4700 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4701
97390ab8
BA		 4702 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4703 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4704 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4705 int ret_val;
4706
c2ade1a4
BA		 4707 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4708 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4709 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4710 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4711 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4712 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4713 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4714 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4715 if (ret_val)
44defeb3 4716 e_warn("Error reading PHY register\n");
7c25769f 4717 } else {
e921eb1a 4718 /* Do not read PHY registers if link is not up
7c25769f
BA		 4719 * Set values to typical power-on defaults
4720 */
4721 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4722 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4723 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4724 BMSR_ERCAP);
4725 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4726 ADVERTISE_ALL | ADVERTISE_CSMA);
4727 phy->lpa = 0;
4728 phy->expansion = EXPANSION_ENABLENPAGE;
4729 phy->ctrl1000 = ADVERTISE_1000FULL;
4730 phy->stat1000 = 0;
4731 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4732 }
7c25769f
BA		 4733}
4734
bc7f75fa
AK		 4735static void e1000_print_link_info(struct e1000_adapter *adapter)
4736{
bc7f75fa
AK		 4737 struct e1000_hw *hw = &adapter->hw;
4738 u32 ctrl = er32(CTRL);
4739
8f12fe86 4740 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4741 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4742 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4743 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4744 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4745 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4746 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4747}
4748
0c6bdb30 4749static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4750{
4751 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4752 bool link_active = false;
318a94d6
JK		 4753 s32 ret_val = 0;
4754
e921eb1a 4755 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4756 * Rx sequence error interrupt. get_link_status will stay
4757 * false until the check_for_link establishes link
4758 * for copper adapters ONLY
4759 */
4760 switch (hw->phy.media_type) {
4761 case e1000_media_type_copper:
4762 if (hw->mac.get_link_status) {
4763 ret_val = hw->mac.ops.check_for_link(hw);
4764 link_active = !hw->mac.get_link_status;
4765 } else {
3db1cd5c 4766 link_active = true;
318a94d6
JK		 4767 }
4768 break;
4769 case e1000_media_type_fiber:
4770 ret_val = hw->mac.ops.check_for_link(hw);
4771 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4772 break;
4773 case e1000_media_type_internal_serdes:
4774 ret_val = hw->mac.ops.check_for_link(hw);
4775 link_active = adapter->hw.mac.serdes_has_link;
4776 break;
4777 default:
4778 case e1000_media_type_unknown:
4779 break;
4780 }
4781
4782 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4783 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4784 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4785 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4786 }
4787
4788 return link_active;
4789}
4790
4791static void e1000e_enable_receives(struct e1000_adapter *adapter)
4792{
4793 /* make sure the receive unit is started */
4794 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4795 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4796 struct e1000_hw *hw = &adapter->hw;
4797 u32 rctl = er32(RCTL);
4798 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4799 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4800 }
4801}
4802
ff10e13c
CW		 4803static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4804{
4805 struct e1000_hw *hw = &adapter->hw;
4806
e921eb1a 4807 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4808 * for hung state and reset, if two calls return true
4809 */
4810 if (e1000_check_phy_82574(hw))
4811 adapter->phy_hang_count++;
4812 else
4813 adapter->phy_hang_count = 0;
4814
4815 if (adapter->phy_hang_count > 1) {
4816 adapter->phy_hang_count = 0;
d9554e96 4817 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 4818 schedule_work(&adapter->reset_task);
4819 }
4820}
4821
bc7f75fa
AK		 4822/**
4823 * e1000_watchdog - Timer Call-back
4824 * @data: pointer to adapter cast into an unsigned long
4825 **/
4826static void e1000_watchdog(unsigned long data)
4827{
53aa82da 4828 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4829
4830 /* Do the rest outside of interrupt context */
4831 schedule_work(&adapter->watchdog_task);
4832
4833 /* TODO: make this use queue_delayed_work() */
4834}
4835
4836static void e1000_watchdog_task(struct work_struct *work)
4837{
4838 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4839 struct e1000_adapter,
4840 watchdog_task);
bc7f75fa
AK		 4841 struct net_device *netdev = adapter->netdev;
4842 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4843 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4844 struct e1000_ring *tx_ring = adapter->tx_ring;
4845 struct e1000_hw *hw = &adapter->hw;
4846 u32 link, tctl;
bc7f75fa 4847
615b32af
JB		 4848 if (test_bit(__E1000_DOWN, &adapter->state))
4849 return;
4850
b405e8df 4851 link = e1000e_has_link(adapter);
318a94d6 4852 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4853 /* Cancel scheduled suspend requests. */
4854 pm_runtime_resume(netdev->dev.parent);
4855
318a94d6 4856 e1000e_enable_receives(adapter);
bc7f75fa 4857 goto link_up;
bc7f75fa
AK		 4858 }
4859
4860 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4861 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4862 e1000_update_mng_vlan(adapter);
4863
bc7f75fa
AK		 4864 if (link) {
4865 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4866 bool txb2b = true;
23606cf5
RW		 4867
4868 /* Cancel scheduled suspend requests. */
4869 pm_runtime_resume(netdev->dev.parent);
4870
318a94d6 4871 /* update snapshot of PHY registers on LSC */
7c25769f 4872 e1000_phy_read_status(adapter);
bc7f75fa 4873 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4874 &adapter->link_speed,
4875 &adapter->link_duplex);
bc7f75fa 4876 e1000_print_link_info(adapter);
e792cd91
KS		 4877
4878 /* check if SmartSpeed worked */
4879 e1000e_check_downshift(hw);
4880 if (phy->speed_downgraded)
4881 netdev_warn(netdev,
4882 "Link Speed was downgraded by SmartSpeed\n");
4883
e921eb1a 4884 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4885 * if link has autonegotiated at 10/100 half
4886 */
4887 if ((hw->phy.type == e1000_phy_igp_3 ||
4888 hw->phy.type == e1000_phy_bm) &&
138953bb 4889 hw->mac.autoneg &&
f4187b56
BA		 4890 (adapter->link_speed == SPEED_10 ||
4891 adapter->link_speed == SPEED_100) &&
4892 (adapter->link_duplex == HALF_DUPLEX)) {
4893 u16 autoneg_exp;
4894
c2ade1a4 4895 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4896
c2ade1a4 4897 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4898 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4899 }
4900
f49c57e1 4901 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4902 adapter->tx_timeout_factor = 1;
4903 switch (adapter->link_speed) {
4904 case SPEED_10:
3db1cd5c 4905 txb2b = false;
10f1b492 4906 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4907 break;
4908 case SPEED_100:
3db1cd5c 4909 txb2b = false;
4c86e0b9 4910 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4911 break;
4912 }
4913
e921eb1a 4914 /* workaround: re-program speed mode bit after
ad68076e
BA		 4915 * link-up event
4916 */
bc7f75fa
AK		 4917 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4918 !txb2b) {
4919 u32 tarc0;
e9ec2c0f 4920 tarc0 = er32(TARC(0));
bc7f75fa 4921 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4922 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4923 }
4924
e921eb1a 4925 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4926 * some hardware issues
4927 */
bc7f75fa
AK		 4928 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4929 switch (adapter->link_speed) {
4930 case SPEED_10:
4931 case SPEED_100:
44defeb3 4932 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4933 netdev->features &= ~NETIF_F_TSO;
4934 netdev->features &= ~NETIF_F_TSO6;
4935 break;
4936 case SPEED_1000:
4937 netdev->features |= NETIF_F_TSO;
4938 netdev->features |= NETIF_F_TSO6;
4939 break;
4940 default:
4941 /* oops */
4942 break;
4943 }
4944 }
4945
e921eb1a 4946 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4947 * after setting TARC(0)
4948 */
bc7f75fa
AK		 4949 tctl = er32(TCTL);
4950 tctl |= E1000_TCTL_EN;
4951 ew32(TCTL, tctl);
4952
e921eb1a 4953 /* Perform any post-link-up configuration before
75eb0fad
BA		 4954 * reporting link up.
4955 */
4956 if (phy->ops.cfg_on_link_up)
4957 phy->ops.cfg_on_link_up(hw);
4958
bc7f75fa 4959 netif_carrier_on(netdev);
bc7f75fa
AK		 4960
4961 if (!test_bit(__E1000_DOWN, &adapter->state))
4962 mod_timer(&adapter->phy_info_timer,
4963 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4964 }
4965 } else {
4966 if (netif_carrier_ok(netdev)) {
4967 adapter->link_speed = 0;
4968 adapter->link_duplex = 0;
8f12fe86 4969 /* Link status message must follow this format */
7dbc1672 4970 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4971 netif_carrier_off(netdev);
bc7f75fa
AK		 4972 if (!test_bit(__E1000_DOWN, &adapter->state))
4973 mod_timer(&adapter->phy_info_timer,
4974 round_jiffies(jiffies + 2 * HZ));
4975
d9554e96
DE		 4976 /* 8000ES2LAN requires a Rx packet buffer work-around
4977 * on link down event; reset the controller to flush
4978 * the Rx packet buffer.
12d43f7d 4979 */
d9554e96 4980 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 4981 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4982 else
4983 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4984 LINK_TIMEOUT);
bc7f75fa
AK		 4985 }
4986 }
4987
4988link_up:
67fd4fcb 4989 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4990 e1000e_update_stats(adapter);
4991
4992 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4993 adapter->tpt_old = adapter->stats.tpt;
4994 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4995 adapter->colc_old = adapter->stats.colc;
4996
7c25769f
BA		 4997 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4998 adapter->gorc_old = adapter->stats.gorc;
4999 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5000 adapter->gotc_old = adapter->stats.gotc;
2084b114 5001 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5002
d9554e96
DE		 5003 /* If the link is lost the controller stops DMA, but
5004 * if there is queued Tx work it cannot be done. So
5005 * reset the controller to flush the Tx packet buffers.
5006 */
5007 if (!netif_carrier_ok(netdev) &&
5008 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5009 adapter->flags |= FLAG_RESTART_NOW;
5010
5011 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5012 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5013 schedule_work(&adapter->reset_task);
5014 /* return immediately since reset is imminent */
5015 return;
bc7f75fa
AK		 5016 }
5017
12d43f7d
BA		 5018 e1000e_update_adaptive(&adapter->hw);
5019
eab2abf5
JB		 5020 /* Simple mode for Interrupt Throttle Rate (ITR) */
5021 if (adapter->itr_setting == 4) {
e921eb1a 5022 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5023 * Total asymmetrical Tx or Rx gets ITR=8000;
5024 * everyone else is between 2000-8000.
5025 */
5026 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5027 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5028 adapter->gotc - adapter->gorc :
5029 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5030 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5031
22a4cca2 5032 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5033 }
5034
ad68076e 5035 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5036 if (adapter->msix_entries)
5037 ew32(ICS, adapter->rx_ring->ims_val);
5038 else
5039 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5040
713b3c9e
JB		 5041 /* flush pending descriptors to memory before detecting Tx hang */
5042 e1000e_flush_descriptors(adapter);
5043
bc7f75fa 5044 /* Force detection of hung controller every watchdog period */
3db1cd5c 5045 adapter->detect_tx_hung = true;
bc7f75fa 5046
e921eb1a 5047 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5048 * reset from the other port. Set the appropriate LAA in RAR[0]
5049 */
bc7f75fa 5050 if (e1000e_get_laa_state_82571(hw))
69e1e019 5051 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5052
ff10e13c
CW		 5053 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5054 e1000e_check_82574_phy_workaround(adapter);
5055
b67e1913
BA		 5056 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5057 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5058 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5059 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5060 er32(RXSTMPH);
5061 adapter->rx_hwtstamp_cleared++;
5062 } else {
5063 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5064 }
5065 }
5066
bc7f75fa
AK		 5067 /* Reset the timer */
5068 if (!test_bit(__E1000_DOWN, &adapter->state))
5069 mod_timer(&adapter->watchdog_timer,
5070 round_jiffies(jiffies + 2 * HZ));
5071}
5072
5073#define E1000_TX_FLAGS_CSUM 0x00000001
5074#define E1000_TX_FLAGS_VLAN 0x00000002
5075#define E1000_TX_FLAGS_TSO 0x00000004
5076#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5077#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5078#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5079#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5080#define E1000_TX_FLAGS_VLAN_SHIFT 16
5081
55aa6985 5082static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5083{
bc7f75fa
AK		 5084 struct e1000_context_desc *context_desc;
5085 struct e1000_buffer *buffer_info;
5086 unsigned int i;
5087 u32 cmd_length = 0;
70443ae9 5088 u16 ipcse = 0, mss;
bc7f75fa 5089 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5090
3d5e33c9
BA		 5091 if (!skb_is_gso(skb))
5092 return 0;
bc7f75fa 5093
3d5e33c9 5094 if (skb_header_cloned(skb)) {
90da0669
BA		 5095 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5096
3d5e33c9
BA		 5097 if (err)
5098 return err;
bc7f75fa
AK		 5099 }
5100
3d5e33c9
BA		 5101 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5102 mss = skb_shinfo(skb)->gso_size;
5103 if (skb->protocol == htons(ETH_P_IP)) {
5104 struct iphdr *iph = ip_hdr(skb);
5105 iph->tot_len = 0;
5106 iph->check = 0;
5107 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5108 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5109 cmd_length = E1000_TXD_CMD_IP;
5110 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5111 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5112 ipv6_hdr(skb)->payload_len = 0;
5113 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5114 &ipv6_hdr(skb)->daddr,
5115 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5116 ipcse = 0;
5117 }
5118 ipcss = skb_network_offset(skb);
5119 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5120 tucss = skb_transport_offset(skb);
5121 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5122
5123 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5124 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5125
5126 i = tx_ring->next_to_use;
5127 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5128 buffer_info = &tx_ring->buffer_info[i];
5129
e80bd1d1
BA		 5130 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5131 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5132 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5133 context_desc->upper_setup.tcp_fields.tucss = tucss;
5134 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5135 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5136 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5137 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5138 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5139
5140 buffer_info->time_stamp = jiffies;
5141 buffer_info->next_to_watch = i;
5142
5143 i++;
5144 if (i == tx_ring->count)
5145 i = 0;
5146 tx_ring->next_to_use = i;
5147
5148 return 1;
bc7f75fa
AK		 5149}
5150
55aa6985 5151static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5152{
55aa6985 5153 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5154 struct e1000_context_desc *context_desc;
5155 struct e1000_buffer *buffer_info;
5156 unsigned int i;
5157 u8 css;
af807c82 5158 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5159 __be16 protocol;
bc7f75fa 5160
af807c82
DG		 5161 if (skb->ip_summed != CHECKSUM_PARTIAL)
5162 return 0;
bc7f75fa 5163
5f66f208
AJ		 5164 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5165 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5166 else
5167 protocol = skb->protocol;
5168
3f518390 5169 switch (protocol) {
09640e63 5170 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5171 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5172 cmd_len |= E1000_TXD_CMD_TCP;
5173 break;
09640e63 5174 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5175 /* XXX not handling all IPV6 headers */
5176 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5177 cmd_len |= E1000_TXD_CMD_TCP;
5178 break;
5179 default:
5180 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5181 e_warn("checksum_partial proto=%x!\n",
5182 be16_to_cpu(protocol));
af807c82 5183 break;
bc7f75fa
AK		 5184 }
5185
0d0b1672 5186 css = skb_checksum_start_offset(skb);
af807c82
DG		 5187
5188 i = tx_ring->next_to_use;
5189 buffer_info = &tx_ring->buffer_info[i];
5190 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5191
5192 context_desc->lower_setup.ip_config = 0;
5193 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5194 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5195 context_desc->upper_setup.tcp_fields.tucse = 0;
5196 context_desc->tcp_seg_setup.data = 0;
5197 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5198
5199 buffer_info->time_stamp = jiffies;
5200 buffer_info->next_to_watch = i;
5201
5202 i++;
5203 if (i == tx_ring->count)
5204 i = 0;
5205 tx_ring->next_to_use = i;
5206
5207 return 1;
bc7f75fa
AK		 5208}
5209
55aa6985
BA		 5210static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5211 unsigned int first, unsigned int max_per_txd,
d821a4c4 5212 unsigned int nr_frags)
bc7f75fa 5213{
55aa6985 5214 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5215 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5216 struct e1000_buffer *buffer_info;
8ddc951c 5217 unsigned int len = skb_headlen(skb);
03b1320d 5218 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5219 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5220
5221 i = tx_ring->next_to_use;
5222
5223 while (len) {
1b7719c4 5224 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5225 size = min(len, max_per_txd);
5226
bc7f75fa 5227 buffer_info->length = size;
bc7f75fa 5228 buffer_info->time_stamp = jiffies;
bc7f75fa 5229 buffer_info->next_to_watch = i;
0be3f55f
NN		 5230 buffer_info->dma = dma_map_single(&pdev->dev,
5231 skb->data + offset,
af667a29 5232 size, DMA_TO_DEVICE);
03b1320d 5233 buffer_info->mapped_as_page = false;
0be3f55f 5234 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5235 goto dma_error;
bc7f75fa
AK		 5236
5237 len -= size;
5238 offset += size;
03b1320d 5239 count++;
1b7719c4
AD		 5240
5241 if (len) {
5242 i++;
5243 if (i == tx_ring->count)
5244 i = 0;
5245 }
bc7f75fa
AK		 5246 }
5247
5248 for (f = 0; f < nr_frags; f++) {
9e903e08 5249 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5250
5251 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5252 len = skb_frag_size(frag);
877749bf 5253 offset = 0;
bc7f75fa
AK		 5254
5255 while (len) {
1b7719c4
AD		 5256 i++;
5257 if (i == tx_ring->count)
5258 i = 0;
5259
bc7f75fa
AK		 5260 buffer_info = &tx_ring->buffer_info[i];
5261 size = min(len, max_per_txd);
bc7f75fa
AK		 5262
5263 buffer_info->length = size;
5264 buffer_info->time_stamp = jiffies;
bc7f75fa 5265 buffer_info->next_to_watch = i;
877749bf 5266 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5267 offset, size,
5268 DMA_TO_DEVICE);
03b1320d 5269 buffer_info->mapped_as_page = true;
0be3f55f 5270 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5271 goto dma_error;
bc7f75fa
AK		 5272
5273 len -= size;
5274 offset += size;
5275 count++;
bc7f75fa
AK		 5276 }
5277 }
5278
af667a29 5279 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5280 /* multiply data chunks by size of headers */
5281 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5282
bc7f75fa 5283 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5284 tx_ring->buffer_info[i].segs = segs;
5285 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5286 tx_ring->buffer_info[first].next_to_watch = i;
5287
5288 return count;
03b1320d
AD		 5289
5290dma_error:
af667a29 5291 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5292 buffer_info->dma = 0;
c1fa347f 5293 if (count)
03b1320d 5294 count--;
c1fa347f
RK		 5295
5296 while (count--) {
af667a29 5297 if (i == 0)
03b1320d 5298 i += tx_ring->count;
c1fa347f 5299 i--;
03b1320d 5300 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5301 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5302 }
5303
5304 return 0;
bc7f75fa
AK		 5305}
5306
55aa6985 5307static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5308{
55aa6985 5309 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5310 struct e1000_tx_desc *tx_desc = NULL;
5311 struct e1000_buffer *buffer_info;
5312 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5313 unsigned int i;
5314
5315 if (tx_flags & E1000_TX_FLAGS_TSO) {
5316 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5317 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5318 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5319
5320 if (tx_flags & E1000_TX_FLAGS_IPV4)
5321 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5322 }
5323
5324 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5325 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5326 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5327 }
5328
5329 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5330 txd_lower |= E1000_TXD_CMD_VLE;
5331 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5332 }
5333
943146de
BG		 5334 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5335 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5336
b67e1913
BA		 5337 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5338 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5339 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5340 }
5341
bc7f75fa
AK		 5342 i = tx_ring->next_to_use;
5343
36b973df 5344 do {
bc7f75fa
AK		 5345 buffer_info = &tx_ring->buffer_info[i];
5346 tx_desc = E1000_TX_DESC(*tx_ring, i);
5347 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5348 tx_desc->lower.data = cpu_to_le32(txd_lower |
5349 buffer_info->length);
bc7f75fa
AK		 5350 tx_desc->upper.data = cpu_to_le32(txd_upper);
5351
5352 i++;
5353 if (i == tx_ring->count)
5354 i = 0;
36b973df 5355 } while (--count > 0);
bc7f75fa
AK		 5356
5357 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5358
943146de
BG		 5359 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5360 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5361 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5362
e921eb1a 5363 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5364 * know there are new descriptors to fetch. (Only
5365 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5366 * such as IA-64).
5367 */
bc7f75fa
AK		 5368 wmb();
5369
5370 tx_ring->next_to_use = i;
c6e7f51e
BA		 5371
5372 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5373 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5374 else
c5083cf6 5375 writel(i, tx_ring->tail);
c6e7f51e 5376
e921eb1a 5377 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5378 * at a time, it synchronizes IO on IA64/Altix systems
5379 */
bc7f75fa
AK		 5380 mmiowb();
5381}
5382
5383#define MINIMUM_DHCP_PACKET_SIZE 282
5384static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5385 struct sk_buff *skb)
5386{
e80bd1d1 5387 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5388 u16 length, offset;
5389
d60923c4
BA		 5390 if (vlan_tx_tag_present(skb) &&
5391 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5392 (adapter->hw.mng_cookie.status &
5393 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5394 return 0;
bc7f75fa
AK		 5395
5396 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5397 return 0;
5398
53aa82da 5399 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5400 return 0;
5401
5402 {
362e20ca 5403 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5404 struct udphdr *udp;
5405
5406 if (ip->protocol != IPPROTO_UDP)
5407 return 0;
5408
5409 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5410 if (ntohs(udp->dest) != 67)
5411 return 0;
5412
5413 offset = (u8 *)udp + 8 - skb->data;
5414 length = skb->len - offset;
5415 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5416 }
5417
5418 return 0;
5419}
5420
55aa6985 5421static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5422{
55aa6985 5423 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5424
55aa6985 5425 netif_stop_queue(adapter->netdev);
e921eb1a 5426 /* Herbert's original patch had:
bc7f75fa 5427 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5428 * but since that doesn't exist yet, just open code it.
5429 */
bc7f75fa
AK		 5430 smp_mb();
5431
e921eb1a 5432 /* We need to check again in a case another CPU has just
ad68076e
BA		 5433 * made room available.
5434 */
55aa6985 5435 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5436 return -EBUSY;
5437
5438 /* A reprieve! */
55aa6985 5439 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5440 ++adapter->restart_queue;
5441 return 0;
5442}
5443
55aa6985 5444static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5445{
d821a4c4
BA		 5446 BUG_ON(size > tx_ring->count);
5447
55aa6985 5448 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5449 return 0;
55aa6985 5450 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5451}
5452
3b29a56d
SH		 5453static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5454 struct net_device *netdev)
bc7f75fa
AK		 5455{
5456 struct e1000_adapter *adapter = netdev_priv(netdev);
5457 struct e1000_ring *tx_ring = adapter->tx_ring;
5458 unsigned int first;
bc7f75fa 5459 unsigned int tx_flags = 0;
e743d313 5460 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5461 unsigned int nr_frags;
5462 unsigned int mss;
bc7f75fa
AK		 5463 int count = 0;
5464 int tso;
5465 unsigned int f;
bc7f75fa
AK		 5466
5467 if (test_bit(__E1000_DOWN, &adapter->state)) {
5468 dev_kfree_skb_any(skb);
5469 return NETDEV_TX_OK;
5470 }
5471
5472 if (skb->len <= 0) {
5473 dev_kfree_skb_any(skb);
5474 return NETDEV_TX_OK;
5475 }
5476
e921eb1a 5477 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5478 * pad skb in order to meet this minimum size requirement
5479 */
5480 if (unlikely(skb->len < 17)) {
5481 if (skb_pad(skb, 17 - skb->len))
5482 return NETDEV_TX_OK;
5483 skb->len = 17;
5484 skb_set_tail_pointer(skb, 17);
5485 }
5486
bc7f75fa 5487 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5488 if (mss) {
5489 u8 hdr_len;
bc7f75fa 5490
e921eb1a 5491 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5492 * points to just header, pull a few bytes of payload from
5493 * frags into skb->data
5494 */
bc7f75fa 5495 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5496 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5497 * avoiding it could save a lot of cycles
5498 */
4e6c709c 5499 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5500 unsigned int pull_size;
5501
a2a5b323 5502 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5503 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5504 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5505 dev_kfree_skb_any(skb);
5506 return NETDEV_TX_OK;
5507 }
e743d313 5508 len = skb_headlen(skb);
bc7f75fa
AK		 5509 }
5510 }
5511
5512 /* reserve a descriptor for the offload context */
5513 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5514 count++;
5515 count++;
5516
d821a4c4 5517 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5518
5519 nr_frags = skb_shinfo(skb)->nr_frags;
5520 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5521 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5522 adapter->tx_fifo_limit);
bc7f75fa
AK		 5523
5524 if (adapter->hw.mac.tx_pkt_filtering)
5525 e1000_transfer_dhcp_info(adapter, skb);
5526
e921eb1a 5527 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5528 * head, otherwise try next time
5529 */
55aa6985 5530 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5531 return NETDEV_TX_BUSY;
bc7f75fa 5532
eab6d18d 5533 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5534 tx_flags |= E1000_TX_FLAGS_VLAN;
5535 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5536 }
5537
5538 first = tx_ring->next_to_use;
5539
55aa6985 5540 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5541 if (tso < 0) {
5542 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5543 return NETDEV_TX_OK;
5544 }
5545
5546 if (tso)
5547 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5548 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5549 tx_flags |= E1000_TX_FLAGS_CSUM;
5550
e921eb1a 5551 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5552 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5553 * no longer assume, we must.
5554 */
bc7f75fa
AK		 5555 if (skb->protocol == htons(ETH_P_IP))
5556 tx_flags |= E1000_TX_FLAGS_IPV4;
5557
943146de
BG		 5558 if (unlikely(skb->no_fcs))
5559 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5560
25985edc 5561 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5562 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5563 nr_frags);
1b7719c4 5564 if (count) {
b67e1913
BA		 5565 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5566 !adapter->tx_hwtstamp_skb)) {
5567 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5568 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5569 adapter->tx_hwtstamp_skb = skb_get(skb);
5570 schedule_work(&adapter->tx_hwtstamp_work);
5571 } else {
5572 skb_tx_timestamp(skb);
5573 }
80be3129 5574
3f0cfa3b 5575 netdev_sent_queue(netdev, skb->len);
55aa6985 5576 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5577 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5578 e1000_maybe_stop_tx(tx_ring,
5579 (MAX_SKB_FRAGS *
5580 DIV_ROUND_UP(PAGE_SIZE,
5581 adapter->tx_fifo_limit) + 2));
1b7719c4 5582 } else {
bc7f75fa 5583 dev_kfree_skb_any(skb);
1b7719c4
AD		 5584 tx_ring->buffer_info[first].time_stamp = 0;
5585 tx_ring->next_to_use = first;
bc7f75fa
AK		 5586 }
5587
bc7f75fa
AK		 5588 return NETDEV_TX_OK;
5589}
5590
5591/**
5592 * e1000_tx_timeout - Respond to a Tx Hang
5593 * @netdev: network interface device structure
5594 **/
5595static void e1000_tx_timeout(struct net_device *netdev)
5596{
5597 struct e1000_adapter *adapter = netdev_priv(netdev);
5598
5599 /* Do the reset outside of interrupt context */
5600 adapter->tx_timeout_count++;
5601 schedule_work(&adapter->reset_task);
5602}
5603
5604static void e1000_reset_task(struct work_struct *work)
5605{
5606 struct e1000_adapter *adapter;
5607 adapter = container_of(work, struct e1000_adapter, reset_task);
5608
615b32af
JB		 5609 /* don't run the task if already down */
5610 if (test_bit(__E1000_DOWN, &adapter->state))
5611 return;
5612
12d43f7d 5613 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5614 e1000e_dump(adapter);
12d43f7d 5615 e_err("Reset adapter unexpectedly\n");
affa9dfb 5616 }
bc7f75fa
AK		 5617 e1000e_reinit_locked(adapter);
5618}
5619
5620/**
67fd4fcb 5621 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5622 * @netdev: network interface device structure
67fd4fcb 5623 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5624 *
5625 * Returns the address of the device statistics structure.
bc7f75fa 5626 **/
67fd4fcb 5627struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5628 struct rtnl_link_stats64 *stats)
bc7f75fa 5629{
67fd4fcb
JK		 5630 struct e1000_adapter *adapter = netdev_priv(netdev);
5631
5632 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5633 spin_lock(&adapter->stats64_lock);
5634 e1000e_update_stats(adapter);
5635 /* Fill out the OS statistics structure */
5636 stats->rx_bytes = adapter->stats.gorc;
5637 stats->rx_packets = adapter->stats.gprc;
5638 stats->tx_bytes = adapter->stats.gotc;
5639 stats->tx_packets = adapter->stats.gptc;
5640 stats->multicast = adapter->stats.mprc;
5641 stats->collisions = adapter->stats.colc;
5642
5643 /* Rx Errors */
5644
e921eb1a 5645 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5646 * our own version based on RUC and ROC
5647 */
5648 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5649 adapter->stats.crcerrs + adapter->stats.algnerrc +
5650 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5651 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5652 stats->rx_crc_errors = adapter->stats.crcerrs;
5653 stats->rx_frame_errors = adapter->stats.algnerrc;
5654 stats->rx_missed_errors = adapter->stats.mpc;
5655
5656 /* Tx Errors */
f0ff4398 5657 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5658 stats->tx_aborted_errors = adapter->stats.ecol;
5659 stats->tx_window_errors = adapter->stats.latecol;
5660 stats->tx_carrier_errors = adapter->stats.tncrs;
5661
5662 /* Tx Dropped needs to be maintained elsewhere */
5663
5664 spin_unlock(&adapter->stats64_lock);
5665 return stats;
bc7f75fa
AK		 5666}
5667
5668/**
5669 * e1000_change_mtu - Change the Maximum Transfer Unit
5670 * @netdev: network interface device structure
5671 * @new_mtu: new value for maximum frame size
5672 *
5673 * Returns 0 on success, negative on failure
5674 **/
5675static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5676{
5677 struct e1000_adapter *adapter = netdev_priv(netdev);
5678 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5679
2adc55c9 5680 /* Jumbo frame support */
2e1706f2
BA		 5681 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5682 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5683 e_err("Jumbo Frames not supported.\n");
5684 return -EINVAL;
bc7f75fa
AK		 5685 }
5686
2adc55c9
BA		 5687 /* Supported frame sizes */
5688 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5689 (max_frame > adapter->max_hw_frame_size)) {
5690 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5691 return -EINVAL;
5692 }
5693
2fbe4526
BA		 5694 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5695 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5696 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5697 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5698 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5699 return -EINVAL;
5700 }
5701
bc7f75fa 5702 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5703 usleep_range(1000, 2000);
610c9928 5704 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5705 adapter->max_frame_size = max_frame;
610c9928
BA		 5706 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5707 netdev->mtu = new_mtu;
63eb48f1
DE		 5708
5709 pm_runtime_get_sync(netdev->dev.parent);
5710
bc7f75fa 5711 if (netif_running(netdev))
28002099 5712 e1000e_down(adapter, true);
bc7f75fa 5713
e921eb1a 5714 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5715 * means we reserve 2 more, this pushes us to allocate from the next
5716 * larger slab size.
ad68076e 5717 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5718 * However with the new *_jumbo_rx* routines, jumbo receives will use
5719 * fragmented skbs
ad68076e 5720 */
bc7f75fa 5721
9926146b 5722 if (max_frame <= 2048)
bc7f75fa
AK		 5723 adapter->rx_buffer_len = 2048;
5724 else
5725 adapter->rx_buffer_len = 4096;
5726
5727 /* adjust allocation if LPE protects us, and we aren't using SBP */
5728 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5729 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5730 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5731 + ETH_FCS_LEN;
bc7f75fa 5732
bc7f75fa
AK		 5733 if (netif_running(netdev))
5734 e1000e_up(adapter);
5735 else
5736 e1000e_reset(adapter);
5737
63eb48f1
DE		 5738 pm_runtime_put_sync(netdev->dev.parent);
5739
bc7f75fa
AK		 5740 clear_bit(__E1000_RESETTING, &adapter->state);
5741
5742 return 0;
5743}
5744
5745static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5746 int cmd)
5747{
5748 struct e1000_adapter *adapter = netdev_priv(netdev);
5749 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5750
318a94d6 5751 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5752 return -EOPNOTSUPP;
5753
5754 switch (cmd) {
5755 case SIOCGMIIPHY:
5756 data->phy_id = adapter->hw.phy.addr;
5757 break;
5758 case SIOCGMIIREG:
b16a002e
BA		 5759 e1000_phy_read_status(adapter);
5760
7c25769f
BA		 5761 switch (data->reg_num & 0x1F) {
5762 case MII_BMCR:
5763 data->val_out = adapter->phy_regs.bmcr;
5764 break;
5765 case MII_BMSR:
5766 data->val_out = adapter->phy_regs.bmsr;
5767 break;
5768 case MII_PHYSID1:
5769 data->val_out = (adapter->hw.phy.id >> 16);
5770 break;
5771 case MII_PHYSID2:
5772 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5773 break;
5774 case MII_ADVERTISE:
5775 data->val_out = adapter->phy_regs.advertise;
5776 break;
5777 case MII_LPA:
5778 data->val_out = adapter->phy_regs.lpa;
5779 break;
5780 case MII_EXPANSION:
5781 data->val_out = adapter->phy_regs.expansion;
5782 break;
5783 case MII_CTRL1000:
5784 data->val_out = adapter->phy_regs.ctrl1000;
5785 break;
5786 case MII_STAT1000:
5787 data->val_out = adapter->phy_regs.stat1000;
5788 break;
5789 case MII_ESTATUS:
5790 data->val_out = adapter->phy_regs.estatus;
5791 break;
5792 default:
bc7f75fa
AK		 5793 return -EIO;
5794 }
bc7f75fa
AK		 5795 break;
5796 case SIOCSMIIREG:
5797 default:
5798 return -EOPNOTSUPP;
5799 }
5800 return 0;
5801}
5802
b67e1913
BA		 5803/**
5804 * e1000e_hwtstamp_ioctl - control hardware time stamping
5805 * @netdev: network interface device structure
5806 * @ifreq: interface request
5807 *
5808 * Outgoing time stamping can be enabled and disabled. Play nice and
5809 * disable it when requested, although it shouldn't cause any overhead
5810 * when no packet needs it. At most one packet in the queue may be
5811 * marked for time stamping, otherwise it would be impossible to tell
5812 * for sure to which packet the hardware time stamp belongs.
5813 *
5814 * Incoming time stamping has to be configured via the hardware filters.
5815 * Not all combinations are supported, in particular event type has to be
5816 * specified. Matching the kind of event packet is not supported, with the
5817 * exception of "all V2 events regardless of level 2 or 4".
5818 **/
4e8cff64 5819static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 5820{
5821 struct e1000_adapter *adapter = netdev_priv(netdev);
5822 struct hwtstamp_config config;
5823 int ret_val;
5824
5825 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5826 return -EFAULT;
5827
62d7e3a2 5828 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 5829 if (ret_val)
5830 return ret_val;
5831
d89777bf
BA		 5832 switch (config.rx_filter) {
5833 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5834 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5835 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5836 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5837 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5838 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5839 /* With V2 type filters which specify a Sync or Delay Request,
5840 * Path Delay Request/Response messages are also time stamped
5841 * by hardware so notify the caller the requested packets plus
5842 * some others are time stamped.
5843 */
5844 config.rx_filter = HWTSTAMP_FILTER_SOME;
5845 break;
5846 default:
5847 break;
5848 }
5849
b67e1913
BA		 5850 return copy_to_user(ifr->ifr_data, &config,
5851 sizeof(config)) ? -EFAULT : 0;
5852}
5853
4e8cff64
BH		 5854static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
5855{
5856 struct e1000_adapter *adapter = netdev_priv(netdev);
5857
5858 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
5859 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
5860}
5861
bc7f75fa
AK		 5862static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5863{
5864 switch (cmd) {
5865 case SIOCGMIIPHY:
5866 case SIOCGMIIREG:
5867 case SIOCSMIIREG:
5868 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 5869 case SIOCSHWTSTAMP:
4e8cff64
BH		 5870 return e1000e_hwtstamp_set(netdev, ifr);
5871 case SIOCGHWTSTAMP:
5872 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 5873 default:
5874 return -EOPNOTSUPP;
5875 }
5876}
5877
a4f58f54
BA		 5878static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5879{
5880 struct e1000_hw *hw = &adapter->hw;
74f350ee 5881 u32 i, mac_reg, wuc;
2b6b168d 5882 u16 phy_reg, wuc_enable;
70806a7f 5883 int retval;
a4f58f54
BA		 5884
5885 /* copy MAC RARs to PHY RARs */
d3738bb8 5886 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5887
2b6b168d
BA		 5888 retval = hw->phy.ops.acquire(hw);
5889 if (retval) {
5890 e_err("Could not acquire PHY\n");
5891 return retval;
5892 }
5893
5894 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5895 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5896 if (retval)
75ce1532 5897 goto release;
2b6b168d
BA		 5898
5899 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5900 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5901 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5902 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5903 (u16)(mac_reg & 0xFFFF));
5904 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5905 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5906 }
5907
5908 /* configure PHY Rx Control register */
2b6b168d 5909 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5910 mac_reg = er32(RCTL);
5911 if (mac_reg & E1000_RCTL_UPE)
5912 phy_reg |= BM_RCTL_UPE;
5913 if (mac_reg & E1000_RCTL_MPE)
5914 phy_reg |= BM_RCTL_MPE;
5915 phy_reg &= ~(BM_RCTL_MO_MASK);
5916 if (mac_reg & E1000_RCTL_MO_3)
5917 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5918 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5919 if (mac_reg & E1000_RCTL_BAM)
5920 phy_reg |= BM_RCTL_BAM;
5921 if (mac_reg & E1000_RCTL_PMCF)
5922 phy_reg |= BM_RCTL_PMCF;
5923 mac_reg = er32(CTRL);
5924 if (mac_reg & E1000_CTRL_RFCE)
5925 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5926 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 5927
74f350ee
DE		 5928 wuc = E1000_WUC_PME_EN;
5929 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
5930 wuc |= E1000_WUC_APME;
5931
a4f58f54
BA		 5932 /* enable PHY wakeup in MAC register */
5933 ew32(WUFC, wufc);
74f350ee
DE		 5934 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
5935 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 5936
5937 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 5938 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 5939 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 5940
5941 /* activate PHY wakeup */
2b6b168d
BA		 5942 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5943 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5944 if (retval)
5945 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5946release:
94d8186a 5947 hw->phy.ops.release(hw);
a4f58f54
BA		 5948
5949 return retval;
5950}
5951
28002099 5952static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 5953{
28002099 5954 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 5955 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 5956
5957 netif_device_detach(netdev);
5958
5959 if (netif_running(netdev)) {
bb9e44d0
BA		 5960 int count = E1000_CHECK_RESET_COUNT;
5961
5962 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5963 usleep_range(10000, 20000);
5964
bc7f75fa 5965 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 5966
5967 /* Quiesce the device without resetting the hardware */
5968 e1000e_down(adapter, false);
bc7f75fa
AK		 5969 e1000_free_irq(adapter);
5970 }
4662e82b 5971 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5972
28002099
DE		 5973 /* Allow time for pending master requests to run */
5974 e1000e_disable_pcie_master(&adapter->hw);
5975
5976 return 0;
5977}
5978
5979static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
5980{
5981 struct net_device *netdev = pci_get_drvdata(pdev);
5982 struct e1000_adapter *adapter = netdev_priv(netdev);
5983 struct e1000_hw *hw = &adapter->hw;
5984 u32 ctrl, ctrl_ext, rctl, status;
5985 /* Runtime suspend should only enable wakeup for link changes */
5986 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
5987 int retval = 0;
5988
bc7f75fa
AK		 5989 status = er32(STATUS);
5990 if (status & E1000_STATUS_LU)
5991 wufc &= ~E1000_WUFC_LNKC;
5992
5993 if (wufc) {
5994 e1000_setup_rctl(adapter);
ef9b965a 5995 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5996
5997 /* turn on all-multi mode if wake on multicast is enabled */
5998 if (wufc & E1000_WUFC_MC) {
5999 rctl = er32(RCTL);
6000 rctl |= E1000_RCTL_MPE;
6001 ew32(RCTL, rctl);
6002 }
6003
6004 ctrl = er32(CTRL);
a4f58f54
BA		 6005 ctrl |= E1000_CTRL_ADVD3WUC;
6006 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6007 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6008 ew32(CTRL, ctrl);
6009
318a94d6
JK		 6010 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6011 adapter->hw.phy.media_type ==
6012 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6013 /* keep the laser running in D3 */
6014 ctrl_ext = er32(CTRL_EXT);
93a23f48 6015 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6016 ew32(CTRL_EXT, ctrl_ext);
6017 }
6018
63eb48f1
DE		 6019 if (!runtime)
6020 e1000e_power_up_phy(adapter);
6021
97ac8cae 6022 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6023 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6024
82776a4b 6025 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6026 /* enable wakeup by the PHY */
6027 retval = e1000_init_phy_wakeup(adapter, wufc);
6028 if (retval)
6029 return retval;
6030 } else {
6031 /* enable wakeup by the MAC */
6032 ew32(WUFC, wufc);
6033 ew32(WUC, E1000_WUC_PME_EN);
6034 }
bc7f75fa
AK		 6035 } else {
6036 ew32(WUC, 0);
6037 ew32(WUFC, 0);
28002099
DE		 6038
6039 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6040 }
6041
74f350ee 6042 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6043 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
74f350ee
DE		 6044 } else if (hw->mac.type == e1000_pch_lpt) {
6045 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6046 /* ULP does not support wake from unicast, multicast
6047 * or broadcast.
6048 */
6049 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6050
6051 if (retval)
6052 return retval;
6053 }
6054
bc7f75fa 6055
e921eb1a 6056 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6057 * would have already happened in close and is redundant.
6058 */
31dbe5b4 6059 e1000e_release_hw_control(adapter);
bc7f75fa 6060
24b41c97
DN		 6061 pci_clear_master(pdev);
6062
e921eb1a 6063 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6064 * correctable error when the MAC transitions from D0 to D3. To
6065 * prevent this we need to mask off the correctable errors on the
6066 * downstream port of the pci-e switch.
e8c254c5
LZ		 6067 *
6068 * We don't have the associated upstream bridge while assigning
6069 * the PCI device into guest. For example, the KVM on power is
6070 * one of the cases.
005cbdfc
AD		 6071 */
6072 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6073 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6074 u16 devctl;
6075
e8c254c5
LZ		 6076 if (!us_dev)
6077 return 0;
6078
f8c0fcac
JL		 6079 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6080 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6081 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6082
66148bab
KK		 6083 pci_save_state(pdev);
6084 pci_prepare_to_sleep(pdev);
005cbdfc 6085
f8c0fcac 6086 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6087 }
66148bab
KK		 6088
6089 return 0;
bc7f75fa
AK		 6090}
6091
13129d9b
CW		 6092/**
6093 * e1000e_disable_aspm - Disable ASPM states
6094 * @pdev: pointer to PCI device struct
6095 * @state: bit-mask of ASPM states to disable
6096 *
6097 * Some devices *must* have certain ASPM states disabled per hardware errata.
6098 **/
6099static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c 6100{
13129d9b
CW		 6101 struct pci_dev *parent = pdev->bus->self;
6102 u16 aspm_dis_mask = 0;
6103 u16 pdev_aspmc, parent_aspmc;
6104
6105 switch (state) {
6106 case PCIE_LINK_STATE_L0S:
6107 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6108 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6109 /* fall-through - can't have L1 without L0s */
6110 case PCIE_LINK_STATE_L1:
6111 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6112 break;
6113 default:
6114 return;
6115 }
6116
6117 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6118 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6119
6120 if (parent) {
6121 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6122 &parent_aspmc);
6123 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6124 }
6125
6126 /* Nothing to do if the ASPM states to be disabled already are */
6127 if (!(pdev_aspmc & aspm_dis_mask) &&
6128 (!parent || !(parent_aspmc & aspm_dis_mask)))
6129 return;
6130
6131 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6132 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6133 "L0s" : "",
6134 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6135 "L1" : "");
6136
6137#ifdef CONFIG_PCIEASPM
9f728f53 6138 pci_disable_link_state_locked(pdev, state);
ffe0b2ff 6139
13129d9b
CW		 6140 /* Double-check ASPM control. If not disabled by the above, the
6141 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6142 * not enabled); override by writing PCI config space directly.
6143 */
6144 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6145 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6146
6147 if (!(aspm_dis_mask & pdev_aspmc))
6148 return;
6149#endif
ffe0b2ff 6150
e921eb1a 6151 /* Both device and parent should have the same ASPM setting.
6f461f6c 6152 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6153 */
13129d9b 6154 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6155
13129d9b
CW		 6156 if (parent)
6157 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6158 aspm_dis_mask);
1eae4eb2
AK		 6159}
6160
aa338601 6161#ifdef CONFIG_PM
23606cf5 6162static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6163{
6164 struct net_device *netdev = pci_get_drvdata(pdev);
6165 struct e1000_adapter *adapter = netdev_priv(netdev);
6166 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6167 u16 aspm_disable_flag = 0;
bc7f75fa 6168
78cd29d5
BA		 6169 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6170 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6171 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6172 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6173 if (aspm_disable_flag)
6174 e1000e_disable_aspm(pdev, aspm_disable_flag);
6175
66148bab 6176 pci_set_master(pdev);
6e4f6f6b 6177
2fbe4526 6178 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6179 e1000_resume_workarounds_pchlan(&adapter->hw);
6180
bc7f75fa 6181 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6182
6183 /* report the system wakeup cause from S3/S4 */
6184 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6185 u16 phy_data;
6186
6187 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6188 if (phy_data) {
6189 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6190 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6191 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6192 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6193 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6194 phy_data & E1000_WUS_LNKC ?
6195 "Link Status Change" : "other");
a4f58f54
BA		 6196 }
6197 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6198 } else {
6199 u32 wus = er32(WUS);
6200 if (wus) {
6201 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6202 wus & E1000_WUS_EX ? "Unicast Packet" :
6203 wus & E1000_WUS_MC ? "Multicast Packet" :
6204 wus & E1000_WUS_BC ? "Broadcast Packet" :
6205 wus & E1000_WUS_MAG ? "Magic Packet" :
6206 wus & E1000_WUS_LNKC ? "Link Status Change" :
6207 "other");
a4f58f54
BA		 6208 }
6209 ew32(WUS, ~0);
6210 }
6211
bc7f75fa 6212 e1000e_reset(adapter);
bc7f75fa 6213
cd791618 6214 e1000_init_manageability_pt(adapter);
bc7f75fa 6215
e921eb1a 6216 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6217 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6218 * under the control of the driver.
6219 */
c43bc57e 6220 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6221 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6222
6223 return 0;
6224}
23606cf5 6225
28002099
DE		 6226static int e1000e_pm_thaw(struct device *dev)
6227{
6228 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6229 struct e1000_adapter *adapter = netdev_priv(netdev);
6230
6231 e1000e_set_interrupt_capability(adapter);
6232 if (netif_running(netdev)) {
6233 u32 err = e1000_request_irq(adapter);
6234
6235 if (err)
6236 return err;
6237
6238 e1000e_up(adapter);
6239 }
6240
6241 netif_device_attach(netdev);
6242
6243 return 0;
6244}
6245
38a529b5 6246#ifdef CONFIG_PM_SLEEP
28002099 6247static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6248{
6249 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6250
28002099
DE		 6251 e1000e_pm_freeze(dev);
6252
66148bab 6253 return __e1000_shutdown(pdev, false);
a0340162
RW		 6254}
6255
28002099 6256static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6257{
6258 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6259 int rc;
23606cf5 6260
28002099
DE		 6261 rc = __e1000_resume(pdev);
6262 if (rc)
6263 return rc;
23606cf5 6264
28002099 6265 return e1000e_pm_thaw(dev);
23606cf5 6266}
38a529b5 6267#endif /* CONFIG_PM_SLEEP */
a0340162
RW		 6268
6269#ifdef CONFIG_PM_RUNTIME
63eb48f1 6270static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6271{
6272 struct pci_dev *pdev = to_pci_dev(dev);
6273 struct net_device *netdev = pci_get_drvdata(pdev);
6274 struct e1000_adapter *adapter = netdev_priv(netdev);
6275
63eb48f1
DE		 6276 if (!e1000e_has_link(adapter))
6277 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
a0340162 6278
63eb48f1 6279 return -EBUSY;
a0340162
RW		 6280}
6281
63eb48f1 6282static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6283{
6284 struct pci_dev *pdev = to_pci_dev(dev);
6285 struct net_device *netdev = pci_get_drvdata(pdev);
6286 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6287 int rc;
a0340162 6288
63eb48f1
DE		 6289 rc = __e1000_resume(pdev);
6290 if (rc)
6291 return rc;
a0340162 6292
63eb48f1
DE		 6293 if (netdev->flags & IFF_UP)
6294 rc = e1000e_up(adapter);
a0340162 6295
63eb48f1 6296 return rc;
a0340162 6297}
23606cf5 6298
63eb48f1 6299static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6300{
6301 struct pci_dev *pdev = to_pci_dev(dev);
6302 struct net_device *netdev = pci_get_drvdata(pdev);
6303 struct e1000_adapter *adapter = netdev_priv(netdev);
6304
63eb48f1
DE		 6305 if (netdev->flags & IFF_UP) {
6306 int count = E1000_CHECK_RESET_COUNT;
6307
6308 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6309 usleep_range(10000, 20000);
23606cf5 6310
63eb48f1
DE		 6311 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6312
6313 /* Down the device without resetting the hardware */
6314 e1000e_down(adapter, false);
6315 }
6316
6317 if (__e1000_shutdown(pdev, true)) {
6318 e1000e_pm_runtime_resume(dev);
6319 return -EBUSY;
6320 }
6321
6322 return 0;
23606cf5 6323}
a0340162 6324#endif /* CONFIG_PM_RUNTIME */
aa338601 6325#endif /* CONFIG_PM */
bc7f75fa
AK		 6326
6327static void e1000_shutdown(struct pci_dev *pdev)
6328{
28002099
DE		 6329 e1000e_pm_freeze(&pdev->dev);
6330
66148bab 6331 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6332}
6333
6334#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6335
8bb62869 6336static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6337{
6338 struct net_device *netdev = data;
6339 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6340
6341 if (adapter->msix_entries) {
90da0669
BA		 6342 int vector, msix_irq;
6343
147b2c8c
DD		 6344 vector = 0;
6345 msix_irq = adapter->msix_entries[vector].vector;
6346 disable_irq(msix_irq);
6347 e1000_intr_msix_rx(msix_irq, netdev);
6348 enable_irq(msix_irq);
6349
6350 vector++;
6351 msix_irq = adapter->msix_entries[vector].vector;
6352 disable_irq(msix_irq);
6353 e1000_intr_msix_tx(msix_irq, netdev);
6354 enable_irq(msix_irq);
6355
6356 vector++;
6357 msix_irq = adapter->msix_entries[vector].vector;
6358 disable_irq(msix_irq);
6359 e1000_msix_other(msix_irq, netdev);
6360 enable_irq(msix_irq);
6361 }
6362
6363 return IRQ_HANDLED;
6364}
6365
e921eb1a
BA		 6366/**
6367 * e1000_netpoll
6368 * @netdev: network interface device structure
6369 *
bc7f75fa
AK		 6370 * Polling 'interrupt' - used by things like netconsole to send skbs
6371 * without having to re-enable interrupts. It's not called while
6372 * the interrupt routine is executing.
6373 */
6374static void e1000_netpoll(struct net_device *netdev)
6375{
6376 struct e1000_adapter *adapter = netdev_priv(netdev);
6377
147b2c8c
DD		 6378 switch (adapter->int_mode) {
6379 case E1000E_INT_MODE_MSIX:
6380 e1000_intr_msix(adapter->pdev->irq, netdev);
6381 break;
6382 case E1000E_INT_MODE_MSI:
6383 disable_irq(adapter->pdev->irq);
6384 e1000_intr_msi(adapter->pdev->irq, netdev);
6385 enable_irq(adapter->pdev->irq);
6386 break;
e80bd1d1 6387 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6388 disable_irq(adapter->pdev->irq);
6389 e1000_intr(adapter->pdev->irq, netdev);
6390 enable_irq(adapter->pdev->irq);
6391 break;
6392 }
bc7f75fa
AK		 6393}
6394#endif
6395
6396/**
6397 * e1000_io_error_detected - called when PCI error is detected
6398 * @pdev: Pointer to PCI device
6399 * @state: The current pci connection state
6400 *
6401 * This function is called after a PCI bus error affecting
6402 * this device has been detected.
6403 */
6404static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6405 pci_channel_state_t state)
6406{
6407 struct net_device *netdev = pci_get_drvdata(pdev);
6408 struct e1000_adapter *adapter = netdev_priv(netdev);
6409
6410 netif_device_detach(netdev);
6411
c93b5a76
MM		 6412 if (state == pci_channel_io_perm_failure)
6413 return PCI_ERS_RESULT_DISCONNECT;
6414
bc7f75fa 6415 if (netif_running(netdev))
28002099 6416 e1000e_down(adapter, true);
bc7f75fa
AK		 6417 pci_disable_device(pdev);
6418
6419 /* Request a slot slot reset. */
6420 return PCI_ERS_RESULT_NEED_RESET;
6421}
6422
6423/**
6424 * e1000_io_slot_reset - called after the pci bus has been reset.
6425 * @pdev: Pointer to PCI device
6426 *
6427 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6428 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6429 */
6430static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6431{
6432 struct net_device *netdev = pci_get_drvdata(pdev);
6433 struct e1000_adapter *adapter = netdev_priv(netdev);
6434 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6435 u16 aspm_disable_flag = 0;
6e4f6f6b 6436 int err;
111b9dc5 6437 pci_ers_result_t result;
bc7f75fa 6438
78cd29d5
BA		 6439 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6440 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6441 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6442 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6443 if (aspm_disable_flag)
6444 e1000e_disable_aspm(pdev, aspm_disable_flag);
6445
f0f422e5 6446 err = pci_enable_device_mem(pdev);
6e4f6f6b 6447 if (err) {
bc7f75fa
AK		 6448 dev_err(&pdev->dev,
6449 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6450 result = PCI_ERS_RESULT_DISCONNECT;
6451 } else {
23606cf5 6452 pdev->state_saved = true;
111b9dc5 6453 pci_restore_state(pdev);
66148bab 6454 pci_set_master(pdev);
bc7f75fa 6455
111b9dc5
JB		 6456 pci_enable_wake(pdev, PCI_D3hot, 0);
6457 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6458
111b9dc5
JB		 6459 e1000e_reset(adapter);
6460 ew32(WUS, ~0);
6461 result = PCI_ERS_RESULT_RECOVERED;
6462 }
bc7f75fa 6463
111b9dc5
JB		 6464 pci_cleanup_aer_uncorrect_error_status(pdev);
6465
6466 return result;
bc7f75fa
AK		 6467}
6468
6469/**
6470 * e1000_io_resume - called when traffic can start flowing again.
6471 * @pdev: Pointer to PCI device
6472 *
6473 * This callback is called when the error recovery driver tells us that
6474 * its OK to resume normal operation. Implementation resembles the
28002099 6475 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6476 */
6477static void e1000_io_resume(struct pci_dev *pdev)
6478{
6479 struct net_device *netdev = pci_get_drvdata(pdev);
6480 struct e1000_adapter *adapter = netdev_priv(netdev);
6481
cd791618 6482 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6483
6484 if (netif_running(netdev)) {
6485 if (e1000e_up(adapter)) {
6486 dev_err(&pdev->dev,
6487 "can't bring device back up after reset\n");
6488 return;
6489 }
6490 }
6491
6492 netif_device_attach(netdev);
6493
e921eb1a 6494 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6495 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6496 * under the control of the driver.
6497 */
c43bc57e 6498 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6499 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6500}
6501
6502static void e1000_print_device_info(struct e1000_adapter *adapter)
6503{
6504 struct e1000_hw *hw = &adapter->hw;
6505 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6506 u32 ret_val;
6507 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6508
6509 /* print bus type/speed/width info */
a5cc7642 6510 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6511 /* bus width */
6512 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6513 "Width x1"),
44defeb3 6514 /* MAC address */
7c510e4b 6515 netdev->dev_addr);
44defeb3
JK		 6516 e_info("Intel(R) PRO/%s Network Connection\n",
6517 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6518 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6519 E1000_PBANUM_LENGTH);
6520 if (ret_val)
f2315bf1 6521 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6522 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6523 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6524}
6525
10aa4c04
AK		 6526static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6527{
6528 struct e1000_hw *hw = &adapter->hw;
6529 int ret_val;
6530 u16 buf = 0;
6531
6532 if (hw->mac.type != e1000_82573)
6533 return;
6534
6535 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6536 le16_to_cpus(&buf);
6537 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6538 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6539 dev_warn(&adapter->pdev->dev,
6540 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6541 }
10aa4c04
AK		 6542}
6543
c8f44aff 6544static int e1000_set_features(struct net_device *netdev,
70495a50 6545 netdev_features_t features)
dc221294
BA		 6546{
6547 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6548 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6549
6550 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6551 adapter->flags |= FLAG_TSO_FORCE;
6552
f646968f 6553 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6554 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6555 NETIF_F_RXALL)))
dc221294
BA		 6556 return 0;
6557
0184039a
BG		 6558 if (changed & NETIF_F_RXFCS) {
6559 if (features & NETIF_F_RXFCS) {
6560 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6561 } else {
6562 /* We need to take it back to defaults, which might mean
6563 * stripping is still disabled at the adapter level.
6564 */
6565 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6566 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6567 else
6568 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6569 }
6570 }
6571
70495a50
BA		 6572 netdev->features = features;
6573
dc221294
BA		 6574 if (netif_running(netdev))
6575 e1000e_reinit_locked(adapter);
6576 else
6577 e1000e_reset(adapter);
6578
6579 return 0;
6580}
6581
651c2466
SH		 6582static const struct net_device_ops e1000e_netdev_ops = {
6583 .ndo_open = e1000_open,
6584 .ndo_stop = e1000_close,
00829823 6585 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6586 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6587 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6588 .ndo_set_mac_address = e1000_set_mac,
6589 .ndo_change_mtu = e1000_change_mtu,
6590 .ndo_do_ioctl = e1000_ioctl,
6591 .ndo_tx_timeout = e1000_tx_timeout,
6592 .ndo_validate_addr = eth_validate_addr,
6593
651c2466
SH		 6594 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6595 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6596#ifdef CONFIG_NET_POLL_CONTROLLER
6597 .ndo_poll_controller = e1000_netpoll,
6598#endif
dc221294 6599 .ndo_set_features = e1000_set_features,
651c2466
SH		 6600};
6601
bc7f75fa
AK		 6602/**
6603 * e1000_probe - Device Initialization Routine
6604 * @pdev: PCI device information struct
6605 * @ent: entry in e1000_pci_tbl
6606 *
6607 * Returns 0 on success, negative on failure
6608 *
6609 * e1000_probe initializes an adapter identified by a pci_dev structure.
6610 * The OS initialization, configuring of the adapter private structure,
6611 * and a hardware reset occur.
6612 **/
1dd06ae8 6613static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6614{
6615 struct net_device *netdev;
6616 struct e1000_adapter *adapter;
6617 struct e1000_hw *hw;
6618 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6619 resource_size_t mmio_start, mmio_len;
6620 resource_size_t flash_start, flash_len;
bc7f75fa 6621 static int cards_found;
78cd29d5 6622 u16 aspm_disable_flag = 0;
17e813ec 6623 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6624 u16 eeprom_data = 0;
6625 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6626
78cd29d5
BA		 6627 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6628 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6629 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6630 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6631 if (aspm_disable_flag)
6632 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6633
f0f422e5 6634 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6635 if (err)
6636 return err;
6637
6638 pci_using_dac = 0;
718a39eb 6639 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6640 if (!err) {
718a39eb 6641 pci_using_dac = 1;
bc7f75fa 6642 } else {
718a39eb 6643 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6644 if (err) {
718a39eb
RK		 6645 dev_err(&pdev->dev,
6646 "No usable DMA configuration, aborting\n");
6647 goto err_dma;
bc7f75fa
AK		 6648 }
6649 }
6650
17e813ec
BA		 6651 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6652 err = pci_request_selected_regions_exclusive(pdev, bars,
6653 e1000e_driver_name);
bc7f75fa
AK		 6654 if (err)
6655 goto err_pci_reg;
6656
68eac460 6657 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6658 pci_enable_pcie_error_reporting(pdev);
68eac460 6659
bc7f75fa 6660 pci_set_master(pdev);
438b365a
BA		 6661 /* PCI config space info */
6662 err = pci_save_state(pdev);
6663 if (err)
6664 goto err_alloc_etherdev;
bc7f75fa
AK		 6665
6666 err = -ENOMEM;
6667 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6668 if (!netdev)
6669 goto err_alloc_etherdev;
6670
bc7f75fa
AK		 6671 SET_NETDEV_DEV(netdev, &pdev->dev);
6672
f85e4dfa
TH		 6673 netdev->irq = pdev->irq;
6674
bc7f75fa
AK		 6675 pci_set_drvdata(pdev, netdev);
6676 adapter = netdev_priv(netdev);
6677 hw = &adapter->hw;
6678 adapter->netdev = netdev;
6679 adapter->pdev = pdev;
6680 adapter->ei = ei;
6681 adapter->pba = ei->pba;
6682 adapter->flags = ei->flags;
eb7c3adb 6683 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6684 adapter->hw.adapter = adapter;
6685 adapter->hw.mac.type = ei->mac;
2adc55c9 6686 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6687 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6688
6689 mmio_start = pci_resource_start(pdev, 0);
6690 mmio_len = pci_resource_len(pdev, 0);
6691
6692 err = -EIO;
6693 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6694 if (!adapter->hw.hw_addr)
6695 goto err_ioremap;
6696
6697 if ((adapter->flags & FLAG_HAS_FLASH) &&
6698 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6699 flash_start = pci_resource_start(pdev, 1);
6700 flash_len = pci_resource_len(pdev, 1);
6701 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6702 if (!adapter->hw.flash_address)
6703 goto err_flashmap;
6704 }
6705
d495bcb8
BA		 6706 /* Set default EEE advertisement */
6707 if (adapter->flags2 & FLAG2_HAS_EEE)
6708 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6709
bc7f75fa 6710 /* construct the net_device struct */
e80bd1d1 6711 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6712 e1000e_set_ethtool_ops(netdev);
e80bd1d1 6713 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6714 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6715 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6716
6717 netdev->mem_start = mmio_start;
6718 netdev->mem_end = mmio_start + mmio_len;
6719
6720 adapter->bd_number = cards_found++;
6721
4662e82b
BA		 6722 e1000e_check_options(adapter);
6723
bc7f75fa
AK		 6724 /* setup adapter struct */
6725 err = e1000_sw_init(adapter);
6726 if (err)
6727 goto err_sw_init;
6728
bc7f75fa
AK		 6729 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6730 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6731 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6732
69e3fd8c 6733 err = ei->get_variants(adapter);
bc7f75fa
AK		 6734 if (err)
6735 goto err_hw_init;
6736
4a770358
BA		 6737 if ((adapter->flags & FLAG_IS_ICH) &&
6738 (adapter->flags & FLAG_READ_ONLY_NVM))
6739 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6740
bc7f75fa
AK		 6741 hw->mac.ops.get_bus_info(&adapter->hw);
6742
318a94d6 6743 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6744
6745 /* Copper options */
318a94d6 6746 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6747 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6748 adapter->hw.phy.disable_polarity_correction = 0;
6749 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6750 }
6751
470a5420 6752 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6753 dev_info(&pdev->dev,
6754 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6755
dc221294
BA		 6756 /* Set initial default active device features */
6757 netdev->features = (NETIF_F_SG |
f646968f
PM		 6758 NETIF_F_HW_VLAN_CTAG_RX |
6759 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6760 NETIF_F_TSO |
6761 NETIF_F_TSO6 |
70495a50 6762 NETIF_F_RXHASH |
dc221294
BA		 6763 NETIF_F_RXCSUM |
6764 NETIF_F_HW_CSUM);
6765
6766 /* Set user-changeable features (subset of all device features) */
6767 netdev->hw_features = netdev->features;
0184039a 6768 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6769 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6770 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6771
6772 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6773 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6774
dc221294
BA		 6775 netdev->vlan_features |= (NETIF_F_SG |
6776 NETIF_F_TSO |
6777 NETIF_F_TSO6 |
6778 NETIF_F_HW_CSUM);
a5136e23 6779
ef9b965a
JB		 6780 netdev->priv_flags |= IFF_UNICAST_FLT;
6781
7b872a55 6782 if (pci_using_dac) {
bc7f75fa 6783 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6784 netdev->vlan_features |= NETIF_F_HIGHDMA;
6785 }
bc7f75fa 6786
bc7f75fa
AK		 6787 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6788 adapter->flags |= FLAG_MNG_PT_ENABLED;
6789
e921eb1a 6790 /* before reading the NVM, reset the controller to
ad68076e
BA		 6791 * put the device in a known good starting state
6792 */
bc7f75fa
AK		 6793 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6794
e921eb1a 6795 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6796 * attempt. Let's give it a few tries
6797 */
6798 for (i = 0;; i++) {
6799 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6800 break;
6801 if (i == 2) {
185095fb 6802 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6803 err = -EIO;
6804 goto err_eeprom;
6805 }
6806 }
6807
10aa4c04
AK		 6808 e1000_eeprom_checks(adapter);
6809
608f8a0d 6810 /* copy the MAC address */
bc7f75fa 6811 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6812 dev_err(&pdev->dev,
6813 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6814
6815 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6816
aaeb6cdf 6817 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6818 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6819 netdev->dev_addr);
bc7f75fa
AK		 6820 err = -EIO;
6821 goto err_eeprom;
6822 }
6823
6824 init_timer(&adapter->watchdog_timer);
c061b18d 6825 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6826 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6827
6828 init_timer(&adapter->phy_info_timer);
c061b18d 6829 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6830 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6831
6832 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6833 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6834 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6835 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6836 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6837
bc7f75fa
AK		 6838 /* Initialize link parameters. User can change them with ethtool */
6839 adapter->hw.mac.autoneg = 1;
3db1cd5c 6840 adapter->fc_autoneg = true;
5c48ef3e
BA		 6841 adapter->hw.fc.requested_mode = e1000_fc_default;
6842 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6843 adapter->hw.phy.autoneg_advertised = 0x2f;
6844
e921eb1a 6845 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6846 * the EEPROM, enable the ACPI Magic Packet filter
6847 */
6848 if (adapter->flags & FLAG_APME_IN_WUC) {
6849 /* APME bit in EEPROM is mapped to WUC.APME */
6850 eeprom_data = er32(WUC);
6851 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6852 if ((hw->mac.type > e1000_ich10lan) &&
6853 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6854 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6855 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6856 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6857 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6858 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6859 1, &eeprom_data);
bc7f75fa 6860 else
3d3a1676
BA		 6861 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6862 1, &eeprom_data);
bc7f75fa
AK		 6863 }
6864
6865 /* fetch WoL from EEPROM */
6866 if (eeprom_data & eeprom_apme_mask)
6867 adapter->eeprom_wol |= E1000_WUFC_MAG;
6868
e921eb1a 6869 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6870 * where the eeprom may be wrong or the board simply won't support
6871 * wake on lan on a particular port
6872 */
6873 if (!(adapter->flags & FLAG_HAS_WOL))
6874 adapter->eeprom_wol = 0;
6875
6876 /* initialize the wol settings based on the eeprom settings */
6877 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6878
6879 /* make sure adapter isn't asleep if manageability is enabled */
6880 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6881 (hw->mac.ops.check_mng_mode(hw)))
6882 device_wakeup_enable(&pdev->dev);
bc7f75fa 6883
84527590
BA		 6884 /* save off EEPROM version number */
6885 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6886
bc7f75fa
AK		 6887 /* reset the hardware with the new settings */
6888 e1000e_reset(adapter);
6889
e921eb1a 6890 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6891 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6892 * under the control of the driver.
6893 */
c43bc57e 6894 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6895 e1000e_get_hw_control(adapter);
bc7f75fa 6896
f2315bf1 6897 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6898 err = register_netdev(netdev);
6899 if (err)
6900 goto err_register;
6901
9c563d20
JB		 6902 /* carrier off reporting is important to ethtool even BEFORE open */
6903 netif_carrier_off(netdev);
6904
d89777bf
BA		 6905 /* init PTP hardware clock */
6906 e1000e_ptp_init(adapter);
6907
bc7f75fa
AK		 6908 e1000_print_device_info(adapter);
6909
f3ec4f87
AS		 6910 if (pci_dev_run_wake(pdev))
6911 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6912
bc7f75fa
AK		 6913 return 0;
6914
6915err_register:
c43bc57e 6916 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6917 e1000e_release_hw_control(adapter);
bc7f75fa 6918err_eeprom:
470a5420 6919 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6920 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6921err_hw_init:
bc7f75fa
AK		 6922 kfree(adapter->tx_ring);
6923 kfree(adapter->rx_ring);
6924err_sw_init:
c43bc57e
JB		 6925 if (adapter->hw.flash_address)
6926 iounmap(adapter->hw.flash_address);
e82f54ba 6927 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6928err_flashmap:
bc7f75fa
AK		 6929 iounmap(adapter->hw.hw_addr);
6930err_ioremap:
6931 free_netdev(netdev);
6932err_alloc_etherdev:
f0f422e5 6933 pci_release_selected_regions(pdev,
f0ff4398 6934 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6935err_pci_reg:
6936err_dma:
6937 pci_disable_device(pdev);
6938 return err;
6939}
6940
6941/**
6942 * e1000_remove - Device Removal Routine
6943 * @pdev: PCI device information struct
6944 *
6945 * e1000_remove is called by the PCI subsystem to alert the driver
6946 * that it should release a PCI device. The could be caused by a
6947 * Hot-Plug event, or because the driver is going to be removed from
6948 * memory.
6949 **/
9f9a12f8 6950static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6951{
6952 struct net_device *netdev = pci_get_drvdata(pdev);
6953 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6954 bool down = test_bit(__E1000_DOWN, &adapter->state);
6955
d89777bf
BA		 6956 e1000e_ptp_remove(adapter);
6957
e921eb1a 6958 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6959 * from being rescheduled.
ad68076e 6960 */
23606cf5
RW		 6961 if (!down)
6962 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6963 del_timer_sync(&adapter->watchdog_timer);
6964 del_timer_sync(&adapter->phy_info_timer);
6965
41cec6f1
BA		 6966 cancel_work_sync(&adapter->reset_task);
6967 cancel_work_sync(&adapter->watchdog_task);
6968 cancel_work_sync(&adapter->downshift_task);
6969 cancel_work_sync(&adapter->update_phy_task);
6970 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6971
b67e1913
BA		 6972 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6973 cancel_work_sync(&adapter->tx_hwtstamp_work);
6974 if (adapter->tx_hwtstamp_skb) {
6975 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6976 adapter->tx_hwtstamp_skb = NULL;
6977 }
6978 }
6979
23606cf5
RW		 6980 /* Don't lie to e1000_close() down the road. */
6981 if (!down)
6982 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6983 unregister_netdev(netdev);
6984
f3ec4f87
AS		 6985 if (pci_dev_run_wake(pdev))
6986 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6987
e921eb1a 6988 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6989 * would have already happened in close and is redundant.
6990 */
31dbe5b4 6991 e1000e_release_hw_control(adapter);
bc7f75fa 6992
4662e82b 6993 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6994 kfree(adapter->tx_ring);
6995 kfree(adapter->rx_ring);
6996
6997 iounmap(adapter->hw.hw_addr);
6998 if (adapter->hw.flash_address)
6999 iounmap(adapter->hw.flash_address);
f0f422e5 7000 pci_release_selected_regions(pdev,
f0ff4398 7001 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 7002
7003 free_netdev(netdev);
7004
111b9dc5 7005 /* AER disable */
19d5afd4 7006 pci_disable_pcie_error_reporting(pdev);
111b9dc5 7007
bc7f75fa
AK		 7008 pci_disable_device(pdev);
7009}
7010
7011/* PCI Error Recovery (ERS) */
3646f0e5 7012static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7013 .error_detected = e1000_io_error_detected,
7014 .slot_reset = e1000_io_slot_reset,
7015 .resume = e1000_io_resume,
7016};
7017
a3aa1884 7018static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 7019 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7020 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7021 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7022 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7023 board_82571 },
bc7f75fa
AK		 7024 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7025 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7026 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7027 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7028 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7029
bc7f75fa
AK		 7030 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7031 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7032 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7033 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7034
bc7f75fa
AK		 7035 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7036 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7037 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7038
4662e82b 7039 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7040 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7041 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7042
bc7f75fa
AK		 7043 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7044 board_80003es2lan },
7045 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7046 board_80003es2lan },
7047 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7048 board_80003es2lan },
7049 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7050 board_80003es2lan },
ad68076e 7051
bc7f75fa
AK		 7052 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7053 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7054 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7055 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7056 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7057 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7058 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7059 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7060
bc7f75fa
AK		 7061 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7062 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7063 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7064 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7065 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7066 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7067 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7068 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7069 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7070
7071 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7072 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7073 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7074
f4187b56
BA		 7075 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7076 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7077 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7078
a4f58f54
BA		 7079 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7080 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7081 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7082 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7083
d3738bb8
BA		 7084 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7085 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7086
2fbe4526
BA		 7087 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7088 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7089 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7090 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7091 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7092 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7093 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7094 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
2fbe4526 7095
f36bb6ca 7096 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7097};
7098MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7099
23606cf5 7100static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7101#ifdef CONFIG_PM_SLEEP
28002099
DE		 7102 .suspend = e1000e_pm_suspend,
7103 .resume = e1000e_pm_resume,
7104 .freeze = e1000e_pm_freeze,
7105 .thaw = e1000e_pm_thaw,
7106 .poweroff = e1000e_pm_suspend,
7107 .restore = e1000e_pm_resume,
72f72dcc 7108#endif
63eb48f1
DE		 7109 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7110 e1000e_pm_runtime_idle)
23606cf5
RW		 7111};
7112
bc7f75fa
AK		 7113/* PCI Device API Driver */
7114static struct pci_driver e1000_driver = {
7115 .name = e1000e_driver_name,
7116 .id_table = e1000_pci_tbl,
7117 .probe = e1000_probe,
9f9a12f8 7118 .remove = e1000_remove,
f36bb6ca
BA		 7119 .driver = {
7120 .pm = &e1000_pm_ops,
7121 },
bc7f75fa
AK		 7122 .shutdown = e1000_shutdown,
7123 .err_handler = &e1000_err_handler
7124};
7125
7126/**
7127 * e1000_init_module - Driver Registration Routine
7128 *
7129 * e1000_init_module is the first routine called when the driver is
7130 * loaded. All it does is register with the PCI subsystem.
7131 **/
7132static int __init e1000_init_module(void)
7133{
7134 int ret;
8544b9f7
BA		 7135 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7136 e1000e_driver_version);
e78b80b1 7137 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n");
bc7f75fa 7138 ret = pci_register_driver(&e1000_driver);
53ec5498 7139
bc7f75fa
AK		 7140 return ret;
7141}
7142module_init(e1000_init_module);
7143
7144/**
7145 * e1000_exit_module - Driver Exit Cleanup Routine
7146 *
7147 * e1000_exit_module is called just before the driver is removed
7148 * from memory.
7149 **/
7150static void __exit e1000_exit_module(void)
7151{
7152 pci_unregister_driver(&e1000_driver);
7153}
7154module_exit(e1000_exit_module);
7155
bc7f75fa
AK		 7156MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7157MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7158MODULE_LICENSE("GPL");
7159MODULE_VERSION(DRV_VERSION);
7160
06c24b91 7161/* netdev.c */
Linux kernel - Deliverables
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