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e1000e: Cleanup parenthesis around return value
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
8defe713 51#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 73};
74
84f4ee90
TI		 75struct e1000_reg_info {
76 u32 ofs;
77 char *name;
78};
79
84f4ee90 80static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 81 /* General Registers */
82 {E1000_CTRL, "CTRL"},
83 {E1000_STATUS, "STATUS"},
84 {E1000_CTRL_EXT, "CTRL_EXT"},
85
86 /* Interrupt Registers */
87 {E1000_ICR, "ICR"},
88
af667a29 89 /* Rx Registers */
84f4ee90 90 {E1000_RCTL, "RCTL"},
1e36052e
BA		 91 {E1000_RDLEN(0), "RDLEN"},
92 {E1000_RDH(0), "RDH"},
93 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 94 {E1000_RDTR, "RDTR"},
95 {E1000_RXDCTL(0), "RXDCTL"},
96 {E1000_ERT, "ERT"},
1e36052e
BA		 97 {E1000_RDBAL(0), "RDBAL"},
98 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 99 {E1000_RDFH, "RDFH"},
100 {E1000_RDFT, "RDFT"},
101 {E1000_RDFHS, "RDFHS"},
102 {E1000_RDFTS, "RDFTS"},
103 {E1000_RDFPC, "RDFPC"},
104
af667a29 105 /* Tx Registers */
84f4ee90 106 {E1000_TCTL, "TCTL"},
1e36052e
BA		 107 {E1000_TDBAL(0), "TDBAL"},
108 {E1000_TDBAH(0), "TDBAH"},
109 {E1000_TDLEN(0), "TDLEN"},
110 {E1000_TDH(0), "TDH"},
111 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 112 {E1000_TIDV, "TIDV"},
113 {E1000_TXDCTL(0), "TXDCTL"},
114 {E1000_TADV, "TADV"},
115 {E1000_TARC(0), "TARC"},
116 {E1000_TDFH, "TDFH"},
117 {E1000_TDFT, "TDFT"},
118 {E1000_TDFHS, "TDFHS"},
119 {E1000_TDFTS, "TDFTS"},
120 {E1000_TDFPC, "TDFPC"},
121
122 /* List Terminator */
f36bb6ca 123 {0, NULL}
84f4ee90
TI		 124};
125
e921eb1a 126/**
84f4ee90 127 * e1000_regdump - register printout routine
e921eb1a
BA		 128 * @hw: pointer to the HW structure
129 * @reginfo: pointer to the register info table
130 **/
84f4ee90
TI		 131static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
132{
133 int n = 0;
134 char rname[16];
135 u32 regs[8];
136
137 switch (reginfo->ofs) {
138 case E1000_RXDCTL(0):
139 for (n = 0; n < 2; n++)
140 regs[n] = __er32(hw, E1000_RXDCTL(n));
141 break;
142 case E1000_TXDCTL(0):
143 for (n = 0; n < 2; n++)
144 regs[n] = __er32(hw, E1000_TXDCTL(n));
145 break;
146 case E1000_TARC(0):
147 for (n = 0; n < 2; n++)
148 regs[n] = __er32(hw, E1000_TARC(n));
149 break;
150 default:
ef456f85
JK		 151 pr_info("%-15s %08x\n",
152 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 153 return;
154 }
155
156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 158}
159
f0c5dadf
ET		 160static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
161 struct e1000_buffer *bi)
162{
163 int i;
164 struct e1000_ps_page *ps_page;
165
166 for (i = 0; i < adapter->rx_ps_pages; i++) {
167 ps_page = &bi->ps_pages[i];
168
169 if (ps_page->page) {
170 pr_info("packet dump for ps_page %d:\n", i);
171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
172 16, 1, page_address(ps_page->page),
173 PAGE_SIZE, true);
174 }
175 }
176}
177
e921eb1a 178/**
af667a29 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 180 * @adapter: board private structure
181 **/
84f4ee90
TI		 182static void e1000e_dump(struct e1000_adapter *adapter)
183{
184 struct net_device *netdev = adapter->netdev;
185 struct e1000_hw *hw = &adapter->hw;
186 struct e1000_reg_info *reginfo;
187 struct e1000_ring *tx_ring = adapter->tx_ring;
188 struct e1000_tx_desc *tx_desc;
af667a29 189 struct my_u0 {
e885d762
BA		 190 __le64 a;
191 __le64 b;
af667a29 192 } *u0;
84f4ee90
TI		 193 struct e1000_buffer *buffer_info;
194 struct e1000_ring *rx_ring = adapter->rx_ring;
195 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 196 union e1000_rx_desc_extended *rx_desc;
af667a29 197 struct my_u1 {
e885d762
BA		 198 __le64 a;
199 __le64 b;
200 __le64 c;
201 __le64 d;
af667a29 202 } *u1;
84f4ee90
TI		 203 u32 staterr;
204 int i = 0;
205
206 if (!netif_msg_hw(adapter))
207 return;
208
209 /* Print netdevice Info */
210 if (netdev) {
211 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 212 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
214 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 215 }
216
217 /* Print Registers */
218 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 219 pr_info(" Register Name Value\n");
84f4ee90
TI		 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
221 reginfo->name; reginfo++) {
222 e1000_regdump(hw, reginfo);
223 }
224
af667a29 225 /* Print Tx Ring Summary */
84f4ee90 226 if (!netdev || !netif_running(netdev))
fe1e980f 227 return;
84f4ee90 228
af667a29 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
233 0, tx_ring->next_to_use, tx_ring->next_to_clean,
234 (unsigned long long)buffer_info->dma,
235 buffer_info->length,
236 buffer_info->next_to_watch,
237 (unsigned long long)buffer_info->time_stamp);
84f4ee90 238
af667a29 239 /* Print Tx Ring */
84f4ee90
TI		 240 if (!netif_msg_tx_done(adapter))
241 goto rx_ring_summary;
242
af667a29 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 244
245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
246 *
247 * Legacy Transmit Descriptor
248 * +--------------------------------------------------------------+
249 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
250 * +--------------------------------------------------------------+
251 * 8 | Special | CSS | Status | CMD | CSO | Length |
252 * +--------------------------------------------------------------+
253 * 63 48 47 36 35 32 31 24 23 16 15 0
254 *
255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
256 * 63 48 47 40 39 32 31 16 15 8 7 0
257 * +----------------------------------------------------------------+
258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
259 * +----------------------------------------------------------------+
260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
261 * +----------------------------------------------------------------+
262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
263 *
264 * Extended Data Descriptor (DTYP=0x1)
265 * +----------------------------------------------------------------+
266 * 0 | Buffer Address [63:0] |
267 * +----------------------------------------------------------------+
268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 */
ef456f85
JK		 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 276 const char *next_desc;
84f4ee90
TI		 277 tx_desc = E1000_TX_DESC(*tx_ring, i);
278 buffer_info = &tx_ring->buffer_info[i];
279 u0 = (struct my_u0 *)tx_desc;
84f4ee90 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 281 next_desc = " NTC/U";
84f4ee90 282 else if (i == tx_ring->next_to_use)
ef456f85 283 next_desc = " NTU";
84f4ee90 284 else if (i == tx_ring->next_to_clean)
ef456f85 285 next_desc = " NTC";
84f4ee90 286 else
ef456f85
JK		 287 next_desc = "";
288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
291 i,
292 (unsigned long long)le64_to_cpu(u0->a),
293 (unsigned long long)le64_to_cpu(u0->b),
294 (unsigned long long)buffer_info->dma,
295 buffer_info->length, buffer_info->next_to_watch,
296 (unsigned long long)buffer_info->time_stamp,
297 buffer_info->skb, next_desc);
84f4ee90 298
f0c5dadf 299 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 301 16, 1, buffer_info->skb->data,
302 buffer_info->skb->len, true);
84f4ee90
TI		 303 }
304
af667a29 305 /* Print Rx Ring Summary */
84f4ee90 306rx_ring_summary:
af667a29 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 308 pr_info("Queue [NTU] [NTC]\n");
309 pr_info(" %5d %5X %5X\n",
310 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 311
af667a29 312 /* Print Rx Ring */
84f4ee90 313 if (!netif_msg_rx_status(adapter))
fe1e980f 314 return;
84f4ee90 315
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 317 switch (adapter->rx_ps_pages) {
318 case 1:
319 case 2:
320 case 3:
321 /* [Extended] Packet Split Receive Descriptor Format
322 *
323 * +-----------------------------------------------------+
324 * 0 | Buffer Address 0 [63:0] |
325 * +-----------------------------------------------------+
326 * 8 | Buffer Address 1 [63:0] |
327 * +-----------------------------------------------------+
328 * 16 | Buffer Address 2 [63:0] |
329 * +-----------------------------------------------------+
330 * 24 | Buffer Address 3 [63:0] |
331 * +-----------------------------------------------------+
332 */
ef456f85 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 334 /* [Extended] Receive Descriptor (Write-Back) Format
335 *
336 * 63 48 47 32 31 13 12 8 7 4 3 0
337 * +------------------------------------------------------+
338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
339 * | Checksum | Ident | | Queue | | Type |
340 * +------------------------------------------------------+
341 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
342 * +------------------------------------------------------+
343 * 63 48 47 32 31 20 19 0
344 */
ef456f85 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 346 for (i = 0; i < rx_ring->count; i++) {
ef456f85 347 const char *next_desc;
84f4ee90
TI		 348 buffer_info = &rx_ring->buffer_info[i];
349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
350 u1 = (struct my_u1 *)rx_desc_ps;
351 staterr =
af667a29 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 353
354 if (i == rx_ring->next_to_use)
355 next_desc = " NTU";
356 else if (i == rx_ring->next_to_clean)
357 next_desc = " NTC";
358 else
359 next_desc = "";
360
84f4ee90
TI		 361 if (staterr & E1000_RXD_STAT_DD) {
362 /* Descriptor Done */
ef456f85
JK		 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
364 "RWB", i,
365 (unsigned long long)le64_to_cpu(u1->a),
366 (unsigned long long)le64_to_cpu(u1->b),
367 (unsigned long long)le64_to_cpu(u1->c),
368 (unsigned long long)le64_to_cpu(u1->d),
369 buffer_info->skb, next_desc);
84f4ee90 370 } else {
ef456f85
JK		 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
372 "R ", i,
373 (unsigned long long)le64_to_cpu(u1->a),
374 (unsigned long long)le64_to_cpu(u1->b),
375 (unsigned long long)le64_to_cpu(u1->c),
376 (unsigned long long)le64_to_cpu(u1->d),
377 (unsigned long long)buffer_info->dma,
378 buffer_info->skb, next_desc);
84f4ee90
TI		 379
380 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 381 e1000e_dump_ps_pages(adapter,
382 buffer_info);
84f4ee90 383 }
84f4ee90
TI		 384 }
385 break;
386 default:
387 case 0:
5f450212 388 /* Extended Receive Descriptor (Read) Format
84f4ee90 389 *
5f450212
BA		 390 * +-----------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +-----------------------------------------------------+
393 * 8 | Reserved |
394 * +-----------------------------------------------------+
84f4ee90 395 */
ef456f85 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 397 /* Extended Receive Descriptor (Write-Back) Format
398 *
399 * 63 48 47 32 31 24 23 4 3 0
400 * +------------------------------------------------------+
401 * | RSS Hash | | | |
402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
403 * | Packet | IP | | | Type |
404 * | Checksum | Ident | | | |
405 * +------------------------------------------------------+
406 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
407 * +------------------------------------------------------+
408 * 63 48 47 32 31 20 19 0
409 */
ef456f85 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 411
412 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 413 const char *next_desc;
414
84f4ee90 415 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
417 u1 = (struct my_u1 *)rx_desc;
418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 419
420 if (i == rx_ring->next_to_use)
421 next_desc = " NTU";
422 else if (i == rx_ring->next_to_clean)
423 next_desc = " NTC";
424 else
425 next_desc = "";
426
5f450212
BA		 427 if (staterr & E1000_RXD_STAT_DD) {
428 /* Descriptor Done */
ef456f85
JK		 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
430 "RWB", i,
431 (unsigned long long)le64_to_cpu(u1->a),
432 (unsigned long long)le64_to_cpu(u1->b),
433 buffer_info->skb, next_desc);
5f450212 434 } else {
ef456f85
JK		 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
436 "R ", i,
437 (unsigned long long)le64_to_cpu(u1->a),
438 (unsigned long long)le64_to_cpu(u1->b),
439 (unsigned long long)buffer_info->dma,
440 buffer_info->skb, next_desc);
5f450212 441
f0c5dadf
ET		 442 if (netif_msg_pktdata(adapter) &&
443 buffer_info->skb)
5f450212
BA		 444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16,
446 1,
f0c5dadf 447 buffer_info->skb->data,
5f450212
BA		 448 adapter->rx_buffer_len,
449 true);
450 }
84f4ee90
TI		 451 }
452 }
84f4ee90
TI		 453}
454
bc7f75fa
AK		 455/**
456 * e1000_desc_unused - calculate if we have unused descriptors
457 **/
458static int e1000_desc_unused(struct e1000_ring *ring)
459{
460 if (ring->next_to_clean > ring->next_to_use)
461 return ring->next_to_clean - ring->next_to_use - 1;
462
463 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
464}
465
b67e1913
BA		 466/**
467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
468 * @adapter: board private structure
469 * @hwtstamps: time stamp structure to update
470 * @systim: unsigned 64bit system time value.
471 *
472 * Convert the system time value stored in the RX/TXSTMP registers into a
473 * hwtstamp which can be used by the upper level time stamping functions.
474 *
475 * The 'systim_lock' spinlock is used to protect the consistency of the
476 * system time value. This is needed because reading the 64 bit time
477 * value involves reading two 32 bit registers. The first read latches the
478 * value.
479 **/
480static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
481 struct skb_shared_hwtstamps *hwtstamps,
482 u64 systim)
483{
484 u64 ns;
485 unsigned long flags;
486
487 spin_lock_irqsave(&adapter->systim_lock, flags);
488 ns = timecounter_cyc2time(&adapter->tc, systim);
489 spin_unlock_irqrestore(&adapter->systim_lock, flags);
490
491 memset(hwtstamps, 0, sizeof(*hwtstamps));
492 hwtstamps->hwtstamp = ns_to_ktime(ns);
493}
494
495/**
496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
497 * @adapter: board private structure
498 * @status: descriptor extended error and status field
499 * @skb: particular skb to include time stamp
500 *
501 * If the time stamp is valid, convert it into the timecounter ns value
502 * and store that result into the shhwtstamps structure which is passed
503 * up the network stack.
504 **/
505static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
506 struct sk_buff *skb)
507{
508 struct e1000_hw *hw = &adapter->hw;
509 u64 rxstmp;
510
511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
512 !(status & E1000_RXDEXT_STATERR_TST) ||
513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
514 return;
515
516 /* The Rx time stamp registers contain the time stamp. No other
517 * received packet will be time stamped until the Rx time stamp
518 * registers are read. Because only one packet can be time stamped
519 * at a time, the register values must belong to this packet and
520 * therefore none of the other additional attributes need to be
521 * compared.
522 */
523 rxstmp = (u64)er32(RXSTMPL);
524 rxstmp |= (u64)er32(RXSTMPH) << 32;
525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
526
527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
528}
529
bc7f75fa 530/**
ad68076e 531 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 532 * @adapter: board private structure
b67e1913 533 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
535 * @skb: pointer to sk_buff to be indicated to stack
536 **/
537static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 538 struct net_device *netdev, struct sk_buff *skb,
b67e1913 539 u32 staterr, __le16 vlan)
bc7f75fa 540{
86d70e53 541 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 542
543 e1000e_rx_hwtstamp(adapter, staterr, skb);
544
bc7f75fa
AK		 545 skb->protocol = eth_type_trans(skb, netdev);
546
b67e1913 547 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 549
550 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 551}
552
553/**
af667a29 554 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 555 * @adapter: board private structure
556 * @status_err: receive descriptor status and error fields
557 * @csum: receive descriptor csum field
558 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 559 **/
560static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 561 struct sk_buff *skb)
bc7f75fa
AK		 562{
563 u16 status = (u16)status_err;
564 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 565
566 skb_checksum_none_assert(skb);
bc7f75fa 567
afd12939
BA		 568 /* Rx checksum disabled */
569 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
570 return;
571
bc7f75fa
AK		 572 /* Ignore Checksum bit is set */
573 if (status & E1000_RXD_STAT_IXSM)
574 return;
afd12939 575
2e1706f2
BA		 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */
577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 578 /* let the stack verify checksum errors */
579 adapter->hw_csum_err++;
580 return;
581 }
582
583 /* TCP/UDP Checksum has not been calculated */
584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
585 return;
586
587 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 588 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 589 adapter->hw_csum_good++;
590}
591
55aa6985 592static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 593{
55aa6985 594 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 595 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 596 s32 ret_val = __ew32_prepare(hw);
597
598 writel(i, rx_ring->tail);
c6e7f51e 599
bdc125f7 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e 601 u32 rctl = er32(RCTL);
6cf08d1c 602
c6e7f51e
BA		 603 ew32(RCTL, rctl & ~E1000_RCTL_EN);
604 e_err("ME firmware caused invalid RDT - resetting\n");
605 schedule_work(&adapter->reset_task);
606 }
607}
608
55aa6985 609static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 610{
55aa6985 611 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 612 struct e1000_hw *hw = &adapter->hw;
bdc125f7 613 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 614
bdc125f7
BA		 615 writel(i, tx_ring->tail);
616
617 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e 618 u32 tctl = er32(TCTL);
6cf08d1c 619
c6e7f51e
BA		 620 ew32(TCTL, tctl & ~E1000_TCTL_EN);
621 e_err("ME firmware caused invalid TDT - resetting\n");
622 schedule_work(&adapter->reset_task);
623 }
624}
625
bc7f75fa 626/**
5f450212 627 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 628 * @rx_ring: Rx descriptor ring
bc7f75fa 629 **/
55aa6985 630static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 631 int cleaned_count, gfp_t gfp)
bc7f75fa 632{
55aa6985 633 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 634 struct net_device *netdev = adapter->netdev;
635 struct pci_dev *pdev = adapter->pdev;
5f450212 636 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 637 struct e1000_buffer *buffer_info;
638 struct sk_buff *skb;
639 unsigned int i;
89d71a66 640 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 641
642 i = rx_ring->next_to_use;
643 buffer_info = &rx_ring->buffer_info[i];
644
645 while (cleaned_count--) {
646 skb = buffer_info->skb;
647 if (skb) {
648 skb_trim(skb, 0);
649 goto map_skb;
650 }
651
c2fed996 652 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 653 if (!skb) {
654 /* Better luck next round */
655 adapter->alloc_rx_buff_failed++;
656 break;
657 }
658
bc7f75fa
AK		 659 buffer_info->skb = skb;
660map_skb:
0be3f55f 661 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 662 adapter->rx_buffer_len,
0be3f55f
NN		 663 DMA_FROM_DEVICE);
664 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 665 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 666 adapter->rx_dma_failed++;
667 break;
668 }
669
5f450212
BA		 670 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
671 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 672
50849d79 673 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 674 /* Force memory writes to complete before letting h/w
50849d79
TH		 675 * know there are new descriptors to fetch. (Only
676 * applicable for weak-ordered memory model archs,
677 * such as IA-64).
678 */
679 wmb();
c6e7f51e 680 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 681 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 682 else
c5083cf6 683 writel(i, rx_ring->tail);
50849d79 684 }
bc7f75fa
AK		 685 i++;
686 if (i == rx_ring->count)
687 i = 0;
688 buffer_info = &rx_ring->buffer_info[i];
689 }
690
50849d79 691 rx_ring->next_to_use = i;
bc7f75fa
AK		 692}
693
694/**
695 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 696 * @rx_ring: Rx descriptor ring
bc7f75fa 697 **/
55aa6985 698static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 699 int cleaned_count, gfp_t gfp)
bc7f75fa 700{
55aa6985 701 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 702 struct net_device *netdev = adapter->netdev;
703 struct pci_dev *pdev = adapter->pdev;
704 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 705 struct e1000_buffer *buffer_info;
706 struct e1000_ps_page *ps_page;
707 struct sk_buff *skb;
708 unsigned int i, j;
709
710 i = rx_ring->next_to_use;
711 buffer_info = &rx_ring->buffer_info[i];
712
713 while (cleaned_count--) {
714 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
715
716 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 717 ps_page = &buffer_info->ps_pages[j];
718 if (j >= adapter->rx_ps_pages) {
719 /* all unused desc entries get hw null ptr */
af667a29
BA		 720 rx_desc->read.buffer_addr[j + 1] =
721 ~cpu_to_le64(0);
47f44e40
AK		 722 continue;
723 }
724 if (!ps_page->page) {
c2fed996 725 ps_page->page = alloc_page(gfp);
bc7f75fa 726 if (!ps_page->page) {
47f44e40
AK		 727 adapter->alloc_rx_buff_failed++;
728 goto no_buffers;
729 }
0be3f55f
NN		 730 ps_page->dma = dma_map_page(&pdev->dev,
731 ps_page->page,
732 0, PAGE_SIZE,
733 DMA_FROM_DEVICE);
734 if (dma_mapping_error(&pdev->dev,
735 ps_page->dma)) {
47f44e40 736 dev_err(&adapter->pdev->dev,
af667a29 737 "Rx DMA page map failed\n");
47f44e40
AK		 738 adapter->rx_dma_failed++;
739 goto no_buffers;
bc7f75fa 740 }
bc7f75fa 741 }
e921eb1a 742 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 743 * didn't change because each write-back
744 * erases this info.
745 */
af667a29
BA		 746 rx_desc->read.buffer_addr[j + 1] =
747 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 748 }
749
e5fe2541 750 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 751 gfp);
bc7f75fa
AK		 752
753 if (!skb) {
754 adapter->alloc_rx_buff_failed++;
755 break;
756 }
757
bc7f75fa 758 buffer_info->skb = skb;
0be3f55f 759 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 760 adapter->rx_ps_bsize0,
0be3f55f
NN		 761 DMA_FROM_DEVICE);
762 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 763 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 764 adapter->rx_dma_failed++;
765 /* cleanup skb */
766 dev_kfree_skb_any(skb);
767 buffer_info->skb = NULL;
768 break;
769 }
770
771 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
772
50849d79 773 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 774 /* Force memory writes to complete before letting h/w
50849d79
TH		 775 * know there are new descriptors to fetch. (Only
776 * applicable for weak-ordered memory model archs,
777 * such as IA-64).
778 */
779 wmb();
c6e7f51e 780 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 781 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 782 else
c5083cf6 783 writel(i << 1, rx_ring->tail);
50849d79
TH		 784 }
785
bc7f75fa
AK		 786 i++;
787 if (i == rx_ring->count)
788 i = 0;
789 buffer_info = &rx_ring->buffer_info[i];
790 }
791
792no_buffers:
50849d79 793 rx_ring->next_to_use = i;
bc7f75fa
AK		 794}
795
97ac8cae
BA		 796/**
797 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 798 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 799 * @cleaned_count: number of buffers to allocate this pass
800 **/
801
55aa6985 802static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 803 int cleaned_count, gfp_t gfp)
97ac8cae 804{
55aa6985 805 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 806 struct net_device *netdev = adapter->netdev;
807 struct pci_dev *pdev = adapter->pdev;
5f450212 808 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 809 struct e1000_buffer *buffer_info;
810 struct sk_buff *skb;
811 unsigned int i;
2a2293b9 812 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 813
814 i = rx_ring->next_to_use;
815 buffer_info = &rx_ring->buffer_info[i];
816
817 while (cleaned_count--) {
818 skb = buffer_info->skb;
819 if (skb) {
820 skb_trim(skb, 0);
821 goto check_page;
822 }
823
c2fed996 824 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 825 if (unlikely(!skb)) {
826 /* Better luck next round */
827 adapter->alloc_rx_buff_failed++;
828 break;
829 }
830
97ac8cae
BA		 831 buffer_info->skb = skb;
832check_page:
833 /* allocate a new page if necessary */
834 if (!buffer_info->page) {
c2fed996 835 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 836 if (unlikely(!buffer_info->page)) {
837 adapter->alloc_rx_buff_failed++;
838 break;
839 }
840 }
841
37287fae 842 if (!buffer_info->dma) {
0be3f55f 843 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 844 buffer_info->page, 0,
845 PAGE_SIZE,
0be3f55f 846 DMA_FROM_DEVICE);
37287fae
CP		 847 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
848 adapter->alloc_rx_buff_failed++;
849 break;
850 }
851 }
97ac8cae 852
5f450212
BA		 853 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
854 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 855
856 if (unlikely(++i == rx_ring->count))
857 i = 0;
858 buffer_info = &rx_ring->buffer_info[i];
859 }
860
861 if (likely(rx_ring->next_to_use != i)) {
862 rx_ring->next_to_use = i;
863 if (unlikely(i-- == 0))
864 i = (rx_ring->count - 1);
865
866 /* Force memory writes to complete before letting h/w
867 * know there are new descriptors to fetch. (Only
868 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 869 * such as IA-64).
870 */
97ac8cae 871 wmb();
c6e7f51e 872 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 873 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 874 else
c5083cf6 875 writel(i, rx_ring->tail);
97ac8cae
BA		 876 }
877}
878
70495a50
BA		 879static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
880 struct sk_buff *skb)
881{
882 if (netdev->features & NETIF_F_RXHASH)
e25909bc 883 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 884}
885
bc7f75fa 886/**
55aa6985
BA		 887 * e1000_clean_rx_irq - Send received data up the network stack
888 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 889 *
890 * the return value indicates whether actual cleaning was done, there
891 * is no guarantee that everything was cleaned
892 **/
55aa6985
BA		 893static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
894 int work_to_do)
bc7f75fa 895{
55aa6985 896 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 897 struct net_device *netdev = adapter->netdev;
898 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 899 struct e1000_hw *hw = &adapter->hw;
5f450212 900 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 901 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 902 u32 length, staterr;
bc7f75fa
AK		 903 unsigned int i;
904 int cleaned_count = 0;
3db1cd5c 905 bool cleaned = false;
bc7f75fa
AK		 906 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
907
908 i = rx_ring->next_to_clean;
5f450212
BA		 909 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
910 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 911 buffer_info = &rx_ring->buffer_info[i];
912
5f450212 913 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 914 struct sk_buff *skb;
bc7f75fa
AK		 915
916 if (*work_done >= work_to_do)
917 break;
918 (*work_done)++;
2d0bb1c1 919 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 920
bc7f75fa
AK		 921 skb = buffer_info->skb;
922 buffer_info->skb = NULL;
923
924 prefetch(skb->data - NET_IP_ALIGN);
925
926 i++;
927 if (i == rx_ring->count)
928 i = 0;
5f450212 929 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 930 prefetch(next_rxd);
931
932 next_buffer = &rx_ring->buffer_info[i];
933
3db1cd5c 934 cleaned = true;
bc7f75fa 935 cleaned_count++;
e5fe2541
BA		 936 dma_unmap_single(&pdev->dev, buffer_info->dma,
937 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 938 buffer_info->dma = 0;
939
5f450212 940 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 941
e921eb1a 942 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 943 * packet, if that's the case we need to toss it. In fact, we
944 * need to toss every packet with the EOP bit clear and the
945 * next frame that _does_ have the EOP bit set, as it is by
946 * definition only a frame fragment
947 */
5f450212 948 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 949 adapter->flags2 |= FLAG2_IS_DISCARDING;
950
951 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 952 /* All receives must fit into a single buffer */
3bb99fe2 953 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 954 /* recycle */
955 buffer_info->skb = skb;
5f450212 956 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 957 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 958 goto next_desc;
959 }
960
cf955e6c
BG		 961 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
962 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 963 /* recycle */
964 buffer_info->skb = skb;
965 goto next_desc;
966 }
967
eb7c3adb 968 /* adjust length to remove Ethernet CRC */
0184039a
BG		 969 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
970 /* If configured to store CRC, don't subtract FCS,
971 * but keep the FCS bytes out of the total_rx_bytes
972 * counter
973 */
974 if (netdev->features & NETIF_F_RXFCS)
975 total_rx_bytes -= 4;
976 else
977 length -= 4;
978 }
eb7c3adb 979
bc7f75fa
AK		 980 total_rx_bytes += length;
981 total_rx_packets++;
982
e921eb1a 983 /* code added for copybreak, this should improve
bc7f75fa 984 * performance for small packets with large amounts
ad68076e
BA		 985 * of reassembly being done in the stack
986 */
bc7f75fa
AK		 987 if (length < copybreak) {
988 struct sk_buff *new_skb =
89d71a66 989 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 990 if (new_skb) {
808ff676
BA		 991 skb_copy_to_linear_data_offset(new_skb,
992 -NET_IP_ALIGN,
993 (skb->data -
994 NET_IP_ALIGN),
995 (length +
996 NET_IP_ALIGN));
bc7f75fa
AK		 997 /* save the skb in buffer_info as good */
998 buffer_info->skb = skb;
999 skb = new_skb;
1000 }
1001 /* else just continue with the old one */
1002 }
1003 /* end copybreak code */
1004 skb_put(skb, length);
1005
1006 /* Receive Checksum Offload */
2e1706f2 1007 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1008
70495a50
BA		 1009 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1010
5f450212
BA		 1011 e1000_receive_skb(adapter, netdev, skb, staterr,
1012 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1013
1014next_desc:
5f450212 1015 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1016
1017 /* return some buffers to hardware, one at a time is too slow */
1018 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1019 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1020 GFP_ATOMIC);
bc7f75fa
AK		 1021 cleaned_count = 0;
1022 }
1023
1024 /* use prefetched values */
1025 rx_desc = next_rxd;
1026 buffer_info = next_buffer;
5f450212
BA		 1027
1028 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1029 }
1030 rx_ring->next_to_clean = i;
1031
1032 cleaned_count = e1000_desc_unused(rx_ring);
1033 if (cleaned_count)
55aa6985 1034 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1035
bc7f75fa 1036 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1037 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1038 return cleaned;
1039}
1040
55aa6985
BA		 1041static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1042 struct e1000_buffer *buffer_info)
bc7f75fa 1043{
55aa6985
BA		 1044 struct e1000_adapter *adapter = tx_ring->adapter;
1045
03b1320d
AD		 1046 if (buffer_info->dma) {
1047 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1048 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1049 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1050 else
0be3f55f
NN		 1051 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1052 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1053 buffer_info->dma = 0;
1054 }
bc7f75fa
AK		 1055 if (buffer_info->skb) {
1056 dev_kfree_skb_any(buffer_info->skb);
1057 buffer_info->skb = NULL;
1058 }
1b7719c4 1059 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1060}
1061
41cec6f1 1062static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1063{
41cec6f1 1064 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1065 struct e1000_adapter,
1066 print_hang_task);
09357b00 1067 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1068 struct e1000_ring *tx_ring = adapter->tx_ring;
1069 unsigned int i = tx_ring->next_to_clean;
1070 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1071 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1072 struct e1000_hw *hw = &adapter->hw;
1073 u16 phy_status, phy_1000t_status, phy_ext_status;
1074 u16 pci_status;
1075
615b32af
JB		 1076 if (test_bit(__E1000_DOWN, &adapter->state))
1077 return;
1078
e5fe2541 1079 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1080 /* May be block on write-back, flush and detect again
09357b00
JK		 1081 * flush pending descriptor writebacks to memory
1082 */
1083 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1084 /* execute the writes immediately */
1085 e1e_flush();
e921eb1a 1086 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1087 * the write is successful
1088 */
1089 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1090 /* execute the writes immediately */
1091 e1e_flush();
09357b00
JK		 1092 adapter->tx_hang_recheck = true;
1093 return;
1094 }
09357b00 1095 adapter->tx_hang_recheck = false;
d9554e96
DE		 1096
1097 if (er32(TDH(0)) == er32(TDT(0))) {
1098 e_dbg("false hang detected, ignoring\n");
1099 return;
1100 }
1101
1102 /* Real hang detected */
09357b00
JK		 1103 netif_stop_queue(netdev);
1104
c2ade1a4
BA		 1105 e1e_rphy(hw, MII_BMSR, &phy_status);
1106 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1107 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1108
41cec6f1
BA		 1109 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1110
1111 /* detected Hardware unit hang */
1112 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1113 " TDH <%x>\n"
1114 " TDT <%x>\n"
1115 " next_to_use <%x>\n"
1116 " next_to_clean <%x>\n"
1117 "buffer_info[next_to_clean]:\n"
1118 " time_stamp <%lx>\n"
1119 " next_to_watch <%x>\n"
1120 " jiffies <%lx>\n"
41cec6f1
BA		 1121 " next_to_watch.status <%x>\n"
1122 "MAC Status <%x>\n"
1123 "PHY Status <%x>\n"
1124 "PHY 1000BASE-T Status <%x>\n"
1125 "PHY Extended Status <%x>\n"
1126 "PCI Status <%x>\n",
e5fe2541
BA		 1127 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1128 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1129 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1130 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1131
d9554e96
DE		 1132 e1000e_dump(adapter);
1133
7c0427ee
BA		 1134 /* Suggest workaround for known h/w issue */
1135 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1136 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1137}
1138
b67e1913
BA		 1139/**
1140 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1141 * @work: pointer to work struct
1142 *
1143 * This work function polls the TSYNCTXCTL valid bit to determine when a
1144 * timestamp has been taken for the current stored skb. The timestamp must
1145 * be for this skb because only one such packet is allowed in the queue.
1146 */
1147static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1148{
1149 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1150 tx_hwtstamp_work);
1151 struct e1000_hw *hw = &adapter->hw;
1152
b67e1913
BA		 1153 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1154 struct skb_shared_hwtstamps shhwtstamps;
1155 u64 txstmp;
1156
1157 txstmp = er32(TXSTMPL);
1158 txstmp |= (u64)er32(TXSTMPH) << 32;
1159
1160 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1161
1162 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1163 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1164 adapter->tx_hwtstamp_skb = NULL;
59c871c5
JK		 1165 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1166 + adapter->tx_timeout_factor * HZ)) {
1167 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1168 adapter->tx_hwtstamp_skb = NULL;
1169 adapter->tx_hwtstamp_timeouts++;
c5ffe7e1 1170 e_warn("clearing Tx timestamp hang\n");
b67e1913
BA		 1171 } else {
1172 /* reschedule to check later */
1173 schedule_work(&adapter->tx_hwtstamp_work);
1174 }
1175}
1176
bc7f75fa
AK		 1177/**
1178 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1179 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1180 *
1181 * the return value indicates whether actual cleaning was done, there
1182 * is no guarantee that everything was cleaned
1183 **/
55aa6985 1184static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1185{
55aa6985 1186 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1187 struct net_device *netdev = adapter->netdev;
1188 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1189 struct e1000_tx_desc *tx_desc, *eop_desc;
1190 struct e1000_buffer *buffer_info;
1191 unsigned int i, eop;
1192 unsigned int count = 0;
bc7f75fa 1193 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1194 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1195
1196 i = tx_ring->next_to_clean;
1197 eop = tx_ring->buffer_info[i].next_to_watch;
1198 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1199
12d04a3c
AD		 1200 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1201 (count < tx_ring->count)) {
a86043c2 1202 bool cleaned = false;
6cf08d1c 1203
e80bd1d1 1204 rmb(); /* read buffer_info after eop_desc */
a86043c2 1205 for (; !cleaned; count++) {
bc7f75fa
AK		 1206 tx_desc = E1000_TX_DESC(*tx_ring, i);
1207 buffer_info = &tx_ring->buffer_info[i];
1208 cleaned = (i == eop);
1209
1210 if (cleaned) {
9ed318d5
TH		 1211 total_tx_packets += buffer_info->segs;
1212 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1213 if (buffer_info->skb) {
1214 bytes_compl += buffer_info->skb->len;
1215 pkts_compl++;
1216 }
bc7f75fa
AK		 1217 }
1218
55aa6985 1219 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1220 tx_desc->upper.data = 0;
1221
1222 i++;
1223 if (i == tx_ring->count)
1224 i = 0;
1225 }
1226
dac87619
TL		 1227 if (i == tx_ring->next_to_use)
1228 break;
bc7f75fa
AK		 1229 eop = tx_ring->buffer_info[i].next_to_watch;
1230 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1231 }
1232
1233 tx_ring->next_to_clean = i;
1234
3f0cfa3b
TH		 1235 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1236
bc7f75fa 1237#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1238 if (count && netif_carrier_ok(netdev) &&
1239 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1240 /* Make sure that anybody stopping the queue after this
1241 * sees the new next_to_clean.
1242 */
1243 smp_mb();
1244
1245 if (netif_queue_stopped(netdev) &&
1246 !(test_bit(__E1000_DOWN, &adapter->state))) {
1247 netif_wake_queue(netdev);
1248 ++adapter->restart_queue;
1249 }
1250 }
1251
1252 if (adapter->detect_tx_hung) {
e921eb1a 1253 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1254 * check with the clearing of time_stamp and movement of i
1255 */
3db1cd5c 1256 adapter->detect_tx_hung = false;
12d04a3c
AD		 1257 if (tx_ring->buffer_info[i].time_stamp &&
1258 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1259 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1260 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1261 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1262 else
1263 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1264 }
1265 adapter->total_tx_bytes += total_tx_bytes;
1266 adapter->total_tx_packets += total_tx_packets;
807540ba 1267 return count < tx_ring->count;
bc7f75fa
AK		 1268}
1269
bc7f75fa
AK		 1270/**
1271 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1272 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1273 *
1274 * the return value indicates whether actual cleaning was done, there
1275 * is no guarantee that everything was cleaned
1276 **/
55aa6985
BA		 1277static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1278 int work_to_do)
bc7f75fa 1279{
55aa6985 1280 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1281 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1282 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1283 struct net_device *netdev = adapter->netdev;
1284 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1285 struct e1000_buffer *buffer_info, *next_buffer;
1286 struct e1000_ps_page *ps_page;
1287 struct sk_buff *skb;
1288 unsigned int i, j;
1289 u32 length, staterr;
1290 int cleaned_count = 0;
3db1cd5c 1291 bool cleaned = false;
bc7f75fa
AK		 1292 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1293
1294 i = rx_ring->next_to_clean;
1295 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1296 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1297 buffer_info = &rx_ring->buffer_info[i];
1298
1299 while (staterr & E1000_RXD_STAT_DD) {
1300 if (*work_done >= work_to_do)
1301 break;
1302 (*work_done)++;
1303 skb = buffer_info->skb;
2d0bb1c1 1304 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1305
1306 /* in the packet split case this is header only */
1307 prefetch(skb->data - NET_IP_ALIGN);
1308
1309 i++;
1310 if (i == rx_ring->count)
1311 i = 0;
1312 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1313 prefetch(next_rxd);
1314
1315 next_buffer = &rx_ring->buffer_info[i];
1316
3db1cd5c 1317 cleaned = true;
bc7f75fa 1318 cleaned_count++;
0be3f55f 1319 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1320 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1321 buffer_info->dma = 0;
1322
af667a29 1323 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1324 if (!(staterr & E1000_RXD_STAT_EOP))
1325 adapter->flags2 |= FLAG2_IS_DISCARDING;
1326
1327 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1328 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1329 dev_kfree_skb_irq(skb);
b94b5028
JB		 1330 if (staterr & E1000_RXD_STAT_EOP)
1331 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1332 goto next_desc;
1333 }
1334
cf955e6c
BG		 1335 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1336 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1337 dev_kfree_skb_irq(skb);
1338 goto next_desc;
1339 }
1340
1341 length = le16_to_cpu(rx_desc->wb.middle.length0);
1342
1343 if (!length) {
ef456f85 1344 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1345 dev_kfree_skb_irq(skb);
1346 goto next_desc;
1347 }
1348
1349 /* Good Receive */
1350 skb_put(skb, length);
1351
1352 {
e921eb1a 1353 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1354 * it more efficient than reusing j
1355 */
1356 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1357
e921eb1a 1358 /* page alloc/put takes too long and effects small
0e15df49
BA		 1359 * packet throughput, so unsplit small packets and
1360 * save the alloc/put only valid in softirq (napi)
1361 * context to call kmap_*
ad68076e 1362 */
0e15df49
BA		 1363 if (l1 && (l1 <= copybreak) &&
1364 ((length + l1) <= adapter->rx_ps_bsize0)) {
1365 u8 *vaddr;
1366
1367 ps_page = &buffer_info->ps_pages[0];
1368
e921eb1a 1369 /* there is no documentation about how to call
0e15df49
BA		 1370 * kmap_atomic, so we can't hold the mapping
1371 * very long
1372 */
1373 dma_sync_single_for_cpu(&pdev->dev,
1374 ps_page->dma,
1375 PAGE_SIZE,
1376 DMA_FROM_DEVICE);
9f393834 1377 vaddr = kmap_atomic(ps_page->page);
0e15df49 1378 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1379 kunmap_atomic(vaddr);
0e15df49
BA		 1380 dma_sync_single_for_device(&pdev->dev,
1381 ps_page->dma,
1382 PAGE_SIZE,
1383 DMA_FROM_DEVICE);
1384
1385 /* remove the CRC */
0184039a
BG		 1386 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1387 if (!(netdev->features & NETIF_F_RXFCS))
1388 l1 -= 4;
1389 }
0e15df49
BA		 1390
1391 skb_put(skb, l1);
1392 goto copydone;
e80bd1d1 1393 } /* if */
bc7f75fa
AK		 1394 }
1395
1396 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1397 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1398 if (!length)
1399 break;
1400
47f44e40 1401 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1402 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1403 DMA_FROM_DEVICE);
bc7f75fa
AK		 1404 ps_page->dma = 0;
1405 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1406 ps_page->page = NULL;
1407 skb->len += length;
1408 skb->data_len += length;
98a045d7 1409 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1410 }
1411
eb7c3adb
JK		 1412 /* strip the ethernet crc, problem is we're using pages now so
1413 * this whole operation can get a little cpu intensive
1414 */
0184039a
BG		 1415 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1416 if (!(netdev->features & NETIF_F_RXFCS))
1417 pskb_trim(skb, skb->len - 4);
1418 }
eb7c3adb 1419
bc7f75fa
AK		 1420copydone:
1421 total_rx_bytes += skb->len;
1422 total_rx_packets++;
1423
2e1706f2 1424 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1425
70495a50
BA		 1426 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1427
bc7f75fa 1428 if (rx_desc->wb.upper.header_status &
17e813ec 1429 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1430 adapter->rx_hdr_split++;
1431
b67e1913
BA		 1432 e1000_receive_skb(adapter, netdev, skb, staterr,
1433 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1434
1435next_desc:
1436 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1437 buffer_info->skb = NULL;
1438
1439 /* return some buffers to hardware, one at a time is too slow */
1440 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1441 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1442 GFP_ATOMIC);
bc7f75fa
AK		 1443 cleaned_count = 0;
1444 }
1445
1446 /* use prefetched values */
1447 rx_desc = next_rxd;
1448 buffer_info = next_buffer;
1449
1450 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1451 }
1452 rx_ring->next_to_clean = i;
1453
1454 cleaned_count = e1000_desc_unused(rx_ring);
1455 if (cleaned_count)
55aa6985 1456 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1457
bc7f75fa 1458 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1459 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1460 return cleaned;
1461}
1462
97ac8cae
BA		 1463/**
1464 * e1000_consume_page - helper function
1465 **/
1466static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1467 u16 length)
97ac8cae
BA		 1468{
1469 bi->page = NULL;
1470 skb->len += length;
1471 skb->data_len += length;
98a045d7 1472 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1473}
1474
1475/**
1476 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1477 * @adapter: board private structure
1478 *
1479 * the return value indicates whether actual cleaning was done, there
1480 * is no guarantee that everything was cleaned
1481 **/
55aa6985
BA		 1482static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1483 int work_to_do)
97ac8cae 1484{
55aa6985 1485 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1486 struct net_device *netdev = adapter->netdev;
1487 struct pci_dev *pdev = adapter->pdev;
5f450212 1488 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1489 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1490 u32 length, staterr;
97ac8cae
BA		 1491 unsigned int i;
1492 int cleaned_count = 0;
1493 bool cleaned = false;
362e20ca 1494 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1495 struct skb_shared_info *shinfo;
97ac8cae
BA		 1496
1497 i = rx_ring->next_to_clean;
5f450212
BA		 1498 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1499 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1500 buffer_info = &rx_ring->buffer_info[i];
1501
5f450212 1502 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1503 struct sk_buff *skb;
97ac8cae
BA		 1504
1505 if (*work_done >= work_to_do)
1506 break;
1507 (*work_done)++;
2d0bb1c1 1508 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1509
97ac8cae
BA		 1510 skb = buffer_info->skb;
1511 buffer_info->skb = NULL;
1512
1513 ++i;
1514 if (i == rx_ring->count)
1515 i = 0;
5f450212 1516 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1517 prefetch(next_rxd);
1518
1519 next_buffer = &rx_ring->buffer_info[i];
1520
1521 cleaned = true;
1522 cleaned_count++;
0be3f55f
NN		 1523 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1524 DMA_FROM_DEVICE);
97ac8cae
BA		 1525 buffer_info->dma = 0;
1526
5f450212 1527 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1528
1529 /* errors is only valid for DD + EOP descriptors */
5f450212 1530 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1531 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1532 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1533 /* recycle both page and skb */
1534 buffer_info->skb = skb;
1535 /* an error means any chain goes out the window too */
1536 if (rx_ring->rx_skb_top)
1537 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1538 rx_ring->rx_skb_top = NULL;
1539 goto next_desc;
97ac8cae 1540 }
f0f1a172 1541#define rxtop (rx_ring->rx_skb_top)
5f450212 1542 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1543 /* this descriptor is only the beginning (or middle) */
1544 if (!rxtop) {
1545 /* this is the beginning of a chain */
1546 rxtop = skb;
1547 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1548 0, length);
97ac8cae
BA		 1549 } else {
1550 /* this is the middle of a chain */
17e813ec
BA		 1551 shinfo = skb_shinfo(rxtop);
1552 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1553 buffer_info->page, 0,
1554 length);
97ac8cae
BA		 1555 /* re-use the skb, only consumed the page */
1556 buffer_info->skb = skb;
1557 }
1558 e1000_consume_page(buffer_info, rxtop, length);
1559 goto next_desc;
1560 } else {
1561 if (rxtop) {
1562 /* end of the chain */
17e813ec
BA		 1563 shinfo = skb_shinfo(rxtop);
1564 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1565 buffer_info->page, 0,
1566 length);
97ac8cae 1567 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1568 * page
1569 */
97ac8cae
BA		 1570 buffer_info->skb = skb;
1571 skb = rxtop;
1572 rxtop = NULL;
1573 e1000_consume_page(buffer_info, skb, length);
1574 } else {
1575 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1576 * copybreak to save the put_page/alloc_page
1577 */
97ac8cae
BA		 1578 if (length <= copybreak &&
1579 skb_tailroom(skb) >= length) {
1580 u8 *vaddr;
4679026d 1581 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1582 memcpy(skb_tail_pointer(skb), vaddr,
1583 length);
4679026d 1584 kunmap_atomic(vaddr);
97ac8cae 1585 /* re-use the page, so don't erase
e921eb1a
BA		 1586 * buffer_info->page
1587 */
97ac8cae
BA		 1588 skb_put(skb, length);
1589 } else {
1590 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1591 buffer_info->page, 0,
1592 length);
97ac8cae 1593 e1000_consume_page(buffer_info, skb,
f0ff4398 1594 length);
97ac8cae
BA		 1595 }
1596 }
1597 }
1598
2e1706f2
BA		 1599 /* Receive Checksum Offload */
1600 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1601
70495a50
BA		 1602 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1603
97ac8cae
BA		 1604 /* probably a little skewed due to removing CRC */
1605 total_rx_bytes += skb->len;
1606 total_rx_packets++;
1607
1608 /* eth type trans needs skb->data to point to something */
1609 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1610 e_err("pskb_may_pull failed.\n");
ef5ab89c 1611 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1612 goto next_desc;
1613 }
1614
5f450212
BA		 1615 e1000_receive_skb(adapter, netdev, skb, staterr,
1616 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1617
1618next_desc:
5f450212 1619 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1620
1621 /* return some buffers to hardware, one at a time is too slow */
1622 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1623 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1624 GFP_ATOMIC);
97ac8cae
BA		 1625 cleaned_count = 0;
1626 }
1627
1628 /* use prefetched values */
1629 rx_desc = next_rxd;
1630 buffer_info = next_buffer;
5f450212
BA		 1631
1632 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1633 }
1634 rx_ring->next_to_clean = i;
1635
1636 cleaned_count = e1000_desc_unused(rx_ring);
1637 if (cleaned_count)
55aa6985 1638 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1639
1640 adapter->total_rx_bytes += total_rx_bytes;
1641 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1642 return cleaned;
1643}
1644
bc7f75fa
AK		 1645/**
1646 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1647 * @rx_ring: Rx descriptor ring
bc7f75fa 1648 **/
55aa6985 1649static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1650{
55aa6985 1651 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1652 struct e1000_buffer *buffer_info;
1653 struct e1000_ps_page *ps_page;
1654 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1655 unsigned int i, j;
1656
1657 /* Free all the Rx ring sk_buffs */
1658 for (i = 0; i < rx_ring->count; i++) {
1659 buffer_info = &rx_ring->buffer_info[i];
1660 if (buffer_info->dma) {
1661 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1662 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1663 adapter->rx_buffer_len,
0be3f55f 1664 DMA_FROM_DEVICE);
97ac8cae 1665 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1666 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1667 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1668 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1669 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1670 adapter->rx_ps_bsize0,
0be3f55f 1671 DMA_FROM_DEVICE);
bc7f75fa
AK		 1672 buffer_info->dma = 0;
1673 }
1674
97ac8cae
BA		 1675 if (buffer_info->page) {
1676 put_page(buffer_info->page);
1677 buffer_info->page = NULL;
1678 }
1679
bc7f75fa
AK		 1680 if (buffer_info->skb) {
1681 dev_kfree_skb(buffer_info->skb);
1682 buffer_info->skb = NULL;
1683 }
1684
1685 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1686 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1687 if (!ps_page->page)
1688 break;
0be3f55f
NN		 1689 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1690 DMA_FROM_DEVICE);
bc7f75fa
AK		 1691 ps_page->dma = 0;
1692 put_page(ps_page->page);
1693 ps_page->page = NULL;
1694 }
1695 }
1696
1697 /* there also may be some cached data from a chained receive */
1698 if (rx_ring->rx_skb_top) {
1699 dev_kfree_skb(rx_ring->rx_skb_top);
1700 rx_ring->rx_skb_top = NULL;
1701 }
1702
bc7f75fa
AK		 1703 /* Zero out the descriptor ring */
1704 memset(rx_ring->desc, 0, rx_ring->size);
1705
1706 rx_ring->next_to_clean = 0;
1707 rx_ring->next_to_use = 0;
b94b5028 1708 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1709
c5083cf6 1710 writel(0, rx_ring->head);
b485dbae 1711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 1712 e1000e_update_rdt_wa(rx_ring, 0);
1713 else
1714 writel(0, rx_ring->tail);
bc7f75fa
AK		 1715}
1716
a8f88ff5
JB		 1717static void e1000e_downshift_workaround(struct work_struct *work)
1718{
1719 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1720 struct e1000_adapter,
1721 downshift_task);
a8f88ff5 1722
615b32af
JB		 1723 if (test_bit(__E1000_DOWN, &adapter->state))
1724 return;
1725
a8f88ff5
JB		 1726 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1727}
1728
bc7f75fa
AK		 1729/**
1730 * e1000_intr_msi - Interrupt Handler
1731 * @irq: interrupt number
1732 * @data: pointer to a network interface device structure
1733 **/
8bb62869 1734static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1735{
1736 struct net_device *netdev = data;
1737 struct e1000_adapter *adapter = netdev_priv(netdev);
1738 struct e1000_hw *hw = &adapter->hw;
1739 u32 icr = er32(ICR);
1740
e921eb1a 1741 /* read ICR disables interrupts using IAM */
573cca8c 1742 if (icr & E1000_ICR_LSC) {
f92518dd 1743 hw->mac.get_link_status = true;
e921eb1a 1744 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1745 * disconnect (LSC) before accessing any PHY registers
1746 */
bc7f75fa
AK		 1747 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1748 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1749 schedule_work(&adapter->downshift_task);
bc7f75fa 1750
e921eb1a 1751 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1752 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1753 * adapter in watchdog
1754 */
bc7f75fa
AK		 1755 if (netif_carrier_ok(netdev) &&
1756 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1757 /* disable receives */
1758 u32 rctl = er32(RCTL);
6cf08d1c 1759
bc7f75fa 1760 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1761 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1762 }
1763 /* guard against interrupt when we're going down */
1764 if (!test_bit(__E1000_DOWN, &adapter->state))
1765 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1766 }
1767
94fb848b
BA		 1768 /* Reset on uncorrectable ECC error */
1769 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1770 u32 pbeccsts = er32(PBECCSTS);
1771
1772 adapter->corr_errors +=
1773 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1774 adapter->uncorr_errors +=
1775 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1776 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1777
1778 /* Do the reset outside of interrupt context */
1779 schedule_work(&adapter->reset_task);
1780
1781 /* return immediately since reset is imminent */
1782 return IRQ_HANDLED;
1783 }
1784
288379f0 1785 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1786 adapter->total_tx_bytes = 0;
1787 adapter->total_tx_packets = 0;
1788 adapter->total_rx_bytes = 0;
1789 adapter->total_rx_packets = 0;
288379f0 1790 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1791 }
1792
1793 return IRQ_HANDLED;
1794}
1795
1796/**
1797 * e1000_intr - Interrupt Handler
1798 * @irq: interrupt number
1799 * @data: pointer to a network interface device structure
1800 **/
8bb62869 1801static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1802{
1803 struct net_device *netdev = data;
1804 struct e1000_adapter *adapter = netdev_priv(netdev);
1805 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1806 u32 rctl, icr = er32(ICR);
4662e82b 1807
a68ea775 1808 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1809 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1810
e921eb1a 1811 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1812 * not set, then the adapter didn't send an interrupt
1813 */
bc7f75fa
AK		 1814 if (!(icr & E1000_ICR_INT_ASSERTED))
1815 return IRQ_NONE;
1816
e921eb1a 1817 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1818 * interrupts are masked. No need for the
1819 * IMC write
1820 */
bc7f75fa 1821
573cca8c 1822 if (icr & E1000_ICR_LSC) {
f92518dd 1823 hw->mac.get_link_status = true;
e921eb1a 1824 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1825 * disconnect (LSC) before accessing any PHY registers
1826 */
bc7f75fa
AK		 1827 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1828 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1829 schedule_work(&adapter->downshift_task);
bc7f75fa 1830
e921eb1a 1831 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1832 * For packet buffer work-around on link down event;
1833 * disable receives here in the ISR and
1834 * reset adapter in watchdog
1835 */
1836 if (netif_carrier_ok(netdev) &&
1837 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1838 /* disable receives */
1839 rctl = er32(RCTL);
1840 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1841 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1842 }
1843 /* guard against interrupt when we're going down */
1844 if (!test_bit(__E1000_DOWN, &adapter->state))
1845 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1846 }
1847
94fb848b
BA		 1848 /* Reset on uncorrectable ECC error */
1849 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1850 u32 pbeccsts = er32(PBECCSTS);
1851
1852 adapter->corr_errors +=
1853 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1854 adapter->uncorr_errors +=
1855 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1856 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1857
1858 /* Do the reset outside of interrupt context */
1859 schedule_work(&adapter->reset_task);
1860
1861 /* return immediately since reset is imminent */
1862 return IRQ_HANDLED;
1863 }
1864
288379f0 1865 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1866 adapter->total_tx_bytes = 0;
1867 adapter->total_tx_packets = 0;
1868 adapter->total_rx_bytes = 0;
1869 adapter->total_rx_packets = 0;
288379f0 1870 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1871 }
1872
1873 return IRQ_HANDLED;
1874}
1875
8bb62869 1876static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1877{
1878 struct net_device *netdev = data;
1879 struct e1000_adapter *adapter = netdev_priv(netdev);
1880 struct e1000_hw *hw = &adapter->hw;
1881 u32 icr = er32(ICR);
1882
1883 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1884 if (!test_bit(__E1000_DOWN, &adapter->state))
1885 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1886 return IRQ_NONE;
1887 }
1888
1889 if (icr & adapter->eiac_mask)
1890 ew32(ICS, (icr & adapter->eiac_mask));
1891
1892 if (icr & E1000_ICR_OTHER) {
1893 if (!(icr & E1000_ICR_LSC))
1894 goto no_link_interrupt;
f92518dd 1895 hw->mac.get_link_status = true;
4662e82b
BA		 1896 /* guard against interrupt when we're going down */
1897 if (!test_bit(__E1000_DOWN, &adapter->state))
1898 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1899 }
1900
1901no_link_interrupt:
a3c69fef
JB		 1902 if (!test_bit(__E1000_DOWN, &adapter->state))
1903 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1904
1905 return IRQ_HANDLED;
1906}
1907
8bb62869 1908static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1909{
1910 struct net_device *netdev = data;
1911 struct e1000_adapter *adapter = netdev_priv(netdev);
1912 struct e1000_hw *hw = &adapter->hw;
1913 struct e1000_ring *tx_ring = adapter->tx_ring;
1914
4662e82b
BA		 1915 adapter->total_tx_bytes = 0;
1916 adapter->total_tx_packets = 0;
1917
55aa6985 1918 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1919 /* Ring was not completely cleaned, so fire another interrupt */
1920 ew32(ICS, tx_ring->ims_val);
1921
1922 return IRQ_HANDLED;
1923}
1924
8bb62869 1925static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1926{
1927 struct net_device *netdev = data;
1928 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1929 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1930
1931 /* Write the ITR value calculated at the end of the
1932 * previous interrupt.
1933 */
55aa6985
BA		 1934 if (rx_ring->set_itr) {
1935 writel(1000000000 / (rx_ring->itr_val * 256),
1936 rx_ring->itr_register);
1937 rx_ring->set_itr = 0;
4662e82b
BA		 1938 }
1939
288379f0 1940 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1941 adapter->total_rx_bytes = 0;
1942 adapter->total_rx_packets = 0;
288379f0 1943 __napi_schedule(&adapter->napi);
4662e82b
BA		 1944 }
1945 return IRQ_HANDLED;
1946}
1947
1948/**
1949 * e1000_configure_msix - Configure MSI-X hardware
1950 *
1951 * e1000_configure_msix sets up the hardware to properly
1952 * generate MSI-X interrupts.
1953 **/
1954static void e1000_configure_msix(struct e1000_adapter *adapter)
1955{
1956 struct e1000_hw *hw = &adapter->hw;
1957 struct e1000_ring *rx_ring = adapter->rx_ring;
1958 struct e1000_ring *tx_ring = adapter->tx_ring;
1959 int vector = 0;
1960 u32 ctrl_ext, ivar = 0;
1961
1962 adapter->eiac_mask = 0;
1963
1964 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1965 if (hw->mac.type == e1000_82574) {
1966 u32 rfctl = er32(RFCTL);
6cf08d1c 1967
4662e82b
BA		 1968 rfctl |= E1000_RFCTL_ACK_DIS;
1969 ew32(RFCTL, rfctl);
1970 }
1971
4662e82b
BA		 1972 /* Configure Rx vector */
1973 rx_ring->ims_val = E1000_IMS_RXQ0;
1974 adapter->eiac_mask |= rx_ring->ims_val;
1975 if (rx_ring->itr_val)
1976 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1977 rx_ring->itr_register);
4662e82b 1978 else
c5083cf6 1979 writel(1, rx_ring->itr_register);
4662e82b
BA		 1980 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1981
1982 /* Configure Tx vector */
1983 tx_ring->ims_val = E1000_IMS_TXQ0;
1984 vector++;
1985 if (tx_ring->itr_val)
1986 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1987 tx_ring->itr_register);
4662e82b 1988 else
c5083cf6 1989 writel(1, tx_ring->itr_register);
4662e82b
BA		 1990 adapter->eiac_mask |= tx_ring->ims_val;
1991 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1992
1993 /* set vector for Other Causes, e.g. link changes */
1994 vector++;
1995 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1996 if (rx_ring->itr_val)
1997 writel(1000000000 / (rx_ring->itr_val * 256),
1998 hw->hw_addr + E1000_EITR_82574(vector));
1999 else
2000 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2001
2002 /* Cause Tx interrupts on every write back */
2003 ivar |= (1 << 31);
2004
2005 ew32(IVAR, ivar);
2006
2007 /* enable MSI-X PBA support */
2008 ctrl_ext = er32(CTRL_EXT);
2009 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2010
2011 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2012 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2013 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2014 ew32(CTRL_EXT, ctrl_ext);
2015 e1e_flush();
2016}
2017
2018void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2019{
2020 if (adapter->msix_entries) {
2021 pci_disable_msix(adapter->pdev);
2022 kfree(adapter->msix_entries);
2023 adapter->msix_entries = NULL;
2024 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2025 pci_disable_msi(adapter->pdev);
2026 adapter->flags &= ~FLAG_MSI_ENABLED;
2027 }
4662e82b
BA		 2028}
2029
2030/**
2031 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2032 *
2033 * Attempt to configure interrupts using the best available
2034 * capabilities of the hardware and kernel.
2035 **/
2036void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2037{
2038 int err;
8e86acd7 2039 int i;
4662e82b
BA		 2040
2041 switch (adapter->int_mode) {
2042 case E1000E_INT_MODE_MSIX:
2043 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2044 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2045 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2046 sizeof(struct
2047 msix_entry),
2048 GFP_KERNEL);
4662e82b 2049 if (adapter->msix_entries) {
0cc7c959
AG		 2050 struct e1000_adapter *a = adapter;
2051
8e86acd7 2052 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2053 adapter->msix_entries[i].entry = i;
2054
0cc7c959
AG		 2055 err = pci_enable_msix_range(a->pdev,
2056 a->msix_entries,
2057 a->num_vectors,
2058 a->num_vectors);
2059 if (err > 0)
4662e82b
BA		 2060 return;
2061 }
2062 /* MSI-X failed, so fall through and try MSI */
ef456f85 2063 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2064 e1000e_reset_interrupt_capability(adapter);
2065 }
2066 adapter->int_mode = E1000E_INT_MODE_MSI;
2067 /* Fall through */
2068 case E1000E_INT_MODE_MSI:
2069 if (!pci_enable_msi(adapter->pdev)) {
2070 adapter->flags |= FLAG_MSI_ENABLED;
2071 } else {
2072 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2073 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2074 }
2075 /* Fall through */
2076 case E1000E_INT_MODE_LEGACY:
2077 /* Don't do anything; this is the system default */
2078 break;
2079 }
8e86acd7
JK		 2080
2081 /* store the number of vectors being used */
2082 adapter->num_vectors = 1;
4662e82b
BA		 2083}
2084
2085/**
2086 * e1000_request_msix - Initialize MSI-X interrupts
2087 *
2088 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2089 * kernel.
2090 **/
2091static int e1000_request_msix(struct e1000_adapter *adapter)
2092{
2093 struct net_device *netdev = adapter->netdev;
2094 int err = 0, vector = 0;
2095
2096 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2097 snprintf(adapter->rx_ring->name,
2098 sizeof(adapter->rx_ring->name) - 1,
2099 "%s-rx-0", netdev->name);
4662e82b
BA		 2100 else
2101 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2102 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2103 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2104 netdev);
2105 if (err)
5015e53a 2106 return err;
c5083cf6
BA		 2107 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2108 E1000_EITR_82574(vector);
4662e82b
BA		 2109 adapter->rx_ring->itr_val = adapter->itr;
2110 vector++;
2111
2112 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2113 snprintf(adapter->tx_ring->name,
2114 sizeof(adapter->tx_ring->name) - 1,
2115 "%s-tx-0", netdev->name);
4662e82b
BA		 2116 else
2117 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2118 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2119 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2120 netdev);
2121 if (err)
5015e53a 2122 return err;
c5083cf6
BA		 2123 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2124 E1000_EITR_82574(vector);
4662e82b
BA		 2125 adapter->tx_ring->itr_val = adapter->itr;
2126 vector++;
2127
2128 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2129 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2130 if (err)
5015e53a 2131 return err;
4662e82b
BA		 2132
2133 e1000_configure_msix(adapter);
5015e53a 2134
4662e82b 2135 return 0;
4662e82b
BA		 2136}
2137
f8d59f78
BA		 2138/**
2139 * e1000_request_irq - initialize interrupts
2140 *
2141 * Attempts to configure interrupts using the best available
2142 * capabilities of the hardware and kernel.
2143 **/
bc7f75fa
AK		 2144static int e1000_request_irq(struct e1000_adapter *adapter)
2145{
2146 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2147 int err;
2148
4662e82b
BA		 2149 if (adapter->msix_entries) {
2150 err = e1000_request_msix(adapter);
2151 if (!err)
2152 return err;
2153 /* fall back to MSI */
2154 e1000e_reset_interrupt_capability(adapter);
2155 adapter->int_mode = E1000E_INT_MODE_MSI;
2156 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2157 }
4662e82b 2158 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2159 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2160 netdev->name, netdev);
2161 if (!err)
2162 return err;
bc7f75fa 2163
4662e82b
BA		 2164 /* fall back to legacy interrupt */
2165 e1000e_reset_interrupt_capability(adapter);
2166 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2167 }
2168
a0607fd3 2169 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2170 netdev->name, netdev);
2171 if (err)
2172 e_err("Unable to allocate interrupt, Error: %d\n", err);
2173
bc7f75fa
AK		 2174 return err;
2175}
2176
2177static void e1000_free_irq(struct e1000_adapter *adapter)
2178{
2179 struct net_device *netdev = adapter->netdev;
2180
4662e82b
BA		 2181 if (adapter->msix_entries) {
2182 int vector = 0;
2183
2184 free_irq(adapter->msix_entries[vector].vector, netdev);
2185 vector++;
2186
2187 free_irq(adapter->msix_entries[vector].vector, netdev);
2188 vector++;
2189
2190 /* Other Causes interrupt vector */
2191 free_irq(adapter->msix_entries[vector].vector, netdev);
2192 return;
bc7f75fa 2193 }
4662e82b
BA		 2194
2195 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2196}
2197
2198/**
2199 * e1000_irq_disable - Mask off interrupt generation on the NIC
2200 **/
2201static void e1000_irq_disable(struct e1000_adapter *adapter)
2202{
2203 struct e1000_hw *hw = &adapter->hw;
2204
bc7f75fa 2205 ew32(IMC, ~0);
4662e82b
BA		 2206 if (adapter->msix_entries)
2207 ew32(EIAC_82574, 0);
bc7f75fa 2208 e1e_flush();
8e86acd7
JK		 2209
2210 if (adapter->msix_entries) {
2211 int i;
6cf08d1c 2212
8e86acd7
JK		 2213 for (i = 0; i < adapter->num_vectors; i++)
2214 synchronize_irq(adapter->msix_entries[i].vector);
2215 } else {
2216 synchronize_irq(adapter->pdev->irq);
2217 }
bc7f75fa
AK		 2218}
2219
2220/**
2221 * e1000_irq_enable - Enable default interrupt generation settings
2222 **/
2223static void e1000_irq_enable(struct e1000_adapter *adapter)
2224{
2225 struct e1000_hw *hw = &adapter->hw;
2226
4662e82b
BA		 2227 if (adapter->msix_entries) {
2228 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2229 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2230 } else if (hw->mac.type == e1000_pch_lpt) {
2231 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2232 } else {
2233 ew32(IMS, IMS_ENABLE_MASK);
2234 }
74ef9c39 2235 e1e_flush();
bc7f75fa
AK		 2236}
2237
2238/**
31dbe5b4 2239 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2240 * @adapter: address of board private structure
2241 *
31dbe5b4 2242 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2243 * For ASF and Pass Through versions of f/w this means that
2244 * the driver is loaded. For AMT version (only with 82573)
2245 * of the f/w this means that the network i/f is open.
2246 **/
31dbe5b4 2247void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2248{
2249 struct e1000_hw *hw = &adapter->hw;
2250 u32 ctrl_ext;
2251 u32 swsm;
2252
2253 /* Let firmware know the driver has taken over */
2254 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2255 swsm = er32(SWSM);
2256 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2257 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2258 ctrl_ext = er32(CTRL_EXT);
ad68076e 2259 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2260 }
2261}
2262
2263/**
31dbe5b4 2264 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2265 * @adapter: address of board private structure
2266 *
31dbe5b4 2267 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2268 * For ASF and Pass Through versions of f/w this means that the
2269 * driver is no longer loaded. For AMT version (only with 82573) i
2270 * of the f/w this means that the network i/f is closed.
2271 *
2272 **/
31dbe5b4 2273void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2274{
2275 struct e1000_hw *hw = &adapter->hw;
2276 u32 ctrl_ext;
2277 u32 swsm;
2278
2279 /* Let firmware taken over control of h/w */
2280 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2281 swsm = er32(SWSM);
2282 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2283 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2284 ctrl_ext = er32(CTRL_EXT);
ad68076e 2285 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2286 }
2287}
2288
bc7f75fa 2289/**
49ce9c2c 2290 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2291 **/
2292static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2293 struct e1000_ring *ring)
2294{
2295 struct pci_dev *pdev = adapter->pdev;
2296
2297 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2298 GFP_KERNEL);
2299 if (!ring->desc)
2300 return -ENOMEM;
2301
2302 return 0;
2303}
2304
2305/**
2306 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2307 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2308 *
2309 * Return 0 on success, negative on failure
2310 **/
55aa6985 2311int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2312{
55aa6985 2313 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2314 int err = -ENOMEM, size;
2315
2316 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2317 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2318 if (!tx_ring->buffer_info)
2319 goto err;
bc7f75fa
AK		 2320
2321 /* round up to nearest 4K */
2322 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2323 tx_ring->size = ALIGN(tx_ring->size, 4096);
2324
2325 err = e1000_alloc_ring_dma(adapter, tx_ring);
2326 if (err)
2327 goto err;
2328
2329 tx_ring->next_to_use = 0;
2330 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2331
2332 return 0;
2333err:
2334 vfree(tx_ring->buffer_info);
44defeb3 2335 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2336 return err;
2337}
2338
2339/**
2340 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2341 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2342 *
2343 * Returns 0 on success, negative on failure
2344 **/
55aa6985 2345int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2346{
55aa6985 2347 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2348 struct e1000_buffer *buffer_info;
2349 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2350
2351 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2352 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2353 if (!rx_ring->buffer_info)
2354 goto err;
bc7f75fa 2355
47f44e40
AK		 2356 for (i = 0; i < rx_ring->count; i++) {
2357 buffer_info = &rx_ring->buffer_info[i];
2358 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2359 sizeof(struct e1000_ps_page),
2360 GFP_KERNEL);
2361 if (!buffer_info->ps_pages)
2362 goto err_pages;
2363 }
bc7f75fa
AK		 2364
2365 desc_len = sizeof(union e1000_rx_desc_packet_split);
2366
2367 /* Round up to nearest 4K */
2368 rx_ring->size = rx_ring->count * desc_len;
2369 rx_ring->size = ALIGN(rx_ring->size, 4096);
2370
2371 err = e1000_alloc_ring_dma(adapter, rx_ring);
2372 if (err)
47f44e40 2373 goto err_pages;
bc7f75fa
AK		 2374
2375 rx_ring->next_to_clean = 0;
2376 rx_ring->next_to_use = 0;
2377 rx_ring->rx_skb_top = NULL;
2378
2379 return 0;
47f44e40
AK		 2380
2381err_pages:
2382 for (i = 0; i < rx_ring->count; i++) {
2383 buffer_info = &rx_ring->buffer_info[i];
2384 kfree(buffer_info->ps_pages);
2385 }
bc7f75fa
AK		 2386err:
2387 vfree(rx_ring->buffer_info);
e9262447 2388 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2389 return err;
2390}
2391
2392/**
2393 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2394 * @tx_ring: Tx descriptor ring
bc7f75fa 2395 **/
55aa6985 2396static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2397{
55aa6985 2398 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2399 struct e1000_buffer *buffer_info;
2400 unsigned long size;
2401 unsigned int i;
2402
2403 for (i = 0; i < tx_ring->count; i++) {
2404 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2405 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2406 }
2407
3f0cfa3b 2408 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2409 size = sizeof(struct e1000_buffer) * tx_ring->count;
2410 memset(tx_ring->buffer_info, 0, size);
2411
2412 memset(tx_ring->desc, 0, tx_ring->size);
2413
2414 tx_ring->next_to_use = 0;
2415 tx_ring->next_to_clean = 0;
2416
c5083cf6 2417 writel(0, tx_ring->head);
b485dbae 2418 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 2419 e1000e_update_tdt_wa(tx_ring, 0);
2420 else
2421 writel(0, tx_ring->tail);
bc7f75fa
AK		 2422}
2423
2424/**
2425 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2426 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2427 *
2428 * Free all transmit software resources
2429 **/
55aa6985 2430void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2431{
55aa6985 2432 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2433 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2434
55aa6985 2435 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2436
2437 vfree(tx_ring->buffer_info);
2438 tx_ring->buffer_info = NULL;
2439
2440 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2441 tx_ring->dma);
2442 tx_ring->desc = NULL;
2443}
2444
2445/**
2446 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2447 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2448 *
2449 * Free all receive software resources
2450 **/
55aa6985 2451void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2452{
55aa6985 2453 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2454 struct pci_dev *pdev = adapter->pdev;
47f44e40 2455 int i;
bc7f75fa 2456
55aa6985 2457 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2458
b1cdfead 2459 for (i = 0; i < rx_ring->count; i++)
47f44e40 2460 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2461
bc7f75fa
AK		 2462 vfree(rx_ring->buffer_info);
2463 rx_ring->buffer_info = NULL;
2464
bc7f75fa
AK		 2465 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2466 rx_ring->dma);
2467 rx_ring->desc = NULL;
2468}
2469
2470/**
2471 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2472 * @adapter: pointer to adapter
2473 * @itr_setting: current adapter->itr
2474 * @packets: the number of packets during this measurement interval
2475 * @bytes: the number of bytes during this measurement interval
2476 *
bc7f75fa
AK		 2477 * Stores a new ITR value based on packets and byte
2478 * counts during the last interrupt. The advantage of per interrupt
2479 * computation is faster updates and more accurate ITR for the current
2480 * traffic pattern. Constants in this function were computed
2481 * based on theoretical maximum wire speed and thresholds were set based
2482 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2483 * while increasing bulk throughput. This functionality is controlled
2484 * by the InterruptThrottleRate module parameter.
bc7f75fa 2485 **/
8bb62869 2486static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2487{
2488 unsigned int retval = itr_setting;
2489
2490 if (packets == 0)
5015e53a 2491 return itr_setting;
bc7f75fa
AK		 2492
2493 switch (itr_setting) {
2494 case lowest_latency:
2495 /* handle TSO and jumbo frames */
362e20ca 2496 if (bytes / packets > 8000)
bc7f75fa 2497 retval = bulk_latency;
b1cdfead 2498 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2499 retval = low_latency;
bc7f75fa 2500 break;
e80bd1d1 2501 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2502 if (bytes > 10000) {
2503 /* this if handles the TSO accounting */
362e20ca 2504 if (bytes / packets > 8000)
bc7f75fa 2505 retval = bulk_latency;
362e20ca 2506 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2507 retval = bulk_latency;
b1cdfead 2508 else if ((packets > 35))
bc7f75fa 2509 retval = lowest_latency;
362e20ca 2510 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2511 retval = bulk_latency;
2512 } else if (packets <= 2 && bytes < 512) {
2513 retval = lowest_latency;
2514 }
2515 break;
e80bd1d1 2516 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2517 if (bytes > 25000) {
b1cdfead 2518 if (packets > 35)
bc7f75fa 2519 retval = low_latency;
bc7f75fa
AK		 2520 } else if (bytes < 6000) {
2521 retval = low_latency;
2522 }
2523 break;
2524 }
2525
bc7f75fa
AK		 2526 return retval;
2527}
2528
2529static void e1000_set_itr(struct e1000_adapter *adapter)
2530{
bc7f75fa
AK		 2531 u16 current_itr;
2532 u32 new_itr = adapter->itr;
2533
2534 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2535 if (adapter->link_speed != SPEED_1000) {
2536 current_itr = 0;
2537 new_itr = 4000;
2538 goto set_itr_now;
2539 }
2540
828bac87
BA		 2541 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2542 new_itr = 0;
2543 goto set_itr_now;
2544 }
2545
8bb62869
BA		 2546 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2547 adapter->total_tx_packets,
2548 adapter->total_tx_bytes);
bc7f75fa
AK		 2549 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2550 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2551 adapter->tx_itr = low_latency;
2552
8bb62869
BA		 2553 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2554 adapter->total_rx_packets,
2555 adapter->total_rx_bytes);
bc7f75fa
AK		 2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2558 adapter->rx_itr = low_latency;
2559
2560 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2561
bc7f75fa 2562 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2563 switch (current_itr) {
bc7f75fa
AK		 2564 case lowest_latency:
2565 new_itr = 70000;
2566 break;
2567 case low_latency:
e80bd1d1 2568 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2569 break;
2570 case bulk_latency:
2571 new_itr = 4000;
2572 break;
2573 default:
2574 break;
2575 }
2576
2577set_itr_now:
2578 if (new_itr != adapter->itr) {
e921eb1a 2579 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2580 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2581 * increasing
2582 */
bc7f75fa 2583 new_itr = new_itr > adapter->itr ?
f0ff4398 2584 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2585 adapter->itr = new_itr;
4662e82b
BA		 2586 adapter->rx_ring->itr_val = new_itr;
2587 if (adapter->msix_entries)
2588 adapter->rx_ring->set_itr = 1;
2589 else
e3d14b08 2590 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2591 }
2592}
2593
22a4cca2
MV		 2594/**
2595 * e1000e_write_itr - write the ITR value to the appropriate registers
2596 * @adapter: address of board private structure
2597 * @itr: new ITR value to program
2598 *
2599 * e1000e_write_itr determines if the adapter is in MSI-X mode
2600 * and, if so, writes the EITR registers with the ITR value.
2601 * Otherwise, it writes the ITR value into the ITR register.
2602 **/
2603void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2604{
2605 struct e1000_hw *hw = &adapter->hw;
2606 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2607
2608 if (adapter->msix_entries) {
2609 int vector;
2610
2611 for (vector = 0; vector < adapter->num_vectors; vector++)
2612 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2613 } else {
2614 ew32(ITR, new_itr);
2615 }
2616}
2617
4662e82b
BA		 2618/**
2619 * e1000_alloc_queues - Allocate memory for all rings
2620 * @adapter: board private structure to initialize
2621 **/
9f9a12f8 2622static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2623{
55aa6985
BA		 2624 int size = sizeof(struct e1000_ring);
2625
2626 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2627 if (!adapter->tx_ring)
2628 goto err;
55aa6985
BA		 2629 adapter->tx_ring->count = adapter->tx_ring_count;
2630 adapter->tx_ring->adapter = adapter;
4662e82b 2631
55aa6985 2632 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2633 if (!adapter->rx_ring)
2634 goto err;
55aa6985
BA		 2635 adapter->rx_ring->count = adapter->rx_ring_count;
2636 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2637
2638 return 0;
2639err:
2640 e_err("Unable to allocate memory for queues\n");
2641 kfree(adapter->rx_ring);
2642 kfree(adapter->tx_ring);
2643 return -ENOMEM;
2644}
2645
bc7f75fa 2646/**
c58c8a78 2647 * e1000e_poll - NAPI Rx polling callback
ad68076e 2648 * @napi: struct associated with this polling callback
c58c8a78 2649 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2650 **/
c58c8a78 2651static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2652{
c58c8a78
BA		 2653 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2654 napi);
4662e82b 2655 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2656 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2657 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2658
4cf1653a 2659 adapter = netdev_priv(poll_dev);
bc7f75fa 2660
c58c8a78
BA		 2661 if (!adapter->msix_entries ||
2662 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2663 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2664
c58c8a78 2665 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2666
12d04a3c 2667 if (!tx_cleaned)
c58c8a78 2668 work_done = weight;
bc7f75fa 2669
c58c8a78
BA		 2670 /* If weight not fully consumed, exit the polling mode */
2671 if (work_done < weight) {
bc7f75fa
AK		 2672 if (adapter->itr_setting & 3)
2673 e1000_set_itr(adapter);
288379f0 2674 napi_complete(napi);
a3c69fef
JB		 2675 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2676 if (adapter->msix_entries)
2677 ew32(IMS, adapter->rx_ring->ims_val);
2678 else
2679 e1000_irq_enable(adapter);
2680 }
bc7f75fa
AK		 2681 }
2682
2683 return work_done;
2684}
2685
80d5c368 2686static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2687 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2688{
2689 struct e1000_adapter *adapter = netdev_priv(netdev);
2690 struct e1000_hw *hw = &adapter->hw;
2691 u32 vfta, index;
2692
2693 /* don't update vlan cookie if already programmed */
2694 if ((adapter->hw.mng_cookie.status &
2695 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2696 (vid == adapter->mng_vlan_id))
8e586137 2697 return 0;
caaddaf8 2698
bc7f75fa 2699 /* add VID to filter table */
caaddaf8
BA		 2700 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2701 index = (vid >> 5) & 0x7F;
2702 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2703 vfta |= (1 << (vid & 0x1F));
2704 hw->mac.ops.write_vfta(hw, index, vfta);
2705 }
86d70e53
JK		 2706
2707 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2708
2709 return 0;
bc7f75fa
AK		 2710}
2711
80d5c368 2712static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2713 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2714{
2715 struct e1000_adapter *adapter = netdev_priv(netdev);
2716 struct e1000_hw *hw = &adapter->hw;
2717 u32 vfta, index;
2718
bc7f75fa
AK		 2719 if ((adapter->hw.mng_cookie.status &
2720 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2721 (vid == adapter->mng_vlan_id)) {
2722 /* release control to f/w */
31dbe5b4 2723 e1000e_release_hw_control(adapter);
8e586137 2724 return 0;
bc7f75fa
AK		 2725 }
2726
2727 /* remove VID from filter table */
caaddaf8
BA		 2728 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2729 index = (vid >> 5) & 0x7F;
2730 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2731 vfta &= ~(1 << (vid & 0x1F));
2732 hw->mac.ops.write_vfta(hw, index, vfta);
2733 }
86d70e53
JK		 2734
2735 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2736
2737 return 0;
bc7f75fa
AK		 2738}
2739
86d70e53
JK		 2740/**
2741 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2742 * @adapter: board private structure to initialize
2743 **/
2744static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2745{
2746 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2747 struct e1000_hw *hw = &adapter->hw;
2748 u32 rctl;
bc7f75fa 2749
86d70e53
JK		 2750 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2751 /* disable VLAN receive filtering */
2752 rctl = er32(RCTL);
2753 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2754 ew32(RCTL, rctl);
2755
2756 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2757 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2758 adapter->mng_vlan_id);
86d70e53 2759 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2760 }
bc7f75fa
AK		 2761 }
2762}
2763
86d70e53
JK		 2764/**
2765 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2766 * @adapter: board private structure to initialize
2767 **/
2768static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2769{
2770 struct e1000_hw *hw = &adapter->hw;
2771 u32 rctl;
2772
2773 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2774 /* enable VLAN receive filtering */
2775 rctl = er32(RCTL);
2776 rctl |= E1000_RCTL_VFE;
2777 rctl &= ~E1000_RCTL_CFIEN;
2778 ew32(RCTL, rctl);
2779 }
2780}
bc7f75fa 2781
86d70e53
JK		 2782/**
2783 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2784 * @adapter: board private structure to initialize
2785 **/
2786static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2787{
bc7f75fa 2788 struct e1000_hw *hw = &adapter->hw;
86d70e53 2789 u32 ctrl;
bc7f75fa 2790
86d70e53
JK		 2791 /* disable VLAN tag insert/strip */
2792 ctrl = er32(CTRL);
2793 ctrl &= ~E1000_CTRL_VME;
2794 ew32(CTRL, ctrl);
2795}
bc7f75fa 2796
86d70e53
JK		 2797/**
2798 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2799 * @adapter: board private structure to initialize
2800 **/
2801static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2802{
2803 struct e1000_hw *hw = &adapter->hw;
2804 u32 ctrl;
bc7f75fa 2805
86d70e53
JK		 2806 /* enable VLAN tag insert/strip */
2807 ctrl = er32(CTRL);
2808 ctrl |= E1000_CTRL_VME;
2809 ew32(CTRL, ctrl);
2810}
bc7f75fa 2811
86d70e53
JK		 2812static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2813{
2814 struct net_device *netdev = adapter->netdev;
2815 u16 vid = adapter->hw.mng_cookie.vlan_id;
2816 u16 old_vid = adapter->mng_vlan_id;
2817
e5fe2541 2818 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2819 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2820 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2821 }
2822
86d70e53 2823 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2824 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2825}
2826
2827static void e1000_restore_vlan(struct e1000_adapter *adapter)
2828{
2829 u16 vid;
2830
80d5c368 2831 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2832
86d70e53 2833 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2834 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2835}
2836
cd791618 2837static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2838{
2839 struct e1000_hw *hw = &adapter->hw;
cd791618 2840 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2841
2842 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2843 return;
2844
2845 manc = er32(MANC);
2846
e921eb1a 2847 /* enable receiving management packets to the host. this will probably
bc7f75fa 2848 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2849 * the packets will be handled on SMBUS
2850 */
bc7f75fa
AK		 2851 manc |= E1000_MANC_EN_MNG2HOST;
2852 manc2h = er32(MANC2H);
cd791618
BA		 2853
2854 switch (hw->mac.type) {
2855 default:
2856 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2857 break;
2858 case e1000_82574:
2859 case e1000_82583:
e921eb1a 2860 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2861 * if so, enable it.
2862 */
2863 for (i = 0, j = 0; i < 8; i++) {
2864 mdef = er32(MDEF(i));
2865
2866 /* Ignore filters with anything other than IPMI ports */
3b21b508 2867 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2868 continue;
2869
2870 /* Enable this decision filter in MANC2H */
2871 if (mdef)
2872 manc2h |= (1 << i);
2873
2874 j |= mdef;
2875 }
2876
2877 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2878 break;
2879
2880 /* Create new decision filter in an empty filter */
2881 for (i = 0, j = 0; i < 8; i++)
2882 if (er32(MDEF(i)) == 0) {
2883 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2884 E1000_MDEF_PORT_664));
2885 manc2h |= (1 << 1);
2886 j++;
2887 break;
2888 }
2889
2890 if (!j)
2891 e_warn("Unable to create IPMI pass-through filter\n");
2892 break;
2893 }
2894
bc7f75fa
AK		 2895 ew32(MANC2H, manc2h);
2896 ew32(MANC, manc);
2897}
2898
2899/**
af667a29 2900 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2901 * @adapter: board private structure
2902 *
2903 * Configure the Tx unit of the MAC after a reset.
2904 **/
2905static void e1000_configure_tx(struct e1000_adapter *adapter)
2906{
2907 struct e1000_hw *hw = &adapter->hw;
2908 struct e1000_ring *tx_ring = adapter->tx_ring;
2909 u64 tdba;
e7e834aa 2910 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2911
2912 /* Setup the HW Tx Head and Tail descriptor pointers */
2913 tdba = tx_ring->dma;
2914 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2915 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2916 ew32(TDBAH(0), (tdba >> 32));
2917 ew32(TDLEN(0), tdlen);
2918 ew32(TDH(0), 0);
2919 ew32(TDT(0), 0);
2920 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2921 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2922
bc7f75fa
AK		 2923 /* Set the Tx Interrupt Delay register */
2924 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2925 /* Tx irq moderation */
bc7f75fa
AK		 2926 ew32(TADV, adapter->tx_abs_int_delay);
2927
3a3b7586
JB		 2928 if (adapter->flags2 & FLAG2_DMA_BURST) {
2929 u32 txdctl = er32(TXDCTL(0));
6cf08d1c 2930
3a3b7586
JB		 2931 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2932 E1000_TXDCTL_WTHRESH);
e921eb1a 2933 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2934 * hardware to use the bus more efficiently in bursts, depends
2935 * on the tx_int_delay to be enabled,
8edc0e62 2936 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2937 * hthresh = 1 ==> prefetch when one or more available
2938 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2939 * BEWARE: this seems to work but should be considered first if
af667a29 2940 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2941 */
2942 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2943 ew32(TXDCTL(0), txdctl);
3a3b7586 2944 }
56032be7
BA		 2945 /* erratum work around: set txdctl the same for both queues */
2946 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2947
e7e834aa
DE		 2948 /* Program the Transmit Control Register */
2949 tctl = er32(TCTL);
2950 tctl &= ~E1000_TCTL_CT;
2951 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2952 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2953
bc7f75fa 2954 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2955 tarc = er32(TARC(0));
e921eb1a 2956 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2957 * gigabit link later
2958 */
bc7f75fa
AK		 2959#define SPEED_MODE_BIT (1 << 21)
2960 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2961 ew32(TARC(0), tarc);
bc7f75fa
AK		 2962 }
2963
2964 /* errata: program both queues to unweighted RR */
2965 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2966 tarc = er32(TARC(0));
bc7f75fa 2967 tarc |= 1;
e9ec2c0f
JK		 2968 ew32(TARC(0), tarc);
2969 tarc = er32(TARC(1));
bc7f75fa 2970 tarc |= 1;
e9ec2c0f 2971 ew32(TARC(1), tarc);
bc7f75fa
AK		 2972 }
2973
bc7f75fa
AK		 2974 /* Setup Transmit Descriptor Settings for eop descriptor */
2975 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2976
2977 /* only set IDE if we are delaying interrupts using the timers */
2978 if (adapter->tx_int_delay)
2979 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2980
2981 /* enable Report Status bit */
2982 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2983
e7e834aa
DE		 2984 ew32(TCTL, tctl);
2985
57cde763 2986 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2987}
2988
2989/**
2990 * e1000_setup_rctl - configure the receive control registers
2991 * @adapter: Board private structure
2992 **/
2993#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2994 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2995static void e1000_setup_rctl(struct e1000_adapter *adapter)
2996{
2997 struct e1000_hw *hw = &adapter->hw;
2998 u32 rctl, rfctl;
bc7f75fa
AK		 2999 u32 pages = 0;
3000
b20a7744
DE		 3001 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3002 * If jumbo frames not set, program related MAC/PHY registers
3003 * to h/w defaults
3004 */
3005 if (hw->mac.type >= e1000_pch2lan) {
3006 s32 ret_val;
3007
3008 if (adapter->netdev->mtu > ETH_DATA_LEN)
3009 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3010 else
3011 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3012
3013 if (ret_val)
3014 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3015 }
a1ce6473 3016
bc7f75fa
AK		 3017 /* Program MC offset vector base */
3018 rctl = er32(RCTL);
3019 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3020 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3021 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3022 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3023
3024 /* Do not Store bad packets */
3025 rctl &= ~E1000_RCTL_SBP;
3026
3027 /* Enable Long Packet receive */
3028 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3029 rctl &= ~E1000_RCTL_LPE;
3030 else
3031 rctl |= E1000_RCTL_LPE;
3032
eb7c3adb
JK		 3033 /* Some systems expect that the CRC is included in SMBUS traffic. The
3034 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3035 * host memory when this is enabled
3036 */
3037 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3038 rctl |= E1000_RCTL_SECRC;
5918bd88 3039
a4f58f54
BA		 3040 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3041 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3042 u16 phy_data;
3043
3044 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3045 phy_data &= 0xfff8;
3046 phy_data |= (1 << 2);
3047 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3048
3049 e1e_rphy(hw, 22, &phy_data);
3050 phy_data &= 0x0fff;
3051 phy_data |= (1 << 14);
3052 e1e_wphy(hw, 0x10, 0x2823);
3053 e1e_wphy(hw, 0x11, 0x0003);
3054 e1e_wphy(hw, 22, phy_data);
3055 }
3056
bc7f75fa
AK		 3057 /* Setup buffer sizes */
3058 rctl &= ~E1000_RCTL_SZ_4096;
3059 rctl |= E1000_RCTL_BSEX;
3060 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3061 case 2048:
3062 default:
3063 rctl |= E1000_RCTL_SZ_2048;
3064 rctl &= ~E1000_RCTL_BSEX;
3065 break;
3066 case 4096:
3067 rctl |= E1000_RCTL_SZ_4096;
3068 break;
3069 case 8192:
3070 rctl |= E1000_RCTL_SZ_8192;
3071 break;
3072 case 16384:
3073 rctl |= E1000_RCTL_SZ_16384;
3074 break;
3075 }
3076
5f450212
BA		 3077 /* Enable Extended Status in all Receive Descriptors */
3078 rfctl = er32(RFCTL);
3079 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3080 ew32(RFCTL, rfctl);
5f450212 3081
e921eb1a 3082 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3083 * header is placed in skb->data and the packet data is
3084 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3085 * In the case of a non-split, skb->data is linearly filled,
3086 * followed by the page buffers. Therefore, skb->data is
3087 * sized to hold the largest protocol header.
3088 *
3089 * allocations using alloc_page take too long for regular MTU
3090 * so only enable packet split for jumbo frames
3091 *
3092 * Using pages when the page size is greater than 16k wastes
3093 * a lot of memory, since we allocate 3 pages at all times
3094 * per packet.
3095 */
bc7f75fa 3096 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3097 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3098 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3099 else
3100 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3101
3102 if (adapter->rx_ps_pages) {
90da0669
BA		 3103 u32 psrctl = 0;
3104
140a7480
AK		 3105 /* Enable Packet split descriptors */
3106 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3107
e5fe2541 3108 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3109
3110 switch (adapter->rx_ps_pages) {
3111 case 3:
e5fe2541
BA		 3112 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3113 /* fall-through */
bc7f75fa 3114 case 2:
e5fe2541
BA		 3115 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3116 /* fall-through */
bc7f75fa 3117 case 1:
e5fe2541 3118 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3119 break;
3120 }
3121
3122 ew32(PSRCTL, psrctl);
3123 }
3124
cf955e6c
BG		 3125 /* This is useful for sniffing bad packets. */
3126 if (adapter->netdev->features & NETIF_F_RXALL) {
3127 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3128 * in e1000e_set_rx_mode
3129 */
e80bd1d1
BA		 3130 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3131 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3132 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3133
e80bd1d1
BA		 3134 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3135 E1000_RCTL_DPF | /* Allow filtered pause */
3136 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3137 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3138 * and that breaks VLANs.
3139 */
3140 }
3141
bc7f75fa 3142 ew32(RCTL, rctl);
318a94d6 3143 /* just started the receive unit, no need to restart */
12d43f7d 3144 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3145}
3146
3147/**
3148 * e1000_configure_rx - Configure Receive Unit after Reset
3149 * @adapter: board private structure
3150 *
3151 * Configure the Rx unit of the MAC after a reset.
3152 **/
3153static void e1000_configure_rx(struct e1000_adapter *adapter)
3154{
3155 struct e1000_hw *hw = &adapter->hw;
3156 struct e1000_ring *rx_ring = adapter->rx_ring;
3157 u64 rdba;
3158 u32 rdlen, rctl, rxcsum, ctrl_ext;
3159
3160 if (adapter->rx_ps_pages) {
3161 /* this is a 32 byte descriptor */
3162 rdlen = rx_ring->count *
af667a29 3163 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3164 adapter->clean_rx = e1000_clean_rx_irq_ps;
3165 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3166 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3167 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3168 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3169 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3170 } else {
5f450212 3171 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3172 adapter->clean_rx = e1000_clean_rx_irq;
3173 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3174 }
3175
3176 /* disable receives while setting up the descriptors */
3177 rctl = er32(RCTL);
7f99ae63
BA		 3178 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3179 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3180 e1e_flush();
1bba4386 3181 usleep_range(10000, 20000);
bc7f75fa 3182
3a3b7586 3183 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3184 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3185 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3186 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3187 * granularity = 01
3188 * wthresh = 04,
3189 * hthresh = 04,
3190 * pthresh = 0x20
3191 */
3192 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3193 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3194
e921eb1a 3195 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3196 * the value was not set by the user via module options
3197 */
3198 if (adapter->rx_int_delay == DEFAULT_RDTR)
3199 adapter->rx_int_delay = BURST_RDTR;
3200 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3201 adapter->rx_abs_int_delay = BURST_RADV;
3202 }
3203
bc7f75fa
AK		 3204 /* set the Receive Delay Timer Register */
3205 ew32(RDTR, adapter->rx_int_delay);
3206
3207 /* irq moderation */
3208 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3209 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3210 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3211
3212 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3213 /* Auto-Mask interrupts upon ICR access */
3214 ctrl_ext |= E1000_CTRL_EXT_IAME;
3215 ew32(IAM, 0xffffffff);
3216 ew32(CTRL_EXT, ctrl_ext);
3217 e1e_flush();
3218
e921eb1a 3219 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3220 * the Base and Length of the Rx Descriptor Ring
3221 */
bc7f75fa 3222 rdba = rx_ring->dma;
1e36052e
BA		 3223 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3224 ew32(RDBAH(0), (rdba >> 32));
3225 ew32(RDLEN(0), rdlen);
3226 ew32(RDH(0), 0);
3227 ew32(RDT(0), 0);
3228 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3229 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3230
3231 /* Enable Receive Checksum Offload for TCP and UDP */
3232 rxcsum = er32(RXCSUM);
2e1706f2 3233 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3234 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3235 else
bc7f75fa 3236 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3237 ew32(RXCSUM, rxcsum);
3238
3e35d991
BA		 3239 /* With jumbo frames, excessive C-state transition latencies result
3240 * in dropped transactions.
3241 */
3242 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3243 u32 lat =
3244 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3245 adapter->max_frame_size) * 8 / 1000;
3246
3247 if (adapter->flags & FLAG_IS_ICH) {
53ec5498 3248 u32 rxdctl = er32(RXDCTL(0));
6cf08d1c 3249
53ec5498 3250 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3251 }
3e35d991
BA		 3252
3253 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3254 } else {
3255 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3256 PM_QOS_DEFAULT_VALUE);
97ac8cae 3257 }
bc7f75fa
AK		 3258
3259 /* Enable Receives */
3260 ew32(RCTL, rctl);
3261}
3262
3263/**
ef9b965a
JB		 3264 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3265 * @netdev: network interface device structure
bc7f75fa 3266 *
ef9b965a
JB		 3267 * Writes multicast address list to the MTA hash table.
3268 * Returns: -ENOMEM on failure
3269 * 0 on no addresses written
3270 * X on writing X addresses to MTA
3271 */
3272static int e1000e_write_mc_addr_list(struct net_device *netdev)
3273{
3274 struct e1000_adapter *adapter = netdev_priv(netdev);
3275 struct e1000_hw *hw = &adapter->hw;
3276 struct netdev_hw_addr *ha;
3277 u8 *mta_list;
3278 int i;
3279
3280 if (netdev_mc_empty(netdev)) {
3281 /* nothing to program, so clear mc list */
3282 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3283 return 0;
3284 }
3285
3286 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3287 if (!mta_list)
3288 return -ENOMEM;
3289
3290 /* update_mc_addr_list expects a packed array of only addresses. */
3291 i = 0;
3292 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3293 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3294
3295 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3296 kfree(mta_list);
3297
3298 return netdev_mc_count(netdev);
3299}
3300
3301/**
3302 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3303 * @netdev: network interface device structure
bc7f75fa 3304 *
ef9b965a
JB		 3305 * Writes unicast address list to the RAR table.
3306 * Returns: -ENOMEM on failure/insufficient address space
3307 * 0 on no addresses written
3308 * X on writing X addresses to the RAR table
bc7f75fa 3309 **/
ef9b965a 3310static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3311{
ef9b965a
JB		 3312 struct e1000_adapter *adapter = netdev_priv(netdev);
3313 struct e1000_hw *hw = &adapter->hw;
b3e5bf1f 3314 unsigned int rar_entries;
ef9b965a
JB		 3315 int count = 0;
3316
b3e5bf1f
DE		 3317 rar_entries = hw->mac.ops.rar_get_count(hw);
3318
ef9b965a
JB		 3319 /* save a rar entry for our hardware address */
3320 rar_entries--;
3321
3322 /* save a rar entry for the LAA workaround */
3323 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3324 rar_entries--;
3325
3326 /* return ENOMEM indicating insufficient memory for addresses */
3327 if (netdev_uc_count(netdev) > rar_entries)
3328 return -ENOMEM;
3329
3330 if (!netdev_uc_empty(netdev) && rar_entries) {
3331 struct netdev_hw_addr *ha;
3332
e921eb1a 3333 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3334 * combining
3335 */
3336 netdev_for_each_uc_addr(ha, netdev) {
b3e5bf1f
DE		 3337 int rval;
3338
ef9b965a
JB		 3339 if (!rar_entries)
3340 break;
b3e5bf1f
DE		 3341 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3342 if (rval < 0)
3343 return -ENOMEM;
ef9b965a
JB		 3344 count++;
3345 }
3346 }
3347
3348 /* zero out the remaining RAR entries not used above */
3349 for (; rar_entries > 0; rar_entries--) {
3350 ew32(RAH(rar_entries), 0);
3351 ew32(RAL(rar_entries), 0);
3352 }
3353 e1e_flush();
3354
3355 return count;
bc7f75fa
AK		 3356}
3357
3358/**
ef9b965a 3359 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3360 * @netdev: network interface device structure
3361 *
ef9b965a
JB		 3362 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3363 * address list or the network interface flags are updated. This routine is
3364 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3365 * promiscuous mode, and all-multi behavior.
3366 **/
ef9b965a 3367static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3368{
3369 struct e1000_adapter *adapter = netdev_priv(netdev);
3370 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3371 u32 rctl;
bc7f75fa 3372
63eb48f1
DE		 3373 if (pm_runtime_suspended(netdev->dev.parent))
3374 return;
3375
bc7f75fa 3376 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3377 rctl = er32(RCTL);
3378
ef9b965a
JB		 3379 /* clear the affected bits */
3380 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3381
bc7f75fa
AK		 3382 if (netdev->flags & IFF_PROMISC) {
3383 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3384 /* Do not hardware filter VLANs in promisc mode */
3385 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3386 } else {
ef9b965a 3387 int count;
3d3a1676 3388
746b9f02
PM		 3389 if (netdev->flags & IFF_ALLMULTI) {
3390 rctl |= E1000_RCTL_MPE;
746b9f02 3391 } else {
e921eb1a 3392 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3393 * then we should just turn on promiscuous mode so
3394 * that we can at least receive multicast traffic
3395 */
3396 count = e1000e_write_mc_addr_list(netdev);
3397 if (count < 0)
3398 rctl |= E1000_RCTL_MPE;
746b9f02 3399 }
86d70e53 3400 e1000e_vlan_filter_enable(adapter);
e921eb1a 3401 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3402 * sufficient space to store all the addresses then enable
3403 * unicast promiscuous mode
bc7f75fa 3404 */
ef9b965a
JB		 3405 count = e1000e_write_uc_addr_list(netdev);
3406 if (count < 0)
3407 rctl |= E1000_RCTL_UPE;
bc7f75fa 3408 }
86d70e53 3409
ef9b965a
JB		 3410 ew32(RCTL, rctl);
3411
f646968f 3412 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3413 e1000e_vlan_strip_enable(adapter);
3414 else
3415 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3416}
3417
70495a50
BA		 3418static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3419{
3420 struct e1000_hw *hw = &adapter->hw;
3421 u32 mrqc, rxcsum;
3422 int i;
3423 static const u32 rsskey[10] = {
3424 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3425 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3426 };
3427
3428 /* Fill out hash function seed */
3429 for (i = 0; i < 10; i++)
3430 ew32(RSSRK(i), rsskey[i]);
3431
3432 /* Direct all traffic to queue 0 */
3433 for (i = 0; i < 32; i++)
3434 ew32(RETA(i), 0);
3435
e921eb1a 3436 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3437 * descriptor on writeback.
3438 */
3439 rxcsum = er32(RXCSUM);
3440 rxcsum |= E1000_RXCSUM_PCSD;
3441
3442 ew32(RXCSUM, rxcsum);
3443
3444 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3445 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3446 E1000_MRQC_RSS_FIELD_IPV6 |
3447 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3448 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3449
3450 ew32(MRQC, mrqc);
3451}
3452
b67e1913
BA		 3453/**
3454 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3455 * @adapter: board private structure
3456 * @timinca: pointer to returned time increment attributes
3457 *
3458 * Get attributes for incrementing the System Time Register SYSTIML/H at
3459 * the default base frequency, and set the cyclecounter shift value.
3460 **/
d89777bf 3461s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3462{
3463 struct e1000_hw *hw = &adapter->hw;
3464 u32 incvalue, incperiod, shift;
3465
3466 /* Make sure clock is enabled on I217 before checking the frequency */
3467 if ((hw->mac.type == e1000_pch_lpt) &&
3468 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3469 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3470 u32 fextnvm7 = er32(FEXTNVM7);
3471
3472 if (!(fextnvm7 & (1 << 0))) {
3473 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3474 e1e_flush();
3475 }
3476 }
3477
3478 switch (hw->mac.type) {
3479 case e1000_pch2lan:
3480 case e1000_pch_lpt:
3481 /* On I217, the clock frequency is 25MHz or 96MHz as
3482 * indicated by the System Clock Frequency Indication
3483 */
3484 if ((hw->mac.type != e1000_pch_lpt) ||
3485 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3486 /* Stable 96MHz frequency */
3487 incperiod = INCPERIOD_96MHz;
3488 incvalue = INCVALUE_96MHz;
3489 shift = INCVALUE_SHIFT_96MHz;
3490 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3491 break;
3492 }
3493 /* fall-through */
3494 case e1000_82574:
3495 case e1000_82583:
3496 /* Stable 25MHz frequency */
3497 incperiod = INCPERIOD_25MHz;
3498 incvalue = INCVALUE_25MHz;
3499 shift = INCVALUE_SHIFT_25MHz;
3500 adapter->cc.shift = shift;
3501 break;
3502 default:
3503 return -EINVAL;
3504 }
3505
3506 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3507 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3508
3509 return 0;
3510}
3511
3512/**
3513 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3514 * @adapter: board private structure
3515 *
3516 * Outgoing time stamping can be enabled and disabled. Play nice and
3517 * disable it when requested, although it shouldn't cause any overhead
3518 * when no packet needs it. At most one packet in the queue may be
3519 * marked for time stamping, otherwise it would be impossible to tell
3520 * for sure to which packet the hardware time stamp belongs.
3521 *
3522 * Incoming time stamping has to be configured via the hardware filters.
3523 * Not all combinations are supported, in particular event type has to be
3524 * specified. Matching the kind of event packet is not supported, with the
3525 * exception of "all V2 events regardless of level 2 or 4".
3526 **/
62d7e3a2
BH		 3527static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3528 struct hwtstamp_config *config)
b67e1913
BA		 3529{
3530 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3531 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3532 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3533 u32 rxmtrl = 0;
3534 u16 rxudp = 0;
3535 bool is_l4 = false;
3536 bool is_l2 = false;
b67e1913
BA		 3537 u32 regval;
3538 s32 ret_val;
3539
3540 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3541 return -EINVAL;
3542
3543 /* flags reserved for future extensions - must be zero */
3544 if (config->flags)
3545 return -EINVAL;
3546
3547 switch (config->tx_type) {
3548 case HWTSTAMP_TX_OFF:
3549 tsync_tx_ctl = 0;
3550 break;
3551 case HWTSTAMP_TX_ON:
3552 break;
3553 default:
3554 return -ERANGE;
3555 }
3556
3557 switch (config->rx_filter) {
3558 case HWTSTAMP_FILTER_NONE:
3559 tsync_rx_ctl = 0;
3560 break;
d89777bf
BA		 3561 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3562 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3563 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3564 is_l4 = true;
3565 break;
3566 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3567 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3568 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3569 is_l4 = true;
3570 break;
3571 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3572 /* Also time stamps V2 L2 Path Delay Request/Response */
3573 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3574 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3575 is_l2 = true;
3576 break;
3577 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3578 /* Also time stamps V2 L2 Path Delay Request/Response. */
3579 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3580 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3581 is_l2 = true;
3582 break;
3583 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3584 /* Hardware cannot filter just V2 L4 Sync messages;
3585 * fall-through to V2 (both L2 and L4) Sync.
3586 */
3587 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3588 /* Also time stamps V2 Path Delay Request/Response. */
3589 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3590 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3591 is_l2 = true;
3592 is_l4 = true;
3593 break;
3594 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3595 /* Hardware cannot filter just V2 L4 Delay Request messages;
3596 * fall-through to V2 (both L2 and L4) Delay Request.
3597 */
3598 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3599 /* Also time stamps V2 Path Delay Request/Response. */
3600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3601 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3602 is_l2 = true;
3603 is_l4 = true;
3604 break;
3605 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3606 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3607 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3608 * fall-through to all V2 (both L2 and L4) Events.
3609 */
3610 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3611 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3612 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3613 is_l2 = true;
3614 is_l4 = true;
3615 break;
3616 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3617 /* For V1, the hardware can only filter Sync messages or
3618 * Delay Request messages but not both so fall-through to
3619 * time stamp all packets.
3620 */
b67e1913 3621 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3622 is_l2 = true;
3623 is_l4 = true;
b67e1913
BA		 3624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3625 config->rx_filter = HWTSTAMP_FILTER_ALL;
3626 break;
3627 default:
3628 return -ERANGE;
3629 }
3630
62d7e3a2
BH		 3631 adapter->hwtstamp_config = *config;
3632
b67e1913
BA		 3633 /* enable/disable Tx h/w time stamping */
3634 regval = er32(TSYNCTXCTL);
3635 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3636 regval |= tsync_tx_ctl;
3637 ew32(TSYNCTXCTL, regval);
3638 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3639 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3640 e_err("Timesync Tx Control register not set as expected\n");
3641 return -EAGAIN;
3642 }
3643
3644 /* enable/disable Rx h/w time stamping */
3645 regval = er32(TSYNCRXCTL);
3646 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3647 regval |= tsync_rx_ctl;
3648 ew32(TSYNCRXCTL, regval);
3649 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3650 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3651 (regval & (E1000_TSYNCRXCTL_ENABLED |
3652 E1000_TSYNCRXCTL_TYPE_MASK))) {
3653 e_err("Timesync Rx Control register not set as expected\n");
3654 return -EAGAIN;
3655 }
3656
d89777bf
BA		 3657 /* L2: define ethertype filter for time stamped packets */
3658 if (is_l2)
3659 rxmtrl |= ETH_P_1588;
3660
3661 /* define which PTP packets get time stamped */
3662 ew32(RXMTRL, rxmtrl);
3663
3664 /* Filter by destination port */
3665 if (is_l4) {
3666 rxudp = PTP_EV_PORT;
3667 cpu_to_be16s(&rxudp);
3668 }
3669 ew32(RXUDP, rxudp);
3670
3671 e1e_flush();
3672
b67e1913 3673 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3674 er32(RXSTMPH);
3675 er32(TXSTMPH);
b67e1913
BA		 3676
3677 /* Get and set the System Time Register SYSTIM base frequency */
3678 ret_val = e1000e_get_base_timinca(adapter, &regval);
3679 if (ret_val)
3680 return ret_val;
3681 ew32(TIMINCA, regval);
3682
3683 /* reset the ns time counter */
3684 timecounter_init(&adapter->tc, &adapter->cc,
3685 ktime_to_ns(ktime_get_real()));
3686
3687 return 0;
3688}
3689
bc7f75fa 3690/**
ad68076e 3691 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3692 * @adapter: private board structure
3693 **/
3694static void e1000_configure(struct e1000_adapter *adapter)
3695{
55aa6985
BA		 3696 struct e1000_ring *rx_ring = adapter->rx_ring;
3697
ef9b965a 3698 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3699
3700 e1000_restore_vlan(adapter);
cd791618 3701 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3702
3703 e1000_configure_tx(adapter);
70495a50
BA		 3704
3705 if (adapter->netdev->features & NETIF_F_RXHASH)
3706 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3707 e1000_setup_rctl(adapter);
3708 e1000_configure_rx(adapter);
55aa6985 3709 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3710}
3711
3712/**
3713 * e1000e_power_up_phy - restore link in case the phy was powered down
3714 * @adapter: address of board private structure
3715 *
3716 * The phy may be powered down to save power and turn off link when the
3717 * driver is unloaded and wake on lan is not enabled (among others)
3718 * *** this routine MUST be followed by a call to e1000e_reset ***
3719 **/
3720void e1000e_power_up_phy(struct e1000_adapter *adapter)
3721{
17f208de
BA		 3722 if (adapter->hw.phy.ops.power_up)
3723 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3724
3725 adapter->hw.mac.ops.setup_link(&adapter->hw);
3726}
3727
3728/**
3729 * e1000_power_down_phy - Power down the PHY
3730 *
17f208de
BA		 3731 * Power down the PHY so no link is implied when interface is down.
3732 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3733 */
3734static void e1000_power_down_phy(struct e1000_adapter *adapter)
3735{
17f208de
BA		 3736 if (adapter->hw.phy.ops.power_down)
3737 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3738}
3739
3740/**
3741 * e1000e_reset - bring the hardware into a known good state
3742 *
3743 * This function boots the hardware and enables some settings that
3744 * require a configuration cycle of the hardware - those cannot be
3745 * set/changed during runtime. After reset the device needs to be
ad68076e 3746 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3747 */
3748void e1000e_reset(struct e1000_adapter *adapter)
3749{
3750 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3751 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3752 struct e1000_hw *hw = &adapter->hw;
3753 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3754 u32 pba = adapter->pba;
bc7f75fa
AK		 3755 u16 hwm;
3756
ad68076e 3757 /* reset Packet Buffer Allocation to default */
318a94d6 3758 ew32(PBA, pba);
df762464 3759
318a94d6 3760 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3761 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3762 * large enough to accommodate two full transmit packets,
3763 * rounded up to the next 1KB and expressed in KB. Likewise,
3764 * the Rx FIFO should be large enough to accommodate at least
3765 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3766 * expressed in KB.
3767 */
df762464 3768 pba = er32(PBA);
bc7f75fa 3769 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3770 tx_space = pba >> 16;
bc7f75fa 3771 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3772 pba &= 0xffff;
e921eb1a 3773 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3774 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3775 */
3776 min_tx_space = (adapter->max_frame_size +
e5fe2541 3777 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3778 min_tx_space = ALIGN(min_tx_space, 1024);
3779 min_tx_space >>= 10;
3780 /* software strips receive CRC, so leave room for it */
318a94d6 3781 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3782 min_rx_space = ALIGN(min_rx_space, 1024);
3783 min_rx_space >>= 10;
3784
e921eb1a 3785 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3786 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3787 * allocation, take space away from current Rx allocation
3788 */
df762464
AK		 3789 if ((tx_space < min_tx_space) &&
3790 ((min_tx_space - tx_space) < pba)) {
3791 pba -= min_tx_space - tx_space;
bc7f75fa 3792
e921eb1a 3793 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3794 * adjustment
ad68076e 3795 */
79d4e908 3796 if (pba < min_rx_space)
df762464 3797 pba = min_rx_space;
bc7f75fa 3798 }
df762464
AK		 3799
3800 ew32(PBA, pba);
bc7f75fa
AK		 3801 }
3802
e921eb1a 3803 /* flow control settings
ad68076e 3804 *
38eb394e 3805 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3806 * (or the size used for early receive) above it in the Rx FIFO.
3807 * Set it to the lower of:
3808 * - 90% of the Rx FIFO size, and
38eb394e 3809 * - the full Rx FIFO size minus one full frame
ad68076e 3810 */
d3738bb8
BA		 3811 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3812 fc->pause_time = 0xFFFF;
3813 else
3814 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3815 fc->send_xon = true;
d3738bb8
BA		 3816 fc->current_mode = fc->requested_mode;
3817
3818 switch (hw->mac.type) {
79d4e908
BA		 3819 case e1000_ich9lan:
3820 case e1000_ich10lan:
3821 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3822 pba = 14;
3823 ew32(PBA, pba);
3824 fc->high_water = 0x2800;
3825 fc->low_water = fc->high_water - 8;
3826 break;
3827 }
3828 /* fall-through */
d3738bb8 3829 default:
79d4e908
BA		 3830 hwm = min(((pba << 10) * 9 / 10),
3831 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3832
e80bd1d1 3833 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3834 fc->low_water = fc->high_water - 8;
3835 break;
3836 case e1000_pchlan:
e921eb1a 3837 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3838 * loads. If hangs persist, try disabling Tx flow control.
3839 */
3840 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3841 fc->high_water = 0x3500;
e80bd1d1 3842 fc->low_water = 0x1500;
38eb394e
BA		 3843 } else {
3844 fc->high_water = 0x5000;
e80bd1d1 3845 fc->low_water = 0x3000;
38eb394e 3846 }
a305595b 3847 fc->refresh_time = 0x1000;
d3738bb8
BA		 3848 break;
3849 case e1000_pch2lan:
2fbe4526 3850 case e1000_pch_lpt:
d3738bb8 3851 fc->refresh_time = 0x0400;
347b5201
BA		 3852
3853 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3854 fc->high_water = 0x05C20;
3855 fc->low_water = 0x05048;
3856 fc->pause_time = 0x0650;
3857 break;
828bac87 3858 }
347b5201 3859
ce345e08
BA		 3860 pba = 14;
3861 ew32(PBA, pba);
347b5201
BA		 3862 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3863 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3864 break;
38eb394e 3865 }
bc7f75fa 3866
e921eb1a 3867 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3868 * maximum size per Tx descriptor limited only to the transmit
3869 * allocation of the packet buffer minus 96 bytes with an upper
3870 * limit of 24KB due to receive synchronization limitations.
3871 */
3872 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3873 24 << 10);
3874
e921eb1a 3875 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3876 * fit in receive buffer.
828bac87
BA		 3877 */
3878 if (adapter->itr_setting & 0x3) {
79d4e908 3879 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3880 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3881 dev_info(&adapter->pdev->dev,
17e813ec 3882 "Interrupt Throttle Rate off\n");
828bac87 3883 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3884 e1000e_write_itr(adapter, 0);
828bac87
BA		 3885 }
3886 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3887 dev_info(&adapter->pdev->dev,
17e813ec 3888 "Interrupt Throttle Rate on\n");
828bac87
BA		 3889 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3890 adapter->itr = 20000;
22a4cca2 3891 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3892 }
3893 }
3894
bc7f75fa
AK		 3895 /* Allow time for pending master requests to run */
3896 mac->ops.reset_hw(hw);
97ac8cae 3897
e921eb1a 3898 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3899 * that the network interface is in control
3900 */
c43bc57e 3901 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3902 e1000e_get_hw_control(adapter);
97ac8cae 3903
bc7f75fa
AK		 3904 ew32(WUC, 0);
3905
3906 if (mac->ops.init_hw(hw))
44defeb3 3907 e_err("Hardware Error\n");
bc7f75fa
AK		 3908
3909 e1000_update_mng_vlan(adapter);
3910
3911 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3912 ew32(VET, ETH_P_8021Q);
3913
3914 e1000e_reset_adaptive(hw);
31dbe5b4 3915
b67e1913 3916 /* initialize systim and reset the ns time counter */
62d7e3a2 3917 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 3918
d495bcb8
BA		 3919 /* Set EEE advertisement as appropriate */
3920 if (adapter->flags2 & FLAG2_HAS_EEE) {
3921 s32 ret_val;
3922 u16 adv_addr;
3923
3924 switch (hw->phy.type) {
3925 case e1000_phy_82579:
3926 adv_addr = I82579_EEE_ADVERTISEMENT;
3927 break;
3928 case e1000_phy_i217:
3929 adv_addr = I217_EEE_ADVERTISEMENT;
3930 break;
3931 default:
3932 dev_err(&adapter->pdev->dev,
3933 "Invalid PHY type setting EEE advertisement\n");
3934 return;
3935 }
3936
3937 ret_val = hw->phy.ops.acquire(hw);
3938 if (ret_val) {
3939 dev_err(&adapter->pdev->dev,
3940 "EEE advertisement - unable to acquire PHY\n");
3941 return;
3942 }
3943
3944 e1000_write_emi_reg_locked(hw, adv_addr,
3945 hw->dev_spec.ich8lan.eee_disable ?
3946 0 : adapter->eee_advert);
3947
3948 hw->phy.ops.release(hw);
3949 }
3950
31dbe5b4 3951 if (!netif_running(adapter->netdev) &&
28002099 3952 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 3953 e1000_power_down_phy(adapter);
31dbe5b4 3954
bc7f75fa
AK		 3955 e1000_get_phy_info(hw);
3956
918d7197
BA		 3957 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3958 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3959 u16 phy_data = 0;
e921eb1a 3960 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3961 * the return value of this function because there is nothing
ad68076e
BA		 3962 * different we would do if it failed
3963 */
bc7f75fa
AK		 3964 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3965 phy_data &= ~IGP02E1000_PM_SPD;
3966 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3967 }
bc7f75fa
AK		 3968}
3969
3970int e1000e_up(struct e1000_adapter *adapter)
3971{
3972 struct e1000_hw *hw = &adapter->hw;
3973
3974 /* hardware has been reset, we need to reload some things */
3975 e1000_configure(adapter);
3976
3977 clear_bit(__E1000_DOWN, &adapter->state);
3978
4662e82b
BA		 3979 if (adapter->msix_entries)
3980 e1000_configure_msix(adapter);
bc7f75fa
AK		 3981 e1000_irq_enable(adapter);
3982
400484fa 3983 netif_start_queue(adapter->netdev);
4cb9be7a 3984
bc7f75fa 3985 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3986 if (adapter->msix_entries)
3987 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3988 else
3989 ew32(ICS, E1000_ICS_LSC);
3990
bc7f75fa
AK		 3991 return 0;
3992}
3993
713b3c9e
JB		 3994static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3995{
3996 struct e1000_hw *hw = &adapter->hw;
3997
3998 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3999 return;
4000
4001 /* flush pending descriptor writebacks to memory */
4002 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4003 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4004
4005 /* execute the writes immediately */
4006 e1e_flush();
bf03085f 4007
e921eb1a 4008 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 4009 * write is successful
4010 */
4011 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4012 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 4013
4014 /* execute the writes immediately */
4015 e1e_flush();
4016}
4017
67fd4fcb
JK		 4018static void e1000e_update_stats(struct e1000_adapter *adapter);
4019
28002099
DE		 4020/**
4021 * e1000e_down - quiesce the device and optionally reset the hardware
4022 * @adapter: board private structure
4023 * @reset: boolean flag to reset the hardware or not
4024 */
4025void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 4026{
4027 struct net_device *netdev = adapter->netdev;
4028 struct e1000_hw *hw = &adapter->hw;
4029 u32 tctl, rctl;
4030
e921eb1a 4031 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4032 * reschedule our watchdog timer
4033 */
bc7f75fa
AK		 4034 set_bit(__E1000_DOWN, &adapter->state);
4035
4036 /* disable receives in the hardware */
4037 rctl = er32(RCTL);
7f99ae63
BA		 4038 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4039 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4040 /* flush and sleep below */
4041
4cb9be7a 4042 netif_stop_queue(netdev);
bc7f75fa
AK		 4043
4044 /* disable transmits in the hardware */
4045 tctl = er32(TCTL);
4046 tctl &= ~E1000_TCTL_EN;
4047 ew32(TCTL, tctl);
7f99ae63 4048
bc7f75fa
AK		 4049 /* flush both disables and wait for them to finish */
4050 e1e_flush();
1bba4386 4051 usleep_range(10000, 20000);
bc7f75fa 4052
bc7f75fa
AK		 4053 e1000_irq_disable(adapter);
4054
a3b87a4c
BA		 4055 napi_synchronize(&adapter->napi);
4056
bc7f75fa
AK		 4057 del_timer_sync(&adapter->watchdog_timer);
4058 del_timer_sync(&adapter->phy_info_timer);
4059
bc7f75fa 4060 netif_carrier_off(netdev);
67fd4fcb
JK		 4061
4062 spin_lock(&adapter->stats64_lock);
4063 e1000e_update_stats(adapter);
4064 spin_unlock(&adapter->stats64_lock);
4065
400484fa 4066 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4067 e1000_clean_tx_ring(adapter->tx_ring);
4068 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4069
bc7f75fa
AK		 4070 adapter->link_speed = 0;
4071 adapter->link_duplex = 0;
4072
da1e2046
BA		 4073 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4074 if ((hw->mac.type >= e1000_pch2lan) &&
4075 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4076 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4077 e_dbg("failed to disable jumbo frame workaround mode\n");
4078
28002099 4079 if (reset && !pci_channel_offline(adapter->pdev))
52cc3086 4080 e1000e_reset(adapter);
bc7f75fa
AK		 4081}
4082
4083void e1000e_reinit_locked(struct e1000_adapter *adapter)
4084{
4085 might_sleep();
4086 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4087 usleep_range(1000, 2000);
28002099 4088 e1000e_down(adapter, true);
bc7f75fa
AK		 4089 e1000e_up(adapter);
4090 clear_bit(__E1000_RESETTING, &adapter->state);
4091}
4092
b67e1913
BA		 4093/**
4094 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4095 * @cc: cyclecounter structure
4096 **/
4097static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4098{
4099 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4100 cc);
4101 struct e1000_hw *hw = &adapter->hw;
5e7ff970 4102 cycle_t systim, systim_next;
b67e1913
BA		 4103
4104 /* latch SYSTIMH on read of SYSTIML */
4105 systim = (cycle_t)er32(SYSTIML);
4106 systim |= (cycle_t)er32(SYSTIMH) << 32;
4107
5e7ff970
TF		 4108 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4109 u64 incvalue, time_delta, rem, temp;
4110 int i;
4111
4112 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4113 * check to see that the time is incrementing at a reasonable
4114 * rate and is a multiple of incvalue
4115 */
4116 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4117 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4118 /* latch SYSTIMH on read of SYSTIML */
4119 systim_next = (cycle_t)er32(SYSTIML);
4120 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4121
4122 time_delta = systim_next - systim;
4123 temp = time_delta;
4124 rem = do_div(temp, incvalue);
4125
4126 systim = systim_next;
4127
4128 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4129 (rem == 0))
4130 break;
4131 }
4132 }
b67e1913
BA		 4133 return systim;
4134}
4135
bc7f75fa
AK		 4136/**
4137 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4138 * @adapter: board private structure to initialize
4139 *
4140 * e1000_sw_init initializes the Adapter private data structure.
4141 * Fields are initialized based on PCI device information and
4142 * OS network device settings (MTU size).
4143 **/
9f9a12f8 4144static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4145{
bc7f75fa
AK		 4146 struct net_device *netdev = adapter->netdev;
4147
4148 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4149 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4150 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4151 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4152 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4153 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4154
67fd4fcb
JK		 4155 spin_lock_init(&adapter->stats64_lock);
4156
4662e82b 4157 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4158
4662e82b
BA		 4159 if (e1000_alloc_queues(adapter))
4160 return -ENOMEM;
bc7f75fa 4161
b67e1913
BA		 4162 /* Setup hardware time stamping cyclecounter */
4163 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4164 adapter->cc.read = e1000e_cyclecounter_read;
4165 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4166 adapter->cc.mult = 1;
4167 /* cc.shift set in e1000e_get_base_tininca() */
4168
4169 spin_lock_init(&adapter->systim_lock);
4170 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4171 }
4172
bc7f75fa 4173 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4174 e1000_irq_disable(adapter);
4175
bc7f75fa
AK		 4176 set_bit(__E1000_DOWN, &adapter->state);
4177 return 0;
bc7f75fa
AK		 4178}
4179
f8d59f78
BA		 4180/**
4181 * e1000_intr_msi_test - Interrupt Handler
4182 * @irq: interrupt number
4183 * @data: pointer to a network interface device structure
4184 **/
8bb62869 4185static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4186{
4187 struct net_device *netdev = data;
4188 struct e1000_adapter *adapter = netdev_priv(netdev);
4189 struct e1000_hw *hw = &adapter->hw;
4190 u32 icr = er32(ICR);
4191
3bb99fe2 4192 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4193 if (icr & E1000_ICR_RXSEQ) {
4194 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4195 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4196 * interrupt is handled.
4197 */
f8d59f78
BA		 4198 wmb();
4199 }
4200
4201 return IRQ_HANDLED;
4202}
4203
4204/**
4205 * e1000_test_msi_interrupt - Returns 0 for successful test
4206 * @adapter: board private struct
4207 *
4208 * code flow taken from tg3.c
4209 **/
4210static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4211{
4212 struct net_device *netdev = adapter->netdev;
4213 struct e1000_hw *hw = &adapter->hw;
4214 int err;
4215
4216 /* poll_enable hasn't been called yet, so don't need disable */
4217 /* clear any pending events */
4218 er32(ICR);
4219
4220 /* free the real vector and request a test handler */
4221 e1000_free_irq(adapter);
4662e82b 4222 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4223
4224 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4225 * MSI irq handler will unset this flag
4226 */
f8d59f78
BA		 4227 adapter->flags |= FLAG_MSI_TEST_FAILED;
4228
4229 err = pci_enable_msi(adapter->pdev);
4230 if (err)
4231 goto msi_test_failed;
4232
a0607fd3 4233 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4234 netdev->name, netdev);
4235 if (err) {
4236 pci_disable_msi(adapter->pdev);
4237 goto msi_test_failed;
4238 }
4239
e921eb1a 4240 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4241 * interrupt.
4242 */
f8d59f78
BA		 4243 wmb();
4244
4245 e1000_irq_enable(adapter);
4246
4247 /* fire an unusual interrupt on the test handler */
4248 ew32(ICS, E1000_ICS_RXSEQ);
4249 e1e_flush();
569a3aff 4250 msleep(100);
f8d59f78
BA		 4251
4252 e1000_irq_disable(adapter);
4253
bc76329d 4254 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4255
4256 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4257 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4258 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4259 } else {
068e8a30 4260 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4261 }
f8d59f78
BA		 4262
4263 free_irq(adapter->pdev->irq, netdev);
4264 pci_disable_msi(adapter->pdev);
4265
f8d59f78 4266msi_test_failed:
4662e82b 4267 e1000e_set_interrupt_capability(adapter);
068e8a30 4268 return e1000_request_irq(adapter);
f8d59f78
BA		 4269}
4270
4271/**
4272 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4273 * @adapter: board private struct
4274 *
4275 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4276 **/
4277static int e1000_test_msi(struct e1000_adapter *adapter)
4278{
4279 int err;
4280 u16 pci_cmd;
4281
4282 if (!(adapter->flags & FLAG_MSI_ENABLED))
4283 return 0;
4284
4285 /* disable SERR in case the MSI write causes a master abort */
4286 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4287 if (pci_cmd & PCI_COMMAND_SERR)
4288 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4289 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4290
4291 err = e1000_test_msi_interrupt(adapter);
4292
36f2407f
DN		 4293 /* re-enable SERR */
4294 if (pci_cmd & PCI_COMMAND_SERR) {
4295 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4296 pci_cmd |= PCI_COMMAND_SERR;
4297 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4298 }
f8d59f78 4299
f8d59f78
BA		 4300 return err;
4301}
4302
bc7f75fa
AK		 4303/**
4304 * e1000_open - Called when a network interface is made active
4305 * @netdev: network interface device structure
4306 *
4307 * Returns 0 on success, negative value on failure
4308 *
4309 * The open entry point is called when a network interface is made
4310 * active by the system (IFF_UP). At this point all resources needed
4311 * for transmit and receive operations are allocated, the interrupt
4312 * handler is registered with the OS, the watchdog timer is started,
4313 * and the stack is notified that the interface is ready.
4314 **/
4315static int e1000_open(struct net_device *netdev)
4316{
4317 struct e1000_adapter *adapter = netdev_priv(netdev);
4318 struct e1000_hw *hw = &adapter->hw;
23606cf5 4319 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4320 int err;
4321
4322 /* disallow open during test */
4323 if (test_bit(__E1000_TESTING, &adapter->state))
4324 return -EBUSY;
4325
23606cf5
RW		 4326 pm_runtime_get_sync(&pdev->dev);
4327
9c563d20
JB		 4328 netif_carrier_off(netdev);
4329
bc7f75fa 4330 /* allocate transmit descriptors */
55aa6985 4331 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4332 if (err)
4333 goto err_setup_tx;
4334
4335 /* allocate receive descriptors */
55aa6985 4336 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4337 if (err)
4338 goto err_setup_rx;
4339
e921eb1a 4340 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4341 * interface is now open and reset the part to a known state.
4342 */
4343 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4344 e1000e_get_hw_control(adapter);
11b08be8
BA		 4345 e1000e_reset(adapter);
4346 }
4347
bc7f75fa
AK		 4348 e1000e_power_up_phy(adapter);
4349
4350 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4351 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4352 e1000_update_mng_vlan(adapter);
4353
79d4e908 4354 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4355 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4356 PM_QOS_DEFAULT_VALUE);
c128ec29 4357
e921eb1a 4358 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4359 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4360 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4361 * clean_rx handler before we do so.
4362 */
bc7f75fa
AK		 4363 e1000_configure(adapter);
4364
4365 err = e1000_request_irq(adapter);
4366 if (err)
4367 goto err_req_irq;
4368
e921eb1a 4369 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4370 * ignore e1000e MSI messages, which means we need to test our MSI
4371 * interrupt now
4372 */
4662e82b 4373 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4374 err = e1000_test_msi(adapter);
4375 if (err) {
4376 e_err("Interrupt allocation failed\n");
4377 goto err_req_irq;
4378 }
4379 }
4380
bc7f75fa
AK		 4381 /* From here on the code is the same as e1000e_up() */
4382 clear_bit(__E1000_DOWN, &adapter->state);
4383
4384 napi_enable(&adapter->napi);
4385
4386 e1000_irq_enable(adapter);
4387
09357b00 4388 adapter->tx_hang_recheck = false;
4cb9be7a 4389 netif_start_queue(netdev);
d55b53ff 4390
66148bab 4391 hw->mac.get_link_status = true;
23606cf5
RW		 4392 pm_runtime_put(&pdev->dev);
4393
bc7f75fa 4394 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4395 if (adapter->msix_entries)
4396 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4397 else
4398 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4399
4400 return 0;
4401
4402err_req_irq:
31dbe5b4 4403 e1000e_release_hw_control(adapter);
bc7f75fa 4404 e1000_power_down_phy(adapter);
55aa6985 4405 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4406err_setup_rx:
55aa6985 4407 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4408err_setup_tx:
4409 e1000e_reset(adapter);
23606cf5 4410 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4411
4412 return err;
4413}
4414
4415/**
4416 * e1000_close - Disables a network interface
4417 * @netdev: network interface device structure
4418 *
4419 * Returns 0, this is not allowed to fail
4420 *
4421 * The close entry point is called when an interface is de-activated
4422 * by the OS. The hardware is still under the drivers control, but
4423 * needs to be disabled. A global MAC reset is issued to stop the
4424 * hardware, and all transmit and receive resources are freed.
4425 **/
4426static int e1000_close(struct net_device *netdev)
4427{
4428 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4429 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4430 int count = E1000_CHECK_RESET_COUNT;
4431
4432 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4433 usleep_range(10000, 20000);
bc7f75fa
AK		 4434
4435 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4436
4437 pm_runtime_get_sync(&pdev->dev);
4438
4439 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4440 e1000e_down(adapter, true);
23606cf5 4441 e1000_free_irq(adapter);
63eb48f1
DE		 4442
4443 /* Link status message must follow this format */
4444 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4445 }
a3b87a4c
BA		 4446
4447 napi_disable(&adapter->napi);
4448
55aa6985
BA		 4449 e1000e_free_tx_resources(adapter->tx_ring);
4450 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4451
e921eb1a 4452 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4453 * the same ID is registered on the host OS (let 8021q kill it)
4454 */
e5fe2541 4455 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4456 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4457 adapter->mng_vlan_id);
bc7f75fa 4458
e921eb1a 4459 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4460 * interface is now closed
4461 */
31dbe5b4
BA		 4462 if ((adapter->flags & FLAG_HAS_AMT) &&
4463 !test_bit(__E1000_TESTING, &adapter->state))
4464 e1000e_release_hw_control(adapter);
bc7f75fa 4465
3e35d991 4466 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4467
23606cf5
RW		 4468 pm_runtime_put_sync(&pdev->dev);
4469
bc7f75fa
AK		 4470 return 0;
4471}
fc830b78 4472
bc7f75fa
AK		 4473/**
4474 * e1000_set_mac - Change the Ethernet Address of the NIC
4475 * @netdev: network interface device structure
4476 * @p: pointer to an address structure
4477 *
4478 * Returns 0 on success, negative on failure
4479 **/
4480static int e1000_set_mac(struct net_device *netdev, void *p)
4481{
4482 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4483 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4484 struct sockaddr *addr = p;
4485
4486 if (!is_valid_ether_addr(addr->sa_data))
4487 return -EADDRNOTAVAIL;
4488
4489 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4490 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4491
69e1e019 4492 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4493
4494 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4495 /* activate the work around */
4496 e1000e_set_laa_state_82571(&adapter->hw, 1);
4497
e921eb1a 4498 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4499 * between the time RAR[0] gets clobbered and the time it
4500 * gets fixed (in e1000_watchdog), the actual LAA is in one
4501 * of the RARs and no incoming packets directed to this port
4502 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4503 * RAR[14]
4504 */
69e1e019
BA		 4505 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4506 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4507 }
4508
4509 return 0;
4510}
4511
a8f88ff5
JB		 4512/**
4513 * e1000e_update_phy_task - work thread to update phy
4514 * @work: pointer to our work struct
4515 *
4516 * this worker thread exists because we must acquire a
4517 * semaphore to read the phy, which we could msleep while
4518 * waiting for it, and we can't msleep in a timer.
4519 **/
4520static void e1000e_update_phy_task(struct work_struct *work)
4521{
4522 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4523 struct e1000_adapter,
4524 update_phy_task);
a03206ed 4525 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4526
4527 if (test_bit(__E1000_DOWN, &adapter->state))
4528 return;
4529
a03206ed
DE		 4530 e1000_get_phy_info(hw);
4531
4532 /* Enable EEE on 82579 after link up */
4533 if (hw->phy.type == e1000_phy_82579)
4534 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4535}
4536
e921eb1a
BA		 4537/**
4538 * e1000_update_phy_info - timre call-back to update PHY info
4539 * @data: pointer to adapter cast into an unsigned long
4540 *
ad68076e
BA		 4541 * Need to wait a few seconds after link up to get diagnostic information from
4542 * the phy
e921eb1a 4543 **/
bc7f75fa
AK		 4544static void e1000_update_phy_info(unsigned long data)
4545{
53aa82da 4546 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4547
4548 if (test_bit(__E1000_DOWN, &adapter->state))
4549 return;
4550
a8f88ff5 4551 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4552}
4553
8c7bbb92
BA		 4554/**
4555 * e1000e_update_phy_stats - Update the PHY statistics counters
4556 * @adapter: board private structure
2b6b168d
BA		 4557 *
4558 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4559 **/
4560static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4561{
4562 struct e1000_hw *hw = &adapter->hw;
4563 s32 ret_val;
4564 u16 phy_data;
4565
4566 ret_val = hw->phy.ops.acquire(hw);
4567 if (ret_val)
4568 return;
4569
e921eb1a 4570 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4571 * If not, set to the page with the PHY status registers.
4572 */
2b6b168d 4573 hw->phy.addr = 1;
8c7bbb92
BA		 4574 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4575 &phy_data);
4576 if (ret_val)
4577 goto release;
2b6b168d
BA		 4578 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4579 ret_val = hw->phy.ops.set_page(hw,
4580 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4581 if (ret_val)
4582 goto release;
4583 }
4584
8c7bbb92 4585 /* Single Collision Count */
2b6b168d
BA		 4586 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4587 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4588 if (!ret_val)
4589 adapter->stats.scc += phy_data;
4590
4591 /* Excessive Collision Count */
2b6b168d
BA		 4592 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4593 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4594 if (!ret_val)
4595 adapter->stats.ecol += phy_data;
4596
4597 /* Multiple Collision Count */
2b6b168d
BA		 4598 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4599 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4600 if (!ret_val)
4601 adapter->stats.mcc += phy_data;
4602
4603 /* Late Collision Count */
2b6b168d
BA		 4604 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4605 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4606 if (!ret_val)
4607 adapter->stats.latecol += phy_data;
4608
4609 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4610 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4611 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4612 if (!ret_val)
4613 hw->mac.collision_delta = phy_data;
4614
4615 /* Defer Count */
2b6b168d
BA		 4616 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4617 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4618 if (!ret_val)
4619 adapter->stats.dc += phy_data;
4620
4621 /* Transmit with no CRS */
2b6b168d
BA		 4622 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4623 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4624 if (!ret_val)
4625 adapter->stats.tncrs += phy_data;
4626
4627release:
4628 hw->phy.ops.release(hw);
4629}
4630
bc7f75fa
AK		 4631/**
4632 * e1000e_update_stats - Update the board statistics counters
4633 * @adapter: board private structure
4634 **/
67fd4fcb 4635static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4636{
7274c20f 4637 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4638 struct e1000_hw *hw = &adapter->hw;
4639 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4640
e921eb1a 4641 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4642 * connection is down.
4643 */
4644 if (adapter->link_speed == 0)
4645 return;
4646 if (pci_channel_offline(pdev))
4647 return;
4648
bc7f75fa
AK		 4649 adapter->stats.crcerrs += er32(CRCERRS);
4650 adapter->stats.gprc += er32(GPRC);
7c25769f 4651 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4652 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4653 adapter->stats.bprc += er32(BPRC);
4654 adapter->stats.mprc += er32(MPRC);
4655 adapter->stats.roc += er32(ROC);
4656
bc7f75fa 4657 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4658
4659 /* Half-duplex statistics */
4660 if (adapter->link_duplex == HALF_DUPLEX) {
4661 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4662 e1000e_update_phy_stats(adapter);
4663 } else {
4664 adapter->stats.scc += er32(SCC);
4665 adapter->stats.ecol += er32(ECOL);
4666 adapter->stats.mcc += er32(MCC);
4667 adapter->stats.latecol += er32(LATECOL);
4668 adapter->stats.dc += er32(DC);
4669
4670 hw->mac.collision_delta = er32(COLC);
4671
4672 if ((hw->mac.type != e1000_82574) &&
4673 (hw->mac.type != e1000_82583))
4674 adapter->stats.tncrs += er32(TNCRS);
4675 }
4676 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4677 }
8c7bbb92 4678
bc7f75fa
AK		 4679 adapter->stats.xonrxc += er32(XONRXC);
4680 adapter->stats.xontxc += er32(XONTXC);
4681 adapter->stats.xoffrxc += er32(XOFFRXC);
4682 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4683 adapter->stats.gptc += er32(GPTC);
7c25769f 4684 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4685 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4686 adapter->stats.rnbc += er32(RNBC);
4687 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4688
4689 adapter->stats.mptc += er32(MPTC);
4690 adapter->stats.bptc += er32(BPTC);
4691
4692 /* used for adaptive IFS */
4693
4694 hw->mac.tx_packet_delta = er32(TPT);
4695 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4696
4697 adapter->stats.algnerrc += er32(ALGNERRC);
4698 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4699 adapter->stats.cexterr += er32(CEXTERR);
4700 adapter->stats.tsctc += er32(TSCTC);
4701 adapter->stats.tsctfc += er32(TSCTFC);
4702
bc7f75fa 4703 /* Fill out the OS statistics structure */
7274c20f
AK		 4704 netdev->stats.multicast = adapter->stats.mprc;
4705 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4706
4707 /* Rx Errors */
4708
e921eb1a 4709 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4710 * our own version based on RUC and ROC
4711 */
7274c20f 4712 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4713 adapter->stats.crcerrs + adapter->stats.algnerrc +
4714 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4715 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4716 adapter->stats.roc;
7274c20f
AK		 4717 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4718 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4719 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4720
4721 /* Tx Errors */
f0ff4398 4722 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4723 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4724 netdev->stats.tx_window_errors = adapter->stats.latecol;
4725 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4726
4727 /* Tx Dropped needs to be maintained elsewhere */
4728
bc7f75fa
AK		 4729 /* Management Stats */
4730 adapter->stats.mgptc += er32(MGTPTC);
4731 adapter->stats.mgprc += er32(MGTPRC);
4732 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4733
4734 /* Correctable ECC Errors */
4735 if (hw->mac.type == e1000_pch_lpt) {
4736 u32 pbeccsts = er32(PBECCSTS);
6cf08d1c 4737
94fb848b
BA		 4738 adapter->corr_errors +=
4739 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4740 adapter->uncorr_errors +=
4741 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4742 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4743 }
bc7f75fa
AK		 4744}
4745
7c25769f
BA		 4746/**
4747 * e1000_phy_read_status - Update the PHY register status snapshot
4748 * @adapter: board private structure
4749 **/
4750static void e1000_phy_read_status(struct e1000_adapter *adapter)
4751{
4752 struct e1000_hw *hw = &adapter->hw;
4753 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4754
97390ab8
BA		 4755 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4756 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4757 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4758 int ret_val;
4759
c2ade1a4
BA		 4760 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4761 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4762 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4763 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4764 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4765 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4766 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4767 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4768 if (ret_val)
44defeb3 4769 e_warn("Error reading PHY register\n");
7c25769f 4770 } else {
e921eb1a 4771 /* Do not read PHY registers if link is not up
7c25769f
BA		 4772 * Set values to typical power-on defaults
4773 */
4774 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4775 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4776 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4777 BMSR_ERCAP);
4778 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4779 ADVERTISE_ALL | ADVERTISE_CSMA);
4780 phy->lpa = 0;
4781 phy->expansion = EXPANSION_ENABLENPAGE;
4782 phy->ctrl1000 = ADVERTISE_1000FULL;
4783 phy->stat1000 = 0;
4784 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4785 }
7c25769f
BA		 4786}
4787
bc7f75fa
AK		 4788static void e1000_print_link_info(struct e1000_adapter *adapter)
4789{
bc7f75fa
AK		 4790 struct e1000_hw *hw = &adapter->hw;
4791 u32 ctrl = er32(CTRL);
4792
8f12fe86 4793 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4794 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4795 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4796 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4797 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4798 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4799 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4800}
4801
0c6bdb30 4802static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4803{
4804 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4805 bool link_active = false;
318a94d6
JK		 4806 s32 ret_val = 0;
4807
e921eb1a 4808 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4809 * Rx sequence error interrupt. get_link_status will stay
4810 * false until the check_for_link establishes link
4811 * for copper adapters ONLY
4812 */
4813 switch (hw->phy.media_type) {
4814 case e1000_media_type_copper:
4815 if (hw->mac.get_link_status) {
4816 ret_val = hw->mac.ops.check_for_link(hw);
4817 link_active = !hw->mac.get_link_status;
4818 } else {
3db1cd5c 4819 link_active = true;
318a94d6
JK		 4820 }
4821 break;
4822 case e1000_media_type_fiber:
4823 ret_val = hw->mac.ops.check_for_link(hw);
4824 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4825 break;
4826 case e1000_media_type_internal_serdes:
4827 ret_val = hw->mac.ops.check_for_link(hw);
4828 link_active = adapter->hw.mac.serdes_has_link;
4829 break;
4830 default:
4831 case e1000_media_type_unknown:
4832 break;
4833 }
4834
4835 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4836 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4837 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4838 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4839 }
4840
4841 return link_active;
4842}
4843
4844static void e1000e_enable_receives(struct e1000_adapter *adapter)
4845{
4846 /* make sure the receive unit is started */
4847 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4848 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4849 struct e1000_hw *hw = &adapter->hw;
4850 u32 rctl = er32(RCTL);
6cf08d1c 4851
318a94d6 4852 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4853 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4854 }
4855}
4856
ff10e13c
CW		 4857static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4858{
4859 struct e1000_hw *hw = &adapter->hw;
4860
e921eb1a 4861 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4862 * for hung state and reset, if two calls return true
4863 */
4864 if (e1000_check_phy_82574(hw))
4865 adapter->phy_hang_count++;
4866 else
4867 adapter->phy_hang_count = 0;
4868
4869 if (adapter->phy_hang_count > 1) {
4870 adapter->phy_hang_count = 0;
d9554e96 4871 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 4872 schedule_work(&adapter->reset_task);
4873 }
4874}
4875
bc7f75fa
AK		 4876/**
4877 * e1000_watchdog - Timer Call-back
4878 * @data: pointer to adapter cast into an unsigned long
4879 **/
4880static void e1000_watchdog(unsigned long data)
4881{
53aa82da 4882 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4883
4884 /* Do the rest outside of interrupt context */
4885 schedule_work(&adapter->watchdog_task);
4886
4887 /* TODO: make this use queue_delayed_work() */
4888}
4889
4890static void e1000_watchdog_task(struct work_struct *work)
4891{
4892 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4893 struct e1000_adapter,
4894 watchdog_task);
bc7f75fa
AK		 4895 struct net_device *netdev = adapter->netdev;
4896 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4897 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4898 struct e1000_ring *tx_ring = adapter->tx_ring;
4899 struct e1000_hw *hw = &adapter->hw;
4900 u32 link, tctl;
bc7f75fa 4901
615b32af
JB		 4902 if (test_bit(__E1000_DOWN, &adapter->state))
4903 return;
4904
b405e8df 4905 link = e1000e_has_link(adapter);
318a94d6 4906 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4907 /* Cancel scheduled suspend requests. */
4908 pm_runtime_resume(netdev->dev.parent);
4909
318a94d6 4910 e1000e_enable_receives(adapter);
bc7f75fa 4911 goto link_up;
bc7f75fa
AK		 4912 }
4913
4914 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4915 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4916 e1000_update_mng_vlan(adapter);
4917
bc7f75fa
AK		 4918 if (link) {
4919 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4920 bool txb2b = true;
23606cf5
RW		 4921
4922 /* Cancel scheduled suspend requests. */
4923 pm_runtime_resume(netdev->dev.parent);
4924
318a94d6 4925 /* update snapshot of PHY registers on LSC */
7c25769f 4926 e1000_phy_read_status(adapter);
bc7f75fa 4927 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4928 &adapter->link_speed,
4929 &adapter->link_duplex);
bc7f75fa 4930 e1000_print_link_info(adapter);
e792cd91
KS		 4931
4932 /* check if SmartSpeed worked */
4933 e1000e_check_downshift(hw);
4934 if (phy->speed_downgraded)
4935 netdev_warn(netdev,
4936 "Link Speed was downgraded by SmartSpeed\n");
4937
e921eb1a 4938 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4939 * if link has autonegotiated at 10/100 half
4940 */
4941 if ((hw->phy.type == e1000_phy_igp_3 ||
4942 hw->phy.type == e1000_phy_bm) &&
138953bb 4943 hw->mac.autoneg &&
f4187b56
BA		 4944 (adapter->link_speed == SPEED_10 ||
4945 adapter->link_speed == SPEED_100) &&
4946 (adapter->link_duplex == HALF_DUPLEX)) {
4947 u16 autoneg_exp;
4948
c2ade1a4 4949 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4950
c2ade1a4 4951 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4952 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4953 }
4954
f49c57e1 4955 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4956 adapter->tx_timeout_factor = 1;
4957 switch (adapter->link_speed) {
4958 case SPEED_10:
3db1cd5c 4959 txb2b = false;
10f1b492 4960 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4961 break;
4962 case SPEED_100:
3db1cd5c 4963 txb2b = false;
4c86e0b9 4964 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4965 break;
4966 }
4967
e921eb1a 4968 /* workaround: re-program speed mode bit after
ad68076e
BA		 4969 * link-up event
4970 */
bc7f75fa
AK		 4971 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4972 !txb2b) {
4973 u32 tarc0;
6cf08d1c 4974
e9ec2c0f 4975 tarc0 = er32(TARC(0));
bc7f75fa 4976 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4977 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4978 }
4979
e921eb1a 4980 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4981 * some hardware issues
4982 */
bc7f75fa
AK		 4983 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4984 switch (adapter->link_speed) {
4985 case SPEED_10:
4986 case SPEED_100:
44defeb3 4987 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4988 netdev->features &= ~NETIF_F_TSO;
4989 netdev->features &= ~NETIF_F_TSO6;
4990 break;
4991 case SPEED_1000:
4992 netdev->features |= NETIF_F_TSO;
4993 netdev->features |= NETIF_F_TSO6;
4994 break;
4995 default:
4996 /* oops */
4997 break;
4998 }
4999 }
5000
e921eb1a 5001 /* enable transmits in the hardware, need to do this
ad68076e
BA		 5002 * after setting TARC(0)
5003 */
bc7f75fa
AK		 5004 tctl = er32(TCTL);
5005 tctl |= E1000_TCTL_EN;
5006 ew32(TCTL, tctl);
5007
e921eb1a 5008 /* Perform any post-link-up configuration before
75eb0fad
BA		 5009 * reporting link up.
5010 */
5011 if (phy->ops.cfg_on_link_up)
5012 phy->ops.cfg_on_link_up(hw);
5013
bc7f75fa 5014 netif_carrier_on(netdev);
bc7f75fa
AK		 5015
5016 if (!test_bit(__E1000_DOWN, &adapter->state))
5017 mod_timer(&adapter->phy_info_timer,
5018 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 5019 }
5020 } else {
5021 if (netif_carrier_ok(netdev)) {
5022 adapter->link_speed = 0;
5023 adapter->link_duplex = 0;
8f12fe86 5024 /* Link status message must follow this format */
7dbc1672 5025 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 5026 netif_carrier_off(netdev);
bc7f75fa
AK		 5027 if (!test_bit(__E1000_DOWN, &adapter->state))
5028 mod_timer(&adapter->phy_info_timer,
5029 round_jiffies(jiffies + 2 * HZ));
5030
d9554e96
DE		 5031 /* 8000ES2LAN requires a Rx packet buffer work-around
5032 * on link down event; reset the controller to flush
5033 * the Rx packet buffer.
12d43f7d 5034 */
d9554e96 5035 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 5036 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 5037 else
5038 pm_schedule_suspend(netdev->dev.parent,
17e813ec 5039 LINK_TIMEOUT);
bc7f75fa
AK		 5040 }
5041 }
5042
5043link_up:
67fd4fcb 5044 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 5045 e1000e_update_stats(adapter);
5046
5047 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5048 adapter->tpt_old = adapter->stats.tpt;
5049 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5050 adapter->colc_old = adapter->stats.colc;
5051
7c25769f
BA		 5052 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5053 adapter->gorc_old = adapter->stats.gorc;
5054 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5055 adapter->gotc_old = adapter->stats.gotc;
2084b114 5056 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5057
d9554e96
DE		 5058 /* If the link is lost the controller stops DMA, but
5059 * if there is queued Tx work it cannot be done. So
5060 * reset the controller to flush the Tx packet buffers.
5061 */
5062 if (!netif_carrier_ok(netdev) &&
5063 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5064 adapter->flags |= FLAG_RESTART_NOW;
5065
5066 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5067 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5068 schedule_work(&adapter->reset_task);
5069 /* return immediately since reset is imminent */
5070 return;
bc7f75fa
AK		 5071 }
5072
12d43f7d
BA		 5073 e1000e_update_adaptive(&adapter->hw);
5074
eab2abf5
JB		 5075 /* Simple mode for Interrupt Throttle Rate (ITR) */
5076 if (adapter->itr_setting == 4) {
e921eb1a 5077 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5078 * Total asymmetrical Tx or Rx gets ITR=8000;
5079 * everyone else is between 2000-8000.
5080 */
5081 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5082 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5083 adapter->gotc - adapter->gorc :
5084 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5085 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5086
22a4cca2 5087 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5088 }
5089
ad68076e 5090 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5091 if (adapter->msix_entries)
5092 ew32(ICS, adapter->rx_ring->ims_val);
5093 else
5094 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5095
713b3c9e
JB		 5096 /* flush pending descriptors to memory before detecting Tx hang */
5097 e1000e_flush_descriptors(adapter);
5098
bc7f75fa 5099 /* Force detection of hung controller every watchdog period */
3db1cd5c 5100 adapter->detect_tx_hung = true;
bc7f75fa 5101
e921eb1a 5102 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5103 * reset from the other port. Set the appropriate LAA in RAR[0]
5104 */
bc7f75fa 5105 if (e1000e_get_laa_state_82571(hw))
69e1e019 5106 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5107
ff10e13c
CW		 5108 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5109 e1000e_check_82574_phy_workaround(adapter);
5110
b67e1913
BA		 5111 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5112 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5113 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5114 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5115 er32(RXSTMPH);
5116 adapter->rx_hwtstamp_cleared++;
5117 } else {
5118 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5119 }
5120 }
5121
bc7f75fa
AK		 5122 /* Reset the timer */
5123 if (!test_bit(__E1000_DOWN, &adapter->state))
5124 mod_timer(&adapter->watchdog_timer,
5125 round_jiffies(jiffies + 2 * HZ));
5126}
5127
5128#define E1000_TX_FLAGS_CSUM 0x00000001
5129#define E1000_TX_FLAGS_VLAN 0x00000002
5130#define E1000_TX_FLAGS_TSO 0x00000004
5131#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5132#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5133#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5134#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5135#define E1000_TX_FLAGS_VLAN_SHIFT 16
5136
55aa6985 5137static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5138{
bc7f75fa
AK		 5139 struct e1000_context_desc *context_desc;
5140 struct e1000_buffer *buffer_info;
5141 unsigned int i;
5142 u32 cmd_length = 0;
70443ae9 5143 u16 ipcse = 0, mss;
bc7f75fa 5144 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bcf1f57f 5145 int err;
bc7f75fa 5146
3d5e33c9
BA		 5147 if (!skb_is_gso(skb))
5148 return 0;
bc7f75fa 5149
bcf1f57f
FR		 5150 err = skb_cow_head(skb, 0);
5151 if (err < 0)
5152 return err;
bc7f75fa 5153
3d5e33c9
BA		 5154 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5155 mss = skb_shinfo(skb)->gso_size;
5156 if (skb->protocol == htons(ETH_P_IP)) {
5157 struct iphdr *iph = ip_hdr(skb);
5158 iph->tot_len = 0;
5159 iph->check = 0;
5160 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5161 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5162 cmd_length = E1000_TXD_CMD_IP;
5163 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5164 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5165 ipv6_hdr(skb)->payload_len = 0;
5166 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5167 &ipv6_hdr(skb)->daddr,
5168 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5169 ipcse = 0;
5170 }
5171 ipcss = skb_network_offset(skb);
5172 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5173 tucss = skb_transport_offset(skb);
5174 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5175
5176 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5177 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5178
5179 i = tx_ring->next_to_use;
5180 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5181 buffer_info = &tx_ring->buffer_info[i];
5182
e80bd1d1
BA		 5183 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5184 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5185 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5186 context_desc->upper_setup.tcp_fields.tucss = tucss;
5187 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5188 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5189 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5190 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5191 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5192
5193 buffer_info->time_stamp = jiffies;
5194 buffer_info->next_to_watch = i;
5195
5196 i++;
5197 if (i == tx_ring->count)
5198 i = 0;
5199 tx_ring->next_to_use = i;
5200
5201 return 1;
bc7f75fa
AK		 5202}
5203
55aa6985 5204static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5205{
55aa6985 5206 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5207 struct e1000_context_desc *context_desc;
5208 struct e1000_buffer *buffer_info;
5209 unsigned int i;
5210 u8 css;
af807c82 5211 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5212 __be16 protocol;
bc7f75fa 5213
af807c82 5214 if (skb->ip_summed != CHECKSUM_PARTIAL)
3992c8ed 5215 return false;
bc7f75fa 5216
5f66f208
AJ		 5217 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5218 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5219 else
5220 protocol = skb->protocol;
5221
3f518390 5222 switch (protocol) {
09640e63 5223 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5224 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5225 cmd_len |= E1000_TXD_CMD_TCP;
5226 break;
09640e63 5227 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5228 /* XXX not handling all IPV6 headers */
5229 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5230 cmd_len |= E1000_TXD_CMD_TCP;
5231 break;
5232 default:
5233 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5234 e_warn("checksum_partial proto=%x!\n",
5235 be16_to_cpu(protocol));
af807c82 5236 break;
bc7f75fa
AK		 5237 }
5238
0d0b1672 5239 css = skb_checksum_start_offset(skb);
af807c82
DG		 5240
5241 i = tx_ring->next_to_use;
5242 buffer_info = &tx_ring->buffer_info[i];
5243 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5244
5245 context_desc->lower_setup.ip_config = 0;
5246 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5247 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5248 context_desc->upper_setup.tcp_fields.tucse = 0;
5249 context_desc->tcp_seg_setup.data = 0;
5250 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5251
5252 buffer_info->time_stamp = jiffies;
5253 buffer_info->next_to_watch = i;
5254
5255 i++;
5256 if (i == tx_ring->count)
5257 i = 0;
5258 tx_ring->next_to_use = i;
5259
3992c8ed 5260 return true;
bc7f75fa
AK		 5261}
5262
55aa6985
BA		 5263static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5264 unsigned int first, unsigned int max_per_txd,
d821a4c4 5265 unsigned int nr_frags)
bc7f75fa 5266{
55aa6985 5267 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5268 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5269 struct e1000_buffer *buffer_info;
8ddc951c 5270 unsigned int len = skb_headlen(skb);
03b1320d 5271 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5272 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5273
5274 i = tx_ring->next_to_use;
5275
5276 while (len) {
1b7719c4 5277 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5278 size = min(len, max_per_txd);
5279
bc7f75fa 5280 buffer_info->length = size;
bc7f75fa 5281 buffer_info->time_stamp = jiffies;
bc7f75fa 5282 buffer_info->next_to_watch = i;
0be3f55f
NN		 5283 buffer_info->dma = dma_map_single(&pdev->dev,
5284 skb->data + offset,
af667a29 5285 size, DMA_TO_DEVICE);
03b1320d 5286 buffer_info->mapped_as_page = false;
0be3f55f 5287 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5288 goto dma_error;
bc7f75fa
AK		 5289
5290 len -= size;
5291 offset += size;
03b1320d 5292 count++;
1b7719c4
AD		 5293
5294 if (len) {
5295 i++;
5296 if (i == tx_ring->count)
5297 i = 0;
5298 }
bc7f75fa
AK		 5299 }
5300
5301 for (f = 0; f < nr_frags; f++) {
9e903e08 5302 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5303
5304 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5305 len = skb_frag_size(frag);
877749bf 5306 offset = 0;
bc7f75fa
AK		 5307
5308 while (len) {
1b7719c4
AD		 5309 i++;
5310 if (i == tx_ring->count)
5311 i = 0;
5312
bc7f75fa
AK		 5313 buffer_info = &tx_ring->buffer_info[i];
5314 size = min(len, max_per_txd);
bc7f75fa
AK		 5315
5316 buffer_info->length = size;
5317 buffer_info->time_stamp = jiffies;
bc7f75fa 5318 buffer_info->next_to_watch = i;
877749bf 5319 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5320 offset, size,
5321 DMA_TO_DEVICE);
03b1320d 5322 buffer_info->mapped_as_page = true;
0be3f55f 5323 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5324 goto dma_error;
bc7f75fa
AK		 5325
5326 len -= size;
5327 offset += size;
5328 count++;
bc7f75fa
AK		 5329 }
5330 }
5331
af667a29 5332 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5333 /* multiply data chunks by size of headers */
5334 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5335
bc7f75fa 5336 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5337 tx_ring->buffer_info[i].segs = segs;
5338 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5339 tx_ring->buffer_info[first].next_to_watch = i;
5340
5341 return count;
03b1320d
AD		 5342
5343dma_error:
af667a29 5344 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5345 buffer_info->dma = 0;
c1fa347f 5346 if (count)
03b1320d 5347 count--;
c1fa347f
RK		 5348
5349 while (count--) {
af667a29 5350 if (i == 0)
03b1320d 5351 i += tx_ring->count;
c1fa347f 5352 i--;
03b1320d 5353 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5354 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5355 }
5356
5357 return 0;
bc7f75fa
AK		 5358}
5359
55aa6985 5360static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5361{
55aa6985 5362 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5363 struct e1000_tx_desc *tx_desc = NULL;
5364 struct e1000_buffer *buffer_info;
5365 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5366 unsigned int i;
5367
5368 if (tx_flags & E1000_TX_FLAGS_TSO) {
5369 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5370 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5371 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5372
5373 if (tx_flags & E1000_TX_FLAGS_IPV4)
5374 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5375 }
5376
5377 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5378 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5379 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5380 }
5381
5382 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5383 txd_lower |= E1000_TXD_CMD_VLE;
5384 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5385 }
5386
943146de
BG		 5387 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5388 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5389
b67e1913
BA		 5390 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5391 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5392 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5393 }
5394
bc7f75fa
AK		 5395 i = tx_ring->next_to_use;
5396
36b973df 5397 do {
bc7f75fa
AK		 5398 buffer_info = &tx_ring->buffer_info[i];
5399 tx_desc = E1000_TX_DESC(*tx_ring, i);
5400 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5401 tx_desc->lower.data = cpu_to_le32(txd_lower |
5402 buffer_info->length);
bc7f75fa
AK		 5403 tx_desc->upper.data = cpu_to_le32(txd_upper);
5404
5405 i++;
5406 if (i == tx_ring->count)
5407 i = 0;
36b973df 5408 } while (--count > 0);
bc7f75fa
AK		 5409
5410 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5411
943146de
BG		 5412 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5413 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5414 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5415
e921eb1a 5416 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5417 * know there are new descriptors to fetch. (Only
5418 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5419 * such as IA-64).
5420 */
bc7f75fa
AK		 5421 wmb();
5422
5423 tx_ring->next_to_use = i;
c6e7f51e
BA		 5424
5425 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5426 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5427 else
c5083cf6 5428 writel(i, tx_ring->tail);
c6e7f51e 5429
e921eb1a 5430 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5431 * at a time, it synchronizes IO on IA64/Altix systems
5432 */
bc7f75fa
AK		 5433 mmiowb();
5434}
5435
5436#define MINIMUM_DHCP_PACKET_SIZE 282
5437static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5438 struct sk_buff *skb)
5439{
e80bd1d1 5440 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5441 u16 length, offset;
5442
d60923c4
BA		 5443 if (vlan_tx_tag_present(skb) &&
5444 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5445 (adapter->hw.mng_cookie.status &
5446 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5447 return 0;
bc7f75fa
AK		 5448
5449 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5450 return 0;
5451
53aa82da 5452 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5453 return 0;
5454
5455 {
362e20ca 5456 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5457 struct udphdr *udp;
5458
5459 if (ip->protocol != IPPROTO_UDP)
5460 return 0;
5461
5462 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5463 if (ntohs(udp->dest) != 67)
5464 return 0;
5465
5466 offset = (u8 *)udp + 8 - skb->data;
5467 length = skb->len - offset;
5468 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5469 }
5470
5471 return 0;
5472}
5473
55aa6985 5474static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5475{
55aa6985 5476 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5477
55aa6985 5478 netif_stop_queue(adapter->netdev);
e921eb1a 5479 /* Herbert's original patch had:
bc7f75fa 5480 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5481 * but since that doesn't exist yet, just open code it.
5482 */
bc7f75fa
AK		 5483 smp_mb();
5484
e921eb1a 5485 /* We need to check again in a case another CPU has just
ad68076e
BA		 5486 * made room available.
5487 */
55aa6985 5488 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5489 return -EBUSY;
5490
5491 /* A reprieve! */
55aa6985 5492 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5493 ++adapter->restart_queue;
5494 return 0;
5495}
5496
55aa6985 5497static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5498{
d821a4c4
BA		 5499 BUG_ON(size > tx_ring->count);
5500
55aa6985 5501 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5502 return 0;
55aa6985 5503 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5504}
5505
3b29a56d
SH		 5506static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5507 struct net_device *netdev)
bc7f75fa
AK		 5508{
5509 struct e1000_adapter *adapter = netdev_priv(netdev);
5510 struct e1000_ring *tx_ring = adapter->tx_ring;
5511 unsigned int first;
bc7f75fa 5512 unsigned int tx_flags = 0;
e743d313 5513 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5514 unsigned int nr_frags;
5515 unsigned int mss;
bc7f75fa
AK		 5516 int count = 0;
5517 int tso;
5518 unsigned int f;
bc7f75fa
AK		 5519
5520 if (test_bit(__E1000_DOWN, &adapter->state)) {
5521 dev_kfree_skb_any(skb);
5522 return NETDEV_TX_OK;
5523 }
5524
5525 if (skb->len <= 0) {
5526 dev_kfree_skb_any(skb);
5527 return NETDEV_TX_OK;
5528 }
5529
e921eb1a 5530 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5531 * pad skb in order to meet this minimum size requirement
5532 */
5533 if (unlikely(skb->len < 17)) {
5534 if (skb_pad(skb, 17 - skb->len))
5535 return NETDEV_TX_OK;
5536 skb->len = 17;
5537 skb_set_tail_pointer(skb, 17);
5538 }
5539
bc7f75fa 5540 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5541 if (mss) {
5542 u8 hdr_len;
bc7f75fa 5543
e921eb1a 5544 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5545 * points to just header, pull a few bytes of payload from
5546 * frags into skb->data
5547 */
bc7f75fa 5548 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5549 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5550 * avoiding it could save a lot of cycles
5551 */
4e6c709c 5552 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5553 unsigned int pull_size;
5554
a2a5b323 5555 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5556 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5557 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5558 dev_kfree_skb_any(skb);
5559 return NETDEV_TX_OK;
5560 }
e743d313 5561 len = skb_headlen(skb);
bc7f75fa
AK		 5562 }
5563 }
5564
5565 /* reserve a descriptor for the offload context */
5566 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5567 count++;
5568 count++;
5569
d821a4c4 5570 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5571
5572 nr_frags = skb_shinfo(skb)->nr_frags;
5573 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5574 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5575 adapter->tx_fifo_limit);
bc7f75fa
AK		 5576
5577 if (adapter->hw.mac.tx_pkt_filtering)
5578 e1000_transfer_dhcp_info(adapter, skb);
5579
e921eb1a 5580 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5581 * head, otherwise try next time
5582 */
55aa6985 5583 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5584 return NETDEV_TX_BUSY;
bc7f75fa 5585
eab6d18d 5586 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5587 tx_flags |= E1000_TX_FLAGS_VLAN;
5588 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5589 }
5590
5591 first = tx_ring->next_to_use;
5592
55aa6985 5593 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5594 if (tso < 0) {
5595 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5596 return NETDEV_TX_OK;
5597 }
5598
5599 if (tso)
5600 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5601 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5602 tx_flags |= E1000_TX_FLAGS_CSUM;
5603
e921eb1a 5604 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5605 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5606 * no longer assume, we must.
5607 */
bc7f75fa
AK		 5608 if (skb->protocol == htons(ETH_P_IP))
5609 tx_flags |= E1000_TX_FLAGS_IPV4;
5610
943146de
BG		 5611 if (unlikely(skb->no_fcs))
5612 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5613
25985edc 5614 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5615 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5616 nr_frags);
1b7719c4 5617 if (count) {
b67e1913
BA		 5618 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5619 !adapter->tx_hwtstamp_skb)) {
5620 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5621 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5622 adapter->tx_hwtstamp_skb = skb_get(skb);
59c871c5 5623 adapter->tx_hwtstamp_start = jiffies;
b67e1913
BA		 5624 schedule_work(&adapter->tx_hwtstamp_work);
5625 } else {
5626 skb_tx_timestamp(skb);
5627 }
80be3129 5628
3f0cfa3b 5629 netdev_sent_queue(netdev, skb->len);
55aa6985 5630 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5631 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5632 e1000_maybe_stop_tx(tx_ring,
5633 (MAX_SKB_FRAGS *
5634 DIV_ROUND_UP(PAGE_SIZE,
5635 adapter->tx_fifo_limit) + 2));
1b7719c4 5636 } else {
bc7f75fa 5637 dev_kfree_skb_any(skb);
1b7719c4
AD		 5638 tx_ring->buffer_info[first].time_stamp = 0;
5639 tx_ring->next_to_use = first;
bc7f75fa
AK		 5640 }
5641
bc7f75fa
AK		 5642 return NETDEV_TX_OK;
5643}
5644
5645/**
5646 * e1000_tx_timeout - Respond to a Tx Hang
5647 * @netdev: network interface device structure
5648 **/
5649static void e1000_tx_timeout(struct net_device *netdev)
5650{
5651 struct e1000_adapter *adapter = netdev_priv(netdev);
5652
5653 /* Do the reset outside of interrupt context */
5654 adapter->tx_timeout_count++;
5655 schedule_work(&adapter->reset_task);
5656}
5657
5658static void e1000_reset_task(struct work_struct *work)
5659{
5660 struct e1000_adapter *adapter;
5661 adapter = container_of(work, struct e1000_adapter, reset_task);
5662
615b32af
JB		 5663 /* don't run the task if already down */
5664 if (test_bit(__E1000_DOWN, &adapter->state))
5665 return;
5666
12d43f7d 5667 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5668 e1000e_dump(adapter);
12d43f7d 5669 e_err("Reset adapter unexpectedly\n");
affa9dfb 5670 }
bc7f75fa
AK		 5671 e1000e_reinit_locked(adapter);
5672}
5673
5674/**
67fd4fcb 5675 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5676 * @netdev: network interface device structure
67fd4fcb 5677 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5678 *
5679 * Returns the address of the device statistics structure.
bc7f75fa 5680 **/
67fd4fcb 5681struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5682 struct rtnl_link_stats64 *stats)
bc7f75fa 5683{
67fd4fcb
JK		 5684 struct e1000_adapter *adapter = netdev_priv(netdev);
5685
5686 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5687 spin_lock(&adapter->stats64_lock);
5688 e1000e_update_stats(adapter);
5689 /* Fill out the OS statistics structure */
5690 stats->rx_bytes = adapter->stats.gorc;
5691 stats->rx_packets = adapter->stats.gprc;
5692 stats->tx_bytes = adapter->stats.gotc;
5693 stats->tx_packets = adapter->stats.gptc;
5694 stats->multicast = adapter->stats.mprc;
5695 stats->collisions = adapter->stats.colc;
5696
5697 /* Rx Errors */
5698
e921eb1a 5699 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5700 * our own version based on RUC and ROC
5701 */
5702 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5703 adapter->stats.crcerrs + adapter->stats.algnerrc +
5704 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5705 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5706 stats->rx_crc_errors = adapter->stats.crcerrs;
5707 stats->rx_frame_errors = adapter->stats.algnerrc;
5708 stats->rx_missed_errors = adapter->stats.mpc;
5709
5710 /* Tx Errors */
f0ff4398 5711 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5712 stats->tx_aborted_errors = adapter->stats.ecol;
5713 stats->tx_window_errors = adapter->stats.latecol;
5714 stats->tx_carrier_errors = adapter->stats.tncrs;
5715
5716 /* Tx Dropped needs to be maintained elsewhere */
5717
5718 spin_unlock(&adapter->stats64_lock);
5719 return stats;
bc7f75fa
AK		 5720}
5721
5722/**
5723 * e1000_change_mtu - Change the Maximum Transfer Unit
5724 * @netdev: network interface device structure
5725 * @new_mtu: new value for maximum frame size
5726 *
5727 * Returns 0 on success, negative on failure
5728 **/
5729static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5730{
5731 struct e1000_adapter *adapter = netdev_priv(netdev);
c751a3d5 5732 int max_frame = new_mtu + VLAN_HLEN + ETH_HLEN + ETH_FCS_LEN;
bc7f75fa 5733
2adc55c9 5734 /* Jumbo frame support */
2e1706f2
BA		 5735 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5736 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5737 e_err("Jumbo Frames not supported.\n");
5738 return -EINVAL;
bc7f75fa
AK		 5739 }
5740
2adc55c9
BA		 5741 /* Supported frame sizes */
5742 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5743 (max_frame > adapter->max_hw_frame_size)) {
5744 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5745 return -EINVAL;
5746 }
5747
2fbe4526
BA		 5748 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5749 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5750 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5751 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5752 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5753 return -EINVAL;
5754 }
5755
bc7f75fa 5756 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5757 usleep_range(1000, 2000);
610c9928 5758 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5759 adapter->max_frame_size = max_frame;
610c9928
BA		 5760 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5761 netdev->mtu = new_mtu;
63eb48f1
DE		 5762
5763 pm_runtime_get_sync(netdev->dev.parent);
5764
bc7f75fa 5765 if (netif_running(netdev))
28002099 5766 e1000e_down(adapter, true);
bc7f75fa 5767
e921eb1a 5768 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5769 * means we reserve 2 more, this pushes us to allocate from the next
5770 * larger slab size.
ad68076e 5771 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5772 * However with the new *_jumbo_rx* routines, jumbo receives will use
5773 * fragmented skbs
ad68076e 5774 */
bc7f75fa 5775
9926146b 5776 if (max_frame <= 2048)
bc7f75fa
AK		 5777 adapter->rx_buffer_len = 2048;
5778 else
5779 adapter->rx_buffer_len = 4096;
5780
5781 /* adjust allocation if LPE protects us, and we aren't using SBP */
5782 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5783 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5784 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5785 + ETH_FCS_LEN;
bc7f75fa 5786
bc7f75fa
AK		 5787 if (netif_running(netdev))
5788 e1000e_up(adapter);
5789 else
5790 e1000e_reset(adapter);
5791
63eb48f1
DE		 5792 pm_runtime_put_sync(netdev->dev.parent);
5793
bc7f75fa
AK		 5794 clear_bit(__E1000_RESETTING, &adapter->state);
5795
5796 return 0;
5797}
5798
5799static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5800 int cmd)
5801{
5802 struct e1000_adapter *adapter = netdev_priv(netdev);
5803 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5804
318a94d6 5805 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5806 return -EOPNOTSUPP;
5807
5808 switch (cmd) {
5809 case SIOCGMIIPHY:
5810 data->phy_id = adapter->hw.phy.addr;
5811 break;
5812 case SIOCGMIIREG:
b16a002e
BA		 5813 e1000_phy_read_status(adapter);
5814
7c25769f
BA		 5815 switch (data->reg_num & 0x1F) {
5816 case MII_BMCR:
5817 data->val_out = adapter->phy_regs.bmcr;
5818 break;
5819 case MII_BMSR:
5820 data->val_out = adapter->phy_regs.bmsr;
5821 break;
5822 case MII_PHYSID1:
5823 data->val_out = (adapter->hw.phy.id >> 16);
5824 break;
5825 case MII_PHYSID2:
5826 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5827 break;
5828 case MII_ADVERTISE:
5829 data->val_out = adapter->phy_regs.advertise;
5830 break;
5831 case MII_LPA:
5832 data->val_out = adapter->phy_regs.lpa;
5833 break;
5834 case MII_EXPANSION:
5835 data->val_out = adapter->phy_regs.expansion;
5836 break;
5837 case MII_CTRL1000:
5838 data->val_out = adapter->phy_regs.ctrl1000;
5839 break;
5840 case MII_STAT1000:
5841 data->val_out = adapter->phy_regs.stat1000;
5842 break;
5843 case MII_ESTATUS:
5844 data->val_out = adapter->phy_regs.estatus;
5845 break;
5846 default:
bc7f75fa
AK		 5847 return -EIO;
5848 }
bc7f75fa
AK		 5849 break;
5850 case SIOCSMIIREG:
5851 default:
5852 return -EOPNOTSUPP;
5853 }
5854 return 0;
5855}
5856
b67e1913
BA		 5857/**
5858 * e1000e_hwtstamp_ioctl - control hardware time stamping
5859 * @netdev: network interface device structure
5860 * @ifreq: interface request
5861 *
5862 * Outgoing time stamping can be enabled and disabled. Play nice and
5863 * disable it when requested, although it shouldn't cause any overhead
5864 * when no packet needs it. At most one packet in the queue may be
5865 * marked for time stamping, otherwise it would be impossible to tell
5866 * for sure to which packet the hardware time stamp belongs.
5867 *
5868 * Incoming time stamping has to be configured via the hardware filters.
5869 * Not all combinations are supported, in particular event type has to be
5870 * specified. Matching the kind of event packet is not supported, with the
5871 * exception of "all V2 events regardless of level 2 or 4".
5872 **/
4e8cff64 5873static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 5874{
5875 struct e1000_adapter *adapter = netdev_priv(netdev);
5876 struct hwtstamp_config config;
5877 int ret_val;
5878
5879 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5880 return -EFAULT;
5881
62d7e3a2 5882 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 5883 if (ret_val)
5884 return ret_val;
5885
d89777bf
BA		 5886 switch (config.rx_filter) {
5887 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5888 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5889 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5890 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5891 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5892 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5893 /* With V2 type filters which specify a Sync or Delay Request,
5894 * Path Delay Request/Response messages are also time stamped
5895 * by hardware so notify the caller the requested packets plus
5896 * some others are time stamped.
5897 */
5898 config.rx_filter = HWTSTAMP_FILTER_SOME;
5899 break;
5900 default:
5901 break;
5902 }
5903
b67e1913
BA		 5904 return copy_to_user(ifr->ifr_data, &config,
5905 sizeof(config)) ? -EFAULT : 0;
5906}
5907
4e8cff64
BH		 5908static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
5909{
5910 struct e1000_adapter *adapter = netdev_priv(netdev);
5911
5912 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
5913 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
5914}
5915
bc7f75fa
AK		 5916static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5917{
5918 switch (cmd) {
5919 case SIOCGMIIPHY:
5920 case SIOCGMIIREG:
5921 case SIOCSMIIREG:
5922 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 5923 case SIOCSHWTSTAMP:
4e8cff64
BH		 5924 return e1000e_hwtstamp_set(netdev, ifr);
5925 case SIOCGHWTSTAMP:
5926 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 5927 default:
5928 return -EOPNOTSUPP;
5929 }
5930}
5931
a4f58f54
BA		 5932static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5933{
5934 struct e1000_hw *hw = &adapter->hw;
74f350ee 5935 u32 i, mac_reg, wuc;
2b6b168d 5936 u16 phy_reg, wuc_enable;
70806a7f 5937 int retval;
a4f58f54
BA		 5938
5939 /* copy MAC RARs to PHY RARs */
d3738bb8 5940 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5941
2b6b168d
BA		 5942 retval = hw->phy.ops.acquire(hw);
5943 if (retval) {
5944 e_err("Could not acquire PHY\n");
5945 return retval;
5946 }
5947
5948 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5949 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5950 if (retval)
75ce1532 5951 goto release;
2b6b168d
BA		 5952
5953 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5954 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5955 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5956 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5957 (u16)(mac_reg & 0xFFFF));
5958 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5959 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5960 }
5961
5962 /* configure PHY Rx Control register */
2b6b168d 5963 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5964 mac_reg = er32(RCTL);
5965 if (mac_reg & E1000_RCTL_UPE)
5966 phy_reg |= BM_RCTL_UPE;
5967 if (mac_reg & E1000_RCTL_MPE)
5968 phy_reg |= BM_RCTL_MPE;
5969 phy_reg &= ~(BM_RCTL_MO_MASK);
5970 if (mac_reg & E1000_RCTL_MO_3)
5971 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5972 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5973 if (mac_reg & E1000_RCTL_BAM)
5974 phy_reg |= BM_RCTL_BAM;
5975 if (mac_reg & E1000_RCTL_PMCF)
5976 phy_reg |= BM_RCTL_PMCF;
5977 mac_reg = er32(CTRL);
5978 if (mac_reg & E1000_CTRL_RFCE)
5979 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5980 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 5981
74f350ee
DE		 5982 wuc = E1000_WUC_PME_EN;
5983 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
5984 wuc |= E1000_WUC_APME;
5985
a4f58f54
BA		 5986 /* enable PHY wakeup in MAC register */
5987 ew32(WUFC, wufc);
74f350ee
DE		 5988 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
5989 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 5990
5991 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 5992 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 5993 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 5994
5995 /* activate PHY wakeup */
2b6b168d
BA		 5996 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5997 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5998 if (retval)
5999 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 6000release:
94d8186a 6001 hw->phy.ops.release(hw);
a4f58f54
BA		 6002
6003 return retval;
6004}
6005
28002099 6006static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 6007{
28002099 6008 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 6009 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 6010
6011 netif_device_detach(netdev);
6012
6013 if (netif_running(netdev)) {
bb9e44d0
BA		 6014 int count = E1000_CHECK_RESET_COUNT;
6015
6016 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6017 usleep_range(10000, 20000);
6018
bc7f75fa 6019 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 6020
6021 /* Quiesce the device without resetting the hardware */
6022 e1000e_down(adapter, false);
bc7f75fa
AK		 6023 e1000_free_irq(adapter);
6024 }
4662e82b 6025 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 6026
28002099
DE		 6027 /* Allow time for pending master requests to run */
6028 e1000e_disable_pcie_master(&adapter->hw);
6029
6030 return 0;
6031}
6032
6033static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6034{
6035 struct net_device *netdev = pci_get_drvdata(pdev);
6036 struct e1000_adapter *adapter = netdev_priv(netdev);
6037 struct e1000_hw *hw = &adapter->hw;
6038 u32 ctrl, ctrl_ext, rctl, status;
6039 /* Runtime suspend should only enable wakeup for link changes */
6040 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6041 int retval = 0;
6042
bc7f75fa
AK		 6043 status = er32(STATUS);
6044 if (status & E1000_STATUS_LU)
6045 wufc &= ~E1000_WUFC_LNKC;
6046
6047 if (wufc) {
6048 e1000_setup_rctl(adapter);
ef9b965a 6049 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 6050
6051 /* turn on all-multi mode if wake on multicast is enabled */
6052 if (wufc & E1000_WUFC_MC) {
6053 rctl = er32(RCTL);
6054 rctl |= E1000_RCTL_MPE;
6055 ew32(RCTL, rctl);
6056 }
6057
6058 ctrl = er32(CTRL);
a4f58f54
BA		 6059 ctrl |= E1000_CTRL_ADVD3WUC;
6060 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6061 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6062 ew32(CTRL, ctrl);
6063
318a94d6
JK		 6064 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6065 adapter->hw.phy.media_type ==
6066 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6067 /* keep the laser running in D3 */
6068 ctrl_ext = er32(CTRL_EXT);
93a23f48 6069 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6070 ew32(CTRL_EXT, ctrl_ext);
6071 }
6072
63eb48f1
DE		 6073 if (!runtime)
6074 e1000e_power_up_phy(adapter);
6075
97ac8cae 6076 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6077 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6078
82776a4b 6079 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6080 /* enable wakeup by the PHY */
6081 retval = e1000_init_phy_wakeup(adapter, wufc);
6082 if (retval)
6083 return retval;
6084 } else {
6085 /* enable wakeup by the MAC */
6086 ew32(WUFC, wufc);
6087 ew32(WUC, E1000_WUC_PME_EN);
6088 }
bc7f75fa
AK		 6089 } else {
6090 ew32(WUC, 0);
6091 ew32(WUFC, 0);
28002099
DE		 6092
6093 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6094 }
6095
74f350ee 6096 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6097 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
74f350ee
DE		 6098 } else if (hw->mac.type == e1000_pch_lpt) {
6099 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6100 /* ULP does not support wake from unicast, multicast
6101 * or broadcast.
6102 */
6103 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6104
6105 if (retval)
6106 return retval;
6107 }
6108
bc7f75fa 6109
e921eb1a 6110 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6111 * would have already happened in close and is redundant.
6112 */
31dbe5b4 6113 e1000e_release_hw_control(adapter);
bc7f75fa 6114
24b41c97
DN		 6115 pci_clear_master(pdev);
6116
e921eb1a 6117 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6118 * correctable error when the MAC transitions from D0 to D3. To
6119 * prevent this we need to mask off the correctable errors on the
6120 * downstream port of the pci-e switch.
e8c254c5
LZ		 6121 *
6122 * We don't have the associated upstream bridge while assigning
6123 * the PCI device into guest. For example, the KVM on power is
6124 * one of the cases.
005cbdfc
AD		 6125 */
6126 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6127 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6128 u16 devctl;
6129
e8c254c5
LZ		 6130 if (!us_dev)
6131 return 0;
6132
f8c0fcac
JL		 6133 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6134 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6135 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6136
66148bab
KK		 6137 pci_save_state(pdev);
6138 pci_prepare_to_sleep(pdev);
005cbdfc 6139
f8c0fcac 6140 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6141 }
66148bab
KK		 6142
6143 return 0;
bc7f75fa
AK		 6144}
6145
13129d9b
CW		 6146/**
6147 * e1000e_disable_aspm - Disable ASPM states
6148 * @pdev: pointer to PCI device struct
6149 * @state: bit-mask of ASPM states to disable
6150 *
6151 * Some devices *must* have certain ASPM states disabled per hardware errata.
6152 **/
6153static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c 6154{
13129d9b
CW		 6155 struct pci_dev *parent = pdev->bus->self;
6156 u16 aspm_dis_mask = 0;
6157 u16 pdev_aspmc, parent_aspmc;
6158
6159 switch (state) {
6160 case PCIE_LINK_STATE_L0S:
6161 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6162 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6163 /* fall-through - can't have L1 without L0s */
6164 case PCIE_LINK_STATE_L1:
6165 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6166 break;
6167 default:
6168 return;
6169 }
6170
6171 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6172 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6173
6174 if (parent) {
6175 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6176 &parent_aspmc);
6177 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6178 }
6179
6180 /* Nothing to do if the ASPM states to be disabled already are */
6181 if (!(pdev_aspmc & aspm_dis_mask) &&
6182 (!parent || !(parent_aspmc & aspm_dis_mask)))
6183 return;
6184
6185 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6186 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6187 "L0s" : "",
6188 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6189 "L1" : "");
6190
6191#ifdef CONFIG_PCIEASPM
9f728f53 6192 pci_disable_link_state_locked(pdev, state);
ffe0b2ff 6193
13129d9b
CW		 6194 /* Double-check ASPM control. If not disabled by the above, the
6195 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6196 * not enabled); override by writing PCI config space directly.
6197 */
6198 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6199 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6200
6201 if (!(aspm_dis_mask & pdev_aspmc))
6202 return;
6203#endif
ffe0b2ff 6204
e921eb1a 6205 /* Both device and parent should have the same ASPM setting.
6f461f6c 6206 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6207 */
13129d9b 6208 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6209
13129d9b
CW		 6210 if (parent)
6211 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6212 aspm_dis_mask);
1eae4eb2
AK		 6213}
6214
aa338601 6215#ifdef CONFIG_PM
23606cf5 6216static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6217{
6218 struct net_device *netdev = pci_get_drvdata(pdev);
6219 struct e1000_adapter *adapter = netdev_priv(netdev);
6220 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6221 u16 aspm_disable_flag = 0;
bc7f75fa 6222
78cd29d5
BA		 6223 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6224 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6225 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6226 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6227 if (aspm_disable_flag)
6228 e1000e_disable_aspm(pdev, aspm_disable_flag);
6229
66148bab 6230 pci_set_master(pdev);
6e4f6f6b 6231
2fbe4526 6232 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6233 e1000_resume_workarounds_pchlan(&adapter->hw);
6234
bc7f75fa 6235 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6236
6237 /* report the system wakeup cause from S3/S4 */
6238 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6239 u16 phy_data;
6240
6241 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6242 if (phy_data) {
6243 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6244 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6245 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6246 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6247 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6248 phy_data & E1000_WUS_LNKC ?
6249 "Link Status Change" : "other");
a4f58f54
BA		 6250 }
6251 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6252 } else {
6253 u32 wus = er32(WUS);
6cf08d1c 6254
a4f58f54
BA		 6255 if (wus) {
6256 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6257 wus & E1000_WUS_EX ? "Unicast Packet" :
6258 wus & E1000_WUS_MC ? "Multicast Packet" :
6259 wus & E1000_WUS_BC ? "Broadcast Packet" :
6260 wus & E1000_WUS_MAG ? "Magic Packet" :
6261 wus & E1000_WUS_LNKC ? "Link Status Change" :
6262 "other");
a4f58f54
BA		 6263 }
6264 ew32(WUS, ~0);
6265 }
6266
bc7f75fa 6267 e1000e_reset(adapter);
bc7f75fa 6268
cd791618 6269 e1000_init_manageability_pt(adapter);
bc7f75fa 6270
e921eb1a 6271 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6272 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6273 * under the control of the driver.
6274 */
c43bc57e 6275 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6276 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6277
6278 return 0;
6279}
23606cf5 6280
3e7986f6 6281#ifdef CONFIG_PM_SLEEP
28002099
DE		 6282static int e1000e_pm_thaw(struct device *dev)
6283{
6284 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6285 struct e1000_adapter *adapter = netdev_priv(netdev);
6286
6287 e1000e_set_interrupt_capability(adapter);
6288 if (netif_running(netdev)) {
6289 u32 err = e1000_request_irq(adapter);
6290
6291 if (err)
6292 return err;
6293
6294 e1000e_up(adapter);
6295 }
6296
6297 netif_device_attach(netdev);
6298
6299 return 0;
6300}
6301
28002099 6302static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6303{
6304 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6305
28002099
DE		 6306 e1000e_pm_freeze(dev);
6307
66148bab 6308 return __e1000_shutdown(pdev, false);
a0340162
RW		 6309}
6310
28002099 6311static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6312{
6313 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6314 int rc;
23606cf5 6315
28002099
DE		 6316 rc = __e1000_resume(pdev);
6317 if (rc)
6318 return rc;
23606cf5 6319
28002099 6320 return e1000e_pm_thaw(dev);
23606cf5 6321}
38a529b5 6322#endif /* CONFIG_PM_SLEEP */
a0340162
RW		 6323
6324#ifdef CONFIG_PM_RUNTIME
63eb48f1 6325static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6326{
6327 struct pci_dev *pdev = to_pci_dev(dev);
6328 struct net_device *netdev = pci_get_drvdata(pdev);
6329 struct e1000_adapter *adapter = netdev_priv(netdev);
6330
63eb48f1
DE		 6331 if (!e1000e_has_link(adapter))
6332 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
a0340162 6333
63eb48f1 6334 return -EBUSY;
a0340162
RW		 6335}
6336
63eb48f1 6337static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6338{
6339 struct pci_dev *pdev = to_pci_dev(dev);
6340 struct net_device *netdev = pci_get_drvdata(pdev);
6341 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6342 int rc;
a0340162 6343
63eb48f1
DE		 6344 rc = __e1000_resume(pdev);
6345 if (rc)
6346 return rc;
a0340162 6347
63eb48f1
DE		 6348 if (netdev->flags & IFF_UP)
6349 rc = e1000e_up(adapter);
a0340162 6350
63eb48f1 6351 return rc;
a0340162 6352}
23606cf5 6353
63eb48f1 6354static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6355{
6356 struct pci_dev *pdev = to_pci_dev(dev);
6357 struct net_device *netdev = pci_get_drvdata(pdev);
6358 struct e1000_adapter *adapter = netdev_priv(netdev);
6359
63eb48f1
DE		 6360 if (netdev->flags & IFF_UP) {
6361 int count = E1000_CHECK_RESET_COUNT;
6362
6363 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6364 usleep_range(10000, 20000);
23606cf5 6365
63eb48f1
DE		 6366 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6367
6368 /* Down the device without resetting the hardware */
6369 e1000e_down(adapter, false);
6370 }
6371
6372 if (__e1000_shutdown(pdev, true)) {
6373 e1000e_pm_runtime_resume(dev);
6374 return -EBUSY;
6375 }
6376
6377 return 0;
23606cf5 6378}
a0340162 6379#endif /* CONFIG_PM_RUNTIME */
aa338601 6380#endif /* CONFIG_PM */
bc7f75fa
AK		 6381
6382static void e1000_shutdown(struct pci_dev *pdev)
6383{
28002099
DE		 6384 e1000e_pm_freeze(&pdev->dev);
6385
66148bab 6386 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6387}
6388
6389#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6390
8bb62869 6391static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6392{
6393 struct net_device *netdev = data;
6394 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6395
6396 if (adapter->msix_entries) {
90da0669
BA		 6397 int vector, msix_irq;
6398
147b2c8c
DD		 6399 vector = 0;
6400 msix_irq = adapter->msix_entries[vector].vector;
6401 disable_irq(msix_irq);
6402 e1000_intr_msix_rx(msix_irq, netdev);
6403 enable_irq(msix_irq);
6404
6405 vector++;
6406 msix_irq = adapter->msix_entries[vector].vector;
6407 disable_irq(msix_irq);
6408 e1000_intr_msix_tx(msix_irq, netdev);
6409 enable_irq(msix_irq);
6410
6411 vector++;
6412 msix_irq = adapter->msix_entries[vector].vector;
6413 disable_irq(msix_irq);
6414 e1000_msix_other(msix_irq, netdev);
6415 enable_irq(msix_irq);
6416 }
6417
6418 return IRQ_HANDLED;
6419}
6420
e921eb1a
BA		 6421/**
6422 * e1000_netpoll
6423 * @netdev: network interface device structure
6424 *
bc7f75fa
AK		 6425 * Polling 'interrupt' - used by things like netconsole to send skbs
6426 * without having to re-enable interrupts. It's not called while
6427 * the interrupt routine is executing.
6428 */
6429static void e1000_netpoll(struct net_device *netdev)
6430{
6431 struct e1000_adapter *adapter = netdev_priv(netdev);
6432
147b2c8c
DD		 6433 switch (adapter->int_mode) {
6434 case E1000E_INT_MODE_MSIX:
6435 e1000_intr_msix(adapter->pdev->irq, netdev);
6436 break;
6437 case E1000E_INT_MODE_MSI:
6438 disable_irq(adapter->pdev->irq);
6439 e1000_intr_msi(adapter->pdev->irq, netdev);
6440 enable_irq(adapter->pdev->irq);
6441 break;
e80bd1d1 6442 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6443 disable_irq(adapter->pdev->irq);
6444 e1000_intr(adapter->pdev->irq, netdev);
6445 enable_irq(adapter->pdev->irq);
6446 break;
6447 }
bc7f75fa
AK		 6448}
6449#endif
6450
6451/**
6452 * e1000_io_error_detected - called when PCI error is detected
6453 * @pdev: Pointer to PCI device
6454 * @state: The current pci connection state
6455 *
6456 * This function is called after a PCI bus error affecting
6457 * this device has been detected.
6458 */
6459static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6460 pci_channel_state_t state)
6461{
6462 struct net_device *netdev = pci_get_drvdata(pdev);
6463 struct e1000_adapter *adapter = netdev_priv(netdev);
6464
6465 netif_device_detach(netdev);
6466
c93b5a76
MM		 6467 if (state == pci_channel_io_perm_failure)
6468 return PCI_ERS_RESULT_DISCONNECT;
6469
bc7f75fa 6470 if (netif_running(netdev))
28002099 6471 e1000e_down(adapter, true);
bc7f75fa
AK		 6472 pci_disable_device(pdev);
6473
6474 /* Request a slot slot reset. */
6475 return PCI_ERS_RESULT_NEED_RESET;
6476}
6477
6478/**
6479 * e1000_io_slot_reset - called after the pci bus has been reset.
6480 * @pdev: Pointer to PCI device
6481 *
6482 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6483 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6484 */
6485static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6486{
6487 struct net_device *netdev = pci_get_drvdata(pdev);
6488 struct e1000_adapter *adapter = netdev_priv(netdev);
6489 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6490 u16 aspm_disable_flag = 0;
6e4f6f6b 6491 int err;
111b9dc5 6492 pci_ers_result_t result;
bc7f75fa 6493
78cd29d5
BA		 6494 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6495 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6496 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6497 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6498 if (aspm_disable_flag)
6499 e1000e_disable_aspm(pdev, aspm_disable_flag);
6500
f0f422e5 6501 err = pci_enable_device_mem(pdev);
6e4f6f6b 6502 if (err) {
bc7f75fa
AK		 6503 dev_err(&pdev->dev,
6504 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6505 result = PCI_ERS_RESULT_DISCONNECT;
6506 } else {
23606cf5 6507 pdev->state_saved = true;
111b9dc5 6508 pci_restore_state(pdev);
66148bab 6509 pci_set_master(pdev);
bc7f75fa 6510
111b9dc5
JB		 6511 pci_enable_wake(pdev, PCI_D3hot, 0);
6512 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6513
111b9dc5
JB		 6514 e1000e_reset(adapter);
6515 ew32(WUS, ~0);
6516 result = PCI_ERS_RESULT_RECOVERED;
6517 }
bc7f75fa 6518
111b9dc5
JB		 6519 pci_cleanup_aer_uncorrect_error_status(pdev);
6520
6521 return result;
bc7f75fa
AK		 6522}
6523
6524/**
6525 * e1000_io_resume - called when traffic can start flowing again.
6526 * @pdev: Pointer to PCI device
6527 *
6528 * This callback is called when the error recovery driver tells us that
6529 * its OK to resume normal operation. Implementation resembles the
28002099 6530 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6531 */
6532static void e1000_io_resume(struct pci_dev *pdev)
6533{
6534 struct net_device *netdev = pci_get_drvdata(pdev);
6535 struct e1000_adapter *adapter = netdev_priv(netdev);
6536
cd791618 6537 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6538
6539 if (netif_running(netdev)) {
6540 if (e1000e_up(adapter)) {
6541 dev_err(&pdev->dev,
6542 "can't bring device back up after reset\n");
6543 return;
6544 }
6545 }
6546
6547 netif_device_attach(netdev);
6548
e921eb1a 6549 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6550 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6551 * under the control of the driver.
6552 */
c43bc57e 6553 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6554 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6555}
6556
6557static void e1000_print_device_info(struct e1000_adapter *adapter)
6558{
6559 struct e1000_hw *hw = &adapter->hw;
6560 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6561 u32 ret_val;
6562 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6563
6564 /* print bus type/speed/width info */
a5cc7642 6565 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6566 /* bus width */
6567 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6568 "Width x1"),
44defeb3 6569 /* MAC address */
7c510e4b 6570 netdev->dev_addr);
44defeb3
JK		 6571 e_info("Intel(R) PRO/%s Network Connection\n",
6572 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6573 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6574 E1000_PBANUM_LENGTH);
6575 if (ret_val)
f2315bf1 6576 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6577 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6578 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6579}
6580
10aa4c04
AK		 6581static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6582{
6583 struct e1000_hw *hw = &adapter->hw;
6584 int ret_val;
6585 u16 buf = 0;
6586
6587 if (hw->mac.type != e1000_82573)
6588 return;
6589
6590 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6591 le16_to_cpus(&buf);
6592 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6593 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6594 dev_warn(&adapter->pdev->dev,
6595 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6596 }
10aa4c04
AK		 6597}
6598
c8f44aff 6599static int e1000_set_features(struct net_device *netdev,
70495a50 6600 netdev_features_t features)
dc221294
BA		 6601{
6602 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6603 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6604
6605 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6606 adapter->flags |= FLAG_TSO_FORCE;
6607
f646968f 6608 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6609 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6610 NETIF_F_RXALL)))
dc221294
BA		 6611 return 0;
6612
0184039a
BG		 6613 if (changed & NETIF_F_RXFCS) {
6614 if (features & NETIF_F_RXFCS) {
6615 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6616 } else {
6617 /* We need to take it back to defaults, which might mean
6618 * stripping is still disabled at the adapter level.
6619 */
6620 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6621 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6622 else
6623 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6624 }
6625 }
6626
70495a50
BA		 6627 netdev->features = features;
6628
dc221294
BA		 6629 if (netif_running(netdev))
6630 e1000e_reinit_locked(adapter);
6631 else
6632 e1000e_reset(adapter);
6633
6634 return 0;
6635}
6636
651c2466
SH		 6637static const struct net_device_ops e1000e_netdev_ops = {
6638 .ndo_open = e1000_open,
6639 .ndo_stop = e1000_close,
00829823 6640 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6641 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6642 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6643 .ndo_set_mac_address = e1000_set_mac,
6644 .ndo_change_mtu = e1000_change_mtu,
6645 .ndo_do_ioctl = e1000_ioctl,
6646 .ndo_tx_timeout = e1000_tx_timeout,
6647 .ndo_validate_addr = eth_validate_addr,
6648
651c2466
SH		 6649 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6650 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6651#ifdef CONFIG_NET_POLL_CONTROLLER
6652 .ndo_poll_controller = e1000_netpoll,
6653#endif
dc221294 6654 .ndo_set_features = e1000_set_features,
651c2466
SH		 6655};
6656
bc7f75fa
AK		 6657/**
6658 * e1000_probe - Device Initialization Routine
6659 * @pdev: PCI device information struct
6660 * @ent: entry in e1000_pci_tbl
6661 *
6662 * Returns 0 on success, negative on failure
6663 *
6664 * e1000_probe initializes an adapter identified by a pci_dev structure.
6665 * The OS initialization, configuring of the adapter private structure,
6666 * and a hardware reset occur.
6667 **/
1dd06ae8 6668static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6669{
6670 struct net_device *netdev;
6671 struct e1000_adapter *adapter;
6672 struct e1000_hw *hw;
6673 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6674 resource_size_t mmio_start, mmio_len;
6675 resource_size_t flash_start, flash_len;
bc7f75fa 6676 static int cards_found;
78cd29d5 6677 u16 aspm_disable_flag = 0;
17e813ec 6678 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6679 u16 eeprom_data = 0;
6680 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6681
78cd29d5
BA		 6682 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6683 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6684 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6685 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6686 if (aspm_disable_flag)
6687 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6688
f0f422e5 6689 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6690 if (err)
6691 return err;
6692
6693 pci_using_dac = 0;
718a39eb 6694 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6695 if (!err) {
718a39eb 6696 pci_using_dac = 1;
bc7f75fa 6697 } else {
718a39eb 6698 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6699 if (err) {
718a39eb
RK		 6700 dev_err(&pdev->dev,
6701 "No usable DMA configuration, aborting\n");
6702 goto err_dma;
bc7f75fa
AK		 6703 }
6704 }
6705
17e813ec
BA		 6706 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6707 err = pci_request_selected_regions_exclusive(pdev, bars,
6708 e1000e_driver_name);
bc7f75fa
AK		 6709 if (err)
6710 goto err_pci_reg;
6711
68eac460 6712 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6713 pci_enable_pcie_error_reporting(pdev);
68eac460 6714
bc7f75fa 6715 pci_set_master(pdev);
438b365a
BA		 6716 /* PCI config space info */
6717 err = pci_save_state(pdev);
6718 if (err)
6719 goto err_alloc_etherdev;
bc7f75fa
AK		 6720
6721 err = -ENOMEM;
6722 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6723 if (!netdev)
6724 goto err_alloc_etherdev;
6725
bc7f75fa
AK		 6726 SET_NETDEV_DEV(netdev, &pdev->dev);
6727
f85e4dfa
TH		 6728 netdev->irq = pdev->irq;
6729
bc7f75fa
AK		 6730 pci_set_drvdata(pdev, netdev);
6731 adapter = netdev_priv(netdev);
6732 hw = &adapter->hw;
6733 adapter->netdev = netdev;
6734 adapter->pdev = pdev;
6735 adapter->ei = ei;
6736 adapter->pba = ei->pba;
6737 adapter->flags = ei->flags;
eb7c3adb 6738 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6739 adapter->hw.adapter = adapter;
6740 adapter->hw.mac.type = ei->mac;
2adc55c9 6741 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6742 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6743
6744 mmio_start = pci_resource_start(pdev, 0);
6745 mmio_len = pci_resource_len(pdev, 0);
6746
6747 err = -EIO;
6748 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6749 if (!adapter->hw.hw_addr)
6750 goto err_ioremap;
6751
6752 if ((adapter->flags & FLAG_HAS_FLASH) &&
6753 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6754 flash_start = pci_resource_start(pdev, 1);
6755 flash_len = pci_resource_len(pdev, 1);
6756 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6757 if (!adapter->hw.flash_address)
6758 goto err_flashmap;
6759 }
6760
d495bcb8
BA		 6761 /* Set default EEE advertisement */
6762 if (adapter->flags2 & FLAG2_HAS_EEE)
6763 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6764
bc7f75fa 6765 /* construct the net_device struct */
e80bd1d1 6766 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6767 e1000e_set_ethtool_ops(netdev);
e80bd1d1 6768 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6769 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6770 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6771
6772 netdev->mem_start = mmio_start;
6773 netdev->mem_end = mmio_start + mmio_len;
6774
6775 adapter->bd_number = cards_found++;
6776
4662e82b
BA		 6777 e1000e_check_options(adapter);
6778
bc7f75fa
AK		 6779 /* setup adapter struct */
6780 err = e1000_sw_init(adapter);
6781 if (err)
6782 goto err_sw_init;
6783
bc7f75fa
AK		 6784 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6785 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6786 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6787
69e3fd8c 6788 err = ei->get_variants(adapter);
bc7f75fa
AK		 6789 if (err)
6790 goto err_hw_init;
6791
4a770358
BA		 6792 if ((adapter->flags & FLAG_IS_ICH) &&
6793 (adapter->flags & FLAG_READ_ONLY_NVM))
6794 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6795
bc7f75fa
AK		 6796 hw->mac.ops.get_bus_info(&adapter->hw);
6797
318a94d6 6798 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6799
6800 /* Copper options */
318a94d6 6801 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6802 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6803 adapter->hw.phy.disable_polarity_correction = 0;
6804 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6805 }
6806
470a5420 6807 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6808 dev_info(&pdev->dev,
6809 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6810
dc221294
BA		 6811 /* Set initial default active device features */
6812 netdev->features = (NETIF_F_SG |
f646968f
PM		 6813 NETIF_F_HW_VLAN_CTAG_RX |
6814 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6815 NETIF_F_TSO |
6816 NETIF_F_TSO6 |
70495a50 6817 NETIF_F_RXHASH |
dc221294
BA		 6818 NETIF_F_RXCSUM |
6819 NETIF_F_HW_CSUM);
6820
6821 /* Set user-changeable features (subset of all device features) */
6822 netdev->hw_features = netdev->features;
0184039a 6823 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6824 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6825 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6826
6827 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6828 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6829
dc221294
BA		 6830 netdev->vlan_features |= (NETIF_F_SG |
6831 NETIF_F_TSO |
6832 NETIF_F_TSO6 |
6833 NETIF_F_HW_CSUM);
a5136e23 6834
ef9b965a
JB		 6835 netdev->priv_flags |= IFF_UNICAST_FLT;
6836
7b872a55 6837 if (pci_using_dac) {
bc7f75fa 6838 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6839 netdev->vlan_features |= NETIF_F_HIGHDMA;
6840 }
bc7f75fa 6841
bc7f75fa
AK		 6842 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6843 adapter->flags |= FLAG_MNG_PT_ENABLED;
6844
e921eb1a 6845 /* before reading the NVM, reset the controller to
ad68076e
BA		 6846 * put the device in a known good starting state
6847 */
bc7f75fa
AK		 6848 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6849
e921eb1a 6850 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6851 * attempt. Let's give it a few tries
6852 */
6853 for (i = 0;; i++) {
6854 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6855 break;
6856 if (i == 2) {
185095fb 6857 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6858 err = -EIO;
6859 goto err_eeprom;
6860 }
6861 }
6862
10aa4c04
AK		 6863 e1000_eeprom_checks(adapter);
6864
608f8a0d 6865 /* copy the MAC address */
bc7f75fa 6866 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6867 dev_err(&pdev->dev,
6868 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6869
6870 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6871
aaeb6cdf 6872 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6873 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6874 netdev->dev_addr);
bc7f75fa
AK		 6875 err = -EIO;
6876 goto err_eeprom;
6877 }
6878
6879 init_timer(&adapter->watchdog_timer);
c061b18d 6880 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6881 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6882
6883 init_timer(&adapter->phy_info_timer);
c061b18d 6884 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6885 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6886
6887 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6888 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6889 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6890 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6891 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6892
bc7f75fa
AK		 6893 /* Initialize link parameters. User can change them with ethtool */
6894 adapter->hw.mac.autoneg = 1;
3db1cd5c 6895 adapter->fc_autoneg = true;
5c48ef3e
BA		 6896 adapter->hw.fc.requested_mode = e1000_fc_default;
6897 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6898 adapter->hw.phy.autoneg_advertised = 0x2f;
6899
e921eb1a 6900 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6901 * the EEPROM, enable the ACPI Magic Packet filter
6902 */
6903 if (adapter->flags & FLAG_APME_IN_WUC) {
6904 /* APME bit in EEPROM is mapped to WUC.APME */
6905 eeprom_data = er32(WUC);
6906 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6907 if ((hw->mac.type > e1000_ich10lan) &&
6908 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6909 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6910 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6911 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6912 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6913 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6914 1, &eeprom_data);
bc7f75fa 6915 else
3d3a1676
BA		 6916 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6917 1, &eeprom_data);
bc7f75fa
AK		 6918 }
6919
6920 /* fetch WoL from EEPROM */
6921 if (eeprom_data & eeprom_apme_mask)
6922 adapter->eeprom_wol |= E1000_WUFC_MAG;
6923
e921eb1a 6924 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6925 * where the eeprom may be wrong or the board simply won't support
6926 * wake on lan on a particular port
6927 */
6928 if (!(adapter->flags & FLAG_HAS_WOL))
6929 adapter->eeprom_wol = 0;
6930
6931 /* initialize the wol settings based on the eeprom settings */
6932 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6933
6934 /* make sure adapter isn't asleep if manageability is enabled */
6935 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6936 (hw->mac.ops.check_mng_mode(hw)))
6937 device_wakeup_enable(&pdev->dev);
bc7f75fa 6938
84527590
BA		 6939 /* save off EEPROM version number */
6940 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6941
bc7f75fa
AK		 6942 /* reset the hardware with the new settings */
6943 e1000e_reset(adapter);
6944
e921eb1a 6945 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6946 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6947 * under the control of the driver.
6948 */
c43bc57e 6949 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6950 e1000e_get_hw_control(adapter);
bc7f75fa 6951
f2315bf1 6952 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6953 err = register_netdev(netdev);
6954 if (err)
6955 goto err_register;
6956
9c563d20
JB		 6957 /* carrier off reporting is important to ethtool even BEFORE open */
6958 netif_carrier_off(netdev);
6959
d89777bf
BA		 6960 /* init PTP hardware clock */
6961 e1000e_ptp_init(adapter);
6962
bc7f75fa
AK		 6963 e1000_print_device_info(adapter);
6964
f3ec4f87
AS		 6965 if (pci_dev_run_wake(pdev))
6966 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6967
bc7f75fa
AK		 6968 return 0;
6969
6970err_register:
c43bc57e 6971 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6972 e1000e_release_hw_control(adapter);
bc7f75fa 6973err_eeprom:
470a5420 6974 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6975 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6976err_hw_init:
bc7f75fa
AK		 6977 kfree(adapter->tx_ring);
6978 kfree(adapter->rx_ring);
6979err_sw_init:
c43bc57e
JB		 6980 if (adapter->hw.flash_address)
6981 iounmap(adapter->hw.flash_address);
e82f54ba 6982 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6983err_flashmap:
bc7f75fa
AK		 6984 iounmap(adapter->hw.hw_addr);
6985err_ioremap:
6986 free_netdev(netdev);
6987err_alloc_etherdev:
f0f422e5 6988 pci_release_selected_regions(pdev,
f0ff4398 6989 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6990err_pci_reg:
6991err_dma:
6992 pci_disable_device(pdev);
6993 return err;
6994}
6995
6996/**
6997 * e1000_remove - Device Removal Routine
6998 * @pdev: PCI device information struct
6999 *
7000 * e1000_remove is called by the PCI subsystem to alert the driver
7001 * that it should release a PCI device. The could be caused by a
7002 * Hot-Plug event, or because the driver is going to be removed from
7003 * memory.
7004 **/
9f9a12f8 7005static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 7006{
7007 struct net_device *netdev = pci_get_drvdata(pdev);
7008 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 7009 bool down = test_bit(__E1000_DOWN, &adapter->state);
7010
d89777bf
BA		 7011 e1000e_ptp_remove(adapter);
7012
e921eb1a 7013 /* The timers may be rescheduled, so explicitly disable them
23f333a2 7014 * from being rescheduled.
ad68076e 7015 */
23606cf5
RW		 7016 if (!down)
7017 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 7018 del_timer_sync(&adapter->watchdog_timer);
7019 del_timer_sync(&adapter->phy_info_timer);
7020
41cec6f1
BA		 7021 cancel_work_sync(&adapter->reset_task);
7022 cancel_work_sync(&adapter->watchdog_task);
7023 cancel_work_sync(&adapter->downshift_task);
7024 cancel_work_sync(&adapter->update_phy_task);
7025 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 7026
b67e1913
BA		 7027 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7028 cancel_work_sync(&adapter->tx_hwtstamp_work);
7029 if (adapter->tx_hwtstamp_skb) {
7030 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7031 adapter->tx_hwtstamp_skb = NULL;
7032 }
7033 }
7034
23606cf5
RW		 7035 /* Don't lie to e1000_close() down the road. */
7036 if (!down)
7037 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 7038 unregister_netdev(netdev);
7039
f3ec4f87
AS		 7040 if (pci_dev_run_wake(pdev))
7041 pm_runtime_get_noresume(&pdev->dev);
23606cf5 7042
e921eb1a 7043 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 7044 * would have already happened in close and is redundant.
7045 */
31dbe5b4 7046 e1000e_release_hw_control(adapter);
bc7f75fa 7047
4662e82b 7048 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 7049 kfree(adapter->tx_ring);
7050 kfree(adapter->rx_ring);
7051
7052 iounmap(adapter->hw.hw_addr);
7053 if (adapter->hw.flash_address)
7054 iounmap(adapter->hw.flash_address);
f0f422e5 7055 pci_release_selected_regions(pdev,
f0ff4398 7056 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 7057
7058 free_netdev(netdev);
7059
111b9dc5 7060 /* AER disable */
19d5afd4 7061 pci_disable_pcie_error_reporting(pdev);
111b9dc5 7062
bc7f75fa
AK		 7063 pci_disable_device(pdev);
7064}
7065
7066/* PCI Error Recovery (ERS) */
3646f0e5 7067static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7068 .error_detected = e1000_io_error_detected,
7069 .slot_reset = e1000_io_slot_reset,
7070 .resume = e1000_io_resume,
7071};
7072
0e8e842b 7073static const struct pci_device_id e1000_pci_tbl[] = {
bc7f75fa
AK		 7074 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7075 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7076 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7077 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7078 board_82571 },
bc7f75fa
AK		 7079 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7080 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7081 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7082 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7083 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7084
bc7f75fa
AK		 7085 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7086 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7087 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7088 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7089
bc7f75fa
AK		 7090 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7091 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7092 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7093
4662e82b 7094 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7095 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7096 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7097
bc7f75fa
AK		 7098 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7099 board_80003es2lan },
7100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7101 board_80003es2lan },
7102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7103 board_80003es2lan },
7104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7105 board_80003es2lan },
ad68076e 7106
bc7f75fa
AK		 7107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7114 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7115
bc7f75fa
AK		 7116 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7117 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7118 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7119 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7120 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7121 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7122 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7123 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7124 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7125
7126 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7127 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7128 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7129
f4187b56
BA		 7130 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7131 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7132 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7133
a4f58f54
BA		 7134 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7135 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7136 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7137 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7138
d3738bb8
BA		 7139 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7140 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7141
2fbe4526
BA		 7142 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7143 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7144 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7145 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7146 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7147 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7148 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7149 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
2fbe4526 7150
f36bb6ca 7151 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7152};
7153MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7154
23606cf5 7155static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7156#ifdef CONFIG_PM_SLEEP
28002099
DE		 7157 .suspend = e1000e_pm_suspend,
7158 .resume = e1000e_pm_resume,
7159 .freeze = e1000e_pm_freeze,
7160 .thaw = e1000e_pm_thaw,
7161 .poweroff = e1000e_pm_suspend,
7162 .restore = e1000e_pm_resume,
72f72dcc 7163#endif
63eb48f1
DE		 7164 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7165 e1000e_pm_runtime_idle)
23606cf5
RW		 7166};
7167
bc7f75fa
AK		 7168/* PCI Device API Driver */
7169static struct pci_driver e1000_driver = {
7170 .name = e1000e_driver_name,
7171 .id_table = e1000_pci_tbl,
7172 .probe = e1000_probe,
9f9a12f8 7173 .remove = e1000_remove,
f36bb6ca
BA		 7174 .driver = {
7175 .pm = &e1000_pm_ops,
7176 },
bc7f75fa
AK		 7177 .shutdown = e1000_shutdown,
7178 .err_handler = &e1000_err_handler
7179};
7180
7181/**
7182 * e1000_init_module - Driver Registration Routine
7183 *
7184 * e1000_init_module is the first routine called when the driver is
7185 * loaded. All it does is register with the PCI subsystem.
7186 **/
7187static int __init e1000_init_module(void)
7188{
7189 int ret;
6cf08d1c 7190
8544b9f7
BA		 7191 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7192 e1000e_driver_version);
e78b80b1 7193 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n");
bc7f75fa 7194 ret = pci_register_driver(&e1000_driver);
53ec5498 7195
bc7f75fa
AK		 7196 return ret;
7197}
7198module_init(e1000_init_module);
7199
7200/**
7201 * e1000_exit_module - Driver Exit Cleanup Routine
7202 *
7203 * e1000_exit_module is called just before the driver is removed
7204 * from memory.
7205 **/
7206static void __exit e1000_exit_module(void)
7207{
7208 pci_unregister_driver(&e1000_driver);
7209}
7210module_exit(e1000_exit_module);
7211
bc7f75fa
AK		 7212MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7213MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7214MODULE_LICENSE("GPL");
7215MODULE_VERSION(DRV_VERSION);
7216
06c24b91 7217/* netdev.c */
Linux kernel - Deliverables
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