projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
e1000e: 82579 packet drop workaround
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
fad59b0d 59#define DRV_VERSION "1.10.6" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
af667a29
BA		 89#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
90#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
91#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
92#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
93#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
94
95#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
96#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
97#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
98#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
99#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 100
101static const struct e1000_reg_info e1000_reg_info_tbl[] = {
102
103 /* General Registers */
104 {E1000_CTRL, "CTRL"},
105 {E1000_STATUS, "STATUS"},
106 {E1000_CTRL_EXT, "CTRL_EXT"},
107
108 /* Interrupt Registers */
109 {E1000_ICR, "ICR"},
110
af667a29 111 /* Rx Registers */
84f4ee90 112 {E1000_RCTL, "RCTL"},
1e36052e
BA		 113 {E1000_RDLEN(0), "RDLEN"},
114 {E1000_RDH(0), "RDH"},
115 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 116 {E1000_RDTR, "RDTR"},
117 {E1000_RXDCTL(0), "RXDCTL"},
118 {E1000_ERT, "ERT"},
1e36052e
BA		 119 {E1000_RDBAL(0), "RDBAL"},
120 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 121 {E1000_RDFH, "RDFH"},
122 {E1000_RDFT, "RDFT"},
123 {E1000_RDFHS, "RDFHS"},
124 {E1000_RDFTS, "RDFTS"},
125 {E1000_RDFPC, "RDFPC"},
126
af667a29 127 /* Tx Registers */
84f4ee90 128 {E1000_TCTL, "TCTL"},
1e36052e
BA		 129 {E1000_TDBAL(0), "TDBAL"},
130 {E1000_TDBAH(0), "TDBAH"},
131 {E1000_TDLEN(0), "TDLEN"},
132 {E1000_TDH(0), "TDH"},
133 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 134 {E1000_TIDV, "TIDV"},
135 {E1000_TXDCTL(0), "TXDCTL"},
136 {E1000_TADV, "TADV"},
137 {E1000_TARC(0), "TARC"},
138 {E1000_TDFH, "TDFH"},
139 {E1000_TDFT, "TDFT"},
140 {E1000_TDFHS, "TDFHS"},
141 {E1000_TDFTS, "TDFTS"},
142 {E1000_TDFPC, "TDFPC"},
143
144 /* List Terminator */
f36bb6ca 145 {0, NULL}
84f4ee90
TI		 146};
147
148/*
149 * e1000_regdump - register printout routine
150 */
151static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
152{
153 int n = 0;
154 char rname[16];
155 u32 regs[8];
156
157 switch (reginfo->ofs) {
158 case E1000_RXDCTL(0):
159 for (n = 0; n < 2; n++)
160 regs[n] = __er32(hw, E1000_RXDCTL(n));
161 break;
162 case E1000_TXDCTL(0):
163 for (n = 0; n < 2; n++)
164 regs[n] = __er32(hw, E1000_TXDCTL(n));
165 break;
166 case E1000_TARC(0):
167 for (n = 0; n < 2; n++)
168 regs[n] = __er32(hw, E1000_TARC(n));
169 break;
170 default:
ef456f85
JK		 171 pr_info("%-15s %08x\n",
172 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 173 return;
174 }
175
176 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 177 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 178}
179
84f4ee90 180/*
af667a29 181 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 182 */
183static void e1000e_dump(struct e1000_adapter *adapter)
184{
185 struct net_device *netdev = adapter->netdev;
186 struct e1000_hw *hw = &adapter->hw;
187 struct e1000_reg_info *reginfo;
188 struct e1000_ring *tx_ring = adapter->tx_ring;
189 struct e1000_tx_desc *tx_desc;
af667a29 190 struct my_u0 {
e885d762
BA		 191 __le64 a;
192 __le64 b;
af667a29 193 } *u0;
84f4ee90
TI		 194 struct e1000_buffer *buffer_info;
195 struct e1000_ring *rx_ring = adapter->rx_ring;
196 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 197 union e1000_rx_desc_extended *rx_desc;
af667a29 198 struct my_u1 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
201 __le64 c;
202 __le64 d;
af667a29 203 } *u1;
84f4ee90
TI		 204 u32 staterr;
205 int i = 0;
206
207 if (!netif_msg_hw(adapter))
208 return;
209
210 /* Print netdevice Info */
211 if (netdev) {
212 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 213 pr_info("Device Name state trans_start last_rx\n");
214 pr_info("%-15s %016lX %016lX %016lX\n",
215 netdev->name, netdev->state, netdev->trans_start,
216 netdev->last_rx);
84f4ee90
TI		 217 }
218
219 /* Print Registers */
220 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 221 pr_info(" Register Name Value\n");
84f4ee90
TI		 222 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
223 reginfo->name; reginfo++) {
224 e1000_regdump(hw, reginfo);
225 }
226
af667a29 227 /* Print Tx Ring Summary */
84f4ee90 228 if (!netdev || !netif_running(netdev))
fe1e980f 229 return;
84f4ee90 230
af667a29 231 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 232 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 233 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 234 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
235 0, tx_ring->next_to_use, tx_ring->next_to_clean,
236 (unsigned long long)buffer_info->dma,
237 buffer_info->length,
238 buffer_info->next_to_watch,
239 (unsigned long long)buffer_info->time_stamp);
84f4ee90 240
af667a29 241 /* Print Tx Ring */
84f4ee90
TI		 242 if (!netif_msg_tx_done(adapter))
243 goto rx_ring_summary;
244
af667a29 245 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 246
247 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
248 *
249 * Legacy Transmit Descriptor
250 * +--------------------------------------------------------------+
251 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
252 * +--------------------------------------------------------------+
253 * 8 | Special | CSS | Status | CMD | CSO | Length |
254 * +--------------------------------------------------------------+
255 * 63 48 47 36 35 32 31 24 23 16 15 0
256 *
257 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
258 * 63 48 47 40 39 32 31 16 15 8 7 0
259 * +----------------------------------------------------------------+
260 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
261 * +----------------------------------------------------------------+
262 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
263 * +----------------------------------------------------------------+
264 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
265 *
266 * Extended Data Descriptor (DTYP=0x1)
267 * +----------------------------------------------------------------+
268 * 0 | Buffer Address [63:0] |
269 * +----------------------------------------------------------------+
270 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 */
ef456f85
JK		 274 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
275 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
276 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 277 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 278 const char *next_desc;
84f4ee90
TI		 279 tx_desc = E1000_TX_DESC(*tx_ring, i);
280 buffer_info = &tx_ring->buffer_info[i];
281 u0 = (struct my_u0 *)tx_desc;
84f4ee90 282 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 283 next_desc = " NTC/U";
84f4ee90 284 else if (i == tx_ring->next_to_use)
ef456f85 285 next_desc = " NTU";
84f4ee90 286 else if (i == tx_ring->next_to_clean)
ef456f85 287 next_desc = " NTC";
84f4ee90 288 else
ef456f85
JK		 289 next_desc = "";
290 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
291 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
292 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
293 i,
294 (unsigned long long)le64_to_cpu(u0->a),
295 (unsigned long long)le64_to_cpu(u0->b),
296 (unsigned long long)buffer_info->dma,
297 buffer_info->length, buffer_info->next_to_watch,
298 (unsigned long long)buffer_info->time_stamp,
299 buffer_info->skb, next_desc);
84f4ee90
TI		 300
301 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
302 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 303 16, 1, phys_to_virt(buffer_info->dma),
304 buffer_info->length, true);
84f4ee90
TI		 305 }
306
af667a29 307 /* Print Rx Ring Summary */
84f4ee90 308rx_ring_summary:
af667a29 309 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 310 pr_info("Queue [NTU] [NTC]\n");
311 pr_info(" %5d %5X %5X\n",
312 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 313
af667a29 314 /* Print Rx Ring */
84f4ee90 315 if (!netif_msg_rx_status(adapter))
fe1e980f 316 return;
84f4ee90 317
af667a29 318 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 319 switch (adapter->rx_ps_pages) {
320 case 1:
321 case 2:
322 case 3:
323 /* [Extended] Packet Split Receive Descriptor Format
324 *
325 * +-----------------------------------------------------+
326 * 0 | Buffer Address 0 [63:0] |
327 * +-----------------------------------------------------+
328 * 8 | Buffer Address 1 [63:0] |
329 * +-----------------------------------------------------+
330 * 16 | Buffer Address 2 [63:0] |
331 * +-----------------------------------------------------+
332 * 24 | Buffer Address 3 [63:0] |
333 * +-----------------------------------------------------+
334 */
ef456f85 335 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 336 /* [Extended] Receive Descriptor (Write-Back) Format
337 *
338 * 63 48 47 32 31 13 12 8 7 4 3 0
339 * +------------------------------------------------------+
340 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
341 * | Checksum | Ident | | Queue | | Type |
342 * +------------------------------------------------------+
343 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
344 * +------------------------------------------------------+
345 * 63 48 47 32 31 20 19 0
346 */
ef456f85 347 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 348 for (i = 0; i < rx_ring->count; i++) {
ef456f85 349 const char *next_desc;
84f4ee90
TI		 350 buffer_info = &rx_ring->buffer_info[i];
351 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
352 u1 = (struct my_u1 *)rx_desc_ps;
353 staterr =
af667a29 354 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 355
356 if (i == rx_ring->next_to_use)
357 next_desc = " NTU";
358 else if (i == rx_ring->next_to_clean)
359 next_desc = " NTC";
360 else
361 next_desc = "";
362
84f4ee90
TI		 363 if (staterr & E1000_RXD_STAT_DD) {
364 /* Descriptor Done */
ef456f85
JK		 365 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
366 "RWB", i,
367 (unsigned long long)le64_to_cpu(u1->a),
368 (unsigned long long)le64_to_cpu(u1->b),
369 (unsigned long long)le64_to_cpu(u1->c),
370 (unsigned long long)le64_to_cpu(u1->d),
371 buffer_info->skb, next_desc);
84f4ee90 372 } else {
ef456f85
JK		 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
374 "R ", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 (unsigned long long)buffer_info->dma,
380 buffer_info->skb, next_desc);
84f4ee90
TI		 381
382 if (netif_msg_pktdata(adapter))
383 print_hex_dump(KERN_INFO, "",
384 DUMP_PREFIX_ADDRESS, 16, 1,
385 phys_to_virt(buffer_info->dma),
386 adapter->rx_ps_bsize0, true);
387 }
84f4ee90
TI		 388 }
389 break;
390 default:
391 case 0:
5f450212 392 /* Extended Receive Descriptor (Read) Format
84f4ee90 393 *
5f450212
BA		 394 * +-----------------------------------------------------+
395 * 0 | Buffer Address [63:0] |
396 * +-----------------------------------------------------+
397 * 8 | Reserved |
398 * +-----------------------------------------------------+
84f4ee90 399 */
ef456f85 400 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 401 /* Extended Receive Descriptor (Write-Back) Format
402 *
403 * 63 48 47 32 31 24 23 4 3 0
404 * +------------------------------------------------------+
405 * | RSS Hash | | | |
406 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
407 * | Packet | IP | | | Type |
408 * | Checksum | Ident | | | |
409 * +------------------------------------------------------+
410 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
411 * +------------------------------------------------------+
412 * 63 48 47 32 31 20 19 0
413 */
ef456f85 414 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 415
416 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 417 const char *next_desc;
418
84f4ee90 419 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 420 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
421 u1 = (struct my_u1 *)rx_desc;
422 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 423
424 if (i == rx_ring->next_to_use)
425 next_desc = " NTU";
426 else if (i == rx_ring->next_to_clean)
427 next_desc = " NTC";
428 else
429 next_desc = "";
430
5f450212
BA		 431 if (staterr & E1000_RXD_STAT_DD) {
432 /* Descriptor Done */
ef456f85
JK		 433 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
434 "RWB", i,
435 (unsigned long long)le64_to_cpu(u1->a),
436 (unsigned long long)le64_to_cpu(u1->b),
437 buffer_info->skb, next_desc);
5f450212 438 } else {
ef456f85
JK		 439 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
440 "R ", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 (unsigned long long)buffer_info->dma,
444 buffer_info->skb, next_desc);
5f450212
BA		 445
446 if (netif_msg_pktdata(adapter))
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16,
449 1,
450 phys_to_virt
451 (buffer_info->dma),
452 adapter->rx_buffer_len,
453 true);
454 }
84f4ee90
TI		 455 }
456 }
84f4ee90
TI		 457}
458
bc7f75fa
AK		 459/**
460 * e1000_desc_unused - calculate if we have unused descriptors
461 **/
462static int e1000_desc_unused(struct e1000_ring *ring)
463{
464 if (ring->next_to_clean > ring->next_to_use)
465 return ring->next_to_clean - ring->next_to_use - 1;
466
467 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
468}
469
470/**
ad68076e 471 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 472 * @adapter: board private structure
473 * @status: descriptor status field as written by hardware
474 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
475 * @skb: pointer to sk_buff to be indicated to stack
476 **/
477static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 478 struct net_device *netdev, struct sk_buff *skb,
a39fe742 479 u8 status, __le16 vlan)
bc7f75fa 480{
86d70e53 481 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 482 skb->protocol = eth_type_trans(skb, netdev);
483
86d70e53
JK		 484 if (status & E1000_RXD_STAT_VP)
485 __vlan_hwaccel_put_tag(skb, tag);
486
487 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 488}
489
490/**
af667a29 491 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 492 * @adapter: board private structure
493 * @status_err: receive descriptor status and error fields
494 * @csum: receive descriptor csum field
495 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 496 **/
497static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 498 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 499{
500 u16 status = (u16)status_err;
501 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 502
503 skb_checksum_none_assert(skb);
bc7f75fa 504
afd12939
BA		 505 /* Rx checksum disabled */
506 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
507 return;
508
bc7f75fa
AK		 509 /* Ignore Checksum bit is set */
510 if (status & E1000_RXD_STAT_IXSM)
511 return;
afd12939 512
bc7f75fa
AK		 513 /* TCP/UDP checksum error bit is set */
514 if (errors & E1000_RXD_ERR_TCPE) {
515 /* let the stack verify checksum errors */
516 adapter->hw_csum_err++;
517 return;
518 }
519
520 /* TCP/UDP Checksum has not been calculated */
521 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
522 return;
523
524 /* It must be a TCP or UDP packet with a valid checksum */
525 if (status & E1000_RXD_STAT_TCPCS) {
526 /* TCP checksum is good */
527 skb->ip_summed = CHECKSUM_UNNECESSARY;
528 } else {
ad68076e
BA		 529 /*
530 * IP fragment with UDP payload
531 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 532 * and then put the value in host order for further stack use.
533 */
afd12939 534 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 535 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 536 skb->ip_summed = CHECKSUM_COMPLETE;
537 }
538 adapter->hw_csum_good++;
539}
540
c6e7f51e
BA		 541/**
542 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
543 * @hw: pointer to the HW structure
544 * @tail: address of tail descriptor register
545 * @i: value to write to tail descriptor register
546 *
547 * When updating the tail register, the ME could be accessing Host CSR
548 * registers at the same time. Normally, this is handled in h/w by an
549 * arbiter but on some parts there is a bug that acknowledges Host accesses
550 * later than it should which could result in the descriptor register to
551 * have an incorrect value. Workaround this by checking the FWSM register
552 * which has bit 24 set while ME is accessing Host CSR registers, wait
553 * if it is set and try again a number of times.
554 **/
c5083cf6 555static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 556 unsigned int i)
557{
558 unsigned int j = 0;
559
560 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
561 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
562 udelay(50);
563
564 writel(i, tail);
565
566 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
567 return E1000_ERR_SWFW_SYNC;
568
569 return 0;
570}
571
55aa6985 572static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 573{
55aa6985 574 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 575 struct e1000_hw *hw = &adapter->hw;
576
55aa6985 577 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 578 u32 rctl = er32(RCTL);
579 ew32(RCTL, rctl & ~E1000_RCTL_EN);
580 e_err("ME firmware caused invalid RDT - resetting\n");
581 schedule_work(&adapter->reset_task);
582 }
583}
584
55aa6985 585static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 586{
55aa6985 587 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 588 struct e1000_hw *hw = &adapter->hw;
589
55aa6985 590 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 591 u32 tctl = er32(TCTL);
592 ew32(TCTL, tctl & ~E1000_TCTL_EN);
593 e_err("ME firmware caused invalid TDT - resetting\n");
594 schedule_work(&adapter->reset_task);
595 }
596}
597
bc7f75fa 598/**
5f450212 599 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 600 * @rx_ring: Rx descriptor ring
bc7f75fa 601 **/
55aa6985 602static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 603 int cleaned_count, gfp_t gfp)
bc7f75fa 604{
55aa6985 605 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 606 struct net_device *netdev = adapter->netdev;
607 struct pci_dev *pdev = adapter->pdev;
5f450212 608 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 609 struct e1000_buffer *buffer_info;
610 struct sk_buff *skb;
611 unsigned int i;
89d71a66 612 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 613
614 i = rx_ring->next_to_use;
615 buffer_info = &rx_ring->buffer_info[i];
616
617 while (cleaned_count--) {
618 skb = buffer_info->skb;
619 if (skb) {
620 skb_trim(skb, 0);
621 goto map_skb;
622 }
623
c2fed996 624 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 625 if (!skb) {
626 /* Better luck next round */
627 adapter->alloc_rx_buff_failed++;
628 break;
629 }
630
bc7f75fa
AK		 631 buffer_info->skb = skb;
632map_skb:
0be3f55f 633 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 634 adapter->rx_buffer_len,
0be3f55f
NN		 635 DMA_FROM_DEVICE);
636 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 637 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 638 adapter->rx_dma_failed++;
639 break;
640 }
641
5f450212
BA		 642 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
643 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 644
50849d79
TH		 645 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
646 /*
647 * Force memory writes to complete before letting h/w
648 * know there are new descriptors to fetch. (Only
649 * applicable for weak-ordered memory model archs,
650 * such as IA-64).
651 */
652 wmb();
c6e7f51e 653 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 654 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 655 else
c5083cf6 656 writel(i, rx_ring->tail);
50849d79 657 }
bc7f75fa
AK		 658 i++;
659 if (i == rx_ring->count)
660 i = 0;
661 buffer_info = &rx_ring->buffer_info[i];
662 }
663
50849d79 664 rx_ring->next_to_use = i;
bc7f75fa
AK		 665}
666
667/**
668 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 669 * @rx_ring: Rx descriptor ring
bc7f75fa 670 **/
55aa6985 671static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 672 int cleaned_count, gfp_t gfp)
bc7f75fa 673{
55aa6985 674 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 675 struct net_device *netdev = adapter->netdev;
676 struct pci_dev *pdev = adapter->pdev;
677 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 678 struct e1000_buffer *buffer_info;
679 struct e1000_ps_page *ps_page;
680 struct sk_buff *skb;
681 unsigned int i, j;
682
683 i = rx_ring->next_to_use;
684 buffer_info = &rx_ring->buffer_info[i];
685
686 while (cleaned_count--) {
687 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
688
689 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 690 ps_page = &buffer_info->ps_pages[j];
691 if (j >= adapter->rx_ps_pages) {
692 /* all unused desc entries get hw null ptr */
af667a29
BA		 693 rx_desc->read.buffer_addr[j + 1] =
694 ~cpu_to_le64(0);
47f44e40
AK		 695 continue;
696 }
697 if (!ps_page->page) {
c2fed996 698 ps_page->page = alloc_page(gfp);
bc7f75fa 699 if (!ps_page->page) {
47f44e40
AK		 700 adapter->alloc_rx_buff_failed++;
701 goto no_buffers;
702 }
0be3f55f
NN		 703 ps_page->dma = dma_map_page(&pdev->dev,
704 ps_page->page,
705 0, PAGE_SIZE,
706 DMA_FROM_DEVICE);
707 if (dma_mapping_error(&pdev->dev,
708 ps_page->dma)) {
47f44e40 709 dev_err(&adapter->pdev->dev,
af667a29 710 "Rx DMA page map failed\n");
47f44e40
AK		 711 adapter->rx_dma_failed++;
712 goto no_buffers;
bc7f75fa 713 }
bc7f75fa 714 }
47f44e40
AK		 715 /*
716 * Refresh the desc even if buffer_addrs
717 * didn't change because each write-back
718 * erases this info.
719 */
af667a29
BA		 720 rx_desc->read.buffer_addr[j + 1] =
721 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 722 }
723
c2fed996
JK		 724 skb = __netdev_alloc_skb_ip_align(netdev,
725 adapter->rx_ps_bsize0,
726 gfp);
bc7f75fa
AK		 727
728 if (!skb) {
729 adapter->alloc_rx_buff_failed++;
730 break;
731 }
732
bc7f75fa 733 buffer_info->skb = skb;
0be3f55f 734 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 735 adapter->rx_ps_bsize0,
0be3f55f
NN		 736 DMA_FROM_DEVICE);
737 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 738 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 739 adapter->rx_dma_failed++;
740 /* cleanup skb */
741 dev_kfree_skb_any(skb);
742 buffer_info->skb = NULL;
743 break;
744 }
745
746 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
747
50849d79
TH		 748 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
749 /*
750 * Force memory writes to complete before letting h/w
751 * know there are new descriptors to fetch. (Only
752 * applicable for weak-ordered memory model archs,
753 * such as IA-64).
754 */
755 wmb();
c6e7f51e 756 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 757 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 758 else
c5083cf6 759 writel(i << 1, rx_ring->tail);
50849d79
TH		 760 }
761
bc7f75fa
AK		 762 i++;
763 if (i == rx_ring->count)
764 i = 0;
765 buffer_info = &rx_ring->buffer_info[i];
766 }
767
768no_buffers:
50849d79 769 rx_ring->next_to_use = i;
bc7f75fa
AK		 770}
771
97ac8cae
BA		 772/**
773 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 774 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 775 * @cleaned_count: number of buffers to allocate this pass
776 **/
777
55aa6985 778static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 779 int cleaned_count, gfp_t gfp)
97ac8cae 780{
55aa6985 781 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 782 struct net_device *netdev = adapter->netdev;
783 struct pci_dev *pdev = adapter->pdev;
5f450212 784 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 785 struct e1000_buffer *buffer_info;
786 struct sk_buff *skb;
787 unsigned int i;
89d71a66 788 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 789
790 i = rx_ring->next_to_use;
791 buffer_info = &rx_ring->buffer_info[i];
792
793 while (cleaned_count--) {
794 skb = buffer_info->skb;
795 if (skb) {
796 skb_trim(skb, 0);
797 goto check_page;
798 }
799
c2fed996 800 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 801 if (unlikely(!skb)) {
802 /* Better luck next round */
803 adapter->alloc_rx_buff_failed++;
804 break;
805 }
806
97ac8cae
BA		 807 buffer_info->skb = skb;
808check_page:
809 /* allocate a new page if necessary */
810 if (!buffer_info->page) {
c2fed996 811 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 812 if (unlikely(!buffer_info->page)) {
813 adapter->alloc_rx_buff_failed++;
814 break;
815 }
816 }
817
818 if (!buffer_info->dma)
0be3f55f 819 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 820 buffer_info->page, 0,
821 PAGE_SIZE,
0be3f55f 822 DMA_FROM_DEVICE);
97ac8cae 823
5f450212
BA		 824 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
825 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 826
827 if (unlikely(++i == rx_ring->count))
828 i = 0;
829 buffer_info = &rx_ring->buffer_info[i];
830 }
831
832 if (likely(rx_ring->next_to_use != i)) {
833 rx_ring->next_to_use = i;
834 if (unlikely(i-- == 0))
835 i = (rx_ring->count - 1);
836
837 /* Force memory writes to complete before letting h/w
838 * know there are new descriptors to fetch. (Only
839 * applicable for weak-ordered memory model archs,
840 * such as IA-64). */
841 wmb();
c6e7f51e 842 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 843 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 844 else
c5083cf6 845 writel(i, rx_ring->tail);
97ac8cae
BA		 846 }
847}
848
70495a50
BA		 849static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
850 struct sk_buff *skb)
851{
852 if (netdev->features & NETIF_F_RXHASH)
853 skb->rxhash = le32_to_cpu(rss);
854}
855
bc7f75fa 856/**
55aa6985
BA		 857 * e1000_clean_rx_irq - Send received data up the network stack
858 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 859 *
860 * the return value indicates whether actual cleaning was done, there
861 * is no guarantee that everything was cleaned
862 **/
55aa6985
BA		 863static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
864 int work_to_do)
bc7f75fa 865{
55aa6985 866 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 867 struct net_device *netdev = adapter->netdev;
868 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 869 struct e1000_hw *hw = &adapter->hw;
5f450212 870 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 871 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 872 u32 length, staterr;
bc7f75fa
AK		 873 unsigned int i;
874 int cleaned_count = 0;
3db1cd5c 875 bool cleaned = false;
bc7f75fa
AK		 876 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
877
878 i = rx_ring->next_to_clean;
5f450212
BA		 879 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
880 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 881 buffer_info = &rx_ring->buffer_info[i];
882
5f450212 883 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 884 struct sk_buff *skb;
bc7f75fa
AK		 885
886 if (*work_done >= work_to_do)
887 break;
888 (*work_done)++;
2d0bb1c1 889 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 890
bc7f75fa
AK		 891 skb = buffer_info->skb;
892 buffer_info->skb = NULL;
893
894 prefetch(skb->data - NET_IP_ALIGN);
895
896 i++;
897 if (i == rx_ring->count)
898 i = 0;
5f450212 899 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 900 prefetch(next_rxd);
901
902 next_buffer = &rx_ring->buffer_info[i];
903
3db1cd5c 904 cleaned = true;
bc7f75fa 905 cleaned_count++;
0be3f55f 906 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 907 buffer_info->dma,
908 adapter->rx_buffer_len,
0be3f55f 909 DMA_FROM_DEVICE);
bc7f75fa
AK		 910 buffer_info->dma = 0;
911
5f450212 912 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 913
b94b5028
JB		 914 /*
915 * !EOP means multiple descriptors were used to store a single
916 * packet, if that's the case we need to toss it. In fact, we
917 * need to toss every packet with the EOP bit clear and the
918 * next frame that _does_ have the EOP bit set, as it is by
919 * definition only a frame fragment
920 */
5f450212 921 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 922 adapter->flags2 |= FLAG2_IS_DISCARDING;
923
924 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 925 /* All receives must fit into a single buffer */
3bb99fe2 926 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 927 /* recycle */
928 buffer_info->skb = skb;
5f450212 929 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 930 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 931 goto next_desc;
932 }
933
cf955e6c
BG		 934 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
935 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 936 /* recycle */
937 buffer_info->skb = skb;
938 goto next_desc;
939 }
940
eb7c3adb 941 /* adjust length to remove Ethernet CRC */
0184039a
BG		 942 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
943 /* If configured to store CRC, don't subtract FCS,
944 * but keep the FCS bytes out of the total_rx_bytes
945 * counter
946 */
947 if (netdev->features & NETIF_F_RXFCS)
948 total_rx_bytes -= 4;
949 else
950 length -= 4;
951 }
eb7c3adb 952
bc7f75fa
AK		 953 total_rx_bytes += length;
954 total_rx_packets++;
955
ad68076e
BA		 956 /*
957 * code added for copybreak, this should improve
bc7f75fa 958 * performance for small packets with large amounts
ad68076e
BA		 959 * of reassembly being done in the stack
960 */
bc7f75fa
AK		 961 if (length < copybreak) {
962 struct sk_buff *new_skb =
89d71a66 963 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 964 if (new_skb) {
808ff676
BA		 965 skb_copy_to_linear_data_offset(new_skb,
966 -NET_IP_ALIGN,
967 (skb->data -
968 NET_IP_ALIGN),
969 (length +
970 NET_IP_ALIGN));
bc7f75fa
AK		 971 /* save the skb in buffer_info as good */
972 buffer_info->skb = skb;
973 skb = new_skb;
974 }
975 /* else just continue with the old one */
976 }
977 /* end copybreak code */
978 skb_put(skb, length);
979
980 /* Receive Checksum Offload */
5f450212 981 e1000_rx_checksum(adapter, staterr,
afd12939 982 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 983
70495a50
BA		 984 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
985
5f450212
BA		 986 e1000_receive_skb(adapter, netdev, skb, staterr,
987 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 988
989next_desc:
5f450212 990 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 991
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 994 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 995 GFP_ATOMIC);
bc7f75fa
AK		 996 cleaned_count = 0;
997 }
998
999 /* use prefetched values */
1000 rx_desc = next_rxd;
1001 buffer_info = next_buffer;
5f450212
BA		 1002
1003 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1004 }
1005 rx_ring->next_to_clean = i;
1006
1007 cleaned_count = e1000_desc_unused(rx_ring);
1008 if (cleaned_count)
55aa6985 1009 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1010
bc7f75fa 1011 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1012 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1013 return cleaned;
1014}
1015
55aa6985
BA		 1016static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1017 struct e1000_buffer *buffer_info)
bc7f75fa 1018{
55aa6985
BA		 1019 struct e1000_adapter *adapter = tx_ring->adapter;
1020
03b1320d
AD		 1021 if (buffer_info->dma) {
1022 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1023 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1024 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1025 else
0be3f55f
NN		 1026 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1027 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1028 buffer_info->dma = 0;
1029 }
bc7f75fa
AK		 1030 if (buffer_info->skb) {
1031 dev_kfree_skb_any(buffer_info->skb);
1032 buffer_info->skb = NULL;
1033 }
1b7719c4 1034 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1035}
1036
41cec6f1 1037static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1038{
41cec6f1
BA		 1039 struct e1000_adapter *adapter = container_of(work,
1040 struct e1000_adapter,
1041 print_hang_task);
09357b00 1042 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1043 struct e1000_ring *tx_ring = adapter->tx_ring;
1044 unsigned int i = tx_ring->next_to_clean;
1045 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1046 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1047 struct e1000_hw *hw = &adapter->hw;
1048 u16 phy_status, phy_1000t_status, phy_ext_status;
1049 u16 pci_status;
1050
615b32af
JB		 1051 if (test_bit(__E1000_DOWN, &adapter->state))
1052 return;
1053
09357b00
JK		 1054 if (!adapter->tx_hang_recheck &&
1055 (adapter->flags2 & FLAG2_DMA_BURST)) {
397c020a
MV		 1056 /*
1057 * May be block on write-back, flush and detect again
09357b00
JK		 1058 * flush pending descriptor writebacks to memory
1059 */
1060 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1061 /* execute the writes immediately */
1062 e1e_flush();
bf03085f
MV		 1063 /*
1064 * Due to rare timing issues, write to TIDV again to ensure
1065 * the write is successful
1066 */
1067 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1068 /* execute the writes immediately */
1069 e1e_flush();
09357b00
JK		 1070 adapter->tx_hang_recheck = true;
1071 return;
1072 }
1073 /* Real hang detected */
1074 adapter->tx_hang_recheck = false;
1075 netif_stop_queue(netdev);
1076
41cec6f1
BA		 1077 e1e_rphy(hw, PHY_STATUS, &phy_status);
1078 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1079 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1080
41cec6f1
BA		 1081 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1082
1083 /* detected Hardware unit hang */
1084 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1085 " TDH <%x>\n"
1086 " TDT <%x>\n"
1087 " next_to_use <%x>\n"
1088 " next_to_clean <%x>\n"
1089 "buffer_info[next_to_clean]:\n"
1090 " time_stamp <%lx>\n"
1091 " next_to_watch <%x>\n"
1092 " jiffies <%lx>\n"
41cec6f1
BA		 1093 " next_to_watch.status <%x>\n"
1094 "MAC Status <%x>\n"
1095 "PHY Status <%x>\n"
1096 "PHY 1000BASE-T Status <%x>\n"
1097 "PHY Extended Status <%x>\n"
1098 "PCI Status <%x>\n",
c5083cf6
BA		 1099 readl(tx_ring->head),
1100 readl(tx_ring->tail),
44defeb3
JK		 1101 tx_ring->next_to_use,
1102 tx_ring->next_to_clean,
1103 tx_ring->buffer_info[eop].time_stamp,
1104 eop,
1105 jiffies,
41cec6f1
BA		 1106 eop_desc->upper.fields.status,
1107 er32(STATUS),
1108 phy_status,
1109 phy_1000t_status,
1110 phy_ext_status,
1111 pci_status);
bc7f75fa
AK		 1112}
1113
1114/**
1115 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1116 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1117 *
1118 * the return value indicates whether actual cleaning was done, there
1119 * is no guarantee that everything was cleaned
1120 **/
55aa6985 1121static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1122{
55aa6985 1123 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1124 struct net_device *netdev = adapter->netdev;
1125 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1126 struct e1000_tx_desc *tx_desc, *eop_desc;
1127 struct e1000_buffer *buffer_info;
1128 unsigned int i, eop;
1129 unsigned int count = 0;
bc7f75fa 1130 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1131 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1132
1133 i = tx_ring->next_to_clean;
1134 eop = tx_ring->buffer_info[i].next_to_watch;
1135 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1136
12d04a3c
AD		 1137 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1138 (count < tx_ring->count)) {
a86043c2 1139 bool cleaned = false;
2d0bb1c1 1140 rmb(); /* read buffer_info after eop_desc */
a86043c2 1141 for (; !cleaned; count++) {
bc7f75fa
AK		 1142 tx_desc = E1000_TX_DESC(*tx_ring, i);
1143 buffer_info = &tx_ring->buffer_info[i];
1144 cleaned = (i == eop);
1145
1146 if (cleaned) {
9ed318d5
TH		 1147 total_tx_packets += buffer_info->segs;
1148 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1149 if (buffer_info->skb) {
1150 bytes_compl += buffer_info->skb->len;
1151 pkts_compl++;
1152 }
bc7f75fa
AK		 1153 }
1154
55aa6985 1155 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1156 tx_desc->upper.data = 0;
1157
1158 i++;
1159 if (i == tx_ring->count)
1160 i = 0;
1161 }
1162
dac87619
TL		 1163 if (i == tx_ring->next_to_use)
1164 break;
bc7f75fa
AK		 1165 eop = tx_ring->buffer_info[i].next_to_watch;
1166 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1167 }
1168
1169 tx_ring->next_to_clean = i;
1170
3f0cfa3b
TH		 1171 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1172
bc7f75fa 1173#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1174 if (count && netif_carrier_ok(netdev) &&
1175 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1176 /* Make sure that anybody stopping the queue after this
1177 * sees the new next_to_clean.
1178 */
1179 smp_mb();
1180
1181 if (netif_queue_stopped(netdev) &&
1182 !(test_bit(__E1000_DOWN, &adapter->state))) {
1183 netif_wake_queue(netdev);
1184 ++adapter->restart_queue;
1185 }
1186 }
1187
1188 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1189 /*
1190 * Detect a transmit hang in hardware, this serializes the
1191 * check with the clearing of time_stamp and movement of i
1192 */
3db1cd5c 1193 adapter->detect_tx_hung = false;
12d04a3c
AD		 1194 if (tx_ring->buffer_info[i].time_stamp &&
1195 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1196 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1197 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1198 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1199 else
1200 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1201 }
1202 adapter->total_tx_bytes += total_tx_bytes;
1203 adapter->total_tx_packets += total_tx_packets;
807540ba 1204 return count < tx_ring->count;
bc7f75fa
AK		 1205}
1206
bc7f75fa
AK		 1207/**
1208 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1209 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1210 *
1211 * the return value indicates whether actual cleaning was done, there
1212 * is no guarantee that everything was cleaned
1213 **/
55aa6985
BA		 1214static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1215 int work_to_do)
bc7f75fa 1216{
55aa6985 1217 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1218 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1219 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1220 struct net_device *netdev = adapter->netdev;
1221 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1222 struct e1000_buffer *buffer_info, *next_buffer;
1223 struct e1000_ps_page *ps_page;
1224 struct sk_buff *skb;
1225 unsigned int i, j;
1226 u32 length, staterr;
1227 int cleaned_count = 0;
3db1cd5c 1228 bool cleaned = false;
bc7f75fa
AK		 1229 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1230
1231 i = rx_ring->next_to_clean;
1232 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1233 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1234 buffer_info = &rx_ring->buffer_info[i];
1235
1236 while (staterr & E1000_RXD_STAT_DD) {
1237 if (*work_done >= work_to_do)
1238 break;
1239 (*work_done)++;
1240 skb = buffer_info->skb;
2d0bb1c1 1241 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1242
1243 /* in the packet split case this is header only */
1244 prefetch(skb->data - NET_IP_ALIGN);
1245
1246 i++;
1247 if (i == rx_ring->count)
1248 i = 0;
1249 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1250 prefetch(next_rxd);
1251
1252 next_buffer = &rx_ring->buffer_info[i];
1253
3db1cd5c 1254 cleaned = true;
bc7f75fa 1255 cleaned_count++;
0be3f55f 1256 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1257 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1258 buffer_info->dma = 0;
1259
af667a29 1260 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1261 if (!(staterr & E1000_RXD_STAT_EOP))
1262 adapter->flags2 |= FLAG2_IS_DISCARDING;
1263
1264 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1265 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1266 dev_kfree_skb_irq(skb);
b94b5028
JB		 1267 if (staterr & E1000_RXD_STAT_EOP)
1268 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1269 goto next_desc;
1270 }
1271
cf955e6c
BG		 1272 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1273 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1274 dev_kfree_skb_irq(skb);
1275 goto next_desc;
1276 }
1277
1278 length = le16_to_cpu(rx_desc->wb.middle.length0);
1279
1280 if (!length) {
ef456f85 1281 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1282 dev_kfree_skb_irq(skb);
1283 goto next_desc;
1284 }
1285
1286 /* Good Receive */
1287 skb_put(skb, length);
1288
1289 {
0e15df49
BA		 1290 /*
1291 * this looks ugly, but it seems compiler issues make
1292 * it more efficient than reusing j
1293 */
1294 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1295
ad68076e 1296 /*
0e15df49
BA		 1297 * page alloc/put takes too long and effects small
1298 * packet throughput, so unsplit small packets and
1299 * save the alloc/put only valid in softirq (napi)
1300 * context to call kmap_*
ad68076e 1301 */
0e15df49
BA		 1302 if (l1 && (l1 <= copybreak) &&
1303 ((length + l1) <= adapter->rx_ps_bsize0)) {
1304 u8 *vaddr;
1305
1306 ps_page = &buffer_info->ps_pages[0];
1307
1308 /*
1309 * there is no documentation about how to call
1310 * kmap_atomic, so we can't hold the mapping
1311 * very long
1312 */
1313 dma_sync_single_for_cpu(&pdev->dev,
1314 ps_page->dma,
1315 PAGE_SIZE,
1316 DMA_FROM_DEVICE);
9f393834 1317 vaddr = kmap_atomic(ps_page->page);
0e15df49 1318 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1319 kunmap_atomic(vaddr);
0e15df49
BA		 1320 dma_sync_single_for_device(&pdev->dev,
1321 ps_page->dma,
1322 PAGE_SIZE,
1323 DMA_FROM_DEVICE);
1324
1325 /* remove the CRC */
0184039a
BG		 1326 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1327 if (!(netdev->features & NETIF_F_RXFCS))
1328 l1 -= 4;
1329 }
0e15df49
BA		 1330
1331 skb_put(skb, l1);
1332 goto copydone;
1333 } /* if */
bc7f75fa
AK		 1334 }
1335
1336 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1337 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1338 if (!length)
1339 break;
1340
47f44e40 1341 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1342 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1343 DMA_FROM_DEVICE);
bc7f75fa
AK		 1344 ps_page->dma = 0;
1345 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1346 ps_page->page = NULL;
1347 skb->len += length;
1348 skb->data_len += length;
98a045d7 1349 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1350 }
1351
eb7c3adb
JK		 1352 /* strip the ethernet crc, problem is we're using pages now so
1353 * this whole operation can get a little cpu intensive
1354 */
0184039a
BG		 1355 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1356 if (!(netdev->features & NETIF_F_RXFCS))
1357 pskb_trim(skb, skb->len - 4);
1358 }
eb7c3adb 1359
bc7f75fa
AK		 1360copydone:
1361 total_rx_bytes += skb->len;
1362 total_rx_packets++;
1363
afd12939
BA		 1364 e1000_rx_checksum(adapter, staterr,
1365 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1366
70495a50
BA		 1367 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1368
bc7f75fa
AK		 1369 if (rx_desc->wb.upper.header_status &
1370 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1371 adapter->rx_hdr_split++;
1372
1373 e1000_receive_skb(adapter, netdev, skb,
1374 staterr, rx_desc->wb.middle.vlan);
1375
1376next_desc:
1377 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1378 buffer_info->skb = NULL;
1379
1380 /* return some buffers to hardware, one at a time is too slow */
1381 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1382 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1383 GFP_ATOMIC);
bc7f75fa
AK		 1384 cleaned_count = 0;
1385 }
1386
1387 /* use prefetched values */
1388 rx_desc = next_rxd;
1389 buffer_info = next_buffer;
1390
1391 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1392 }
1393 rx_ring->next_to_clean = i;
1394
1395 cleaned_count = e1000_desc_unused(rx_ring);
1396 if (cleaned_count)
55aa6985 1397 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1398
bc7f75fa 1399 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1400 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1401 return cleaned;
1402}
1403
97ac8cae
BA		 1404/**
1405 * e1000_consume_page - helper function
1406 **/
1407static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1408 u16 length)
1409{
1410 bi->page = NULL;
1411 skb->len += length;
1412 skb->data_len += length;
98a045d7 1413 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1414}
1415
1416/**
1417 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1418 * @adapter: board private structure
1419 *
1420 * the return value indicates whether actual cleaning was done, there
1421 * is no guarantee that everything was cleaned
1422 **/
55aa6985
BA		 1423static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1424 int work_to_do)
97ac8cae 1425{
55aa6985 1426 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1427 struct net_device *netdev = adapter->netdev;
1428 struct pci_dev *pdev = adapter->pdev;
5f450212 1429 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1430 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1431 u32 length, staterr;
97ac8cae
BA		 1432 unsigned int i;
1433 int cleaned_count = 0;
1434 bool cleaned = false;
1435 unsigned int total_rx_bytes=0, total_rx_packets=0;
1436
1437 i = rx_ring->next_to_clean;
5f450212
BA		 1438 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1439 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1440 buffer_info = &rx_ring->buffer_info[i];
1441
5f450212 1442 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1443 struct sk_buff *skb;
97ac8cae
BA		 1444
1445 if (*work_done >= work_to_do)
1446 break;
1447 (*work_done)++;
2d0bb1c1 1448 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1449
97ac8cae
BA		 1450 skb = buffer_info->skb;
1451 buffer_info->skb = NULL;
1452
1453 ++i;
1454 if (i == rx_ring->count)
1455 i = 0;
5f450212 1456 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1457 prefetch(next_rxd);
1458
1459 next_buffer = &rx_ring->buffer_info[i];
1460
1461 cleaned = true;
1462 cleaned_count++;
0be3f55f
NN		 1463 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1464 DMA_FROM_DEVICE);
97ac8cae
BA		 1465 buffer_info->dma = 0;
1466
5f450212 1467 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1468
1469 /* errors is only valid for DD + EOP descriptors */
5f450212 1470 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1471 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1472 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1473 /* recycle both page and skb */
1474 buffer_info->skb = skb;
1475 /* an error means any chain goes out the window too */
1476 if (rx_ring->rx_skb_top)
1477 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1478 rx_ring->rx_skb_top = NULL;
1479 goto next_desc;
97ac8cae
BA		 1480 }
1481
f0f1a172 1482#define rxtop (rx_ring->rx_skb_top)
5f450212 1483 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1484 /* this descriptor is only the beginning (or middle) */
1485 if (!rxtop) {
1486 /* this is the beginning of a chain */
1487 rxtop = skb;
1488 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1489 0, length);
1490 } else {
1491 /* this is the middle of a chain */
1492 skb_fill_page_desc(rxtop,
1493 skb_shinfo(rxtop)->nr_frags,
1494 buffer_info->page, 0, length);
1495 /* re-use the skb, only consumed the page */
1496 buffer_info->skb = skb;
1497 }
1498 e1000_consume_page(buffer_info, rxtop, length);
1499 goto next_desc;
1500 } else {
1501 if (rxtop) {
1502 /* end of the chain */
1503 skb_fill_page_desc(rxtop,
1504 skb_shinfo(rxtop)->nr_frags,
1505 buffer_info->page, 0, length);
1506 /* re-use the current skb, we only consumed the
1507 * page */
1508 buffer_info->skb = skb;
1509 skb = rxtop;
1510 rxtop = NULL;
1511 e1000_consume_page(buffer_info, skb, length);
1512 } else {
1513 /* no chain, got EOP, this buf is the packet
1514 * copybreak to save the put_page/alloc_page */
1515 if (length <= copybreak &&
1516 skb_tailroom(skb) >= length) {
1517 u8 *vaddr;
4679026d 1518 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1519 memcpy(skb_tail_pointer(skb), vaddr,
1520 length);
4679026d 1521 kunmap_atomic(vaddr);
97ac8cae
BA		 1522 /* re-use the page, so don't erase
1523 * buffer_info->page */
1524 skb_put(skb, length);
1525 } else {
1526 skb_fill_page_desc(skb, 0,
1527 buffer_info->page, 0,
1528 length);
1529 e1000_consume_page(buffer_info, skb,
1530 length);
1531 }
1532 }
1533 }
1534
1535 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1536 e1000_rx_checksum(adapter, staterr,
afd12939 1537 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1538
70495a50
BA		 1539 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1540
97ac8cae
BA		 1541 /* probably a little skewed due to removing CRC */
1542 total_rx_bytes += skb->len;
1543 total_rx_packets++;
1544
1545 /* eth type trans needs skb->data to point to something */
1546 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1547 e_err("pskb_may_pull failed.\n");
ef5ab89c 1548 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1549 goto next_desc;
1550 }
1551
5f450212
BA		 1552 e1000_receive_skb(adapter, netdev, skb, staterr,
1553 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1554
1555next_desc:
5f450212 1556 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1557
1558 /* return some buffers to hardware, one at a time is too slow */
1559 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1560 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1561 GFP_ATOMIC);
97ac8cae
BA		 1562 cleaned_count = 0;
1563 }
1564
1565 /* use prefetched values */
1566 rx_desc = next_rxd;
1567 buffer_info = next_buffer;
5f450212
BA		 1568
1569 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1570 }
1571 rx_ring->next_to_clean = i;
1572
1573 cleaned_count = e1000_desc_unused(rx_ring);
1574 if (cleaned_count)
55aa6985 1575 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1576
1577 adapter->total_rx_bytes += total_rx_bytes;
1578 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1579 return cleaned;
1580}
1581
bc7f75fa
AK		 1582/**
1583 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1584 * @rx_ring: Rx descriptor ring
bc7f75fa 1585 **/
55aa6985 1586static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1587{
55aa6985 1588 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1589 struct e1000_buffer *buffer_info;
1590 struct e1000_ps_page *ps_page;
1591 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1592 unsigned int i, j;
1593
1594 /* Free all the Rx ring sk_buffs */
1595 for (i = 0; i < rx_ring->count; i++) {
1596 buffer_info = &rx_ring->buffer_info[i];
1597 if (buffer_info->dma) {
1598 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1599 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1600 adapter->rx_buffer_len,
0be3f55f 1601 DMA_FROM_DEVICE);
97ac8cae 1602 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1603 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1604 PAGE_SIZE,
0be3f55f 1605 DMA_FROM_DEVICE);
bc7f75fa 1606 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1607 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1608 adapter->rx_ps_bsize0,
0be3f55f 1609 DMA_FROM_DEVICE);
bc7f75fa
AK		 1610 buffer_info->dma = 0;
1611 }
1612
97ac8cae
BA		 1613 if (buffer_info->page) {
1614 put_page(buffer_info->page);
1615 buffer_info->page = NULL;
1616 }
1617
bc7f75fa
AK		 1618 if (buffer_info->skb) {
1619 dev_kfree_skb(buffer_info->skb);
1620 buffer_info->skb = NULL;
1621 }
1622
1623 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1624 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1625 if (!ps_page->page)
1626 break;
0be3f55f
NN		 1627 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1628 DMA_FROM_DEVICE);
bc7f75fa
AK		 1629 ps_page->dma = 0;
1630 put_page(ps_page->page);
1631 ps_page->page = NULL;
1632 }
1633 }
1634
1635 /* there also may be some cached data from a chained receive */
1636 if (rx_ring->rx_skb_top) {
1637 dev_kfree_skb(rx_ring->rx_skb_top);
1638 rx_ring->rx_skb_top = NULL;
1639 }
1640
bc7f75fa
AK		 1641 /* Zero out the descriptor ring */
1642 memset(rx_ring->desc, 0, rx_ring->size);
1643
1644 rx_ring->next_to_clean = 0;
1645 rx_ring->next_to_use = 0;
b94b5028 1646 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1647
c5083cf6
BA		 1648 writel(0, rx_ring->head);
1649 writel(0, rx_ring->tail);
bc7f75fa
AK		 1650}
1651
a8f88ff5
JB		 1652static void e1000e_downshift_workaround(struct work_struct *work)
1653{
1654 struct e1000_adapter *adapter = container_of(work,
1655 struct e1000_adapter, downshift_task);
1656
615b32af
JB		 1657 if (test_bit(__E1000_DOWN, &adapter->state))
1658 return;
1659
a8f88ff5
JB		 1660 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1661}
1662
bc7f75fa
AK		 1663/**
1664 * e1000_intr_msi - Interrupt Handler
1665 * @irq: interrupt number
1666 * @data: pointer to a network interface device structure
1667 **/
1668static irqreturn_t e1000_intr_msi(int irq, void *data)
1669{
1670 struct net_device *netdev = data;
1671 struct e1000_adapter *adapter = netdev_priv(netdev);
1672 struct e1000_hw *hw = &adapter->hw;
1673 u32 icr = er32(ICR);
1674
ad68076e
BA		 1675 /*
1676 * read ICR disables interrupts using IAM
1677 */
bc7f75fa 1678
573cca8c 1679 if (icr & E1000_ICR_LSC) {
f92518dd 1680 hw->mac.get_link_status = true;
ad68076e
BA		 1681 /*
1682 * ICH8 workaround-- Call gig speed drop workaround on cable
1683 * disconnect (LSC) before accessing any PHY registers
1684 */
bc7f75fa
AK		 1685 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1686 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1687 schedule_work(&adapter->downshift_task);
bc7f75fa 1688
ad68076e
BA		 1689 /*
1690 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1691 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1692 * adapter in watchdog
1693 */
bc7f75fa
AK		 1694 if (netif_carrier_ok(netdev) &&
1695 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1696 /* disable receives */
1697 u32 rctl = er32(RCTL);
1698 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1699 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1700 }
1701 /* guard against interrupt when we're going down */
1702 if (!test_bit(__E1000_DOWN, &adapter->state))
1703 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1704 }
1705
288379f0 1706 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1707 adapter->total_tx_bytes = 0;
1708 adapter->total_tx_packets = 0;
1709 adapter->total_rx_bytes = 0;
1710 adapter->total_rx_packets = 0;
288379f0 1711 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1712 }
1713
1714 return IRQ_HANDLED;
1715}
1716
1717/**
1718 * e1000_intr - Interrupt Handler
1719 * @irq: interrupt number
1720 * @data: pointer to a network interface device structure
1721 **/
1722static irqreturn_t e1000_intr(int irq, void *data)
1723{
1724 struct net_device *netdev = data;
1725 struct e1000_adapter *adapter = netdev_priv(netdev);
1726 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1727 u32 rctl, icr = er32(ICR);
4662e82b 1728
a68ea775 1729 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1730 return IRQ_NONE; /* Not our interrupt */
1731
ad68076e
BA		 1732 /*
1733 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1734 * not set, then the adapter didn't send an interrupt
1735 */
bc7f75fa
AK		 1736 if (!(icr & E1000_ICR_INT_ASSERTED))
1737 return IRQ_NONE;
1738
ad68076e
BA		 1739 /*
1740 * Interrupt Auto-Mask...upon reading ICR,
1741 * interrupts are masked. No need for the
1742 * IMC write
1743 */
bc7f75fa 1744
573cca8c 1745 if (icr & E1000_ICR_LSC) {
f92518dd 1746 hw->mac.get_link_status = true;
ad68076e
BA		 1747 /*
1748 * ICH8 workaround-- Call gig speed drop workaround on cable
1749 * disconnect (LSC) before accessing any PHY registers
1750 */
bc7f75fa
AK		 1751 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1752 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1753 schedule_work(&adapter->downshift_task);
bc7f75fa 1754
ad68076e
BA		 1755 /*
1756 * 80003ES2LAN workaround--
bc7f75fa
AK		 1757 * For packet buffer work-around on link down event;
1758 * disable receives here in the ISR and
1759 * reset adapter in watchdog
1760 */
1761 if (netif_carrier_ok(netdev) &&
1762 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1763 /* disable receives */
1764 rctl = er32(RCTL);
1765 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1766 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1767 }
1768 /* guard against interrupt when we're going down */
1769 if (!test_bit(__E1000_DOWN, &adapter->state))
1770 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1771 }
1772
288379f0 1773 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1774 adapter->total_tx_bytes = 0;
1775 adapter->total_tx_packets = 0;
1776 adapter->total_rx_bytes = 0;
1777 adapter->total_rx_packets = 0;
288379f0 1778 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1779 }
1780
1781 return IRQ_HANDLED;
1782}
1783
4662e82b
BA		 1784static irqreturn_t e1000_msix_other(int irq, void *data)
1785{
1786 struct net_device *netdev = data;
1787 struct e1000_adapter *adapter = netdev_priv(netdev);
1788 struct e1000_hw *hw = &adapter->hw;
1789 u32 icr = er32(ICR);
1790
1791 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1792 if (!test_bit(__E1000_DOWN, &adapter->state))
1793 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1794 return IRQ_NONE;
1795 }
1796
1797 if (icr & adapter->eiac_mask)
1798 ew32(ICS, (icr & adapter->eiac_mask));
1799
1800 if (icr & E1000_ICR_OTHER) {
1801 if (!(icr & E1000_ICR_LSC))
1802 goto no_link_interrupt;
f92518dd 1803 hw->mac.get_link_status = true;
4662e82b
BA		 1804 /* guard against interrupt when we're going down */
1805 if (!test_bit(__E1000_DOWN, &adapter->state))
1806 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1807 }
1808
1809no_link_interrupt:
a3c69fef
JB		 1810 if (!test_bit(__E1000_DOWN, &adapter->state))
1811 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1812
1813 return IRQ_HANDLED;
1814}
1815
1816
1817static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1818{
1819 struct net_device *netdev = data;
1820 struct e1000_adapter *adapter = netdev_priv(netdev);
1821 struct e1000_hw *hw = &adapter->hw;
1822 struct e1000_ring *tx_ring = adapter->tx_ring;
1823
1824
1825 adapter->total_tx_bytes = 0;
1826 adapter->total_tx_packets = 0;
1827
55aa6985 1828 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1829 /* Ring was not completely cleaned, so fire another interrupt */
1830 ew32(ICS, tx_ring->ims_val);
1831
1832 return IRQ_HANDLED;
1833}
1834
1835static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1836{
1837 struct net_device *netdev = data;
1838 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1839 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1840
1841 /* Write the ITR value calculated at the end of the
1842 * previous interrupt.
1843 */
55aa6985
BA		 1844 if (rx_ring->set_itr) {
1845 writel(1000000000 / (rx_ring->itr_val * 256),
1846 rx_ring->itr_register);
1847 rx_ring->set_itr = 0;
4662e82b
BA		 1848 }
1849
288379f0 1850 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1851 adapter->total_rx_bytes = 0;
1852 adapter->total_rx_packets = 0;
288379f0 1853 __napi_schedule(&adapter->napi);
4662e82b
BA		 1854 }
1855 return IRQ_HANDLED;
1856}
1857
1858/**
1859 * e1000_configure_msix - Configure MSI-X hardware
1860 *
1861 * e1000_configure_msix sets up the hardware to properly
1862 * generate MSI-X interrupts.
1863 **/
1864static void e1000_configure_msix(struct e1000_adapter *adapter)
1865{
1866 struct e1000_hw *hw = &adapter->hw;
1867 struct e1000_ring *rx_ring = adapter->rx_ring;
1868 struct e1000_ring *tx_ring = adapter->tx_ring;
1869 int vector = 0;
1870 u32 ctrl_ext, ivar = 0;
1871
1872 adapter->eiac_mask = 0;
1873
1874 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1875 if (hw->mac.type == e1000_82574) {
1876 u32 rfctl = er32(RFCTL);
1877 rfctl |= E1000_RFCTL_ACK_DIS;
1878 ew32(RFCTL, rfctl);
1879 }
1880
1881#define E1000_IVAR_INT_ALLOC_VALID 0x8
1882 /* Configure Rx vector */
1883 rx_ring->ims_val = E1000_IMS_RXQ0;
1884 adapter->eiac_mask |= rx_ring->ims_val;
1885 if (rx_ring->itr_val)
1886 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1887 rx_ring->itr_register);
4662e82b 1888 else
c5083cf6 1889 writel(1, rx_ring->itr_register);
4662e82b
BA		 1890 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1891
1892 /* Configure Tx vector */
1893 tx_ring->ims_val = E1000_IMS_TXQ0;
1894 vector++;
1895 if (tx_ring->itr_val)
1896 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1897 tx_ring->itr_register);
4662e82b 1898 else
c5083cf6 1899 writel(1, tx_ring->itr_register);
4662e82b
BA		 1900 adapter->eiac_mask |= tx_ring->ims_val;
1901 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1902
1903 /* set vector for Other Causes, e.g. link changes */
1904 vector++;
1905 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1906 if (rx_ring->itr_val)
1907 writel(1000000000 / (rx_ring->itr_val * 256),
1908 hw->hw_addr + E1000_EITR_82574(vector));
1909 else
1910 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1911
1912 /* Cause Tx interrupts on every write back */
1913 ivar |= (1 << 31);
1914
1915 ew32(IVAR, ivar);
1916
1917 /* enable MSI-X PBA support */
1918 ctrl_ext = er32(CTRL_EXT);
1919 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1920
1921 /* Auto-Mask Other interrupts upon ICR read */
1922#define E1000_EIAC_MASK_82574 0x01F00000
1923 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1924 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1925 ew32(CTRL_EXT, ctrl_ext);
1926 e1e_flush();
1927}
1928
1929void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1930{
1931 if (adapter->msix_entries) {
1932 pci_disable_msix(adapter->pdev);
1933 kfree(adapter->msix_entries);
1934 adapter->msix_entries = NULL;
1935 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1936 pci_disable_msi(adapter->pdev);
1937 adapter->flags &= ~FLAG_MSI_ENABLED;
1938 }
4662e82b
BA		 1939}
1940
1941/**
1942 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1943 *
1944 * Attempt to configure interrupts using the best available
1945 * capabilities of the hardware and kernel.
1946 **/
1947void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1948{
1949 int err;
8e86acd7 1950 int i;
4662e82b
BA		 1951
1952 switch (adapter->int_mode) {
1953 case E1000E_INT_MODE_MSIX:
1954 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1955 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1956 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1957 sizeof(struct msix_entry),
1958 GFP_KERNEL);
1959 if (adapter->msix_entries) {
8e86acd7 1960 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1961 adapter->msix_entries[i].entry = i;
1962
1963 err = pci_enable_msix(adapter->pdev,
1964 adapter->msix_entries,
8e86acd7 1965 adapter->num_vectors);
b1cdfead 1966 if (err == 0)
4662e82b
BA		 1967 return;
1968 }
1969 /* MSI-X failed, so fall through and try MSI */
ef456f85 1970 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1971 e1000e_reset_interrupt_capability(adapter);
1972 }
1973 adapter->int_mode = E1000E_INT_MODE_MSI;
1974 /* Fall through */
1975 case E1000E_INT_MODE_MSI:
1976 if (!pci_enable_msi(adapter->pdev)) {
1977 adapter->flags |= FLAG_MSI_ENABLED;
1978 } else {
1979 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1980 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1981 }
1982 /* Fall through */
1983 case E1000E_INT_MODE_LEGACY:
1984 /* Don't do anything; this is the system default */
1985 break;
1986 }
8e86acd7
JK		 1987
1988 /* store the number of vectors being used */
1989 adapter->num_vectors = 1;
4662e82b
BA		 1990}
1991
1992/**
1993 * e1000_request_msix - Initialize MSI-X interrupts
1994 *
1995 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1996 * kernel.
1997 **/
1998static int e1000_request_msix(struct e1000_adapter *adapter)
1999{
2000 struct net_device *netdev = adapter->netdev;
2001 int err = 0, vector = 0;
2002
2003 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2004 snprintf(adapter->rx_ring->name,
2005 sizeof(adapter->rx_ring->name) - 1,
2006 "%s-rx-0", netdev->name);
4662e82b
BA		 2007 else
2008 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2009 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2010 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2011 netdev);
2012 if (err)
5015e53a 2013 return err;
c5083cf6
BA		 2014 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2015 E1000_EITR_82574(vector);
4662e82b
BA		 2016 adapter->rx_ring->itr_val = adapter->itr;
2017 vector++;
2018
2019 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2020 snprintf(adapter->tx_ring->name,
2021 sizeof(adapter->tx_ring->name) - 1,
2022 "%s-tx-0", netdev->name);
4662e82b
BA		 2023 else
2024 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2025 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2026 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2027 netdev);
2028 if (err)
5015e53a 2029 return err;
c5083cf6
BA		 2030 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2031 E1000_EITR_82574(vector);
4662e82b
BA		 2032 adapter->tx_ring->itr_val = adapter->itr;
2033 vector++;
2034
2035 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2036 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2037 if (err)
5015e53a 2038 return err;
4662e82b
BA		 2039
2040 e1000_configure_msix(adapter);
5015e53a 2041
4662e82b 2042 return 0;
4662e82b
BA		 2043}
2044
f8d59f78
BA		 2045/**
2046 * e1000_request_irq - initialize interrupts
2047 *
2048 * Attempts to configure interrupts using the best available
2049 * capabilities of the hardware and kernel.
2050 **/
bc7f75fa
AK		 2051static int e1000_request_irq(struct e1000_adapter *adapter)
2052{
2053 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2054 int err;
2055
4662e82b
BA		 2056 if (adapter->msix_entries) {
2057 err = e1000_request_msix(adapter);
2058 if (!err)
2059 return err;
2060 /* fall back to MSI */
2061 e1000e_reset_interrupt_capability(adapter);
2062 adapter->int_mode = E1000E_INT_MODE_MSI;
2063 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2064 }
4662e82b 2065 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2066 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2067 netdev->name, netdev);
2068 if (!err)
2069 return err;
bc7f75fa 2070
4662e82b
BA		 2071 /* fall back to legacy interrupt */
2072 e1000e_reset_interrupt_capability(adapter);
2073 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2074 }
2075
a0607fd3 2076 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2077 netdev->name, netdev);
2078 if (err)
2079 e_err("Unable to allocate interrupt, Error: %d\n", err);
2080
bc7f75fa
AK		 2081 return err;
2082}
2083
2084static void e1000_free_irq(struct e1000_adapter *adapter)
2085{
2086 struct net_device *netdev = adapter->netdev;
2087
4662e82b
BA		 2088 if (adapter->msix_entries) {
2089 int vector = 0;
2090
2091 free_irq(adapter->msix_entries[vector].vector, netdev);
2092 vector++;
2093
2094 free_irq(adapter->msix_entries[vector].vector, netdev);
2095 vector++;
2096
2097 /* Other Causes interrupt vector */
2098 free_irq(adapter->msix_entries[vector].vector, netdev);
2099 return;
bc7f75fa 2100 }
4662e82b
BA		 2101
2102 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2103}
2104
2105/**
2106 * e1000_irq_disable - Mask off interrupt generation on the NIC
2107 **/
2108static void e1000_irq_disable(struct e1000_adapter *adapter)
2109{
2110 struct e1000_hw *hw = &adapter->hw;
2111
bc7f75fa 2112 ew32(IMC, ~0);
4662e82b
BA		 2113 if (adapter->msix_entries)
2114 ew32(EIAC_82574, 0);
bc7f75fa 2115 e1e_flush();
8e86acd7
JK		 2116
2117 if (adapter->msix_entries) {
2118 int i;
2119 for (i = 0; i < adapter->num_vectors; i++)
2120 synchronize_irq(adapter->msix_entries[i].vector);
2121 } else {
2122 synchronize_irq(adapter->pdev->irq);
2123 }
bc7f75fa
AK		 2124}
2125
2126/**
2127 * e1000_irq_enable - Enable default interrupt generation settings
2128 **/
2129static void e1000_irq_enable(struct e1000_adapter *adapter)
2130{
2131 struct e1000_hw *hw = &adapter->hw;
2132
4662e82b
BA		 2133 if (adapter->msix_entries) {
2134 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2135 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2136 } else {
2137 ew32(IMS, IMS_ENABLE_MASK);
2138 }
74ef9c39 2139 e1e_flush();
bc7f75fa
AK		 2140}
2141
2142/**
31dbe5b4 2143 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2144 * @adapter: address of board private structure
2145 *
31dbe5b4 2146 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2147 * For ASF and Pass Through versions of f/w this means that
2148 * the driver is loaded. For AMT version (only with 82573)
2149 * of the f/w this means that the network i/f is open.
2150 **/
31dbe5b4 2151void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2152{
2153 struct e1000_hw *hw = &adapter->hw;
2154 u32 ctrl_ext;
2155 u32 swsm;
2156
2157 /* Let firmware know the driver has taken over */
2158 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2159 swsm = er32(SWSM);
2160 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2161 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2162 ctrl_ext = er32(CTRL_EXT);
ad68076e 2163 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2164 }
2165}
2166
2167/**
31dbe5b4 2168 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2169 * @adapter: address of board private structure
2170 *
31dbe5b4 2171 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2172 * For ASF and Pass Through versions of f/w this means that the
2173 * driver is no longer loaded. For AMT version (only with 82573) i
2174 * of the f/w this means that the network i/f is closed.
2175 *
2176 **/
31dbe5b4 2177void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2178{
2179 struct e1000_hw *hw = &adapter->hw;
2180 u32 ctrl_ext;
2181 u32 swsm;
2182
2183 /* Let firmware taken over control of h/w */
2184 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2185 swsm = er32(SWSM);
2186 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2187 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2188 ctrl_ext = er32(CTRL_EXT);
ad68076e 2189 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2190 }
2191}
2192
bc7f75fa
AK		 2193/**
2194 * @e1000_alloc_ring - allocate memory for a ring structure
2195 **/
2196static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2197 struct e1000_ring *ring)
2198{
2199 struct pci_dev *pdev = adapter->pdev;
2200
2201 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2202 GFP_KERNEL);
2203 if (!ring->desc)
2204 return -ENOMEM;
2205
2206 return 0;
2207}
2208
2209/**
2210 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2211 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2212 *
2213 * Return 0 on success, negative on failure
2214 **/
55aa6985 2215int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2216{
55aa6985 2217 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2218 int err = -ENOMEM, size;
2219
2220 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2221 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2222 if (!tx_ring->buffer_info)
2223 goto err;
bc7f75fa
AK		 2224
2225 /* round up to nearest 4K */
2226 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2227 tx_ring->size = ALIGN(tx_ring->size, 4096);
2228
2229 err = e1000_alloc_ring_dma(adapter, tx_ring);
2230 if (err)
2231 goto err;
2232
2233 tx_ring->next_to_use = 0;
2234 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2235
2236 return 0;
2237err:
2238 vfree(tx_ring->buffer_info);
44defeb3 2239 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2240 return err;
2241}
2242
2243/**
2244 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2245 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2246 *
2247 * Returns 0 on success, negative on failure
2248 **/
55aa6985 2249int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2250{
55aa6985 2251 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2252 struct e1000_buffer *buffer_info;
2253 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2254
2255 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2256 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2257 if (!rx_ring->buffer_info)
2258 goto err;
bc7f75fa 2259
47f44e40
AK		 2260 for (i = 0; i < rx_ring->count; i++) {
2261 buffer_info = &rx_ring->buffer_info[i];
2262 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2263 sizeof(struct e1000_ps_page),
2264 GFP_KERNEL);
2265 if (!buffer_info->ps_pages)
2266 goto err_pages;
2267 }
bc7f75fa
AK		 2268
2269 desc_len = sizeof(union e1000_rx_desc_packet_split);
2270
2271 /* Round up to nearest 4K */
2272 rx_ring->size = rx_ring->count * desc_len;
2273 rx_ring->size = ALIGN(rx_ring->size, 4096);
2274
2275 err = e1000_alloc_ring_dma(adapter, rx_ring);
2276 if (err)
47f44e40 2277 goto err_pages;
bc7f75fa
AK		 2278
2279 rx_ring->next_to_clean = 0;
2280 rx_ring->next_to_use = 0;
2281 rx_ring->rx_skb_top = NULL;
2282
2283 return 0;
47f44e40
AK		 2284
2285err_pages:
2286 for (i = 0; i < rx_ring->count; i++) {
2287 buffer_info = &rx_ring->buffer_info[i];
2288 kfree(buffer_info->ps_pages);
2289 }
bc7f75fa
AK		 2290err:
2291 vfree(rx_ring->buffer_info);
e9262447 2292 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2293 return err;
2294}
2295
2296/**
2297 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2298 * @tx_ring: Tx descriptor ring
bc7f75fa 2299 **/
55aa6985 2300static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2301{
55aa6985 2302 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2303 struct e1000_buffer *buffer_info;
2304 unsigned long size;
2305 unsigned int i;
2306
2307 for (i = 0; i < tx_ring->count; i++) {
2308 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2309 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2310 }
2311
3f0cfa3b 2312 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2313 size = sizeof(struct e1000_buffer) * tx_ring->count;
2314 memset(tx_ring->buffer_info, 0, size);
2315
2316 memset(tx_ring->desc, 0, tx_ring->size);
2317
2318 tx_ring->next_to_use = 0;
2319 tx_ring->next_to_clean = 0;
2320
c5083cf6
BA		 2321 writel(0, tx_ring->head);
2322 writel(0, tx_ring->tail);
bc7f75fa
AK		 2323}
2324
2325/**
2326 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2327 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2328 *
2329 * Free all transmit software resources
2330 **/
55aa6985 2331void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2332{
55aa6985 2333 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2334 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2335
55aa6985 2336 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2337
2338 vfree(tx_ring->buffer_info);
2339 tx_ring->buffer_info = NULL;
2340
2341 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2342 tx_ring->dma);
2343 tx_ring->desc = NULL;
2344}
2345
2346/**
2347 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2348 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2349 *
2350 * Free all receive software resources
2351 **/
55aa6985 2352void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2353{
55aa6985 2354 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2355 struct pci_dev *pdev = adapter->pdev;
47f44e40 2356 int i;
bc7f75fa 2357
55aa6985 2358 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2359
b1cdfead 2360 for (i = 0; i < rx_ring->count; i++)
47f44e40 2361 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2362
bc7f75fa
AK		 2363 vfree(rx_ring->buffer_info);
2364 rx_ring->buffer_info = NULL;
2365
bc7f75fa
AK		 2366 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2367 rx_ring->dma);
2368 rx_ring->desc = NULL;
2369}
2370
2371/**
2372 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2373 * @adapter: pointer to adapter
2374 * @itr_setting: current adapter->itr
2375 * @packets: the number of packets during this measurement interval
2376 * @bytes: the number of bytes during this measurement interval
2377 *
bc7f75fa
AK		 2378 * Stores a new ITR value based on packets and byte
2379 * counts during the last interrupt. The advantage of per interrupt
2380 * computation is faster updates and more accurate ITR for the current
2381 * traffic pattern. Constants in this function were computed
2382 * based on theoretical maximum wire speed and thresholds were set based
2383 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2384 * while increasing bulk throughput. This functionality is controlled
2385 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2386 **/
2387static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2388 u16 itr_setting, int packets,
2389 int bytes)
2390{
2391 unsigned int retval = itr_setting;
2392
2393 if (packets == 0)
5015e53a 2394 return itr_setting;
bc7f75fa
AK		 2395
2396 switch (itr_setting) {
2397 case lowest_latency:
2398 /* handle TSO and jumbo frames */
2399 if (bytes/packets > 8000)
2400 retval = bulk_latency;
b1cdfead 2401 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2402 retval = low_latency;
bc7f75fa
AK		 2403 break;
2404 case low_latency: /* 50 usec aka 20000 ints/s */
2405 if (bytes > 10000) {
2406 /* this if handles the TSO accounting */
b1cdfead 2407 if (bytes/packets > 8000)
bc7f75fa 2408 retval = bulk_latency;
b1cdfead 2409 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2410 retval = bulk_latency;
b1cdfead 2411 else if ((packets > 35))
bc7f75fa 2412 retval = lowest_latency;
bc7f75fa
AK		 2413 } else if (bytes/packets > 2000) {
2414 retval = bulk_latency;
2415 } else if (packets <= 2 && bytes < 512) {
2416 retval = lowest_latency;
2417 }
2418 break;
2419 case bulk_latency: /* 250 usec aka 4000 ints/s */
2420 if (bytes > 25000) {
b1cdfead 2421 if (packets > 35)
bc7f75fa 2422 retval = low_latency;
bc7f75fa
AK		 2423 } else if (bytes < 6000) {
2424 retval = low_latency;
2425 }
2426 break;
2427 }
2428
bc7f75fa
AK		 2429 return retval;
2430}
2431
2432static void e1000_set_itr(struct e1000_adapter *adapter)
2433{
2434 struct e1000_hw *hw = &adapter->hw;
2435 u16 current_itr;
2436 u32 new_itr = adapter->itr;
2437
2438 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2439 if (adapter->link_speed != SPEED_1000) {
2440 current_itr = 0;
2441 new_itr = 4000;
2442 goto set_itr_now;
2443 }
2444
828bac87
BA		 2445 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2446 new_itr = 0;
2447 goto set_itr_now;
2448 }
2449
bc7f75fa
AK		 2450 adapter->tx_itr = e1000_update_itr(adapter,
2451 adapter->tx_itr,
2452 adapter->total_tx_packets,
2453 adapter->total_tx_bytes);
2454 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2455 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2456 adapter->tx_itr = low_latency;
2457
2458 adapter->rx_itr = e1000_update_itr(adapter,
2459 adapter->rx_itr,
2460 adapter->total_rx_packets,
2461 adapter->total_rx_bytes);
2462 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2463 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2464 adapter->rx_itr = low_latency;
2465
2466 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2467
2468 switch (current_itr) {
2469 /* counts and packets in update_itr are dependent on these numbers */
2470 case lowest_latency:
2471 new_itr = 70000;
2472 break;
2473 case low_latency:
2474 new_itr = 20000; /* aka hwitr = ~200 */
2475 break;
2476 case bulk_latency:
2477 new_itr = 4000;
2478 break;
2479 default:
2480 break;
2481 }
2482
2483set_itr_now:
2484 if (new_itr != adapter->itr) {
ad68076e
BA		 2485 /*
2486 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2487 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2488 * increasing
2489 */
bc7f75fa
AK		 2490 new_itr = new_itr > adapter->itr ?
2491 min(adapter->itr + (new_itr >> 2), new_itr) :
2492 new_itr;
2493 adapter->itr = new_itr;
4662e82b
BA		 2494 adapter->rx_ring->itr_val = new_itr;
2495 if (adapter->msix_entries)
2496 adapter->rx_ring->set_itr = 1;
2497 else
828bac87
BA		 2498 if (new_itr)
2499 ew32(ITR, 1000000000 / (new_itr * 256));
2500 else
2501 ew32(ITR, 0);
bc7f75fa
AK		 2502 }
2503}
2504
4662e82b
BA		 2505/**
2506 * e1000_alloc_queues - Allocate memory for all rings
2507 * @adapter: board private structure to initialize
2508 **/
2509static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2510{
55aa6985
BA		 2511 int size = sizeof(struct e1000_ring);
2512
2513 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2514 if (!adapter->tx_ring)
2515 goto err;
55aa6985
BA		 2516 adapter->tx_ring->count = adapter->tx_ring_count;
2517 adapter->tx_ring->adapter = adapter;
4662e82b 2518
55aa6985 2519 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2520 if (!adapter->rx_ring)
2521 goto err;
55aa6985
BA		 2522 adapter->rx_ring->count = adapter->rx_ring_count;
2523 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2524
2525 return 0;
2526err:
2527 e_err("Unable to allocate memory for queues\n");
2528 kfree(adapter->rx_ring);
2529 kfree(adapter->tx_ring);
2530 return -ENOMEM;
2531}
2532
bc7f75fa 2533/**
c58c8a78 2534 * e1000e_poll - NAPI Rx polling callback
ad68076e 2535 * @napi: struct associated with this polling callback
c58c8a78 2536 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2537 **/
c58c8a78 2538static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2539{
c58c8a78
BA		 2540 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2541 napi);
4662e82b 2542 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2543 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2544 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2545
4cf1653a 2546 adapter = netdev_priv(poll_dev);
bc7f75fa 2547
c58c8a78
BA		 2548 if (!adapter->msix_entries ||
2549 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2550 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2551
c58c8a78 2552 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2553
12d04a3c 2554 if (!tx_cleaned)
c58c8a78 2555 work_done = weight;
bc7f75fa 2556
c58c8a78
BA		 2557 /* If weight not fully consumed, exit the polling mode */
2558 if (work_done < weight) {
bc7f75fa
AK		 2559 if (adapter->itr_setting & 3)
2560 e1000_set_itr(adapter);
288379f0 2561 napi_complete(napi);
a3c69fef
JB		 2562 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2563 if (adapter->msix_entries)
2564 ew32(IMS, adapter->rx_ring->ims_val);
2565 else
2566 e1000_irq_enable(adapter);
2567 }
bc7f75fa
AK		 2568 }
2569
2570 return work_done;
2571}
2572
8e586137 2573static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2574{
2575 struct e1000_adapter *adapter = netdev_priv(netdev);
2576 struct e1000_hw *hw = &adapter->hw;
2577 u32 vfta, index;
2578
2579 /* don't update vlan cookie if already programmed */
2580 if ((adapter->hw.mng_cookie.status &
2581 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2582 (vid == adapter->mng_vlan_id))
8e586137 2583 return 0;
caaddaf8 2584
bc7f75fa 2585 /* add VID to filter table */
caaddaf8
BA		 2586 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2587 index = (vid >> 5) & 0x7F;
2588 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2589 vfta |= (1 << (vid & 0x1F));
2590 hw->mac.ops.write_vfta(hw, index, vfta);
2591 }
86d70e53
JK		 2592
2593 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2594
2595 return 0;
bc7f75fa
AK		 2596}
2597
8e586137 2598static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2599{
2600 struct e1000_adapter *adapter = netdev_priv(netdev);
2601 struct e1000_hw *hw = &adapter->hw;
2602 u32 vfta, index;
2603
bc7f75fa
AK		 2604 if ((adapter->hw.mng_cookie.status &
2605 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2606 (vid == adapter->mng_vlan_id)) {
2607 /* release control to f/w */
31dbe5b4 2608 e1000e_release_hw_control(adapter);
8e586137 2609 return 0;
bc7f75fa
AK		 2610 }
2611
2612 /* remove VID from filter table */
caaddaf8
BA		 2613 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2614 index = (vid >> 5) & 0x7F;
2615 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2616 vfta &= ~(1 << (vid & 0x1F));
2617 hw->mac.ops.write_vfta(hw, index, vfta);
2618 }
86d70e53
JK		 2619
2620 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2621
2622 return 0;
bc7f75fa
AK		 2623}
2624
86d70e53
JK		 2625/**
2626 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2627 * @adapter: board private structure to initialize
2628 **/
2629static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2630{
2631 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2632 struct e1000_hw *hw = &adapter->hw;
2633 u32 rctl;
bc7f75fa 2634
86d70e53
JK		 2635 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2636 /* disable VLAN receive filtering */
2637 rctl = er32(RCTL);
2638 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2639 ew32(RCTL, rctl);
2640
2641 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2642 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2643 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2644 }
bc7f75fa
AK		 2645 }
2646}
2647
86d70e53
JK		 2648/**
2649 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2650 * @adapter: board private structure to initialize
2651 **/
2652static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2653{
2654 struct e1000_hw *hw = &adapter->hw;
2655 u32 rctl;
2656
2657 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2658 /* enable VLAN receive filtering */
2659 rctl = er32(RCTL);
2660 rctl |= E1000_RCTL_VFE;
2661 rctl &= ~E1000_RCTL_CFIEN;
2662 ew32(RCTL, rctl);
2663 }
2664}
bc7f75fa 2665
86d70e53
JK		 2666/**
2667 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2668 * @adapter: board private structure to initialize
2669 **/
2670static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2671{
bc7f75fa 2672 struct e1000_hw *hw = &adapter->hw;
86d70e53 2673 u32 ctrl;
bc7f75fa 2674
86d70e53
JK		 2675 /* disable VLAN tag insert/strip */
2676 ctrl = er32(CTRL);
2677 ctrl &= ~E1000_CTRL_VME;
2678 ew32(CTRL, ctrl);
2679}
bc7f75fa 2680
86d70e53
JK		 2681/**
2682 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2683 * @adapter: board private structure to initialize
2684 **/
2685static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2686{
2687 struct e1000_hw *hw = &adapter->hw;
2688 u32 ctrl;
bc7f75fa 2689
86d70e53
JK		 2690 /* enable VLAN tag insert/strip */
2691 ctrl = er32(CTRL);
2692 ctrl |= E1000_CTRL_VME;
2693 ew32(CTRL, ctrl);
2694}
bc7f75fa 2695
86d70e53
JK		 2696static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2697{
2698 struct net_device *netdev = adapter->netdev;
2699 u16 vid = adapter->hw.mng_cookie.vlan_id;
2700 u16 old_vid = adapter->mng_vlan_id;
2701
2702 if (adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2704 e1000_vlan_rx_add_vid(netdev, vid);
2705 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2706 }
2707
86d70e53
JK		 2708 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2709 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2710}
2711
2712static void e1000_restore_vlan(struct e1000_adapter *adapter)
2713{
2714 u16 vid;
2715
86d70e53 2716 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2717
86d70e53 2718 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2719 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2720}
2721
cd791618 2722static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2723{
2724 struct e1000_hw *hw = &adapter->hw;
cd791618 2725 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2726
2727 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2728 return;
2729
2730 manc = er32(MANC);
2731
ad68076e
BA		 2732 /*
2733 * enable receiving management packets to the host. this will probably
bc7f75fa 2734 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2735 * the packets will be handled on SMBUS
2736 */
bc7f75fa
AK		 2737 manc |= E1000_MANC_EN_MNG2HOST;
2738 manc2h = er32(MANC2H);
cd791618
BA		 2739
2740 switch (hw->mac.type) {
2741 default:
2742 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2743 break;
2744 case e1000_82574:
2745 case e1000_82583:
2746 /*
2747 * Check if IPMI pass-through decision filter already exists;
2748 * if so, enable it.
2749 */
2750 for (i = 0, j = 0; i < 8; i++) {
2751 mdef = er32(MDEF(i));
2752
2753 /* Ignore filters with anything other than IPMI ports */
3b21b508 2754 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2755 continue;
2756
2757 /* Enable this decision filter in MANC2H */
2758 if (mdef)
2759 manc2h |= (1 << i);
2760
2761 j |= mdef;
2762 }
2763
2764 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2765 break;
2766
2767 /* Create new decision filter in an empty filter */
2768 for (i = 0, j = 0; i < 8; i++)
2769 if (er32(MDEF(i)) == 0) {
2770 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2771 E1000_MDEF_PORT_664));
2772 manc2h |= (1 << 1);
2773 j++;
2774 break;
2775 }
2776
2777 if (!j)
2778 e_warn("Unable to create IPMI pass-through filter\n");
2779 break;
2780 }
2781
bc7f75fa
AK		 2782 ew32(MANC2H, manc2h);
2783 ew32(MANC, manc);
2784}
2785
2786/**
af667a29 2787 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2788 * @adapter: board private structure
2789 *
2790 * Configure the Tx unit of the MAC after a reset.
2791 **/
2792static void e1000_configure_tx(struct e1000_adapter *adapter)
2793{
2794 struct e1000_hw *hw = &adapter->hw;
2795 struct e1000_ring *tx_ring = adapter->tx_ring;
2796 u64 tdba;
c550b121 2797 u32 tdlen, tarc;
bc7f75fa
AK		 2798
2799 /* Setup the HW Tx Head and Tail descriptor pointers */
2800 tdba = tx_ring->dma;
2801 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2802 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2803 ew32(TDBAH(0), (tdba >> 32));
2804 ew32(TDLEN(0), tdlen);
2805 ew32(TDH(0), 0);
2806 ew32(TDT(0), 0);
2807 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2808 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2809
bc7f75fa
AK		 2810 /* Set the Tx Interrupt Delay register */
2811 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2812 /* Tx irq moderation */
bc7f75fa
AK		 2813 ew32(TADV, adapter->tx_abs_int_delay);
2814
3a3b7586
JB		 2815 if (adapter->flags2 & FLAG2_DMA_BURST) {
2816 u32 txdctl = er32(TXDCTL(0));
2817 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2818 E1000_TXDCTL_WTHRESH);
2819 /*
2820 * set up some performance related parameters to encourage the
2821 * hardware to use the bus more efficiently in bursts, depends
2822 * on the tx_int_delay to be enabled,
2823 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2824 * hthresh = 1 ==> prefetch when one or more available
2825 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2826 * BEWARE: this seems to work but should be considered first if
af667a29 2827 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2828 */
2829 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2830 ew32(TXDCTL(0), txdctl);
3a3b7586 2831 }
56032be7
BA		 2832 /* erratum work around: set txdctl the same for both queues */
2833 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2834
bc7f75fa 2835 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2836 tarc = er32(TARC(0));
ad68076e
BA		 2837 /*
2838 * set the speed mode bit, we'll clear it if we're not at
2839 * gigabit link later
2840 */
bc7f75fa
AK		 2841#define SPEED_MODE_BIT (1 << 21)
2842 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2843 ew32(TARC(0), tarc);
bc7f75fa
AK		 2844 }
2845
2846 /* errata: program both queues to unweighted RR */
2847 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2848 tarc = er32(TARC(0));
bc7f75fa 2849 tarc |= 1;
e9ec2c0f
JK		 2850 ew32(TARC(0), tarc);
2851 tarc = er32(TARC(1));
bc7f75fa 2852 tarc |= 1;
e9ec2c0f 2853 ew32(TARC(1), tarc);
bc7f75fa
AK		 2854 }
2855
bc7f75fa
AK		 2856 /* Setup Transmit Descriptor Settings for eop descriptor */
2857 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2858
2859 /* only set IDE if we are delaying interrupts using the timers */
2860 if (adapter->tx_int_delay)
2861 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2862
2863 /* enable Report Status bit */
2864 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2865
57cde763 2866 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2867}
2868
2869/**
2870 * e1000_setup_rctl - configure the receive control registers
2871 * @adapter: Board private structure
2872 **/
2873#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2874 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2875static void e1000_setup_rctl(struct e1000_adapter *adapter)
2876{
2877 struct e1000_hw *hw = &adapter->hw;
2878 u32 rctl, rfctl;
bc7f75fa
AK		 2879 u32 pages = 0;
2880
a1ce6473
BA		 2881 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2882 if (hw->mac.type == e1000_pch2lan) {
2883 s32 ret_val;
2884
2885 if (adapter->netdev->mtu > ETH_DATA_LEN)
2886 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2887 else
2888 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2889
2890 if (ret_val)
2891 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2892 }
2893
bc7f75fa
AK		 2894 /* Program MC offset vector base */
2895 rctl = er32(RCTL);
2896 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2897 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2898 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2899 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2900
2901 /* Do not Store bad packets */
2902 rctl &= ~E1000_RCTL_SBP;
2903
2904 /* Enable Long Packet receive */
2905 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2906 rctl &= ~E1000_RCTL_LPE;
2907 else
2908 rctl |= E1000_RCTL_LPE;
2909
eb7c3adb
JK		 2910 /* Some systems expect that the CRC is included in SMBUS traffic. The
2911 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2912 * host memory when this is enabled
2913 */
2914 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2915 rctl |= E1000_RCTL_SECRC;
5918bd88 2916
a4f58f54
BA		 2917 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2918 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2919 u16 phy_data;
2920
2921 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2922 phy_data &= 0xfff8;
2923 phy_data |= (1 << 2);
2924 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2925
2926 e1e_rphy(hw, 22, &phy_data);
2927 phy_data &= 0x0fff;
2928 phy_data |= (1 << 14);
2929 e1e_wphy(hw, 0x10, 0x2823);
2930 e1e_wphy(hw, 0x11, 0x0003);
2931 e1e_wphy(hw, 22, phy_data);
2932 }
2933
bc7f75fa
AK		 2934 /* Setup buffer sizes */
2935 rctl &= ~E1000_RCTL_SZ_4096;
2936 rctl |= E1000_RCTL_BSEX;
2937 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2938 case 2048:
2939 default:
2940 rctl |= E1000_RCTL_SZ_2048;
2941 rctl &= ~E1000_RCTL_BSEX;
2942 break;
2943 case 4096:
2944 rctl |= E1000_RCTL_SZ_4096;
2945 break;
2946 case 8192:
2947 rctl |= E1000_RCTL_SZ_8192;
2948 break;
2949 case 16384:
2950 rctl |= E1000_RCTL_SZ_16384;
2951 break;
2952 }
2953
5f450212
BA		 2954 /* Enable Extended Status in all Receive Descriptors */
2955 rfctl = er32(RFCTL);
2956 rfctl |= E1000_RFCTL_EXTEN;
2957
bc7f75fa
AK		 2958 /*
2959 * 82571 and greater support packet-split where the protocol
2960 * header is placed in skb->data and the packet data is
2961 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2962 * In the case of a non-split, skb->data is linearly filled,
2963 * followed by the page buffers. Therefore, skb->data is
2964 * sized to hold the largest protocol header.
2965 *
2966 * allocations using alloc_page take too long for regular MTU
2967 * so only enable packet split for jumbo frames
2968 *
2969 * Using pages when the page size is greater than 16k wastes
2970 * a lot of memory, since we allocate 3 pages at all times
2971 * per packet.
2972 */
bc7f75fa 2973 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2974 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2975 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2976 else
2977 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2978
2979 if (adapter->rx_ps_pages) {
90da0669
BA		 2980 u32 psrctl = 0;
2981
ad68076e
BA		 2982 /*
2983 * disable packet split support for IPv6 extension headers,
2984 * because some malformed IPv6 headers can hang the Rx
2985 */
bc7f75fa
AK		 2986 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2987 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2988
140a7480
AK		 2989 /* Enable Packet split descriptors */
2990 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2991
2992 psrctl |= adapter->rx_ps_bsize0 >>
2993 E1000_PSRCTL_BSIZE0_SHIFT;
2994
2995 switch (adapter->rx_ps_pages) {
2996 case 3:
2997 psrctl |= PAGE_SIZE <<
2998 E1000_PSRCTL_BSIZE3_SHIFT;
2999 case 2:
3000 psrctl |= PAGE_SIZE <<
3001 E1000_PSRCTL_BSIZE2_SHIFT;
3002 case 1:
3003 psrctl |= PAGE_SIZE >>
3004 E1000_PSRCTL_BSIZE1_SHIFT;
3005 break;
3006 }
3007
3008 ew32(PSRCTL, psrctl);
3009 }
3010
cf955e6c
BG		 3011 /* This is useful for sniffing bad packets. */
3012 if (adapter->netdev->features & NETIF_F_RXALL) {
3013 /* UPE and MPE will be handled by normal PROMISC logic
3014 * in e1000e_set_rx_mode */
3015 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3016 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3017 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3018
3019 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3020 E1000_RCTL_DPF | /* Allow filtered pause */
3021 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3022 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3023 * and that breaks VLANs.
3024 */
3025 }
3026
5f450212 3027 ew32(RFCTL, rfctl);
bc7f75fa 3028 ew32(RCTL, rctl);
318a94d6
JK		 3029 /* just started the receive unit, no need to restart */
3030 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3031}
3032
3033/**
3034 * e1000_configure_rx - Configure Receive Unit after Reset
3035 * @adapter: board private structure
3036 *
3037 * Configure the Rx unit of the MAC after a reset.
3038 **/
3039static void e1000_configure_rx(struct e1000_adapter *adapter)
3040{
3041 struct e1000_hw *hw = &adapter->hw;
3042 struct e1000_ring *rx_ring = adapter->rx_ring;
3043 u64 rdba;
3044 u32 rdlen, rctl, rxcsum, ctrl_ext;
3045
3046 if (adapter->rx_ps_pages) {
3047 /* this is a 32 byte descriptor */
3048 rdlen = rx_ring->count *
af667a29 3049 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3050 adapter->clean_rx = e1000_clean_rx_irq_ps;
3051 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3052 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3053 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3054 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3055 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3056 } else {
5f450212 3057 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3058 adapter->clean_rx = e1000_clean_rx_irq;
3059 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3060 }
3061
3062 /* disable receives while setting up the descriptors */
3063 rctl = er32(RCTL);
7f99ae63
BA		 3064 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3065 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3066 e1e_flush();
1bba4386 3067 usleep_range(10000, 20000);
bc7f75fa 3068
3a3b7586
JB		 3069 if (adapter->flags2 & FLAG2_DMA_BURST) {
3070 /*
3071 * set the writeback threshold (only takes effect if the RDTR
3072 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3073 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3074 * granularity = 01
3075 * wthresh = 04,
3076 * hthresh = 04,
3077 * pthresh = 0x20
3078 */
3079 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3080 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3081
3082 /*
3083 * override the delay timers for enabling bursting, only if
3084 * the value was not set by the user via module options
3085 */
3086 if (adapter->rx_int_delay == DEFAULT_RDTR)
3087 adapter->rx_int_delay = BURST_RDTR;
3088 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3089 adapter->rx_abs_int_delay = BURST_RADV;
3090 }
3091
bc7f75fa
AK		 3092 /* set the Receive Delay Timer Register */
3093 ew32(RDTR, adapter->rx_int_delay);
3094
3095 /* irq moderation */
3096 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3097 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3098 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3099
3100 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3101 /* Auto-Mask interrupts upon ICR access */
3102 ctrl_ext |= E1000_CTRL_EXT_IAME;
3103 ew32(IAM, 0xffffffff);
3104 ew32(CTRL_EXT, ctrl_ext);
3105 e1e_flush();
3106
ad68076e
BA		 3107 /*
3108 * Setup the HW Rx Head and Tail Descriptor Pointers and
3109 * the Base and Length of the Rx Descriptor Ring
3110 */
bc7f75fa 3111 rdba = rx_ring->dma;
1e36052e
BA		 3112 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3113 ew32(RDBAH(0), (rdba >> 32));
3114 ew32(RDLEN(0), rdlen);
3115 ew32(RDH(0), 0);
3116 ew32(RDT(0), 0);
3117 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3118 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3119
3120 /* Enable Receive Checksum Offload for TCP and UDP */
3121 rxcsum = er32(RXCSUM);
dc221294 3122 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3123 rxcsum |= E1000_RXCSUM_TUOFL;
3124
ad68076e
BA		 3125 /*
3126 * IPv4 payload checksum for UDP fragments must be
3127 * used in conjunction with packet-split.
3128 */
bc7f75fa
AK		 3129 if (adapter->rx_ps_pages)
3130 rxcsum |= E1000_RXCSUM_IPPCSE;
3131 } else {
3132 rxcsum &= ~E1000_RXCSUM_TUOFL;
3133 /* no need to clear IPPCSE as it defaults to 0 */
3134 }
3135 ew32(RXCSUM, rxcsum);
3136
79d4e908
BA		 3137 if (adapter->hw.mac.type == e1000_pch2lan) {
3138 /*
3139 * With jumbo frames, excessive C-state transition
3140 * latencies result in dropped transactions.
3141 */
53ec5498
BA		 3142 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3143 u32 rxdctl = er32(RXDCTL(0));
3144 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3145 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3146 } else {
af667a29
BA		 3147 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3148 PM_QOS_DEFAULT_VALUE);
53ec5498 3149 }
97ac8cae 3150 }
bc7f75fa
AK		 3151
3152 /* Enable Receives */
3153 ew32(RCTL, rctl);
3154}
3155
3156/**
ef9b965a
JB		 3157 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3158 * @netdev: network interface device structure
bc7f75fa 3159 *
ef9b965a
JB		 3160 * Writes multicast address list to the MTA hash table.
3161 * Returns: -ENOMEM on failure
3162 * 0 on no addresses written
3163 * X on writing X addresses to MTA
3164 */
3165static int e1000e_write_mc_addr_list(struct net_device *netdev)
3166{
3167 struct e1000_adapter *adapter = netdev_priv(netdev);
3168 struct e1000_hw *hw = &adapter->hw;
3169 struct netdev_hw_addr *ha;
3170 u8 *mta_list;
3171 int i;
3172
3173 if (netdev_mc_empty(netdev)) {
3174 /* nothing to program, so clear mc list */
3175 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3176 return 0;
3177 }
3178
3179 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3180 if (!mta_list)
3181 return -ENOMEM;
3182
3183 /* update_mc_addr_list expects a packed array of only addresses. */
3184 i = 0;
3185 netdev_for_each_mc_addr(ha, netdev)
3186 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3187
3188 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3189 kfree(mta_list);
3190
3191 return netdev_mc_count(netdev);
3192}
3193
3194/**
3195 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3196 * @netdev: network interface device structure
bc7f75fa 3197 *
ef9b965a
JB		 3198 * Writes unicast address list to the RAR table.
3199 * Returns: -ENOMEM on failure/insufficient address space
3200 * 0 on no addresses written
3201 * X on writing X addresses to the RAR table
bc7f75fa 3202 **/
ef9b965a 3203static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3204{
ef9b965a
JB		 3205 struct e1000_adapter *adapter = netdev_priv(netdev);
3206 struct e1000_hw *hw = &adapter->hw;
3207 unsigned int rar_entries = hw->mac.rar_entry_count;
3208 int count = 0;
3209
3210 /* save a rar entry for our hardware address */
3211 rar_entries--;
3212
3213 /* save a rar entry for the LAA workaround */
3214 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3215 rar_entries--;
3216
3217 /* return ENOMEM indicating insufficient memory for addresses */
3218 if (netdev_uc_count(netdev) > rar_entries)
3219 return -ENOMEM;
3220
3221 if (!netdev_uc_empty(netdev) && rar_entries) {
3222 struct netdev_hw_addr *ha;
3223
3224 /*
3225 * write the addresses in reverse order to avoid write
3226 * combining
3227 */
3228 netdev_for_each_uc_addr(ha, netdev) {
3229 if (!rar_entries)
3230 break;
3231 e1000e_rar_set(hw, ha->addr, rar_entries--);
3232 count++;
3233 }
3234 }
3235
3236 /* zero out the remaining RAR entries not used above */
3237 for (; rar_entries > 0; rar_entries--) {
3238 ew32(RAH(rar_entries), 0);
3239 ew32(RAL(rar_entries), 0);
3240 }
3241 e1e_flush();
3242
3243 return count;
bc7f75fa
AK		 3244}
3245
3246/**
ef9b965a 3247 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3248 * @netdev: network interface device structure
3249 *
ef9b965a
JB		 3250 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3251 * address list or the network interface flags are updated. This routine is
3252 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3253 * promiscuous mode, and all-multi behavior.
3254 **/
ef9b965a 3255static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3256{
3257 struct e1000_adapter *adapter = netdev_priv(netdev);
3258 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3259 u32 rctl;
bc7f75fa
AK		 3260
3261 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3262 rctl = er32(RCTL);
3263
ef9b965a
JB		 3264 /* clear the affected bits */
3265 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3266
bc7f75fa
AK		 3267 if (netdev->flags & IFF_PROMISC) {
3268 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3269 /* Do not hardware filter VLANs in promisc mode */
3270 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3271 } else {
ef9b965a 3272 int count;
3d3a1676 3273
746b9f02
PM		 3274 if (netdev->flags & IFF_ALLMULTI) {
3275 rctl |= E1000_RCTL_MPE;
746b9f02 3276 } else {
ef9b965a
JB		 3277 /*
3278 * Write addresses to the MTA, if the attempt fails
3279 * then we should just turn on promiscuous mode so
3280 * that we can at least receive multicast traffic
3281 */
3282 count = e1000e_write_mc_addr_list(netdev);
3283 if (count < 0)
3284 rctl |= E1000_RCTL_MPE;
746b9f02 3285 }
86d70e53 3286 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3287 /*
ef9b965a
JB		 3288 * Write addresses to available RAR registers, if there is not
3289 * sufficient space to store all the addresses then enable
3290 * unicast promiscuous mode
bc7f75fa 3291 */
ef9b965a
JB		 3292 count = e1000e_write_uc_addr_list(netdev);
3293 if (count < 0)
3294 rctl |= E1000_RCTL_UPE;
bc7f75fa 3295 }
86d70e53 3296
ef9b965a
JB		 3297 ew32(RCTL, rctl);
3298
86d70e53
JK		 3299 if (netdev->features & NETIF_F_HW_VLAN_RX)
3300 e1000e_vlan_strip_enable(adapter);
3301 else
3302 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3303}
3304
70495a50
BA		 3305static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3306{
3307 struct e1000_hw *hw = &adapter->hw;
3308 u32 mrqc, rxcsum;
3309 int i;
3310 static const u32 rsskey[10] = {
3311 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3312 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3313 };
3314
3315 /* Fill out hash function seed */
3316 for (i = 0; i < 10; i++)
3317 ew32(RSSRK(i), rsskey[i]);
3318
3319 /* Direct all traffic to queue 0 */
3320 for (i = 0; i < 32; i++)
3321 ew32(RETA(i), 0);
3322
3323 /*
3324 * Disable raw packet checksumming so that RSS hash is placed in
3325 * descriptor on writeback.
3326 */
3327 rxcsum = er32(RXCSUM);
3328 rxcsum |= E1000_RXCSUM_PCSD;
3329
3330 ew32(RXCSUM, rxcsum);
3331
3332 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3333 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3334 E1000_MRQC_RSS_FIELD_IPV6 |
3335 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3336 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3337
3338 ew32(MRQC, mrqc);
3339}
3340
bc7f75fa 3341/**
ad68076e 3342 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3343 * @adapter: private board structure
3344 **/
3345static void e1000_configure(struct e1000_adapter *adapter)
3346{
55aa6985
BA		 3347 struct e1000_ring *rx_ring = adapter->rx_ring;
3348
ef9b965a 3349 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3350
3351 e1000_restore_vlan(adapter);
cd791618 3352 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3353
3354 e1000_configure_tx(adapter);
70495a50
BA		 3355
3356 if (adapter->netdev->features & NETIF_F_RXHASH)
3357 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3358 e1000_setup_rctl(adapter);
3359 e1000_configure_rx(adapter);
55aa6985 3360 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3361}
3362
3363/**
3364 * e1000e_power_up_phy - restore link in case the phy was powered down
3365 * @adapter: address of board private structure
3366 *
3367 * The phy may be powered down to save power and turn off link when the
3368 * driver is unloaded and wake on lan is not enabled (among others)
3369 * *** this routine MUST be followed by a call to e1000e_reset ***
3370 **/
3371void e1000e_power_up_phy(struct e1000_adapter *adapter)
3372{
17f208de
BA		 3373 if (adapter->hw.phy.ops.power_up)
3374 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3375
3376 adapter->hw.mac.ops.setup_link(&adapter->hw);
3377}
3378
3379/**
3380 * e1000_power_down_phy - Power down the PHY
3381 *
17f208de
BA		 3382 * Power down the PHY so no link is implied when interface is down.
3383 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3384 */
3385static void e1000_power_down_phy(struct e1000_adapter *adapter)
3386{
bc7f75fa 3387 /* WoL is enabled */
23b66e2b 3388 if (adapter->wol)
bc7f75fa
AK		 3389 return;
3390
17f208de
BA		 3391 if (adapter->hw.phy.ops.power_down)
3392 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3393}
3394
3395/**
3396 * e1000e_reset - bring the hardware into a known good state
3397 *
3398 * This function boots the hardware and enables some settings that
3399 * require a configuration cycle of the hardware - those cannot be
3400 * set/changed during runtime. After reset the device needs to be
ad68076e 3401 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3402 */
3403void e1000e_reset(struct e1000_adapter *adapter)
3404{
3405 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3406 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3407 struct e1000_hw *hw = &adapter->hw;
3408 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3409 u32 pba = adapter->pba;
bc7f75fa
AK		 3410 u16 hwm;
3411
ad68076e 3412 /* reset Packet Buffer Allocation to default */
318a94d6 3413 ew32(PBA, pba);
df762464 3414
318a94d6 3415 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3416 /*
3417 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3418 * large enough to accommodate two full transmit packets,
3419 * rounded up to the next 1KB and expressed in KB. Likewise,
3420 * the Rx FIFO should be large enough to accommodate at least
3421 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3422 * expressed in KB.
3423 */
df762464 3424 pba = er32(PBA);
bc7f75fa 3425 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3426 tx_space = pba >> 16;
bc7f75fa 3427 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3428 pba &= 0xffff;
ad68076e 3429 /*
af667a29 3430 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3431 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3432 */
3433 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3434 sizeof(struct e1000_tx_desc) -
3435 ETH_FCS_LEN) * 2;
3436 min_tx_space = ALIGN(min_tx_space, 1024);
3437 min_tx_space >>= 10;
3438 /* software strips receive CRC, so leave room for it */
318a94d6 3439 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3440 min_rx_space = ALIGN(min_rx_space, 1024);
3441 min_rx_space >>= 10;
3442
ad68076e
BA		 3443 /*
3444 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3445 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3446 * allocation, take space away from current Rx allocation
3447 */
df762464
AK		 3448 if ((tx_space < min_tx_space) &&
3449 ((min_tx_space - tx_space) < pba)) {
3450 pba -= min_tx_space - tx_space;
bc7f75fa 3451
ad68076e 3452 /*
af667a29 3453 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3454 * adjustment or use Early Receive if available
3455 */
79d4e908 3456 if (pba < min_rx_space)
df762464 3457 pba = min_rx_space;
bc7f75fa 3458 }
df762464
AK		 3459
3460 ew32(PBA, pba);
bc7f75fa
AK		 3461 }
3462
ad68076e
BA		 3463 /*
3464 * flow control settings
3465 *
38eb394e 3466 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3467 * (or the size used for early receive) above it in the Rx FIFO.
3468 * Set it to the lower of:
3469 * - 90% of the Rx FIFO size, and
38eb394e 3470 * - the full Rx FIFO size minus one full frame
ad68076e 3471 */
d3738bb8
BA		 3472 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3473 fc->pause_time = 0xFFFF;
3474 else
3475 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3476 fc->send_xon = true;
d3738bb8
BA		 3477 fc->current_mode = fc->requested_mode;
3478
3479 switch (hw->mac.type) {
79d4e908
BA		 3480 case e1000_ich9lan:
3481 case e1000_ich10lan:
3482 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3483 pba = 14;
3484 ew32(PBA, pba);
3485 fc->high_water = 0x2800;
3486 fc->low_water = fc->high_water - 8;
3487 break;
3488 }
3489 /* fall-through */
d3738bb8 3490 default:
79d4e908
BA		 3491 hwm = min(((pba << 10) * 9 / 10),
3492 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3493
3494 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3495 fc->low_water = fc->high_water - 8;
3496 break;
3497 case e1000_pchlan:
38eb394e
BA		 3498 /*
3499 * Workaround PCH LOM adapter hangs with certain network
3500 * loads. If hangs persist, try disabling Tx flow control.
3501 */
3502 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3503 fc->high_water = 0x3500;
3504 fc->low_water = 0x1500;
3505 } else {
3506 fc->high_water = 0x5000;
3507 fc->low_water = 0x3000;
3508 }
a305595b 3509 fc->refresh_time = 0x1000;
d3738bb8
BA		 3510 break;
3511 case e1000_pch2lan:
3512 fc->high_water = 0x05C20;
3513 fc->low_water = 0x05048;
3514 fc->pause_time = 0x0650;
3515 fc->refresh_time = 0x0400;
828bac87
BA		 3516 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3517 pba = 14;
3518 ew32(PBA, pba);
3519 }
d3738bb8 3520 break;
38eb394e 3521 }
bc7f75fa 3522
828bac87
BA		 3523 /*
3524 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3525 * fit in receive buffer.
828bac87
BA		 3526 */
3527 if (adapter->itr_setting & 0x3) {
79d4e908 3528 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3529 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3530 dev_info(&adapter->pdev->dev,
3531 "Interrupt Throttle Rate turned off\n");
3532 adapter->flags2 |= FLAG2_DISABLE_AIM;
3533 ew32(ITR, 0);
3534 }
3535 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3536 dev_info(&adapter->pdev->dev,
3537 "Interrupt Throttle Rate turned on\n");
3538 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3539 adapter->itr = 20000;
3540 ew32(ITR, 1000000000 / (adapter->itr * 256));
3541 }
3542 }
3543
bc7f75fa
AK		 3544 /* Allow time for pending master requests to run */
3545 mac->ops.reset_hw(hw);
97ac8cae
BA		 3546
3547 /*
3548 * For parts with AMT enabled, let the firmware know
3549 * that the network interface is in control
3550 */
c43bc57e 3551 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3552 e1000e_get_hw_control(adapter);
97ac8cae 3553
bc7f75fa
AK		 3554 ew32(WUC, 0);
3555
3556 if (mac->ops.init_hw(hw))
44defeb3 3557 e_err("Hardware Error\n");
bc7f75fa
AK		 3558
3559 e1000_update_mng_vlan(adapter);
3560
3561 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3562 ew32(VET, ETH_P_8021Q);
3563
3564 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3565
3566 if (!netif_running(adapter->netdev) &&
3567 !test_bit(__E1000_TESTING, &adapter->state)) {
3568 e1000_power_down_phy(adapter);
3569 return;
3570 }
3571
bc7f75fa
AK		 3572 e1000_get_phy_info(hw);
3573
918d7197
BA		 3574 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3575 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3576 u16 phy_data = 0;
ad68076e
BA		 3577 /*
3578 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3579 * the return value of this function because there is nothing
ad68076e
BA		 3580 * different we would do if it failed
3581 */
bc7f75fa
AK		 3582 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3583 phy_data &= ~IGP02E1000_PM_SPD;
3584 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3585 }
bc7f75fa
AK		 3586}
3587
3588int e1000e_up(struct e1000_adapter *adapter)
3589{
3590 struct e1000_hw *hw = &adapter->hw;
3591
3592 /* hardware has been reset, we need to reload some things */
3593 e1000_configure(adapter);
3594
3595 clear_bit(__E1000_DOWN, &adapter->state);
3596
4662e82b
BA		 3597 if (adapter->msix_entries)
3598 e1000_configure_msix(adapter);
bc7f75fa
AK		 3599 e1000_irq_enable(adapter);
3600
400484fa 3601 netif_start_queue(adapter->netdev);
4cb9be7a 3602
bc7f75fa 3603 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3604 if (adapter->msix_entries)
3605 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3606 else
3607 ew32(ICS, E1000_ICS_LSC);
3608
bc7f75fa
AK		 3609 return 0;
3610}
3611
713b3c9e
JB		 3612static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3613{
3614 struct e1000_hw *hw = &adapter->hw;
3615
3616 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3617 return;
3618
3619 /* flush pending descriptor writebacks to memory */
3620 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3621 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3622
3623 /* execute the writes immediately */
3624 e1e_flush();
bf03085f
MV		 3625
3626 /*
3627 * due to rare timing issues, write to TIDV/RDTR again to ensure the
3628 * write is successful
3629 */
3630 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3631 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3632
3633 /* execute the writes immediately */
3634 e1e_flush();
3635}
3636
67fd4fcb
JK		 3637static void e1000e_update_stats(struct e1000_adapter *adapter);
3638
bc7f75fa
AK		 3639void e1000e_down(struct e1000_adapter *adapter)
3640{
3641 struct net_device *netdev = adapter->netdev;
3642 struct e1000_hw *hw = &adapter->hw;
3643 u32 tctl, rctl;
3644
ad68076e
BA		 3645 /*
3646 * signal that we're down so the interrupt handler does not
3647 * reschedule our watchdog timer
3648 */
bc7f75fa
AK		 3649 set_bit(__E1000_DOWN, &adapter->state);
3650
3651 /* disable receives in the hardware */
3652 rctl = er32(RCTL);
7f99ae63
BA		 3653 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3654 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3655 /* flush and sleep below */
3656
4cb9be7a 3657 netif_stop_queue(netdev);
bc7f75fa
AK		 3658
3659 /* disable transmits in the hardware */
3660 tctl = er32(TCTL);
3661 tctl &= ~E1000_TCTL_EN;
3662 ew32(TCTL, tctl);
7f99ae63 3663
bc7f75fa
AK		 3664 /* flush both disables and wait for them to finish */
3665 e1e_flush();
1bba4386 3666 usleep_range(10000, 20000);
bc7f75fa 3667
bc7f75fa
AK		 3668 e1000_irq_disable(adapter);
3669
3670 del_timer_sync(&adapter->watchdog_timer);
3671 del_timer_sync(&adapter->phy_info_timer);
3672
bc7f75fa 3673 netif_carrier_off(netdev);
67fd4fcb
JK		 3674
3675 spin_lock(&adapter->stats64_lock);
3676 e1000e_update_stats(adapter);
3677 spin_unlock(&adapter->stats64_lock);
3678
400484fa 3679 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3680 e1000_clean_tx_ring(adapter->tx_ring);
3681 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3682
bc7f75fa
AK		 3683 adapter->link_speed = 0;
3684 adapter->link_duplex = 0;
3685
52cc3086
JK		 3686 if (!pci_channel_offline(adapter->pdev))
3687 e1000e_reset(adapter);
713b3c9e 3688
bc7f75fa
AK		 3689 /*
3690 * TODO: for power management, we could drop the link and
3691 * pci_disable_device here.
3692 */
3693}
3694
3695void e1000e_reinit_locked(struct e1000_adapter *adapter)
3696{
3697 might_sleep();
3698 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3699 usleep_range(1000, 2000);
bc7f75fa
AK		 3700 e1000e_down(adapter);
3701 e1000e_up(adapter);
3702 clear_bit(__E1000_RESETTING, &adapter->state);
3703}
3704
3705/**
3706 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3707 * @adapter: board private structure to initialize
3708 *
3709 * e1000_sw_init initializes the Adapter private data structure.
3710 * Fields are initialized based on PCI device information and
3711 * OS network device settings (MTU size).
3712 **/
3713static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3714{
bc7f75fa
AK		 3715 struct net_device *netdev = adapter->netdev;
3716
3717 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3718 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3719 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3720 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3721 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3722 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3723
67fd4fcb
JK		 3724 spin_lock_init(&adapter->stats64_lock);
3725
4662e82b 3726 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3727
4662e82b
BA		 3728 if (e1000_alloc_queues(adapter))
3729 return -ENOMEM;
bc7f75fa 3730
bc7f75fa 3731 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3732 e1000_irq_disable(adapter);
3733
bc7f75fa
AK		 3734 set_bit(__E1000_DOWN, &adapter->state);
3735 return 0;
bc7f75fa
AK		 3736}
3737
f8d59f78
BA		 3738/**
3739 * e1000_intr_msi_test - Interrupt Handler
3740 * @irq: interrupt number
3741 * @data: pointer to a network interface device structure
3742 **/
3743static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3744{
3745 struct net_device *netdev = data;
3746 struct e1000_adapter *adapter = netdev_priv(netdev);
3747 struct e1000_hw *hw = &adapter->hw;
3748 u32 icr = er32(ICR);
3749
3bb99fe2 3750 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3751 if (icr & E1000_ICR_RXSEQ) {
3752 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3753 wmb();
3754 }
3755
3756 return IRQ_HANDLED;
3757}
3758
3759/**
3760 * e1000_test_msi_interrupt - Returns 0 for successful test
3761 * @adapter: board private struct
3762 *
3763 * code flow taken from tg3.c
3764 **/
3765static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3766{
3767 struct net_device *netdev = adapter->netdev;
3768 struct e1000_hw *hw = &adapter->hw;
3769 int err;
3770
3771 /* poll_enable hasn't been called yet, so don't need disable */
3772 /* clear any pending events */
3773 er32(ICR);
3774
3775 /* free the real vector and request a test handler */
3776 e1000_free_irq(adapter);
4662e82b 3777 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3778
3779 /* Assume that the test fails, if it succeeds then the test
3780 * MSI irq handler will unset this flag */
3781 adapter->flags |= FLAG_MSI_TEST_FAILED;
3782
3783 err = pci_enable_msi(adapter->pdev);
3784 if (err)
3785 goto msi_test_failed;
3786
a0607fd3 3787 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3788 netdev->name, netdev);
3789 if (err) {
3790 pci_disable_msi(adapter->pdev);
3791 goto msi_test_failed;
3792 }
3793
3794 wmb();
3795
3796 e1000_irq_enable(adapter);
3797
3798 /* fire an unusual interrupt on the test handler */
3799 ew32(ICS, E1000_ICS_RXSEQ);
3800 e1e_flush();
3801 msleep(50);
3802
3803 e1000_irq_disable(adapter);
3804
3805 rmb();
3806
3807 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3808 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3809 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3810 } else {
068e8a30 3811 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3812 }
f8d59f78
BA		 3813
3814 free_irq(adapter->pdev->irq, netdev);
3815 pci_disable_msi(adapter->pdev);
3816
f8d59f78 3817msi_test_failed:
4662e82b 3818 e1000e_set_interrupt_capability(adapter);
068e8a30 3819 return e1000_request_irq(adapter);
f8d59f78
BA		 3820}
3821
3822/**
3823 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3824 * @adapter: board private struct
3825 *
3826 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3827 **/
3828static int e1000_test_msi(struct e1000_adapter *adapter)
3829{
3830 int err;
3831 u16 pci_cmd;
3832
3833 if (!(adapter->flags & FLAG_MSI_ENABLED))
3834 return 0;
3835
3836 /* disable SERR in case the MSI write causes a master abort */
3837 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3838 if (pci_cmd & PCI_COMMAND_SERR)
3839 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3840 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3841
3842 err = e1000_test_msi_interrupt(adapter);
3843
36f2407f
DN		 3844 /* re-enable SERR */
3845 if (pci_cmd & PCI_COMMAND_SERR) {
3846 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3847 pci_cmd |= PCI_COMMAND_SERR;
3848 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3849 }
f8d59f78 3850
f8d59f78
BA		 3851 return err;
3852}
3853
bc7f75fa
AK		 3854/**
3855 * e1000_open - Called when a network interface is made active
3856 * @netdev: network interface device structure
3857 *
3858 * Returns 0 on success, negative value on failure
3859 *
3860 * The open entry point is called when a network interface is made
3861 * active by the system (IFF_UP). At this point all resources needed
3862 * for transmit and receive operations are allocated, the interrupt
3863 * handler is registered with the OS, the watchdog timer is started,
3864 * and the stack is notified that the interface is ready.
3865 **/
3866static int e1000_open(struct net_device *netdev)
3867{
3868 struct e1000_adapter *adapter = netdev_priv(netdev);
3869 struct e1000_hw *hw = &adapter->hw;
23606cf5 3870 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3871 int err;
3872
3873 /* disallow open during test */
3874 if (test_bit(__E1000_TESTING, &adapter->state))
3875 return -EBUSY;
3876
23606cf5
RW		 3877 pm_runtime_get_sync(&pdev->dev);
3878
9c563d20
JB		 3879 netif_carrier_off(netdev);
3880
bc7f75fa 3881 /* allocate transmit descriptors */
55aa6985 3882 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3883 if (err)
3884 goto err_setup_tx;
3885
3886 /* allocate receive descriptors */
55aa6985 3887 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3888 if (err)
3889 goto err_setup_rx;
3890
11b08be8
BA		 3891 /*
3892 * If AMT is enabled, let the firmware know that the network
3893 * interface is now open and reset the part to a known state.
3894 */
3895 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3896 e1000e_get_hw_control(adapter);
11b08be8
BA		 3897 e1000e_reset(adapter);
3898 }
3899
bc7f75fa
AK		 3900 e1000e_power_up_phy(adapter);
3901
3902 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3903 if ((adapter->hw.mng_cookie.status &
3904 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3905 e1000_update_mng_vlan(adapter);
3906
79d4e908
BA		 3907 /* DMA latency requirement to workaround jumbo issue */
3908 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3909 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3910 PM_QOS_CPU_DMA_LATENCY,
3911 PM_QOS_DEFAULT_VALUE);
c128ec29 3912
ad68076e
BA		 3913 /*
3914 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3915 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3916 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3917 * clean_rx handler before we do so.
3918 */
bc7f75fa
AK		 3919 e1000_configure(adapter);
3920
3921 err = e1000_request_irq(adapter);
3922 if (err)
3923 goto err_req_irq;
3924
f8d59f78
BA		 3925 /*
3926 * Work around PCIe errata with MSI interrupts causing some chipsets to
3927 * ignore e1000e MSI messages, which means we need to test our MSI
3928 * interrupt now
3929 */
4662e82b 3930 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3931 err = e1000_test_msi(adapter);
3932 if (err) {
3933 e_err("Interrupt allocation failed\n");
3934 goto err_req_irq;
3935 }
3936 }
3937
bc7f75fa
AK		 3938 /* From here on the code is the same as e1000e_up() */
3939 clear_bit(__E1000_DOWN, &adapter->state);
3940
3941 napi_enable(&adapter->napi);
3942
3943 e1000_irq_enable(adapter);
3944
09357b00 3945 adapter->tx_hang_recheck = false;
4cb9be7a 3946 netif_start_queue(netdev);
d55b53ff 3947
23606cf5
RW		 3948 adapter->idle_check = true;
3949 pm_runtime_put(&pdev->dev);
3950
bc7f75fa 3951 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3952 if (adapter->msix_entries)
3953 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3954 else
3955 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3956
3957 return 0;
3958
3959err_req_irq:
31dbe5b4 3960 e1000e_release_hw_control(adapter);
bc7f75fa 3961 e1000_power_down_phy(adapter);
55aa6985 3962 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3963err_setup_rx:
55aa6985 3964 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3965err_setup_tx:
3966 e1000e_reset(adapter);
23606cf5 3967 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3968
3969 return err;
3970}
3971
3972/**
3973 * e1000_close - Disables a network interface
3974 * @netdev: network interface device structure
3975 *
3976 * Returns 0, this is not allowed to fail
3977 *
3978 * The close entry point is called when an interface is de-activated
3979 * by the OS. The hardware is still under the drivers control, but
3980 * needs to be disabled. A global MAC reset is issued to stop the
3981 * hardware, and all transmit and receive resources are freed.
3982 **/
3983static int e1000_close(struct net_device *netdev)
3984{
3985 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3986 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 3987 int count = E1000_CHECK_RESET_COUNT;
3988
3989 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
3990 usleep_range(10000, 20000);
bc7f75fa
AK		 3991
3992 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3993
3994 pm_runtime_get_sync(&pdev->dev);
3995
5f4a780d
BA		 3996 napi_disable(&adapter->napi);
3997
23606cf5
RW		 3998 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3999 e1000e_down(adapter);
4000 e1000_free_irq(adapter);
4001 }
bc7f75fa 4002 e1000_power_down_phy(adapter);
bc7f75fa 4003
55aa6985
BA		 4004 e1000e_free_tx_resources(adapter->tx_ring);
4005 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4006
ad68076e
BA		 4007 /*
4008 * kill manageability vlan ID if supported, but not if a vlan with
4009 * the same ID is registered on the host OS (let 8021q kill it)
4010 */
86d70e53
JK		 4011 if (adapter->hw.mng_cookie.status &
4012 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4013 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4014
ad68076e
BA		 4015 /*
4016 * If AMT is enabled, let the firmware know that the network
4017 * interface is now closed
4018 */
31dbe5b4
BA		 4019 if ((adapter->flags & FLAG_HAS_AMT) &&
4020 !test_bit(__E1000_TESTING, &adapter->state))
4021 e1000e_release_hw_control(adapter);
bc7f75fa 4022
79d4e908 4023 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4024 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4025
23606cf5
RW		 4026 pm_runtime_put_sync(&pdev->dev);
4027
bc7f75fa
AK		 4028 return 0;
4029}
4030/**
4031 * e1000_set_mac - Change the Ethernet Address of the NIC
4032 * @netdev: network interface device structure
4033 * @p: pointer to an address structure
4034 *
4035 * Returns 0 on success, negative on failure
4036 **/
4037static int e1000_set_mac(struct net_device *netdev, void *p)
4038{
4039 struct e1000_adapter *adapter = netdev_priv(netdev);
4040 struct sockaddr *addr = p;
4041
4042 if (!is_valid_ether_addr(addr->sa_data))
4043 return -EADDRNOTAVAIL;
4044
4045 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4046 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4047
4048 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4049
4050 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4051 /* activate the work around */
4052 e1000e_set_laa_state_82571(&adapter->hw, 1);
4053
ad68076e
BA		 4054 /*
4055 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4056 * between the time RAR[0] gets clobbered and the time it
4057 * gets fixed (in e1000_watchdog), the actual LAA is in one
4058 * of the RARs and no incoming packets directed to this port
4059 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4060 * RAR[14]
4061 */
bc7f75fa
AK		 4062 e1000e_rar_set(&adapter->hw,
4063 adapter->hw.mac.addr,
4064 adapter->hw.mac.rar_entry_count - 1);
4065 }
4066
4067 return 0;
4068}
4069
a8f88ff5
JB		 4070/**
4071 * e1000e_update_phy_task - work thread to update phy
4072 * @work: pointer to our work struct
4073 *
4074 * this worker thread exists because we must acquire a
4075 * semaphore to read the phy, which we could msleep while
4076 * waiting for it, and we can't msleep in a timer.
4077 **/
4078static void e1000e_update_phy_task(struct work_struct *work)
4079{
4080 struct e1000_adapter *adapter = container_of(work,
4081 struct e1000_adapter, update_phy_task);
615b32af
JB		 4082
4083 if (test_bit(__E1000_DOWN, &adapter->state))
4084 return;
4085
a8f88ff5
JB		 4086 e1000_get_phy_info(&adapter->hw);
4087}
4088
ad68076e
BA		 4089/*
4090 * Need to wait a few seconds after link up to get diagnostic information from
4091 * the phy
4092 */
bc7f75fa
AK		 4093static void e1000_update_phy_info(unsigned long data)
4094{
4095 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4096
4097 if (test_bit(__E1000_DOWN, &adapter->state))
4098 return;
4099
a8f88ff5 4100 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4101}
4102
8c7bbb92
BA		 4103/**
4104 * e1000e_update_phy_stats - Update the PHY statistics counters
4105 * @adapter: board private structure
2b6b168d
BA		 4106 *
4107 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4108 **/
4109static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4110{
4111 struct e1000_hw *hw = &adapter->hw;
4112 s32 ret_val;
4113 u16 phy_data;
4114
4115 ret_val = hw->phy.ops.acquire(hw);
4116 if (ret_val)
4117 return;
4118
8c7bbb92
BA		 4119 /*
4120 * A page set is expensive so check if already on desired page.
4121 * If not, set to the page with the PHY status registers.
4122 */
2b6b168d 4123 hw->phy.addr = 1;
8c7bbb92
BA		 4124 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4125 &phy_data);
4126 if (ret_val)
4127 goto release;
2b6b168d
BA		 4128 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4129 ret_val = hw->phy.ops.set_page(hw,
4130 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4131 if (ret_val)
4132 goto release;
4133 }
4134
8c7bbb92 4135 /* Single Collision Count */
2b6b168d
BA		 4136 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4137 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4138 if (!ret_val)
4139 adapter->stats.scc += phy_data;
4140
4141 /* Excessive Collision Count */
2b6b168d
BA		 4142 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4143 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4144 if (!ret_val)
4145 adapter->stats.ecol += phy_data;
4146
4147 /* Multiple Collision Count */
2b6b168d
BA		 4148 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4149 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4150 if (!ret_val)
4151 adapter->stats.mcc += phy_data;
4152
4153 /* Late Collision Count */
2b6b168d
BA		 4154 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4155 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4156 if (!ret_val)
4157 adapter->stats.latecol += phy_data;
4158
4159 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4160 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4161 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4162 if (!ret_val)
4163 hw->mac.collision_delta = phy_data;
4164
4165 /* Defer Count */
2b6b168d
BA		 4166 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4167 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4168 if (!ret_val)
4169 adapter->stats.dc += phy_data;
4170
4171 /* Transmit with no CRS */
2b6b168d
BA		 4172 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4173 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4174 if (!ret_val)
4175 adapter->stats.tncrs += phy_data;
4176
4177release:
4178 hw->phy.ops.release(hw);
4179}
4180
bc7f75fa
AK		 4181/**
4182 * e1000e_update_stats - Update the board statistics counters
4183 * @adapter: board private structure
4184 **/
67fd4fcb 4185static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4186{
7274c20f 4187 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4188 struct e1000_hw *hw = &adapter->hw;
4189 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4190
4191 /*
4192 * Prevent stats update while adapter is being reset, or if the pci
4193 * connection is down.
4194 */
4195 if (adapter->link_speed == 0)
4196 return;
4197 if (pci_channel_offline(pdev))
4198 return;
4199
bc7f75fa
AK		 4200 adapter->stats.crcerrs += er32(CRCERRS);
4201 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4202 adapter->stats.gorc += er32(GORCL);
4203 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4204 adapter->stats.bprc += er32(BPRC);
4205 adapter->stats.mprc += er32(MPRC);
4206 adapter->stats.roc += er32(ROC);
4207
bc7f75fa 4208 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4209
4210 /* Half-duplex statistics */
4211 if (adapter->link_duplex == HALF_DUPLEX) {
4212 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4213 e1000e_update_phy_stats(adapter);
4214 } else {
4215 adapter->stats.scc += er32(SCC);
4216 adapter->stats.ecol += er32(ECOL);
4217 adapter->stats.mcc += er32(MCC);
4218 adapter->stats.latecol += er32(LATECOL);
4219 adapter->stats.dc += er32(DC);
4220
4221 hw->mac.collision_delta = er32(COLC);
4222
4223 if ((hw->mac.type != e1000_82574) &&
4224 (hw->mac.type != e1000_82583))
4225 adapter->stats.tncrs += er32(TNCRS);
4226 }
4227 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4228 }
8c7bbb92 4229
bc7f75fa
AK		 4230 adapter->stats.xonrxc += er32(XONRXC);
4231 adapter->stats.xontxc += er32(XONTXC);
4232 adapter->stats.xoffrxc += er32(XOFFRXC);
4233 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4234 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4235 adapter->stats.gotc += er32(GOTCL);
4236 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4237 adapter->stats.rnbc += er32(RNBC);
4238 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4239
4240 adapter->stats.mptc += er32(MPTC);
4241 adapter->stats.bptc += er32(BPTC);
4242
4243 /* used for adaptive IFS */
4244
4245 hw->mac.tx_packet_delta = er32(TPT);
4246 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4247
4248 adapter->stats.algnerrc += er32(ALGNERRC);
4249 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4250 adapter->stats.cexterr += er32(CEXTERR);
4251 adapter->stats.tsctc += er32(TSCTC);
4252 adapter->stats.tsctfc += er32(TSCTFC);
4253
bc7f75fa 4254 /* Fill out the OS statistics structure */
7274c20f
AK		 4255 netdev->stats.multicast = adapter->stats.mprc;
4256 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4257
4258 /* Rx Errors */
4259
ad68076e
BA		 4260 /*
4261 * RLEC on some newer hardware can be incorrect so build
4262 * our own version based on RUC and ROC
4263 */
7274c20f 4264 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4265 adapter->stats.crcerrs + adapter->stats.algnerrc +
4266 adapter->stats.ruc + adapter->stats.roc +
4267 adapter->stats.cexterr;
7274c20f 4268 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4269 adapter->stats.roc;
7274c20f
AK		 4270 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4271 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4272 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4273
4274 /* Tx Errors */
7274c20f 4275 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4276 adapter->stats.latecol;
7274c20f
AK		 4277 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4278 netdev->stats.tx_window_errors = adapter->stats.latecol;
4279 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4280
4281 /* Tx Dropped needs to be maintained elsewhere */
4282
bc7f75fa
AK		 4283 /* Management Stats */
4284 adapter->stats.mgptc += er32(MGTPTC);
4285 adapter->stats.mgprc += er32(MGTPRC);
4286 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4287}
4288
7c25769f
BA		 4289/**
4290 * e1000_phy_read_status - Update the PHY register status snapshot
4291 * @adapter: board private structure
4292 **/
4293static void e1000_phy_read_status(struct e1000_adapter *adapter)
4294{
4295 struct e1000_hw *hw = &adapter->hw;
4296 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4297
4298 if ((er32(STATUS) & E1000_STATUS_LU) &&
4299 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4300 int ret_val;
4301
7c25769f
BA		 4302 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4303 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4304 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4305 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4306 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4307 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4308 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4309 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4310 if (ret_val)
44defeb3 4311 e_warn("Error reading PHY register\n");
7c25769f
BA		 4312 } else {
4313 /*
4314 * Do not read PHY registers if link is not up
4315 * Set values to typical power-on defaults
4316 */
4317 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4318 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4319 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4320 BMSR_ERCAP);
4321 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4322 ADVERTISE_ALL | ADVERTISE_CSMA);
4323 phy->lpa = 0;
4324 phy->expansion = EXPANSION_ENABLENPAGE;
4325 phy->ctrl1000 = ADVERTISE_1000FULL;
4326 phy->stat1000 = 0;
4327 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4328 }
7c25769f
BA		 4329}
4330
bc7f75fa
AK		 4331static void e1000_print_link_info(struct e1000_adapter *adapter)
4332{
bc7f75fa
AK		 4333 struct e1000_hw *hw = &adapter->hw;
4334 u32 ctrl = er32(CTRL);
4335
8f12fe86 4336 /* Link status message must follow this format for user tools */
ef456f85
JK		 4337 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4338 adapter->netdev->name,
4339 adapter->link_speed,
4340 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4341 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4342 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4343 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4344}
4345
0c6bdb30 4346static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4347{
4348 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4349 bool link_active = false;
318a94d6
JK		 4350 s32 ret_val = 0;
4351
4352 /*
4353 * get_link_status is set on LSC (link status) interrupt or
4354 * Rx sequence error interrupt. get_link_status will stay
4355 * false until the check_for_link establishes link
4356 * for copper adapters ONLY
4357 */
4358 switch (hw->phy.media_type) {
4359 case e1000_media_type_copper:
4360 if (hw->mac.get_link_status) {
4361 ret_val = hw->mac.ops.check_for_link(hw);
4362 link_active = !hw->mac.get_link_status;
4363 } else {
3db1cd5c 4364 link_active = true;
318a94d6
JK		 4365 }
4366 break;
4367 case e1000_media_type_fiber:
4368 ret_val = hw->mac.ops.check_for_link(hw);
4369 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4370 break;
4371 case e1000_media_type_internal_serdes:
4372 ret_val = hw->mac.ops.check_for_link(hw);
4373 link_active = adapter->hw.mac.serdes_has_link;
4374 break;
4375 default:
4376 case e1000_media_type_unknown:
4377 break;
4378 }
4379
4380 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4381 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4382 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4383 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4384 }
4385
4386 return link_active;
4387}
4388
4389static void e1000e_enable_receives(struct e1000_adapter *adapter)
4390{
4391 /* make sure the receive unit is started */
4392 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4393 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4394 struct e1000_hw *hw = &adapter->hw;
4395 u32 rctl = er32(RCTL);
4396 ew32(RCTL, rctl | E1000_RCTL_EN);
4397 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4398 }
4399}
4400
ff10e13c
CW		 4401static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4402{
4403 struct e1000_hw *hw = &adapter->hw;
4404
4405 /*
4406 * With 82574 controllers, PHY needs to be checked periodically
4407 * for hung state and reset, if two calls return true
4408 */
4409 if (e1000_check_phy_82574(hw))
4410 adapter->phy_hang_count++;
4411 else
4412 adapter->phy_hang_count = 0;
4413
4414 if (adapter->phy_hang_count > 1) {
4415 adapter->phy_hang_count = 0;
4416 schedule_work(&adapter->reset_task);
4417 }
4418}
4419
bc7f75fa
AK		 4420/**
4421 * e1000_watchdog - Timer Call-back
4422 * @data: pointer to adapter cast into an unsigned long
4423 **/
4424static void e1000_watchdog(unsigned long data)
4425{
4426 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4427
4428 /* Do the rest outside of interrupt context */
4429 schedule_work(&adapter->watchdog_task);
4430
4431 /* TODO: make this use queue_delayed_work() */
4432}
4433
4434static void e1000_watchdog_task(struct work_struct *work)
4435{
4436 struct e1000_adapter *adapter = container_of(work,
4437 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4438 struct net_device *netdev = adapter->netdev;
4439 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4440 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4441 struct e1000_ring *tx_ring = adapter->tx_ring;
4442 struct e1000_hw *hw = &adapter->hw;
4443 u32 link, tctl;
bc7f75fa 4444
615b32af
JB		 4445 if (test_bit(__E1000_DOWN, &adapter->state))
4446 return;
4447
b405e8df 4448 link = e1000e_has_link(adapter);
318a94d6 4449 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4450 /* Cancel scheduled suspend requests. */
4451 pm_runtime_resume(netdev->dev.parent);
4452
318a94d6 4453 e1000e_enable_receives(adapter);
bc7f75fa 4454 goto link_up;
bc7f75fa
AK		 4455 }
4456
4457 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4458 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4459 e1000_update_mng_vlan(adapter);
4460
bc7f75fa
AK		 4461 if (link) {
4462 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4463 bool txb2b = true;
23606cf5
RW		 4464
4465 /* Cancel scheduled suspend requests. */
4466 pm_runtime_resume(netdev->dev.parent);
4467
318a94d6 4468 /* update snapshot of PHY registers on LSC */
7c25769f 4469 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4470 mac->ops.get_link_up_info(&adapter->hw,
4471 &adapter->link_speed,
4472 &adapter->link_duplex);
4473 e1000_print_link_info(adapter);
f4187b56
BA		 4474 /*
4475 * On supported PHYs, check for duplex mismatch only
4476 * if link has autonegotiated at 10/100 half
4477 */
4478 if ((hw->phy.type == e1000_phy_igp_3 ||
4479 hw->phy.type == e1000_phy_bm) &&
4480 (hw->mac.autoneg == true) &&
4481 (adapter->link_speed == SPEED_10 ||
4482 adapter->link_speed == SPEED_100) &&
4483 (adapter->link_duplex == HALF_DUPLEX)) {
4484 u16 autoneg_exp;
4485
4486 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4487
4488 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4489 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4490 }
4491
f49c57e1 4492 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4493 adapter->tx_timeout_factor = 1;
4494 switch (adapter->link_speed) {
4495 case SPEED_10:
3db1cd5c 4496 txb2b = false;
10f1b492 4497 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4498 break;
4499 case SPEED_100:
3db1cd5c 4500 txb2b = false;
4c86e0b9 4501 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4502 break;
4503 }
4504
ad68076e
BA		 4505 /*
4506 * workaround: re-program speed mode bit after
4507 * link-up event
4508 */
bc7f75fa
AK		 4509 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4510 !txb2b) {
4511 u32 tarc0;
e9ec2c0f 4512 tarc0 = er32(TARC(0));
bc7f75fa 4513 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4514 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4515 }
4516
ad68076e
BA		 4517 /*
4518 * disable TSO for pcie and 10/100 speeds, to avoid
4519 * some hardware issues
4520 */
bc7f75fa
AK		 4521 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4522 switch (adapter->link_speed) {
4523 case SPEED_10:
4524 case SPEED_100:
44defeb3 4525 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4526 netdev->features &= ~NETIF_F_TSO;
4527 netdev->features &= ~NETIF_F_TSO6;
4528 break;
4529 case SPEED_1000:
4530 netdev->features |= NETIF_F_TSO;
4531 netdev->features |= NETIF_F_TSO6;
4532 break;
4533 default:
4534 /* oops */
4535 break;
4536 }
4537 }
4538
ad68076e
BA		 4539 /*
4540 * enable transmits in the hardware, need to do this
4541 * after setting TARC(0)
4542 */
bc7f75fa
AK		 4543 tctl = er32(TCTL);
4544 tctl |= E1000_TCTL_EN;
4545 ew32(TCTL, tctl);
4546
75eb0fad
BA		 4547 /*
4548 * Perform any post-link-up configuration before
4549 * reporting link up.
4550 */
4551 if (phy->ops.cfg_on_link_up)
4552 phy->ops.cfg_on_link_up(hw);
4553
bc7f75fa 4554 netif_carrier_on(netdev);
bc7f75fa
AK		 4555
4556 if (!test_bit(__E1000_DOWN, &adapter->state))
4557 mod_timer(&adapter->phy_info_timer,
4558 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4559 }
4560 } else {
4561 if (netif_carrier_ok(netdev)) {
4562 adapter->link_speed = 0;
4563 adapter->link_duplex = 0;
8f12fe86
BA		 4564 /* Link status message must follow this format */
4565 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4566 adapter->netdev->name);
bc7f75fa 4567 netif_carrier_off(netdev);
bc7f75fa
AK		 4568 if (!test_bit(__E1000_DOWN, &adapter->state))
4569 mod_timer(&adapter->phy_info_timer,
4570 round_jiffies(jiffies + 2 * HZ));
4571
4572 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4573 schedule_work(&adapter->reset_task);
23606cf5
RW		 4574 else
4575 pm_schedule_suspend(netdev->dev.parent,
4576 LINK_TIMEOUT);
bc7f75fa
AK		 4577 }
4578 }
4579
4580link_up:
67fd4fcb 4581 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4582 e1000e_update_stats(adapter);
4583
4584 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4585 adapter->tpt_old = adapter->stats.tpt;
4586 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4587 adapter->colc_old = adapter->stats.colc;
4588
7c25769f
BA		 4589 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4590 adapter->gorc_old = adapter->stats.gorc;
4591 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4592 adapter->gotc_old = adapter->stats.gotc;
2084b114 4593 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4594
4595 e1000e_update_adaptive(&adapter->hw);
4596
90da0669
BA		 4597 if (!netif_carrier_ok(netdev) &&
4598 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4599 /*
4600 * We've lost link, so the controller stops DMA,
4601 * but we've got queued Tx work that's never going
4602 * to get done, so reset controller to flush Tx.
4603 * (Do the reset outside of interrupt context).
4604 */
90da0669
BA		 4605 schedule_work(&adapter->reset_task);
4606 /* return immediately since reset is imminent */
4607 return;
bc7f75fa
AK		 4608 }
4609
eab2abf5
JB		 4610 /* Simple mode for Interrupt Throttle Rate (ITR) */
4611 if (adapter->itr_setting == 4) {
4612 /*
4613 * Symmetric Tx/Rx gets a reduced ITR=2000;
4614 * Total asymmetrical Tx or Rx gets ITR=8000;
4615 * everyone else is between 2000-8000.
4616 */
4617 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4618 u32 dif = (adapter->gotc > adapter->gorc ?
4619 adapter->gotc - adapter->gorc :
4620 adapter->gorc - adapter->gotc) / 10000;
4621 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4622
4623 ew32(ITR, 1000000000 / (itr * 256));
4624 }
4625
ad68076e 4626 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4627 if (adapter->msix_entries)
4628 ew32(ICS, adapter->rx_ring->ims_val);
4629 else
4630 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4631
713b3c9e
JB		 4632 /* flush pending descriptors to memory before detecting Tx hang */
4633 e1000e_flush_descriptors(adapter);
4634
bc7f75fa 4635 /* Force detection of hung controller every watchdog period */
3db1cd5c 4636 adapter->detect_tx_hung = true;
bc7f75fa 4637
ad68076e
BA		 4638 /*
4639 * With 82571 controllers, LAA may be overwritten due to controller
4640 * reset from the other port. Set the appropriate LAA in RAR[0]
4641 */
bc7f75fa
AK		 4642 if (e1000e_get_laa_state_82571(hw))
4643 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4644
ff10e13c
CW		 4645 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4646 e1000e_check_82574_phy_workaround(adapter);
4647
bc7f75fa
AK		 4648 /* Reset the timer */
4649 if (!test_bit(__E1000_DOWN, &adapter->state))
4650 mod_timer(&adapter->watchdog_timer,
4651 round_jiffies(jiffies + 2 * HZ));
4652}
4653
4654#define E1000_TX_FLAGS_CSUM 0x00000001
4655#define E1000_TX_FLAGS_VLAN 0x00000002
4656#define E1000_TX_FLAGS_TSO 0x00000004
4657#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4658#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4659#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4660#define E1000_TX_FLAGS_VLAN_SHIFT 16
4661
55aa6985 4662static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4663{
bc7f75fa
AK		 4664 struct e1000_context_desc *context_desc;
4665 struct e1000_buffer *buffer_info;
4666 unsigned int i;
4667 u32 cmd_length = 0;
4668 u16 ipcse = 0, tucse, mss;
4669 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4670
3d5e33c9
BA		 4671 if (!skb_is_gso(skb))
4672 return 0;
bc7f75fa 4673
3d5e33c9 4674 if (skb_header_cloned(skb)) {
90da0669
BA		 4675 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4676
3d5e33c9
BA		 4677 if (err)
4678 return err;
bc7f75fa
AK		 4679 }
4680
3d5e33c9
BA		 4681 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4682 mss = skb_shinfo(skb)->gso_size;
4683 if (skb->protocol == htons(ETH_P_IP)) {
4684 struct iphdr *iph = ip_hdr(skb);
4685 iph->tot_len = 0;
4686 iph->check = 0;
4687 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4688 0, IPPROTO_TCP, 0);
4689 cmd_length = E1000_TXD_CMD_IP;
4690 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4691 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4692 ipv6_hdr(skb)->payload_len = 0;
4693 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4694 &ipv6_hdr(skb)->daddr,
4695 0, IPPROTO_TCP, 0);
4696 ipcse = 0;
4697 }
4698 ipcss = skb_network_offset(skb);
4699 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4700 tucss = skb_transport_offset(skb);
4701 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4702 tucse = 0;
4703
4704 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4705 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4706
4707 i = tx_ring->next_to_use;
4708 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4709 buffer_info = &tx_ring->buffer_info[i];
4710
4711 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4712 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4713 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4714 context_desc->upper_setup.tcp_fields.tucss = tucss;
4715 context_desc->upper_setup.tcp_fields.tucso = tucso;
4716 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4717 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4718 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4719 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4720
4721 buffer_info->time_stamp = jiffies;
4722 buffer_info->next_to_watch = i;
4723
4724 i++;
4725 if (i == tx_ring->count)
4726 i = 0;
4727 tx_ring->next_to_use = i;
4728
4729 return 1;
bc7f75fa
AK		 4730}
4731
55aa6985 4732static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4733{
55aa6985 4734 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4735 struct e1000_context_desc *context_desc;
4736 struct e1000_buffer *buffer_info;
4737 unsigned int i;
4738 u8 css;
af807c82 4739 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4740 __be16 protocol;
bc7f75fa 4741
af807c82
DG		 4742 if (skb->ip_summed != CHECKSUM_PARTIAL)
4743 return 0;
bc7f75fa 4744
5f66f208
AJ		 4745 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4746 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4747 else
4748 protocol = skb->protocol;
4749
3f518390 4750 switch (protocol) {
09640e63 4751 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4752 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4753 cmd_len |= E1000_TXD_CMD_TCP;
4754 break;
09640e63 4755 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4756 /* XXX not handling all IPV6 headers */
4757 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4758 cmd_len |= E1000_TXD_CMD_TCP;
4759 break;
4760 default:
4761 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4762 e_warn("checksum_partial proto=%x!\n",
4763 be16_to_cpu(protocol));
af807c82 4764 break;
bc7f75fa
AK		 4765 }
4766
0d0b1672 4767 css = skb_checksum_start_offset(skb);
af807c82
DG		 4768
4769 i = tx_ring->next_to_use;
4770 buffer_info = &tx_ring->buffer_info[i];
4771 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4772
4773 context_desc->lower_setup.ip_config = 0;
4774 context_desc->upper_setup.tcp_fields.tucss = css;
4775 context_desc->upper_setup.tcp_fields.tucso =
4776 css + skb->csum_offset;
4777 context_desc->upper_setup.tcp_fields.tucse = 0;
4778 context_desc->tcp_seg_setup.data = 0;
4779 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4780
4781 buffer_info->time_stamp = jiffies;
4782 buffer_info->next_to_watch = i;
4783
4784 i++;
4785 if (i == tx_ring->count)
4786 i = 0;
4787 tx_ring->next_to_use = i;
4788
4789 return 1;
bc7f75fa
AK		 4790}
4791
4792#define E1000_MAX_PER_TXD 8192
4793#define E1000_MAX_TXD_PWR 12
4794
55aa6985
BA		 4795static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4796 unsigned int first, unsigned int max_per_txd,
4797 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4798{
55aa6985 4799 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4800 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4801 struct e1000_buffer *buffer_info;
8ddc951c 4802 unsigned int len = skb_headlen(skb);
03b1320d 4803 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4804 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4805
4806 i = tx_ring->next_to_use;
4807
4808 while (len) {
1b7719c4 4809 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4810 size = min(len, max_per_txd);
4811
bc7f75fa 4812 buffer_info->length = size;
bc7f75fa 4813 buffer_info->time_stamp = jiffies;
bc7f75fa 4814 buffer_info->next_to_watch = i;
0be3f55f
NN		 4815 buffer_info->dma = dma_map_single(&pdev->dev,
4816 skb->data + offset,
af667a29 4817 size, DMA_TO_DEVICE);
03b1320d 4818 buffer_info->mapped_as_page = false;
0be3f55f 4819 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4820 goto dma_error;
bc7f75fa
AK		 4821
4822 len -= size;
4823 offset += size;
03b1320d 4824 count++;
1b7719c4
AD		 4825
4826 if (len) {
4827 i++;
4828 if (i == tx_ring->count)
4829 i = 0;
4830 }
bc7f75fa
AK		 4831 }
4832
4833 for (f = 0; f < nr_frags; f++) {
9e903e08 4834 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4835
4836 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4837 len = skb_frag_size(frag);
877749bf 4838 offset = 0;
bc7f75fa
AK		 4839
4840 while (len) {
1b7719c4
AD		 4841 i++;
4842 if (i == tx_ring->count)
4843 i = 0;
4844
bc7f75fa
AK		 4845 buffer_info = &tx_ring->buffer_info[i];
4846 size = min(len, max_per_txd);
bc7f75fa
AK		 4847
4848 buffer_info->length = size;
4849 buffer_info->time_stamp = jiffies;
bc7f75fa 4850 buffer_info->next_to_watch = i;
877749bf
IC		 4851 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4852 offset, size, DMA_TO_DEVICE);
03b1320d 4853 buffer_info->mapped_as_page = true;
0be3f55f 4854 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4855 goto dma_error;
bc7f75fa
AK		 4856
4857 len -= size;
4858 offset += size;
4859 count++;
bc7f75fa
AK		 4860 }
4861 }
4862
af667a29 4863 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4864 /* multiply data chunks by size of headers */
4865 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4866
bc7f75fa 4867 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4868 tx_ring->buffer_info[i].segs = segs;
4869 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4870 tx_ring->buffer_info[first].next_to_watch = i;
4871
4872 return count;
03b1320d
AD		 4873
4874dma_error:
af667a29 4875 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4876 buffer_info->dma = 0;
c1fa347f 4877 if (count)
03b1320d 4878 count--;
c1fa347f
RK		 4879
4880 while (count--) {
af667a29 4881 if (i == 0)
03b1320d 4882 i += tx_ring->count;
c1fa347f 4883 i--;
03b1320d 4884 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4885 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4886 }
4887
4888 return 0;
bc7f75fa
AK		 4889}
4890
55aa6985 4891static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4892{
55aa6985 4893 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4894 struct e1000_tx_desc *tx_desc = NULL;
4895 struct e1000_buffer *buffer_info;
4896 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4897 unsigned int i;
4898
4899 if (tx_flags & E1000_TX_FLAGS_TSO) {
4900 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4901 E1000_TXD_CMD_TSE;
4902 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4903
4904 if (tx_flags & E1000_TX_FLAGS_IPV4)
4905 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4906 }
4907
4908 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4909 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4910 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4911 }
4912
4913 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4914 txd_lower |= E1000_TXD_CMD_VLE;
4915 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4916 }
4917
943146de
BG		 4918 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4919 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4920
bc7f75fa
AK		 4921 i = tx_ring->next_to_use;
4922
36b973df 4923 do {
bc7f75fa
AK		 4924 buffer_info = &tx_ring->buffer_info[i];
4925 tx_desc = E1000_TX_DESC(*tx_ring, i);
4926 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4927 tx_desc->lower.data =
4928 cpu_to_le32(txd_lower | buffer_info->length);
4929 tx_desc->upper.data = cpu_to_le32(txd_upper);
4930
4931 i++;
4932 if (i == tx_ring->count)
4933 i = 0;
36b973df 4934 } while (--count > 0);
bc7f75fa
AK		 4935
4936 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4937
943146de
BG		 4938 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4939 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4940 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4941
ad68076e
BA		 4942 /*
4943 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4944 * know there are new descriptors to fetch. (Only
4945 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4946 * such as IA-64).
4947 */
bc7f75fa
AK		 4948 wmb();
4949
4950 tx_ring->next_to_use = i;
c6e7f51e
BA		 4951
4952 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4953 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4954 else
c5083cf6 4955 writel(i, tx_ring->tail);
c6e7f51e 4956
ad68076e
BA		 4957 /*
4958 * we need this if more than one processor can write to our tail
4959 * at a time, it synchronizes IO on IA64/Altix systems
4960 */
bc7f75fa
AK		 4961 mmiowb();
4962}
4963
4964#define MINIMUM_DHCP_PACKET_SIZE 282
4965static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4966 struct sk_buff *skb)
4967{
4968 struct e1000_hw *hw = &adapter->hw;
4969 u16 length, offset;
4970
4971 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4972 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4973 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4974 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4975 return 0;
4976 }
4977
4978 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4979 return 0;
4980
4981 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4982 return 0;
4983
4984 {
4985 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4986 struct udphdr *udp;
4987
4988 if (ip->protocol != IPPROTO_UDP)
4989 return 0;
4990
4991 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4992 if (ntohs(udp->dest) != 67)
4993 return 0;
4994
4995 offset = (u8 *)udp + 8 - skb->data;
4996 length = skb->len - offset;
4997 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4998 }
4999
5000 return 0;
5001}
5002
55aa6985 5003static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5004{
55aa6985 5005 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5006
55aa6985 5007 netif_stop_queue(adapter->netdev);
ad68076e
BA		 5008 /*
5009 * Herbert's original patch had:
bc7f75fa 5010 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5011 * but since that doesn't exist yet, just open code it.
5012 */
bc7f75fa
AK		 5013 smp_mb();
5014
ad68076e
BA		 5015 /*
5016 * We need to check again in a case another CPU has just
5017 * made room available.
5018 */
55aa6985 5019 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5020 return -EBUSY;
5021
5022 /* A reprieve! */
55aa6985 5023 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5024 ++adapter->restart_queue;
5025 return 0;
5026}
5027
55aa6985 5028static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5029{
55aa6985 5030 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5031 return 0;
55aa6985 5032 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5033}
5034
0e15df49 5035#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 5036static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5037 struct net_device *netdev)
bc7f75fa
AK		 5038{
5039 struct e1000_adapter *adapter = netdev_priv(netdev);
5040 struct e1000_ring *tx_ring = adapter->tx_ring;
5041 unsigned int first;
5042 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5043 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5044 unsigned int tx_flags = 0;
e743d313 5045 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5046 unsigned int nr_frags;
5047 unsigned int mss;
bc7f75fa
AK		 5048 int count = 0;
5049 int tso;
5050 unsigned int f;
bc7f75fa
AK		 5051
5052 if (test_bit(__E1000_DOWN, &adapter->state)) {
5053 dev_kfree_skb_any(skb);
5054 return NETDEV_TX_OK;
5055 }
5056
5057 if (skb->len <= 0) {
5058 dev_kfree_skb_any(skb);
5059 return NETDEV_TX_OK;
5060 }
5061
5062 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5063 /*
5064 * The controller does a simple calculation to
bc7f75fa
AK		 5065 * make sure there is enough room in the FIFO before
5066 * initiating the DMA for each buffer. The calc is:
5067 * 4 = ceil(buffer len/mss). To make sure we don't
5068 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5069 * drops.
5070 */
bc7f75fa
AK		 5071 if (mss) {
5072 u8 hdr_len;
5073 max_per_txd = min(mss << 2, max_per_txd);
5074 max_txd_pwr = fls(max_per_txd) - 1;
5075
ad68076e
BA		 5076 /*
5077 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5078 * points to just header, pull a few bytes of payload from
5079 * frags into skb->data
5080 */
bc7f75fa 5081 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5082 /*
5083 * we do this workaround for ES2LAN, but it is un-necessary,
5084 * avoiding it could save a lot of cycles
5085 */
4e6c709c 5086 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5087 unsigned int pull_size;
5088
a2a5b323 5089 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5090 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5091 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5092 dev_kfree_skb_any(skb);
5093 return NETDEV_TX_OK;
5094 }
e743d313 5095 len = skb_headlen(skb);
bc7f75fa
AK		 5096 }
5097 }
5098
5099 /* reserve a descriptor for the offload context */
5100 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5101 count++;
5102 count++;
5103
5104 count += TXD_USE_COUNT(len, max_txd_pwr);
5105
5106 nr_frags = skb_shinfo(skb)->nr_frags;
5107 for (f = 0; f < nr_frags; f++)
9e903e08 5108 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5109 max_txd_pwr);
5110
5111 if (adapter->hw.mac.tx_pkt_filtering)
5112 e1000_transfer_dhcp_info(adapter, skb);
5113
ad68076e
BA		 5114 /*
5115 * need: count + 2 desc gap to keep tail from touching
5116 * head, otherwise try next time
5117 */
55aa6985 5118 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5119 return NETDEV_TX_BUSY;
bc7f75fa 5120
eab6d18d 5121 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5122 tx_flags |= E1000_TX_FLAGS_VLAN;
5123 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5124 }
5125
5126 first = tx_ring->next_to_use;
5127
55aa6985 5128 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5129 if (tso < 0) {
5130 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5131 return NETDEV_TX_OK;
5132 }
5133
5134 if (tso)
5135 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5136 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5137 tx_flags |= E1000_TX_FLAGS_CSUM;
5138
ad68076e
BA		 5139 /*
5140 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5141 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5142 * no longer assume, we must.
5143 */
bc7f75fa
AK		 5144 if (skb->protocol == htons(ETH_P_IP))
5145 tx_flags |= E1000_TX_FLAGS_IPV4;
5146
943146de
BG		 5147 if (unlikely(skb->no_fcs))
5148 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5149
25985edc 5150 /* if count is 0 then mapping error has occurred */
55aa6985 5151 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5152 if (count) {
3f0cfa3b 5153 netdev_sent_queue(netdev, skb->len);
55aa6985 5154 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5155 /* Make sure there is space in the ring for the next send. */
55aa6985 5156 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5157
5158 } else {
bc7f75fa 5159 dev_kfree_skb_any(skb);
1b7719c4
AD		 5160 tx_ring->buffer_info[first].time_stamp = 0;
5161 tx_ring->next_to_use = first;
bc7f75fa
AK		 5162 }
5163
bc7f75fa
AK		 5164 return NETDEV_TX_OK;
5165}
5166
5167/**
5168 * e1000_tx_timeout - Respond to a Tx Hang
5169 * @netdev: network interface device structure
5170 **/
5171static void e1000_tx_timeout(struct net_device *netdev)
5172{
5173 struct e1000_adapter *adapter = netdev_priv(netdev);
5174
5175 /* Do the reset outside of interrupt context */
5176 adapter->tx_timeout_count++;
5177 schedule_work(&adapter->reset_task);
5178}
5179
5180static void e1000_reset_task(struct work_struct *work)
5181{
5182 struct e1000_adapter *adapter;
5183 adapter = container_of(work, struct e1000_adapter, reset_task);
5184
615b32af
JB		 5185 /* don't run the task if already down */
5186 if (test_bit(__E1000_DOWN, &adapter->state))
5187 return;
5188
affa9dfb
CW		 5189 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5190 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5191 e1000e_dump(adapter);
5192 e_err("Reset adapter\n");
5193 }
bc7f75fa
AK		 5194 e1000e_reinit_locked(adapter);
5195}
5196
5197/**
67fd4fcb 5198 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5199 * @netdev: network interface device structure
67fd4fcb 5200 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5201 *
5202 * Returns the address of the device statistics structure.
bc7f75fa 5203 **/
67fd4fcb
JK		 5204struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5205 struct rtnl_link_stats64 *stats)
bc7f75fa 5206{
67fd4fcb
JK		 5207 struct e1000_adapter *adapter = netdev_priv(netdev);
5208
5209 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5210 spin_lock(&adapter->stats64_lock);
5211 e1000e_update_stats(adapter);
5212 /* Fill out the OS statistics structure */
5213 stats->rx_bytes = adapter->stats.gorc;
5214 stats->rx_packets = adapter->stats.gprc;
5215 stats->tx_bytes = adapter->stats.gotc;
5216 stats->tx_packets = adapter->stats.gptc;
5217 stats->multicast = adapter->stats.mprc;
5218 stats->collisions = adapter->stats.colc;
5219
5220 /* Rx Errors */
5221
5222 /*
5223 * RLEC on some newer hardware can be incorrect so build
5224 * our own version based on RUC and ROC
5225 */
5226 stats->rx_errors = adapter->stats.rxerrc +
5227 adapter->stats.crcerrs + adapter->stats.algnerrc +
5228 adapter->stats.ruc + adapter->stats.roc +
5229 adapter->stats.cexterr;
5230 stats->rx_length_errors = adapter->stats.ruc +
5231 adapter->stats.roc;
5232 stats->rx_crc_errors = adapter->stats.crcerrs;
5233 stats->rx_frame_errors = adapter->stats.algnerrc;
5234 stats->rx_missed_errors = adapter->stats.mpc;
5235
5236 /* Tx Errors */
5237 stats->tx_errors = adapter->stats.ecol +
5238 adapter->stats.latecol;
5239 stats->tx_aborted_errors = adapter->stats.ecol;
5240 stats->tx_window_errors = adapter->stats.latecol;
5241 stats->tx_carrier_errors = adapter->stats.tncrs;
5242
5243 /* Tx Dropped needs to be maintained elsewhere */
5244
5245 spin_unlock(&adapter->stats64_lock);
5246 return stats;
bc7f75fa
AK		 5247}
5248
5249/**
5250 * e1000_change_mtu - Change the Maximum Transfer Unit
5251 * @netdev: network interface device structure
5252 * @new_mtu: new value for maximum frame size
5253 *
5254 * Returns 0 on success, negative on failure
5255 **/
5256static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5257{
5258 struct e1000_adapter *adapter = netdev_priv(netdev);
5259 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5260
2adc55c9 5261 /* Jumbo frame support */
70495a50
BA		 5262 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5263 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5264 e_err("Jumbo Frames not supported.\n");
5265 return -EINVAL;
5266 }
5267
5268 /*
5269 * IP payload checksum (enabled with jumbos/packet-split when
5270 * Rx checksum is enabled) and generation of RSS hash is
5271 * mutually exclusive in the hardware.
5272 */
5273 if ((netdev->features & NETIF_F_RXCSUM) &&
5274 (netdev->features & NETIF_F_RXHASH)) {
5275 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5276 return -EINVAL;
5277 }
bc7f75fa
AK		 5278 }
5279
2adc55c9
BA		 5280 /* Supported frame sizes */
5281 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5282 (max_frame > adapter->max_hw_frame_size)) {
5283 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5284 return -EINVAL;
5285 }
5286
a1ce6473
BA		 5287 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5288 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5289 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5290 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5291 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5292 return -EINVAL;
5293 }
5294
6f461f6c
BA		 5295 /* 82573 Errata 17 */
5296 if (((adapter->hw.mac.type == e1000_82573) ||
5297 (adapter->hw.mac.type == e1000_82574)) &&
5298 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5299 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5300 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5301 }
5302
bc7f75fa 5303 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5304 usleep_range(1000, 2000);
610c9928 5305 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5306 adapter->max_frame_size = max_frame;
610c9928
BA		 5307 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5308 netdev->mtu = new_mtu;
bc7f75fa
AK		 5309 if (netif_running(netdev))
5310 e1000e_down(adapter);
5311
ad68076e
BA		 5312 /*
5313 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5314 * means we reserve 2 more, this pushes us to allocate from the next
5315 * larger slab size.
ad68076e 5316 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5317 * However with the new *_jumbo_rx* routines, jumbo receives will use
5318 * fragmented skbs
ad68076e 5319 */
bc7f75fa 5320
9926146b 5321 if (max_frame <= 2048)
bc7f75fa
AK		 5322 adapter->rx_buffer_len = 2048;
5323 else
5324 adapter->rx_buffer_len = 4096;
5325
5326 /* adjust allocation if LPE protects us, and we aren't using SBP */
5327 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5328 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5329 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5330 + ETH_FCS_LEN;
bc7f75fa 5331
bc7f75fa
AK		 5332 if (netif_running(netdev))
5333 e1000e_up(adapter);
5334 else
5335 e1000e_reset(adapter);
5336
5337 clear_bit(__E1000_RESETTING, &adapter->state);
5338
5339 return 0;
5340}
5341
5342static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5343 int cmd)
5344{
5345 struct e1000_adapter *adapter = netdev_priv(netdev);
5346 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5347
318a94d6 5348 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5349 return -EOPNOTSUPP;
5350
5351 switch (cmd) {
5352 case SIOCGMIIPHY:
5353 data->phy_id = adapter->hw.phy.addr;
5354 break;
5355 case SIOCGMIIREG:
b16a002e
BA		 5356 e1000_phy_read_status(adapter);
5357
7c25769f
BA		 5358 switch (data->reg_num & 0x1F) {
5359 case MII_BMCR:
5360 data->val_out = adapter->phy_regs.bmcr;
5361 break;
5362 case MII_BMSR:
5363 data->val_out = adapter->phy_regs.bmsr;
5364 break;
5365 case MII_PHYSID1:
5366 data->val_out = (adapter->hw.phy.id >> 16);
5367 break;
5368 case MII_PHYSID2:
5369 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5370 break;
5371 case MII_ADVERTISE:
5372 data->val_out = adapter->phy_regs.advertise;
5373 break;
5374 case MII_LPA:
5375 data->val_out = adapter->phy_regs.lpa;
5376 break;
5377 case MII_EXPANSION:
5378 data->val_out = adapter->phy_regs.expansion;
5379 break;
5380 case MII_CTRL1000:
5381 data->val_out = adapter->phy_regs.ctrl1000;
5382 break;
5383 case MII_STAT1000:
5384 data->val_out = adapter->phy_regs.stat1000;
5385 break;
5386 case MII_ESTATUS:
5387 data->val_out = adapter->phy_regs.estatus;
5388 break;
5389 default:
bc7f75fa
AK		 5390 return -EIO;
5391 }
bc7f75fa
AK		 5392 break;
5393 case SIOCSMIIREG:
5394 default:
5395 return -EOPNOTSUPP;
5396 }
5397 return 0;
5398}
5399
5400static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5401{
5402 switch (cmd) {
5403 case SIOCGMIIPHY:
5404 case SIOCGMIIREG:
5405 case SIOCSMIIREG:
5406 return e1000_mii_ioctl(netdev, ifr, cmd);
5407 default:
5408 return -EOPNOTSUPP;
5409 }
5410}
5411
a4f58f54
BA		 5412static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5413{
5414 struct e1000_hw *hw = &adapter->hw;
5415 u32 i, mac_reg;
2b6b168d 5416 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5417 int retval = 0;
5418
5419 /* copy MAC RARs to PHY RARs */
d3738bb8 5420 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5421
2b6b168d
BA		 5422 retval = hw->phy.ops.acquire(hw);
5423 if (retval) {
5424 e_err("Could not acquire PHY\n");
5425 return retval;
5426 }
5427
5428 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5429 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5430 if (retval)
75ce1532 5431 goto release;
2b6b168d
BA		 5432
5433 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5434 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5435 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5436 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5437 (u16)(mac_reg & 0xFFFF));
5438 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5439 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5440 }
5441
5442 /* configure PHY Rx Control register */
2b6b168d 5443 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5444 mac_reg = er32(RCTL);
5445 if (mac_reg & E1000_RCTL_UPE)
5446 phy_reg |= BM_RCTL_UPE;
5447 if (mac_reg & E1000_RCTL_MPE)
5448 phy_reg |= BM_RCTL_MPE;
5449 phy_reg &= ~(BM_RCTL_MO_MASK);
5450 if (mac_reg & E1000_RCTL_MO_3)
5451 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5452 << BM_RCTL_MO_SHIFT);
5453 if (mac_reg & E1000_RCTL_BAM)
5454 phy_reg |= BM_RCTL_BAM;
5455 if (mac_reg & E1000_RCTL_PMCF)
5456 phy_reg |= BM_RCTL_PMCF;
5457 mac_reg = er32(CTRL);
5458 if (mac_reg & E1000_CTRL_RFCE)
5459 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5460 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5461
5462 /* enable PHY wakeup in MAC register */
5463 ew32(WUFC, wufc);
5464 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5465
5466 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5467 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5468 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5469
5470 /* activate PHY wakeup */
2b6b168d
BA		 5471 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5472 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5473 if (retval)
5474 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5475release:
94d8186a 5476 hw->phy.ops.release(hw);
a4f58f54
BA		 5477
5478 return retval;
5479}
5480
23606cf5
RW		 5481static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5482 bool runtime)
bc7f75fa
AK		 5483{
5484 struct net_device *netdev = pci_get_drvdata(pdev);
5485 struct e1000_adapter *adapter = netdev_priv(netdev);
5486 struct e1000_hw *hw = &adapter->hw;
5487 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5488 /* Runtime suspend should only enable wakeup for link changes */
5489 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5490 int retval = 0;
5491
5492 netif_device_detach(netdev);
5493
5494 if (netif_running(netdev)) {
bb9e44d0
BA		 5495 int count = E1000_CHECK_RESET_COUNT;
5496
5497 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5498 usleep_range(10000, 20000);
5499
bc7f75fa
AK		 5500 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5501 e1000e_down(adapter);
5502 e1000_free_irq(adapter);
5503 }
4662e82b 5504 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5505
5506 retval = pci_save_state(pdev);
5507 if (retval)
5508 return retval;
5509
5510 status = er32(STATUS);
5511 if (status & E1000_STATUS_LU)
5512 wufc &= ~E1000_WUFC_LNKC;
5513
5514 if (wufc) {
5515 e1000_setup_rctl(adapter);
ef9b965a 5516 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5517
5518 /* turn on all-multi mode if wake on multicast is enabled */
5519 if (wufc & E1000_WUFC_MC) {
5520 rctl = er32(RCTL);
5521 rctl |= E1000_RCTL_MPE;
5522 ew32(RCTL, rctl);
5523 }
5524
5525 ctrl = er32(CTRL);
5526 /* advertise wake from D3Cold */
5527 #define E1000_CTRL_ADVD3WUC 0x00100000
5528 /* phy power management enable */
5529 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5530 ctrl |= E1000_CTRL_ADVD3WUC;
5531 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5532 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5533 ew32(CTRL, ctrl);
5534
318a94d6
JK		 5535 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5536 adapter->hw.phy.media_type ==
5537 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5538 /* keep the laser running in D3 */
5539 ctrl_ext = er32(CTRL_EXT);
93a23f48 5540 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5541 ew32(CTRL_EXT, ctrl_ext);
5542 }
5543
97ac8cae 5544 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5545 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5546
bc7f75fa
AK		 5547 /* Allow time for pending master requests to run */
5548 e1000e_disable_pcie_master(&adapter->hw);
5549
82776a4b 5550 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5551 /* enable wakeup by the PHY */
5552 retval = e1000_init_phy_wakeup(adapter, wufc);
5553 if (retval)
5554 return retval;
5555 } else {
5556 /* enable wakeup by the MAC */
5557 ew32(WUFC, wufc);
5558 ew32(WUC, E1000_WUC_PME_EN);
5559 }
bc7f75fa
AK		 5560 } else {
5561 ew32(WUC, 0);
5562 ew32(WUFC, 0);
bc7f75fa
AK		 5563 }
5564
4f9de721
RW		 5565 *enable_wake = !!wufc;
5566
bc7f75fa 5567 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5568 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5569 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5570 *enable_wake = true;
bc7f75fa
AK		 5571
5572 if (adapter->hw.phy.type == e1000_phy_igp_3)
5573 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5574
ad68076e
BA		 5575 /*
5576 * Release control of h/w to f/w. If f/w is AMT enabled, this
5577 * would have already happened in close and is redundant.
5578 */
31dbe5b4 5579 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5580
5581 pci_disable_device(pdev);
5582
4f9de721
RW		 5583 return 0;
5584}
5585
5586static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5587{
5588 if (sleep && wake) {
5589 pci_prepare_to_sleep(pdev);
5590 return;
5591 }
5592
5593 pci_wake_from_d3(pdev, wake);
5594 pci_set_power_state(pdev, PCI_D3hot);
5595}
5596
5597static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5598 bool wake)
5599{
5600 struct net_device *netdev = pci_get_drvdata(pdev);
5601 struct e1000_adapter *adapter = netdev_priv(netdev);
5602
005cbdfc
AD		 5603 /*
5604 * The pci-e switch on some quad port adapters will report a
5605 * correctable error when the MAC transitions from D0 to D3. To
5606 * prevent this we need to mask off the correctable errors on the
5607 * downstream port of the pci-e switch.
5608 */
5609 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5610 struct pci_dev *us_dev = pdev->bus->self;
353064de 5611 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5612 u16 devctl;
5613
5614 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5615 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5616 (devctl & ~PCI_EXP_DEVCTL_CERE));
5617
4f9de721 5618 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5619
5620 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5621 } else {
4f9de721 5622 e1000_power_off(pdev, sleep, wake);
005cbdfc 5623 }
bc7f75fa
AK		 5624}
5625
6f461f6c
BA		 5626#ifdef CONFIG_PCIEASPM
5627static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5628{
9f728f53 5629 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5630}
5631#else
5632static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5633{
5634 int pos;
6f461f6c 5635 u16 reg16;
1eae4eb2
AK		 5636
5637 /*
6f461f6c
BA		 5638 * Both device and parent should have the same ASPM setting.
5639 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5640 */
6f461f6c
BA		 5641 pos = pci_pcie_cap(pdev);
5642 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5643 reg16 &= ~state;
5644 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5645
0c75ba22
AB		 5646 if (!pdev->bus->self)
5647 return;
5648
6f461f6c
BA		 5649 pos = pci_pcie_cap(pdev->bus->self);
5650 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5651 reg16 &= ~state;
5652 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5653}
5654#endif
78cd29d5 5655static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5656{
5657 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5658 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5659 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5660
5661 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5662}
5663
aa338601 5664#ifdef CONFIG_PM
23606cf5 5665static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5666{
23606cf5 5667 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5668}
5669
23606cf5 5670static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5671{
5672 struct net_device *netdev = pci_get_drvdata(pdev);
5673 struct e1000_adapter *adapter = netdev_priv(netdev);
5674 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5675 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5676 u32 err;
5677
78cd29d5
BA		 5678 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5679 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5680 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5681 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5682 if (aspm_disable_flag)
5683 e1000e_disable_aspm(pdev, aspm_disable_flag);
5684
bc7f75fa
AK		 5685 pci_set_power_state(pdev, PCI_D0);
5686 pci_restore_state(pdev);
28b8f04a 5687 pci_save_state(pdev);
6e4f6f6b 5688
4662e82b 5689 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5690 if (netif_running(netdev)) {
5691 err = e1000_request_irq(adapter);
5692 if (err)
5693 return err;
5694 }
5695
99730e4c
BA		 5696 if (hw->mac.type == e1000_pch2lan)
5697 e1000_resume_workarounds_pchlan(&adapter->hw);
5698
bc7f75fa 5699 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5700
5701 /* report the system wakeup cause from S3/S4 */
5702 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5703 u16 phy_data;
5704
5705 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5706 if (phy_data) {
5707 e_info("PHY Wakeup cause - %s\n",
5708 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5709 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5710 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5711 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5712 phy_data & E1000_WUS_LNKC ?
5713 "Link Status Change" : "other");
a4f58f54
BA		 5714 }
5715 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5716 } else {
5717 u32 wus = er32(WUS);
5718 if (wus) {
5719 e_info("MAC Wakeup cause - %s\n",
5720 wus & E1000_WUS_EX ? "Unicast Packet" :
5721 wus & E1000_WUS_MC ? "Multicast Packet" :
5722 wus & E1000_WUS_BC ? "Broadcast Packet" :
5723 wus & E1000_WUS_MAG ? "Magic Packet" :
5724 wus & E1000_WUS_LNKC ? "Link Status Change" :
5725 "other");
5726 }
5727 ew32(WUS, ~0);
5728 }
5729
bc7f75fa 5730 e1000e_reset(adapter);
bc7f75fa 5731
cd791618 5732 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5733
5734 if (netif_running(netdev))
5735 e1000e_up(adapter);
5736
5737 netif_device_attach(netdev);
5738
ad68076e
BA		 5739 /*
5740 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5741 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5742 * under the control of the driver.
5743 */
c43bc57e 5744 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5745 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5746
5747 return 0;
5748}
23606cf5 5749
a0340162
RW		 5750#ifdef CONFIG_PM_SLEEP
5751static int e1000_suspend(struct device *dev)
5752{
5753 struct pci_dev *pdev = to_pci_dev(dev);
5754 int retval;
5755 bool wake;
5756
5757 retval = __e1000_shutdown(pdev, &wake, false);
5758 if (!retval)
5759 e1000_complete_shutdown(pdev, true, wake);
5760
5761 return retval;
5762}
5763
23606cf5
RW		 5764static int e1000_resume(struct device *dev)
5765{
5766 struct pci_dev *pdev = to_pci_dev(dev);
5767 struct net_device *netdev = pci_get_drvdata(pdev);
5768 struct e1000_adapter *adapter = netdev_priv(netdev);
5769
5770 if (e1000e_pm_ready(adapter))
5771 adapter->idle_check = true;
5772
5773 return __e1000_resume(pdev);
5774}
a0340162
RW		 5775#endif /* CONFIG_PM_SLEEP */
5776
5777#ifdef CONFIG_PM_RUNTIME
5778static int e1000_runtime_suspend(struct device *dev)
5779{
5780 struct pci_dev *pdev = to_pci_dev(dev);
5781 struct net_device *netdev = pci_get_drvdata(pdev);
5782 struct e1000_adapter *adapter = netdev_priv(netdev);
5783
5784 if (e1000e_pm_ready(adapter)) {
5785 bool wake;
5786
5787 __e1000_shutdown(pdev, &wake, true);
5788 }
5789
5790 return 0;
5791}
5792
5793static int e1000_idle(struct device *dev)
5794{
5795 struct pci_dev *pdev = to_pci_dev(dev);
5796 struct net_device *netdev = pci_get_drvdata(pdev);
5797 struct e1000_adapter *adapter = netdev_priv(netdev);
5798
5799 if (!e1000e_pm_ready(adapter))
5800 return 0;
5801
5802 if (adapter->idle_check) {
5803 adapter->idle_check = false;
5804 if (!e1000e_has_link(adapter))
5805 pm_schedule_suspend(dev, MSEC_PER_SEC);
5806 }
5807
5808 return -EBUSY;
5809}
23606cf5
RW		 5810
5811static int e1000_runtime_resume(struct device *dev)
5812{
5813 struct pci_dev *pdev = to_pci_dev(dev);
5814 struct net_device *netdev = pci_get_drvdata(pdev);
5815 struct e1000_adapter *adapter = netdev_priv(netdev);
5816
5817 if (!e1000e_pm_ready(adapter))
5818 return 0;
5819
5820 adapter->idle_check = !dev->power.runtime_auto;
5821 return __e1000_resume(pdev);
5822}
a0340162 5823#endif /* CONFIG_PM_RUNTIME */
aa338601 5824#endif /* CONFIG_PM */
bc7f75fa
AK		 5825
5826static void e1000_shutdown(struct pci_dev *pdev)
5827{
4f9de721
RW		 5828 bool wake = false;
5829
23606cf5 5830 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5831
5832 if (system_state == SYSTEM_POWER_OFF)
5833 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5834}
5835
5836#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5837
5838static irqreturn_t e1000_intr_msix(int irq, void *data)
5839{
5840 struct net_device *netdev = data;
5841 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5842
5843 if (adapter->msix_entries) {
90da0669
BA		 5844 int vector, msix_irq;
5845
147b2c8c
DD		 5846 vector = 0;
5847 msix_irq = adapter->msix_entries[vector].vector;
5848 disable_irq(msix_irq);
5849 e1000_intr_msix_rx(msix_irq, netdev);
5850 enable_irq(msix_irq);
5851
5852 vector++;
5853 msix_irq = adapter->msix_entries[vector].vector;
5854 disable_irq(msix_irq);
5855 e1000_intr_msix_tx(msix_irq, netdev);
5856 enable_irq(msix_irq);
5857
5858 vector++;
5859 msix_irq = adapter->msix_entries[vector].vector;
5860 disable_irq(msix_irq);
5861 e1000_msix_other(msix_irq, netdev);
5862 enable_irq(msix_irq);
5863 }
5864
5865 return IRQ_HANDLED;
5866}
5867
bc7f75fa
AK		 5868/*
5869 * Polling 'interrupt' - used by things like netconsole to send skbs
5870 * without having to re-enable interrupts. It's not called while
5871 * the interrupt routine is executing.
5872 */
5873static void e1000_netpoll(struct net_device *netdev)
5874{
5875 struct e1000_adapter *adapter = netdev_priv(netdev);
5876
147b2c8c
DD		 5877 switch (adapter->int_mode) {
5878 case E1000E_INT_MODE_MSIX:
5879 e1000_intr_msix(adapter->pdev->irq, netdev);
5880 break;
5881 case E1000E_INT_MODE_MSI:
5882 disable_irq(adapter->pdev->irq);
5883 e1000_intr_msi(adapter->pdev->irq, netdev);
5884 enable_irq(adapter->pdev->irq);
5885 break;
5886 default: /* E1000E_INT_MODE_LEGACY */
5887 disable_irq(adapter->pdev->irq);
5888 e1000_intr(adapter->pdev->irq, netdev);
5889 enable_irq(adapter->pdev->irq);
5890 break;
5891 }
bc7f75fa
AK		 5892}
5893#endif
5894
5895/**
5896 * e1000_io_error_detected - called when PCI error is detected
5897 * @pdev: Pointer to PCI device
5898 * @state: The current pci connection state
5899 *
5900 * This function is called after a PCI bus error affecting
5901 * this device has been detected.
5902 */
5903static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5904 pci_channel_state_t state)
5905{
5906 struct net_device *netdev = pci_get_drvdata(pdev);
5907 struct e1000_adapter *adapter = netdev_priv(netdev);
5908
5909 netif_device_detach(netdev);
5910
c93b5a76
MM		 5911 if (state == pci_channel_io_perm_failure)
5912 return PCI_ERS_RESULT_DISCONNECT;
5913
bc7f75fa
AK		 5914 if (netif_running(netdev))
5915 e1000e_down(adapter);
5916 pci_disable_device(pdev);
5917
5918 /* Request a slot slot reset. */
5919 return PCI_ERS_RESULT_NEED_RESET;
5920}
5921
5922/**
5923 * e1000_io_slot_reset - called after the pci bus has been reset.
5924 * @pdev: Pointer to PCI device
5925 *
5926 * Restart the card from scratch, as if from a cold-boot. Implementation
5927 * resembles the first-half of the e1000_resume routine.
5928 */
5929static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5930{
5931 struct net_device *netdev = pci_get_drvdata(pdev);
5932 struct e1000_adapter *adapter = netdev_priv(netdev);
5933 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5934 u16 aspm_disable_flag = 0;
6e4f6f6b 5935 int err;
111b9dc5 5936 pci_ers_result_t result;
bc7f75fa 5937
78cd29d5
BA		 5938 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5939 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5940 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5941 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5942 if (aspm_disable_flag)
5943 e1000e_disable_aspm(pdev, aspm_disable_flag);
5944
f0f422e5 5945 err = pci_enable_device_mem(pdev);
6e4f6f6b 5946 if (err) {
bc7f75fa
AK		 5947 dev_err(&pdev->dev,
5948 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5949 result = PCI_ERS_RESULT_DISCONNECT;
5950 } else {
5951 pci_set_master(pdev);
23606cf5 5952 pdev->state_saved = true;
111b9dc5 5953 pci_restore_state(pdev);
bc7f75fa 5954
111b9dc5
JB		 5955 pci_enable_wake(pdev, PCI_D3hot, 0);
5956 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5957
111b9dc5
JB		 5958 e1000e_reset(adapter);
5959 ew32(WUS, ~0);
5960 result = PCI_ERS_RESULT_RECOVERED;
5961 }
bc7f75fa 5962
111b9dc5
JB		 5963 pci_cleanup_aer_uncorrect_error_status(pdev);
5964
5965 return result;
bc7f75fa
AK		 5966}
5967
5968/**
5969 * e1000_io_resume - called when traffic can start flowing again.
5970 * @pdev: Pointer to PCI device
5971 *
5972 * This callback is called when the error recovery driver tells us that
5973 * its OK to resume normal operation. Implementation resembles the
5974 * second-half of the e1000_resume routine.
5975 */
5976static void e1000_io_resume(struct pci_dev *pdev)
5977{
5978 struct net_device *netdev = pci_get_drvdata(pdev);
5979 struct e1000_adapter *adapter = netdev_priv(netdev);
5980
cd791618 5981 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5982
5983 if (netif_running(netdev)) {
5984 if (e1000e_up(adapter)) {
5985 dev_err(&pdev->dev,
5986 "can't bring device back up after reset\n");
5987 return;
5988 }
5989 }
5990
5991 netif_device_attach(netdev);
5992
ad68076e
BA		 5993 /*
5994 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5995 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5996 * under the control of the driver.
5997 */
c43bc57e 5998 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5999 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6000
6001}
6002
6003static void e1000_print_device_info(struct e1000_adapter *adapter)
6004{
6005 struct e1000_hw *hw = &adapter->hw;
6006 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6007 u32 ret_val;
6008 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6009
6010 /* print bus type/speed/width info */
a5cc7642 6011 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6012 /* bus width */
6013 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6014 "Width x1"),
6015 /* MAC address */
7c510e4b 6016 netdev->dev_addr);
44defeb3
JK		 6017 e_info("Intel(R) PRO/%s Network Connection\n",
6018 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6019 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6020 E1000_PBANUM_LENGTH);
6021 if (ret_val)
f2315bf1 6022 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6023 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6024 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6025}
6026
10aa4c04
AK		 6027static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6028{
6029 struct e1000_hw *hw = &adapter->hw;
6030 int ret_val;
6031 u16 buf = 0;
6032
6033 if (hw->mac.type != e1000_82573)
6034 return;
6035
6036 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6037 le16_to_cpus(&buf);
6038 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6039 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6040 dev_warn(&adapter->pdev->dev,
6041 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6042 }
10aa4c04
AK		 6043}
6044
c8f44aff 6045static int e1000_set_features(struct net_device *netdev,
70495a50 6046 netdev_features_t features)
dc221294
BA		 6047{
6048 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6049 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6050
6051 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6052 adapter->flags |= FLAG_TSO_FORCE;
6053
6054 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6055 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6056 NETIF_F_RXALL)))
dc221294
BA		 6057 return 0;
6058
70495a50
BA		 6059 /*
6060 * IP payload checksum (enabled with jumbos/packet-split when Rx
6061 * checksum is enabled) and generation of RSS hash is mutually
6062 * exclusive in the hardware.
6063 */
6064 if (adapter->rx_ps_pages &&
6065 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6066 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6067 return -EINVAL;
6068 }
6069
0184039a
BG		 6070 if (changed & NETIF_F_RXFCS) {
6071 if (features & NETIF_F_RXFCS) {
6072 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6073 } else {
6074 /* We need to take it back to defaults, which might mean
6075 * stripping is still disabled at the adapter level.
6076 */
6077 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6078 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6079 else
6080 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6081 }
6082 }
6083
70495a50
BA		 6084 netdev->features = features;
6085
dc221294
BA		 6086 if (netif_running(netdev))
6087 e1000e_reinit_locked(adapter);
6088 else
6089 e1000e_reset(adapter);
6090
6091 return 0;
6092}
6093
651c2466
SH		 6094static const struct net_device_ops e1000e_netdev_ops = {
6095 .ndo_open = e1000_open,
6096 .ndo_stop = e1000_close,
00829823 6097 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6098 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6099 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6100 .ndo_set_mac_address = e1000_set_mac,
6101 .ndo_change_mtu = e1000_change_mtu,
6102 .ndo_do_ioctl = e1000_ioctl,
6103 .ndo_tx_timeout = e1000_tx_timeout,
6104 .ndo_validate_addr = eth_validate_addr,
6105
651c2466
SH		 6106 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6107 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6108#ifdef CONFIG_NET_POLL_CONTROLLER
6109 .ndo_poll_controller = e1000_netpoll,
6110#endif
dc221294 6111 .ndo_set_features = e1000_set_features,
651c2466
SH		 6112};
6113
bc7f75fa
AK		 6114/**
6115 * e1000_probe - Device Initialization Routine
6116 * @pdev: PCI device information struct
6117 * @ent: entry in e1000_pci_tbl
6118 *
6119 * Returns 0 on success, negative on failure
6120 *
6121 * e1000_probe initializes an adapter identified by a pci_dev structure.
6122 * The OS initialization, configuring of the adapter private structure,
6123 * and a hardware reset occur.
6124 **/
6125static int __devinit e1000_probe(struct pci_dev *pdev,
6126 const struct pci_device_id *ent)
6127{
6128 struct net_device *netdev;
6129 struct e1000_adapter *adapter;
6130 struct e1000_hw *hw;
6131 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6132 resource_size_t mmio_start, mmio_len;
6133 resource_size_t flash_start, flash_len;
bc7f75fa 6134 static int cards_found;
78cd29d5 6135 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6136 int i, err, pci_using_dac;
6137 u16 eeprom_data = 0;
6138 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6139
78cd29d5
BA		 6140 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6141 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6142 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6143 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6144 if (aspm_disable_flag)
6145 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6146
f0f422e5 6147 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6148 if (err)
6149 return err;
6150
6151 pci_using_dac = 0;
0be3f55f 6152 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6153 if (!err) {
0be3f55f 6154 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6155 if (!err)
6156 pci_using_dac = 1;
6157 } else {
0be3f55f 6158 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6159 if (err) {
0be3f55f
NN		 6160 err = dma_set_coherent_mask(&pdev->dev,
6161 DMA_BIT_MASK(32));
bc7f75fa 6162 if (err) {
ef456f85 6163 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6164 goto err_dma;
6165 }
6166 }
6167 }
6168
e8de1481 6169 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6170 pci_select_bars(pdev, IORESOURCE_MEM),
6171 e1000e_driver_name);
bc7f75fa
AK		 6172 if (err)
6173 goto err_pci_reg;
6174
68eac460 6175 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6176 pci_enable_pcie_error_reporting(pdev);
68eac460 6177
bc7f75fa 6178 pci_set_master(pdev);
438b365a
BA		 6179 /* PCI config space info */
6180 err = pci_save_state(pdev);
6181 if (err)
6182 goto err_alloc_etherdev;
bc7f75fa
AK		 6183
6184 err = -ENOMEM;
6185 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6186 if (!netdev)
6187 goto err_alloc_etherdev;
6188
bc7f75fa
AK		 6189 SET_NETDEV_DEV(netdev, &pdev->dev);
6190
f85e4dfa
TH		 6191 netdev->irq = pdev->irq;
6192
bc7f75fa
AK		 6193 pci_set_drvdata(pdev, netdev);
6194 adapter = netdev_priv(netdev);
6195 hw = &adapter->hw;
6196 adapter->netdev = netdev;
6197 adapter->pdev = pdev;
6198 adapter->ei = ei;
6199 adapter->pba = ei->pba;
6200 adapter->flags = ei->flags;
eb7c3adb 6201 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6202 adapter->hw.adapter = adapter;
6203 adapter->hw.mac.type = ei->mac;
2adc55c9 6204 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6205 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6206
6207 mmio_start = pci_resource_start(pdev, 0);
6208 mmio_len = pci_resource_len(pdev, 0);
6209
6210 err = -EIO;
6211 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6212 if (!adapter->hw.hw_addr)
6213 goto err_ioremap;
6214
6215 if ((adapter->flags & FLAG_HAS_FLASH) &&
6216 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6217 flash_start = pci_resource_start(pdev, 1);
6218 flash_len = pci_resource_len(pdev, 1);
6219 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6220 if (!adapter->hw.flash_address)
6221 goto err_flashmap;
6222 }
6223
6224 /* construct the net_device struct */
651c2466 6225 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6226 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6227 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6228 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6229 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6230
6231 netdev->mem_start = mmio_start;
6232 netdev->mem_end = mmio_start + mmio_len;
6233
6234 adapter->bd_number = cards_found++;
6235
4662e82b
BA		 6236 e1000e_check_options(adapter);
6237
bc7f75fa
AK		 6238 /* setup adapter struct */
6239 err = e1000_sw_init(adapter);
6240 if (err)
6241 goto err_sw_init;
6242
bc7f75fa
AK		 6243 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6244 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6245 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6246
69e3fd8c 6247 err = ei->get_variants(adapter);
bc7f75fa
AK		 6248 if (err)
6249 goto err_hw_init;
6250
4a770358
BA		 6251 if ((adapter->flags & FLAG_IS_ICH) &&
6252 (adapter->flags & FLAG_READ_ONLY_NVM))
6253 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6254
bc7f75fa
AK		 6255 hw->mac.ops.get_bus_info(&adapter->hw);
6256
318a94d6 6257 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6258
6259 /* Copper options */
318a94d6 6260 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6261 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6262 adapter->hw.phy.disable_polarity_correction = 0;
6263 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6264 }
6265
44abd5c1 6266 if (hw->phy.ops.check_reset_block(hw))
44defeb3 6267 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6268
dc221294
BA		 6269 /* Set initial default active device features */
6270 netdev->features = (NETIF_F_SG |
6271 NETIF_F_HW_VLAN_RX |
6272 NETIF_F_HW_VLAN_TX |
6273 NETIF_F_TSO |
6274 NETIF_F_TSO6 |
70495a50 6275 NETIF_F_RXHASH |
dc221294
BA		 6276 NETIF_F_RXCSUM |
6277 NETIF_F_HW_CSUM);
6278
6279 /* Set user-changeable features (subset of all device features) */
6280 netdev->hw_features = netdev->features;
0184039a 6281 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6282 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6283 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6284
6285 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6286 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6287
dc221294
BA		 6288 netdev->vlan_features |= (NETIF_F_SG |
6289 NETIF_F_TSO |
6290 NETIF_F_TSO6 |
6291 NETIF_F_HW_CSUM);
a5136e23 6292
ef9b965a
JB		 6293 netdev->priv_flags |= IFF_UNICAST_FLT;
6294
7b872a55 6295 if (pci_using_dac) {
bc7f75fa 6296 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6297 netdev->vlan_features |= NETIF_F_HIGHDMA;
6298 }
bc7f75fa 6299
bc7f75fa
AK		 6300 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6301 adapter->flags |= FLAG_MNG_PT_ENABLED;
6302
ad68076e
BA		 6303 /*
6304 * before reading the NVM, reset the controller to
6305 * put the device in a known good starting state
6306 */
bc7f75fa
AK		 6307 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6308
6309 /*
6310 * systems with ASPM and others may see the checksum fail on the first
6311 * attempt. Let's give it a few tries
6312 */
6313 for (i = 0;; i++) {
6314 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6315 break;
6316 if (i == 2) {
44defeb3 6317 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6318 err = -EIO;
6319 goto err_eeprom;
6320 }
6321 }
6322
10aa4c04
AK		 6323 e1000_eeprom_checks(adapter);
6324
608f8a0d 6325 /* copy the MAC address */
bc7f75fa 6326 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6327 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6328
6329 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6330 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6331
6332 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6333 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6334 err = -EIO;
6335 goto err_eeprom;
6336 }
6337
6338 init_timer(&adapter->watchdog_timer);
c061b18d 6339 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6340 adapter->watchdog_timer.data = (unsigned long) adapter;
6341
6342 init_timer(&adapter->phy_info_timer);
c061b18d 6343 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6344 adapter->phy_info_timer.data = (unsigned long) adapter;
6345
6346 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6347 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6348 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6349 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6350 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6351
bc7f75fa
AK		 6352 /* Initialize link parameters. User can change them with ethtool */
6353 adapter->hw.mac.autoneg = 1;
3db1cd5c 6354 adapter->fc_autoneg = true;
5c48ef3e
BA		 6355 adapter->hw.fc.requested_mode = e1000_fc_default;
6356 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6357 adapter->hw.phy.autoneg_advertised = 0x2f;
6358
6359 /* ring size defaults */
6360 adapter->rx_ring->count = 256;
6361 adapter->tx_ring->count = 256;
6362
6363 /*
6364 * Initial Wake on LAN setting - If APM wake is enabled in
6365 * the EEPROM, enable the ACPI Magic Packet filter
6366 */
6367 if (adapter->flags & FLAG_APME_IN_WUC) {
6368 /* APME bit in EEPROM is mapped to WUC.APME */
6369 eeprom_data = er32(WUC);
6370 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6371 if ((hw->mac.type > e1000_ich10lan) &&
6372 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6373 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6374 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6375 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6376 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6377 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6378 1, &eeprom_data);
bc7f75fa 6379 else
3d3a1676
BA		 6380 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6381 1, &eeprom_data);
bc7f75fa
AK		 6382 }
6383
6384 /* fetch WoL from EEPROM */
6385 if (eeprom_data & eeprom_apme_mask)
6386 adapter->eeprom_wol |= E1000_WUFC_MAG;
6387
6388 /*
6389 * now that we have the eeprom settings, apply the special cases
6390 * where the eeprom may be wrong or the board simply won't support
6391 * wake on lan on a particular port
6392 */
6393 if (!(adapter->flags & FLAG_HAS_WOL))
6394 adapter->eeprom_wol = 0;
6395
6396 /* initialize the wol settings based on the eeprom settings */
6397 adapter->wol = adapter->eeprom_wol;
6ff68026 6398 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6399
84527590
BA		 6400 /* save off EEPROM version number */
6401 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6402
bc7f75fa
AK		 6403 /* reset the hardware with the new settings */
6404 e1000e_reset(adapter);
6405
ad68076e
BA		 6406 /*
6407 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6408 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6409 * under the control of the driver.
6410 */
c43bc57e 6411 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6412 e1000e_get_hw_control(adapter);
bc7f75fa 6413
f2315bf1 6414 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6415 err = register_netdev(netdev);
6416 if (err)
6417 goto err_register;
6418
9c563d20
JB		 6419 /* carrier off reporting is important to ethtool even BEFORE open */
6420 netif_carrier_off(netdev);
6421
bc7f75fa
AK		 6422 e1000_print_device_info(adapter);
6423
f3ec4f87
AS		 6424 if (pci_dev_run_wake(pdev))
6425 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6426
bc7f75fa
AK		 6427 return 0;
6428
6429err_register:
c43bc57e 6430 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6431 e1000e_release_hw_control(adapter);
bc7f75fa 6432err_eeprom:
44abd5c1 6433 if (!hw->phy.ops.check_reset_block(hw))
bc7f75fa 6434 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6435err_hw_init:
bc7f75fa
AK		 6436 kfree(adapter->tx_ring);
6437 kfree(adapter->rx_ring);
6438err_sw_init:
c43bc57e
JB		 6439 if (adapter->hw.flash_address)
6440 iounmap(adapter->hw.flash_address);
e82f54ba 6441 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6442err_flashmap:
bc7f75fa
AK		 6443 iounmap(adapter->hw.hw_addr);
6444err_ioremap:
6445 free_netdev(netdev);
6446err_alloc_etherdev:
f0f422e5
BA		 6447 pci_release_selected_regions(pdev,
6448 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6449err_pci_reg:
6450err_dma:
6451 pci_disable_device(pdev);
6452 return err;
6453}
6454
6455/**
6456 * e1000_remove - Device Removal Routine
6457 * @pdev: PCI device information struct
6458 *
6459 * e1000_remove is called by the PCI subsystem to alert the driver
6460 * that it should release a PCI device. The could be caused by a
6461 * Hot-Plug event, or because the driver is going to be removed from
6462 * memory.
6463 **/
6464static void __devexit e1000_remove(struct pci_dev *pdev)
6465{
6466 struct net_device *netdev = pci_get_drvdata(pdev);
6467 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6468 bool down = test_bit(__E1000_DOWN, &adapter->state);
6469
ad68076e 6470 /*
23f333a2
TH		 6471 * The timers may be rescheduled, so explicitly disable them
6472 * from being rescheduled.
ad68076e 6473 */
23606cf5
RW		 6474 if (!down)
6475 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6476 del_timer_sync(&adapter->watchdog_timer);
6477 del_timer_sync(&adapter->phy_info_timer);
6478
41cec6f1
BA		 6479 cancel_work_sync(&adapter->reset_task);
6480 cancel_work_sync(&adapter->watchdog_task);
6481 cancel_work_sync(&adapter->downshift_task);
6482 cancel_work_sync(&adapter->update_phy_task);
6483 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6484
17f208de
BA		 6485 if (!(netdev->flags & IFF_UP))
6486 e1000_power_down_phy(adapter);
6487
23606cf5
RW		 6488 /* Don't lie to e1000_close() down the road. */
6489 if (!down)
6490 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6491 unregister_netdev(netdev);
6492
f3ec4f87
AS		 6493 if (pci_dev_run_wake(pdev))
6494 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6495
ad68076e
BA		 6496 /*
6497 * Release control of h/w to f/w. If f/w is AMT enabled, this
6498 * would have already happened in close and is redundant.
6499 */
31dbe5b4 6500 e1000e_release_hw_control(adapter);
bc7f75fa 6501
4662e82b 6502 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6503 kfree(adapter->tx_ring);
6504 kfree(adapter->rx_ring);
6505
6506 iounmap(adapter->hw.hw_addr);
6507 if (adapter->hw.flash_address)
6508 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6509 pci_release_selected_regions(pdev,
6510 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6511
6512 free_netdev(netdev);
6513
111b9dc5 6514 /* AER disable */
19d5afd4 6515 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6516
bc7f75fa
AK		 6517 pci_disable_device(pdev);
6518}
6519
6520/* PCI Error Recovery (ERS) */
6521static struct pci_error_handlers e1000_err_handler = {
6522 .error_detected = e1000_io_error_detected,
6523 .slot_reset = e1000_io_slot_reset,
6524 .resume = e1000_io_resume,
6525};
6526
a3aa1884 6527static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6529 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6532 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6533 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6537
bc7f75fa
AK		 6538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6542
bc7f75fa
AK		 6543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6546
4662e82b 6547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6550
bc7f75fa
AK		 6551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6552 board_80003es2lan },
6553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6554 board_80003es2lan },
6555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6556 board_80003es2lan },
6557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6558 board_80003es2lan },
ad68076e 6559
bc7f75fa
AK		 6560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6561 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6565 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6566 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6567 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6568
bc7f75fa
AK		 6569 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6570 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6571 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6572 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6573 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6574 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6575 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6576 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6577 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6578
6579 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6580 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6581 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6582
f4187b56
BA		 6583 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6584 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6585 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6586
a4f58f54
BA		 6587 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6588 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6589 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6590 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6591
d3738bb8
BA		 6592 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6593 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6594
f36bb6ca 6595 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6596};
6597MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6598
aa338601 6599#ifdef CONFIG_PM
23606cf5 6600static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6601 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6602 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6603 e1000_runtime_resume, e1000_idle)
23606cf5 6604};
e50208a0 6605#endif
23606cf5 6606
bc7f75fa
AK		 6607/* PCI Device API Driver */
6608static struct pci_driver e1000_driver = {
6609 .name = e1000e_driver_name,
6610 .id_table = e1000_pci_tbl,
6611 .probe = e1000_probe,
6612 .remove = __devexit_p(e1000_remove),
aa338601 6613#ifdef CONFIG_PM
f36bb6ca
BA		 6614 .driver = {
6615 .pm = &e1000_pm_ops,
6616 },
bc7f75fa
AK		 6617#endif
6618 .shutdown = e1000_shutdown,
6619 .err_handler = &e1000_err_handler
6620};
6621
6622/**
6623 * e1000_init_module - Driver Registration Routine
6624 *
6625 * e1000_init_module is the first routine called when the driver is
6626 * loaded. All it does is register with the PCI subsystem.
6627 **/
6628static int __init e1000_init_module(void)
6629{
6630 int ret;
8544b9f7
BA		 6631 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6632 e1000e_driver_version);
f5e261e6 6633 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6634 ret = pci_register_driver(&e1000_driver);
53ec5498 6635
bc7f75fa
AK		 6636 return ret;
6637}
6638module_init(e1000_init_module);
6639
6640/**
6641 * e1000_exit_module - Driver Exit Cleanup Routine
6642 *
6643 * e1000_exit_module is called just before the driver is removed
6644 * from memory.
6645 **/
6646static void __exit e1000_exit_module(void)
6647{
6648 pci_unregister_driver(&e1000_driver);
6649}
6650module_exit(e1000_exit_module);
6651
6652
6653MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6654MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6655MODULE_LICENSE("GPL");
6656MODULE_VERSION(DRV_VERSION);
6657
06c24b91 6658/* netdev.c */
Linux kernel - Deliverables
This page took 1.377668 seconds and 5 git commands to generate.