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vlan: rename vlan_dev_info to vlan_dev_priv
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
c5778b43 59#define DRV_VERSION "1.5.1" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
140 {}
141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29
BA		 185 struct my_u0 {
186 u64 a;
187 u64 b;
188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29
BA		 193 struct my_u1 {
194 u64 a;
195 u64 b;
196 u64 c;
197 u64 d;
198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90
TI		 223 if (!netdev || !netif_running(netdev))
224 goto exit;
225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90
TI		 310 if (!netif_msg_rx_status(adapter))
311 goto exit;
312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
452
453exit:
454 return;
455}
456
bc7f75fa
AK		 457/**
458 * e1000_desc_unused - calculate if we have unused descriptors
459 **/
460static int e1000_desc_unused(struct e1000_ring *ring)
461{
462 if (ring->next_to_clean > ring->next_to_use)
463 return ring->next_to_clean - ring->next_to_use - 1;
464
465 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
466}
467
468/**
ad68076e 469 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 470 * @adapter: board private structure
471 * @status: descriptor status field as written by hardware
472 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
473 * @skb: pointer to sk_buff to be indicated to stack
474 **/
475static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 476 struct net_device *netdev, struct sk_buff *skb,
a39fe742 477 u8 status, __le16 vlan)
bc7f75fa 478{
86d70e53 479 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 480 skb->protocol = eth_type_trans(skb, netdev);
481
86d70e53
JK		 482 if (status & E1000_RXD_STAT_VP)
483 __vlan_hwaccel_put_tag(skb, tag);
484
485 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 486}
487
488/**
af667a29 489 * e1000_rx_checksum - Receive Checksum Offload
bc7f75fa
AK		 490 * @adapter: board private structure
491 * @status_err: receive descriptor status and error fields
492 * @csum: receive descriptor csum field
493 * @sk_buff: socket buffer with received data
494 **/
495static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
496 u32 csum, struct sk_buff *skb)
497{
498 u16 status = (u16)status_err;
499 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 500
501 skb_checksum_none_assert(skb);
bc7f75fa
AK		 502
503 /* Ignore Checksum bit is set */
504 if (status & E1000_RXD_STAT_IXSM)
505 return;
506 /* TCP/UDP checksum error bit is set */
507 if (errors & E1000_RXD_ERR_TCPE) {
508 /* let the stack verify checksum errors */
509 adapter->hw_csum_err++;
510 return;
511 }
512
513 /* TCP/UDP Checksum has not been calculated */
514 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
515 return;
516
517 /* It must be a TCP or UDP packet with a valid checksum */
518 if (status & E1000_RXD_STAT_TCPCS) {
519 /* TCP checksum is good */
520 skb->ip_summed = CHECKSUM_UNNECESSARY;
521 } else {
ad68076e
BA		 522 /*
523 * IP fragment with UDP payload
524 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 525 * and then put the value in host order for further stack use.
526 */
a39fe742
AV		 527 __sum16 sum = (__force __sum16)htons(csum);
528 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 529 skb->ip_summed = CHECKSUM_COMPLETE;
530 }
531 adapter->hw_csum_good++;
532}
533
c6e7f51e
BA		 534/**
535 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
536 * @hw: pointer to the HW structure
537 * @tail: address of tail descriptor register
538 * @i: value to write to tail descriptor register
539 *
540 * When updating the tail register, the ME could be accessing Host CSR
541 * registers at the same time. Normally, this is handled in h/w by an
542 * arbiter but on some parts there is a bug that acknowledges Host accesses
543 * later than it should which could result in the descriptor register to
544 * have an incorrect value. Workaround this by checking the FWSM register
545 * which has bit 24 set while ME is accessing Host CSR registers, wait
546 * if it is set and try again a number of times.
547 **/
548static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, u8 __iomem * tail,
549 unsigned int i)
550{
551 unsigned int j = 0;
552
553 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
554 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
555 udelay(50);
556
557 writel(i, tail);
558
559 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
560 return E1000_ERR_SWFW_SYNC;
561
562 return 0;
563}
564
565static void e1000e_update_rdt_wa(struct e1000_adapter *adapter, unsigned int i)
566{
567 u8 __iomem *tail = (adapter->hw.hw_addr + adapter->rx_ring->tail);
568 struct e1000_hw *hw = &adapter->hw;
569
570 if (e1000e_update_tail_wa(hw, tail, i)) {
571 u32 rctl = er32(RCTL);
572 ew32(RCTL, rctl & ~E1000_RCTL_EN);
573 e_err("ME firmware caused invalid RDT - resetting\n");
574 schedule_work(&adapter->reset_task);
575 }
576}
577
578static void e1000e_update_tdt_wa(struct e1000_adapter *adapter, unsigned int i)
579{
580 u8 __iomem *tail = (adapter->hw.hw_addr + adapter->tx_ring->tail);
581 struct e1000_hw *hw = &adapter->hw;
582
583 if (e1000e_update_tail_wa(hw, tail, i)) {
584 u32 tctl = er32(TCTL);
585 ew32(TCTL, tctl & ~E1000_TCTL_EN);
586 e_err("ME firmware caused invalid TDT - resetting\n");
587 schedule_work(&adapter->reset_task);
588 }
589}
590
bc7f75fa 591/**
5f450212 592 * e1000_alloc_rx_buffers - Replace used receive buffers
bc7f75fa
AK		 593 * @adapter: address of board private structure
594 **/
595static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
c2fed996 596 int cleaned_count, gfp_t gfp)
bc7f75fa
AK		 597{
598 struct net_device *netdev = adapter->netdev;
599 struct pci_dev *pdev = adapter->pdev;
600 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 601 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 602 struct e1000_buffer *buffer_info;
603 struct sk_buff *skb;
604 unsigned int i;
89d71a66 605 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 606
607 i = rx_ring->next_to_use;
608 buffer_info = &rx_ring->buffer_info[i];
609
610 while (cleaned_count--) {
611 skb = buffer_info->skb;
612 if (skb) {
613 skb_trim(skb, 0);
614 goto map_skb;
615 }
616
c2fed996 617 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 618 if (!skb) {
619 /* Better luck next round */
620 adapter->alloc_rx_buff_failed++;
621 break;
622 }
623
bc7f75fa
AK		 624 buffer_info->skb = skb;
625map_skb:
0be3f55f 626 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 627 adapter->rx_buffer_len,
0be3f55f
NN		 628 DMA_FROM_DEVICE);
629 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 630 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 631 adapter->rx_dma_failed++;
632 break;
633 }
634
5f450212
BA		 635 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
636 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 637
50849d79
TH		 638 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
639 /*
640 * Force memory writes to complete before letting h/w
641 * know there are new descriptors to fetch. (Only
642 * applicable for weak-ordered memory model archs,
643 * such as IA-64).
644 */
645 wmb();
c6e7f51e
BA		 646 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
647 e1000e_update_rdt_wa(adapter, i);
648 else
649 writel(i, adapter->hw.hw_addr + rx_ring->tail);
50849d79 650 }
bc7f75fa
AK		 651 i++;
652 if (i == rx_ring->count)
653 i = 0;
654 buffer_info = &rx_ring->buffer_info[i];
655 }
656
50849d79 657 rx_ring->next_to_use = i;
bc7f75fa
AK		 658}
659
660/**
661 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
662 * @adapter: address of board private structure
663 **/
664static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
c2fed996 665 int cleaned_count, gfp_t gfp)
bc7f75fa
AK		 666{
667 struct net_device *netdev = adapter->netdev;
668 struct pci_dev *pdev = adapter->pdev;
669 union e1000_rx_desc_packet_split *rx_desc;
670 struct e1000_ring *rx_ring = adapter->rx_ring;
671 struct e1000_buffer *buffer_info;
672 struct e1000_ps_page *ps_page;
673 struct sk_buff *skb;
674 unsigned int i, j;
675
676 i = rx_ring->next_to_use;
677 buffer_info = &rx_ring->buffer_info[i];
678
679 while (cleaned_count--) {
680 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
681
682 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 683 ps_page = &buffer_info->ps_pages[j];
684 if (j >= adapter->rx_ps_pages) {
685 /* all unused desc entries get hw null ptr */
af667a29
BA		 686 rx_desc->read.buffer_addr[j + 1] =
687 ~cpu_to_le64(0);
47f44e40
AK		 688 continue;
689 }
690 if (!ps_page->page) {
c2fed996 691 ps_page->page = alloc_page(gfp);
bc7f75fa 692 if (!ps_page->page) {
47f44e40
AK		 693 adapter->alloc_rx_buff_failed++;
694 goto no_buffers;
695 }
0be3f55f
NN		 696 ps_page->dma = dma_map_page(&pdev->dev,
697 ps_page->page,
698 0, PAGE_SIZE,
699 DMA_FROM_DEVICE);
700 if (dma_mapping_error(&pdev->dev,
701 ps_page->dma)) {
47f44e40 702 dev_err(&adapter->pdev->dev,
af667a29 703 "Rx DMA page map failed\n");
47f44e40
AK		 704 adapter->rx_dma_failed++;
705 goto no_buffers;
bc7f75fa 706 }
bc7f75fa 707 }
47f44e40
AK		 708 /*
709 * Refresh the desc even if buffer_addrs
710 * didn't change because each write-back
711 * erases this info.
712 */
af667a29
BA		 713 rx_desc->read.buffer_addr[j + 1] =
714 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 715 }
716
c2fed996
JK		 717 skb = __netdev_alloc_skb_ip_align(netdev,
718 adapter->rx_ps_bsize0,
719 gfp);
bc7f75fa
AK		 720
721 if (!skb) {
722 adapter->alloc_rx_buff_failed++;
723 break;
724 }
725
bc7f75fa 726 buffer_info->skb = skb;
0be3f55f 727 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 728 adapter->rx_ps_bsize0,
0be3f55f
NN		 729 DMA_FROM_DEVICE);
730 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 731 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 732 adapter->rx_dma_failed++;
733 /* cleanup skb */
734 dev_kfree_skb_any(skb);
735 buffer_info->skb = NULL;
736 break;
737 }
738
739 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
740
50849d79
TH		 741 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
742 /*
743 * Force memory writes to complete before letting h/w
744 * know there are new descriptors to fetch. (Only
745 * applicable for weak-ordered memory model archs,
746 * such as IA-64).
747 */
748 wmb();
c6e7f51e
BA		 749 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
750 e1000e_update_rdt_wa(adapter, i << 1);
751 else
752 writel(i << 1,
753 adapter->hw.hw_addr + rx_ring->tail);
50849d79
TH		 754 }
755
bc7f75fa
AK		 756 i++;
757 if (i == rx_ring->count)
758 i = 0;
759 buffer_info = &rx_ring->buffer_info[i];
760 }
761
762no_buffers:
50849d79 763 rx_ring->next_to_use = i;
bc7f75fa
AK		 764}
765
97ac8cae
BA		 766/**
767 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
768 * @adapter: address of board private structure
97ac8cae
BA		 769 * @cleaned_count: number of buffers to allocate this pass
770 **/
771
772static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
c2fed996 773 int cleaned_count, gfp_t gfp)
97ac8cae
BA		 774{
775 struct net_device *netdev = adapter->netdev;
776 struct pci_dev *pdev = adapter->pdev;
5f450212 777 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 778 struct e1000_ring *rx_ring = adapter->rx_ring;
779 struct e1000_buffer *buffer_info;
780 struct sk_buff *skb;
781 unsigned int i;
89d71a66 782 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 783
784 i = rx_ring->next_to_use;
785 buffer_info = &rx_ring->buffer_info[i];
786
787 while (cleaned_count--) {
788 skb = buffer_info->skb;
789 if (skb) {
790 skb_trim(skb, 0);
791 goto check_page;
792 }
793
c2fed996 794 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 795 if (unlikely(!skb)) {
796 /* Better luck next round */
797 adapter->alloc_rx_buff_failed++;
798 break;
799 }
800
97ac8cae
BA		 801 buffer_info->skb = skb;
802check_page:
803 /* allocate a new page if necessary */
804 if (!buffer_info->page) {
c2fed996 805 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 806 if (unlikely(!buffer_info->page)) {
807 adapter->alloc_rx_buff_failed++;
808 break;
809 }
810 }
811
812 if (!buffer_info->dma)
0be3f55f 813 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 814 buffer_info->page, 0,
815 PAGE_SIZE,
0be3f55f 816 DMA_FROM_DEVICE);
97ac8cae 817
5f450212
BA		 818 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
819 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 820
821 if (unlikely(++i == rx_ring->count))
822 i = 0;
823 buffer_info = &rx_ring->buffer_info[i];
824 }
825
826 if (likely(rx_ring->next_to_use != i)) {
827 rx_ring->next_to_use = i;
828 if (unlikely(i-- == 0))
829 i = (rx_ring->count - 1);
830
831 /* Force memory writes to complete before letting h/w
832 * know there are new descriptors to fetch. (Only
833 * applicable for weak-ordered memory model archs,
834 * such as IA-64). */
835 wmb();
c6e7f51e
BA		 836 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
837 e1000e_update_rdt_wa(adapter, i);
838 else
839 writel(i, adapter->hw.hw_addr + rx_ring->tail);
97ac8cae
BA		 840 }
841}
842
bc7f75fa
AK		 843/**
844 * e1000_clean_rx_irq - Send received data up the network stack; legacy
845 * @adapter: board private structure
846 *
847 * the return value indicates whether actual cleaning was done, there
848 * is no guarantee that everything was cleaned
849 **/
850static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
851 int *work_done, int work_to_do)
852{
853 struct net_device *netdev = adapter->netdev;
854 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 855 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 856 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 857 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 858 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 859 u32 length, staterr;
bc7f75fa
AK		 860 unsigned int i;
861 int cleaned_count = 0;
862 bool cleaned = 0;
863 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
864
865 i = rx_ring->next_to_clean;
5f450212
BA		 866 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
867 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 868 buffer_info = &rx_ring->buffer_info[i];
869
5f450212 870 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 871 struct sk_buff *skb;
bc7f75fa
AK		 872
873 if (*work_done >= work_to_do)
874 break;
875 (*work_done)++;
2d0bb1c1 876 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 877
bc7f75fa
AK		 878 skb = buffer_info->skb;
879 buffer_info->skb = NULL;
880
881 prefetch(skb->data - NET_IP_ALIGN);
882
883 i++;
884 if (i == rx_ring->count)
885 i = 0;
5f450212 886 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 887 prefetch(next_rxd);
888
889 next_buffer = &rx_ring->buffer_info[i];
890
891 cleaned = 1;
892 cleaned_count++;
0be3f55f 893 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 894 buffer_info->dma,
895 adapter->rx_buffer_len,
0be3f55f 896 DMA_FROM_DEVICE);
bc7f75fa
AK		 897 buffer_info->dma = 0;
898
5f450212 899 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 900
b94b5028
JB		 901 /*
902 * !EOP means multiple descriptors were used to store a single
903 * packet, if that's the case we need to toss it. In fact, we
904 * need to toss every packet with the EOP bit clear and the
905 * next frame that _does_ have the EOP bit set, as it is by
906 * definition only a frame fragment
907 */
5f450212 908 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 909 adapter->flags2 |= FLAG2_IS_DISCARDING;
910
911 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 912 /* All receives must fit into a single buffer */
3bb99fe2 913 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 914 /* recycle */
915 buffer_info->skb = skb;
5f450212 916 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 917 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 918 goto next_desc;
919 }
920
5f450212 921 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
bc7f75fa
AK		 922 /* recycle */
923 buffer_info->skb = skb;
924 goto next_desc;
925 }
926
eb7c3adb
JK		 927 /* adjust length to remove Ethernet CRC */
928 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
929 length -= 4;
930
bc7f75fa
AK		 931 total_rx_bytes += length;
932 total_rx_packets++;
933
ad68076e
BA		 934 /*
935 * code added for copybreak, this should improve
bc7f75fa 936 * performance for small packets with large amounts
ad68076e
BA		 937 * of reassembly being done in the stack
938 */
bc7f75fa
AK		 939 if (length < copybreak) {
940 struct sk_buff *new_skb =
89d71a66 941 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 942 if (new_skb) {
808ff676
BA		 943 skb_copy_to_linear_data_offset(new_skb,
944 -NET_IP_ALIGN,
945 (skb->data -
946 NET_IP_ALIGN),
947 (length +
948 NET_IP_ALIGN));
bc7f75fa
AK		 949 /* save the skb in buffer_info as good */
950 buffer_info->skb = skb;
951 skb = new_skb;
952 }
953 /* else just continue with the old one */
954 }
955 /* end copybreak code */
956 skb_put(skb, length);
957
958 /* Receive Checksum Offload */
5f450212
BA		 959 e1000_rx_checksum(adapter, staterr,
960 le16_to_cpu(rx_desc->wb.lower.hi_dword.
961 csum_ip.csum), skb);
bc7f75fa 962
5f450212
BA		 963 e1000_receive_skb(adapter, netdev, skb, staterr,
964 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 965
966next_desc:
5f450212 967 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 968
969 /* return some buffers to hardware, one at a time is too slow */
970 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
c2fed996
JK		 971 adapter->alloc_rx_buf(adapter, cleaned_count,
972 GFP_ATOMIC);
bc7f75fa
AK		 973 cleaned_count = 0;
974 }
975
976 /* use prefetched values */
977 rx_desc = next_rxd;
978 buffer_info = next_buffer;
5f450212
BA		 979
980 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 981 }
982 rx_ring->next_to_clean = i;
983
984 cleaned_count = e1000_desc_unused(rx_ring);
985 if (cleaned_count)
c2fed996 986 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
bc7f75fa 987
bc7f75fa 988 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 989 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 990 return cleaned;
991}
992
bc7f75fa
AK		 993static void e1000_put_txbuf(struct e1000_adapter *adapter,
994 struct e1000_buffer *buffer_info)
995{
03b1320d
AD		 996 if (buffer_info->dma) {
997 if (buffer_info->mapped_as_page)
0be3f55f
NN		 998 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
999 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1000 else
0be3f55f
NN		 1001 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1002 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1003 buffer_info->dma = 0;
1004 }
bc7f75fa
AK		 1005 if (buffer_info->skb) {
1006 dev_kfree_skb_any(buffer_info->skb);
1007 buffer_info->skb = NULL;
1008 }
1b7719c4 1009 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1010}
1011
41cec6f1 1012static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1013{
41cec6f1
BA		 1014 struct e1000_adapter *adapter = container_of(work,
1015 struct e1000_adapter,
1016 print_hang_task);
09357b00 1017 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1018 struct e1000_ring *tx_ring = adapter->tx_ring;
1019 unsigned int i = tx_ring->next_to_clean;
1020 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1021 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1022 struct e1000_hw *hw = &adapter->hw;
1023 u16 phy_status, phy_1000t_status, phy_ext_status;
1024 u16 pci_status;
1025
615b32af
JB		 1026 if (test_bit(__E1000_DOWN, &adapter->state))
1027 return;
1028
09357b00
JK		 1029 if (!adapter->tx_hang_recheck &&
1030 (adapter->flags2 & FLAG2_DMA_BURST)) {
1031 /* May be block on write-back, flush and detect again
1032 * flush pending descriptor writebacks to memory
1033 */
1034 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1035 /* execute the writes immediately */
1036 e1e_flush();
1037 adapter->tx_hang_recheck = true;
1038 return;
1039 }
1040 /* Real hang detected */
1041 adapter->tx_hang_recheck = false;
1042 netif_stop_queue(netdev);
1043
41cec6f1
BA		 1044 e1e_rphy(hw, PHY_STATUS, &phy_status);
1045 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1046 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1047
41cec6f1
BA		 1048 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1049
1050 /* detected Hardware unit hang */
1051 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1052 " TDH <%x>\n"
1053 " TDT <%x>\n"
1054 " next_to_use <%x>\n"
1055 " next_to_clean <%x>\n"
1056 "buffer_info[next_to_clean]:\n"
1057 " time_stamp <%lx>\n"
1058 " next_to_watch <%x>\n"
1059 " jiffies <%lx>\n"
41cec6f1
BA		 1060 " next_to_watch.status <%x>\n"
1061 "MAC Status <%x>\n"
1062 "PHY Status <%x>\n"
1063 "PHY 1000BASE-T Status <%x>\n"
1064 "PHY Extended Status <%x>\n"
1065 "PCI Status <%x>\n",
44defeb3
JK		 1066 readl(adapter->hw.hw_addr + tx_ring->head),
1067 readl(adapter->hw.hw_addr + tx_ring->tail),
1068 tx_ring->next_to_use,
1069 tx_ring->next_to_clean,
1070 tx_ring->buffer_info[eop].time_stamp,
1071 eop,
1072 jiffies,
41cec6f1
BA		 1073 eop_desc->upper.fields.status,
1074 er32(STATUS),
1075 phy_status,
1076 phy_1000t_status,
1077 phy_ext_status,
1078 pci_status);
bc7f75fa
AK		 1079}
1080
1081/**
1082 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1083 * @adapter: board private structure
1084 *
1085 * the return value indicates whether actual cleaning was done, there
1086 * is no guarantee that everything was cleaned
1087 **/
1088static bool e1000_clean_tx_irq(struct e1000_adapter *adapter)
1089{
1090 struct net_device *netdev = adapter->netdev;
1091 struct e1000_hw *hw = &adapter->hw;
1092 struct e1000_ring *tx_ring = adapter->tx_ring;
1093 struct e1000_tx_desc *tx_desc, *eop_desc;
1094 struct e1000_buffer *buffer_info;
1095 unsigned int i, eop;
1096 unsigned int count = 0;
bc7f75fa 1097 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1098 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1099
1100 i = tx_ring->next_to_clean;
1101 eop = tx_ring->buffer_info[i].next_to_watch;
1102 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1103
12d04a3c
AD		 1104 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1105 (count < tx_ring->count)) {
a86043c2 1106 bool cleaned = false;
2d0bb1c1 1107 rmb(); /* read buffer_info after eop_desc */
a86043c2 1108 for (; !cleaned; count++) {
bc7f75fa
AK		 1109 tx_desc = E1000_TX_DESC(*tx_ring, i);
1110 buffer_info = &tx_ring->buffer_info[i];
1111 cleaned = (i == eop);
1112
1113 if (cleaned) {
9ed318d5
TH		 1114 total_tx_packets += buffer_info->segs;
1115 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1116 if (buffer_info->skb) {
1117 bytes_compl += buffer_info->skb->len;
1118 pkts_compl++;
1119 }
bc7f75fa
AK		 1120 }
1121
1122 e1000_put_txbuf(adapter, buffer_info);
1123 tx_desc->upper.data = 0;
1124
1125 i++;
1126 if (i == tx_ring->count)
1127 i = 0;
1128 }
1129
dac87619
TL		 1130 if (i == tx_ring->next_to_use)
1131 break;
bc7f75fa
AK		 1132 eop = tx_ring->buffer_info[i].next_to_watch;
1133 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1134 }
1135
1136 tx_ring->next_to_clean = i;
1137
3f0cfa3b
TH		 1138 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1139
bc7f75fa 1140#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1141 if (count && netif_carrier_ok(netdev) &&
1142 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1143 /* Make sure that anybody stopping the queue after this
1144 * sees the new next_to_clean.
1145 */
1146 smp_mb();
1147
1148 if (netif_queue_stopped(netdev) &&
1149 !(test_bit(__E1000_DOWN, &adapter->state))) {
1150 netif_wake_queue(netdev);
1151 ++adapter->restart_queue;
1152 }
1153 }
1154
1155 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1156 /*
1157 * Detect a transmit hang in hardware, this serializes the
1158 * check with the clearing of time_stamp and movement of i
1159 */
bc7f75fa 1160 adapter->detect_tx_hung = 0;
12d04a3c
AD		 1161 if (tx_ring->buffer_info[i].time_stamp &&
1162 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1163 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1164 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1165 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1166 else
1167 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1168 }
1169 adapter->total_tx_bytes += total_tx_bytes;
1170 adapter->total_tx_packets += total_tx_packets;
807540ba 1171 return count < tx_ring->count;
bc7f75fa
AK		 1172}
1173
bc7f75fa
AK		 1174/**
1175 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1176 * @adapter: board private structure
1177 *
1178 * the return value indicates whether actual cleaning was done, there
1179 * is no guarantee that everything was cleaned
1180 **/
1181static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
1182 int *work_done, int work_to_do)
1183{
3bb99fe2 1184 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1185 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1186 struct net_device *netdev = adapter->netdev;
1187 struct pci_dev *pdev = adapter->pdev;
1188 struct e1000_ring *rx_ring = adapter->rx_ring;
1189 struct e1000_buffer *buffer_info, *next_buffer;
1190 struct e1000_ps_page *ps_page;
1191 struct sk_buff *skb;
1192 unsigned int i, j;
1193 u32 length, staterr;
1194 int cleaned_count = 0;
1195 bool cleaned = 0;
1196 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197
1198 i = rx_ring->next_to_clean;
1199 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1200 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1201 buffer_info = &rx_ring->buffer_info[i];
1202
1203 while (staterr & E1000_RXD_STAT_DD) {
1204 if (*work_done >= work_to_do)
1205 break;
1206 (*work_done)++;
1207 skb = buffer_info->skb;
2d0bb1c1 1208 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1209
1210 /* in the packet split case this is header only */
1211 prefetch(skb->data - NET_IP_ALIGN);
1212
1213 i++;
1214 if (i == rx_ring->count)
1215 i = 0;
1216 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1217 prefetch(next_rxd);
1218
1219 next_buffer = &rx_ring->buffer_info[i];
1220
1221 cleaned = 1;
1222 cleaned_count++;
0be3f55f 1223 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1224 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1225 buffer_info->dma = 0;
1226
af667a29 1227 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1228 if (!(staterr & E1000_RXD_STAT_EOP))
1229 adapter->flags2 |= FLAG2_IS_DISCARDING;
1230
1231 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1232 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1233 dev_kfree_skb_irq(skb);
b94b5028
JB		 1234 if (staterr & E1000_RXD_STAT_EOP)
1235 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1236 goto next_desc;
1237 }
1238
1239 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
1240 dev_kfree_skb_irq(skb);
1241 goto next_desc;
1242 }
1243
1244 length = le16_to_cpu(rx_desc->wb.middle.length0);
1245
1246 if (!length) {
ef456f85 1247 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1248 dev_kfree_skb_irq(skb);
1249 goto next_desc;
1250 }
1251
1252 /* Good Receive */
1253 skb_put(skb, length);
1254
1255 {
ad68076e
BA		 1256 /*
1257 * this looks ugly, but it seems compiler issues make it
1258 * more efficient than reusing j
1259 */
bc7f75fa
AK		 1260 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1261
ad68076e
BA		 1262 /*
1263 * page alloc/put takes too long and effects small packet
1264 * throughput, so unsplit small packets and save the alloc/put
1265 * only valid in softirq (napi) context to call kmap_*
1266 */
bc7f75fa
AK		 1267 if (l1 && (l1 <= copybreak) &&
1268 ((length + l1) <= adapter->rx_ps_bsize0)) {
1269 u8 *vaddr;
1270
47f44e40 1271 ps_page = &buffer_info->ps_pages[0];
bc7f75fa 1272
ad68076e
BA		 1273 /*
1274 * there is no documentation about how to call
bc7f75fa 1275 * kmap_atomic, so we can't hold the mapping
ad68076e
BA		 1276 * very long
1277 */
0be3f55f
NN		 1278 dma_sync_single_for_cpu(&pdev->dev, ps_page->dma,
1279 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa
AK		 1280 vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
1281 memcpy(skb_tail_pointer(skb), vaddr, l1);
1282 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
0be3f55f
NN		 1283 dma_sync_single_for_device(&pdev->dev, ps_page->dma,
1284 PAGE_SIZE, DMA_FROM_DEVICE);
140a7480 1285
eb7c3adb
JK		 1286 /* remove the CRC */
1287 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1288 l1 -= 4;
1289
bc7f75fa
AK		 1290 skb_put(skb, l1);
1291 goto copydone;
1292 } /* if */
1293 }
1294
1295 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1296 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1297 if (!length)
1298 break;
1299
47f44e40 1300 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1301 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1302 DMA_FROM_DEVICE);
bc7f75fa
AK		 1303 ps_page->dma = 0;
1304 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1305 ps_page->page = NULL;
1306 skb->len += length;
1307 skb->data_len += length;
98a045d7 1308 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1309 }
1310
eb7c3adb
JK		 1311 /* strip the ethernet crc, problem is we're using pages now so
1312 * this whole operation can get a little cpu intensive
1313 */
1314 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1315 pskb_trim(skb, skb->len - 4);
1316
bc7f75fa
AK		 1317copydone:
1318 total_rx_bytes += skb->len;
1319 total_rx_packets++;
1320
1321 e1000_rx_checksum(adapter, staterr, le16_to_cpu(
1322 rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
1323
1324 if (rx_desc->wb.upper.header_status &
1325 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1326 adapter->rx_hdr_split++;
1327
1328 e1000_receive_skb(adapter, netdev, skb,
1329 staterr, rx_desc->wb.middle.vlan);
1330
1331next_desc:
1332 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1333 buffer_info->skb = NULL;
1334
1335 /* return some buffers to hardware, one at a time is too slow */
1336 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
c2fed996
JK		 1337 adapter->alloc_rx_buf(adapter, cleaned_count,
1338 GFP_ATOMIC);
bc7f75fa
AK		 1339 cleaned_count = 0;
1340 }
1341
1342 /* use prefetched values */
1343 rx_desc = next_rxd;
1344 buffer_info = next_buffer;
1345
1346 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1347 }
1348 rx_ring->next_to_clean = i;
1349
1350 cleaned_count = e1000_desc_unused(rx_ring);
1351 if (cleaned_count)
c2fed996 1352 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
bc7f75fa 1353
bc7f75fa 1354 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1355 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1356 return cleaned;
1357}
1358
97ac8cae
BA		 1359/**
1360 * e1000_consume_page - helper function
1361 **/
1362static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1363 u16 length)
1364{
1365 bi->page = NULL;
1366 skb->len += length;
1367 skb->data_len += length;
98a045d7 1368 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1369}
1370
1371/**
1372 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1373 * @adapter: board private structure
1374 *
1375 * the return value indicates whether actual cleaning was done, there
1376 * is no guarantee that everything was cleaned
1377 **/
1378
1379static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
1380 int *work_done, int work_to_do)
1381{
1382 struct net_device *netdev = adapter->netdev;
1383 struct pci_dev *pdev = adapter->pdev;
1384 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 1385 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1386 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1387 u32 length, staterr;
97ac8cae
BA		 1388 unsigned int i;
1389 int cleaned_count = 0;
1390 bool cleaned = false;
1391 unsigned int total_rx_bytes=0, total_rx_packets=0;
1392
1393 i = rx_ring->next_to_clean;
5f450212
BA		 1394 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1395 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1396 buffer_info = &rx_ring->buffer_info[i];
1397
5f450212 1398 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1399 struct sk_buff *skb;
97ac8cae
BA		 1400
1401 if (*work_done >= work_to_do)
1402 break;
1403 (*work_done)++;
2d0bb1c1 1404 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1405
97ac8cae
BA		 1406 skb = buffer_info->skb;
1407 buffer_info->skb = NULL;
1408
1409 ++i;
1410 if (i == rx_ring->count)
1411 i = 0;
5f450212 1412 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1413 prefetch(next_rxd);
1414
1415 next_buffer = &rx_ring->buffer_info[i];
1416
1417 cleaned = true;
1418 cleaned_count++;
0be3f55f
NN		 1419 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1420 DMA_FROM_DEVICE);
97ac8cae
BA		 1421 buffer_info->dma = 0;
1422
5f450212 1423 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1424
1425 /* errors is only valid for DD + EOP descriptors */
5f450212
BA		 1426 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1427 (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK))) {
1428 /* recycle both page and skb */
1429 buffer_info->skb = skb;
1430 /* an error means any chain goes out the window too */
1431 if (rx_ring->rx_skb_top)
1432 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1433 rx_ring->rx_skb_top = NULL;
1434 goto next_desc;
97ac8cae
BA		 1435 }
1436
f0f1a172 1437#define rxtop (rx_ring->rx_skb_top)
5f450212 1438 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1439 /* this descriptor is only the beginning (or middle) */
1440 if (!rxtop) {
1441 /* this is the beginning of a chain */
1442 rxtop = skb;
1443 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1444 0, length);
1445 } else {
1446 /* this is the middle of a chain */
1447 skb_fill_page_desc(rxtop,
1448 skb_shinfo(rxtop)->nr_frags,
1449 buffer_info->page, 0, length);
1450 /* re-use the skb, only consumed the page */
1451 buffer_info->skb = skb;
1452 }
1453 e1000_consume_page(buffer_info, rxtop, length);
1454 goto next_desc;
1455 } else {
1456 if (rxtop) {
1457 /* end of the chain */
1458 skb_fill_page_desc(rxtop,
1459 skb_shinfo(rxtop)->nr_frags,
1460 buffer_info->page, 0, length);
1461 /* re-use the current skb, we only consumed the
1462 * page */
1463 buffer_info->skb = skb;
1464 skb = rxtop;
1465 rxtop = NULL;
1466 e1000_consume_page(buffer_info, skb, length);
1467 } else {
1468 /* no chain, got EOP, this buf is the packet
1469 * copybreak to save the put_page/alloc_page */
1470 if (length <= copybreak &&
1471 skb_tailroom(skb) >= length) {
1472 u8 *vaddr;
1473 vaddr = kmap_atomic(buffer_info->page,
1474 KM_SKB_DATA_SOFTIRQ);
1475 memcpy(skb_tail_pointer(skb), vaddr,
1476 length);
1477 kunmap_atomic(vaddr,
1478 KM_SKB_DATA_SOFTIRQ);
1479 /* re-use the page, so don't erase
1480 * buffer_info->page */
1481 skb_put(skb, length);
1482 } else {
1483 skb_fill_page_desc(skb, 0,
1484 buffer_info->page, 0,
1485 length);
1486 e1000_consume_page(buffer_info, skb,
1487 length);
1488 }
1489 }
1490 }
1491
1492 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212
BA		 1493 e1000_rx_checksum(adapter, staterr,
1494 le16_to_cpu(rx_desc->wb.lower.hi_dword.
1495 csum_ip.csum), skb);
97ac8cae
BA		 1496
1497 /* probably a little skewed due to removing CRC */
1498 total_rx_bytes += skb->len;
1499 total_rx_packets++;
1500
1501 /* eth type trans needs skb->data to point to something */
1502 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1503 e_err("pskb_may_pull failed.\n");
ef5ab89c 1504 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1505 goto next_desc;
1506 }
1507
5f450212
BA		 1508 e1000_receive_skb(adapter, netdev, skb, staterr,
1509 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1510
1511next_desc:
5f450212 1512 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1513
1514 /* return some buffers to hardware, one at a time is too slow */
1515 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
c2fed996
JK		 1516 adapter->alloc_rx_buf(adapter, cleaned_count,
1517 GFP_ATOMIC);
97ac8cae
BA		 1518 cleaned_count = 0;
1519 }
1520
1521 /* use prefetched values */
1522 rx_desc = next_rxd;
1523 buffer_info = next_buffer;
5f450212
BA		 1524
1525 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1526 }
1527 rx_ring->next_to_clean = i;
1528
1529 cleaned_count = e1000_desc_unused(rx_ring);
1530 if (cleaned_count)
c2fed996 1531 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1532
1533 adapter->total_rx_bytes += total_rx_bytes;
1534 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1535 return cleaned;
1536}
1537
bc7f75fa
AK		 1538/**
1539 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1540 * @adapter: board private structure
1541 **/
1542static void e1000_clean_rx_ring(struct e1000_adapter *adapter)
1543{
1544 struct e1000_ring *rx_ring = adapter->rx_ring;
1545 struct e1000_buffer *buffer_info;
1546 struct e1000_ps_page *ps_page;
1547 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1548 unsigned int i, j;
1549
1550 /* Free all the Rx ring sk_buffs */
1551 for (i = 0; i < rx_ring->count; i++) {
1552 buffer_info = &rx_ring->buffer_info[i];
1553 if (buffer_info->dma) {
1554 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1555 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1556 adapter->rx_buffer_len,
0be3f55f 1557 DMA_FROM_DEVICE);
97ac8cae 1558 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1559 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1560 PAGE_SIZE,
0be3f55f 1561 DMA_FROM_DEVICE);
bc7f75fa 1562 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1563 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1564 adapter->rx_ps_bsize0,
0be3f55f 1565 DMA_FROM_DEVICE);
bc7f75fa
AK		 1566 buffer_info->dma = 0;
1567 }
1568
97ac8cae
BA		 1569 if (buffer_info->page) {
1570 put_page(buffer_info->page);
1571 buffer_info->page = NULL;
1572 }
1573
bc7f75fa
AK		 1574 if (buffer_info->skb) {
1575 dev_kfree_skb(buffer_info->skb);
1576 buffer_info->skb = NULL;
1577 }
1578
1579 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1580 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1581 if (!ps_page->page)
1582 break;
0be3f55f
NN		 1583 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1584 DMA_FROM_DEVICE);
bc7f75fa
AK		 1585 ps_page->dma = 0;
1586 put_page(ps_page->page);
1587 ps_page->page = NULL;
1588 }
1589 }
1590
1591 /* there also may be some cached data from a chained receive */
1592 if (rx_ring->rx_skb_top) {
1593 dev_kfree_skb(rx_ring->rx_skb_top);
1594 rx_ring->rx_skb_top = NULL;
1595 }
1596
bc7f75fa
AK		 1597 /* Zero out the descriptor ring */
1598 memset(rx_ring->desc, 0, rx_ring->size);
1599
1600 rx_ring->next_to_clean = 0;
1601 rx_ring->next_to_use = 0;
b94b5028 1602 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1603
1604 writel(0, adapter->hw.hw_addr + rx_ring->head);
1605 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1606}
1607
a8f88ff5
JB		 1608static void e1000e_downshift_workaround(struct work_struct *work)
1609{
1610 struct e1000_adapter *adapter = container_of(work,
1611 struct e1000_adapter, downshift_task);
1612
615b32af
JB		 1613 if (test_bit(__E1000_DOWN, &adapter->state))
1614 return;
1615
a8f88ff5
JB		 1616 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1617}
1618
bc7f75fa
AK		 1619/**
1620 * e1000_intr_msi - Interrupt Handler
1621 * @irq: interrupt number
1622 * @data: pointer to a network interface device structure
1623 **/
1624static irqreturn_t e1000_intr_msi(int irq, void *data)
1625{
1626 struct net_device *netdev = data;
1627 struct e1000_adapter *adapter = netdev_priv(netdev);
1628 struct e1000_hw *hw = &adapter->hw;
1629 u32 icr = er32(ICR);
1630
ad68076e
BA		 1631 /*
1632 * read ICR disables interrupts using IAM
1633 */
bc7f75fa 1634
573cca8c 1635 if (icr & E1000_ICR_LSC) {
bc7f75fa 1636 hw->mac.get_link_status = 1;
ad68076e
BA		 1637 /*
1638 * ICH8 workaround-- Call gig speed drop workaround on cable
1639 * disconnect (LSC) before accessing any PHY registers
1640 */
bc7f75fa
AK		 1641 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1642 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1643 schedule_work(&adapter->downshift_task);
bc7f75fa 1644
ad68076e
BA		 1645 /*
1646 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1647 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1648 * adapter in watchdog
1649 */
bc7f75fa
AK		 1650 if (netif_carrier_ok(netdev) &&
1651 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1652 /* disable receives */
1653 u32 rctl = er32(RCTL);
1654 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1655 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1656 }
1657 /* guard against interrupt when we're going down */
1658 if (!test_bit(__E1000_DOWN, &adapter->state))
1659 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1660 }
1661
288379f0 1662 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1663 adapter->total_tx_bytes = 0;
1664 adapter->total_tx_packets = 0;
1665 adapter->total_rx_bytes = 0;
1666 adapter->total_rx_packets = 0;
288379f0 1667 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1668 }
1669
1670 return IRQ_HANDLED;
1671}
1672
1673/**
1674 * e1000_intr - Interrupt Handler
1675 * @irq: interrupt number
1676 * @data: pointer to a network interface device structure
1677 **/
1678static irqreturn_t e1000_intr(int irq, void *data)
1679{
1680 struct net_device *netdev = data;
1681 struct e1000_adapter *adapter = netdev_priv(netdev);
1682 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1683 u32 rctl, icr = er32(ICR);
4662e82b 1684
a68ea775 1685 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1686 return IRQ_NONE; /* Not our interrupt */
1687
ad68076e
BA		 1688 /*
1689 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1690 * not set, then the adapter didn't send an interrupt
1691 */
bc7f75fa
AK		 1692 if (!(icr & E1000_ICR_INT_ASSERTED))
1693 return IRQ_NONE;
1694
ad68076e
BA		 1695 /*
1696 * Interrupt Auto-Mask...upon reading ICR,
1697 * interrupts are masked. No need for the
1698 * IMC write
1699 */
bc7f75fa 1700
573cca8c 1701 if (icr & E1000_ICR_LSC) {
bc7f75fa 1702 hw->mac.get_link_status = 1;
ad68076e
BA		 1703 /*
1704 * ICH8 workaround-- Call gig speed drop workaround on cable
1705 * disconnect (LSC) before accessing any PHY registers
1706 */
bc7f75fa
AK		 1707 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1708 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1709 schedule_work(&adapter->downshift_task);
bc7f75fa 1710
ad68076e
BA		 1711 /*
1712 * 80003ES2LAN workaround--
bc7f75fa
AK		 1713 * For packet buffer work-around on link down event;
1714 * disable receives here in the ISR and
1715 * reset adapter in watchdog
1716 */
1717 if (netif_carrier_ok(netdev) &&
1718 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1719 /* disable receives */
1720 rctl = er32(RCTL);
1721 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1722 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1723 }
1724 /* guard against interrupt when we're going down */
1725 if (!test_bit(__E1000_DOWN, &adapter->state))
1726 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1727 }
1728
288379f0 1729 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1730 adapter->total_tx_bytes = 0;
1731 adapter->total_tx_packets = 0;
1732 adapter->total_rx_bytes = 0;
1733 adapter->total_rx_packets = 0;
288379f0 1734 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1735 }
1736
1737 return IRQ_HANDLED;
1738}
1739
4662e82b
BA		 1740static irqreturn_t e1000_msix_other(int irq, void *data)
1741{
1742 struct net_device *netdev = data;
1743 struct e1000_adapter *adapter = netdev_priv(netdev);
1744 struct e1000_hw *hw = &adapter->hw;
1745 u32 icr = er32(ICR);
1746
1747 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1748 if (!test_bit(__E1000_DOWN, &adapter->state))
1749 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1750 return IRQ_NONE;
1751 }
1752
1753 if (icr & adapter->eiac_mask)
1754 ew32(ICS, (icr & adapter->eiac_mask));
1755
1756 if (icr & E1000_ICR_OTHER) {
1757 if (!(icr & E1000_ICR_LSC))
1758 goto no_link_interrupt;
1759 hw->mac.get_link_status = 1;
1760 /* guard against interrupt when we're going down */
1761 if (!test_bit(__E1000_DOWN, &adapter->state))
1762 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1763 }
1764
1765no_link_interrupt:
a3c69fef
JB		 1766 if (!test_bit(__E1000_DOWN, &adapter->state))
1767 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1768
1769 return IRQ_HANDLED;
1770}
1771
1772
1773static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1774{
1775 struct net_device *netdev = data;
1776 struct e1000_adapter *adapter = netdev_priv(netdev);
1777 struct e1000_hw *hw = &adapter->hw;
1778 struct e1000_ring *tx_ring = adapter->tx_ring;
1779
1780
1781 adapter->total_tx_bytes = 0;
1782 adapter->total_tx_packets = 0;
1783
1784 if (!e1000_clean_tx_irq(adapter))
1785 /* Ring was not completely cleaned, so fire another interrupt */
1786 ew32(ICS, tx_ring->ims_val);
1787
1788 return IRQ_HANDLED;
1789}
1790
1791static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1792{
1793 struct net_device *netdev = data;
1794 struct e1000_adapter *adapter = netdev_priv(netdev);
1795
1796 /* Write the ITR value calculated at the end of the
1797 * previous interrupt.
1798 */
1799 if (adapter->rx_ring->set_itr) {
1800 writel(1000000000 / (adapter->rx_ring->itr_val * 256),
1801 adapter->hw.hw_addr + adapter->rx_ring->itr_register);
1802 adapter->rx_ring->set_itr = 0;
1803 }
1804
288379f0 1805 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1806 adapter->total_rx_bytes = 0;
1807 adapter->total_rx_packets = 0;
288379f0 1808 __napi_schedule(&adapter->napi);
4662e82b
BA		 1809 }
1810 return IRQ_HANDLED;
1811}
1812
1813/**
1814 * e1000_configure_msix - Configure MSI-X hardware
1815 *
1816 * e1000_configure_msix sets up the hardware to properly
1817 * generate MSI-X interrupts.
1818 **/
1819static void e1000_configure_msix(struct e1000_adapter *adapter)
1820{
1821 struct e1000_hw *hw = &adapter->hw;
1822 struct e1000_ring *rx_ring = adapter->rx_ring;
1823 struct e1000_ring *tx_ring = adapter->tx_ring;
1824 int vector = 0;
1825 u32 ctrl_ext, ivar = 0;
1826
1827 adapter->eiac_mask = 0;
1828
1829 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1830 if (hw->mac.type == e1000_82574) {
1831 u32 rfctl = er32(RFCTL);
1832 rfctl |= E1000_RFCTL_ACK_DIS;
1833 ew32(RFCTL, rfctl);
1834 }
1835
1836#define E1000_IVAR_INT_ALLOC_VALID 0x8
1837 /* Configure Rx vector */
1838 rx_ring->ims_val = E1000_IMS_RXQ0;
1839 adapter->eiac_mask |= rx_ring->ims_val;
1840 if (rx_ring->itr_val)
1841 writel(1000000000 / (rx_ring->itr_val * 256),
1842 hw->hw_addr + rx_ring->itr_register);
1843 else
1844 writel(1, hw->hw_addr + rx_ring->itr_register);
1845 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1846
1847 /* Configure Tx vector */
1848 tx_ring->ims_val = E1000_IMS_TXQ0;
1849 vector++;
1850 if (tx_ring->itr_val)
1851 writel(1000000000 / (tx_ring->itr_val * 256),
1852 hw->hw_addr + tx_ring->itr_register);
1853 else
1854 writel(1, hw->hw_addr + tx_ring->itr_register);
1855 adapter->eiac_mask |= tx_ring->ims_val;
1856 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1857
1858 /* set vector for Other Causes, e.g. link changes */
1859 vector++;
1860 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1861 if (rx_ring->itr_val)
1862 writel(1000000000 / (rx_ring->itr_val * 256),
1863 hw->hw_addr + E1000_EITR_82574(vector));
1864 else
1865 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1866
1867 /* Cause Tx interrupts on every write back */
1868 ivar |= (1 << 31);
1869
1870 ew32(IVAR, ivar);
1871
1872 /* enable MSI-X PBA support */
1873 ctrl_ext = er32(CTRL_EXT);
1874 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1875
1876 /* Auto-Mask Other interrupts upon ICR read */
1877#define E1000_EIAC_MASK_82574 0x01F00000
1878 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1879 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1880 ew32(CTRL_EXT, ctrl_ext);
1881 e1e_flush();
1882}
1883
1884void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1885{
1886 if (adapter->msix_entries) {
1887 pci_disable_msix(adapter->pdev);
1888 kfree(adapter->msix_entries);
1889 adapter->msix_entries = NULL;
1890 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1891 pci_disable_msi(adapter->pdev);
1892 adapter->flags &= ~FLAG_MSI_ENABLED;
1893 }
4662e82b
BA		 1894}
1895
1896/**
1897 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1898 *
1899 * Attempt to configure interrupts using the best available
1900 * capabilities of the hardware and kernel.
1901 **/
1902void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1903{
1904 int err;
8e86acd7 1905 int i;
4662e82b
BA		 1906
1907 switch (adapter->int_mode) {
1908 case E1000E_INT_MODE_MSIX:
1909 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1910 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1911 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1912 sizeof(struct msix_entry),
1913 GFP_KERNEL);
1914 if (adapter->msix_entries) {
8e86acd7 1915 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1916 adapter->msix_entries[i].entry = i;
1917
1918 err = pci_enable_msix(adapter->pdev,
1919 adapter->msix_entries,
8e86acd7 1920 adapter->num_vectors);
b1cdfead 1921 if (err == 0)
4662e82b
BA		 1922 return;
1923 }
1924 /* MSI-X failed, so fall through and try MSI */
ef456f85 1925 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1926 e1000e_reset_interrupt_capability(adapter);
1927 }
1928 adapter->int_mode = E1000E_INT_MODE_MSI;
1929 /* Fall through */
1930 case E1000E_INT_MODE_MSI:
1931 if (!pci_enable_msi(adapter->pdev)) {
1932 adapter->flags |= FLAG_MSI_ENABLED;
1933 } else {
1934 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1935 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1936 }
1937 /* Fall through */
1938 case E1000E_INT_MODE_LEGACY:
1939 /* Don't do anything; this is the system default */
1940 break;
1941 }
8e86acd7
JK		 1942
1943 /* store the number of vectors being used */
1944 adapter->num_vectors = 1;
4662e82b
BA		 1945}
1946
1947/**
1948 * e1000_request_msix - Initialize MSI-X interrupts
1949 *
1950 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1951 * kernel.
1952 **/
1953static int e1000_request_msix(struct e1000_adapter *adapter)
1954{
1955 struct net_device *netdev = adapter->netdev;
1956 int err = 0, vector = 0;
1957
1958 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1959 snprintf(adapter->rx_ring->name,
1960 sizeof(adapter->rx_ring->name) - 1,
1961 "%s-rx-0", netdev->name);
4662e82b
BA		 1962 else
1963 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1964 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1965 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1966 netdev);
1967 if (err)
1968 goto out;
1969 adapter->rx_ring->itr_register = E1000_EITR_82574(vector);
1970 adapter->rx_ring->itr_val = adapter->itr;
1971 vector++;
1972
1973 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1974 snprintf(adapter->tx_ring->name,
1975 sizeof(adapter->tx_ring->name) - 1,
1976 "%s-tx-0", netdev->name);
4662e82b
BA		 1977 else
1978 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1979 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1980 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1981 netdev);
1982 if (err)
1983 goto out;
1984 adapter->tx_ring->itr_register = E1000_EITR_82574(vector);
1985 adapter->tx_ring->itr_val = adapter->itr;
1986 vector++;
1987
1988 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1989 e1000_msix_other, 0, netdev->name, netdev);
4662e82b
BA		 1990 if (err)
1991 goto out;
1992
1993 e1000_configure_msix(adapter);
1994 return 0;
1995out:
1996 return err;
1997}
1998
f8d59f78
BA		 1999/**
2000 * e1000_request_irq - initialize interrupts
2001 *
2002 * Attempts to configure interrupts using the best available
2003 * capabilities of the hardware and kernel.
2004 **/
bc7f75fa
AK		 2005static int e1000_request_irq(struct e1000_adapter *adapter)
2006{
2007 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2008 int err;
2009
4662e82b
BA		 2010 if (adapter->msix_entries) {
2011 err = e1000_request_msix(adapter);
2012 if (!err)
2013 return err;
2014 /* fall back to MSI */
2015 e1000e_reset_interrupt_capability(adapter);
2016 adapter->int_mode = E1000E_INT_MODE_MSI;
2017 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2018 }
4662e82b 2019 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2020 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2021 netdev->name, netdev);
2022 if (!err)
2023 return err;
bc7f75fa 2024
4662e82b
BA		 2025 /* fall back to legacy interrupt */
2026 e1000e_reset_interrupt_capability(adapter);
2027 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2028 }
2029
a0607fd3 2030 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2031 netdev->name, netdev);
2032 if (err)
2033 e_err("Unable to allocate interrupt, Error: %d\n", err);
2034
bc7f75fa
AK		 2035 return err;
2036}
2037
2038static void e1000_free_irq(struct e1000_adapter *adapter)
2039{
2040 struct net_device *netdev = adapter->netdev;
2041
4662e82b
BA		 2042 if (adapter->msix_entries) {
2043 int vector = 0;
2044
2045 free_irq(adapter->msix_entries[vector].vector, netdev);
2046 vector++;
2047
2048 free_irq(adapter->msix_entries[vector].vector, netdev);
2049 vector++;
2050
2051 /* Other Causes interrupt vector */
2052 free_irq(adapter->msix_entries[vector].vector, netdev);
2053 return;
bc7f75fa 2054 }
4662e82b
BA		 2055
2056 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2057}
2058
2059/**
2060 * e1000_irq_disable - Mask off interrupt generation on the NIC
2061 **/
2062static void e1000_irq_disable(struct e1000_adapter *adapter)
2063{
2064 struct e1000_hw *hw = &adapter->hw;
2065
bc7f75fa 2066 ew32(IMC, ~0);
4662e82b
BA		 2067 if (adapter->msix_entries)
2068 ew32(EIAC_82574, 0);
bc7f75fa 2069 e1e_flush();
8e86acd7
JK		 2070
2071 if (adapter->msix_entries) {
2072 int i;
2073 for (i = 0; i < adapter->num_vectors; i++)
2074 synchronize_irq(adapter->msix_entries[i].vector);
2075 } else {
2076 synchronize_irq(adapter->pdev->irq);
2077 }
bc7f75fa
AK		 2078}
2079
2080/**
2081 * e1000_irq_enable - Enable default interrupt generation settings
2082 **/
2083static void e1000_irq_enable(struct e1000_adapter *adapter)
2084{
2085 struct e1000_hw *hw = &adapter->hw;
2086
4662e82b
BA		 2087 if (adapter->msix_entries) {
2088 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2089 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2090 } else {
2091 ew32(IMS, IMS_ENABLE_MASK);
2092 }
74ef9c39 2093 e1e_flush();
bc7f75fa
AK		 2094}
2095
2096/**
31dbe5b4 2097 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2098 * @adapter: address of board private structure
2099 *
31dbe5b4 2100 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2101 * For ASF and Pass Through versions of f/w this means that
2102 * the driver is loaded. For AMT version (only with 82573)
2103 * of the f/w this means that the network i/f is open.
2104 **/
31dbe5b4 2105void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2106{
2107 struct e1000_hw *hw = &adapter->hw;
2108 u32 ctrl_ext;
2109 u32 swsm;
2110
2111 /* Let firmware know the driver has taken over */
2112 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2113 swsm = er32(SWSM);
2114 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2115 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2116 ctrl_ext = er32(CTRL_EXT);
ad68076e 2117 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2118 }
2119}
2120
2121/**
31dbe5b4 2122 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2123 * @adapter: address of board private structure
2124 *
31dbe5b4 2125 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2126 * For ASF and Pass Through versions of f/w this means that the
2127 * driver is no longer loaded. For AMT version (only with 82573) i
2128 * of the f/w this means that the network i/f is closed.
2129 *
2130 **/
31dbe5b4 2131void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2132{
2133 struct e1000_hw *hw = &adapter->hw;
2134 u32 ctrl_ext;
2135 u32 swsm;
2136
2137 /* Let firmware taken over control of h/w */
2138 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2139 swsm = er32(SWSM);
2140 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2141 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2142 ctrl_ext = er32(CTRL_EXT);
ad68076e 2143 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2144 }
2145}
2146
bc7f75fa
AK		 2147/**
2148 * @e1000_alloc_ring - allocate memory for a ring structure
2149 **/
2150static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2151 struct e1000_ring *ring)
2152{
2153 struct pci_dev *pdev = adapter->pdev;
2154
2155 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2156 GFP_KERNEL);
2157 if (!ring->desc)
2158 return -ENOMEM;
2159
2160 return 0;
2161}
2162
2163/**
2164 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2165 * @adapter: board private structure
2166 *
2167 * Return 0 on success, negative on failure
2168 **/
2169int e1000e_setup_tx_resources(struct e1000_adapter *adapter)
2170{
2171 struct e1000_ring *tx_ring = adapter->tx_ring;
2172 int err = -ENOMEM, size;
2173
2174 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2175 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2176 if (!tx_ring->buffer_info)
2177 goto err;
bc7f75fa
AK		 2178
2179 /* round up to nearest 4K */
2180 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2181 tx_ring->size = ALIGN(tx_ring->size, 4096);
2182
2183 err = e1000_alloc_ring_dma(adapter, tx_ring);
2184 if (err)
2185 goto err;
2186
2187 tx_ring->next_to_use = 0;
2188 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2189
2190 return 0;
2191err:
2192 vfree(tx_ring->buffer_info);
44defeb3 2193 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2194 return err;
2195}
2196
2197/**
2198 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2199 * @adapter: board private structure
2200 *
2201 * Returns 0 on success, negative on failure
2202 **/
2203int e1000e_setup_rx_resources(struct e1000_adapter *adapter)
2204{
2205 struct e1000_ring *rx_ring = adapter->rx_ring;
47f44e40
AK		 2206 struct e1000_buffer *buffer_info;
2207 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2208
2209 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2210 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2211 if (!rx_ring->buffer_info)
2212 goto err;
bc7f75fa 2213
47f44e40
AK		 2214 for (i = 0; i < rx_ring->count; i++) {
2215 buffer_info = &rx_ring->buffer_info[i];
2216 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2217 sizeof(struct e1000_ps_page),
2218 GFP_KERNEL);
2219 if (!buffer_info->ps_pages)
2220 goto err_pages;
2221 }
bc7f75fa
AK		 2222
2223 desc_len = sizeof(union e1000_rx_desc_packet_split);
2224
2225 /* Round up to nearest 4K */
2226 rx_ring->size = rx_ring->count * desc_len;
2227 rx_ring->size = ALIGN(rx_ring->size, 4096);
2228
2229 err = e1000_alloc_ring_dma(adapter, rx_ring);
2230 if (err)
47f44e40 2231 goto err_pages;
bc7f75fa
AK		 2232
2233 rx_ring->next_to_clean = 0;
2234 rx_ring->next_to_use = 0;
2235 rx_ring->rx_skb_top = NULL;
2236
2237 return 0;
47f44e40
AK		 2238
2239err_pages:
2240 for (i = 0; i < rx_ring->count; i++) {
2241 buffer_info = &rx_ring->buffer_info[i];
2242 kfree(buffer_info->ps_pages);
2243 }
bc7f75fa
AK		 2244err:
2245 vfree(rx_ring->buffer_info);
e9262447 2246 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2247 return err;
2248}
2249
2250/**
2251 * e1000_clean_tx_ring - Free Tx Buffers
2252 * @adapter: board private structure
2253 **/
2254static void e1000_clean_tx_ring(struct e1000_adapter *adapter)
2255{
2256 struct e1000_ring *tx_ring = adapter->tx_ring;
2257 struct e1000_buffer *buffer_info;
2258 unsigned long size;
2259 unsigned int i;
2260
2261 for (i = 0; i < tx_ring->count; i++) {
2262 buffer_info = &tx_ring->buffer_info[i];
2263 e1000_put_txbuf(adapter, buffer_info);
2264 }
2265
3f0cfa3b 2266 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2267 size = sizeof(struct e1000_buffer) * tx_ring->count;
2268 memset(tx_ring->buffer_info, 0, size);
2269
2270 memset(tx_ring->desc, 0, tx_ring->size);
2271
2272 tx_ring->next_to_use = 0;
2273 tx_ring->next_to_clean = 0;
2274
2275 writel(0, adapter->hw.hw_addr + tx_ring->head);
2276 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2277}
2278
2279/**
2280 * e1000e_free_tx_resources - Free Tx Resources per Queue
2281 * @adapter: board private structure
2282 *
2283 * Free all transmit software resources
2284 **/
2285void e1000e_free_tx_resources(struct e1000_adapter *adapter)
2286{
2287 struct pci_dev *pdev = adapter->pdev;
2288 struct e1000_ring *tx_ring = adapter->tx_ring;
2289
2290 e1000_clean_tx_ring(adapter);
2291
2292 vfree(tx_ring->buffer_info);
2293 tx_ring->buffer_info = NULL;
2294
2295 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2296 tx_ring->dma);
2297 tx_ring->desc = NULL;
2298}
2299
2300/**
2301 * e1000e_free_rx_resources - Free Rx Resources
2302 * @adapter: board private structure
2303 *
2304 * Free all receive software resources
2305 **/
2306
2307void e1000e_free_rx_resources(struct e1000_adapter *adapter)
2308{
2309 struct pci_dev *pdev = adapter->pdev;
2310 struct e1000_ring *rx_ring = adapter->rx_ring;
47f44e40 2311 int i;
bc7f75fa
AK		 2312
2313 e1000_clean_rx_ring(adapter);
2314
b1cdfead 2315 for (i = 0; i < rx_ring->count; i++)
47f44e40 2316 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2317
bc7f75fa
AK		 2318 vfree(rx_ring->buffer_info);
2319 rx_ring->buffer_info = NULL;
2320
bc7f75fa
AK		 2321 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2322 rx_ring->dma);
2323 rx_ring->desc = NULL;
2324}
2325
2326/**
2327 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2328 * @adapter: pointer to adapter
2329 * @itr_setting: current adapter->itr
2330 * @packets: the number of packets during this measurement interval
2331 * @bytes: the number of bytes during this measurement interval
2332 *
bc7f75fa
AK		 2333 * Stores a new ITR value based on packets and byte
2334 * counts during the last interrupt. The advantage of per interrupt
2335 * computation is faster updates and more accurate ITR for the current
2336 * traffic pattern. Constants in this function were computed
2337 * based on theoretical maximum wire speed and thresholds were set based
2338 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2339 * while increasing bulk throughput. This functionality is controlled
2340 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2341 **/
2342static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2343 u16 itr_setting, int packets,
2344 int bytes)
2345{
2346 unsigned int retval = itr_setting;
2347
2348 if (packets == 0)
2349 goto update_itr_done;
2350
2351 switch (itr_setting) {
2352 case lowest_latency:
2353 /* handle TSO and jumbo frames */
2354 if (bytes/packets > 8000)
2355 retval = bulk_latency;
b1cdfead 2356 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2357 retval = low_latency;
bc7f75fa
AK		 2358 break;
2359 case low_latency: /* 50 usec aka 20000 ints/s */
2360 if (bytes > 10000) {
2361 /* this if handles the TSO accounting */
b1cdfead 2362 if (bytes/packets > 8000)
bc7f75fa 2363 retval = bulk_latency;
b1cdfead 2364 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2365 retval = bulk_latency;
b1cdfead 2366 else if ((packets > 35))
bc7f75fa 2367 retval = lowest_latency;
bc7f75fa
AK		 2368 } else if (bytes/packets > 2000) {
2369 retval = bulk_latency;
2370 } else if (packets <= 2 && bytes < 512) {
2371 retval = lowest_latency;
2372 }
2373 break;
2374 case bulk_latency: /* 250 usec aka 4000 ints/s */
2375 if (bytes > 25000) {
b1cdfead 2376 if (packets > 35)
bc7f75fa 2377 retval = low_latency;
bc7f75fa
AK		 2378 } else if (bytes < 6000) {
2379 retval = low_latency;
2380 }
2381 break;
2382 }
2383
2384update_itr_done:
2385 return retval;
2386}
2387
2388static void e1000_set_itr(struct e1000_adapter *adapter)
2389{
2390 struct e1000_hw *hw = &adapter->hw;
2391 u16 current_itr;
2392 u32 new_itr = adapter->itr;
2393
2394 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2395 if (adapter->link_speed != SPEED_1000) {
2396 current_itr = 0;
2397 new_itr = 4000;
2398 goto set_itr_now;
2399 }
2400
828bac87
BA		 2401 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2402 new_itr = 0;
2403 goto set_itr_now;
2404 }
2405
bc7f75fa
AK		 2406 adapter->tx_itr = e1000_update_itr(adapter,
2407 adapter->tx_itr,
2408 adapter->total_tx_packets,
2409 adapter->total_tx_bytes);
2410 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2411 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2412 adapter->tx_itr = low_latency;
2413
2414 adapter->rx_itr = e1000_update_itr(adapter,
2415 adapter->rx_itr,
2416 adapter->total_rx_packets,
2417 adapter->total_rx_bytes);
2418 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2419 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2420 adapter->rx_itr = low_latency;
2421
2422 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2423
2424 switch (current_itr) {
2425 /* counts and packets in update_itr are dependent on these numbers */
2426 case lowest_latency:
2427 new_itr = 70000;
2428 break;
2429 case low_latency:
2430 new_itr = 20000; /* aka hwitr = ~200 */
2431 break;
2432 case bulk_latency:
2433 new_itr = 4000;
2434 break;
2435 default:
2436 break;
2437 }
2438
2439set_itr_now:
2440 if (new_itr != adapter->itr) {
ad68076e
BA		 2441 /*
2442 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2443 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2444 * increasing
2445 */
bc7f75fa
AK		 2446 new_itr = new_itr > adapter->itr ?
2447 min(adapter->itr + (new_itr >> 2), new_itr) :
2448 new_itr;
2449 adapter->itr = new_itr;
4662e82b
BA		 2450 adapter->rx_ring->itr_val = new_itr;
2451 if (adapter->msix_entries)
2452 adapter->rx_ring->set_itr = 1;
2453 else
828bac87
BA		 2454 if (new_itr)
2455 ew32(ITR, 1000000000 / (new_itr * 256));
2456 else
2457 ew32(ITR, 0);
bc7f75fa
AK		 2458 }
2459}
2460
4662e82b
BA		 2461/**
2462 * e1000_alloc_queues - Allocate memory for all rings
2463 * @adapter: board private structure to initialize
2464 **/
2465static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2466{
2467 adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
2468 if (!adapter->tx_ring)
2469 goto err;
2470
2471 adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
2472 if (!adapter->rx_ring)
2473 goto err;
2474
2475 return 0;
2476err:
2477 e_err("Unable to allocate memory for queues\n");
2478 kfree(adapter->rx_ring);
2479 kfree(adapter->tx_ring);
2480 return -ENOMEM;
2481}
2482
bc7f75fa
AK		 2483/**
2484 * e1000_clean - NAPI Rx polling callback
ad68076e 2485 * @napi: struct associated with this polling callback
489815ce 2486 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2487 **/
2488static int e1000_clean(struct napi_struct *napi, int budget)
2489{
2490 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2491 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2492 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2493 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2494
4cf1653a 2495 adapter = netdev_priv(poll_dev);
bc7f75fa 2496
4662e82b
BA		 2497 if (adapter->msix_entries &&
2498 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2499 goto clean_rx;
2500
92af3e95 2501 tx_cleaned = e1000_clean_tx_irq(adapter);
bc7f75fa 2502
4662e82b 2503clean_rx:
bc7f75fa 2504 adapter->clean_rx(adapter, &work_done, budget);
d2c7ddd6 2505
12d04a3c 2506 if (!tx_cleaned)
d2c7ddd6 2507 work_done = budget;
bc7f75fa 2508
53e52c72
DM		 2509 /* If budget not fully consumed, exit the polling mode */
2510 if (work_done < budget) {
bc7f75fa
AK		 2511 if (adapter->itr_setting & 3)
2512 e1000_set_itr(adapter);
288379f0 2513 napi_complete(napi);
a3c69fef
JB		 2514 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2515 if (adapter->msix_entries)
2516 ew32(IMS, adapter->rx_ring->ims_val);
2517 else
2518 e1000_irq_enable(adapter);
2519 }
bc7f75fa
AK		 2520 }
2521
2522 return work_done;
2523}
2524
2525static void e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2526{
2527 struct e1000_adapter *adapter = netdev_priv(netdev);
2528 struct e1000_hw *hw = &adapter->hw;
2529 u32 vfta, index;
2530
2531 /* don't update vlan cookie if already programmed */
2532 if ((adapter->hw.mng_cookie.status &
2533 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2534 (vid == adapter->mng_vlan_id))
2535 return;
caaddaf8 2536
bc7f75fa 2537 /* add VID to filter table */
caaddaf8
BA		 2538 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2539 index = (vid >> 5) & 0x7F;
2540 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2541 vfta |= (1 << (vid & 0x1F));
2542 hw->mac.ops.write_vfta(hw, index, vfta);
2543 }
86d70e53
JK		 2544
2545 set_bit(vid, adapter->active_vlans);
bc7f75fa
AK		 2546}
2547
2548static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2549{
2550 struct e1000_adapter *adapter = netdev_priv(netdev);
2551 struct e1000_hw *hw = &adapter->hw;
2552 u32 vfta, index;
2553
bc7f75fa
AK		 2554 if ((adapter->hw.mng_cookie.status &
2555 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2556 (vid == adapter->mng_vlan_id)) {
2557 /* release control to f/w */
31dbe5b4 2558 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 2559 return;
2560 }
2561
2562 /* remove VID from filter table */
caaddaf8
BA		 2563 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2564 index = (vid >> 5) & 0x7F;
2565 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2566 vfta &= ~(1 << (vid & 0x1F));
2567 hw->mac.ops.write_vfta(hw, index, vfta);
2568 }
86d70e53
JK		 2569
2570 clear_bit(vid, adapter->active_vlans);
bc7f75fa
AK		 2571}
2572
86d70e53
JK		 2573/**
2574 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2575 * @adapter: board private structure to initialize
2576 **/
2577static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2578{
2579 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2580 struct e1000_hw *hw = &adapter->hw;
2581 u32 rctl;
bc7f75fa 2582
86d70e53
JK		 2583 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2584 /* disable VLAN receive filtering */
2585 rctl = er32(RCTL);
2586 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2587 ew32(RCTL, rctl);
2588
2589 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2590 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2591 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2592 }
bc7f75fa
AK		 2593 }
2594}
2595
86d70e53
JK		 2596/**
2597 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2598 * @adapter: board private structure to initialize
2599 **/
2600static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2601{
2602 struct e1000_hw *hw = &adapter->hw;
2603 u32 rctl;
2604
2605 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2606 /* enable VLAN receive filtering */
2607 rctl = er32(RCTL);
2608 rctl |= E1000_RCTL_VFE;
2609 rctl &= ~E1000_RCTL_CFIEN;
2610 ew32(RCTL, rctl);
2611 }
2612}
bc7f75fa 2613
86d70e53
JK		 2614/**
2615 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2616 * @adapter: board private structure to initialize
2617 **/
2618static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2619{
bc7f75fa 2620 struct e1000_hw *hw = &adapter->hw;
86d70e53 2621 u32 ctrl;
bc7f75fa 2622
86d70e53
JK		 2623 /* disable VLAN tag insert/strip */
2624 ctrl = er32(CTRL);
2625 ctrl &= ~E1000_CTRL_VME;
2626 ew32(CTRL, ctrl);
2627}
bc7f75fa 2628
86d70e53
JK		 2629/**
2630 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2631 * @adapter: board private structure to initialize
2632 **/
2633static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2634{
2635 struct e1000_hw *hw = &adapter->hw;
2636 u32 ctrl;
bc7f75fa 2637
86d70e53
JK		 2638 /* enable VLAN tag insert/strip */
2639 ctrl = er32(CTRL);
2640 ctrl |= E1000_CTRL_VME;
2641 ew32(CTRL, ctrl);
2642}
bc7f75fa 2643
86d70e53
JK		 2644static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2645{
2646 struct net_device *netdev = adapter->netdev;
2647 u16 vid = adapter->hw.mng_cookie.vlan_id;
2648 u16 old_vid = adapter->mng_vlan_id;
2649
2650 if (adapter->hw.mng_cookie.status &
2651 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2652 e1000_vlan_rx_add_vid(netdev, vid);
2653 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2654 }
2655
86d70e53
JK		 2656 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2657 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2658}
2659
2660static void e1000_restore_vlan(struct e1000_adapter *adapter)
2661{
2662 u16 vid;
2663
86d70e53 2664 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2665
86d70e53 2666 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2667 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2668}
2669
cd791618 2670static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2671{
2672 struct e1000_hw *hw = &adapter->hw;
cd791618 2673 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2674
2675 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2676 return;
2677
2678 manc = er32(MANC);
2679
ad68076e
BA		 2680 /*
2681 * enable receiving management packets to the host. this will probably
bc7f75fa 2682 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2683 * the packets will be handled on SMBUS
2684 */
bc7f75fa
AK		 2685 manc |= E1000_MANC_EN_MNG2HOST;
2686 manc2h = er32(MANC2H);
cd791618
BA		 2687
2688 switch (hw->mac.type) {
2689 default:
2690 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2691 break;
2692 case e1000_82574:
2693 case e1000_82583:
2694 /*
2695 * Check if IPMI pass-through decision filter already exists;
2696 * if so, enable it.
2697 */
2698 for (i = 0, j = 0; i < 8; i++) {
2699 mdef = er32(MDEF(i));
2700
2701 /* Ignore filters with anything other than IPMI ports */
3b21b508 2702 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2703 continue;
2704
2705 /* Enable this decision filter in MANC2H */
2706 if (mdef)
2707 manc2h |= (1 << i);
2708
2709 j |= mdef;
2710 }
2711
2712 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2713 break;
2714
2715 /* Create new decision filter in an empty filter */
2716 for (i = 0, j = 0; i < 8; i++)
2717 if (er32(MDEF(i)) == 0) {
2718 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2719 E1000_MDEF_PORT_664));
2720 manc2h |= (1 << 1);
2721 j++;
2722 break;
2723 }
2724
2725 if (!j)
2726 e_warn("Unable to create IPMI pass-through filter\n");
2727 break;
2728 }
2729
bc7f75fa
AK		 2730 ew32(MANC2H, manc2h);
2731 ew32(MANC, manc);
2732}
2733
2734/**
af667a29 2735 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2736 * @adapter: board private structure
2737 *
2738 * Configure the Tx unit of the MAC after a reset.
2739 **/
2740static void e1000_configure_tx(struct e1000_adapter *adapter)
2741{
2742 struct e1000_hw *hw = &adapter->hw;
2743 struct e1000_ring *tx_ring = adapter->tx_ring;
2744 u64 tdba;
2745 u32 tdlen, tctl, tipg, tarc;
2746 u32 ipgr1, ipgr2;
2747
2748 /* Setup the HW Tx Head and Tail descriptor pointers */
2749 tdba = tx_ring->dma;
2750 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2751 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2752 ew32(TDBAH, (tdba >> 32));
2753 ew32(TDLEN, tdlen);
2754 ew32(TDH, 0);
2755 ew32(TDT, 0);
2756 tx_ring->head = E1000_TDH;
2757 tx_ring->tail = E1000_TDT;
2758
2759 /* Set the default values for the Tx Inter Packet Gap timer */
2760 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
2761 ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
2762 ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
2763
2764 if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
2765 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
2766
2767 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
2768 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
2769 ew32(TIPG, tipg);
2770
2771 /* Set the Tx Interrupt Delay register */
2772 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2773 /* Tx irq moderation */
bc7f75fa
AK		 2774 ew32(TADV, adapter->tx_abs_int_delay);
2775
3a3b7586
JB		 2776 if (adapter->flags2 & FLAG2_DMA_BURST) {
2777 u32 txdctl = er32(TXDCTL(0));
2778 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2779 E1000_TXDCTL_WTHRESH);
2780 /*
2781 * set up some performance related parameters to encourage the
2782 * hardware to use the bus more efficiently in bursts, depends
2783 * on the tx_int_delay to be enabled,
2784 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2785 * hthresh = 1 ==> prefetch when one or more available
2786 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2787 * BEWARE: this seems to work but should be considered first if
af667a29 2788 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2789 */
2790 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2791 ew32(TXDCTL(0), txdctl);
2792 /* erratum work around: set txdctl the same for both queues */
2793 ew32(TXDCTL(1), txdctl);
2794 }
2795
bc7f75fa
AK		 2796 /* Program the Transmit Control Register */
2797 tctl = er32(TCTL);
2798 tctl &= ~E1000_TCTL_CT;
2799 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2800 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2801
2802 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2803 tarc = er32(TARC(0));
ad68076e
BA		 2804 /*
2805 * set the speed mode bit, we'll clear it if we're not at
2806 * gigabit link later
2807 */
bc7f75fa
AK		 2808#define SPEED_MODE_BIT (1 << 21)
2809 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2810 ew32(TARC(0), tarc);
bc7f75fa
AK		 2811 }
2812
2813 /* errata: program both queues to unweighted RR */
2814 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2815 tarc = er32(TARC(0));
bc7f75fa 2816 tarc |= 1;
e9ec2c0f
JK		 2817 ew32(TARC(0), tarc);
2818 tarc = er32(TARC(1));
bc7f75fa 2819 tarc |= 1;
e9ec2c0f 2820 ew32(TARC(1), tarc);
bc7f75fa
AK		 2821 }
2822
bc7f75fa
AK		 2823 /* Setup Transmit Descriptor Settings for eop descriptor */
2824 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2825
2826 /* only set IDE if we are delaying interrupts using the timers */
2827 if (adapter->tx_int_delay)
2828 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2829
2830 /* enable Report Status bit */
2831 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2832
2833 ew32(TCTL, tctl);
2834
edfea6e6 2835 e1000e_config_collision_dist(hw);
bc7f75fa
AK		 2836}
2837
2838/**
2839 * e1000_setup_rctl - configure the receive control registers
2840 * @adapter: Board private structure
2841 **/
2842#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2843 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2844static void e1000_setup_rctl(struct e1000_adapter *adapter)
2845{
2846 struct e1000_hw *hw = &adapter->hw;
2847 u32 rctl, rfctl;
bc7f75fa
AK		 2848 u32 pages = 0;
2849
a1ce6473
BA		 2850 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2851 if (hw->mac.type == e1000_pch2lan) {
2852 s32 ret_val;
2853
2854 if (adapter->netdev->mtu > ETH_DATA_LEN)
2855 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2856 else
2857 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2858
2859 if (ret_val)
2860 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2861 }
2862
bc7f75fa
AK		 2863 /* Program MC offset vector base */
2864 rctl = er32(RCTL);
2865 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2866 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2867 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2868 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2869
2870 /* Do not Store bad packets */
2871 rctl &= ~E1000_RCTL_SBP;
2872
2873 /* Enable Long Packet receive */
2874 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2875 rctl &= ~E1000_RCTL_LPE;
2876 else
2877 rctl |= E1000_RCTL_LPE;
2878
eb7c3adb
JK		 2879 /* Some systems expect that the CRC is included in SMBUS traffic. The
2880 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2881 * host memory when this is enabled
2882 */
2883 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2884 rctl |= E1000_RCTL_SECRC;
5918bd88 2885
a4f58f54
BA		 2886 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2887 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2888 u16 phy_data;
2889
2890 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2891 phy_data &= 0xfff8;
2892 phy_data |= (1 << 2);
2893 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2894
2895 e1e_rphy(hw, 22, &phy_data);
2896 phy_data &= 0x0fff;
2897 phy_data |= (1 << 14);
2898 e1e_wphy(hw, 0x10, 0x2823);
2899 e1e_wphy(hw, 0x11, 0x0003);
2900 e1e_wphy(hw, 22, phy_data);
2901 }
2902
bc7f75fa
AK		 2903 /* Setup buffer sizes */
2904 rctl &= ~E1000_RCTL_SZ_4096;
2905 rctl |= E1000_RCTL_BSEX;
2906 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2907 case 2048:
2908 default:
2909 rctl |= E1000_RCTL_SZ_2048;
2910 rctl &= ~E1000_RCTL_BSEX;
2911 break;
2912 case 4096:
2913 rctl |= E1000_RCTL_SZ_4096;
2914 break;
2915 case 8192:
2916 rctl |= E1000_RCTL_SZ_8192;
2917 break;
2918 case 16384:
2919 rctl |= E1000_RCTL_SZ_16384;
2920 break;
2921 }
2922
5f450212
BA		 2923 /* Enable Extended Status in all Receive Descriptors */
2924 rfctl = er32(RFCTL);
2925 rfctl |= E1000_RFCTL_EXTEN;
2926
bc7f75fa
AK		 2927 /*
2928 * 82571 and greater support packet-split where the protocol
2929 * header is placed in skb->data and the packet data is
2930 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2931 * In the case of a non-split, skb->data is linearly filled,
2932 * followed by the page buffers. Therefore, skb->data is
2933 * sized to hold the largest protocol header.
2934 *
2935 * allocations using alloc_page take too long for regular MTU
2936 * so only enable packet split for jumbo frames
2937 *
2938 * Using pages when the page size is greater than 16k wastes
2939 * a lot of memory, since we allocate 3 pages at all times
2940 * per packet.
2941 */
bc7f75fa 2942 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
dbcb9fec 2943 if (!(adapter->flags & FLAG_HAS_ERT) && (pages <= 3) &&
97ac8cae 2944 (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2945 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2946 else
2947 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2948
2949 if (adapter->rx_ps_pages) {
90da0669
BA		 2950 u32 psrctl = 0;
2951
ad68076e
BA		 2952 /*
2953 * disable packet split support for IPv6 extension headers,
2954 * because some malformed IPv6 headers can hang the Rx
2955 */
bc7f75fa
AK		 2956 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2957 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2958
140a7480
AK		 2959 /* Enable Packet split descriptors */
2960 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2961
2962 psrctl |= adapter->rx_ps_bsize0 >>
2963 E1000_PSRCTL_BSIZE0_SHIFT;
2964
2965 switch (adapter->rx_ps_pages) {
2966 case 3:
2967 psrctl |= PAGE_SIZE <<
2968 E1000_PSRCTL_BSIZE3_SHIFT;
2969 case 2:
2970 psrctl |= PAGE_SIZE <<
2971 E1000_PSRCTL_BSIZE2_SHIFT;
2972 case 1:
2973 psrctl |= PAGE_SIZE >>
2974 E1000_PSRCTL_BSIZE1_SHIFT;
2975 break;
2976 }
2977
2978 ew32(PSRCTL, psrctl);
2979 }
2980
5f450212 2981 ew32(RFCTL, rfctl);
bc7f75fa 2982 ew32(RCTL, rctl);
318a94d6
JK		 2983 /* just started the receive unit, no need to restart */
2984 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 2985}
2986
2987/**
2988 * e1000_configure_rx - Configure Receive Unit after Reset
2989 * @adapter: board private structure
2990 *
2991 * Configure the Rx unit of the MAC after a reset.
2992 **/
2993static void e1000_configure_rx(struct e1000_adapter *adapter)
2994{
2995 struct e1000_hw *hw = &adapter->hw;
2996 struct e1000_ring *rx_ring = adapter->rx_ring;
2997 u64 rdba;
2998 u32 rdlen, rctl, rxcsum, ctrl_ext;
2999
3000 if (adapter->rx_ps_pages) {
3001 /* this is a 32 byte descriptor */
3002 rdlen = rx_ring->count *
af667a29 3003 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3004 adapter->clean_rx = e1000_clean_rx_irq_ps;
3005 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3006 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3007 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3008 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3009 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3010 } else {
5f450212 3011 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3012 adapter->clean_rx = e1000_clean_rx_irq;
3013 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3014 }
3015
3016 /* disable receives while setting up the descriptors */
3017 rctl = er32(RCTL);
7f99ae63
BA		 3018 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3019 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3020 e1e_flush();
1bba4386 3021 usleep_range(10000, 20000);
bc7f75fa 3022
3a3b7586
JB		 3023 if (adapter->flags2 & FLAG2_DMA_BURST) {
3024 /*
3025 * set the writeback threshold (only takes effect if the RDTR
3026 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3027 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3028 * granularity = 01
3029 * wthresh = 04,
3030 * hthresh = 04,
3031 * pthresh = 0x20
3032 */
3033 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3034 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3035
3036 /*
3037 * override the delay timers for enabling bursting, only if
3038 * the value was not set by the user via module options
3039 */
3040 if (adapter->rx_int_delay == DEFAULT_RDTR)
3041 adapter->rx_int_delay = BURST_RDTR;
3042 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3043 adapter->rx_abs_int_delay = BURST_RADV;
3044 }
3045
bc7f75fa
AK		 3046 /* set the Receive Delay Timer Register */
3047 ew32(RDTR, adapter->rx_int_delay);
3048
3049 /* irq moderation */
3050 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3051 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3052 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3053
3054 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3055 /* Auto-Mask interrupts upon ICR access */
3056 ctrl_ext |= E1000_CTRL_EXT_IAME;
3057 ew32(IAM, 0xffffffff);
3058 ew32(CTRL_EXT, ctrl_ext);
3059 e1e_flush();
3060
ad68076e
BA		 3061 /*
3062 * Setup the HW Rx Head and Tail Descriptor Pointers and
3063 * the Base and Length of the Rx Descriptor Ring
3064 */
bc7f75fa 3065 rdba = rx_ring->dma;
284901a9 3066 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3067 ew32(RDBAH, (rdba >> 32));
3068 ew32(RDLEN, rdlen);
3069 ew32(RDH, 0);
3070 ew32(RDT, 0);
3071 rx_ring->head = E1000_RDH;
3072 rx_ring->tail = E1000_RDT;
3073
3074 /* Enable Receive Checksum Offload for TCP and UDP */
3075 rxcsum = er32(RXCSUM);
dc221294 3076 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3077 rxcsum |= E1000_RXCSUM_TUOFL;
3078
ad68076e
BA		 3079 /*
3080 * IPv4 payload checksum for UDP fragments must be
3081 * used in conjunction with packet-split.
3082 */
bc7f75fa
AK		 3083 if (adapter->rx_ps_pages)
3084 rxcsum |= E1000_RXCSUM_IPPCSE;
3085 } else {
3086 rxcsum &= ~E1000_RXCSUM_TUOFL;
3087 /* no need to clear IPPCSE as it defaults to 0 */
3088 }
3089 ew32(RXCSUM, rxcsum);
3090
ad68076e
BA		 3091 /*
3092 * Enable early receives on supported devices, only takes effect when
bc7f75fa 3093 * packet size is equal or larger than the specified value (in 8 byte
ad68076e
BA		 3094 * units), e.g. using jumbo frames when setting to E1000_ERT_2048
3095 */
828bac87
BA		 3096 if ((adapter->flags & FLAG_HAS_ERT) ||
3097 (adapter->hw.mac.type == e1000_pch2lan)) {
53ec5498
BA		 3098 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3099 u32 rxdctl = er32(RXDCTL(0));
3100 ew32(RXDCTL(0), rxdctl | 0x3);
828bac87
BA		 3101 if (adapter->flags & FLAG_HAS_ERT)
3102 ew32(ERT, E1000_ERT_2048 | (1 << 13));
53ec5498
BA		 3103 /*
3104 * With jumbo frames and early-receive enabled,
3105 * excessive C-state transition latencies result in
3106 * dropped transactions.
3107 */
af667a29 3108 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3109 } else {
af667a29
BA		 3110 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3111 PM_QOS_DEFAULT_VALUE);
53ec5498 3112 }
97ac8cae 3113 }
bc7f75fa
AK		 3114
3115 /* Enable Receives */
3116 ew32(RCTL, rctl);
3117}
3118
3119/**
ef9b965a
JB		 3120 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3121 * @netdev: network interface device structure
bc7f75fa 3122 *
ef9b965a
JB		 3123 * Writes multicast address list to the MTA hash table.
3124 * Returns: -ENOMEM on failure
3125 * 0 on no addresses written
3126 * X on writing X addresses to MTA
3127 */
3128static int e1000e_write_mc_addr_list(struct net_device *netdev)
3129{
3130 struct e1000_adapter *adapter = netdev_priv(netdev);
3131 struct e1000_hw *hw = &adapter->hw;
3132 struct netdev_hw_addr *ha;
3133 u8 *mta_list;
3134 int i;
3135
3136 if (netdev_mc_empty(netdev)) {
3137 /* nothing to program, so clear mc list */
3138 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3139 return 0;
3140 }
3141
3142 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3143 if (!mta_list)
3144 return -ENOMEM;
3145
3146 /* update_mc_addr_list expects a packed array of only addresses. */
3147 i = 0;
3148 netdev_for_each_mc_addr(ha, netdev)
3149 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3150
3151 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3152 kfree(mta_list);
3153
3154 return netdev_mc_count(netdev);
3155}
3156
3157/**
3158 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3159 * @netdev: network interface device structure
bc7f75fa 3160 *
ef9b965a
JB		 3161 * Writes unicast address list to the RAR table.
3162 * Returns: -ENOMEM on failure/insufficient address space
3163 * 0 on no addresses written
3164 * X on writing X addresses to the RAR table
bc7f75fa 3165 **/
ef9b965a 3166static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3167{
ef9b965a
JB		 3168 struct e1000_adapter *adapter = netdev_priv(netdev);
3169 struct e1000_hw *hw = &adapter->hw;
3170 unsigned int rar_entries = hw->mac.rar_entry_count;
3171 int count = 0;
3172
3173 /* save a rar entry for our hardware address */
3174 rar_entries--;
3175
3176 /* save a rar entry for the LAA workaround */
3177 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3178 rar_entries--;
3179
3180 /* return ENOMEM indicating insufficient memory for addresses */
3181 if (netdev_uc_count(netdev) > rar_entries)
3182 return -ENOMEM;
3183
3184 if (!netdev_uc_empty(netdev) && rar_entries) {
3185 struct netdev_hw_addr *ha;
3186
3187 /*
3188 * write the addresses in reverse order to avoid write
3189 * combining
3190 */
3191 netdev_for_each_uc_addr(ha, netdev) {
3192 if (!rar_entries)
3193 break;
3194 e1000e_rar_set(hw, ha->addr, rar_entries--);
3195 count++;
3196 }
3197 }
3198
3199 /* zero out the remaining RAR entries not used above */
3200 for (; rar_entries > 0; rar_entries--) {
3201 ew32(RAH(rar_entries), 0);
3202 ew32(RAL(rar_entries), 0);
3203 }
3204 e1e_flush();
3205
3206 return count;
bc7f75fa
AK		 3207}
3208
3209/**
ef9b965a 3210 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3211 * @netdev: network interface device structure
3212 *
ef9b965a
JB		 3213 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3214 * address list or the network interface flags are updated. This routine is
3215 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3216 * promiscuous mode, and all-multi behavior.
3217 **/
ef9b965a 3218static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3219{
3220 struct e1000_adapter *adapter = netdev_priv(netdev);
3221 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3222 u32 rctl;
bc7f75fa
AK		 3223
3224 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3225 rctl = er32(RCTL);
3226
ef9b965a
JB		 3227 /* clear the affected bits */
3228 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3229
bc7f75fa
AK		 3230 if (netdev->flags & IFF_PROMISC) {
3231 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3232 /* Do not hardware filter VLANs in promisc mode */
3233 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3234 } else {
ef9b965a 3235 int count;
746b9f02
PM		 3236 if (netdev->flags & IFF_ALLMULTI) {
3237 rctl |= E1000_RCTL_MPE;
746b9f02 3238 } else {
ef9b965a
JB		 3239 /*
3240 * Write addresses to the MTA, if the attempt fails
3241 * then we should just turn on promiscuous mode so
3242 * that we can at least receive multicast traffic
3243 */
3244 count = e1000e_write_mc_addr_list(netdev);
3245 if (count < 0)
3246 rctl |= E1000_RCTL_MPE;
746b9f02 3247 }
86d70e53 3248 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3249 /*
ef9b965a
JB		 3250 * Write addresses to available RAR registers, if there is not
3251 * sufficient space to store all the addresses then enable
3252 * unicast promiscuous mode
bc7f75fa 3253 */
ef9b965a
JB		 3254 count = e1000e_write_uc_addr_list(netdev);
3255 if (count < 0)
3256 rctl |= E1000_RCTL_UPE;
bc7f75fa 3257 }
86d70e53 3258
ef9b965a
JB		 3259 ew32(RCTL, rctl);
3260
86d70e53
JK		 3261 if (netdev->features & NETIF_F_HW_VLAN_RX)
3262 e1000e_vlan_strip_enable(adapter);
3263 else
3264 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3265}
3266
3267/**
ad68076e 3268 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3269 * @adapter: private board structure
3270 **/
3271static void e1000_configure(struct e1000_adapter *adapter)
3272{
ef9b965a 3273 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3274
3275 e1000_restore_vlan(adapter);
cd791618 3276 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3277
3278 e1000_configure_tx(adapter);
3279 e1000_setup_rctl(adapter);
3280 e1000_configure_rx(adapter);
c2fed996
JK		 3281 adapter->alloc_rx_buf(adapter, e1000_desc_unused(adapter->rx_ring),
3282 GFP_KERNEL);
bc7f75fa
AK		 3283}
3284
3285/**
3286 * e1000e_power_up_phy - restore link in case the phy was powered down
3287 * @adapter: address of board private structure
3288 *
3289 * The phy may be powered down to save power and turn off link when the
3290 * driver is unloaded and wake on lan is not enabled (among others)
3291 * *** this routine MUST be followed by a call to e1000e_reset ***
3292 **/
3293void e1000e_power_up_phy(struct e1000_adapter *adapter)
3294{
17f208de
BA		 3295 if (adapter->hw.phy.ops.power_up)
3296 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3297
3298 adapter->hw.mac.ops.setup_link(&adapter->hw);
3299}
3300
3301/**
3302 * e1000_power_down_phy - Power down the PHY
3303 *
17f208de
BA		 3304 * Power down the PHY so no link is implied when interface is down.
3305 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3306 */
3307static void e1000_power_down_phy(struct e1000_adapter *adapter)
3308{
bc7f75fa 3309 /* WoL is enabled */
23b66e2b 3310 if (adapter->wol)
bc7f75fa
AK		 3311 return;
3312
17f208de
BA		 3313 if (adapter->hw.phy.ops.power_down)
3314 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3315}
3316
3317/**
3318 * e1000e_reset - bring the hardware into a known good state
3319 *
3320 * This function boots the hardware and enables some settings that
3321 * require a configuration cycle of the hardware - those cannot be
3322 * set/changed during runtime. After reset the device needs to be
ad68076e 3323 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3324 */
3325void e1000e_reset(struct e1000_adapter *adapter)
3326{
3327 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3328 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3329 struct e1000_hw *hw = &adapter->hw;
3330 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3331 u32 pba = adapter->pba;
bc7f75fa
AK		 3332 u16 hwm;
3333
ad68076e 3334 /* reset Packet Buffer Allocation to default */
318a94d6 3335 ew32(PBA, pba);
df762464 3336
318a94d6 3337 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3338 /*
3339 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3340 * large enough to accommodate two full transmit packets,
3341 * rounded up to the next 1KB and expressed in KB. Likewise,
3342 * the Rx FIFO should be large enough to accommodate at least
3343 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3344 * expressed in KB.
3345 */
df762464 3346 pba = er32(PBA);
bc7f75fa 3347 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3348 tx_space = pba >> 16;
bc7f75fa 3349 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3350 pba &= 0xffff;
ad68076e 3351 /*
af667a29 3352 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3353 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3354 */
3355 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3356 sizeof(struct e1000_tx_desc) -
3357 ETH_FCS_LEN) * 2;
3358 min_tx_space = ALIGN(min_tx_space, 1024);
3359 min_tx_space >>= 10;
3360 /* software strips receive CRC, so leave room for it */
318a94d6 3361 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3362 min_rx_space = ALIGN(min_rx_space, 1024);
3363 min_rx_space >>= 10;
3364
ad68076e
BA		 3365 /*
3366 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3367 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3368 * allocation, take space away from current Rx allocation
3369 */
df762464
AK		 3370 if ((tx_space < min_tx_space) &&
3371 ((min_tx_space - tx_space) < pba)) {
3372 pba -= min_tx_space - tx_space;
bc7f75fa 3373
ad68076e 3374 /*
af667a29 3375 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3376 * adjustment or use Early Receive if available
3377 */
df762464 3378 if ((pba < min_rx_space) &&
bc7f75fa
AK		 3379 (!(adapter->flags & FLAG_HAS_ERT)))
3380 /* ERT enabled in e1000_configure_rx */
df762464 3381 pba = min_rx_space;
bc7f75fa 3382 }
df762464
AK		 3383
3384 ew32(PBA, pba);
bc7f75fa
AK		 3385 }
3386
ad68076e
BA		 3387 /*
3388 * flow control settings
3389 *
38eb394e 3390 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3391 * (or the size used for early receive) above it in the Rx FIFO.
3392 * Set it to the lower of:
3393 * - 90% of the Rx FIFO size, and
3394 * - the full Rx FIFO size minus the early receive size (for parts
3395 * with ERT support assuming ERT set to E1000_ERT_2048), or
38eb394e 3396 * - the full Rx FIFO size minus one full frame
ad68076e 3397 */
d3738bb8
BA		 3398 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3399 fc->pause_time = 0xFFFF;
3400 else
3401 fc->pause_time = E1000_FC_PAUSE_TIME;
3402 fc->send_xon = 1;
3403 fc->current_mode = fc->requested_mode;
3404
3405 switch (hw->mac.type) {
3406 default:
3407 if ((adapter->flags & FLAG_HAS_ERT) &&
3408 (adapter->netdev->mtu > ETH_DATA_LEN))
3409 hwm = min(((pba << 10) * 9 / 10),
3410 ((pba << 10) - (E1000_ERT_2048 << 3)));
3411 else
3412 hwm = min(((pba << 10) * 9 / 10),
3413 ((pba << 10) - adapter->max_frame_size));
3414
3415 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3416 fc->low_water = fc->high_water - 8;
3417 break;
3418 case e1000_pchlan:
38eb394e
BA		 3419 /*
3420 * Workaround PCH LOM adapter hangs with certain network
3421 * loads. If hangs persist, try disabling Tx flow control.
3422 */
3423 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3424 fc->high_water = 0x3500;
3425 fc->low_water = 0x1500;
3426 } else {
3427 fc->high_water = 0x5000;
3428 fc->low_water = 0x3000;
3429 }
a305595b 3430 fc->refresh_time = 0x1000;
d3738bb8
BA		 3431 break;
3432 case e1000_pch2lan:
3433 fc->high_water = 0x05C20;
3434 fc->low_water = 0x05048;
3435 fc->pause_time = 0x0650;
3436 fc->refresh_time = 0x0400;
828bac87
BA		 3437 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3438 pba = 14;
3439 ew32(PBA, pba);
3440 }
d3738bb8 3441 break;
38eb394e 3442 }
bc7f75fa 3443
828bac87
BA		 3444 /*
3445 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3446 * fit in receive buffer and early-receive not supported.
3447 */
3448 if (adapter->itr_setting & 0x3) {
3449 if (((adapter->max_frame_size * 2) > (pba << 10)) &&
3450 !(adapter->flags & FLAG_HAS_ERT)) {
3451 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3452 dev_info(&adapter->pdev->dev,
3453 "Interrupt Throttle Rate turned off\n");
3454 adapter->flags2 |= FLAG2_DISABLE_AIM;
3455 ew32(ITR, 0);
3456 }
3457 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3458 dev_info(&adapter->pdev->dev,
3459 "Interrupt Throttle Rate turned on\n");
3460 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3461 adapter->itr = 20000;
3462 ew32(ITR, 1000000000 / (adapter->itr * 256));
3463 }
3464 }
3465
bc7f75fa
AK		 3466 /* Allow time for pending master requests to run */
3467 mac->ops.reset_hw(hw);
97ac8cae
BA		 3468
3469 /*
3470 * For parts with AMT enabled, let the firmware know
3471 * that the network interface is in control
3472 */
c43bc57e 3473 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3474 e1000e_get_hw_control(adapter);
97ac8cae 3475
bc7f75fa
AK		 3476 ew32(WUC, 0);
3477
3478 if (mac->ops.init_hw(hw))
44defeb3 3479 e_err("Hardware Error\n");
bc7f75fa
AK		 3480
3481 e1000_update_mng_vlan(adapter);
3482
3483 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3484 ew32(VET, ETH_P_8021Q);
3485
3486 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3487
3488 if (!netif_running(adapter->netdev) &&
3489 !test_bit(__E1000_TESTING, &adapter->state)) {
3490 e1000_power_down_phy(adapter);
3491 return;
3492 }
3493
bc7f75fa
AK		 3494 e1000_get_phy_info(hw);
3495
918d7197
BA		 3496 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3497 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3498 u16 phy_data = 0;
ad68076e
BA		 3499 /*
3500 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3501 * the return value of this function because there is nothing
ad68076e
BA		 3502 * different we would do if it failed
3503 */
bc7f75fa
AK		 3504 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3505 phy_data &= ~IGP02E1000_PM_SPD;
3506 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3507 }
bc7f75fa
AK		 3508}
3509
3510int e1000e_up(struct e1000_adapter *adapter)
3511{
3512 struct e1000_hw *hw = &adapter->hw;
3513
3514 /* hardware has been reset, we need to reload some things */
3515 e1000_configure(adapter);
3516
3517 clear_bit(__E1000_DOWN, &adapter->state);
3518
4662e82b
BA		 3519 if (adapter->msix_entries)
3520 e1000_configure_msix(adapter);
bc7f75fa
AK		 3521 e1000_irq_enable(adapter);
3522
400484fa 3523 netif_start_queue(adapter->netdev);
4cb9be7a 3524
bc7f75fa 3525 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3526 if (adapter->msix_entries)
3527 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3528 else
3529 ew32(ICS, E1000_ICS_LSC);
3530
bc7f75fa
AK		 3531 return 0;
3532}
3533
713b3c9e
JB		 3534static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3535{
3536 struct e1000_hw *hw = &adapter->hw;
3537
3538 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3539 return;
3540
3541 /* flush pending descriptor writebacks to memory */
3542 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3543 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3544
3545 /* execute the writes immediately */
3546 e1e_flush();
3547}
3548
67fd4fcb
JK		 3549static void e1000e_update_stats(struct e1000_adapter *adapter);
3550
bc7f75fa
AK		 3551void e1000e_down(struct e1000_adapter *adapter)
3552{
3553 struct net_device *netdev = adapter->netdev;
3554 struct e1000_hw *hw = &adapter->hw;
3555 u32 tctl, rctl;
3556
ad68076e
BA		 3557 /*
3558 * signal that we're down so the interrupt handler does not
3559 * reschedule our watchdog timer
3560 */
bc7f75fa
AK		 3561 set_bit(__E1000_DOWN, &adapter->state);
3562
3563 /* disable receives in the hardware */
3564 rctl = er32(RCTL);
7f99ae63
BA		 3565 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3566 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3567 /* flush and sleep below */
3568
4cb9be7a 3569 netif_stop_queue(netdev);
bc7f75fa
AK		 3570
3571 /* disable transmits in the hardware */
3572 tctl = er32(TCTL);
3573 tctl &= ~E1000_TCTL_EN;
3574 ew32(TCTL, tctl);
7f99ae63 3575
bc7f75fa
AK		 3576 /* flush both disables and wait for them to finish */
3577 e1e_flush();
1bba4386 3578 usleep_range(10000, 20000);
bc7f75fa 3579
bc7f75fa
AK		 3580 e1000_irq_disable(adapter);
3581
3582 del_timer_sync(&adapter->watchdog_timer);
3583 del_timer_sync(&adapter->phy_info_timer);
3584
bc7f75fa 3585 netif_carrier_off(netdev);
67fd4fcb
JK		 3586
3587 spin_lock(&adapter->stats64_lock);
3588 e1000e_update_stats(adapter);
3589 spin_unlock(&adapter->stats64_lock);
3590
400484fa
BA		 3591 e1000e_flush_descriptors(adapter);
3592 e1000_clean_tx_ring(adapter);
3593 e1000_clean_rx_ring(adapter);
3594
bc7f75fa
AK		 3595 adapter->link_speed = 0;
3596 adapter->link_duplex = 0;
3597
52cc3086
JK		 3598 if (!pci_channel_offline(adapter->pdev))
3599 e1000e_reset(adapter);
713b3c9e 3600
bc7f75fa
AK		 3601 /*
3602 * TODO: for power management, we could drop the link and
3603 * pci_disable_device here.
3604 */
3605}
3606
3607void e1000e_reinit_locked(struct e1000_adapter *adapter)
3608{
3609 might_sleep();
3610 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3611 usleep_range(1000, 2000);
bc7f75fa
AK		 3612 e1000e_down(adapter);
3613 e1000e_up(adapter);
3614 clear_bit(__E1000_RESETTING, &adapter->state);
3615}
3616
3617/**
3618 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3619 * @adapter: board private structure to initialize
3620 *
3621 * e1000_sw_init initializes the Adapter private data structure.
3622 * Fields are initialized based on PCI device information and
3623 * OS network device settings (MTU size).
3624 **/
3625static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3626{
bc7f75fa
AK		 3627 struct net_device *netdev = adapter->netdev;
3628
3629 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3630 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3631 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3632 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
bc7f75fa 3633
67fd4fcb
JK		 3634 spin_lock_init(&adapter->stats64_lock);
3635
4662e82b 3636 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3637
4662e82b
BA		 3638 if (e1000_alloc_queues(adapter))
3639 return -ENOMEM;
bc7f75fa 3640
bc7f75fa 3641 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3642 e1000_irq_disable(adapter);
3643
bc7f75fa
AK		 3644 set_bit(__E1000_DOWN, &adapter->state);
3645 return 0;
bc7f75fa
AK		 3646}
3647
f8d59f78
BA		 3648/**
3649 * e1000_intr_msi_test - Interrupt Handler
3650 * @irq: interrupt number
3651 * @data: pointer to a network interface device structure
3652 **/
3653static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3654{
3655 struct net_device *netdev = data;
3656 struct e1000_adapter *adapter = netdev_priv(netdev);
3657 struct e1000_hw *hw = &adapter->hw;
3658 u32 icr = er32(ICR);
3659
3bb99fe2 3660 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3661 if (icr & E1000_ICR_RXSEQ) {
3662 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3663 wmb();
3664 }
3665
3666 return IRQ_HANDLED;
3667}
3668
3669/**
3670 * e1000_test_msi_interrupt - Returns 0 for successful test
3671 * @adapter: board private struct
3672 *
3673 * code flow taken from tg3.c
3674 **/
3675static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3676{
3677 struct net_device *netdev = adapter->netdev;
3678 struct e1000_hw *hw = &adapter->hw;
3679 int err;
3680
3681 /* poll_enable hasn't been called yet, so don't need disable */
3682 /* clear any pending events */
3683 er32(ICR);
3684
3685 /* free the real vector and request a test handler */
3686 e1000_free_irq(adapter);
4662e82b 3687 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3688
3689 /* Assume that the test fails, if it succeeds then the test
3690 * MSI irq handler will unset this flag */
3691 adapter->flags |= FLAG_MSI_TEST_FAILED;
3692
3693 err = pci_enable_msi(adapter->pdev);
3694 if (err)
3695 goto msi_test_failed;
3696
a0607fd3 3697 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3698 netdev->name, netdev);
3699 if (err) {
3700 pci_disable_msi(adapter->pdev);
3701 goto msi_test_failed;
3702 }
3703
3704 wmb();
3705
3706 e1000_irq_enable(adapter);
3707
3708 /* fire an unusual interrupt on the test handler */
3709 ew32(ICS, E1000_ICS_RXSEQ);
3710 e1e_flush();
3711 msleep(50);
3712
3713 e1000_irq_disable(adapter);
3714
3715 rmb();
3716
3717 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3718 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30
JD		 3719 e_info("MSI interrupt test failed, using legacy interrupt.\n");
3720 } else
3721 e_dbg("MSI interrupt test succeeded!\n");
f8d59f78
BA		 3722
3723 free_irq(adapter->pdev->irq, netdev);
3724 pci_disable_msi(adapter->pdev);
3725
f8d59f78 3726msi_test_failed:
4662e82b 3727 e1000e_set_interrupt_capability(adapter);
068e8a30 3728 return e1000_request_irq(adapter);
f8d59f78
BA		 3729}
3730
3731/**
3732 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3733 * @adapter: board private struct
3734 *
3735 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3736 **/
3737static int e1000_test_msi(struct e1000_adapter *adapter)
3738{
3739 int err;
3740 u16 pci_cmd;
3741
3742 if (!(adapter->flags & FLAG_MSI_ENABLED))
3743 return 0;
3744
3745 /* disable SERR in case the MSI write causes a master abort */
3746 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3747 if (pci_cmd & PCI_COMMAND_SERR)
3748 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3749 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3750
3751 err = e1000_test_msi_interrupt(adapter);
3752
36f2407f
DN		 3753 /* re-enable SERR */
3754 if (pci_cmd & PCI_COMMAND_SERR) {
3755 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3756 pci_cmd |= PCI_COMMAND_SERR;
3757 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3758 }
f8d59f78 3759
f8d59f78
BA		 3760 return err;
3761}
3762
bc7f75fa
AK		 3763/**
3764 * e1000_open - Called when a network interface is made active
3765 * @netdev: network interface device structure
3766 *
3767 * Returns 0 on success, negative value on failure
3768 *
3769 * The open entry point is called when a network interface is made
3770 * active by the system (IFF_UP). At this point all resources needed
3771 * for transmit and receive operations are allocated, the interrupt
3772 * handler is registered with the OS, the watchdog timer is started,
3773 * and the stack is notified that the interface is ready.
3774 **/
3775static int e1000_open(struct net_device *netdev)
3776{
3777 struct e1000_adapter *adapter = netdev_priv(netdev);
3778 struct e1000_hw *hw = &adapter->hw;
23606cf5 3779 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3780 int err;
3781
3782 /* disallow open during test */
3783 if (test_bit(__E1000_TESTING, &adapter->state))
3784 return -EBUSY;
3785
23606cf5
RW		 3786 pm_runtime_get_sync(&pdev->dev);
3787
9c563d20
JB		 3788 netif_carrier_off(netdev);
3789
bc7f75fa
AK		 3790 /* allocate transmit descriptors */
3791 err = e1000e_setup_tx_resources(adapter);
3792 if (err)
3793 goto err_setup_tx;
3794
3795 /* allocate receive descriptors */
3796 err = e1000e_setup_rx_resources(adapter);
3797 if (err)
3798 goto err_setup_rx;
3799
11b08be8
BA		 3800 /*
3801 * If AMT is enabled, let the firmware know that the network
3802 * interface is now open and reset the part to a known state.
3803 */
3804 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3805 e1000e_get_hw_control(adapter);
11b08be8
BA		 3806 e1000e_reset(adapter);
3807 }
3808
bc7f75fa
AK		 3809 e1000e_power_up_phy(adapter);
3810
3811 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3812 if ((adapter->hw.mng_cookie.status &
3813 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3814 e1000_update_mng_vlan(adapter);
3815
c128ec29 3816 /* DMA latency requirement to workaround early-receive/jumbo issue */
828bac87
BA		 3817 if ((adapter->flags & FLAG_HAS_ERT) ||
3818 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014
LT		 3819 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3820 PM_QOS_CPU_DMA_LATENCY,
3821 PM_QOS_DEFAULT_VALUE);
c128ec29 3822
ad68076e
BA		 3823 /*
3824 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3825 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3826 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3827 * clean_rx handler before we do so.
3828 */
bc7f75fa
AK		 3829 e1000_configure(adapter);
3830
3831 err = e1000_request_irq(adapter);
3832 if (err)
3833 goto err_req_irq;
3834
f8d59f78
BA		 3835 /*
3836 * Work around PCIe errata with MSI interrupts causing some chipsets to
3837 * ignore e1000e MSI messages, which means we need to test our MSI
3838 * interrupt now
3839 */
4662e82b 3840 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3841 err = e1000_test_msi(adapter);
3842 if (err) {
3843 e_err("Interrupt allocation failed\n");
3844 goto err_req_irq;
3845 }
3846 }
3847
bc7f75fa
AK		 3848 /* From here on the code is the same as e1000e_up() */
3849 clear_bit(__E1000_DOWN, &adapter->state);
3850
3851 napi_enable(&adapter->napi);
3852
3853 e1000_irq_enable(adapter);
3854
09357b00 3855 adapter->tx_hang_recheck = false;
4cb9be7a 3856 netif_start_queue(netdev);
d55b53ff 3857
23606cf5
RW		 3858 adapter->idle_check = true;
3859 pm_runtime_put(&pdev->dev);
3860
bc7f75fa 3861 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3862 if (adapter->msix_entries)
3863 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3864 else
3865 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3866
3867 return 0;
3868
3869err_req_irq:
31dbe5b4 3870 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 3871 e1000_power_down_phy(adapter);
3872 e1000e_free_rx_resources(adapter);
3873err_setup_rx:
3874 e1000e_free_tx_resources(adapter);
3875err_setup_tx:
3876 e1000e_reset(adapter);
23606cf5 3877 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3878
3879 return err;
3880}
3881
3882/**
3883 * e1000_close - Disables a network interface
3884 * @netdev: network interface device structure
3885 *
3886 * Returns 0, this is not allowed to fail
3887 *
3888 * The close entry point is called when an interface is de-activated
3889 * by the OS. The hardware is still under the drivers control, but
3890 * needs to be disabled. A global MAC reset is issued to stop the
3891 * hardware, and all transmit and receive resources are freed.
3892 **/
3893static int e1000_close(struct net_device *netdev)
3894{
3895 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3896 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3897
3898 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3899
3900 pm_runtime_get_sync(&pdev->dev);
3901
5f4a780d
BA		 3902 napi_disable(&adapter->napi);
3903
23606cf5
RW		 3904 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3905 e1000e_down(adapter);
3906 e1000_free_irq(adapter);
3907 }
bc7f75fa 3908 e1000_power_down_phy(adapter);
bc7f75fa
AK		 3909
3910 e1000e_free_tx_resources(adapter);
3911 e1000e_free_rx_resources(adapter);
3912
ad68076e
BA		 3913 /*
3914 * kill manageability vlan ID if supported, but not if a vlan with
3915 * the same ID is registered on the host OS (let 8021q kill it)
3916 */
86d70e53
JK		 3917 if (adapter->hw.mng_cookie.status &
3918 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3919 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3920
ad68076e
BA		 3921 /*
3922 * If AMT is enabled, let the firmware know that the network
3923 * interface is now closed
3924 */
31dbe5b4
BA		 3925 if ((adapter->flags & FLAG_HAS_AMT) &&
3926 !test_bit(__E1000_TESTING, &adapter->state))
3927 e1000e_release_hw_control(adapter);
bc7f75fa 3928
828bac87
BA		 3929 if ((adapter->flags & FLAG_HAS_ERT) ||
3930 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014 3931 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3932
23606cf5
RW		 3933 pm_runtime_put_sync(&pdev->dev);
3934
bc7f75fa
AK		 3935 return 0;
3936}
3937/**
3938 * e1000_set_mac - Change the Ethernet Address of the NIC
3939 * @netdev: network interface device structure
3940 * @p: pointer to an address structure
3941 *
3942 * Returns 0 on success, negative on failure
3943 **/
3944static int e1000_set_mac(struct net_device *netdev, void *p)
3945{
3946 struct e1000_adapter *adapter = netdev_priv(netdev);
3947 struct sockaddr *addr = p;
3948
3949 if (!is_valid_ether_addr(addr->sa_data))
3950 return -EADDRNOTAVAIL;
3951
3952 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3953 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3954
3955 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
3956
3957 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
3958 /* activate the work around */
3959 e1000e_set_laa_state_82571(&adapter->hw, 1);
3960
ad68076e
BA		 3961 /*
3962 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 3963 * between the time RAR[0] gets clobbered and the time it
3964 * gets fixed (in e1000_watchdog), the actual LAA is in one
3965 * of the RARs and no incoming packets directed to this port
3966 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 3967 * RAR[14]
3968 */
bc7f75fa
AK		 3969 e1000e_rar_set(&adapter->hw,
3970 adapter->hw.mac.addr,
3971 adapter->hw.mac.rar_entry_count - 1);
3972 }
3973
3974 return 0;
3975}
3976
a8f88ff5
JB		 3977/**
3978 * e1000e_update_phy_task - work thread to update phy
3979 * @work: pointer to our work struct
3980 *
3981 * this worker thread exists because we must acquire a
3982 * semaphore to read the phy, which we could msleep while
3983 * waiting for it, and we can't msleep in a timer.
3984 **/
3985static void e1000e_update_phy_task(struct work_struct *work)
3986{
3987 struct e1000_adapter *adapter = container_of(work,
3988 struct e1000_adapter, update_phy_task);
615b32af
JB		 3989
3990 if (test_bit(__E1000_DOWN, &adapter->state))
3991 return;
3992
a8f88ff5
JB		 3993 e1000_get_phy_info(&adapter->hw);
3994}
3995
ad68076e
BA		 3996/*
3997 * Need to wait a few seconds after link up to get diagnostic information from
3998 * the phy
3999 */
bc7f75fa
AK		 4000static void e1000_update_phy_info(unsigned long data)
4001{
4002 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4003
4004 if (test_bit(__E1000_DOWN, &adapter->state))
4005 return;
4006
a8f88ff5 4007 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4008}
4009
8c7bbb92
BA		 4010/**
4011 * e1000e_update_phy_stats - Update the PHY statistics counters
4012 * @adapter: board private structure
2b6b168d
BA		 4013 *
4014 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4015 **/
4016static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4017{
4018 struct e1000_hw *hw = &adapter->hw;
4019 s32 ret_val;
4020 u16 phy_data;
4021
4022 ret_val = hw->phy.ops.acquire(hw);
4023 if (ret_val)
4024 return;
4025
8c7bbb92
BA		 4026 /*
4027 * A page set is expensive so check if already on desired page.
4028 * If not, set to the page with the PHY status registers.
4029 */
2b6b168d 4030 hw->phy.addr = 1;
8c7bbb92
BA		 4031 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4032 &phy_data);
4033 if (ret_val)
4034 goto release;
2b6b168d
BA		 4035 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4036 ret_val = hw->phy.ops.set_page(hw,
4037 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4038 if (ret_val)
4039 goto release;
4040 }
4041
8c7bbb92 4042 /* Single Collision Count */
2b6b168d
BA		 4043 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4044 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4045 if (!ret_val)
4046 adapter->stats.scc += phy_data;
4047
4048 /* Excessive Collision Count */
2b6b168d
BA		 4049 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4050 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4051 if (!ret_val)
4052 adapter->stats.ecol += phy_data;
4053
4054 /* Multiple Collision Count */
2b6b168d
BA		 4055 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4056 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4057 if (!ret_val)
4058 adapter->stats.mcc += phy_data;
4059
4060 /* Late Collision Count */
2b6b168d
BA		 4061 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4062 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4063 if (!ret_val)
4064 adapter->stats.latecol += phy_data;
4065
4066 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4067 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4068 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4069 if (!ret_val)
4070 hw->mac.collision_delta = phy_data;
4071
4072 /* Defer Count */
2b6b168d
BA		 4073 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4074 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4075 if (!ret_val)
4076 adapter->stats.dc += phy_data;
4077
4078 /* Transmit with no CRS */
2b6b168d
BA		 4079 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4080 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4081 if (!ret_val)
4082 adapter->stats.tncrs += phy_data;
4083
4084release:
4085 hw->phy.ops.release(hw);
4086}
4087
bc7f75fa
AK		 4088/**
4089 * e1000e_update_stats - Update the board statistics counters
4090 * @adapter: board private structure
4091 **/
67fd4fcb 4092static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4093{
7274c20f 4094 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4095 struct e1000_hw *hw = &adapter->hw;
4096 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4097
4098 /*
4099 * Prevent stats update while adapter is being reset, or if the pci
4100 * connection is down.
4101 */
4102 if (adapter->link_speed == 0)
4103 return;
4104 if (pci_channel_offline(pdev))
4105 return;
4106
bc7f75fa
AK		 4107 adapter->stats.crcerrs += er32(CRCERRS);
4108 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4109 adapter->stats.gorc += er32(GORCL);
4110 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4111 adapter->stats.bprc += er32(BPRC);
4112 adapter->stats.mprc += er32(MPRC);
4113 adapter->stats.roc += er32(ROC);
4114
bc7f75fa 4115 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4116
4117 /* Half-duplex statistics */
4118 if (adapter->link_duplex == HALF_DUPLEX) {
4119 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4120 e1000e_update_phy_stats(adapter);
4121 } else {
4122 adapter->stats.scc += er32(SCC);
4123 adapter->stats.ecol += er32(ECOL);
4124 adapter->stats.mcc += er32(MCC);
4125 adapter->stats.latecol += er32(LATECOL);
4126 adapter->stats.dc += er32(DC);
4127
4128 hw->mac.collision_delta = er32(COLC);
4129
4130 if ((hw->mac.type != e1000_82574) &&
4131 (hw->mac.type != e1000_82583))
4132 adapter->stats.tncrs += er32(TNCRS);
4133 }
4134 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4135 }
8c7bbb92 4136
bc7f75fa
AK		 4137 adapter->stats.xonrxc += er32(XONRXC);
4138 adapter->stats.xontxc += er32(XONTXC);
4139 adapter->stats.xoffrxc += er32(XOFFRXC);
4140 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4141 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4142 adapter->stats.gotc += er32(GOTCL);
4143 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4144 adapter->stats.rnbc += er32(RNBC);
4145 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4146
4147 adapter->stats.mptc += er32(MPTC);
4148 adapter->stats.bptc += er32(BPTC);
4149
4150 /* used for adaptive IFS */
4151
4152 hw->mac.tx_packet_delta = er32(TPT);
4153 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4154
4155 adapter->stats.algnerrc += er32(ALGNERRC);
4156 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4157 adapter->stats.cexterr += er32(CEXTERR);
4158 adapter->stats.tsctc += er32(TSCTC);
4159 adapter->stats.tsctfc += er32(TSCTFC);
4160
bc7f75fa 4161 /* Fill out the OS statistics structure */
7274c20f
AK		 4162 netdev->stats.multicast = adapter->stats.mprc;
4163 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4164
4165 /* Rx Errors */
4166
ad68076e
BA		 4167 /*
4168 * RLEC on some newer hardware can be incorrect so build
4169 * our own version based on RUC and ROC
4170 */
7274c20f 4171 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4172 adapter->stats.crcerrs + adapter->stats.algnerrc +
4173 adapter->stats.ruc + adapter->stats.roc +
4174 adapter->stats.cexterr;
7274c20f 4175 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4176 adapter->stats.roc;
7274c20f
AK		 4177 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4178 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4179 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4180
4181 /* Tx Errors */
7274c20f 4182 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4183 adapter->stats.latecol;
7274c20f
AK		 4184 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4185 netdev->stats.tx_window_errors = adapter->stats.latecol;
4186 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4187
4188 /* Tx Dropped needs to be maintained elsewhere */
4189
bc7f75fa
AK		 4190 /* Management Stats */
4191 adapter->stats.mgptc += er32(MGTPTC);
4192 adapter->stats.mgprc += er32(MGTPRC);
4193 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4194}
4195
7c25769f
BA		 4196/**
4197 * e1000_phy_read_status - Update the PHY register status snapshot
4198 * @adapter: board private structure
4199 **/
4200static void e1000_phy_read_status(struct e1000_adapter *adapter)
4201{
4202 struct e1000_hw *hw = &adapter->hw;
4203 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4204
4205 if ((er32(STATUS) & E1000_STATUS_LU) &&
4206 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4207 int ret_val;
4208
7c25769f
BA		 4209 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4210 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4211 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4212 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4213 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4214 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4215 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4216 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4217 if (ret_val)
44defeb3 4218 e_warn("Error reading PHY register\n");
7c25769f
BA		 4219 } else {
4220 /*
4221 * Do not read PHY registers if link is not up
4222 * Set values to typical power-on defaults
4223 */
4224 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4225 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4226 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4227 BMSR_ERCAP);
4228 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4229 ADVERTISE_ALL | ADVERTISE_CSMA);
4230 phy->lpa = 0;
4231 phy->expansion = EXPANSION_ENABLENPAGE;
4232 phy->ctrl1000 = ADVERTISE_1000FULL;
4233 phy->stat1000 = 0;
4234 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4235 }
7c25769f
BA		 4236}
4237
bc7f75fa
AK		 4238static void e1000_print_link_info(struct e1000_adapter *adapter)
4239{
bc7f75fa
AK		 4240 struct e1000_hw *hw = &adapter->hw;
4241 u32 ctrl = er32(CTRL);
4242
8f12fe86 4243 /* Link status message must follow this format for user tools */
ef456f85
JK		 4244 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4245 adapter->netdev->name,
4246 adapter->link_speed,
4247 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4248 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4249 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4250 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4251}
4252
0c6bdb30 4253static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4254{
4255 struct e1000_hw *hw = &adapter->hw;
4256 bool link_active = 0;
4257 s32 ret_val = 0;
4258
4259 /*
4260 * get_link_status is set on LSC (link status) interrupt or
4261 * Rx sequence error interrupt. get_link_status will stay
4262 * false until the check_for_link establishes link
4263 * for copper adapters ONLY
4264 */
4265 switch (hw->phy.media_type) {
4266 case e1000_media_type_copper:
4267 if (hw->mac.get_link_status) {
4268 ret_val = hw->mac.ops.check_for_link(hw);
4269 link_active = !hw->mac.get_link_status;
4270 } else {
4271 link_active = 1;
4272 }
4273 break;
4274 case e1000_media_type_fiber:
4275 ret_val = hw->mac.ops.check_for_link(hw);
4276 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4277 break;
4278 case e1000_media_type_internal_serdes:
4279 ret_val = hw->mac.ops.check_for_link(hw);
4280 link_active = adapter->hw.mac.serdes_has_link;
4281 break;
4282 default:
4283 case e1000_media_type_unknown:
4284 break;
4285 }
4286
4287 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4288 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4289 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4290 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4291 }
4292
4293 return link_active;
4294}
4295
4296static void e1000e_enable_receives(struct e1000_adapter *adapter)
4297{
4298 /* make sure the receive unit is started */
4299 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4300 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4301 struct e1000_hw *hw = &adapter->hw;
4302 u32 rctl = er32(RCTL);
4303 ew32(RCTL, rctl | E1000_RCTL_EN);
4304 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4305 }
4306}
4307
ff10e13c
CW		 4308static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4309{
4310 struct e1000_hw *hw = &adapter->hw;
4311
4312 /*
4313 * With 82574 controllers, PHY needs to be checked periodically
4314 * for hung state and reset, if two calls return true
4315 */
4316 if (e1000_check_phy_82574(hw))
4317 adapter->phy_hang_count++;
4318 else
4319 adapter->phy_hang_count = 0;
4320
4321 if (adapter->phy_hang_count > 1) {
4322 adapter->phy_hang_count = 0;
4323 schedule_work(&adapter->reset_task);
4324 }
4325}
4326
bc7f75fa
AK		 4327/**
4328 * e1000_watchdog - Timer Call-back
4329 * @data: pointer to adapter cast into an unsigned long
4330 **/
4331static void e1000_watchdog(unsigned long data)
4332{
4333 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4334
4335 /* Do the rest outside of interrupt context */
4336 schedule_work(&adapter->watchdog_task);
4337
4338 /* TODO: make this use queue_delayed_work() */
4339}
4340
4341static void e1000_watchdog_task(struct work_struct *work)
4342{
4343 struct e1000_adapter *adapter = container_of(work,
4344 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4345 struct net_device *netdev = adapter->netdev;
4346 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4347 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4348 struct e1000_ring *tx_ring = adapter->tx_ring;
4349 struct e1000_hw *hw = &adapter->hw;
4350 u32 link, tctl;
bc7f75fa 4351
615b32af
JB		 4352 if (test_bit(__E1000_DOWN, &adapter->state))
4353 return;
4354
b405e8df 4355 link = e1000e_has_link(adapter);
318a94d6 4356 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4357 /* Cancel scheduled suspend requests. */
4358 pm_runtime_resume(netdev->dev.parent);
4359
318a94d6 4360 e1000e_enable_receives(adapter);
bc7f75fa 4361 goto link_up;
bc7f75fa
AK		 4362 }
4363
4364 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4365 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4366 e1000_update_mng_vlan(adapter);
4367
bc7f75fa
AK		 4368 if (link) {
4369 if (!netif_carrier_ok(netdev)) {
4370 bool txb2b = 1;
23606cf5
RW		 4371
4372 /* Cancel scheduled suspend requests. */
4373 pm_runtime_resume(netdev->dev.parent);
4374
318a94d6 4375 /* update snapshot of PHY registers on LSC */
7c25769f 4376 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4377 mac->ops.get_link_up_info(&adapter->hw,
4378 &adapter->link_speed,
4379 &adapter->link_duplex);
4380 e1000_print_link_info(adapter);
f4187b56
BA		 4381 /*
4382 * On supported PHYs, check for duplex mismatch only
4383 * if link has autonegotiated at 10/100 half
4384 */
4385 if ((hw->phy.type == e1000_phy_igp_3 ||
4386 hw->phy.type == e1000_phy_bm) &&
4387 (hw->mac.autoneg == true) &&
4388 (adapter->link_speed == SPEED_10 ||
4389 adapter->link_speed == SPEED_100) &&
4390 (adapter->link_duplex == HALF_DUPLEX)) {
4391 u16 autoneg_exp;
4392
4393 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4394
4395 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4396 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4397 }
4398
f49c57e1 4399 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4400 adapter->tx_timeout_factor = 1;
4401 switch (adapter->link_speed) {
4402 case SPEED_10:
4403 txb2b = 0;
10f1b492 4404 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4405 break;
4406 case SPEED_100:
4407 txb2b = 0;
4c86e0b9 4408 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4409 break;
4410 }
4411
ad68076e
BA		 4412 /*
4413 * workaround: re-program speed mode bit after
4414 * link-up event
4415 */
bc7f75fa
AK		 4416 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4417 !txb2b) {
4418 u32 tarc0;
e9ec2c0f 4419 tarc0 = er32(TARC(0));
bc7f75fa 4420 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4421 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4422 }
4423
ad68076e
BA		 4424 /*
4425 * disable TSO for pcie and 10/100 speeds, to avoid
4426 * some hardware issues
4427 */
bc7f75fa
AK		 4428 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4429 switch (adapter->link_speed) {
4430 case SPEED_10:
4431 case SPEED_100:
44defeb3 4432 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4433 netdev->features &= ~NETIF_F_TSO;
4434 netdev->features &= ~NETIF_F_TSO6;
4435 break;
4436 case SPEED_1000:
4437 netdev->features |= NETIF_F_TSO;
4438 netdev->features |= NETIF_F_TSO6;
4439 break;
4440 default:
4441 /* oops */
4442 break;
4443 }
4444 }
4445
ad68076e
BA		 4446 /*
4447 * enable transmits in the hardware, need to do this
4448 * after setting TARC(0)
4449 */
bc7f75fa
AK		 4450 tctl = er32(TCTL);
4451 tctl |= E1000_TCTL_EN;
4452 ew32(TCTL, tctl);
4453
75eb0fad
BA		 4454 /*
4455 * Perform any post-link-up configuration before
4456 * reporting link up.
4457 */
4458 if (phy->ops.cfg_on_link_up)
4459 phy->ops.cfg_on_link_up(hw);
4460
bc7f75fa 4461 netif_carrier_on(netdev);
bc7f75fa
AK		 4462
4463 if (!test_bit(__E1000_DOWN, &adapter->state))
4464 mod_timer(&adapter->phy_info_timer,
4465 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4466 }
4467 } else {
4468 if (netif_carrier_ok(netdev)) {
4469 adapter->link_speed = 0;
4470 adapter->link_duplex = 0;
8f12fe86
BA		 4471 /* Link status message must follow this format */
4472 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4473 adapter->netdev->name);
bc7f75fa 4474 netif_carrier_off(netdev);
bc7f75fa
AK		 4475 if (!test_bit(__E1000_DOWN, &adapter->state))
4476 mod_timer(&adapter->phy_info_timer,
4477 round_jiffies(jiffies + 2 * HZ));
4478
4479 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4480 schedule_work(&adapter->reset_task);
23606cf5
RW		 4481 else
4482 pm_schedule_suspend(netdev->dev.parent,
4483 LINK_TIMEOUT);
bc7f75fa
AK		 4484 }
4485 }
4486
4487link_up:
67fd4fcb 4488 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4489 e1000e_update_stats(adapter);
4490
4491 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4492 adapter->tpt_old = adapter->stats.tpt;
4493 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4494 adapter->colc_old = adapter->stats.colc;
4495
7c25769f
BA		 4496 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4497 adapter->gorc_old = adapter->stats.gorc;
4498 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4499 adapter->gotc_old = adapter->stats.gotc;
2084b114 4500 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4501
4502 e1000e_update_adaptive(&adapter->hw);
4503
90da0669
BA		 4504 if (!netif_carrier_ok(netdev) &&
4505 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4506 /*
4507 * We've lost link, so the controller stops DMA,
4508 * but we've got queued Tx work that's never going
4509 * to get done, so reset controller to flush Tx.
4510 * (Do the reset outside of interrupt context).
4511 */
90da0669
BA		 4512 schedule_work(&adapter->reset_task);
4513 /* return immediately since reset is imminent */
4514 return;
bc7f75fa
AK		 4515 }
4516
eab2abf5
JB		 4517 /* Simple mode for Interrupt Throttle Rate (ITR) */
4518 if (adapter->itr_setting == 4) {
4519 /*
4520 * Symmetric Tx/Rx gets a reduced ITR=2000;
4521 * Total asymmetrical Tx or Rx gets ITR=8000;
4522 * everyone else is between 2000-8000.
4523 */
4524 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4525 u32 dif = (adapter->gotc > adapter->gorc ?
4526 adapter->gotc - adapter->gorc :
4527 adapter->gorc - adapter->gotc) / 10000;
4528 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4529
4530 ew32(ITR, 1000000000 / (itr * 256));
4531 }
4532
ad68076e 4533 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4534 if (adapter->msix_entries)
4535 ew32(ICS, adapter->rx_ring->ims_val);
4536 else
4537 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4538
713b3c9e
JB		 4539 /* flush pending descriptors to memory before detecting Tx hang */
4540 e1000e_flush_descriptors(adapter);
4541
bc7f75fa
AK		 4542 /* Force detection of hung controller every watchdog period */
4543 adapter->detect_tx_hung = 1;
4544
ad68076e
BA		 4545 /*
4546 * With 82571 controllers, LAA may be overwritten due to controller
4547 * reset from the other port. Set the appropriate LAA in RAR[0]
4548 */
bc7f75fa
AK		 4549 if (e1000e_get_laa_state_82571(hw))
4550 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4551
ff10e13c
CW		 4552 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4553 e1000e_check_82574_phy_workaround(adapter);
4554
bc7f75fa
AK		 4555 /* Reset the timer */
4556 if (!test_bit(__E1000_DOWN, &adapter->state))
4557 mod_timer(&adapter->watchdog_timer,
4558 round_jiffies(jiffies + 2 * HZ));
4559}
4560
4561#define E1000_TX_FLAGS_CSUM 0x00000001
4562#define E1000_TX_FLAGS_VLAN 0x00000002
4563#define E1000_TX_FLAGS_TSO 0x00000004
4564#define E1000_TX_FLAGS_IPV4 0x00000008
4565#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4566#define E1000_TX_FLAGS_VLAN_SHIFT 16
4567
4568static int e1000_tso(struct e1000_adapter *adapter,
4569 struct sk_buff *skb)
4570{
4571 struct e1000_ring *tx_ring = adapter->tx_ring;
4572 struct e1000_context_desc *context_desc;
4573 struct e1000_buffer *buffer_info;
4574 unsigned int i;
4575 u32 cmd_length = 0;
4576 u16 ipcse = 0, tucse, mss;
4577 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4578
3d5e33c9
BA		 4579 if (!skb_is_gso(skb))
4580 return 0;
bc7f75fa 4581
3d5e33c9 4582 if (skb_header_cloned(skb)) {
90da0669
BA		 4583 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4584
3d5e33c9
BA		 4585 if (err)
4586 return err;
bc7f75fa
AK		 4587 }
4588
3d5e33c9
BA		 4589 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4590 mss = skb_shinfo(skb)->gso_size;
4591 if (skb->protocol == htons(ETH_P_IP)) {
4592 struct iphdr *iph = ip_hdr(skb);
4593 iph->tot_len = 0;
4594 iph->check = 0;
4595 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4596 0, IPPROTO_TCP, 0);
4597 cmd_length = E1000_TXD_CMD_IP;
4598 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4599 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4600 ipv6_hdr(skb)->payload_len = 0;
4601 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4602 &ipv6_hdr(skb)->daddr,
4603 0, IPPROTO_TCP, 0);
4604 ipcse = 0;
4605 }
4606 ipcss = skb_network_offset(skb);
4607 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4608 tucss = skb_transport_offset(skb);
4609 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4610 tucse = 0;
4611
4612 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4613 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4614
4615 i = tx_ring->next_to_use;
4616 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4617 buffer_info = &tx_ring->buffer_info[i];
4618
4619 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4620 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4621 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4622 context_desc->upper_setup.tcp_fields.tucss = tucss;
4623 context_desc->upper_setup.tcp_fields.tucso = tucso;
4624 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4625 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4626 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4627 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4628
4629 buffer_info->time_stamp = jiffies;
4630 buffer_info->next_to_watch = i;
4631
4632 i++;
4633 if (i == tx_ring->count)
4634 i = 0;
4635 tx_ring->next_to_use = i;
4636
4637 return 1;
bc7f75fa
AK		 4638}
4639
4640static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
4641{
4642 struct e1000_ring *tx_ring = adapter->tx_ring;
4643 struct e1000_context_desc *context_desc;
4644 struct e1000_buffer *buffer_info;
4645 unsigned int i;
4646 u8 css;
af807c82 4647 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4648 __be16 protocol;
bc7f75fa 4649
af807c82
DG		 4650 if (skb->ip_summed != CHECKSUM_PARTIAL)
4651 return 0;
bc7f75fa 4652
5f66f208
AJ		 4653 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4654 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4655 else
4656 protocol = skb->protocol;
4657
3f518390 4658 switch (protocol) {
09640e63 4659 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4660 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4661 cmd_len |= E1000_TXD_CMD_TCP;
4662 break;
09640e63 4663 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4664 /* XXX not handling all IPV6 headers */
4665 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4666 cmd_len |= E1000_TXD_CMD_TCP;
4667 break;
4668 default:
4669 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4670 e_warn("checksum_partial proto=%x!\n",
4671 be16_to_cpu(protocol));
af807c82 4672 break;
bc7f75fa
AK		 4673 }
4674
0d0b1672 4675 css = skb_checksum_start_offset(skb);
af807c82
DG		 4676
4677 i = tx_ring->next_to_use;
4678 buffer_info = &tx_ring->buffer_info[i];
4679 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4680
4681 context_desc->lower_setup.ip_config = 0;
4682 context_desc->upper_setup.tcp_fields.tucss = css;
4683 context_desc->upper_setup.tcp_fields.tucso =
4684 css + skb->csum_offset;
4685 context_desc->upper_setup.tcp_fields.tucse = 0;
4686 context_desc->tcp_seg_setup.data = 0;
4687 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4688
4689 buffer_info->time_stamp = jiffies;
4690 buffer_info->next_to_watch = i;
4691
4692 i++;
4693 if (i == tx_ring->count)
4694 i = 0;
4695 tx_ring->next_to_use = i;
4696
4697 return 1;
bc7f75fa
AK		 4698}
4699
4700#define E1000_MAX_PER_TXD 8192
4701#define E1000_MAX_TXD_PWR 12
4702
4703static int e1000_tx_map(struct e1000_adapter *adapter,
4704 struct sk_buff *skb, unsigned int first,
4705 unsigned int max_per_txd, unsigned int nr_frags,
4706 unsigned int mss)
4707{
4708 struct e1000_ring *tx_ring = adapter->tx_ring;
03b1320d 4709 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4710 struct e1000_buffer *buffer_info;
8ddc951c 4711 unsigned int len = skb_headlen(skb);
03b1320d 4712 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4713 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4714
4715 i = tx_ring->next_to_use;
4716
4717 while (len) {
1b7719c4 4718 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4719 size = min(len, max_per_txd);
4720
bc7f75fa 4721 buffer_info->length = size;
bc7f75fa 4722 buffer_info->time_stamp = jiffies;
bc7f75fa 4723 buffer_info->next_to_watch = i;
0be3f55f
NN		 4724 buffer_info->dma = dma_map_single(&pdev->dev,
4725 skb->data + offset,
af667a29 4726 size, DMA_TO_DEVICE);
03b1320d 4727 buffer_info->mapped_as_page = false;
0be3f55f 4728 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4729 goto dma_error;
bc7f75fa
AK		 4730
4731 len -= size;
4732 offset += size;
03b1320d 4733 count++;
1b7719c4
AD		 4734
4735 if (len) {
4736 i++;
4737 if (i == tx_ring->count)
4738 i = 0;
4739 }
bc7f75fa
AK		 4740 }
4741
4742 for (f = 0; f < nr_frags; f++) {
9e903e08 4743 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4744
4745 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4746 len = skb_frag_size(frag);
877749bf 4747 offset = 0;
bc7f75fa
AK		 4748
4749 while (len) {
1b7719c4
AD		 4750 i++;
4751 if (i == tx_ring->count)
4752 i = 0;
4753
bc7f75fa
AK		 4754 buffer_info = &tx_ring->buffer_info[i];
4755 size = min(len, max_per_txd);
bc7f75fa
AK		 4756
4757 buffer_info->length = size;
4758 buffer_info->time_stamp = jiffies;
bc7f75fa 4759 buffer_info->next_to_watch = i;
877749bf
IC		 4760 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4761 offset, size, DMA_TO_DEVICE);
03b1320d 4762 buffer_info->mapped_as_page = true;
0be3f55f 4763 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4764 goto dma_error;
bc7f75fa
AK		 4765
4766 len -= size;
4767 offset += size;
4768 count++;
bc7f75fa
AK		 4769 }
4770 }
4771
af667a29 4772 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4773 /* multiply data chunks by size of headers */
4774 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4775
bc7f75fa 4776 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4777 tx_ring->buffer_info[i].segs = segs;
4778 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4779 tx_ring->buffer_info[first].next_to_watch = i;
4780
4781 return count;
03b1320d
AD		 4782
4783dma_error:
af667a29 4784 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4785 buffer_info->dma = 0;
c1fa347f 4786 if (count)
03b1320d 4787 count--;
c1fa347f
RK		 4788
4789 while (count--) {
af667a29 4790 if (i == 0)
03b1320d 4791 i += tx_ring->count;
c1fa347f 4792 i--;
03b1320d 4793 buffer_info = &tx_ring->buffer_info[i];
1d51c418 4794 e1000_put_txbuf(adapter, buffer_info);
03b1320d
AD		 4795 }
4796
4797 return 0;
bc7f75fa
AK		 4798}
4799
4800static void e1000_tx_queue(struct e1000_adapter *adapter,
4801 int tx_flags, int count)
4802{
4803 struct e1000_ring *tx_ring = adapter->tx_ring;
4804 struct e1000_tx_desc *tx_desc = NULL;
4805 struct e1000_buffer *buffer_info;
4806 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4807 unsigned int i;
4808
4809 if (tx_flags & E1000_TX_FLAGS_TSO) {
4810 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4811 E1000_TXD_CMD_TSE;
4812 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4813
4814 if (tx_flags & E1000_TX_FLAGS_IPV4)
4815 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4816 }
4817
4818 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4819 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4820 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4821 }
4822
4823 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4824 txd_lower |= E1000_TXD_CMD_VLE;
4825 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4826 }
4827
4828 i = tx_ring->next_to_use;
4829
36b973df 4830 do {
bc7f75fa
AK		 4831 buffer_info = &tx_ring->buffer_info[i];
4832 tx_desc = E1000_TX_DESC(*tx_ring, i);
4833 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4834 tx_desc->lower.data =
4835 cpu_to_le32(txd_lower | buffer_info->length);
4836 tx_desc->upper.data = cpu_to_le32(txd_upper);
4837
4838 i++;
4839 if (i == tx_ring->count)
4840 i = 0;
36b973df 4841 } while (--count > 0);
bc7f75fa
AK		 4842
4843 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4844
ad68076e
BA		 4845 /*
4846 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4847 * know there are new descriptors to fetch. (Only
4848 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4849 * such as IA-64).
4850 */
bc7f75fa
AK		 4851 wmb();
4852
4853 tx_ring->next_to_use = i;
c6e7f51e
BA		 4854
4855 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
4856 e1000e_update_tdt_wa(adapter, i);
4857 else
4858 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4859
ad68076e
BA		 4860 /*
4861 * we need this if more than one processor can write to our tail
4862 * at a time, it synchronizes IO on IA64/Altix systems
4863 */
bc7f75fa
AK		 4864 mmiowb();
4865}
4866
4867#define MINIMUM_DHCP_PACKET_SIZE 282
4868static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4869 struct sk_buff *skb)
4870{
4871 struct e1000_hw *hw = &adapter->hw;
4872 u16 length, offset;
4873
4874 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4875 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4876 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4877 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4878 return 0;
4879 }
4880
4881 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4882 return 0;
4883
4884 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4885 return 0;
4886
4887 {
4888 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4889 struct udphdr *udp;
4890
4891 if (ip->protocol != IPPROTO_UDP)
4892 return 0;
4893
4894 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4895 if (ntohs(udp->dest) != 67)
4896 return 0;
4897
4898 offset = (u8 *)udp + 8 - skb->data;
4899 length = skb->len - offset;
4900 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4901 }
4902
4903 return 0;
4904}
4905
4906static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
4907{
4908 struct e1000_adapter *adapter = netdev_priv(netdev);
4909
4910 netif_stop_queue(netdev);
ad68076e
BA		 4911 /*
4912 * Herbert's original patch had:
bc7f75fa 4913 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4914 * but since that doesn't exist yet, just open code it.
4915 */
bc7f75fa
AK		 4916 smp_mb();
4917
ad68076e
BA		 4918 /*
4919 * We need to check again in a case another CPU has just
4920 * made room available.
4921 */
bc7f75fa
AK		 4922 if (e1000_desc_unused(adapter->tx_ring) < size)
4923 return -EBUSY;
4924
4925 /* A reprieve! */
4926 netif_start_queue(netdev);
4927 ++adapter->restart_queue;
4928 return 0;
4929}
4930
4931static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
4932{
4933 struct e1000_adapter *adapter = netdev_priv(netdev);
4934
4935 if (e1000_desc_unused(adapter->tx_ring) >= size)
4936 return 0;
4937 return __e1000_maybe_stop_tx(netdev, size);
4938}
4939
4940#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3b29a56d
SH		 4941static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4942 struct net_device *netdev)
bc7f75fa
AK		 4943{
4944 struct e1000_adapter *adapter = netdev_priv(netdev);
4945 struct e1000_ring *tx_ring = adapter->tx_ring;
4946 unsigned int first;
4947 unsigned int max_per_txd = E1000_MAX_PER_TXD;
4948 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
4949 unsigned int tx_flags = 0;
e743d313 4950 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4951 unsigned int nr_frags;
4952 unsigned int mss;
bc7f75fa
AK		 4953 int count = 0;
4954 int tso;
4955 unsigned int f;
bc7f75fa
AK		 4956
4957 if (test_bit(__E1000_DOWN, &adapter->state)) {
4958 dev_kfree_skb_any(skb);
4959 return NETDEV_TX_OK;
4960 }
4961
4962 if (skb->len <= 0) {
4963 dev_kfree_skb_any(skb);
4964 return NETDEV_TX_OK;
4965 }
4966
4967 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 4968 /*
4969 * The controller does a simple calculation to
bc7f75fa
AK		 4970 * make sure there is enough room in the FIFO before
4971 * initiating the DMA for each buffer. The calc is:
4972 * 4 = ceil(buffer len/mss). To make sure we don't
4973 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 4974 * drops.
4975 */
bc7f75fa
AK		 4976 if (mss) {
4977 u8 hdr_len;
4978 max_per_txd = min(mss << 2, max_per_txd);
4979 max_txd_pwr = fls(max_per_txd) - 1;
4980
ad68076e
BA		 4981 /*
4982 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
4983 * points to just header, pull a few bytes of payload from
4984 * frags into skb->data
4985 */
bc7f75fa 4986 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 4987 /*
4988 * we do this workaround for ES2LAN, but it is un-necessary,
4989 * avoiding it could save a lot of cycles
4990 */
4e6c709c 4991 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 4992 unsigned int pull_size;
4993
4994 pull_size = min((unsigned int)4, skb->data_len);
4995 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 4996 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 4997 dev_kfree_skb_any(skb);
4998 return NETDEV_TX_OK;
4999 }
e743d313 5000 len = skb_headlen(skb);
bc7f75fa
AK		 5001 }
5002 }
5003
5004 /* reserve a descriptor for the offload context */
5005 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5006 count++;
5007 count++;
5008
5009 count += TXD_USE_COUNT(len, max_txd_pwr);
5010
5011 nr_frags = skb_shinfo(skb)->nr_frags;
5012 for (f = 0; f < nr_frags; f++)
9e903e08 5013 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5014 max_txd_pwr);
5015
5016 if (adapter->hw.mac.tx_pkt_filtering)
5017 e1000_transfer_dhcp_info(adapter, skb);
5018
ad68076e
BA		 5019 /*
5020 * need: count + 2 desc gap to keep tail from touching
5021 * head, otherwise try next time
5022 */
92af3e95 5023 if (e1000_maybe_stop_tx(netdev, count + 2))
bc7f75fa 5024 return NETDEV_TX_BUSY;
bc7f75fa 5025
eab6d18d 5026 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5027 tx_flags |= E1000_TX_FLAGS_VLAN;
5028 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5029 }
5030
5031 first = tx_ring->next_to_use;
5032
5033 tso = e1000_tso(adapter, skb);
5034 if (tso < 0) {
5035 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5036 return NETDEV_TX_OK;
5037 }
5038
5039 if (tso)
5040 tx_flags |= E1000_TX_FLAGS_TSO;
5041 else if (e1000_tx_csum(adapter, skb))
5042 tx_flags |= E1000_TX_FLAGS_CSUM;
5043
ad68076e
BA		 5044 /*
5045 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5046 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5047 * no longer assume, we must.
5048 */
bc7f75fa
AK		 5049 if (skb->protocol == htons(ETH_P_IP))
5050 tx_flags |= E1000_TX_FLAGS_IPV4;
5051
25985edc 5052 /* if count is 0 then mapping error has occurred */
bc7f75fa 5053 count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5054 if (count) {
3f0cfa3b 5055 netdev_sent_queue(netdev, skb->len);
1b7719c4 5056 e1000_tx_queue(adapter, tx_flags, count);
1b7719c4
AD		 5057 /* Make sure there is space in the ring for the next send. */
5058 e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2);
5059
5060 } else {
bc7f75fa 5061 dev_kfree_skb_any(skb);
1b7719c4
AD		 5062 tx_ring->buffer_info[first].time_stamp = 0;
5063 tx_ring->next_to_use = first;
bc7f75fa
AK		 5064 }
5065
bc7f75fa
AK		 5066 return NETDEV_TX_OK;
5067}
5068
5069/**
5070 * e1000_tx_timeout - Respond to a Tx Hang
5071 * @netdev: network interface device structure
5072 **/
5073static void e1000_tx_timeout(struct net_device *netdev)
5074{
5075 struct e1000_adapter *adapter = netdev_priv(netdev);
5076
5077 /* Do the reset outside of interrupt context */
5078 adapter->tx_timeout_count++;
5079 schedule_work(&adapter->reset_task);
5080}
5081
5082static void e1000_reset_task(struct work_struct *work)
5083{
5084 struct e1000_adapter *adapter;
5085 adapter = container_of(work, struct e1000_adapter, reset_task);
5086
615b32af
JB		 5087 /* don't run the task if already down */
5088 if (test_bit(__E1000_DOWN, &adapter->state))
5089 return;
5090
affa9dfb
CW		 5091 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5092 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5093 e1000e_dump(adapter);
5094 e_err("Reset adapter\n");
5095 }
bc7f75fa
AK		 5096 e1000e_reinit_locked(adapter);
5097}
5098
5099/**
67fd4fcb 5100 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5101 * @netdev: network interface device structure
67fd4fcb 5102 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5103 *
5104 * Returns the address of the device statistics structure.
bc7f75fa 5105 **/
67fd4fcb
JK		 5106struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5107 struct rtnl_link_stats64 *stats)
bc7f75fa 5108{
67fd4fcb
JK		 5109 struct e1000_adapter *adapter = netdev_priv(netdev);
5110
5111 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5112 spin_lock(&adapter->stats64_lock);
5113 e1000e_update_stats(adapter);
5114 /* Fill out the OS statistics structure */
5115 stats->rx_bytes = adapter->stats.gorc;
5116 stats->rx_packets = adapter->stats.gprc;
5117 stats->tx_bytes = adapter->stats.gotc;
5118 stats->tx_packets = adapter->stats.gptc;
5119 stats->multicast = adapter->stats.mprc;
5120 stats->collisions = adapter->stats.colc;
5121
5122 /* Rx Errors */
5123
5124 /*
5125 * RLEC on some newer hardware can be incorrect so build
5126 * our own version based on RUC and ROC
5127 */
5128 stats->rx_errors = adapter->stats.rxerrc +
5129 adapter->stats.crcerrs + adapter->stats.algnerrc +
5130 adapter->stats.ruc + adapter->stats.roc +
5131 adapter->stats.cexterr;
5132 stats->rx_length_errors = adapter->stats.ruc +
5133 adapter->stats.roc;
5134 stats->rx_crc_errors = adapter->stats.crcerrs;
5135 stats->rx_frame_errors = adapter->stats.algnerrc;
5136 stats->rx_missed_errors = adapter->stats.mpc;
5137
5138 /* Tx Errors */
5139 stats->tx_errors = adapter->stats.ecol +
5140 adapter->stats.latecol;
5141 stats->tx_aborted_errors = adapter->stats.ecol;
5142 stats->tx_window_errors = adapter->stats.latecol;
5143 stats->tx_carrier_errors = adapter->stats.tncrs;
5144
5145 /* Tx Dropped needs to be maintained elsewhere */
5146
5147 spin_unlock(&adapter->stats64_lock);
5148 return stats;
bc7f75fa
AK		 5149}
5150
5151/**
5152 * e1000_change_mtu - Change the Maximum Transfer Unit
5153 * @netdev: network interface device structure
5154 * @new_mtu: new value for maximum frame size
5155 *
5156 * Returns 0 on success, negative on failure
5157 **/
5158static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5159{
5160 struct e1000_adapter *adapter = netdev_priv(netdev);
5161 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5162
2adc55c9
BA		 5163 /* Jumbo frame support */
5164 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5165 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5166 e_err("Jumbo Frames not supported.\n");
bc7f75fa
AK		 5167 return -EINVAL;
5168 }
5169
2adc55c9
BA		 5170 /* Supported frame sizes */
5171 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5172 (max_frame > adapter->max_hw_frame_size)) {
5173 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5174 return -EINVAL;
5175 }
5176
a1ce6473
BA		 5177 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5178 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5179 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5180 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5181 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5182 return -EINVAL;
5183 }
5184
6f461f6c
BA		 5185 /* 82573 Errata 17 */
5186 if (((adapter->hw.mac.type == e1000_82573) ||
5187 (adapter->hw.mac.type == e1000_82574)) &&
5188 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5189 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5190 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5191 }
5192
bc7f75fa 5193 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5194 usleep_range(1000, 2000);
610c9928 5195 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5196 adapter->max_frame_size = max_frame;
610c9928
BA		 5197 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5198 netdev->mtu = new_mtu;
bc7f75fa
AK		 5199 if (netif_running(netdev))
5200 e1000e_down(adapter);
5201
ad68076e
BA		 5202 /*
5203 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5204 * means we reserve 2 more, this pushes us to allocate from the next
5205 * larger slab size.
ad68076e 5206 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5207 * However with the new *_jumbo_rx* routines, jumbo receives will use
5208 * fragmented skbs
ad68076e 5209 */
bc7f75fa 5210
9926146b 5211 if (max_frame <= 2048)
bc7f75fa
AK		 5212 adapter->rx_buffer_len = 2048;
5213 else
5214 adapter->rx_buffer_len = 4096;
5215
5216 /* adjust allocation if LPE protects us, and we aren't using SBP */
5217 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5218 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5219 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5220 + ETH_FCS_LEN;
bc7f75fa 5221
bc7f75fa
AK		 5222 if (netif_running(netdev))
5223 e1000e_up(adapter);
5224 else
5225 e1000e_reset(adapter);
5226
5227 clear_bit(__E1000_RESETTING, &adapter->state);
5228
5229 return 0;
5230}
5231
5232static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5233 int cmd)
5234{
5235 struct e1000_adapter *adapter = netdev_priv(netdev);
5236 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5237
318a94d6 5238 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5239 return -EOPNOTSUPP;
5240
5241 switch (cmd) {
5242 case SIOCGMIIPHY:
5243 data->phy_id = adapter->hw.phy.addr;
5244 break;
5245 case SIOCGMIIREG:
b16a002e
BA		 5246 e1000_phy_read_status(adapter);
5247
7c25769f
BA		 5248 switch (data->reg_num & 0x1F) {
5249 case MII_BMCR:
5250 data->val_out = adapter->phy_regs.bmcr;
5251 break;
5252 case MII_BMSR:
5253 data->val_out = adapter->phy_regs.bmsr;
5254 break;
5255 case MII_PHYSID1:
5256 data->val_out = (adapter->hw.phy.id >> 16);
5257 break;
5258 case MII_PHYSID2:
5259 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5260 break;
5261 case MII_ADVERTISE:
5262 data->val_out = adapter->phy_regs.advertise;
5263 break;
5264 case MII_LPA:
5265 data->val_out = adapter->phy_regs.lpa;
5266 break;
5267 case MII_EXPANSION:
5268 data->val_out = adapter->phy_regs.expansion;
5269 break;
5270 case MII_CTRL1000:
5271 data->val_out = adapter->phy_regs.ctrl1000;
5272 break;
5273 case MII_STAT1000:
5274 data->val_out = adapter->phy_regs.stat1000;
5275 break;
5276 case MII_ESTATUS:
5277 data->val_out = adapter->phy_regs.estatus;
5278 break;
5279 default:
bc7f75fa
AK		 5280 return -EIO;
5281 }
bc7f75fa
AK		 5282 break;
5283 case SIOCSMIIREG:
5284 default:
5285 return -EOPNOTSUPP;
5286 }
5287 return 0;
5288}
5289
5290static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5291{
5292 switch (cmd) {
5293 case SIOCGMIIPHY:
5294 case SIOCGMIIREG:
5295 case SIOCSMIIREG:
5296 return e1000_mii_ioctl(netdev, ifr, cmd);
5297 default:
5298 return -EOPNOTSUPP;
5299 }
5300}
5301
a4f58f54
BA		 5302static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5303{
5304 struct e1000_hw *hw = &adapter->hw;
5305 u32 i, mac_reg;
2b6b168d 5306 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5307 int retval = 0;
5308
5309 /* copy MAC RARs to PHY RARs */
d3738bb8 5310 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5311
2b6b168d
BA		 5312 retval = hw->phy.ops.acquire(hw);
5313 if (retval) {
5314 e_err("Could not acquire PHY\n");
5315 return retval;
5316 }
5317
5318 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5319 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5320 if (retval)
5321 goto out;
5322
5323 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5324 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5325 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5326 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5327 (u16)(mac_reg & 0xFFFF));
5328 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5329 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5330 }
5331
5332 /* configure PHY Rx Control register */
2b6b168d 5333 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5334 mac_reg = er32(RCTL);
5335 if (mac_reg & E1000_RCTL_UPE)
5336 phy_reg |= BM_RCTL_UPE;
5337 if (mac_reg & E1000_RCTL_MPE)
5338 phy_reg |= BM_RCTL_MPE;
5339 phy_reg &= ~(BM_RCTL_MO_MASK);
5340 if (mac_reg & E1000_RCTL_MO_3)
5341 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5342 << BM_RCTL_MO_SHIFT);
5343 if (mac_reg & E1000_RCTL_BAM)
5344 phy_reg |= BM_RCTL_BAM;
5345 if (mac_reg & E1000_RCTL_PMCF)
5346 phy_reg |= BM_RCTL_PMCF;
5347 mac_reg = er32(CTRL);
5348 if (mac_reg & E1000_CTRL_RFCE)
5349 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5350 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5351
5352 /* enable PHY wakeup in MAC register */
5353 ew32(WUFC, wufc);
5354 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5355
5356 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5357 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5358 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5359
5360 /* activate PHY wakeup */
2b6b168d
BA		 5361 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5362 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5363 if (retval)
5364 e_err("Could not set PHY Host Wakeup bit\n");
5365out:
94d8186a 5366 hw->phy.ops.release(hw);
a4f58f54
BA		 5367
5368 return retval;
5369}
5370
23606cf5
RW		 5371static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5372 bool runtime)
bc7f75fa
AK		 5373{
5374 struct net_device *netdev = pci_get_drvdata(pdev);
5375 struct e1000_adapter *adapter = netdev_priv(netdev);
5376 struct e1000_hw *hw = &adapter->hw;
5377 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5378 /* Runtime suspend should only enable wakeup for link changes */
5379 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5380 int retval = 0;
5381
5382 netif_device_detach(netdev);
5383
5384 if (netif_running(netdev)) {
5385 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5386 e1000e_down(adapter);
5387 e1000_free_irq(adapter);
5388 }
4662e82b 5389 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5390
5391 retval = pci_save_state(pdev);
5392 if (retval)
5393 return retval;
5394
5395 status = er32(STATUS);
5396 if (status & E1000_STATUS_LU)
5397 wufc &= ~E1000_WUFC_LNKC;
5398
5399 if (wufc) {
5400 e1000_setup_rctl(adapter);
ef9b965a 5401 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5402
5403 /* turn on all-multi mode if wake on multicast is enabled */
5404 if (wufc & E1000_WUFC_MC) {
5405 rctl = er32(RCTL);
5406 rctl |= E1000_RCTL_MPE;
5407 ew32(RCTL, rctl);
5408 }
5409
5410 ctrl = er32(CTRL);
5411 /* advertise wake from D3Cold */
5412 #define E1000_CTRL_ADVD3WUC 0x00100000
5413 /* phy power management enable */
5414 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5415 ctrl |= E1000_CTRL_ADVD3WUC;
5416 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5417 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5418 ew32(CTRL, ctrl);
5419
318a94d6
JK		 5420 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5421 adapter->hw.phy.media_type ==
5422 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5423 /* keep the laser running in D3 */
5424 ctrl_ext = er32(CTRL_EXT);
93a23f48 5425 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5426 ew32(CTRL_EXT, ctrl_ext);
5427 }
5428
97ac8cae 5429 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5430 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5431
bc7f75fa
AK		 5432 /* Allow time for pending master requests to run */
5433 e1000e_disable_pcie_master(&adapter->hw);
5434
82776a4b 5435 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5436 /* enable wakeup by the PHY */
5437 retval = e1000_init_phy_wakeup(adapter, wufc);
5438 if (retval)
5439 return retval;
5440 } else {
5441 /* enable wakeup by the MAC */
5442 ew32(WUFC, wufc);
5443 ew32(WUC, E1000_WUC_PME_EN);
5444 }
bc7f75fa
AK		 5445 } else {
5446 ew32(WUC, 0);
5447 ew32(WUFC, 0);
bc7f75fa
AK		 5448 }
5449
4f9de721
RW		 5450 *enable_wake = !!wufc;
5451
bc7f75fa 5452 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5453 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5454 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5455 *enable_wake = true;
bc7f75fa
AK		 5456
5457 if (adapter->hw.phy.type == e1000_phy_igp_3)
5458 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5459
ad68076e
BA		 5460 /*
5461 * Release control of h/w to f/w. If f/w is AMT enabled, this
5462 * would have already happened in close and is redundant.
5463 */
31dbe5b4 5464 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5465
5466 pci_disable_device(pdev);
5467
4f9de721
RW		 5468 return 0;
5469}
5470
5471static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5472{
5473 if (sleep && wake) {
5474 pci_prepare_to_sleep(pdev);
5475 return;
5476 }
5477
5478 pci_wake_from_d3(pdev, wake);
5479 pci_set_power_state(pdev, PCI_D3hot);
5480}
5481
5482static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5483 bool wake)
5484{
5485 struct net_device *netdev = pci_get_drvdata(pdev);
5486 struct e1000_adapter *adapter = netdev_priv(netdev);
5487
005cbdfc
AD		 5488 /*
5489 * The pci-e switch on some quad port adapters will report a
5490 * correctable error when the MAC transitions from D0 to D3. To
5491 * prevent this we need to mask off the correctable errors on the
5492 * downstream port of the pci-e switch.
5493 */
5494 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5495 struct pci_dev *us_dev = pdev->bus->self;
353064de 5496 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5497 u16 devctl;
5498
5499 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5500 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5501 (devctl & ~PCI_EXP_DEVCTL_CERE));
5502
4f9de721 5503 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5504
5505 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5506 } else {
4f9de721 5507 e1000_power_off(pdev, sleep, wake);
005cbdfc 5508 }
bc7f75fa
AK		 5509}
5510
6f461f6c
BA		 5511#ifdef CONFIG_PCIEASPM
5512static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5513{
9f728f53 5514 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5515}
5516#else
5517static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5518{
5519 int pos;
6f461f6c 5520 u16 reg16;
1eae4eb2
AK		 5521
5522 /*
6f461f6c
BA		 5523 * Both device and parent should have the same ASPM setting.
5524 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5525 */
6f461f6c
BA		 5526 pos = pci_pcie_cap(pdev);
5527 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5528 reg16 &= ~state;
5529 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5530
0c75ba22
AB		 5531 if (!pdev->bus->self)
5532 return;
5533
6f461f6c
BA		 5534 pos = pci_pcie_cap(pdev->bus->self);
5535 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5536 reg16 &= ~state;
5537 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5538}
5539#endif
78cd29d5 5540static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5541{
5542 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5543 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5544 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5545
5546 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5547}
5548
aa338601 5549#ifdef CONFIG_PM
23606cf5 5550static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5551{
23606cf5 5552 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5553}
5554
23606cf5 5555static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5556{
5557 struct net_device *netdev = pci_get_drvdata(pdev);
5558 struct e1000_adapter *adapter = netdev_priv(netdev);
5559 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5560 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5561 u32 err;
5562
78cd29d5
BA		 5563 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5564 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5565 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5566 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5567 if (aspm_disable_flag)
5568 e1000e_disable_aspm(pdev, aspm_disable_flag);
5569
bc7f75fa
AK		 5570 pci_set_power_state(pdev, PCI_D0);
5571 pci_restore_state(pdev);
28b8f04a 5572 pci_save_state(pdev);
6e4f6f6b 5573
4662e82b 5574 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5575 if (netif_running(netdev)) {
5576 err = e1000_request_irq(adapter);
5577 if (err)
5578 return err;
5579 }
5580
99730e4c
BA		 5581 if (hw->mac.type == e1000_pch2lan)
5582 e1000_resume_workarounds_pchlan(&adapter->hw);
5583
bc7f75fa 5584 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5585
5586 /* report the system wakeup cause from S3/S4 */
5587 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5588 u16 phy_data;
5589
5590 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5591 if (phy_data) {
5592 e_info("PHY Wakeup cause - %s\n",
5593 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5594 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5595 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5596 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5597 phy_data & E1000_WUS_LNKC ?
5598 "Link Status Change" : "other");
a4f58f54
BA		 5599 }
5600 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5601 } else {
5602 u32 wus = er32(WUS);
5603 if (wus) {
5604 e_info("MAC Wakeup cause - %s\n",
5605 wus & E1000_WUS_EX ? "Unicast Packet" :
5606 wus & E1000_WUS_MC ? "Multicast Packet" :
5607 wus & E1000_WUS_BC ? "Broadcast Packet" :
5608 wus & E1000_WUS_MAG ? "Magic Packet" :
5609 wus & E1000_WUS_LNKC ? "Link Status Change" :
5610 "other");
5611 }
5612 ew32(WUS, ~0);
5613 }
5614
bc7f75fa 5615 e1000e_reset(adapter);
bc7f75fa 5616
cd791618 5617 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5618
5619 if (netif_running(netdev))
5620 e1000e_up(adapter);
5621
5622 netif_device_attach(netdev);
5623
ad68076e
BA		 5624 /*
5625 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5626 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5627 * under the control of the driver.
5628 */
c43bc57e 5629 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5630 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5631
5632 return 0;
5633}
23606cf5 5634
a0340162
RW		 5635#ifdef CONFIG_PM_SLEEP
5636static int e1000_suspend(struct device *dev)
5637{
5638 struct pci_dev *pdev = to_pci_dev(dev);
5639 int retval;
5640 bool wake;
5641
5642 retval = __e1000_shutdown(pdev, &wake, false);
5643 if (!retval)
5644 e1000_complete_shutdown(pdev, true, wake);
5645
5646 return retval;
5647}
5648
23606cf5
RW		 5649static int e1000_resume(struct device *dev)
5650{
5651 struct pci_dev *pdev = to_pci_dev(dev);
5652 struct net_device *netdev = pci_get_drvdata(pdev);
5653 struct e1000_adapter *adapter = netdev_priv(netdev);
5654
5655 if (e1000e_pm_ready(adapter))
5656 adapter->idle_check = true;
5657
5658 return __e1000_resume(pdev);
5659}
a0340162
RW		 5660#endif /* CONFIG_PM_SLEEP */
5661
5662#ifdef CONFIG_PM_RUNTIME
5663static int e1000_runtime_suspend(struct device *dev)
5664{
5665 struct pci_dev *pdev = to_pci_dev(dev);
5666 struct net_device *netdev = pci_get_drvdata(pdev);
5667 struct e1000_adapter *adapter = netdev_priv(netdev);
5668
5669 if (e1000e_pm_ready(adapter)) {
5670 bool wake;
5671
5672 __e1000_shutdown(pdev, &wake, true);
5673 }
5674
5675 return 0;
5676}
5677
5678static int e1000_idle(struct device *dev)
5679{
5680 struct pci_dev *pdev = to_pci_dev(dev);
5681 struct net_device *netdev = pci_get_drvdata(pdev);
5682 struct e1000_adapter *adapter = netdev_priv(netdev);
5683
5684 if (!e1000e_pm_ready(adapter))
5685 return 0;
5686
5687 if (adapter->idle_check) {
5688 adapter->idle_check = false;
5689 if (!e1000e_has_link(adapter))
5690 pm_schedule_suspend(dev, MSEC_PER_SEC);
5691 }
5692
5693 return -EBUSY;
5694}
23606cf5
RW		 5695
5696static int e1000_runtime_resume(struct device *dev)
5697{
5698 struct pci_dev *pdev = to_pci_dev(dev);
5699 struct net_device *netdev = pci_get_drvdata(pdev);
5700 struct e1000_adapter *adapter = netdev_priv(netdev);
5701
5702 if (!e1000e_pm_ready(adapter))
5703 return 0;
5704
5705 adapter->idle_check = !dev->power.runtime_auto;
5706 return __e1000_resume(pdev);
5707}
a0340162 5708#endif /* CONFIG_PM_RUNTIME */
aa338601 5709#endif /* CONFIG_PM */
bc7f75fa
AK		 5710
5711static void e1000_shutdown(struct pci_dev *pdev)
5712{
4f9de721
RW		 5713 bool wake = false;
5714
23606cf5 5715 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5716
5717 if (system_state == SYSTEM_POWER_OFF)
5718 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5719}
5720
5721#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5722
5723static irqreturn_t e1000_intr_msix(int irq, void *data)
5724{
5725 struct net_device *netdev = data;
5726 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5727
5728 if (adapter->msix_entries) {
90da0669
BA		 5729 int vector, msix_irq;
5730
147b2c8c
DD		 5731 vector = 0;
5732 msix_irq = adapter->msix_entries[vector].vector;
5733 disable_irq(msix_irq);
5734 e1000_intr_msix_rx(msix_irq, netdev);
5735 enable_irq(msix_irq);
5736
5737 vector++;
5738 msix_irq = adapter->msix_entries[vector].vector;
5739 disable_irq(msix_irq);
5740 e1000_intr_msix_tx(msix_irq, netdev);
5741 enable_irq(msix_irq);
5742
5743 vector++;
5744 msix_irq = adapter->msix_entries[vector].vector;
5745 disable_irq(msix_irq);
5746 e1000_msix_other(msix_irq, netdev);
5747 enable_irq(msix_irq);
5748 }
5749
5750 return IRQ_HANDLED;
5751}
5752
bc7f75fa
AK		 5753/*
5754 * Polling 'interrupt' - used by things like netconsole to send skbs
5755 * without having to re-enable interrupts. It's not called while
5756 * the interrupt routine is executing.
5757 */
5758static void e1000_netpoll(struct net_device *netdev)
5759{
5760 struct e1000_adapter *adapter = netdev_priv(netdev);
5761
147b2c8c
DD		 5762 switch (adapter->int_mode) {
5763 case E1000E_INT_MODE_MSIX:
5764 e1000_intr_msix(adapter->pdev->irq, netdev);
5765 break;
5766 case E1000E_INT_MODE_MSI:
5767 disable_irq(adapter->pdev->irq);
5768 e1000_intr_msi(adapter->pdev->irq, netdev);
5769 enable_irq(adapter->pdev->irq);
5770 break;
5771 default: /* E1000E_INT_MODE_LEGACY */
5772 disable_irq(adapter->pdev->irq);
5773 e1000_intr(adapter->pdev->irq, netdev);
5774 enable_irq(adapter->pdev->irq);
5775 break;
5776 }
bc7f75fa
AK		 5777}
5778#endif
5779
5780/**
5781 * e1000_io_error_detected - called when PCI error is detected
5782 * @pdev: Pointer to PCI device
5783 * @state: The current pci connection state
5784 *
5785 * This function is called after a PCI bus error affecting
5786 * this device has been detected.
5787 */
5788static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5789 pci_channel_state_t state)
5790{
5791 struct net_device *netdev = pci_get_drvdata(pdev);
5792 struct e1000_adapter *adapter = netdev_priv(netdev);
5793
5794 netif_device_detach(netdev);
5795
c93b5a76
MM		 5796 if (state == pci_channel_io_perm_failure)
5797 return PCI_ERS_RESULT_DISCONNECT;
5798
bc7f75fa
AK		 5799 if (netif_running(netdev))
5800 e1000e_down(adapter);
5801 pci_disable_device(pdev);
5802
5803 /* Request a slot slot reset. */
5804 return PCI_ERS_RESULT_NEED_RESET;
5805}
5806
5807/**
5808 * e1000_io_slot_reset - called after the pci bus has been reset.
5809 * @pdev: Pointer to PCI device
5810 *
5811 * Restart the card from scratch, as if from a cold-boot. Implementation
5812 * resembles the first-half of the e1000_resume routine.
5813 */
5814static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5815{
5816 struct net_device *netdev = pci_get_drvdata(pdev);
5817 struct e1000_adapter *adapter = netdev_priv(netdev);
5818 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5819 u16 aspm_disable_flag = 0;
6e4f6f6b 5820 int err;
111b9dc5 5821 pci_ers_result_t result;
bc7f75fa 5822
78cd29d5
BA		 5823 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5824 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5825 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5826 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5827 if (aspm_disable_flag)
5828 e1000e_disable_aspm(pdev, aspm_disable_flag);
5829
f0f422e5 5830 err = pci_enable_device_mem(pdev);
6e4f6f6b 5831 if (err) {
bc7f75fa
AK		 5832 dev_err(&pdev->dev,
5833 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5834 result = PCI_ERS_RESULT_DISCONNECT;
5835 } else {
5836 pci_set_master(pdev);
23606cf5 5837 pdev->state_saved = true;
111b9dc5 5838 pci_restore_state(pdev);
bc7f75fa 5839
111b9dc5
JB		 5840 pci_enable_wake(pdev, PCI_D3hot, 0);
5841 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5842
111b9dc5
JB		 5843 e1000e_reset(adapter);
5844 ew32(WUS, ~0);
5845 result = PCI_ERS_RESULT_RECOVERED;
5846 }
bc7f75fa 5847
111b9dc5
JB		 5848 pci_cleanup_aer_uncorrect_error_status(pdev);
5849
5850 return result;
bc7f75fa
AK		 5851}
5852
5853/**
5854 * e1000_io_resume - called when traffic can start flowing again.
5855 * @pdev: Pointer to PCI device
5856 *
5857 * This callback is called when the error recovery driver tells us that
5858 * its OK to resume normal operation. Implementation resembles the
5859 * second-half of the e1000_resume routine.
5860 */
5861static void e1000_io_resume(struct pci_dev *pdev)
5862{
5863 struct net_device *netdev = pci_get_drvdata(pdev);
5864 struct e1000_adapter *adapter = netdev_priv(netdev);
5865
cd791618 5866 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5867
5868 if (netif_running(netdev)) {
5869 if (e1000e_up(adapter)) {
5870 dev_err(&pdev->dev,
5871 "can't bring device back up after reset\n");
5872 return;
5873 }
5874 }
5875
5876 netif_device_attach(netdev);
5877
ad68076e
BA		 5878 /*
5879 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5880 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5881 * under the control of the driver.
5882 */
c43bc57e 5883 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5884 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5885
5886}
5887
5888static void e1000_print_device_info(struct e1000_adapter *adapter)
5889{
5890 struct e1000_hw *hw = &adapter->hw;
5891 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5892 u32 ret_val;
5893 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5894
5895 /* print bus type/speed/width info */
a5cc7642 5896 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5897 /* bus width */
5898 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5899 "Width x1"),
5900 /* MAC address */
7c510e4b 5901 netdev->dev_addr);
44defeb3
JK		 5902 e_info("Intel(R) PRO/%s Network Connection\n",
5903 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5904 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5905 E1000_PBANUM_LENGTH);
5906 if (ret_val)
e0dc4f12 5907 strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
073287c0
BA		 5908 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5909 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5910}
5911
10aa4c04
AK		 5912static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5913{
5914 struct e1000_hw *hw = &adapter->hw;
5915 int ret_val;
5916 u16 buf = 0;
5917
5918 if (hw->mac.type != e1000_82573)
5919 return;
5920
5921 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e243455d 5922 if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
10aa4c04 5923 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5924 dev_warn(&adapter->pdev->dev,
5925 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5926 }
10aa4c04
AK		 5927}
5928
c8f44aff
MM		 5929static int e1000_set_features(struct net_device *netdev,
5930 netdev_features_t features)
dc221294
BA		 5931{
5932 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5933 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5934
5935 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5936 adapter->flags |= FLAG_TSO_FORCE;
5937
5938 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
5939 NETIF_F_RXCSUM)))
5940 return 0;
5941
5942 if (netif_running(netdev))
5943 e1000e_reinit_locked(adapter);
5944 else
5945 e1000e_reset(adapter);
5946
5947 return 0;
5948}
5949
651c2466
SH		 5950static const struct net_device_ops e1000e_netdev_ops = {
5951 .ndo_open = e1000_open,
5952 .ndo_stop = e1000_close,
00829823 5953 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 5954 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 5955 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 5956 .ndo_set_mac_address = e1000_set_mac,
5957 .ndo_change_mtu = e1000_change_mtu,
5958 .ndo_do_ioctl = e1000_ioctl,
5959 .ndo_tx_timeout = e1000_tx_timeout,
5960 .ndo_validate_addr = eth_validate_addr,
5961
651c2466
SH		 5962 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
5963 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
5964#ifdef CONFIG_NET_POLL_CONTROLLER
5965 .ndo_poll_controller = e1000_netpoll,
5966#endif
dc221294 5967 .ndo_set_features = e1000_set_features,
651c2466
SH		 5968};
5969
bc7f75fa
AK		 5970/**
5971 * e1000_probe - Device Initialization Routine
5972 * @pdev: PCI device information struct
5973 * @ent: entry in e1000_pci_tbl
5974 *
5975 * Returns 0 on success, negative on failure
5976 *
5977 * e1000_probe initializes an adapter identified by a pci_dev structure.
5978 * The OS initialization, configuring of the adapter private structure,
5979 * and a hardware reset occur.
5980 **/
5981static int __devinit e1000_probe(struct pci_dev *pdev,
5982 const struct pci_device_id *ent)
5983{
5984 struct net_device *netdev;
5985 struct e1000_adapter *adapter;
5986 struct e1000_hw *hw;
5987 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 5988 resource_size_t mmio_start, mmio_len;
5989 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 5990
5991 static int cards_found;
78cd29d5 5992 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5993 int i, err, pci_using_dac;
5994 u16 eeprom_data = 0;
5995 u16 eeprom_apme_mask = E1000_EEPROM_APME;
5996
78cd29d5
BA		 5997 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
5998 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5999 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6000 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6001 if (aspm_disable_flag)
6002 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6003
f0f422e5 6004 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6005 if (err)
6006 return err;
6007
6008 pci_using_dac = 0;
0be3f55f 6009 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6010 if (!err) {
0be3f55f 6011 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6012 if (!err)
6013 pci_using_dac = 1;
6014 } else {
0be3f55f 6015 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6016 if (err) {
0be3f55f
NN		 6017 err = dma_set_coherent_mask(&pdev->dev,
6018 DMA_BIT_MASK(32));
bc7f75fa 6019 if (err) {
ef456f85 6020 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6021 goto err_dma;
6022 }
6023 }
6024 }
6025
e8de1481 6026 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6027 pci_select_bars(pdev, IORESOURCE_MEM),
6028 e1000e_driver_name);
bc7f75fa
AK		 6029 if (err)
6030 goto err_pci_reg;
6031
68eac460 6032 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6033 pci_enable_pcie_error_reporting(pdev);
68eac460 6034
bc7f75fa 6035 pci_set_master(pdev);
438b365a
BA		 6036 /* PCI config space info */
6037 err = pci_save_state(pdev);
6038 if (err)
6039 goto err_alloc_etherdev;
bc7f75fa
AK		 6040
6041 err = -ENOMEM;
6042 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6043 if (!netdev)
6044 goto err_alloc_etherdev;
6045
bc7f75fa
AK		 6046 SET_NETDEV_DEV(netdev, &pdev->dev);
6047
f85e4dfa
TH		 6048 netdev->irq = pdev->irq;
6049
bc7f75fa
AK		 6050 pci_set_drvdata(pdev, netdev);
6051 adapter = netdev_priv(netdev);
6052 hw = &adapter->hw;
6053 adapter->netdev = netdev;
6054 adapter->pdev = pdev;
6055 adapter->ei = ei;
6056 adapter->pba = ei->pba;
6057 adapter->flags = ei->flags;
eb7c3adb 6058 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6059 adapter->hw.adapter = adapter;
6060 adapter->hw.mac.type = ei->mac;
2adc55c9 6061 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6062 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6063
6064 mmio_start = pci_resource_start(pdev, 0);
6065 mmio_len = pci_resource_len(pdev, 0);
6066
6067 err = -EIO;
6068 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6069 if (!adapter->hw.hw_addr)
6070 goto err_ioremap;
6071
6072 if ((adapter->flags & FLAG_HAS_FLASH) &&
6073 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6074 flash_start = pci_resource_start(pdev, 1);
6075 flash_len = pci_resource_len(pdev, 1);
6076 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6077 if (!adapter->hw.flash_address)
6078 goto err_flashmap;
6079 }
6080
6081 /* construct the net_device struct */
651c2466 6082 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6083 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6084 netdev->watchdog_timeo = 5 * HZ;
6085 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
bc7f75fa
AK		 6086 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6087
6088 netdev->mem_start = mmio_start;
6089 netdev->mem_end = mmio_start + mmio_len;
6090
6091 adapter->bd_number = cards_found++;
6092
4662e82b
BA		 6093 e1000e_check_options(adapter);
6094
bc7f75fa
AK		 6095 /* setup adapter struct */
6096 err = e1000_sw_init(adapter);
6097 if (err)
6098 goto err_sw_init;
6099
bc7f75fa
AK		 6100 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6101 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6102 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6103
69e3fd8c 6104 err = ei->get_variants(adapter);
bc7f75fa
AK		 6105 if (err)
6106 goto err_hw_init;
6107
4a770358
BA		 6108 if ((adapter->flags & FLAG_IS_ICH) &&
6109 (adapter->flags & FLAG_READ_ONLY_NVM))
6110 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6111
bc7f75fa
AK		 6112 hw->mac.ops.get_bus_info(&adapter->hw);
6113
318a94d6 6114 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6115
6116 /* Copper options */
318a94d6 6117 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6118 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6119 adapter->hw.phy.disable_polarity_correction = 0;
6120 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6121 }
6122
6123 if (e1000_check_reset_block(&adapter->hw))
44defeb3 6124 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6125
dc221294
BA		 6126 /* Set initial default active device features */
6127 netdev->features = (NETIF_F_SG |
6128 NETIF_F_HW_VLAN_RX |
6129 NETIF_F_HW_VLAN_TX |
6130 NETIF_F_TSO |
6131 NETIF_F_TSO6 |
6132 NETIF_F_RXCSUM |
6133 NETIF_F_HW_CSUM);
6134
6135 /* Set user-changeable features (subset of all device features) */
6136 netdev->hw_features = netdev->features;
bc7f75fa
AK		 6137
6138 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6139 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6140
dc221294
BA		 6141 netdev->vlan_features |= (NETIF_F_SG |
6142 NETIF_F_TSO |
6143 NETIF_F_TSO6 |
6144 NETIF_F_HW_CSUM);
a5136e23 6145
ef9b965a
JB		 6146 netdev->priv_flags |= IFF_UNICAST_FLT;
6147
7b872a55 6148 if (pci_using_dac) {
bc7f75fa 6149 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6150 netdev->vlan_features |= NETIF_F_HIGHDMA;
6151 }
bc7f75fa 6152
bc7f75fa
AK		 6153 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6154 adapter->flags |= FLAG_MNG_PT_ENABLED;
6155
ad68076e
BA		 6156 /*
6157 * before reading the NVM, reset the controller to
6158 * put the device in a known good starting state
6159 */
bc7f75fa
AK		 6160 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6161
6162 /*
6163 * systems with ASPM and others may see the checksum fail on the first
6164 * attempt. Let's give it a few tries
6165 */
6166 for (i = 0;; i++) {
6167 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6168 break;
6169 if (i == 2) {
44defeb3 6170 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6171 err = -EIO;
6172 goto err_eeprom;
6173 }
6174 }
6175
10aa4c04
AK		 6176 e1000_eeprom_checks(adapter);
6177
608f8a0d 6178 /* copy the MAC address */
bc7f75fa 6179 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6180 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6181
6182 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6183 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6184
6185 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6186 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6187 err = -EIO;
6188 goto err_eeprom;
6189 }
6190
6191 init_timer(&adapter->watchdog_timer);
c061b18d 6192 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6193 adapter->watchdog_timer.data = (unsigned long) adapter;
6194
6195 init_timer(&adapter->phy_info_timer);
c061b18d 6196 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6197 adapter->phy_info_timer.data = (unsigned long) adapter;
6198
6199 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6200 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6201 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6202 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6203 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6204
bc7f75fa
AK		 6205 /* Initialize link parameters. User can change them with ethtool */
6206 adapter->hw.mac.autoneg = 1;
309af40b 6207 adapter->fc_autoneg = 1;
5c48ef3e
BA		 6208 adapter->hw.fc.requested_mode = e1000_fc_default;
6209 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6210 adapter->hw.phy.autoneg_advertised = 0x2f;
6211
6212 /* ring size defaults */
6213 adapter->rx_ring->count = 256;
6214 adapter->tx_ring->count = 256;
6215
6216 /*
6217 * Initial Wake on LAN setting - If APM wake is enabled in
6218 * the EEPROM, enable the ACPI Magic Packet filter
6219 */
6220 if (adapter->flags & FLAG_APME_IN_WUC) {
6221 /* APME bit in EEPROM is mapped to WUC.APME */
6222 eeprom_data = er32(WUC);
6223 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6224 if ((hw->mac.type > e1000_ich10lan) &&
6225 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6226 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6227 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6228 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6229 (adapter->hw.bus.func == 1))
6230 e1000_read_nvm(&adapter->hw,
6231 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6232 else
6233 e1000_read_nvm(&adapter->hw,
6234 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6235 }
6236
6237 /* fetch WoL from EEPROM */
6238 if (eeprom_data & eeprom_apme_mask)
6239 adapter->eeprom_wol |= E1000_WUFC_MAG;
6240
6241 /*
6242 * now that we have the eeprom settings, apply the special cases
6243 * where the eeprom may be wrong or the board simply won't support
6244 * wake on lan on a particular port
6245 */
6246 if (!(adapter->flags & FLAG_HAS_WOL))
6247 adapter->eeprom_wol = 0;
6248
6249 /* initialize the wol settings based on the eeprom settings */
6250 adapter->wol = adapter->eeprom_wol;
6ff68026 6251 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6252
84527590
BA		 6253 /* save off EEPROM version number */
6254 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6255
bc7f75fa
AK		 6256 /* reset the hardware with the new settings */
6257 e1000e_reset(adapter);
6258
ad68076e
BA		 6259 /*
6260 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6261 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6262 * under the control of the driver.
6263 */
c43bc57e 6264 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6265 e1000e_get_hw_control(adapter);
bc7f75fa 6266
e0dc4f12 6267 strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
bc7f75fa
AK		 6268 err = register_netdev(netdev);
6269 if (err)
6270 goto err_register;
6271
9c563d20
JB		 6272 /* carrier off reporting is important to ethtool even BEFORE open */
6273 netif_carrier_off(netdev);
6274
bc7f75fa
AK		 6275 e1000_print_device_info(adapter);
6276
f3ec4f87
AS		 6277 if (pci_dev_run_wake(pdev))
6278 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6279
bc7f75fa
AK		 6280 return 0;
6281
6282err_register:
c43bc57e 6283 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6284 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 6285err_eeprom:
6286 if (!e1000_check_reset_block(&adapter->hw))
6287 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6288err_hw_init:
bc7f75fa
AK		 6289 kfree(adapter->tx_ring);
6290 kfree(adapter->rx_ring);
6291err_sw_init:
c43bc57e
JB		 6292 if (adapter->hw.flash_address)
6293 iounmap(adapter->hw.flash_address);
e82f54ba 6294 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6295err_flashmap:
bc7f75fa
AK		 6296 iounmap(adapter->hw.hw_addr);
6297err_ioremap:
6298 free_netdev(netdev);
6299err_alloc_etherdev:
f0f422e5
BA		 6300 pci_release_selected_regions(pdev,
6301 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6302err_pci_reg:
6303err_dma:
6304 pci_disable_device(pdev);
6305 return err;
6306}
6307
6308/**
6309 * e1000_remove - Device Removal Routine
6310 * @pdev: PCI device information struct
6311 *
6312 * e1000_remove is called by the PCI subsystem to alert the driver
6313 * that it should release a PCI device. The could be caused by a
6314 * Hot-Plug event, or because the driver is going to be removed from
6315 * memory.
6316 **/
6317static void __devexit e1000_remove(struct pci_dev *pdev)
6318{
6319 struct net_device *netdev = pci_get_drvdata(pdev);
6320 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6321 bool down = test_bit(__E1000_DOWN, &adapter->state);
6322
ad68076e 6323 /*
23f333a2
TH		 6324 * The timers may be rescheduled, so explicitly disable them
6325 * from being rescheduled.
ad68076e 6326 */
23606cf5
RW		 6327 if (!down)
6328 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6329 del_timer_sync(&adapter->watchdog_timer);
6330 del_timer_sync(&adapter->phy_info_timer);
6331
41cec6f1
BA		 6332 cancel_work_sync(&adapter->reset_task);
6333 cancel_work_sync(&adapter->watchdog_task);
6334 cancel_work_sync(&adapter->downshift_task);
6335 cancel_work_sync(&adapter->update_phy_task);
6336 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6337
17f208de
BA		 6338 if (!(netdev->flags & IFF_UP))
6339 e1000_power_down_phy(adapter);
6340
23606cf5
RW		 6341 /* Don't lie to e1000_close() down the road. */
6342 if (!down)
6343 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6344 unregister_netdev(netdev);
6345
f3ec4f87
AS		 6346 if (pci_dev_run_wake(pdev))
6347 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6348
ad68076e
BA		 6349 /*
6350 * Release control of h/w to f/w. If f/w is AMT enabled, this
6351 * would have already happened in close and is redundant.
6352 */
31dbe5b4 6353 e1000e_release_hw_control(adapter);
bc7f75fa 6354
4662e82b 6355 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6356 kfree(adapter->tx_ring);
6357 kfree(adapter->rx_ring);
6358
6359 iounmap(adapter->hw.hw_addr);
6360 if (adapter->hw.flash_address)
6361 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6362 pci_release_selected_regions(pdev,
6363 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6364
6365 free_netdev(netdev);
6366
111b9dc5 6367 /* AER disable */
19d5afd4 6368 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6369
bc7f75fa
AK		 6370 pci_disable_device(pdev);
6371}
6372
6373/* PCI Error Recovery (ERS) */
6374static struct pci_error_handlers e1000_err_handler = {
6375 .error_detected = e1000_io_error_detected,
6376 .slot_reset = e1000_io_slot_reset,
6377 .resume = e1000_io_resume,
6378};
6379
a3aa1884 6380static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6381 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6382 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6383 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6384 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6385 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6386 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6387 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6388 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6389 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6390
bc7f75fa
AK		 6391 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6392 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6393 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6394 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6395
bc7f75fa
AK		 6396 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6397 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6398 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6399
4662e82b 6400 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6401 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6402 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6403
bc7f75fa
AK		 6404 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6405 board_80003es2lan },
6406 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6407 board_80003es2lan },
6408 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6409 board_80003es2lan },
6410 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6411 board_80003es2lan },
ad68076e 6412
bc7f75fa
AK		 6413 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6414 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6415 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6416 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6417 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6418 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6419 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6421
bc7f75fa
AK		 6422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6431
6432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6435
f4187b56
BA		 6436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6439
a4f58f54
BA		 6440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6443 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6444
d3738bb8
BA		 6445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6447
bc7f75fa
AK		 6448 { } /* terminate list */
6449};
6450MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6451
aa338601 6452#ifdef CONFIG_PM
23606cf5 6453static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6454 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6455 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6456 e1000_runtime_resume, e1000_idle)
23606cf5 6457};
e50208a0 6458#endif
23606cf5 6459
bc7f75fa
AK		 6460/* PCI Device API Driver */
6461static struct pci_driver e1000_driver = {
6462 .name = e1000e_driver_name,
6463 .id_table = e1000_pci_tbl,
6464 .probe = e1000_probe,
6465 .remove = __devexit_p(e1000_remove),
aa338601 6466#ifdef CONFIG_PM
23606cf5 6467 .driver.pm = &e1000_pm_ops,
bc7f75fa
AK		 6468#endif
6469 .shutdown = e1000_shutdown,
6470 .err_handler = &e1000_err_handler
6471};
6472
6473/**
6474 * e1000_init_module - Driver Registration Routine
6475 *
6476 * e1000_init_module is the first routine called when the driver is
6477 * loaded. All it does is register with the PCI subsystem.
6478 **/
6479static int __init e1000_init_module(void)
6480{
6481 int ret;
8544b9f7
BA		 6482 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6483 e1000e_driver_version);
0d6057e4 6484 pr_info("Copyright(c) 1999 - 2011 Intel Corporation.\n");
bc7f75fa 6485 ret = pci_register_driver(&e1000_driver);
53ec5498 6486
bc7f75fa
AK		 6487 return ret;
6488}
6489module_init(e1000_init_module);
6490
6491/**
6492 * e1000_exit_module - Driver Exit Cleanup Routine
6493 *
6494 * e1000_exit_module is called just before the driver is removed
6495 * from memory.
6496 **/
6497static void __exit e1000_exit_module(void)
6498{
6499 pci_unregister_driver(&e1000_driver);
6500}
6501module_exit(e1000_exit_module);
6502
6503
6504MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6505MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6506MODULE_LICENSE("GPL");
6507MODULE_VERSION(DRV_VERSION);
6508
6509/* e1000_main.c */
Linux kernel - Deliverables
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