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e1000e: do not ignore variables which get set a value
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
076d8070 59#define DRV_VERSION "2.1.4" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 82 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 83};
84
84f4ee90
TI		 85struct e1000_reg_info {
86 u32 ofs;
87 char *name;
88};
89
af667a29
BA		 90#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
91#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
92#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
93#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
94#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
95
96#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
97#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
98#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
99#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
100#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 101
102static const struct e1000_reg_info e1000_reg_info_tbl[] = {
103
104 /* General Registers */
105 {E1000_CTRL, "CTRL"},
106 {E1000_STATUS, "STATUS"},
107 {E1000_CTRL_EXT, "CTRL_EXT"},
108
109 /* Interrupt Registers */
110 {E1000_ICR, "ICR"},
111
af667a29 112 /* Rx Registers */
84f4ee90 113 {E1000_RCTL, "RCTL"},
1e36052e
BA		 114 {E1000_RDLEN(0), "RDLEN"},
115 {E1000_RDH(0), "RDH"},
116 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 117 {E1000_RDTR, "RDTR"},
118 {E1000_RXDCTL(0), "RXDCTL"},
119 {E1000_ERT, "ERT"},
1e36052e
BA		 120 {E1000_RDBAL(0), "RDBAL"},
121 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 122 {E1000_RDFH, "RDFH"},
123 {E1000_RDFT, "RDFT"},
124 {E1000_RDFHS, "RDFHS"},
125 {E1000_RDFTS, "RDFTS"},
126 {E1000_RDFPC, "RDFPC"},
127
af667a29 128 /* Tx Registers */
84f4ee90 129 {E1000_TCTL, "TCTL"},
1e36052e
BA		 130 {E1000_TDBAL(0), "TDBAL"},
131 {E1000_TDBAH(0), "TDBAH"},
132 {E1000_TDLEN(0), "TDLEN"},
133 {E1000_TDH(0), "TDH"},
134 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 135 {E1000_TIDV, "TIDV"},
136 {E1000_TXDCTL(0), "TXDCTL"},
137 {E1000_TADV, "TADV"},
138 {E1000_TARC(0), "TARC"},
139 {E1000_TDFH, "TDFH"},
140 {E1000_TDFT, "TDFT"},
141 {E1000_TDFHS, "TDFHS"},
142 {E1000_TDFTS, "TDFTS"},
143 {E1000_TDFPC, "TDFPC"},
144
145 /* List Terminator */
f36bb6ca 146 {0, NULL}
84f4ee90
TI		 147};
148
e921eb1a 149/**
84f4ee90 150 * e1000_regdump - register printout routine
e921eb1a
BA		 151 * @hw: pointer to the HW structure
152 * @reginfo: pointer to the register info table
153 **/
84f4ee90
TI		 154static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
155{
156 int n = 0;
157 char rname[16];
158 u32 regs[8];
159
160 switch (reginfo->ofs) {
161 case E1000_RXDCTL(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_RXDCTL(n));
164 break;
165 case E1000_TXDCTL(0):
166 for (n = 0; n < 2; n++)
167 regs[n] = __er32(hw, E1000_TXDCTL(n));
168 break;
169 case E1000_TARC(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_TARC(n));
172 break;
173 default:
ef456f85
JK		 174 pr_info("%-15s %08x\n",
175 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 176 return;
177 }
178
179 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 180 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 181}
182
f0c5dadf
ET		 183static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
184 struct e1000_buffer *bi)
185{
186 int i;
187 struct e1000_ps_page *ps_page;
188
189 for (i = 0; i < adapter->rx_ps_pages; i++) {
190 ps_page = &bi->ps_pages[i];
191
192 if (ps_page->page) {
193 pr_info("packet dump for ps_page %d:\n", i);
194 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
195 16, 1, page_address(ps_page->page),
196 PAGE_SIZE, true);
197 }
198 }
199}
200
e921eb1a 201/**
af667a29 202 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 203 * @adapter: board private structure
204 **/
84f4ee90
TI		 205static void e1000e_dump(struct e1000_adapter *adapter)
206{
207 struct net_device *netdev = adapter->netdev;
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_reg_info *reginfo;
210 struct e1000_ring *tx_ring = adapter->tx_ring;
211 struct e1000_tx_desc *tx_desc;
af667a29 212 struct my_u0 {
e885d762
BA		 213 __le64 a;
214 __le64 b;
af667a29 215 } *u0;
84f4ee90
TI		 216 struct e1000_buffer *buffer_info;
217 struct e1000_ring *rx_ring = adapter->rx_ring;
218 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 219 union e1000_rx_desc_extended *rx_desc;
af667a29 220 struct my_u1 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
223 __le64 c;
224 __le64 d;
af667a29 225 } *u1;
84f4ee90
TI		 226 u32 staterr;
227 int i = 0;
228
229 if (!netif_msg_hw(adapter))
230 return;
231
232 /* Print netdevice Info */
233 if (netdev) {
234 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 235 pr_info("Device Name state trans_start last_rx\n");
236 pr_info("%-15s %016lX %016lX %016lX\n",
237 netdev->name, netdev->state, netdev->trans_start,
238 netdev->last_rx);
84f4ee90
TI		 239 }
240
241 /* Print Registers */
242 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 243 pr_info(" Register Name Value\n");
84f4ee90
TI		 244 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
245 reginfo->name; reginfo++) {
246 e1000_regdump(hw, reginfo);
247 }
248
af667a29 249 /* Print Tx Ring Summary */
84f4ee90 250 if (!netdev || !netif_running(netdev))
fe1e980f 251 return;
84f4ee90 252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 254 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 255 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 256 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
257 0, tx_ring->next_to_use, tx_ring->next_to_clean,
258 (unsigned long long)buffer_info->dma,
259 buffer_info->length,
260 buffer_info->next_to_watch,
261 (unsigned long long)buffer_info->time_stamp);
84f4ee90 262
af667a29 263 /* Print Tx Ring */
84f4ee90
TI		 264 if (!netif_msg_tx_done(adapter))
265 goto rx_ring_summary;
266
af667a29 267 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 268
269 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
270 *
271 * Legacy Transmit Descriptor
272 * +--------------------------------------------------------------+
273 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
274 * +--------------------------------------------------------------+
275 * 8 | Special | CSS | Status | CMD | CSO | Length |
276 * +--------------------------------------------------------------+
277 * 63 48 47 36 35 32 31 24 23 16 15 0
278 *
279 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
280 * 63 48 47 40 39 32 31 16 15 8 7 0
281 * +----------------------------------------------------------------+
282 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
283 * +----------------------------------------------------------------+
284 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
285 * +----------------------------------------------------------------+
286 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
287 *
288 * Extended Data Descriptor (DTYP=0x1)
289 * +----------------------------------------------------------------+
290 * 0 | Buffer Address [63:0] |
291 * +----------------------------------------------------------------+
292 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
293 * +----------------------------------------------------------------+
294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
295 */
ef456f85
JK		 296 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
297 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
298 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 299 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 300 const char *next_desc;
84f4ee90
TI		 301 tx_desc = E1000_TX_DESC(*tx_ring, i);
302 buffer_info = &tx_ring->buffer_info[i];
303 u0 = (struct my_u0 *)tx_desc;
84f4ee90 304 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 305 next_desc = " NTC/U";
84f4ee90 306 else if (i == tx_ring->next_to_use)
ef456f85 307 next_desc = " NTU";
84f4ee90 308 else if (i == tx_ring->next_to_clean)
ef456f85 309 next_desc = " NTC";
84f4ee90 310 else
ef456f85
JK		 311 next_desc = "";
312 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
313 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
314 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
315 i,
316 (unsigned long long)le64_to_cpu(u0->a),
317 (unsigned long long)le64_to_cpu(u0->b),
318 (unsigned long long)buffer_info->dma,
319 buffer_info->length, buffer_info->next_to_watch,
320 (unsigned long long)buffer_info->time_stamp,
321 buffer_info->skb, next_desc);
84f4ee90 322
f0c5dadf 323 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 324 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 325 16, 1, buffer_info->skb->data,
326 buffer_info->skb->len, true);
84f4ee90
TI		 327 }
328
af667a29 329 /* Print Rx Ring Summary */
84f4ee90 330rx_ring_summary:
af667a29 331 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 332 pr_info("Queue [NTU] [NTC]\n");
333 pr_info(" %5d %5X %5X\n",
334 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 335
af667a29 336 /* Print Rx Ring */
84f4ee90 337 if (!netif_msg_rx_status(adapter))
fe1e980f 338 return;
84f4ee90 339
af667a29 340 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 341 switch (adapter->rx_ps_pages) {
342 case 1:
343 case 2:
344 case 3:
345 /* [Extended] Packet Split Receive Descriptor Format
346 *
347 * +-----------------------------------------------------+
348 * 0 | Buffer Address 0 [63:0] |
349 * +-----------------------------------------------------+
350 * 8 | Buffer Address 1 [63:0] |
351 * +-----------------------------------------------------+
352 * 16 | Buffer Address 2 [63:0] |
353 * +-----------------------------------------------------+
354 * 24 | Buffer Address 3 [63:0] |
355 * +-----------------------------------------------------+
356 */
ef456f85 357 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 358 /* [Extended] Receive Descriptor (Write-Back) Format
359 *
360 * 63 48 47 32 31 13 12 8 7 4 3 0
361 * +------------------------------------------------------+
362 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
363 * | Checksum | Ident | | Queue | | Type |
364 * +------------------------------------------------------+
365 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
366 * +------------------------------------------------------+
367 * 63 48 47 32 31 20 19 0
368 */
ef456f85 369 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 370 for (i = 0; i < rx_ring->count; i++) {
ef456f85 371 const char *next_desc;
84f4ee90
TI		 372 buffer_info = &rx_ring->buffer_info[i];
373 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
374 u1 = (struct my_u1 *)rx_desc_ps;
375 staterr =
af667a29 376 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 377
378 if (i == rx_ring->next_to_use)
379 next_desc = " NTU";
380 else if (i == rx_ring->next_to_clean)
381 next_desc = " NTC";
382 else
383 next_desc = "";
384
84f4ee90
TI		 385 if (staterr & E1000_RXD_STAT_DD) {
386 /* Descriptor Done */
ef456f85
JK		 387 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
388 "RWB", i,
389 (unsigned long long)le64_to_cpu(u1->a),
390 (unsigned long long)le64_to_cpu(u1->b),
391 (unsigned long long)le64_to_cpu(u1->c),
392 (unsigned long long)le64_to_cpu(u1->d),
393 buffer_info->skb, next_desc);
84f4ee90 394 } else {
ef456f85
JK		 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
396 "R ", i,
397 (unsigned long long)le64_to_cpu(u1->a),
398 (unsigned long long)le64_to_cpu(u1->b),
399 (unsigned long long)le64_to_cpu(u1->c),
400 (unsigned long long)le64_to_cpu(u1->d),
401 (unsigned long long)buffer_info->dma,
402 buffer_info->skb, next_desc);
84f4ee90
TI		 403
404 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 405 e1000e_dump_ps_pages(adapter,
406 buffer_info);
84f4ee90 407 }
84f4ee90
TI		 408 }
409 break;
410 default:
411 case 0:
5f450212 412 /* Extended Receive Descriptor (Read) Format
84f4ee90 413 *
5f450212
BA		 414 * +-----------------------------------------------------+
415 * 0 | Buffer Address [63:0] |
416 * +-----------------------------------------------------+
417 * 8 | Reserved |
418 * +-----------------------------------------------------+
84f4ee90 419 */
ef456f85 420 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 421 /* Extended Receive Descriptor (Write-Back) Format
422 *
423 * 63 48 47 32 31 24 23 4 3 0
424 * +------------------------------------------------------+
425 * | RSS Hash | | | |
426 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
427 * | Packet | IP | | | Type |
428 * | Checksum | Ident | | | |
429 * +------------------------------------------------------+
430 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
431 * +------------------------------------------------------+
432 * 63 48 47 32 31 20 19 0
433 */
ef456f85 434 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 435
436 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 437 const char *next_desc;
438
84f4ee90 439 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 440 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
441 u1 = (struct my_u1 *)rx_desc;
442 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 443
444 if (i == rx_ring->next_to_use)
445 next_desc = " NTU";
446 else if (i == rx_ring->next_to_clean)
447 next_desc = " NTC";
448 else
449 next_desc = "";
450
5f450212
BA		 451 if (staterr & E1000_RXD_STAT_DD) {
452 /* Descriptor Done */
ef456f85
JK		 453 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
454 "RWB", i,
455 (unsigned long long)le64_to_cpu(u1->a),
456 (unsigned long long)le64_to_cpu(u1->b),
457 buffer_info->skb, next_desc);
5f450212 458 } else {
ef456f85
JK		 459 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
460 "R ", i,
461 (unsigned long long)le64_to_cpu(u1->a),
462 (unsigned long long)le64_to_cpu(u1->b),
463 (unsigned long long)buffer_info->dma,
464 buffer_info->skb, next_desc);
5f450212 465
f0c5dadf
ET		 466 if (netif_msg_pktdata(adapter) &&
467 buffer_info->skb)
5f450212
BA		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16,
470 1,
f0c5dadf 471 buffer_info->skb->data,
5f450212
BA		 472 adapter->rx_buffer_len,
473 true);
474 }
84f4ee90
TI		 475 }
476 }
84f4ee90
TI		 477}
478
bc7f75fa
AK		 479/**
480 * e1000_desc_unused - calculate if we have unused descriptors
481 **/
482static int e1000_desc_unused(struct e1000_ring *ring)
483{
484 if (ring->next_to_clean > ring->next_to_use)
485 return ring->next_to_clean - ring->next_to_use - 1;
486
487 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
488}
489
b67e1913
BA		 490/**
491 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
492 * @adapter: board private structure
493 * @hwtstamps: time stamp structure to update
494 * @systim: unsigned 64bit system time value.
495 *
496 * Convert the system time value stored in the RX/TXSTMP registers into a
497 * hwtstamp which can be used by the upper level time stamping functions.
498 *
499 * The 'systim_lock' spinlock is used to protect the consistency of the
500 * system time value. This is needed because reading the 64 bit time
501 * value involves reading two 32 bit registers. The first read latches the
502 * value.
503 **/
504static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
505 struct skb_shared_hwtstamps *hwtstamps,
506 u64 systim)
507{
508 u64 ns;
509 unsigned long flags;
510
511 spin_lock_irqsave(&adapter->systim_lock, flags);
512 ns = timecounter_cyc2time(&adapter->tc, systim);
513 spin_unlock_irqrestore(&adapter->systim_lock, flags);
514
515 memset(hwtstamps, 0, sizeof(*hwtstamps));
516 hwtstamps->hwtstamp = ns_to_ktime(ns);
517}
518
519/**
520 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
521 * @adapter: board private structure
522 * @status: descriptor extended error and status field
523 * @skb: particular skb to include time stamp
524 *
525 * If the time stamp is valid, convert it into the timecounter ns value
526 * and store that result into the shhwtstamps structure which is passed
527 * up the network stack.
528 **/
529static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
530 struct sk_buff *skb)
531{
532 struct e1000_hw *hw = &adapter->hw;
533 u64 rxstmp;
534
535 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
536 !(status & E1000_RXDEXT_STATERR_TST) ||
537 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
538 return;
539
540 /* The Rx time stamp registers contain the time stamp. No other
541 * received packet will be time stamped until the Rx time stamp
542 * registers are read. Because only one packet can be time stamped
543 * at a time, the register values must belong to this packet and
544 * therefore none of the other additional attributes need to be
545 * compared.
546 */
547 rxstmp = (u64)er32(RXSTMPL);
548 rxstmp |= (u64)er32(RXSTMPH) << 32;
549 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
550
551 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
552}
553
bc7f75fa 554/**
ad68076e 555 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 556 * @adapter: board private structure
b67e1913 557 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 558 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
559 * @skb: pointer to sk_buff to be indicated to stack
560 **/
561static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 562 struct net_device *netdev, struct sk_buff *skb,
b67e1913 563 u32 staterr, __le16 vlan)
bc7f75fa 564{
86d70e53 565 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 566
567 e1000e_rx_hwtstamp(adapter, staterr, skb);
568
bc7f75fa
AK		 569 skb->protocol = eth_type_trans(skb, netdev);
570
b67e1913 571 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 572 __vlan_hwaccel_put_tag(skb, tag);
573
574 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 575}
576
577/**
af667a29 578 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 579 * @adapter: board private structure
580 * @status_err: receive descriptor status and error fields
581 * @csum: receive descriptor csum field
582 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 583 **/
584static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 585 struct sk_buff *skb)
bc7f75fa
AK		 586{
587 u16 status = (u16)status_err;
588 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 589
590 skb_checksum_none_assert(skb);
bc7f75fa 591
afd12939
BA		 592 /* Rx checksum disabled */
593 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
594 return;
595
bc7f75fa
AK		 596 /* Ignore Checksum bit is set */
597 if (status & E1000_RXD_STAT_IXSM)
598 return;
afd12939 599
2e1706f2
BA		 600 /* TCP/UDP checksum error bit or IP checksum error bit is set */
601 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 602 /* let the stack verify checksum errors */
603 adapter->hw_csum_err++;
604 return;
605 }
606
607 /* TCP/UDP Checksum has not been calculated */
608 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
609 return;
610
611 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 612 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 613 adapter->hw_csum_good++;
614}
615
55aa6985 616static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 617{
55aa6985 618 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 619 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 620 s32 ret_val = __ew32_prepare(hw);
621
622 writel(i, rx_ring->tail);
c6e7f51e 623
bdc125f7 624 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 625 u32 rctl = er32(RCTL);
626 ew32(RCTL, rctl & ~E1000_RCTL_EN);
627 e_err("ME firmware caused invalid RDT - resetting\n");
628 schedule_work(&adapter->reset_task);
629 }
630}
631
55aa6985 632static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 633{
55aa6985 634 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 635 struct e1000_hw *hw = &adapter->hw;
bdc125f7 636 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 637
bdc125f7
BA		 638 writel(i, tx_ring->tail);
639
640 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 641 u32 tctl = er32(TCTL);
642 ew32(TCTL, tctl & ~E1000_TCTL_EN);
643 e_err("ME firmware caused invalid TDT - resetting\n");
644 schedule_work(&adapter->reset_task);
645 }
646}
647
bc7f75fa 648/**
5f450212 649 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 650 * @rx_ring: Rx descriptor ring
bc7f75fa 651 **/
55aa6985 652static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 653 int cleaned_count, gfp_t gfp)
bc7f75fa 654{
55aa6985 655 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 656 struct net_device *netdev = adapter->netdev;
657 struct pci_dev *pdev = adapter->pdev;
5f450212 658 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 659 struct e1000_buffer *buffer_info;
660 struct sk_buff *skb;
661 unsigned int i;
89d71a66 662 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 663
664 i = rx_ring->next_to_use;
665 buffer_info = &rx_ring->buffer_info[i];
666
667 while (cleaned_count--) {
668 skb = buffer_info->skb;
669 if (skb) {
670 skb_trim(skb, 0);
671 goto map_skb;
672 }
673
c2fed996 674 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 675 if (!skb) {
676 /* Better luck next round */
677 adapter->alloc_rx_buff_failed++;
678 break;
679 }
680
bc7f75fa
AK		 681 buffer_info->skb = skb;
682map_skb:
0be3f55f 683 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 684 adapter->rx_buffer_len,
0be3f55f
NN		 685 DMA_FROM_DEVICE);
686 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 687 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 688 adapter->rx_dma_failed++;
689 break;
690 }
691
5f450212
BA		 692 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
693 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 694
50849d79 695 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 696 /* Force memory writes to complete before letting h/w
50849d79
TH		 697 * know there are new descriptors to fetch. (Only
698 * applicable for weak-ordered memory model archs,
699 * such as IA-64).
700 */
701 wmb();
c6e7f51e 702 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 703 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 704 else
c5083cf6 705 writel(i, rx_ring->tail);
50849d79 706 }
bc7f75fa
AK		 707 i++;
708 if (i == rx_ring->count)
709 i = 0;
710 buffer_info = &rx_ring->buffer_info[i];
711 }
712
50849d79 713 rx_ring->next_to_use = i;
bc7f75fa
AK		 714}
715
716/**
717 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 718 * @rx_ring: Rx descriptor ring
bc7f75fa 719 **/
55aa6985 720static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 721 int cleaned_count, gfp_t gfp)
bc7f75fa 722{
55aa6985 723 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 724 struct net_device *netdev = adapter->netdev;
725 struct pci_dev *pdev = adapter->pdev;
726 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 727 struct e1000_buffer *buffer_info;
728 struct e1000_ps_page *ps_page;
729 struct sk_buff *skb;
730 unsigned int i, j;
731
732 i = rx_ring->next_to_use;
733 buffer_info = &rx_ring->buffer_info[i];
734
735 while (cleaned_count--) {
736 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
737
738 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 739 ps_page = &buffer_info->ps_pages[j];
740 if (j >= adapter->rx_ps_pages) {
741 /* all unused desc entries get hw null ptr */
af667a29
BA		 742 rx_desc->read.buffer_addr[j + 1] =
743 ~cpu_to_le64(0);
47f44e40
AK		 744 continue;
745 }
746 if (!ps_page->page) {
c2fed996 747 ps_page->page = alloc_page(gfp);
bc7f75fa 748 if (!ps_page->page) {
47f44e40
AK		 749 adapter->alloc_rx_buff_failed++;
750 goto no_buffers;
751 }
0be3f55f
NN		 752 ps_page->dma = dma_map_page(&pdev->dev,
753 ps_page->page,
754 0, PAGE_SIZE,
755 DMA_FROM_DEVICE);
756 if (dma_mapping_error(&pdev->dev,
757 ps_page->dma)) {
47f44e40 758 dev_err(&adapter->pdev->dev,
af667a29 759 "Rx DMA page map failed\n");
47f44e40
AK		 760 adapter->rx_dma_failed++;
761 goto no_buffers;
bc7f75fa 762 }
bc7f75fa 763 }
e921eb1a 764 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 765 * didn't change because each write-back
766 * erases this info.
767 */
af667a29
BA		 768 rx_desc->read.buffer_addr[j + 1] =
769 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 770 }
771
c2fed996
JK		 772 skb = __netdev_alloc_skb_ip_align(netdev,
773 adapter->rx_ps_bsize0,
774 gfp);
bc7f75fa
AK		 775
776 if (!skb) {
777 adapter->alloc_rx_buff_failed++;
778 break;
779 }
780
bc7f75fa 781 buffer_info->skb = skb;
0be3f55f 782 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 783 adapter->rx_ps_bsize0,
0be3f55f
NN		 784 DMA_FROM_DEVICE);
785 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 786 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 787 adapter->rx_dma_failed++;
788 /* cleanup skb */
789 dev_kfree_skb_any(skb);
790 buffer_info->skb = NULL;
791 break;
792 }
793
794 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
795
50849d79 796 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 797 /* Force memory writes to complete before letting h/w
50849d79
TH		 798 * know there are new descriptors to fetch. (Only
799 * applicable for weak-ordered memory model archs,
800 * such as IA-64).
801 */
802 wmb();
c6e7f51e 803 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 804 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 805 else
c5083cf6 806 writel(i << 1, rx_ring->tail);
50849d79
TH		 807 }
808
bc7f75fa
AK		 809 i++;
810 if (i == rx_ring->count)
811 i = 0;
812 buffer_info = &rx_ring->buffer_info[i];
813 }
814
815no_buffers:
50849d79 816 rx_ring->next_to_use = i;
bc7f75fa
AK		 817}
818
97ac8cae
BA		 819/**
820 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 821 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 822 * @cleaned_count: number of buffers to allocate this pass
823 **/
824
55aa6985 825static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 826 int cleaned_count, gfp_t gfp)
97ac8cae 827{
55aa6985 828 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 829 struct net_device *netdev = adapter->netdev;
830 struct pci_dev *pdev = adapter->pdev;
5f450212 831 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 832 struct e1000_buffer *buffer_info;
833 struct sk_buff *skb;
834 unsigned int i;
2a2293b9 835 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 836
837 i = rx_ring->next_to_use;
838 buffer_info = &rx_ring->buffer_info[i];
839
840 while (cleaned_count--) {
841 skb = buffer_info->skb;
842 if (skb) {
843 skb_trim(skb, 0);
844 goto check_page;
845 }
846
c2fed996 847 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 848 if (unlikely(!skb)) {
849 /* Better luck next round */
850 adapter->alloc_rx_buff_failed++;
851 break;
852 }
853
97ac8cae
BA		 854 buffer_info->skb = skb;
855check_page:
856 /* allocate a new page if necessary */
857 if (!buffer_info->page) {
c2fed996 858 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 859 if (unlikely(!buffer_info->page)) {
860 adapter->alloc_rx_buff_failed++;
861 break;
862 }
863 }
864
865 if (!buffer_info->dma)
0be3f55f 866 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 867 buffer_info->page, 0,
868 PAGE_SIZE,
0be3f55f 869 DMA_FROM_DEVICE);
97ac8cae 870
5f450212
BA		 871 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
872 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 873
874 if (unlikely(++i == rx_ring->count))
875 i = 0;
876 buffer_info = &rx_ring->buffer_info[i];
877 }
878
879 if (likely(rx_ring->next_to_use != i)) {
880 rx_ring->next_to_use = i;
881 if (unlikely(i-- == 0))
882 i = (rx_ring->count - 1);
883
884 /* Force memory writes to complete before letting h/w
885 * know there are new descriptors to fetch. (Only
886 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 887 * such as IA-64).
888 */
97ac8cae 889 wmb();
c6e7f51e 890 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 891 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 892 else
c5083cf6 893 writel(i, rx_ring->tail);
97ac8cae
BA		 894 }
895}
896
70495a50
BA		 897static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
898 struct sk_buff *skb)
899{
900 if (netdev->features & NETIF_F_RXHASH)
901 skb->rxhash = le32_to_cpu(rss);
902}
903
bc7f75fa 904/**
55aa6985
BA		 905 * e1000_clean_rx_irq - Send received data up the network stack
906 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 907 *
908 * the return value indicates whether actual cleaning was done, there
909 * is no guarantee that everything was cleaned
910 **/
55aa6985
BA		 911static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
912 int work_to_do)
bc7f75fa 913{
55aa6985 914 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 915 struct net_device *netdev = adapter->netdev;
916 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 917 struct e1000_hw *hw = &adapter->hw;
5f450212 918 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 919 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 920 u32 length, staterr;
bc7f75fa
AK		 921 unsigned int i;
922 int cleaned_count = 0;
3db1cd5c 923 bool cleaned = false;
bc7f75fa
AK		 924 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
925
926 i = rx_ring->next_to_clean;
5f450212
BA		 927 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 929 buffer_info = &rx_ring->buffer_info[i];
930
5f450212 931 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 932 struct sk_buff *skb;
bc7f75fa
AK		 933
934 if (*work_done >= work_to_do)
935 break;
936 (*work_done)++;
2d0bb1c1 937 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 938
bc7f75fa
AK		 939 skb = buffer_info->skb;
940 buffer_info->skb = NULL;
941
942 prefetch(skb->data - NET_IP_ALIGN);
943
944 i++;
945 if (i == rx_ring->count)
946 i = 0;
5f450212 947 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 948 prefetch(next_rxd);
949
950 next_buffer = &rx_ring->buffer_info[i];
951
3db1cd5c 952 cleaned = true;
bc7f75fa 953 cleaned_count++;
0be3f55f 954 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 955 buffer_info->dma,
956 adapter->rx_buffer_len,
0be3f55f 957 DMA_FROM_DEVICE);
bc7f75fa
AK		 958 buffer_info->dma = 0;
959
5f450212 960 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 961
e921eb1a 962 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 963 * packet, if that's the case we need to toss it. In fact, we
964 * need to toss every packet with the EOP bit clear and the
965 * next frame that _does_ have the EOP bit set, as it is by
966 * definition only a frame fragment
967 */
5f450212 968 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 969 adapter->flags2 |= FLAG2_IS_DISCARDING;
970
971 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 972 /* All receives must fit into a single buffer */
3bb99fe2 973 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 974 /* recycle */
975 buffer_info->skb = skb;
5f450212 976 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 977 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 978 goto next_desc;
979 }
980
cf955e6c
BG		 981 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
982 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 983 /* recycle */
984 buffer_info->skb = skb;
985 goto next_desc;
986 }
987
eb7c3adb 988 /* adjust length to remove Ethernet CRC */
0184039a
BG		 989 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
990 /* If configured to store CRC, don't subtract FCS,
991 * but keep the FCS bytes out of the total_rx_bytes
992 * counter
993 */
994 if (netdev->features & NETIF_F_RXFCS)
995 total_rx_bytes -= 4;
996 else
997 length -= 4;
998 }
eb7c3adb 999
bc7f75fa
AK		 1000 total_rx_bytes += length;
1001 total_rx_packets++;
1002
e921eb1a 1003 /* code added for copybreak, this should improve
bc7f75fa 1004 * performance for small packets with large amounts
ad68076e
BA		 1005 * of reassembly being done in the stack
1006 */
bc7f75fa
AK		 1007 if (length < copybreak) {
1008 struct sk_buff *new_skb =
89d71a66 1009 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 1010 if (new_skb) {
808ff676
BA		 1011 skb_copy_to_linear_data_offset(new_skb,
1012 -NET_IP_ALIGN,
1013 (skb->data -
1014 NET_IP_ALIGN),
1015 (length +
1016 NET_IP_ALIGN));
bc7f75fa
AK		 1017 /* save the skb in buffer_info as good */
1018 buffer_info->skb = skb;
1019 skb = new_skb;
1020 }
1021 /* else just continue with the old one */
1022 }
1023 /* end copybreak code */
1024 skb_put(skb, length);
1025
1026 /* Receive Checksum Offload */
2e1706f2 1027 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1028
70495a50
BA		 1029 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1030
5f450212
BA		 1031 e1000_receive_skb(adapter, netdev, skb, staterr,
1032 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1033
1034next_desc:
5f450212 1035 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1036
1037 /* return some buffers to hardware, one at a time is too slow */
1038 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1039 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1040 GFP_ATOMIC);
bc7f75fa
AK		 1041 cleaned_count = 0;
1042 }
1043
1044 /* use prefetched values */
1045 rx_desc = next_rxd;
1046 buffer_info = next_buffer;
5f450212
BA		 1047
1048 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1049 }
1050 rx_ring->next_to_clean = i;
1051
1052 cleaned_count = e1000_desc_unused(rx_ring);
1053 if (cleaned_count)
55aa6985 1054 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1055
bc7f75fa 1056 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1057 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1058 return cleaned;
1059}
1060
55aa6985
BA		 1061static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1062 struct e1000_buffer *buffer_info)
bc7f75fa 1063{
55aa6985
BA		 1064 struct e1000_adapter *adapter = tx_ring->adapter;
1065
03b1320d
AD		 1066 if (buffer_info->dma) {
1067 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1068 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1069 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1070 else
0be3f55f
NN		 1071 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1072 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1073 buffer_info->dma = 0;
1074 }
bc7f75fa
AK		 1075 if (buffer_info->skb) {
1076 dev_kfree_skb_any(buffer_info->skb);
1077 buffer_info->skb = NULL;
1078 }
1b7719c4 1079 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1080}
1081
41cec6f1 1082static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1083{
41cec6f1
BA		 1084 struct e1000_adapter *adapter = container_of(work,
1085 struct e1000_adapter,
1086 print_hang_task);
09357b00 1087 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1088 struct e1000_ring *tx_ring = adapter->tx_ring;
1089 unsigned int i = tx_ring->next_to_clean;
1090 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1091 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1092 struct e1000_hw *hw = &adapter->hw;
1093 u16 phy_status, phy_1000t_status, phy_ext_status;
1094 u16 pci_status;
1095
615b32af
JB		 1096 if (test_bit(__E1000_DOWN, &adapter->state))
1097 return;
1098
09357b00
JK		 1099 if (!adapter->tx_hang_recheck &&
1100 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1101 /* May be block on write-back, flush and detect again
09357b00
JK		 1102 * flush pending descriptor writebacks to memory
1103 */
1104 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1105 /* execute the writes immediately */
1106 e1e_flush();
e921eb1a 1107 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1108 * the write is successful
1109 */
1110 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1111 /* execute the writes immediately */
1112 e1e_flush();
09357b00
JK		 1113 adapter->tx_hang_recheck = true;
1114 return;
1115 }
1116 /* Real hang detected */
1117 adapter->tx_hang_recheck = false;
1118 netif_stop_queue(netdev);
1119
41cec6f1
BA		 1120 e1e_rphy(hw, PHY_STATUS, &phy_status);
1121 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1122 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1123
41cec6f1
BA		 1124 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1125
1126 /* detected Hardware unit hang */
1127 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1128 " TDH <%x>\n"
1129 " TDT <%x>\n"
1130 " next_to_use <%x>\n"
1131 " next_to_clean <%x>\n"
1132 "buffer_info[next_to_clean]:\n"
1133 " time_stamp <%lx>\n"
1134 " next_to_watch <%x>\n"
1135 " jiffies <%lx>\n"
41cec6f1
BA		 1136 " next_to_watch.status <%x>\n"
1137 "MAC Status <%x>\n"
1138 "PHY Status <%x>\n"
1139 "PHY 1000BASE-T Status <%x>\n"
1140 "PHY Extended Status <%x>\n"
1141 "PCI Status <%x>\n",
c5083cf6
BA		 1142 readl(tx_ring->head),
1143 readl(tx_ring->tail),
44defeb3
JK		 1144 tx_ring->next_to_use,
1145 tx_ring->next_to_clean,
1146 tx_ring->buffer_info[eop].time_stamp,
1147 eop,
1148 jiffies,
41cec6f1
BA		 1149 eop_desc->upper.fields.status,
1150 er32(STATUS),
1151 phy_status,
1152 phy_1000t_status,
1153 phy_ext_status,
1154 pci_status);
7c0427ee
BA		 1155
1156 /* Suggest workaround for known h/w issue */
1157 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1158 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1159}
1160
b67e1913
BA		 1161/**
1162 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1163 * @work: pointer to work struct
1164 *
1165 * This work function polls the TSYNCTXCTL valid bit to determine when a
1166 * timestamp has been taken for the current stored skb. The timestamp must
1167 * be for this skb because only one such packet is allowed in the queue.
1168 */
1169static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1170{
1171 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1172 tx_hwtstamp_work);
1173 struct e1000_hw *hw = &adapter->hw;
1174
1175 if (!adapter->tx_hwtstamp_skb)
1176 return;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct skb_shared_hwtstamps shhwtstamps;
1180 u64 txstmp;
1181
1182 txstmp = er32(TXSTMPL);
1183 txstmp |= (u64)er32(TXSTMPH) << 32;
1184
1185 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1186
1187 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1188 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1189 adapter->tx_hwtstamp_skb = NULL;
1190 } else {
1191 /* reschedule to check later */
1192 schedule_work(&adapter->tx_hwtstamp_work);
1193 }
1194}
1195
bc7f75fa
AK		 1196/**
1197 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1198 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1199 *
1200 * the return value indicates whether actual cleaning was done, there
1201 * is no guarantee that everything was cleaned
1202 **/
55aa6985 1203static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1204{
55aa6985 1205 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1206 struct net_device *netdev = adapter->netdev;
1207 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1208 struct e1000_tx_desc *tx_desc, *eop_desc;
1209 struct e1000_buffer *buffer_info;
1210 unsigned int i, eop;
1211 unsigned int count = 0;
bc7f75fa 1212 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1213 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1214
1215 i = tx_ring->next_to_clean;
1216 eop = tx_ring->buffer_info[i].next_to_watch;
1217 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1218
12d04a3c
AD		 1219 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1220 (count < tx_ring->count)) {
a86043c2 1221 bool cleaned = false;
2d0bb1c1 1222 rmb(); /* read buffer_info after eop_desc */
a86043c2 1223 for (; !cleaned; count++) {
bc7f75fa
AK		 1224 tx_desc = E1000_TX_DESC(*tx_ring, i);
1225 buffer_info = &tx_ring->buffer_info[i];
1226 cleaned = (i == eop);
1227
1228 if (cleaned) {
9ed318d5
TH		 1229 total_tx_packets += buffer_info->segs;
1230 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1231 if (buffer_info->skb) {
1232 bytes_compl += buffer_info->skb->len;
1233 pkts_compl++;
1234 }
bc7f75fa
AK		 1235 }
1236
55aa6985 1237 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1238 tx_desc->upper.data = 0;
1239
1240 i++;
1241 if (i == tx_ring->count)
1242 i = 0;
1243 }
1244
dac87619
TL		 1245 if (i == tx_ring->next_to_use)
1246 break;
bc7f75fa
AK		 1247 eop = tx_ring->buffer_info[i].next_to_watch;
1248 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1249 }
1250
1251 tx_ring->next_to_clean = i;
1252
3f0cfa3b
TH		 1253 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1254
bc7f75fa 1255#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1256 if (count && netif_carrier_ok(netdev) &&
1257 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1258 /* Make sure that anybody stopping the queue after this
1259 * sees the new next_to_clean.
1260 */
1261 smp_mb();
1262
1263 if (netif_queue_stopped(netdev) &&
1264 !(test_bit(__E1000_DOWN, &adapter->state))) {
1265 netif_wake_queue(netdev);
1266 ++adapter->restart_queue;
1267 }
1268 }
1269
1270 if (adapter->detect_tx_hung) {
e921eb1a 1271 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1272 * check with the clearing of time_stamp and movement of i
1273 */
3db1cd5c 1274 adapter->detect_tx_hung = false;
12d04a3c
AD		 1275 if (tx_ring->buffer_info[i].time_stamp &&
1276 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1277 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1278 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1279 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1280 else
1281 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1282 }
1283 adapter->total_tx_bytes += total_tx_bytes;
1284 adapter->total_tx_packets += total_tx_packets;
807540ba 1285 return count < tx_ring->count;
bc7f75fa
AK		 1286}
1287
bc7f75fa
AK		 1288/**
1289 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1290 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1291 *
1292 * the return value indicates whether actual cleaning was done, there
1293 * is no guarantee that everything was cleaned
1294 **/
55aa6985
BA		 1295static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1296 int work_to_do)
bc7f75fa 1297{
55aa6985 1298 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1299 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1300 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1301 struct net_device *netdev = adapter->netdev;
1302 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1303 struct e1000_buffer *buffer_info, *next_buffer;
1304 struct e1000_ps_page *ps_page;
1305 struct sk_buff *skb;
1306 unsigned int i, j;
1307 u32 length, staterr;
1308 int cleaned_count = 0;
3db1cd5c 1309 bool cleaned = false;
bc7f75fa
AK		 1310 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1311
1312 i = rx_ring->next_to_clean;
1313 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1314 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1315 buffer_info = &rx_ring->buffer_info[i];
1316
1317 while (staterr & E1000_RXD_STAT_DD) {
1318 if (*work_done >= work_to_do)
1319 break;
1320 (*work_done)++;
1321 skb = buffer_info->skb;
2d0bb1c1 1322 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1323
1324 /* in the packet split case this is header only */
1325 prefetch(skb->data - NET_IP_ALIGN);
1326
1327 i++;
1328 if (i == rx_ring->count)
1329 i = 0;
1330 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1331 prefetch(next_rxd);
1332
1333 next_buffer = &rx_ring->buffer_info[i];
1334
3db1cd5c 1335 cleaned = true;
bc7f75fa 1336 cleaned_count++;
0be3f55f 1337 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1338 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1339 buffer_info->dma = 0;
1340
af667a29 1341 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1342 if (!(staterr & E1000_RXD_STAT_EOP))
1343 adapter->flags2 |= FLAG2_IS_DISCARDING;
1344
1345 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1346 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1347 dev_kfree_skb_irq(skb);
b94b5028
JB		 1348 if (staterr & E1000_RXD_STAT_EOP)
1349 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1350 goto next_desc;
1351 }
1352
cf955e6c
BG		 1353 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1354 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1355 dev_kfree_skb_irq(skb);
1356 goto next_desc;
1357 }
1358
1359 length = le16_to_cpu(rx_desc->wb.middle.length0);
1360
1361 if (!length) {
ef456f85 1362 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1363 dev_kfree_skb_irq(skb);
1364 goto next_desc;
1365 }
1366
1367 /* Good Receive */
1368 skb_put(skb, length);
1369
1370 {
e921eb1a 1371 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1372 * it more efficient than reusing j
1373 */
1374 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1375
e921eb1a 1376 /* page alloc/put takes too long and effects small
0e15df49
BA		 1377 * packet throughput, so unsplit small packets and
1378 * save the alloc/put only valid in softirq (napi)
1379 * context to call kmap_*
ad68076e 1380 */
0e15df49
BA		 1381 if (l1 && (l1 <= copybreak) &&
1382 ((length + l1) <= adapter->rx_ps_bsize0)) {
1383 u8 *vaddr;
1384
1385 ps_page = &buffer_info->ps_pages[0];
1386
e921eb1a 1387 /* there is no documentation about how to call
0e15df49
BA		 1388 * kmap_atomic, so we can't hold the mapping
1389 * very long
1390 */
1391 dma_sync_single_for_cpu(&pdev->dev,
1392 ps_page->dma,
1393 PAGE_SIZE,
1394 DMA_FROM_DEVICE);
9f393834 1395 vaddr = kmap_atomic(ps_page->page);
0e15df49 1396 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1397 kunmap_atomic(vaddr);
0e15df49
BA		 1398 dma_sync_single_for_device(&pdev->dev,
1399 ps_page->dma,
1400 PAGE_SIZE,
1401 DMA_FROM_DEVICE);
1402
1403 /* remove the CRC */
0184039a
BG		 1404 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1405 if (!(netdev->features & NETIF_F_RXFCS))
1406 l1 -= 4;
1407 }
0e15df49
BA		 1408
1409 skb_put(skb, l1);
1410 goto copydone;
1411 } /* if */
bc7f75fa
AK		 1412 }
1413
1414 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1415 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1416 if (!length)
1417 break;
1418
47f44e40 1419 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1420 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1421 DMA_FROM_DEVICE);
bc7f75fa
AK		 1422 ps_page->dma = 0;
1423 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1424 ps_page->page = NULL;
1425 skb->len += length;
1426 skb->data_len += length;
98a045d7 1427 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1428 }
1429
eb7c3adb
JK		 1430 /* strip the ethernet crc, problem is we're using pages now so
1431 * this whole operation can get a little cpu intensive
1432 */
0184039a
BG		 1433 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1434 if (!(netdev->features & NETIF_F_RXFCS))
1435 pskb_trim(skb, skb->len - 4);
1436 }
eb7c3adb 1437
bc7f75fa
AK		 1438copydone:
1439 total_rx_bytes += skb->len;
1440 total_rx_packets++;
1441
2e1706f2 1442 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1443
70495a50
BA		 1444 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1445
bc7f75fa
AK		 1446 if (rx_desc->wb.upper.header_status &
1447 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1448 adapter->rx_hdr_split++;
1449
b67e1913
BA		 1450 e1000_receive_skb(adapter, netdev, skb, staterr,
1451 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1452
1453next_desc:
1454 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1455 buffer_info->skb = NULL;
1456
1457 /* return some buffers to hardware, one at a time is too slow */
1458 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1459 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1460 GFP_ATOMIC);
bc7f75fa
AK		 1461 cleaned_count = 0;
1462 }
1463
1464 /* use prefetched values */
1465 rx_desc = next_rxd;
1466 buffer_info = next_buffer;
1467
1468 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1469 }
1470 rx_ring->next_to_clean = i;
1471
1472 cleaned_count = e1000_desc_unused(rx_ring);
1473 if (cleaned_count)
55aa6985 1474 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1475
bc7f75fa 1476 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1477 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1478 return cleaned;
1479}
1480
97ac8cae
BA		 1481/**
1482 * e1000_consume_page - helper function
1483 **/
1484static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1485 u16 length)
1486{
1487 bi->page = NULL;
1488 skb->len += length;
1489 skb->data_len += length;
98a045d7 1490 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1491}
1492
1493/**
1494 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1495 * @adapter: board private structure
1496 *
1497 * the return value indicates whether actual cleaning was done, there
1498 * is no guarantee that everything was cleaned
1499 **/
55aa6985
BA		 1500static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1501 int work_to_do)
97ac8cae 1502{
55aa6985 1503 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1504 struct net_device *netdev = adapter->netdev;
1505 struct pci_dev *pdev = adapter->pdev;
5f450212 1506 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1507 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1508 u32 length, staterr;
97ac8cae
BA		 1509 unsigned int i;
1510 int cleaned_count = 0;
1511 bool cleaned = false;
1512 unsigned int total_rx_bytes=0, total_rx_packets=0;
1513
1514 i = rx_ring->next_to_clean;
5f450212
BA		 1515 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1516 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1517 buffer_info = &rx_ring->buffer_info[i];
1518
5f450212 1519 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1520 struct sk_buff *skb;
97ac8cae
BA		 1521
1522 if (*work_done >= work_to_do)
1523 break;
1524 (*work_done)++;
2d0bb1c1 1525 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1526
97ac8cae
BA		 1527 skb = buffer_info->skb;
1528 buffer_info->skb = NULL;
1529
1530 ++i;
1531 if (i == rx_ring->count)
1532 i = 0;
5f450212 1533 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1534 prefetch(next_rxd);
1535
1536 next_buffer = &rx_ring->buffer_info[i];
1537
1538 cleaned = true;
1539 cleaned_count++;
0be3f55f
NN		 1540 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1541 DMA_FROM_DEVICE);
97ac8cae
BA		 1542 buffer_info->dma = 0;
1543
5f450212 1544 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1545
1546 /* errors is only valid for DD + EOP descriptors */
5f450212 1547 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1548 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1549 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1550 /* recycle both page and skb */
1551 buffer_info->skb = skb;
1552 /* an error means any chain goes out the window too */
1553 if (rx_ring->rx_skb_top)
1554 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1555 rx_ring->rx_skb_top = NULL;
1556 goto next_desc;
97ac8cae
BA		 1557 }
1558
f0f1a172 1559#define rxtop (rx_ring->rx_skb_top)
5f450212 1560 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1561 /* this descriptor is only the beginning (or middle) */
1562 if (!rxtop) {
1563 /* this is the beginning of a chain */
1564 rxtop = skb;
1565 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1566 0, length);
1567 } else {
1568 /* this is the middle of a chain */
1569 skb_fill_page_desc(rxtop,
1570 skb_shinfo(rxtop)->nr_frags,
1571 buffer_info->page, 0, length);
1572 /* re-use the skb, only consumed the page */
1573 buffer_info->skb = skb;
1574 }
1575 e1000_consume_page(buffer_info, rxtop, length);
1576 goto next_desc;
1577 } else {
1578 if (rxtop) {
1579 /* end of the chain */
1580 skb_fill_page_desc(rxtop,
1581 skb_shinfo(rxtop)->nr_frags,
1582 buffer_info->page, 0, length);
1583 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1584 * page
1585 */
97ac8cae
BA		 1586 buffer_info->skb = skb;
1587 skb = rxtop;
1588 rxtop = NULL;
1589 e1000_consume_page(buffer_info, skb, length);
1590 } else {
1591 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1592 * copybreak to save the put_page/alloc_page
1593 */
97ac8cae
BA		 1594 if (length <= copybreak &&
1595 skb_tailroom(skb) >= length) {
1596 u8 *vaddr;
4679026d 1597 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1598 memcpy(skb_tail_pointer(skb), vaddr,
1599 length);
4679026d 1600 kunmap_atomic(vaddr);
97ac8cae 1601 /* re-use the page, so don't erase
e921eb1a
BA		 1602 * buffer_info->page
1603 */
97ac8cae
BA		 1604 skb_put(skb, length);
1605 } else {
1606 skb_fill_page_desc(skb, 0,
1607 buffer_info->page, 0,
1608 length);
1609 e1000_consume_page(buffer_info, skb,
1610 length);
1611 }
1612 }
1613 }
1614
2e1706f2
BA		 1615 /* Receive Checksum Offload */
1616 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1617
70495a50
BA		 1618 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1619
97ac8cae
BA		 1620 /* probably a little skewed due to removing CRC */
1621 total_rx_bytes += skb->len;
1622 total_rx_packets++;
1623
1624 /* eth type trans needs skb->data to point to something */
1625 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1626 e_err("pskb_may_pull failed.\n");
ef5ab89c 1627 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1628 goto next_desc;
1629 }
1630
5f450212
BA		 1631 e1000_receive_skb(adapter, netdev, skb, staterr,
1632 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1633
1634next_desc:
5f450212 1635 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1636
1637 /* return some buffers to hardware, one at a time is too slow */
1638 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1639 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1640 GFP_ATOMIC);
97ac8cae
BA		 1641 cleaned_count = 0;
1642 }
1643
1644 /* use prefetched values */
1645 rx_desc = next_rxd;
1646 buffer_info = next_buffer;
5f450212
BA		 1647
1648 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1649 }
1650 rx_ring->next_to_clean = i;
1651
1652 cleaned_count = e1000_desc_unused(rx_ring);
1653 if (cleaned_count)
55aa6985 1654 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1655
1656 adapter->total_rx_bytes += total_rx_bytes;
1657 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1658 return cleaned;
1659}
1660
bc7f75fa
AK		 1661/**
1662 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1663 * @rx_ring: Rx descriptor ring
bc7f75fa 1664 **/
55aa6985 1665static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1666{
55aa6985 1667 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1668 struct e1000_buffer *buffer_info;
1669 struct e1000_ps_page *ps_page;
1670 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1671 unsigned int i, j;
1672
1673 /* Free all the Rx ring sk_buffs */
1674 for (i = 0; i < rx_ring->count; i++) {
1675 buffer_info = &rx_ring->buffer_info[i];
1676 if (buffer_info->dma) {
1677 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1678 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1679 adapter->rx_buffer_len,
0be3f55f 1680 DMA_FROM_DEVICE);
97ac8cae 1681 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1682 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1683 PAGE_SIZE,
0be3f55f 1684 DMA_FROM_DEVICE);
bc7f75fa 1685 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1686 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1687 adapter->rx_ps_bsize0,
0be3f55f 1688 DMA_FROM_DEVICE);
bc7f75fa
AK		 1689 buffer_info->dma = 0;
1690 }
1691
97ac8cae
BA		 1692 if (buffer_info->page) {
1693 put_page(buffer_info->page);
1694 buffer_info->page = NULL;
1695 }
1696
bc7f75fa
AK		 1697 if (buffer_info->skb) {
1698 dev_kfree_skb(buffer_info->skb);
1699 buffer_info->skb = NULL;
1700 }
1701
1702 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1703 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1704 if (!ps_page->page)
1705 break;
0be3f55f
NN		 1706 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1707 DMA_FROM_DEVICE);
bc7f75fa
AK		 1708 ps_page->dma = 0;
1709 put_page(ps_page->page);
1710 ps_page->page = NULL;
1711 }
1712 }
1713
1714 /* there also may be some cached data from a chained receive */
1715 if (rx_ring->rx_skb_top) {
1716 dev_kfree_skb(rx_ring->rx_skb_top);
1717 rx_ring->rx_skb_top = NULL;
1718 }
1719
bc7f75fa
AK		 1720 /* Zero out the descriptor ring */
1721 memset(rx_ring->desc, 0, rx_ring->size);
1722
1723 rx_ring->next_to_clean = 0;
1724 rx_ring->next_to_use = 0;
b94b5028 1725 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1726
c5083cf6 1727 writel(0, rx_ring->head);
bdc125f7
BA		 1728 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1729 e1000e_update_rdt_wa(rx_ring, 0);
1730 else
1731 writel(0, rx_ring->tail);
bc7f75fa
AK		 1732}
1733
a8f88ff5
JB		 1734static void e1000e_downshift_workaround(struct work_struct *work)
1735{
1736 struct e1000_adapter *adapter = container_of(work,
1737 struct e1000_adapter, downshift_task);
1738
615b32af
JB		 1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
a8f88ff5
JB		 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
bc7f75fa
AK		 1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
e921eb1a 1757 /* read ICR disables interrupts using IAM */
573cca8c 1758 if (icr & E1000_ICR_LSC) {
f92518dd 1759 hw->mac.get_link_status = true;
e921eb1a 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1761 * disconnect (LSC) before accessing any PHY registers
1762 */
bc7f75fa
AK		 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1765 schedule_work(&adapter->downshift_task);
bc7f75fa 1766
e921eb1a 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1768 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1769 * adapter in watchdog
1770 */
bc7f75fa
AK		 1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1776 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1777 }
1778 /* guard against interrupt when we're going down */
1779 if (!test_bit(__E1000_DOWN, &adapter->state))
1780 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1781 }
1782
94fb848b
BA		 1783 /* Reset on uncorrectable ECC error */
1784 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1785 u32 pbeccsts = er32(PBECCSTS);
1786
1787 adapter->corr_errors +=
1788 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1789 adapter->uncorr_errors +=
1790 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1791 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
288379f0 1800 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
288379f0 1805 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1806 }
1807
1808 return IRQ_HANDLED;
1809}
1810
1811/**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
1816static irqreturn_t e1000_intr(int irq, void *data)
1817{
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1821 u32 rctl, icr = er32(ICR);
4662e82b 1822
a68ea775 1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1824 return IRQ_NONE; /* Not our interrupt */
1825
e921eb1a 1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1827 * not set, then the adapter didn't send an interrupt
1828 */
bc7f75fa
AK		 1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
e921eb1a 1832 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
bc7f75fa 1836
573cca8c 1837 if (icr & E1000_ICR_LSC) {
f92518dd 1838 hw->mac.get_link_status = true;
e921eb1a 1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1840 * disconnect (LSC) before accessing any PHY registers
1841 */
bc7f75fa
AK		 1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1844 schedule_work(&adapter->downshift_task);
bc7f75fa 1845
e921eb1a 1846 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1856 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1861 }
1862
94fb848b
BA		 1863 /* Reset on uncorrectable ECC error */
1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
1870 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1871 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1872
1873 /* Do the reset outside of interrupt context */
1874 schedule_work(&adapter->reset_task);
1875
1876 /* return immediately since reset is imminent */
1877 return IRQ_HANDLED;
1878 }
1879
288379f0 1880 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1881 adapter->total_tx_bytes = 0;
1882 adapter->total_tx_packets = 0;
1883 adapter->total_rx_bytes = 0;
1884 adapter->total_rx_packets = 0;
288379f0 1885 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1886 }
1887
1888 return IRQ_HANDLED;
1889}
1890
4662e82b
BA		 1891static irqreturn_t e1000_msix_other(int irq, void *data)
1892{
1893 struct net_device *netdev = data;
1894 struct e1000_adapter *adapter = netdev_priv(netdev);
1895 struct e1000_hw *hw = &adapter->hw;
1896 u32 icr = er32(ICR);
1897
1898 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1899 if (!test_bit(__E1000_DOWN, &adapter->state))
1900 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1901 return IRQ_NONE;
1902 }
1903
1904 if (icr & adapter->eiac_mask)
1905 ew32(ICS, (icr & adapter->eiac_mask));
1906
1907 if (icr & E1000_ICR_OTHER) {
1908 if (!(icr & E1000_ICR_LSC))
1909 goto no_link_interrupt;
f92518dd 1910 hw->mac.get_link_status = true;
4662e82b
BA		 1911 /* guard against interrupt when we're going down */
1912 if (!test_bit(__E1000_DOWN, &adapter->state))
1913 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1914 }
1915
1916no_link_interrupt:
a3c69fef
JB		 1917 if (!test_bit(__E1000_DOWN, &adapter->state))
1918 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1919
1920 return IRQ_HANDLED;
1921}
1922
1923
1924static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1925{
1926 struct net_device *netdev = data;
1927 struct e1000_adapter *adapter = netdev_priv(netdev);
1928 struct e1000_hw *hw = &adapter->hw;
1929 struct e1000_ring *tx_ring = adapter->tx_ring;
1930
1931
1932 adapter->total_tx_bytes = 0;
1933 adapter->total_tx_packets = 0;
1934
55aa6985 1935 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1936 /* Ring was not completely cleaned, so fire another interrupt */
1937 ew32(ICS, tx_ring->ims_val);
1938
1939 return IRQ_HANDLED;
1940}
1941
1942static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1943{
1944 struct net_device *netdev = data;
1945 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1946 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1947
1948 /* Write the ITR value calculated at the end of the
1949 * previous interrupt.
1950 */
55aa6985
BA		 1951 if (rx_ring->set_itr) {
1952 writel(1000000000 / (rx_ring->itr_val * 256),
1953 rx_ring->itr_register);
1954 rx_ring->set_itr = 0;
4662e82b
BA		 1955 }
1956
288379f0 1957 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1958 adapter->total_rx_bytes = 0;
1959 adapter->total_rx_packets = 0;
288379f0 1960 __napi_schedule(&adapter->napi);
4662e82b
BA		 1961 }
1962 return IRQ_HANDLED;
1963}
1964
1965/**
1966 * e1000_configure_msix - Configure MSI-X hardware
1967 *
1968 * e1000_configure_msix sets up the hardware to properly
1969 * generate MSI-X interrupts.
1970 **/
1971static void e1000_configure_msix(struct e1000_adapter *adapter)
1972{
1973 struct e1000_hw *hw = &adapter->hw;
1974 struct e1000_ring *rx_ring = adapter->rx_ring;
1975 struct e1000_ring *tx_ring = adapter->tx_ring;
1976 int vector = 0;
1977 u32 ctrl_ext, ivar = 0;
1978
1979 adapter->eiac_mask = 0;
1980
1981 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1982 if (hw->mac.type == e1000_82574) {
1983 u32 rfctl = er32(RFCTL);
1984 rfctl |= E1000_RFCTL_ACK_DIS;
1985 ew32(RFCTL, rfctl);
1986 }
1987
1988#define E1000_IVAR_INT_ALLOC_VALID 0x8
1989 /* Configure Rx vector */
1990 rx_ring->ims_val = E1000_IMS_RXQ0;
1991 adapter->eiac_mask |= rx_ring->ims_val;
1992 if (rx_ring->itr_val)
1993 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1994 rx_ring->itr_register);
4662e82b 1995 else
c5083cf6 1996 writel(1, rx_ring->itr_register);
4662e82b
BA		 1997 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1998
1999 /* Configure Tx vector */
2000 tx_ring->ims_val = E1000_IMS_TXQ0;
2001 vector++;
2002 if (tx_ring->itr_val)
2003 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 2004 tx_ring->itr_register);
4662e82b 2005 else
c5083cf6 2006 writel(1, tx_ring->itr_register);
4662e82b
BA		 2007 adapter->eiac_mask |= tx_ring->ims_val;
2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2009
2010 /* set vector for Other Causes, e.g. link changes */
2011 vector++;
2012 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2013 if (rx_ring->itr_val)
2014 writel(1000000000 / (rx_ring->itr_val * 256),
2015 hw->hw_addr + E1000_EITR_82574(vector));
2016 else
2017 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2018
2019 /* Cause Tx interrupts on every write back */
2020 ivar |= (1 << 31);
2021
2022 ew32(IVAR, ivar);
2023
2024 /* enable MSI-X PBA support */
2025 ctrl_ext = er32(CTRL_EXT);
2026 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2027
2028 /* Auto-Mask Other interrupts upon ICR read */
2029#define E1000_EIAC_MASK_82574 0x01F00000
2030 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2031 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2032 ew32(CTRL_EXT, ctrl_ext);
2033 e1e_flush();
2034}
2035
2036void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2037{
2038 if (adapter->msix_entries) {
2039 pci_disable_msix(adapter->pdev);
2040 kfree(adapter->msix_entries);
2041 adapter->msix_entries = NULL;
2042 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2043 pci_disable_msi(adapter->pdev);
2044 adapter->flags &= ~FLAG_MSI_ENABLED;
2045 }
4662e82b
BA		 2046}
2047
2048/**
2049 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2050 *
2051 * Attempt to configure interrupts using the best available
2052 * capabilities of the hardware and kernel.
2053 **/
2054void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2055{
2056 int err;
8e86acd7 2057 int i;
4662e82b
BA		 2058
2059 switch (adapter->int_mode) {
2060 case E1000E_INT_MODE_MSIX:
2061 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2062 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2063 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 2064 sizeof(struct msix_entry),
2065 GFP_KERNEL);
2066 if (adapter->msix_entries) {
8e86acd7 2067 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2068 adapter->msix_entries[i].entry = i;
2069
2070 err = pci_enable_msix(adapter->pdev,
2071 adapter->msix_entries,
8e86acd7 2072 adapter->num_vectors);
b1cdfead 2073 if (err == 0)
4662e82b
BA		 2074 return;
2075 }
2076 /* MSI-X failed, so fall through and try MSI */
ef456f85 2077 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2078 e1000e_reset_interrupt_capability(adapter);
2079 }
2080 adapter->int_mode = E1000E_INT_MODE_MSI;
2081 /* Fall through */
2082 case E1000E_INT_MODE_MSI:
2083 if (!pci_enable_msi(adapter->pdev)) {
2084 adapter->flags |= FLAG_MSI_ENABLED;
2085 } else {
2086 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2087 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2088 }
2089 /* Fall through */
2090 case E1000E_INT_MODE_LEGACY:
2091 /* Don't do anything; this is the system default */
2092 break;
2093 }
8e86acd7
JK		 2094
2095 /* store the number of vectors being used */
2096 adapter->num_vectors = 1;
4662e82b
BA		 2097}
2098
2099/**
2100 * e1000_request_msix - Initialize MSI-X interrupts
2101 *
2102 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2103 * kernel.
2104 **/
2105static int e1000_request_msix(struct e1000_adapter *adapter)
2106{
2107 struct net_device *netdev = adapter->netdev;
2108 int err = 0, vector = 0;
2109
2110 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2111 snprintf(adapter->rx_ring->name,
2112 sizeof(adapter->rx_ring->name) - 1,
2113 "%s-rx-0", netdev->name);
4662e82b
BA		 2114 else
2115 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2116 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2117 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2118 netdev);
2119 if (err)
5015e53a 2120 return err;
c5083cf6
BA		 2121 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2122 E1000_EITR_82574(vector);
4662e82b
BA		 2123 adapter->rx_ring->itr_val = adapter->itr;
2124 vector++;
2125
2126 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2127 snprintf(adapter->tx_ring->name,
2128 sizeof(adapter->tx_ring->name) - 1,
2129 "%s-tx-0", netdev->name);
4662e82b
BA		 2130 else
2131 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2132 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2133 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2134 netdev);
2135 if (err)
5015e53a 2136 return err;
c5083cf6
BA		 2137 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2138 E1000_EITR_82574(vector);
4662e82b
BA		 2139 adapter->tx_ring->itr_val = adapter->itr;
2140 vector++;
2141
2142 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2143 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2144 if (err)
5015e53a 2145 return err;
4662e82b
BA		 2146
2147 e1000_configure_msix(adapter);
5015e53a 2148
4662e82b 2149 return 0;
4662e82b
BA		 2150}
2151
f8d59f78
BA		 2152/**
2153 * e1000_request_irq - initialize interrupts
2154 *
2155 * Attempts to configure interrupts using the best available
2156 * capabilities of the hardware and kernel.
2157 **/
bc7f75fa
AK		 2158static int e1000_request_irq(struct e1000_adapter *adapter)
2159{
2160 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2161 int err;
2162
4662e82b
BA		 2163 if (adapter->msix_entries) {
2164 err = e1000_request_msix(adapter);
2165 if (!err)
2166 return err;
2167 /* fall back to MSI */
2168 e1000e_reset_interrupt_capability(adapter);
2169 adapter->int_mode = E1000E_INT_MODE_MSI;
2170 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2171 }
4662e82b 2172 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2173 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2174 netdev->name, netdev);
2175 if (!err)
2176 return err;
bc7f75fa 2177
4662e82b
BA		 2178 /* fall back to legacy interrupt */
2179 e1000e_reset_interrupt_capability(adapter);
2180 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2181 }
2182
a0607fd3 2183 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2184 netdev->name, netdev);
2185 if (err)
2186 e_err("Unable to allocate interrupt, Error: %d\n", err);
2187
bc7f75fa
AK		 2188 return err;
2189}
2190
2191static void e1000_free_irq(struct e1000_adapter *adapter)
2192{
2193 struct net_device *netdev = adapter->netdev;
2194
4662e82b
BA		 2195 if (adapter->msix_entries) {
2196 int vector = 0;
2197
2198 free_irq(adapter->msix_entries[vector].vector, netdev);
2199 vector++;
2200
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 vector++;
2203
2204 /* Other Causes interrupt vector */
2205 free_irq(adapter->msix_entries[vector].vector, netdev);
2206 return;
bc7f75fa 2207 }
4662e82b
BA		 2208
2209 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2210}
2211
2212/**
2213 * e1000_irq_disable - Mask off interrupt generation on the NIC
2214 **/
2215static void e1000_irq_disable(struct e1000_adapter *adapter)
2216{
2217 struct e1000_hw *hw = &adapter->hw;
2218
bc7f75fa 2219 ew32(IMC, ~0);
4662e82b
BA		 2220 if (adapter->msix_entries)
2221 ew32(EIAC_82574, 0);
bc7f75fa 2222 e1e_flush();
8e86acd7
JK		 2223
2224 if (adapter->msix_entries) {
2225 int i;
2226 for (i = 0; i < adapter->num_vectors; i++)
2227 synchronize_irq(adapter->msix_entries[i].vector);
2228 } else {
2229 synchronize_irq(adapter->pdev->irq);
2230 }
bc7f75fa
AK		 2231}
2232
2233/**
2234 * e1000_irq_enable - Enable default interrupt generation settings
2235 **/
2236static void e1000_irq_enable(struct e1000_adapter *adapter)
2237{
2238 struct e1000_hw *hw = &adapter->hw;
2239
4662e82b
BA		 2240 if (adapter->msix_entries) {
2241 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2242 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2243 } else if (hw->mac.type == e1000_pch_lpt) {
2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
74ef9c39 2248 e1e_flush();
bc7f75fa
AK		 2249}
2250
2251/**
31dbe5b4 2252 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2253 * @adapter: address of board private structure
2254 *
31dbe5b4 2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
31dbe5b4 2260void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2261{
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
ad68076e 2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2273 }
2274}
2275
2276/**
31dbe5b4 2277 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2278 * @adapter: address of board private structure
2279 *
31dbe5b4 2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
31dbe5b4 2286void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2287{
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
ad68076e 2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2299 }
2300}
2301
bc7f75fa 2302/**
49ce9c2c 2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2304 **/
2305static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2306 struct e1000_ring *ring)
2307{
2308 struct pci_dev *pdev = adapter->pdev;
2309
2310 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2311 GFP_KERNEL);
2312 if (!ring->desc)
2313 return -ENOMEM;
2314
2315 return 0;
2316}
2317
2318/**
2319 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2320 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2321 *
2322 * Return 0 on success, negative on failure
2323 **/
55aa6985 2324int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2325{
55aa6985 2326 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2327 int err = -ENOMEM, size;
2328
2329 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2330 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2331 if (!tx_ring->buffer_info)
2332 goto err;
bc7f75fa
AK		 2333
2334 /* round up to nearest 4K */
2335 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2336 tx_ring->size = ALIGN(tx_ring->size, 4096);
2337
2338 err = e1000_alloc_ring_dma(adapter, tx_ring);
2339 if (err)
2340 goto err;
2341
2342 tx_ring->next_to_use = 0;
2343 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2344
2345 return 0;
2346err:
2347 vfree(tx_ring->buffer_info);
44defeb3 2348 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2349 return err;
2350}
2351
2352/**
2353 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2354 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2355 *
2356 * Returns 0 on success, negative on failure
2357 **/
55aa6985 2358int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2359{
55aa6985 2360 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2361 struct e1000_buffer *buffer_info;
2362 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2363
2364 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2365 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2366 if (!rx_ring->buffer_info)
2367 goto err;
bc7f75fa 2368
47f44e40
AK		 2369 for (i = 0; i < rx_ring->count; i++) {
2370 buffer_info = &rx_ring->buffer_info[i];
2371 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2372 sizeof(struct e1000_ps_page),
2373 GFP_KERNEL);
2374 if (!buffer_info->ps_pages)
2375 goto err_pages;
2376 }
bc7f75fa
AK		 2377
2378 desc_len = sizeof(union e1000_rx_desc_packet_split);
2379
2380 /* Round up to nearest 4K */
2381 rx_ring->size = rx_ring->count * desc_len;
2382 rx_ring->size = ALIGN(rx_ring->size, 4096);
2383
2384 err = e1000_alloc_ring_dma(adapter, rx_ring);
2385 if (err)
47f44e40 2386 goto err_pages;
bc7f75fa
AK		 2387
2388 rx_ring->next_to_clean = 0;
2389 rx_ring->next_to_use = 0;
2390 rx_ring->rx_skb_top = NULL;
2391
2392 return 0;
47f44e40
AK		 2393
2394err_pages:
2395 for (i = 0; i < rx_ring->count; i++) {
2396 buffer_info = &rx_ring->buffer_info[i];
2397 kfree(buffer_info->ps_pages);
2398 }
bc7f75fa
AK		 2399err:
2400 vfree(rx_ring->buffer_info);
e9262447 2401 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2402 return err;
2403}
2404
2405/**
2406 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2407 * @tx_ring: Tx descriptor ring
bc7f75fa 2408 **/
55aa6985 2409static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2410{
55aa6985 2411 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2412 struct e1000_buffer *buffer_info;
2413 unsigned long size;
2414 unsigned int i;
2415
2416 for (i = 0; i < tx_ring->count; i++) {
2417 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2418 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2419 }
2420
3f0cfa3b 2421 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2422 size = sizeof(struct e1000_buffer) * tx_ring->count;
2423 memset(tx_ring->buffer_info, 0, size);
2424
2425 memset(tx_ring->desc, 0, tx_ring->size);
2426
2427 tx_ring->next_to_use = 0;
2428 tx_ring->next_to_clean = 0;
2429
c5083cf6 2430 writel(0, tx_ring->head);
bdc125f7
BA		 2431 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2432 e1000e_update_tdt_wa(tx_ring, 0);
2433 else
2434 writel(0, tx_ring->tail);
bc7f75fa
AK		 2435}
2436
2437/**
2438 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2439 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2440 *
2441 * Free all transmit software resources
2442 **/
55aa6985 2443void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2444{
55aa6985 2445 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2446 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2447
55aa6985 2448 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2449
2450 vfree(tx_ring->buffer_info);
2451 tx_ring->buffer_info = NULL;
2452
2453 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2454 tx_ring->dma);
2455 tx_ring->desc = NULL;
2456}
2457
2458/**
2459 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2460 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2461 *
2462 * Free all receive software resources
2463 **/
55aa6985 2464void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2465{
55aa6985 2466 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2467 struct pci_dev *pdev = adapter->pdev;
47f44e40 2468 int i;
bc7f75fa 2469
55aa6985 2470 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2471
b1cdfead 2472 for (i = 0; i < rx_ring->count; i++)
47f44e40 2473 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2474
bc7f75fa
AK		 2475 vfree(rx_ring->buffer_info);
2476 rx_ring->buffer_info = NULL;
2477
bc7f75fa
AK		 2478 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2479 rx_ring->dma);
2480 rx_ring->desc = NULL;
2481}
2482
2483/**
2484 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2485 * @adapter: pointer to adapter
2486 * @itr_setting: current adapter->itr
2487 * @packets: the number of packets during this measurement interval
2488 * @bytes: the number of bytes during this measurement interval
2489 *
bc7f75fa
AK		 2490 * Stores a new ITR value based on packets and byte
2491 * counts during the last interrupt. The advantage of per interrupt
2492 * computation is faster updates and more accurate ITR for the current
2493 * traffic pattern. Constants in this function were computed
2494 * based on theoretical maximum wire speed and thresholds were set based
2495 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2496 * while increasing bulk throughput. This functionality is controlled
2497 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2498 **/
2499static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2500 u16 itr_setting, int packets,
2501 int bytes)
2502{
2503 unsigned int retval = itr_setting;
2504
2505 if (packets == 0)
5015e53a 2506 return itr_setting;
bc7f75fa
AK		 2507
2508 switch (itr_setting) {
2509 case lowest_latency:
2510 /* handle TSO and jumbo frames */
2511 if (bytes/packets > 8000)
2512 retval = bulk_latency;
b1cdfead 2513 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2514 retval = low_latency;
bc7f75fa
AK		 2515 break;
2516 case low_latency: /* 50 usec aka 20000 ints/s */
2517 if (bytes > 10000) {
2518 /* this if handles the TSO accounting */
b1cdfead 2519 if (bytes/packets > 8000)
bc7f75fa 2520 retval = bulk_latency;
b1cdfead 2521 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2522 retval = bulk_latency;
b1cdfead 2523 else if ((packets > 35))
bc7f75fa 2524 retval = lowest_latency;
bc7f75fa
AK		 2525 } else if (bytes/packets > 2000) {
2526 retval = bulk_latency;
2527 } else if (packets <= 2 && bytes < 512) {
2528 retval = lowest_latency;
2529 }
2530 break;
2531 case bulk_latency: /* 250 usec aka 4000 ints/s */
2532 if (bytes > 25000) {
b1cdfead 2533 if (packets > 35)
bc7f75fa 2534 retval = low_latency;
bc7f75fa
AK		 2535 } else if (bytes < 6000) {
2536 retval = low_latency;
2537 }
2538 break;
2539 }
2540
bc7f75fa
AK		 2541 return retval;
2542}
2543
2544static void e1000_set_itr(struct e1000_adapter *adapter)
2545{
bc7f75fa
AK		 2546 u16 current_itr;
2547 u32 new_itr = adapter->itr;
2548
2549 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2550 if (adapter->link_speed != SPEED_1000) {
2551 current_itr = 0;
2552 new_itr = 4000;
2553 goto set_itr_now;
2554 }
2555
828bac87
BA		 2556 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2557 new_itr = 0;
2558 goto set_itr_now;
2559 }
2560
bc7f75fa
AK		 2561 adapter->tx_itr = e1000_update_itr(adapter,
2562 adapter->tx_itr,
2563 adapter->total_tx_packets,
2564 adapter->total_tx_bytes);
2565 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2566 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2567 adapter->tx_itr = low_latency;
2568
2569 adapter->rx_itr = e1000_update_itr(adapter,
2570 adapter->rx_itr,
2571 adapter->total_rx_packets,
2572 adapter->total_rx_bytes);
2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2574 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2575 adapter->rx_itr = low_latency;
2576
2577 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2578
2579 switch (current_itr) {
2580 /* counts and packets in update_itr are dependent on these numbers */
2581 case lowest_latency:
2582 new_itr = 70000;
2583 break;
2584 case low_latency:
2585 new_itr = 20000; /* aka hwitr = ~200 */
2586 break;
2587 case bulk_latency:
2588 new_itr = 4000;
2589 break;
2590 default:
2591 break;
2592 }
2593
2594set_itr_now:
2595 if (new_itr != adapter->itr) {
e921eb1a 2596 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2597 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2598 * increasing
2599 */
bc7f75fa
AK		 2600 new_itr = new_itr > adapter->itr ?
2601 min(adapter->itr + (new_itr >> 2), new_itr) :
2602 new_itr;
2603 adapter->itr = new_itr;
4662e82b
BA		 2604 adapter->rx_ring->itr_val = new_itr;
2605 if (adapter->msix_entries)
2606 adapter->rx_ring->set_itr = 1;
2607 else
e3d14b08 2608 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2609 }
2610}
2611
22a4cca2
MV		 2612/**
2613 * e1000e_write_itr - write the ITR value to the appropriate registers
2614 * @adapter: address of board private structure
2615 * @itr: new ITR value to program
2616 *
2617 * e1000e_write_itr determines if the adapter is in MSI-X mode
2618 * and, if so, writes the EITR registers with the ITR value.
2619 * Otherwise, it writes the ITR value into the ITR register.
2620 **/
2621void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2622{
2623 struct e1000_hw *hw = &adapter->hw;
2624 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2625
2626 if (adapter->msix_entries) {
2627 int vector;
2628
2629 for (vector = 0; vector < adapter->num_vectors; vector++)
2630 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2631 } else {
2632 ew32(ITR, new_itr);
2633 }
2634}
2635
4662e82b
BA		 2636/**
2637 * e1000_alloc_queues - Allocate memory for all rings
2638 * @adapter: board private structure to initialize
2639 **/
9f9a12f8 2640static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2641{
55aa6985
BA		 2642 int size = sizeof(struct e1000_ring);
2643
2644 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2645 if (!adapter->tx_ring)
2646 goto err;
55aa6985
BA		 2647 adapter->tx_ring->count = adapter->tx_ring_count;
2648 adapter->tx_ring->adapter = adapter;
4662e82b 2649
55aa6985 2650 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2651 if (!adapter->rx_ring)
2652 goto err;
55aa6985
BA		 2653 adapter->rx_ring->count = adapter->rx_ring_count;
2654 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2655
2656 return 0;
2657err:
2658 e_err("Unable to allocate memory for queues\n");
2659 kfree(adapter->rx_ring);
2660 kfree(adapter->tx_ring);
2661 return -ENOMEM;
2662}
2663
bc7f75fa 2664/**
c58c8a78 2665 * e1000e_poll - NAPI Rx polling callback
ad68076e 2666 * @napi: struct associated with this polling callback
c58c8a78 2667 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2668 **/
c58c8a78 2669static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2670{
c58c8a78
BA		 2671 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2672 napi);
4662e82b 2673 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2674 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2675 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2676
4cf1653a 2677 adapter = netdev_priv(poll_dev);
bc7f75fa 2678
c58c8a78
BA		 2679 if (!adapter->msix_entries ||
2680 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2681 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2682
c58c8a78 2683 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2684
12d04a3c 2685 if (!tx_cleaned)
c58c8a78 2686 work_done = weight;
bc7f75fa 2687
c58c8a78
BA		 2688 /* If weight not fully consumed, exit the polling mode */
2689 if (work_done < weight) {
bc7f75fa
AK		 2690 if (adapter->itr_setting & 3)
2691 e1000_set_itr(adapter);
288379f0 2692 napi_complete(napi);
a3c69fef
JB		 2693 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2694 if (adapter->msix_entries)
2695 ew32(IMS, adapter->rx_ring->ims_val);
2696 else
2697 e1000_irq_enable(adapter);
2698 }
bc7f75fa
AK		 2699 }
2700
2701 return work_done;
2702}
2703
8e586137 2704static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2705{
2706 struct e1000_adapter *adapter = netdev_priv(netdev);
2707 struct e1000_hw *hw = &adapter->hw;
2708 u32 vfta, index;
2709
2710 /* don't update vlan cookie if already programmed */
2711 if ((adapter->hw.mng_cookie.status &
2712 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2713 (vid == adapter->mng_vlan_id))
8e586137 2714 return 0;
caaddaf8 2715
bc7f75fa 2716 /* add VID to filter table */
caaddaf8
BA		 2717 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2718 index = (vid >> 5) & 0x7F;
2719 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2720 vfta |= (1 << (vid & 0x1F));
2721 hw->mac.ops.write_vfta(hw, index, vfta);
2722 }
86d70e53
JK		 2723
2724 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2725
2726 return 0;
bc7f75fa
AK		 2727}
2728
8e586137 2729static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2730{
2731 struct e1000_adapter *adapter = netdev_priv(netdev);
2732 struct e1000_hw *hw = &adapter->hw;
2733 u32 vfta, index;
2734
bc7f75fa
AK		 2735 if ((adapter->hw.mng_cookie.status &
2736 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2737 (vid == adapter->mng_vlan_id)) {
2738 /* release control to f/w */
31dbe5b4 2739 e1000e_release_hw_control(adapter);
8e586137 2740 return 0;
bc7f75fa
AK		 2741 }
2742
2743 /* remove VID from filter table */
caaddaf8
BA		 2744 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2745 index = (vid >> 5) & 0x7F;
2746 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2747 vfta &= ~(1 << (vid & 0x1F));
2748 hw->mac.ops.write_vfta(hw, index, vfta);
2749 }
86d70e53
JK		 2750
2751 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2752
2753 return 0;
bc7f75fa
AK		 2754}
2755
86d70e53
JK		 2756/**
2757 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2758 * @adapter: board private structure to initialize
2759 **/
2760static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2761{
2762 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2763 struct e1000_hw *hw = &adapter->hw;
2764 u32 rctl;
bc7f75fa 2765
86d70e53
JK		 2766 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2767 /* disable VLAN receive filtering */
2768 rctl = er32(RCTL);
2769 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2770 ew32(RCTL, rctl);
2771
2772 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2773 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2774 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2775 }
bc7f75fa
AK		 2776 }
2777}
2778
86d70e53
JK		 2779/**
2780 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2781 * @adapter: board private structure to initialize
2782 **/
2783static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2784{
2785 struct e1000_hw *hw = &adapter->hw;
2786 u32 rctl;
2787
2788 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2789 /* enable VLAN receive filtering */
2790 rctl = er32(RCTL);
2791 rctl |= E1000_RCTL_VFE;
2792 rctl &= ~E1000_RCTL_CFIEN;
2793 ew32(RCTL, rctl);
2794 }
2795}
bc7f75fa 2796
86d70e53
JK		 2797/**
2798 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2799 * @adapter: board private structure to initialize
2800 **/
2801static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2802{
bc7f75fa 2803 struct e1000_hw *hw = &adapter->hw;
86d70e53 2804 u32 ctrl;
bc7f75fa 2805
86d70e53
JK		 2806 /* disable VLAN tag insert/strip */
2807 ctrl = er32(CTRL);
2808 ctrl &= ~E1000_CTRL_VME;
2809 ew32(CTRL, ctrl);
2810}
bc7f75fa 2811
86d70e53
JK		 2812/**
2813 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2814 * @adapter: board private structure to initialize
2815 **/
2816static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2817{
2818 struct e1000_hw *hw = &adapter->hw;
2819 u32 ctrl;
bc7f75fa 2820
86d70e53
JK		 2821 /* enable VLAN tag insert/strip */
2822 ctrl = er32(CTRL);
2823 ctrl |= E1000_CTRL_VME;
2824 ew32(CTRL, ctrl);
2825}
bc7f75fa 2826
86d70e53
JK		 2827static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2828{
2829 struct net_device *netdev = adapter->netdev;
2830 u16 vid = adapter->hw.mng_cookie.vlan_id;
2831 u16 old_vid = adapter->mng_vlan_id;
2832
2833 if (adapter->hw.mng_cookie.status &
2834 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2835 e1000_vlan_rx_add_vid(netdev, vid);
2836 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2837 }
2838
86d70e53
JK		 2839 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2840 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2841}
2842
2843static void e1000_restore_vlan(struct e1000_adapter *adapter)
2844{
2845 u16 vid;
2846
86d70e53 2847 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2848
86d70e53 2849 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2850 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2851}
2852
cd791618 2853static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2854{
2855 struct e1000_hw *hw = &adapter->hw;
cd791618 2856 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2857
2858 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2859 return;
2860
2861 manc = er32(MANC);
2862
e921eb1a 2863 /* enable receiving management packets to the host. this will probably
bc7f75fa 2864 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2865 * the packets will be handled on SMBUS
2866 */
bc7f75fa
AK		 2867 manc |= E1000_MANC_EN_MNG2HOST;
2868 manc2h = er32(MANC2H);
cd791618
BA		 2869
2870 switch (hw->mac.type) {
2871 default:
2872 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2873 break;
2874 case e1000_82574:
2875 case e1000_82583:
e921eb1a 2876 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2877 * if so, enable it.
2878 */
2879 for (i = 0, j = 0; i < 8; i++) {
2880 mdef = er32(MDEF(i));
2881
2882 /* Ignore filters with anything other than IPMI ports */
3b21b508 2883 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2884 continue;
2885
2886 /* Enable this decision filter in MANC2H */
2887 if (mdef)
2888 manc2h |= (1 << i);
2889
2890 j |= mdef;
2891 }
2892
2893 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2894 break;
2895
2896 /* Create new decision filter in an empty filter */
2897 for (i = 0, j = 0; i < 8; i++)
2898 if (er32(MDEF(i)) == 0) {
2899 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2900 E1000_MDEF_PORT_664));
2901 manc2h |= (1 << 1);
2902 j++;
2903 break;
2904 }
2905
2906 if (!j)
2907 e_warn("Unable to create IPMI pass-through filter\n");
2908 break;
2909 }
2910
bc7f75fa
AK		 2911 ew32(MANC2H, manc2h);
2912 ew32(MANC, manc);
2913}
2914
2915/**
af667a29 2916 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2917 * @adapter: board private structure
2918 *
2919 * Configure the Tx unit of the MAC after a reset.
2920 **/
2921static void e1000_configure_tx(struct e1000_adapter *adapter)
2922{
2923 struct e1000_hw *hw = &adapter->hw;
2924 struct e1000_ring *tx_ring = adapter->tx_ring;
2925 u64 tdba;
c550b121 2926 u32 tdlen, tarc;
bc7f75fa
AK		 2927
2928 /* Setup the HW Tx Head and Tail descriptor pointers */
2929 tdba = tx_ring->dma;
2930 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2931 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2932 ew32(TDBAH(0), (tdba >> 32));
2933 ew32(TDLEN(0), tdlen);
2934 ew32(TDH(0), 0);
2935 ew32(TDT(0), 0);
2936 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2937 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2938
bc7f75fa
AK		 2939 /* Set the Tx Interrupt Delay register */
2940 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2941 /* Tx irq moderation */
bc7f75fa
AK		 2942 ew32(TADV, adapter->tx_abs_int_delay);
2943
3a3b7586
JB		 2944 if (adapter->flags2 & FLAG2_DMA_BURST) {
2945 u32 txdctl = er32(TXDCTL(0));
2946 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2947 E1000_TXDCTL_WTHRESH);
e921eb1a 2948 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2949 * hardware to use the bus more efficiently in bursts, depends
2950 * on the tx_int_delay to be enabled,
8edc0e62 2951 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2952 * hthresh = 1 ==> prefetch when one or more available
2953 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2954 * BEWARE: this seems to work but should be considered first if
af667a29 2955 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2956 */
2957 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2958 ew32(TXDCTL(0), txdctl);
3a3b7586 2959 }
56032be7
BA		 2960 /* erratum work around: set txdctl the same for both queues */
2961 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2962
bc7f75fa 2963 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2964 tarc = er32(TARC(0));
e921eb1a 2965 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2966 * gigabit link later
2967 */
bc7f75fa
AK		 2968#define SPEED_MODE_BIT (1 << 21)
2969 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2970 ew32(TARC(0), tarc);
bc7f75fa
AK		 2971 }
2972
2973 /* errata: program both queues to unweighted RR */
2974 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2975 tarc = er32(TARC(0));
bc7f75fa 2976 tarc |= 1;
e9ec2c0f
JK		 2977 ew32(TARC(0), tarc);
2978 tarc = er32(TARC(1));
bc7f75fa 2979 tarc |= 1;
e9ec2c0f 2980 ew32(TARC(1), tarc);
bc7f75fa
AK		 2981 }
2982
bc7f75fa
AK		 2983 /* Setup Transmit Descriptor Settings for eop descriptor */
2984 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2985
2986 /* only set IDE if we are delaying interrupts using the timers */
2987 if (adapter->tx_int_delay)
2988 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2989
2990 /* enable Report Status bit */
2991 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2992
57cde763 2993 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2994}
2995
2996/**
2997 * e1000_setup_rctl - configure the receive control registers
2998 * @adapter: Board private structure
2999 **/
3000#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3001 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3002static void e1000_setup_rctl(struct e1000_adapter *adapter)
3003{
3004 struct e1000_hw *hw = &adapter->hw;
3005 u32 rctl, rfctl;
bc7f75fa
AK		 3006 u32 pages = 0;
3007
2fbe4526
BA		 3008 /* Workaround Si errata on PCHx - configure jumbo frame flow */
3009 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 3010 s32 ret_val;
3011
3012 if (adapter->netdev->mtu > ETH_DATA_LEN)
3013 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3014 else
3015 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 3016
3017 if (ret_val)
3018 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 3019 }
3020
bc7f75fa
AK		 3021 /* Program MC offset vector base */
3022 rctl = er32(RCTL);
3023 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3024 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3025 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3026 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3027
3028 /* Do not Store bad packets */
3029 rctl &= ~E1000_RCTL_SBP;
3030
3031 /* Enable Long Packet receive */
3032 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3033 rctl &= ~E1000_RCTL_LPE;
3034 else
3035 rctl |= E1000_RCTL_LPE;
3036
eb7c3adb
JK		 3037 /* Some systems expect that the CRC is included in SMBUS traffic. The
3038 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3039 * host memory when this is enabled
3040 */
3041 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3042 rctl |= E1000_RCTL_SECRC;
5918bd88 3043
a4f58f54
BA		 3044 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3045 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3046 u16 phy_data;
3047
3048 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3049 phy_data &= 0xfff8;
3050 phy_data |= (1 << 2);
3051 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3052
3053 e1e_rphy(hw, 22, &phy_data);
3054 phy_data &= 0x0fff;
3055 phy_data |= (1 << 14);
3056 e1e_wphy(hw, 0x10, 0x2823);
3057 e1e_wphy(hw, 0x11, 0x0003);
3058 e1e_wphy(hw, 22, phy_data);
3059 }
3060
bc7f75fa
AK		 3061 /* Setup buffer sizes */
3062 rctl &= ~E1000_RCTL_SZ_4096;
3063 rctl |= E1000_RCTL_BSEX;
3064 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3065 case 2048:
3066 default:
3067 rctl |= E1000_RCTL_SZ_2048;
3068 rctl &= ~E1000_RCTL_BSEX;
3069 break;
3070 case 4096:
3071 rctl |= E1000_RCTL_SZ_4096;
3072 break;
3073 case 8192:
3074 rctl |= E1000_RCTL_SZ_8192;
3075 break;
3076 case 16384:
3077 rctl |= E1000_RCTL_SZ_16384;
3078 break;
3079 }
3080
5f450212
BA		 3081 /* Enable Extended Status in all Receive Descriptors */
3082 rfctl = er32(RFCTL);
3083 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3084 ew32(RFCTL, rfctl);
5f450212 3085
e921eb1a 3086 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3087 * header is placed in skb->data and the packet data is
3088 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3089 * In the case of a non-split, skb->data is linearly filled,
3090 * followed by the page buffers. Therefore, skb->data is
3091 * sized to hold the largest protocol header.
3092 *
3093 * allocations using alloc_page take too long for regular MTU
3094 * so only enable packet split for jumbo frames
3095 *
3096 * Using pages when the page size is greater than 16k wastes
3097 * a lot of memory, since we allocate 3 pages at all times
3098 * per packet.
3099 */
bc7f75fa 3100 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3101 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3102 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3103 else
3104 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3105
3106 if (adapter->rx_ps_pages) {
90da0669
BA		 3107 u32 psrctl = 0;
3108
140a7480
AK		 3109 /* Enable Packet split descriptors */
3110 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 3111
3112 psrctl |= adapter->rx_ps_bsize0 >>
3113 E1000_PSRCTL_BSIZE0_SHIFT;
3114
3115 switch (adapter->rx_ps_pages) {
3116 case 3:
3117 psrctl |= PAGE_SIZE <<
3118 E1000_PSRCTL_BSIZE3_SHIFT;
3119 case 2:
3120 psrctl |= PAGE_SIZE <<
3121 E1000_PSRCTL_BSIZE2_SHIFT;
3122 case 1:
3123 psrctl |= PAGE_SIZE >>
3124 E1000_PSRCTL_BSIZE1_SHIFT;
3125 break;
3126 }
3127
3128 ew32(PSRCTL, psrctl);
3129 }
3130
cf955e6c
BG		 3131 /* This is useful for sniffing bad packets. */
3132 if (adapter->netdev->features & NETIF_F_RXALL) {
3133 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3134 * in e1000e_set_rx_mode
3135 */
cf955e6c
BG		 3136 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3137 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3138 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3139
3140 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3141 E1000_RCTL_DPF | /* Allow filtered pause */
3142 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3143 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3144 * and that breaks VLANs.
3145 */
3146 }
3147
bc7f75fa 3148 ew32(RCTL, rctl);
318a94d6 3149 /* just started the receive unit, no need to restart */
12d43f7d 3150 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3151}
3152
3153/**
3154 * e1000_configure_rx - Configure Receive Unit after Reset
3155 * @adapter: board private structure
3156 *
3157 * Configure the Rx unit of the MAC after a reset.
3158 **/
3159static void e1000_configure_rx(struct e1000_adapter *adapter)
3160{
3161 struct e1000_hw *hw = &adapter->hw;
3162 struct e1000_ring *rx_ring = adapter->rx_ring;
3163 u64 rdba;
3164 u32 rdlen, rctl, rxcsum, ctrl_ext;
3165
3166 if (adapter->rx_ps_pages) {
3167 /* this is a 32 byte descriptor */
3168 rdlen = rx_ring->count *
af667a29 3169 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3170 adapter->clean_rx = e1000_clean_rx_irq_ps;
3171 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3172 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3173 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3174 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3175 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3176 } else {
5f450212 3177 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3178 adapter->clean_rx = e1000_clean_rx_irq;
3179 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3180 }
3181
3182 /* disable receives while setting up the descriptors */
3183 rctl = er32(RCTL);
7f99ae63
BA		 3184 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3185 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3186 e1e_flush();
1bba4386 3187 usleep_range(10000, 20000);
bc7f75fa 3188
3a3b7586 3189 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3190 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3191 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3192 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3193 * granularity = 01
3194 * wthresh = 04,
3195 * hthresh = 04,
3196 * pthresh = 0x20
3197 */
3198 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3199 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3200
e921eb1a 3201 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3202 * the value was not set by the user via module options
3203 */
3204 if (adapter->rx_int_delay == DEFAULT_RDTR)
3205 adapter->rx_int_delay = BURST_RDTR;
3206 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3207 adapter->rx_abs_int_delay = BURST_RADV;
3208 }
3209
bc7f75fa
AK		 3210 /* set the Receive Delay Timer Register */
3211 ew32(RDTR, adapter->rx_int_delay);
3212
3213 /* irq moderation */
3214 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3215 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3216 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3217
3218 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3219 /* Auto-Mask interrupts upon ICR access */
3220 ctrl_ext |= E1000_CTRL_EXT_IAME;
3221 ew32(IAM, 0xffffffff);
3222 ew32(CTRL_EXT, ctrl_ext);
3223 e1e_flush();
3224
e921eb1a 3225 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3226 * the Base and Length of the Rx Descriptor Ring
3227 */
bc7f75fa 3228 rdba = rx_ring->dma;
1e36052e
BA		 3229 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3230 ew32(RDBAH(0), (rdba >> 32));
3231 ew32(RDLEN(0), rdlen);
3232 ew32(RDH(0), 0);
3233 ew32(RDT(0), 0);
3234 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3235 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3236
3237 /* Enable Receive Checksum Offload for TCP and UDP */
3238 rxcsum = er32(RXCSUM);
2e1706f2 3239 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3240 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3241 else
bc7f75fa 3242 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3243 ew32(RXCSUM, rxcsum);
3244
79d4e908 3245 if (adapter->hw.mac.type == e1000_pch2lan) {
e921eb1a 3246 /* With jumbo frames, excessive C-state transition
79d4e908
BA		 3247 * latencies result in dropped transactions.
3248 */
53ec5498
BA		 3249 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3250 u32 rxdctl = er32(RXDCTL(0));
3251 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3252 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3253 } else {
af667a29
BA		 3254 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3255 PM_QOS_DEFAULT_VALUE);
53ec5498 3256 }
97ac8cae 3257 }
bc7f75fa
AK		 3258
3259 /* Enable Receives */
3260 ew32(RCTL, rctl);
3261}
3262
3263/**
ef9b965a
JB		 3264 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3265 * @netdev: network interface device structure
bc7f75fa 3266 *
ef9b965a
JB		 3267 * Writes multicast address list to the MTA hash table.
3268 * Returns: -ENOMEM on failure
3269 * 0 on no addresses written
3270 * X on writing X addresses to MTA
3271 */
3272static int e1000e_write_mc_addr_list(struct net_device *netdev)
3273{
3274 struct e1000_adapter *adapter = netdev_priv(netdev);
3275 struct e1000_hw *hw = &adapter->hw;
3276 struct netdev_hw_addr *ha;
3277 u8 *mta_list;
3278 int i;
3279
3280 if (netdev_mc_empty(netdev)) {
3281 /* nothing to program, so clear mc list */
3282 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3283 return 0;
3284 }
3285
3286 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3287 if (!mta_list)
3288 return -ENOMEM;
3289
3290 /* update_mc_addr_list expects a packed array of only addresses. */
3291 i = 0;
3292 netdev_for_each_mc_addr(ha, netdev)
3293 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3294
3295 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3296 kfree(mta_list);
3297
3298 return netdev_mc_count(netdev);
3299}
3300
3301/**
3302 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3303 * @netdev: network interface device structure
bc7f75fa 3304 *
ef9b965a
JB		 3305 * Writes unicast address list to the RAR table.
3306 * Returns: -ENOMEM on failure/insufficient address space
3307 * 0 on no addresses written
3308 * X on writing X addresses to the RAR table
bc7f75fa 3309 **/
ef9b965a 3310static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3311{
ef9b965a
JB		 3312 struct e1000_adapter *adapter = netdev_priv(netdev);
3313 struct e1000_hw *hw = &adapter->hw;
3314 unsigned int rar_entries = hw->mac.rar_entry_count;
3315 int count = 0;
3316
3317 /* save a rar entry for our hardware address */
3318 rar_entries--;
3319
3320 /* save a rar entry for the LAA workaround */
3321 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3322 rar_entries--;
3323
3324 /* return ENOMEM indicating insufficient memory for addresses */
3325 if (netdev_uc_count(netdev) > rar_entries)
3326 return -ENOMEM;
3327
3328 if (!netdev_uc_empty(netdev) && rar_entries) {
3329 struct netdev_hw_addr *ha;
3330
e921eb1a 3331 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3332 * combining
3333 */
3334 netdev_for_each_uc_addr(ha, netdev) {
3335 if (!rar_entries)
3336 break;
69e1e019 3337 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3338 count++;
3339 }
3340 }
3341
3342 /* zero out the remaining RAR entries not used above */
3343 for (; rar_entries > 0; rar_entries--) {
3344 ew32(RAH(rar_entries), 0);
3345 ew32(RAL(rar_entries), 0);
3346 }
3347 e1e_flush();
3348
3349 return count;
bc7f75fa
AK		 3350}
3351
3352/**
ef9b965a 3353 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3354 * @netdev: network interface device structure
3355 *
ef9b965a
JB		 3356 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3357 * address list or the network interface flags are updated. This routine is
3358 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3359 * promiscuous mode, and all-multi behavior.
3360 **/
ef9b965a 3361static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3362{
3363 struct e1000_adapter *adapter = netdev_priv(netdev);
3364 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3365 u32 rctl;
bc7f75fa
AK		 3366
3367 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3368 rctl = er32(RCTL);
3369
ef9b965a
JB		 3370 /* clear the affected bits */
3371 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3372
bc7f75fa
AK		 3373 if (netdev->flags & IFF_PROMISC) {
3374 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3375 /* Do not hardware filter VLANs in promisc mode */
3376 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3377 } else {
ef9b965a 3378 int count;
3d3a1676 3379
746b9f02
PM		 3380 if (netdev->flags & IFF_ALLMULTI) {
3381 rctl |= E1000_RCTL_MPE;
746b9f02 3382 } else {
e921eb1a 3383 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3384 * then we should just turn on promiscuous mode so
3385 * that we can at least receive multicast traffic
3386 */
3387 count = e1000e_write_mc_addr_list(netdev);
3388 if (count < 0)
3389 rctl |= E1000_RCTL_MPE;
746b9f02 3390 }
86d70e53 3391 e1000e_vlan_filter_enable(adapter);
e921eb1a 3392 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3393 * sufficient space to store all the addresses then enable
3394 * unicast promiscuous mode
bc7f75fa 3395 */
ef9b965a
JB		 3396 count = e1000e_write_uc_addr_list(netdev);
3397 if (count < 0)
3398 rctl |= E1000_RCTL_UPE;
bc7f75fa 3399 }
86d70e53 3400
ef9b965a
JB		 3401 ew32(RCTL, rctl);
3402
86d70e53
JK		 3403 if (netdev->features & NETIF_F_HW_VLAN_RX)
3404 e1000e_vlan_strip_enable(adapter);
3405 else
3406 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3407}
3408
70495a50
BA		 3409static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3410{
3411 struct e1000_hw *hw = &adapter->hw;
3412 u32 mrqc, rxcsum;
3413 int i;
3414 static const u32 rsskey[10] = {
3415 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3416 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3417 };
3418
3419 /* Fill out hash function seed */
3420 for (i = 0; i < 10; i++)
3421 ew32(RSSRK(i), rsskey[i]);
3422
3423 /* Direct all traffic to queue 0 */
3424 for (i = 0; i < 32; i++)
3425 ew32(RETA(i), 0);
3426
e921eb1a 3427 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3428 * descriptor on writeback.
3429 */
3430 rxcsum = er32(RXCSUM);
3431 rxcsum |= E1000_RXCSUM_PCSD;
3432
3433 ew32(RXCSUM, rxcsum);
3434
3435 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3436 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3437 E1000_MRQC_RSS_FIELD_IPV6 |
3438 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3439 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3440
3441 ew32(MRQC, mrqc);
3442}
3443
b67e1913
BA		 3444/**
3445 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3446 * @adapter: board private structure
3447 * @timinca: pointer to returned time increment attributes
3448 *
3449 * Get attributes for incrementing the System Time Register SYSTIML/H at
3450 * the default base frequency, and set the cyclecounter shift value.
3451 **/
d89777bf 3452s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3453{
3454 struct e1000_hw *hw = &adapter->hw;
3455 u32 incvalue, incperiod, shift;
3456
3457 /* Make sure clock is enabled on I217 before checking the frequency */
3458 if ((hw->mac.type == e1000_pch_lpt) &&
3459 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3460 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3461 u32 fextnvm7 = er32(FEXTNVM7);
3462
3463 if (!(fextnvm7 & (1 << 0))) {
3464 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3465 e1e_flush();
3466 }
3467 }
3468
3469 switch (hw->mac.type) {
3470 case e1000_pch2lan:
3471 case e1000_pch_lpt:
3472 /* On I217, the clock frequency is 25MHz or 96MHz as
3473 * indicated by the System Clock Frequency Indication
3474 */
3475 if ((hw->mac.type != e1000_pch_lpt) ||
3476 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3477 /* Stable 96MHz frequency */
3478 incperiod = INCPERIOD_96MHz;
3479 incvalue = INCVALUE_96MHz;
3480 shift = INCVALUE_SHIFT_96MHz;
3481 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3482 break;
3483 }
3484 /* fall-through */
3485 case e1000_82574:
3486 case e1000_82583:
3487 /* Stable 25MHz frequency */
3488 incperiod = INCPERIOD_25MHz;
3489 incvalue = INCVALUE_25MHz;
3490 shift = INCVALUE_SHIFT_25MHz;
3491 adapter->cc.shift = shift;
3492 break;
3493 default:
3494 return -EINVAL;
3495 }
3496
3497 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3498 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3499
3500 return 0;
3501}
3502
3503/**
3504 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3505 * @adapter: board private structure
3506 *
3507 * Outgoing time stamping can be enabled and disabled. Play nice and
3508 * disable it when requested, although it shouldn't cause any overhead
3509 * when no packet needs it. At most one packet in the queue may be
3510 * marked for time stamping, otherwise it would be impossible to tell
3511 * for sure to which packet the hardware time stamp belongs.
3512 *
3513 * Incoming time stamping has to be configured via the hardware filters.
3514 * Not all combinations are supported, in particular event type has to be
3515 * specified. Matching the kind of event packet is not supported, with the
3516 * exception of "all V2 events regardless of level 2 or 4".
3517 **/
3518static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3519{
3520 struct e1000_hw *hw = &adapter->hw;
3521 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3522 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3523 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3524 u32 rxmtrl = 0;
3525 u16 rxudp = 0;
3526 bool is_l4 = false;
3527 bool is_l2 = false;
b67e1913
BA		 3528 u32 regval;
3529 s32 ret_val;
3530
3531 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3532 return -EINVAL;
3533
3534 /* flags reserved for future extensions - must be zero */
3535 if (config->flags)
3536 return -EINVAL;
3537
3538 switch (config->tx_type) {
3539 case HWTSTAMP_TX_OFF:
3540 tsync_tx_ctl = 0;
3541 break;
3542 case HWTSTAMP_TX_ON:
3543 break;
3544 default:
3545 return -ERANGE;
3546 }
3547
3548 switch (config->rx_filter) {
3549 case HWTSTAMP_FILTER_NONE:
3550 tsync_rx_ctl = 0;
3551 break;
d89777bf
BA		 3552 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3553 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3554 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3555 is_l4 = true;
3556 break;
3557 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3558 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3559 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3560 is_l4 = true;
3561 break;
3562 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3563 /* Also time stamps V2 L2 Path Delay Request/Response */
3564 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3565 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3566 is_l2 = true;
3567 break;
3568 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3569 /* Also time stamps V2 L2 Path Delay Request/Response. */
3570 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3571 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3572 is_l2 = true;
3573 break;
3574 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3575 /* Hardware cannot filter just V2 L4 Sync messages;
3576 * fall-through to V2 (both L2 and L4) Sync.
3577 */
3578 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3579 /* Also time stamps V2 Path Delay Request/Response. */
3580 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3581 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3582 is_l2 = true;
3583 is_l4 = true;
3584 break;
3585 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3586 /* Hardware cannot filter just V2 L4 Delay Request messages;
3587 * fall-through to V2 (both L2 and L4) Delay Request.
3588 */
3589 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3590 /* Also time stamps V2 Path Delay Request/Response. */
3591 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3592 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3593 is_l2 = true;
3594 is_l4 = true;
3595 break;
3596 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3597 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3598 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3599 * fall-through to all V2 (both L2 and L4) Events.
3600 */
3601 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3602 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3603 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3604 is_l2 = true;
3605 is_l4 = true;
3606 break;
3607 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3608 /* For V1, the hardware can only filter Sync messages or
3609 * Delay Request messages but not both so fall-through to
3610 * time stamp all packets.
3611 */
b67e1913 3612 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3613 is_l2 = true;
3614 is_l4 = true;
b67e1913
BA		 3615 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3616 config->rx_filter = HWTSTAMP_FILTER_ALL;
3617 break;
3618 default:
3619 return -ERANGE;
3620 }
3621
3622 /* enable/disable Tx h/w time stamping */
3623 regval = er32(TSYNCTXCTL);
3624 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3625 regval |= tsync_tx_ctl;
3626 ew32(TSYNCTXCTL, regval);
3627 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3628 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3629 e_err("Timesync Tx Control register not set as expected\n");
3630 return -EAGAIN;
3631 }
3632
3633 /* enable/disable Rx h/w time stamping */
3634 regval = er32(TSYNCRXCTL);
3635 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3636 regval |= tsync_rx_ctl;
3637 ew32(TSYNCRXCTL, regval);
3638 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3639 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3640 (regval & (E1000_TSYNCRXCTL_ENABLED |
3641 E1000_TSYNCRXCTL_TYPE_MASK))) {
3642 e_err("Timesync Rx Control register not set as expected\n");
3643 return -EAGAIN;
3644 }
3645
d89777bf
BA		 3646 /* L2: define ethertype filter for time stamped packets */
3647 if (is_l2)
3648 rxmtrl |= ETH_P_1588;
3649
3650 /* define which PTP packets get time stamped */
3651 ew32(RXMTRL, rxmtrl);
3652
3653 /* Filter by destination port */
3654 if (is_l4) {
3655 rxudp = PTP_EV_PORT;
3656 cpu_to_be16s(&rxudp);
3657 }
3658 ew32(RXUDP, rxudp);
3659
3660 e1e_flush();
3661
b67e1913
BA		 3662 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3663 regval = er32(RXSTMPH);
3664 regval = er32(TXSTMPH);
3665
3666 /* Get and set the System Time Register SYSTIM base frequency */
3667 ret_val = e1000e_get_base_timinca(adapter, &regval);
3668 if (ret_val)
3669 return ret_val;
3670 ew32(TIMINCA, regval);
3671
3672 /* reset the ns time counter */
3673 timecounter_init(&adapter->tc, &adapter->cc,
3674 ktime_to_ns(ktime_get_real()));
3675
3676 return 0;
3677}
3678
bc7f75fa 3679/**
ad68076e 3680 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3681 * @adapter: private board structure
3682 **/
3683static void e1000_configure(struct e1000_adapter *adapter)
3684{
55aa6985
BA		 3685 struct e1000_ring *rx_ring = adapter->rx_ring;
3686
ef9b965a 3687 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3688
3689 e1000_restore_vlan(adapter);
cd791618 3690 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3691
3692 e1000_configure_tx(adapter);
70495a50
BA		 3693
3694 if (adapter->netdev->features & NETIF_F_RXHASH)
3695 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3696 e1000_setup_rctl(adapter);
3697 e1000_configure_rx(adapter);
55aa6985 3698 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3699}
3700
3701/**
3702 * e1000e_power_up_phy - restore link in case the phy was powered down
3703 * @adapter: address of board private structure
3704 *
3705 * The phy may be powered down to save power and turn off link when the
3706 * driver is unloaded and wake on lan is not enabled (among others)
3707 * *** this routine MUST be followed by a call to e1000e_reset ***
3708 **/
3709void e1000e_power_up_phy(struct e1000_adapter *adapter)
3710{
17f208de
BA		 3711 if (adapter->hw.phy.ops.power_up)
3712 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3713
3714 adapter->hw.mac.ops.setup_link(&adapter->hw);
3715}
3716
3717/**
3718 * e1000_power_down_phy - Power down the PHY
3719 *
17f208de
BA		 3720 * Power down the PHY so no link is implied when interface is down.
3721 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3722 */
3723static void e1000_power_down_phy(struct e1000_adapter *adapter)
3724{
bc7f75fa 3725 /* WoL is enabled */
23b66e2b 3726 if (adapter->wol)
bc7f75fa
AK		 3727 return;
3728
17f208de
BA		 3729 if (adapter->hw.phy.ops.power_down)
3730 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3731}
3732
3733/**
3734 * e1000e_reset - bring the hardware into a known good state
3735 *
3736 * This function boots the hardware and enables some settings that
3737 * require a configuration cycle of the hardware - those cannot be
3738 * set/changed during runtime. After reset the device needs to be
ad68076e 3739 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3740 */
3741void e1000e_reset(struct e1000_adapter *adapter)
3742{
3743 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3744 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3745 struct e1000_hw *hw = &adapter->hw;
3746 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3747 u32 pba = adapter->pba;
bc7f75fa
AK		 3748 u16 hwm;
3749
ad68076e 3750 /* reset Packet Buffer Allocation to default */
318a94d6 3751 ew32(PBA, pba);
df762464 3752
318a94d6 3753 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3754 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3755 * large enough to accommodate two full transmit packets,
3756 * rounded up to the next 1KB and expressed in KB. Likewise,
3757 * the Rx FIFO should be large enough to accommodate at least
3758 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3759 * expressed in KB.
3760 */
df762464 3761 pba = er32(PBA);
bc7f75fa 3762 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3763 tx_space = pba >> 16;
bc7f75fa 3764 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3765 pba &= 0xffff;
e921eb1a 3766 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3767 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3768 */
3769 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3770 sizeof(struct e1000_tx_desc) -
3771 ETH_FCS_LEN) * 2;
3772 min_tx_space = ALIGN(min_tx_space, 1024);
3773 min_tx_space >>= 10;
3774 /* software strips receive CRC, so leave room for it */
318a94d6 3775 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3776 min_rx_space = ALIGN(min_rx_space, 1024);
3777 min_rx_space >>= 10;
3778
e921eb1a 3779 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3780 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3781 * allocation, take space away from current Rx allocation
3782 */
df762464
AK		 3783 if ((tx_space < min_tx_space) &&
3784 ((min_tx_space - tx_space) < pba)) {
3785 pba -= min_tx_space - tx_space;
bc7f75fa 3786
e921eb1a 3787 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3788 * adjustment
ad68076e 3789 */
79d4e908 3790 if (pba < min_rx_space)
df762464 3791 pba = min_rx_space;
bc7f75fa 3792 }
df762464
AK		 3793
3794 ew32(PBA, pba);
bc7f75fa
AK		 3795 }
3796
e921eb1a 3797 /* flow control settings
ad68076e 3798 *
38eb394e 3799 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3800 * (or the size used for early receive) above it in the Rx FIFO.
3801 * Set it to the lower of:
3802 * - 90% of the Rx FIFO size, and
38eb394e 3803 * - the full Rx FIFO size minus one full frame
ad68076e 3804 */
d3738bb8
BA		 3805 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3806 fc->pause_time = 0xFFFF;
3807 else
3808 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3809 fc->send_xon = true;
d3738bb8
BA		 3810 fc->current_mode = fc->requested_mode;
3811
3812 switch (hw->mac.type) {
79d4e908
BA		 3813 case e1000_ich9lan:
3814 case e1000_ich10lan:
3815 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3816 pba = 14;
3817 ew32(PBA, pba);
3818 fc->high_water = 0x2800;
3819 fc->low_water = fc->high_water - 8;
3820 break;
3821 }
3822 /* fall-through */
d3738bb8 3823 default:
79d4e908
BA		 3824 hwm = min(((pba << 10) * 9 / 10),
3825 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3826
3827 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3828 fc->low_water = fc->high_water - 8;
3829 break;
3830 case e1000_pchlan:
e921eb1a 3831 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3832 * loads. If hangs persist, try disabling Tx flow control.
3833 */
3834 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3835 fc->high_water = 0x3500;
3836 fc->low_water = 0x1500;
3837 } else {
3838 fc->high_water = 0x5000;
3839 fc->low_water = 0x3000;
3840 }
a305595b 3841 fc->refresh_time = 0x1000;
d3738bb8
BA		 3842 break;
3843 case e1000_pch2lan:
2fbe4526 3844 case e1000_pch_lpt:
d3738bb8 3845 fc->refresh_time = 0x0400;
347b5201
BA		 3846
3847 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3848 fc->high_water = 0x05C20;
3849 fc->low_water = 0x05048;
3850 fc->pause_time = 0x0650;
3851 break;
828bac87 3852 }
347b5201
BA		 3853
3854 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3855 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3856 break;
38eb394e 3857 }
bc7f75fa 3858
e921eb1a 3859 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3860 * maximum size per Tx descriptor limited only to the transmit
3861 * allocation of the packet buffer minus 96 bytes with an upper
3862 * limit of 24KB due to receive synchronization limitations.
3863 */
3864 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3865 24 << 10);
3866
e921eb1a 3867 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3868 * fit in receive buffer.
828bac87
BA		 3869 */
3870 if (adapter->itr_setting & 0x3) {
79d4e908 3871 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3872 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3873 dev_info(&adapter->pdev->dev,
3874 "Interrupt Throttle Rate turned off\n");
3875 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3876 e1000e_write_itr(adapter, 0);
828bac87
BA		 3877 }
3878 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3879 dev_info(&adapter->pdev->dev,
3880 "Interrupt Throttle Rate turned on\n");
3881 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3882 adapter->itr = 20000;
22a4cca2 3883 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3884 }
3885 }
3886
bc7f75fa
AK		 3887 /* Allow time for pending master requests to run */
3888 mac->ops.reset_hw(hw);
97ac8cae 3889
e921eb1a 3890 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3891 * that the network interface is in control
3892 */
c43bc57e 3893 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3894 e1000e_get_hw_control(adapter);
97ac8cae 3895
bc7f75fa
AK		 3896 ew32(WUC, 0);
3897
3898 if (mac->ops.init_hw(hw))
44defeb3 3899 e_err("Hardware Error\n");
bc7f75fa
AK		 3900
3901 e1000_update_mng_vlan(adapter);
3902
3903 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3904 ew32(VET, ETH_P_8021Q);
3905
3906 e1000e_reset_adaptive(hw);
31dbe5b4 3907
b67e1913
BA		 3908 /* initialize systim and reset the ns time counter */
3909 e1000e_config_hwtstamp(adapter);
3910
31dbe5b4
BA		 3911 if (!netif_running(adapter->netdev) &&
3912 !test_bit(__E1000_TESTING, &adapter->state)) {
3913 e1000_power_down_phy(adapter);
3914 return;
3915 }
3916
bc7f75fa
AK		 3917 e1000_get_phy_info(hw);
3918
918d7197
BA		 3919 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3920 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3921 u16 phy_data = 0;
e921eb1a 3922 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3923 * the return value of this function because there is nothing
ad68076e
BA		 3924 * different we would do if it failed
3925 */
bc7f75fa
AK		 3926 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3927 phy_data &= ~IGP02E1000_PM_SPD;
3928 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3929 }
bc7f75fa
AK		 3930}
3931
3932int e1000e_up(struct e1000_adapter *adapter)
3933{
3934 struct e1000_hw *hw = &adapter->hw;
3935
3936 /* hardware has been reset, we need to reload some things */
3937 e1000_configure(adapter);
3938
3939 clear_bit(__E1000_DOWN, &adapter->state);
3940
4662e82b
BA		 3941 if (adapter->msix_entries)
3942 e1000_configure_msix(adapter);
bc7f75fa
AK		 3943 e1000_irq_enable(adapter);
3944
400484fa 3945 netif_start_queue(adapter->netdev);
4cb9be7a 3946
bc7f75fa 3947 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3948 if (adapter->msix_entries)
3949 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3950 else
3951 ew32(ICS, E1000_ICS_LSC);
3952
bc7f75fa
AK		 3953 return 0;
3954}
3955
713b3c9e
JB		 3956static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3957{
3958 struct e1000_hw *hw = &adapter->hw;
3959
3960 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3961 return;
3962
3963 /* flush pending descriptor writebacks to memory */
3964 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3965 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3966
3967 /* execute the writes immediately */
3968 e1e_flush();
bf03085f 3969
e921eb1a 3970 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3971 * write is successful
3972 */
3973 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3974 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3975
3976 /* execute the writes immediately */
3977 e1e_flush();
3978}
3979
67fd4fcb
JK		 3980static void e1000e_update_stats(struct e1000_adapter *adapter);
3981
bc7f75fa
AK		 3982void e1000e_down(struct e1000_adapter *adapter)
3983{
3984 struct net_device *netdev = adapter->netdev;
3985 struct e1000_hw *hw = &adapter->hw;
3986 u32 tctl, rctl;
3987
e921eb1a 3988 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3989 * reschedule our watchdog timer
3990 */
bc7f75fa
AK		 3991 set_bit(__E1000_DOWN, &adapter->state);
3992
3993 /* disable receives in the hardware */
3994 rctl = er32(RCTL);
7f99ae63
BA		 3995 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3996 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3997 /* flush and sleep below */
3998
4cb9be7a 3999 netif_stop_queue(netdev);
bc7f75fa
AK		 4000
4001 /* disable transmits in the hardware */
4002 tctl = er32(TCTL);
4003 tctl &= ~E1000_TCTL_EN;
4004 ew32(TCTL, tctl);
7f99ae63 4005
bc7f75fa
AK		 4006 /* flush both disables and wait for them to finish */
4007 e1e_flush();
1bba4386 4008 usleep_range(10000, 20000);
bc7f75fa 4009
bc7f75fa
AK		 4010 e1000_irq_disable(adapter);
4011
4012 del_timer_sync(&adapter->watchdog_timer);
4013 del_timer_sync(&adapter->phy_info_timer);
4014
bc7f75fa 4015 netif_carrier_off(netdev);
67fd4fcb
JK		 4016
4017 spin_lock(&adapter->stats64_lock);
4018 e1000e_update_stats(adapter);
4019 spin_unlock(&adapter->stats64_lock);
4020
400484fa 4021 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4022 e1000_clean_tx_ring(adapter->tx_ring);
4023 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4024
bc7f75fa
AK		 4025 adapter->link_speed = 0;
4026 adapter->link_duplex = 0;
4027
52cc3086
JK		 4028 if (!pci_channel_offline(adapter->pdev))
4029 e1000e_reset(adapter);
713b3c9e 4030
e921eb1a 4031 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 4032 * pci_disable_device here.
4033 */
4034}
4035
4036void e1000e_reinit_locked(struct e1000_adapter *adapter)
4037{
4038 might_sleep();
4039 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4040 usleep_range(1000, 2000);
bc7f75fa
AK		 4041 e1000e_down(adapter);
4042 e1000e_up(adapter);
4043 clear_bit(__E1000_RESETTING, &adapter->state);
4044}
4045
b67e1913
BA		 4046/**
4047 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4048 * @cc: cyclecounter structure
4049 **/
4050static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4051{
4052 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4053 cc);
4054 struct e1000_hw *hw = &adapter->hw;
4055 cycle_t systim;
4056
4057 /* latch SYSTIMH on read of SYSTIML */
4058 systim = (cycle_t)er32(SYSTIML);
4059 systim |= (cycle_t)er32(SYSTIMH) << 32;
4060
4061 return systim;
4062}
4063
bc7f75fa
AK		 4064/**
4065 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4066 * @adapter: board private structure to initialize
4067 *
4068 * e1000_sw_init initializes the Adapter private data structure.
4069 * Fields are initialized based on PCI device information and
4070 * OS network device settings (MTU size).
4071 **/
9f9a12f8 4072static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4073{
bc7f75fa
AK		 4074 struct net_device *netdev = adapter->netdev;
4075
4076 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4077 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4078 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4079 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4080 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4081 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4082
67fd4fcb
JK		 4083 spin_lock_init(&adapter->stats64_lock);
4084
4662e82b 4085 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4086
4662e82b
BA		 4087 if (e1000_alloc_queues(adapter))
4088 return -ENOMEM;
bc7f75fa 4089
b67e1913
BA		 4090 /* Setup hardware time stamping cyclecounter */
4091 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4092 adapter->cc.read = e1000e_cyclecounter_read;
4093 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4094 adapter->cc.mult = 1;
4095 /* cc.shift set in e1000e_get_base_tininca() */
4096
4097 spin_lock_init(&adapter->systim_lock);
4098 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4099 }
4100
bc7f75fa 4101 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4102 e1000_irq_disable(adapter);
4103
bc7f75fa
AK		 4104 set_bit(__E1000_DOWN, &adapter->state);
4105 return 0;
bc7f75fa
AK		 4106}
4107
f8d59f78
BA		 4108/**
4109 * e1000_intr_msi_test - Interrupt Handler
4110 * @irq: interrupt number
4111 * @data: pointer to a network interface device structure
4112 **/
4113static irqreturn_t e1000_intr_msi_test(int irq, void *data)
4114{
4115 struct net_device *netdev = data;
4116 struct e1000_adapter *adapter = netdev_priv(netdev);
4117 struct e1000_hw *hw = &adapter->hw;
4118 u32 icr = er32(ICR);
4119
3bb99fe2 4120 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4121 if (icr & E1000_ICR_RXSEQ) {
4122 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4123 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4124 * interrupt is handled.
4125 */
f8d59f78
BA		 4126 wmb();
4127 }
4128
4129 return IRQ_HANDLED;
4130}
4131
4132/**
4133 * e1000_test_msi_interrupt - Returns 0 for successful test
4134 * @adapter: board private struct
4135 *
4136 * code flow taken from tg3.c
4137 **/
4138static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4139{
4140 struct net_device *netdev = adapter->netdev;
4141 struct e1000_hw *hw = &adapter->hw;
4142 int err;
4143
4144 /* poll_enable hasn't been called yet, so don't need disable */
4145 /* clear any pending events */
4146 er32(ICR);
4147
4148 /* free the real vector and request a test handler */
4149 e1000_free_irq(adapter);
4662e82b 4150 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4151
4152 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4153 * MSI irq handler will unset this flag
4154 */
f8d59f78
BA		 4155 adapter->flags |= FLAG_MSI_TEST_FAILED;
4156
4157 err = pci_enable_msi(adapter->pdev);
4158 if (err)
4159 goto msi_test_failed;
4160
a0607fd3 4161 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4162 netdev->name, netdev);
4163 if (err) {
4164 pci_disable_msi(adapter->pdev);
4165 goto msi_test_failed;
4166 }
4167
e921eb1a 4168 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4169 * interrupt.
4170 */
f8d59f78
BA		 4171 wmb();
4172
4173 e1000_irq_enable(adapter);
4174
4175 /* fire an unusual interrupt on the test handler */
4176 ew32(ICS, E1000_ICS_RXSEQ);
4177 e1e_flush();
569a3aff 4178 msleep(100);
f8d59f78
BA		 4179
4180 e1000_irq_disable(adapter);
4181
bc76329d 4182 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4183
4184 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4185 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4186 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4187 } else {
068e8a30 4188 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4189 }
f8d59f78
BA		 4190
4191 free_irq(adapter->pdev->irq, netdev);
4192 pci_disable_msi(adapter->pdev);
4193
f8d59f78 4194msi_test_failed:
4662e82b 4195 e1000e_set_interrupt_capability(adapter);
068e8a30 4196 return e1000_request_irq(adapter);
f8d59f78
BA		 4197}
4198
4199/**
4200 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4201 * @adapter: board private struct
4202 *
4203 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4204 **/
4205static int e1000_test_msi(struct e1000_adapter *adapter)
4206{
4207 int err;
4208 u16 pci_cmd;
4209
4210 if (!(adapter->flags & FLAG_MSI_ENABLED))
4211 return 0;
4212
4213 /* disable SERR in case the MSI write causes a master abort */
4214 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4215 if (pci_cmd & PCI_COMMAND_SERR)
4216 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4217 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4218
4219 err = e1000_test_msi_interrupt(adapter);
4220
36f2407f
DN		 4221 /* re-enable SERR */
4222 if (pci_cmd & PCI_COMMAND_SERR) {
4223 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4224 pci_cmd |= PCI_COMMAND_SERR;
4225 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4226 }
f8d59f78 4227
f8d59f78
BA		 4228 return err;
4229}
4230
bc7f75fa
AK		 4231/**
4232 * e1000_open - Called when a network interface is made active
4233 * @netdev: network interface device structure
4234 *
4235 * Returns 0 on success, negative value on failure
4236 *
4237 * The open entry point is called when a network interface is made
4238 * active by the system (IFF_UP). At this point all resources needed
4239 * for transmit and receive operations are allocated, the interrupt
4240 * handler is registered with the OS, the watchdog timer is started,
4241 * and the stack is notified that the interface is ready.
4242 **/
4243static int e1000_open(struct net_device *netdev)
4244{
4245 struct e1000_adapter *adapter = netdev_priv(netdev);
4246 struct e1000_hw *hw = &adapter->hw;
23606cf5 4247 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4248 int err;
4249
4250 /* disallow open during test */
4251 if (test_bit(__E1000_TESTING, &adapter->state))
4252 return -EBUSY;
4253
23606cf5
RW		 4254 pm_runtime_get_sync(&pdev->dev);
4255
9c563d20
JB		 4256 netif_carrier_off(netdev);
4257
bc7f75fa 4258 /* allocate transmit descriptors */
55aa6985 4259 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4260 if (err)
4261 goto err_setup_tx;
4262
4263 /* allocate receive descriptors */
55aa6985 4264 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4265 if (err)
4266 goto err_setup_rx;
4267
e921eb1a 4268 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4269 * interface is now open and reset the part to a known state.
4270 */
4271 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4272 e1000e_get_hw_control(adapter);
11b08be8
BA		 4273 e1000e_reset(adapter);
4274 }
4275
bc7f75fa
AK		 4276 e1000e_power_up_phy(adapter);
4277
4278 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4279 if ((adapter->hw.mng_cookie.status &
4280 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4281 e1000_update_mng_vlan(adapter);
4282
79d4e908
BA		 4283 /* DMA latency requirement to workaround jumbo issue */
4284 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 4285 pm_qos_add_request(&adapter->netdev->pm_qos_req,
4286 PM_QOS_CPU_DMA_LATENCY,
4287 PM_QOS_DEFAULT_VALUE);
c128ec29 4288
e921eb1a 4289 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4290 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4291 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4292 * clean_rx handler before we do so.
4293 */
bc7f75fa
AK		 4294 e1000_configure(adapter);
4295
4296 err = e1000_request_irq(adapter);
4297 if (err)
4298 goto err_req_irq;
4299
e921eb1a 4300 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4301 * ignore e1000e MSI messages, which means we need to test our MSI
4302 * interrupt now
4303 */
4662e82b 4304 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4305 err = e1000_test_msi(adapter);
4306 if (err) {
4307 e_err("Interrupt allocation failed\n");
4308 goto err_req_irq;
4309 }
4310 }
4311
bc7f75fa
AK		 4312 /* From here on the code is the same as e1000e_up() */
4313 clear_bit(__E1000_DOWN, &adapter->state);
4314
4315 napi_enable(&adapter->napi);
4316
4317 e1000_irq_enable(adapter);
4318
09357b00 4319 adapter->tx_hang_recheck = false;
4cb9be7a 4320 netif_start_queue(netdev);
d55b53ff 4321
23606cf5
RW		 4322 adapter->idle_check = true;
4323 pm_runtime_put(&pdev->dev);
4324
bc7f75fa 4325 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4326 if (adapter->msix_entries)
4327 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4328 else
4329 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4330
4331 return 0;
4332
4333err_req_irq:
31dbe5b4 4334 e1000e_release_hw_control(adapter);
bc7f75fa 4335 e1000_power_down_phy(adapter);
55aa6985 4336 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4337err_setup_rx:
55aa6985 4338 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4339err_setup_tx:
4340 e1000e_reset(adapter);
23606cf5 4341 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4342
4343 return err;
4344}
4345
4346/**
4347 * e1000_close - Disables a network interface
4348 * @netdev: network interface device structure
4349 *
4350 * Returns 0, this is not allowed to fail
4351 *
4352 * The close entry point is called when an interface is de-activated
4353 * by the OS. The hardware is still under the drivers control, but
4354 * needs to be disabled. A global MAC reset is issued to stop the
4355 * hardware, and all transmit and receive resources are freed.
4356 **/
4357static int e1000_close(struct net_device *netdev)
4358{
4359 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4360 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4361 int count = E1000_CHECK_RESET_COUNT;
4362
4363 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4364 usleep_range(10000, 20000);
bc7f75fa
AK		 4365
4366 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4367
4368 pm_runtime_get_sync(&pdev->dev);
4369
5f4a780d
BA		 4370 napi_disable(&adapter->napi);
4371
23606cf5
RW		 4372 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4373 e1000e_down(adapter);
4374 e1000_free_irq(adapter);
4375 }
bc7f75fa 4376 e1000_power_down_phy(adapter);
bc7f75fa 4377
55aa6985
BA		 4378 e1000e_free_tx_resources(adapter->tx_ring);
4379 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4380
e921eb1a 4381 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4382 * the same ID is registered on the host OS (let 8021q kill it)
4383 */
86d70e53
JK		 4384 if (adapter->hw.mng_cookie.status &
4385 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4386 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4387
e921eb1a 4388 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4389 * interface is now closed
4390 */
31dbe5b4
BA		 4391 if ((adapter->flags & FLAG_HAS_AMT) &&
4392 !test_bit(__E1000_TESTING, &adapter->state))
4393 e1000e_release_hw_control(adapter);
bc7f75fa 4394
79d4e908 4395 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4396 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4397
23606cf5
RW		 4398 pm_runtime_put_sync(&pdev->dev);
4399
bc7f75fa
AK		 4400 return 0;
4401}
4402/**
4403 * e1000_set_mac - Change the Ethernet Address of the NIC
4404 * @netdev: network interface device structure
4405 * @p: pointer to an address structure
4406 *
4407 * Returns 0 on success, negative on failure
4408 **/
4409static int e1000_set_mac(struct net_device *netdev, void *p)
4410{
4411 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4412 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4413 struct sockaddr *addr = p;
4414
4415 if (!is_valid_ether_addr(addr->sa_data))
4416 return -EADDRNOTAVAIL;
4417
4418 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4419 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4420
69e1e019 4421 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4422
4423 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4424 /* activate the work around */
4425 e1000e_set_laa_state_82571(&adapter->hw, 1);
4426
e921eb1a 4427 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4428 * between the time RAR[0] gets clobbered and the time it
4429 * gets fixed (in e1000_watchdog), the actual LAA is in one
4430 * of the RARs and no incoming packets directed to this port
4431 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4432 * RAR[14]
4433 */
69e1e019
BA		 4434 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4435 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4436 }
4437
4438 return 0;
4439}
4440
a8f88ff5
JB		 4441/**
4442 * e1000e_update_phy_task - work thread to update phy
4443 * @work: pointer to our work struct
4444 *
4445 * this worker thread exists because we must acquire a
4446 * semaphore to read the phy, which we could msleep while
4447 * waiting for it, and we can't msleep in a timer.
4448 **/
4449static void e1000e_update_phy_task(struct work_struct *work)
4450{
4451 struct e1000_adapter *adapter = container_of(work,
4452 struct e1000_adapter, update_phy_task);
615b32af
JB		 4453
4454 if (test_bit(__E1000_DOWN, &adapter->state))
4455 return;
4456
a8f88ff5
JB		 4457 e1000_get_phy_info(&adapter->hw);
4458}
4459
e921eb1a
BA		 4460/**
4461 * e1000_update_phy_info - timre call-back to update PHY info
4462 * @data: pointer to adapter cast into an unsigned long
4463 *
ad68076e
BA		 4464 * Need to wait a few seconds after link up to get diagnostic information from
4465 * the phy
e921eb1a 4466 **/
bc7f75fa
AK		 4467static void e1000_update_phy_info(unsigned long data)
4468{
4469 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4470
4471 if (test_bit(__E1000_DOWN, &adapter->state))
4472 return;
4473
a8f88ff5 4474 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4475}
4476
8c7bbb92
BA		 4477/**
4478 * e1000e_update_phy_stats - Update the PHY statistics counters
4479 * @adapter: board private structure
2b6b168d
BA		 4480 *
4481 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4482 **/
4483static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4484{
4485 struct e1000_hw *hw = &adapter->hw;
4486 s32 ret_val;
4487 u16 phy_data;
4488
4489 ret_val = hw->phy.ops.acquire(hw);
4490 if (ret_val)
4491 return;
4492
e921eb1a 4493 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4494 * If not, set to the page with the PHY status registers.
4495 */
2b6b168d 4496 hw->phy.addr = 1;
8c7bbb92
BA		 4497 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4498 &phy_data);
4499 if (ret_val)
4500 goto release;
2b6b168d
BA		 4501 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4502 ret_val = hw->phy.ops.set_page(hw,
4503 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4504 if (ret_val)
4505 goto release;
4506 }
4507
8c7bbb92 4508 /* Single Collision Count */
2b6b168d
BA		 4509 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4510 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4511 if (!ret_val)
4512 adapter->stats.scc += phy_data;
4513
4514 /* Excessive Collision Count */
2b6b168d
BA		 4515 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4516 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4517 if (!ret_val)
4518 adapter->stats.ecol += phy_data;
4519
4520 /* Multiple Collision Count */
2b6b168d
BA		 4521 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4522 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4523 if (!ret_val)
4524 adapter->stats.mcc += phy_data;
4525
4526 /* Late Collision Count */
2b6b168d
BA		 4527 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4528 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4529 if (!ret_val)
4530 adapter->stats.latecol += phy_data;
4531
4532 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4533 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4534 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4535 if (!ret_val)
4536 hw->mac.collision_delta = phy_data;
4537
4538 /* Defer Count */
2b6b168d
BA		 4539 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4540 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4541 if (!ret_val)
4542 adapter->stats.dc += phy_data;
4543
4544 /* Transmit with no CRS */
2b6b168d
BA		 4545 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4546 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4547 if (!ret_val)
4548 adapter->stats.tncrs += phy_data;
4549
4550release:
4551 hw->phy.ops.release(hw);
4552}
4553
bc7f75fa
AK		 4554/**
4555 * e1000e_update_stats - Update the board statistics counters
4556 * @adapter: board private structure
4557 **/
67fd4fcb 4558static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4559{
7274c20f 4560 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4561 struct e1000_hw *hw = &adapter->hw;
4562 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4563
e921eb1a 4564 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4565 * connection is down.
4566 */
4567 if (adapter->link_speed == 0)
4568 return;
4569 if (pci_channel_offline(pdev))
4570 return;
4571
bc7f75fa
AK		 4572 adapter->stats.crcerrs += er32(CRCERRS);
4573 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4574 adapter->stats.gorc += er32(GORCL);
4575 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4576 adapter->stats.bprc += er32(BPRC);
4577 adapter->stats.mprc += er32(MPRC);
4578 adapter->stats.roc += er32(ROC);
4579
bc7f75fa 4580 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4581
4582 /* Half-duplex statistics */
4583 if (adapter->link_duplex == HALF_DUPLEX) {
4584 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4585 e1000e_update_phy_stats(adapter);
4586 } else {
4587 adapter->stats.scc += er32(SCC);
4588 adapter->stats.ecol += er32(ECOL);
4589 adapter->stats.mcc += er32(MCC);
4590 adapter->stats.latecol += er32(LATECOL);
4591 adapter->stats.dc += er32(DC);
4592
4593 hw->mac.collision_delta = er32(COLC);
4594
4595 if ((hw->mac.type != e1000_82574) &&
4596 (hw->mac.type != e1000_82583))
4597 adapter->stats.tncrs += er32(TNCRS);
4598 }
4599 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4600 }
8c7bbb92 4601
bc7f75fa
AK		 4602 adapter->stats.xonrxc += er32(XONRXC);
4603 adapter->stats.xontxc += er32(XONTXC);
4604 adapter->stats.xoffrxc += er32(XOFFRXC);
4605 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4606 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4607 adapter->stats.gotc += er32(GOTCL);
4608 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4609 adapter->stats.rnbc += er32(RNBC);
4610 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4611
4612 adapter->stats.mptc += er32(MPTC);
4613 adapter->stats.bptc += er32(BPTC);
4614
4615 /* used for adaptive IFS */
4616
4617 hw->mac.tx_packet_delta = er32(TPT);
4618 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4619
4620 adapter->stats.algnerrc += er32(ALGNERRC);
4621 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4622 adapter->stats.cexterr += er32(CEXTERR);
4623 adapter->stats.tsctc += er32(TSCTC);
4624 adapter->stats.tsctfc += er32(TSCTFC);
4625
bc7f75fa 4626 /* Fill out the OS statistics structure */
7274c20f
AK		 4627 netdev->stats.multicast = adapter->stats.mprc;
4628 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4629
4630 /* Rx Errors */
4631
e921eb1a 4632 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4633 * our own version based on RUC and ROC
4634 */
7274c20f 4635 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4636 adapter->stats.crcerrs + adapter->stats.algnerrc +
4637 adapter->stats.ruc + adapter->stats.roc +
4638 adapter->stats.cexterr;
7274c20f 4639 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4640 adapter->stats.roc;
7274c20f
AK		 4641 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4642 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4643 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4644
4645 /* Tx Errors */
7274c20f 4646 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4647 adapter->stats.latecol;
7274c20f
AK		 4648 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4649 netdev->stats.tx_window_errors = adapter->stats.latecol;
4650 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4651
4652 /* Tx Dropped needs to be maintained elsewhere */
4653
bc7f75fa
AK		 4654 /* Management Stats */
4655 adapter->stats.mgptc += er32(MGTPTC);
4656 adapter->stats.mgprc += er32(MGTPRC);
4657 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4658
4659 /* Correctable ECC Errors */
4660 if (hw->mac.type == e1000_pch_lpt) {
4661 u32 pbeccsts = er32(PBECCSTS);
4662 adapter->corr_errors +=
4663 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4664 adapter->uncorr_errors +=
4665 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4666 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4667 }
bc7f75fa
AK		 4668}
4669
7c25769f
BA		 4670/**
4671 * e1000_phy_read_status - Update the PHY register status snapshot
4672 * @adapter: board private structure
4673 **/
4674static void e1000_phy_read_status(struct e1000_adapter *adapter)
4675{
4676 struct e1000_hw *hw = &adapter->hw;
4677 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4678
4679 if ((er32(STATUS) & E1000_STATUS_LU) &&
4680 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4681 int ret_val;
4682
7c25769f
BA		 4683 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4684 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4685 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4686 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4687 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4688 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4689 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4690 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4691 if (ret_val)
44defeb3 4692 e_warn("Error reading PHY register\n");
7c25769f 4693 } else {
e921eb1a 4694 /* Do not read PHY registers if link is not up
7c25769f
BA		 4695 * Set values to typical power-on defaults
4696 */
4697 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4698 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4699 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4700 BMSR_ERCAP);
4701 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4702 ADVERTISE_ALL | ADVERTISE_CSMA);
4703 phy->lpa = 0;
4704 phy->expansion = EXPANSION_ENABLENPAGE;
4705 phy->ctrl1000 = ADVERTISE_1000FULL;
4706 phy->stat1000 = 0;
4707 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4708 }
7c25769f
BA		 4709}
4710
bc7f75fa
AK		 4711static void e1000_print_link_info(struct e1000_adapter *adapter)
4712{
bc7f75fa
AK		 4713 struct e1000_hw *hw = &adapter->hw;
4714 u32 ctrl = er32(CTRL);
4715
8f12fe86 4716 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4717 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4718 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4719 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4720 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4721 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4722 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4723}
4724
0c6bdb30 4725static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4726{
4727 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4728 bool link_active = false;
318a94d6
JK		 4729 s32 ret_val = 0;
4730
e921eb1a 4731 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4732 * Rx sequence error interrupt. get_link_status will stay
4733 * false until the check_for_link establishes link
4734 * for copper adapters ONLY
4735 */
4736 switch (hw->phy.media_type) {
4737 case e1000_media_type_copper:
4738 if (hw->mac.get_link_status) {
4739 ret_val = hw->mac.ops.check_for_link(hw);
4740 link_active = !hw->mac.get_link_status;
4741 } else {
3db1cd5c 4742 link_active = true;
318a94d6
JK		 4743 }
4744 break;
4745 case e1000_media_type_fiber:
4746 ret_val = hw->mac.ops.check_for_link(hw);
4747 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4748 break;
4749 case e1000_media_type_internal_serdes:
4750 ret_val = hw->mac.ops.check_for_link(hw);
4751 link_active = adapter->hw.mac.serdes_has_link;
4752 break;
4753 default:
4754 case e1000_media_type_unknown:
4755 break;
4756 }
4757
4758 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4759 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4760 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4761 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4762 }
4763
4764 return link_active;
4765}
4766
4767static void e1000e_enable_receives(struct e1000_adapter *adapter)
4768{
4769 /* make sure the receive unit is started */
4770 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4771 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4772 struct e1000_hw *hw = &adapter->hw;
4773 u32 rctl = er32(RCTL);
4774 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4775 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4776 }
4777}
4778
ff10e13c
CW		 4779static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4780{
4781 struct e1000_hw *hw = &adapter->hw;
4782
e921eb1a 4783 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4784 * for hung state and reset, if two calls return true
4785 */
4786 if (e1000_check_phy_82574(hw))
4787 adapter->phy_hang_count++;
4788 else
4789 adapter->phy_hang_count = 0;
4790
4791 if (adapter->phy_hang_count > 1) {
4792 adapter->phy_hang_count = 0;
4793 schedule_work(&adapter->reset_task);
4794 }
4795}
4796
bc7f75fa
AK		 4797/**
4798 * e1000_watchdog - Timer Call-back
4799 * @data: pointer to adapter cast into an unsigned long
4800 **/
4801static void e1000_watchdog(unsigned long data)
4802{
4803 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4804
4805 /* Do the rest outside of interrupt context */
4806 schedule_work(&adapter->watchdog_task);
4807
4808 /* TODO: make this use queue_delayed_work() */
4809}
4810
4811static void e1000_watchdog_task(struct work_struct *work)
4812{
4813 struct e1000_adapter *adapter = container_of(work,
4814 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4815 struct net_device *netdev = adapter->netdev;
4816 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4817 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4818 struct e1000_ring *tx_ring = adapter->tx_ring;
4819 struct e1000_hw *hw = &adapter->hw;
4820 u32 link, tctl;
bc7f75fa 4821
615b32af
JB		 4822 if (test_bit(__E1000_DOWN, &adapter->state))
4823 return;
4824
b405e8df 4825 link = e1000e_has_link(adapter);
318a94d6 4826 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4827 /* Cancel scheduled suspend requests. */
4828 pm_runtime_resume(netdev->dev.parent);
4829
318a94d6 4830 e1000e_enable_receives(adapter);
bc7f75fa 4831 goto link_up;
bc7f75fa
AK		 4832 }
4833
4834 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4835 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4836 e1000_update_mng_vlan(adapter);
4837
bc7f75fa
AK		 4838 if (link) {
4839 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4840 bool txb2b = true;
23606cf5
RW		 4841
4842 /* Cancel scheduled suspend requests. */
4843 pm_runtime_resume(netdev->dev.parent);
4844
318a94d6 4845 /* update snapshot of PHY registers on LSC */
7c25769f 4846 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4847 mac->ops.get_link_up_info(&adapter->hw,
4848 &adapter->link_speed,
4849 &adapter->link_duplex);
4850 e1000_print_link_info(adapter);
e921eb1a 4851 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4852 * if link has autonegotiated at 10/100 half
4853 */
4854 if ((hw->phy.type == e1000_phy_igp_3 ||
4855 hw->phy.type == e1000_phy_bm) &&
4856 (hw->mac.autoneg == true) &&
4857 (adapter->link_speed == SPEED_10 ||
4858 adapter->link_speed == SPEED_100) &&
4859 (adapter->link_duplex == HALF_DUPLEX)) {
4860 u16 autoneg_exp;
4861
4862 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4863
4864 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4865 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4866 }
4867
f49c57e1 4868 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4869 adapter->tx_timeout_factor = 1;
4870 switch (adapter->link_speed) {
4871 case SPEED_10:
3db1cd5c 4872 txb2b = false;
10f1b492 4873 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4874 break;
4875 case SPEED_100:
3db1cd5c 4876 txb2b = false;
4c86e0b9 4877 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4878 break;
4879 }
4880
e921eb1a 4881 /* workaround: re-program speed mode bit after
ad68076e
BA		 4882 * link-up event
4883 */
bc7f75fa
AK		 4884 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4885 !txb2b) {
4886 u32 tarc0;
e9ec2c0f 4887 tarc0 = er32(TARC(0));
bc7f75fa 4888 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4889 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4890 }
4891
e921eb1a 4892 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4893 * some hardware issues
4894 */
bc7f75fa
AK		 4895 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4896 switch (adapter->link_speed) {
4897 case SPEED_10:
4898 case SPEED_100:
44defeb3 4899 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4900 netdev->features &= ~NETIF_F_TSO;
4901 netdev->features &= ~NETIF_F_TSO6;
4902 break;
4903 case SPEED_1000:
4904 netdev->features |= NETIF_F_TSO;
4905 netdev->features |= NETIF_F_TSO6;
4906 break;
4907 default:
4908 /* oops */
4909 break;
4910 }
4911 }
4912
e921eb1a 4913 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4914 * after setting TARC(0)
4915 */
bc7f75fa
AK		 4916 tctl = er32(TCTL);
4917 tctl |= E1000_TCTL_EN;
4918 ew32(TCTL, tctl);
4919
e921eb1a 4920 /* Perform any post-link-up configuration before
75eb0fad
BA		 4921 * reporting link up.
4922 */
4923 if (phy->ops.cfg_on_link_up)
4924 phy->ops.cfg_on_link_up(hw);
4925
bc7f75fa 4926 netif_carrier_on(netdev);
bc7f75fa
AK		 4927
4928 if (!test_bit(__E1000_DOWN, &adapter->state))
4929 mod_timer(&adapter->phy_info_timer,
4930 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4931 }
4932 } else {
4933 if (netif_carrier_ok(netdev)) {
4934 adapter->link_speed = 0;
4935 adapter->link_duplex = 0;
8f12fe86 4936 /* Link status message must follow this format */
7dbc1672 4937 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4938 netif_carrier_off(netdev);
bc7f75fa
AK		 4939 if (!test_bit(__E1000_DOWN, &adapter->state))
4940 mod_timer(&adapter->phy_info_timer,
4941 round_jiffies(jiffies + 2 * HZ));
4942
12d43f7d
BA		 4943 /* The link is lost so the controller stops DMA.
4944 * If there is queued Tx work that cannot be done
4945 * or if on an 8000ES2LAN which requires a Rx packet
4946 * buffer work-around on link down event, reset the
4947 * controller to flush the Tx/Rx packet buffers.
4948 * (Do the reset outside of interrupt context).
4949 */
4950 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4951 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4952 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4953 else
4954 pm_schedule_suspend(netdev->dev.parent,
4955 LINK_TIMEOUT);
bc7f75fa
AK		 4956 }
4957 }
4958
4959link_up:
67fd4fcb 4960 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4961 e1000e_update_stats(adapter);
4962
4963 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4964 adapter->tpt_old = adapter->stats.tpt;
4965 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4966 adapter->colc_old = adapter->stats.colc;
4967
7c25769f
BA		 4968 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4969 adapter->gorc_old = adapter->stats.gorc;
4970 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4971 adapter->gotc_old = adapter->stats.gotc;
2084b114 4972 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4973
12d43f7d 4974 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4975 schedule_work(&adapter->reset_task);
4976 /* return immediately since reset is imminent */
4977 return;
bc7f75fa
AK		 4978 }
4979
12d43f7d
BA		 4980 e1000e_update_adaptive(&adapter->hw);
4981
eab2abf5
JB		 4982 /* Simple mode for Interrupt Throttle Rate (ITR) */
4983 if (adapter->itr_setting == 4) {
e921eb1a 4984 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4985 * Total asymmetrical Tx or Rx gets ITR=8000;
4986 * everyone else is between 2000-8000.
4987 */
4988 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4989 u32 dif = (adapter->gotc > adapter->gorc ?
4990 adapter->gotc - adapter->gorc :
4991 adapter->gorc - adapter->gotc) / 10000;
4992 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4993
22a4cca2 4994 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4995 }
4996
ad68076e 4997 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4998 if (adapter->msix_entries)
4999 ew32(ICS, adapter->rx_ring->ims_val);
5000 else
5001 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5002
713b3c9e
JB		 5003 /* flush pending descriptors to memory before detecting Tx hang */
5004 e1000e_flush_descriptors(adapter);
5005
bc7f75fa 5006 /* Force detection of hung controller every watchdog period */
3db1cd5c 5007 adapter->detect_tx_hung = true;
bc7f75fa 5008
e921eb1a 5009 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5010 * reset from the other port. Set the appropriate LAA in RAR[0]
5011 */
bc7f75fa 5012 if (e1000e_get_laa_state_82571(hw))
69e1e019 5013 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5014
ff10e13c
CW		 5015 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5016 e1000e_check_82574_phy_workaround(adapter);
5017
b67e1913
BA		 5018 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5019 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5020 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5021 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5022 er32(RXSTMPH);
5023 adapter->rx_hwtstamp_cleared++;
5024 } else {
5025 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5026 }
5027 }
5028
bc7f75fa
AK		 5029 /* Reset the timer */
5030 if (!test_bit(__E1000_DOWN, &adapter->state))
5031 mod_timer(&adapter->watchdog_timer,
5032 round_jiffies(jiffies + 2 * HZ));
5033}
5034
5035#define E1000_TX_FLAGS_CSUM 0x00000001
5036#define E1000_TX_FLAGS_VLAN 0x00000002
5037#define E1000_TX_FLAGS_TSO 0x00000004
5038#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5039#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5040#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5041#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5042#define E1000_TX_FLAGS_VLAN_SHIFT 16
5043
55aa6985 5044static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5045{
bc7f75fa
AK		 5046 struct e1000_context_desc *context_desc;
5047 struct e1000_buffer *buffer_info;
5048 unsigned int i;
5049 u32 cmd_length = 0;
70443ae9 5050 u16 ipcse = 0, mss;
bc7f75fa 5051 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5052
3d5e33c9
BA		 5053 if (!skb_is_gso(skb))
5054 return 0;
bc7f75fa 5055
3d5e33c9 5056 if (skb_header_cloned(skb)) {
90da0669
BA		 5057 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5058
3d5e33c9
BA		 5059 if (err)
5060 return err;
bc7f75fa
AK		 5061 }
5062
3d5e33c9
BA		 5063 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5064 mss = skb_shinfo(skb)->gso_size;
5065 if (skb->protocol == htons(ETH_P_IP)) {
5066 struct iphdr *iph = ip_hdr(skb);
5067 iph->tot_len = 0;
5068 iph->check = 0;
5069 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5070 0, IPPROTO_TCP, 0);
5071 cmd_length = E1000_TXD_CMD_IP;
5072 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5073 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5074 ipv6_hdr(skb)->payload_len = 0;
5075 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5076 &ipv6_hdr(skb)->daddr,
5077 0, IPPROTO_TCP, 0);
5078 ipcse = 0;
5079 }
5080 ipcss = skb_network_offset(skb);
5081 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5082 tucss = skb_transport_offset(skb);
5083 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5084
5085 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5086 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5087
5088 i = tx_ring->next_to_use;
5089 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5090 buffer_info = &tx_ring->buffer_info[i];
5091
5092 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5093 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5094 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5095 context_desc->upper_setup.tcp_fields.tucss = tucss;
5096 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5097 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 5098 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5099 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5100 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5101
5102 buffer_info->time_stamp = jiffies;
5103 buffer_info->next_to_watch = i;
5104
5105 i++;
5106 if (i == tx_ring->count)
5107 i = 0;
5108 tx_ring->next_to_use = i;
5109
5110 return 1;
bc7f75fa
AK		 5111}
5112
55aa6985 5113static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5114{
55aa6985 5115 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5116 struct e1000_context_desc *context_desc;
5117 struct e1000_buffer *buffer_info;
5118 unsigned int i;
5119 u8 css;
af807c82 5120 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5121 __be16 protocol;
bc7f75fa 5122
af807c82
DG		 5123 if (skb->ip_summed != CHECKSUM_PARTIAL)
5124 return 0;
bc7f75fa 5125
5f66f208
AJ		 5126 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5127 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5128 else
5129 protocol = skb->protocol;
5130
3f518390 5131 switch (protocol) {
09640e63 5132 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5133 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5134 cmd_len |= E1000_TXD_CMD_TCP;
5135 break;
09640e63 5136 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5137 /* XXX not handling all IPV6 headers */
5138 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5139 cmd_len |= E1000_TXD_CMD_TCP;
5140 break;
5141 default:
5142 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5143 e_warn("checksum_partial proto=%x!\n",
5144 be16_to_cpu(protocol));
af807c82 5145 break;
bc7f75fa
AK		 5146 }
5147
0d0b1672 5148 css = skb_checksum_start_offset(skb);
af807c82
DG		 5149
5150 i = tx_ring->next_to_use;
5151 buffer_info = &tx_ring->buffer_info[i];
5152 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5153
5154 context_desc->lower_setup.ip_config = 0;
5155 context_desc->upper_setup.tcp_fields.tucss = css;
5156 context_desc->upper_setup.tcp_fields.tucso =
5157 css + skb->csum_offset;
5158 context_desc->upper_setup.tcp_fields.tucse = 0;
5159 context_desc->tcp_seg_setup.data = 0;
5160 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5161
5162 buffer_info->time_stamp = jiffies;
5163 buffer_info->next_to_watch = i;
5164
5165 i++;
5166 if (i == tx_ring->count)
5167 i = 0;
5168 tx_ring->next_to_use = i;
5169
5170 return 1;
bc7f75fa
AK		 5171}
5172
55aa6985
BA		 5173static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5174 unsigned int first, unsigned int max_per_txd,
d821a4c4 5175 unsigned int nr_frags)
bc7f75fa 5176{
55aa6985 5177 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5178 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5179 struct e1000_buffer *buffer_info;
8ddc951c 5180 unsigned int len = skb_headlen(skb);
03b1320d 5181 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5182 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5183
5184 i = tx_ring->next_to_use;
5185
5186 while (len) {
1b7719c4 5187 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5188 size = min(len, max_per_txd);
5189
bc7f75fa 5190 buffer_info->length = size;
bc7f75fa 5191 buffer_info->time_stamp = jiffies;
bc7f75fa 5192 buffer_info->next_to_watch = i;
0be3f55f
NN		 5193 buffer_info->dma = dma_map_single(&pdev->dev,
5194 skb->data + offset,
af667a29 5195 size, DMA_TO_DEVICE);
03b1320d 5196 buffer_info->mapped_as_page = false;
0be3f55f 5197 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5198 goto dma_error;
bc7f75fa
AK		 5199
5200 len -= size;
5201 offset += size;
03b1320d 5202 count++;
1b7719c4
AD		 5203
5204 if (len) {
5205 i++;
5206 if (i == tx_ring->count)
5207 i = 0;
5208 }
bc7f75fa
AK		 5209 }
5210
5211 for (f = 0; f < nr_frags; f++) {
9e903e08 5212 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5213
5214 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5215 len = skb_frag_size(frag);
877749bf 5216 offset = 0;
bc7f75fa
AK		 5217
5218 while (len) {
1b7719c4
AD		 5219 i++;
5220 if (i == tx_ring->count)
5221 i = 0;
5222
bc7f75fa
AK		 5223 buffer_info = &tx_ring->buffer_info[i];
5224 size = min(len, max_per_txd);
bc7f75fa
AK		 5225
5226 buffer_info->length = size;
5227 buffer_info->time_stamp = jiffies;
bc7f75fa 5228 buffer_info->next_to_watch = i;
877749bf
IC		 5229 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5230 offset, size, DMA_TO_DEVICE);
03b1320d 5231 buffer_info->mapped_as_page = true;
0be3f55f 5232 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5233 goto dma_error;
bc7f75fa
AK		 5234
5235 len -= size;
5236 offset += size;
5237 count++;
bc7f75fa
AK		 5238 }
5239 }
5240
af667a29 5241 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5242 /* multiply data chunks by size of headers */
5243 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5244
bc7f75fa 5245 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5246 tx_ring->buffer_info[i].segs = segs;
5247 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5248 tx_ring->buffer_info[first].next_to_watch = i;
5249
5250 return count;
03b1320d
AD		 5251
5252dma_error:
af667a29 5253 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5254 buffer_info->dma = 0;
c1fa347f 5255 if (count)
03b1320d 5256 count--;
c1fa347f
RK		 5257
5258 while (count--) {
af667a29 5259 if (i == 0)
03b1320d 5260 i += tx_ring->count;
c1fa347f 5261 i--;
03b1320d 5262 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5263 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5264 }
5265
5266 return 0;
bc7f75fa
AK		 5267}
5268
55aa6985 5269static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5270{
55aa6985 5271 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5272 struct e1000_tx_desc *tx_desc = NULL;
5273 struct e1000_buffer *buffer_info;
5274 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5275 unsigned int i;
5276
5277 if (tx_flags & E1000_TX_FLAGS_TSO) {
5278 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5279 E1000_TXD_CMD_TSE;
5280 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5281
5282 if (tx_flags & E1000_TX_FLAGS_IPV4)
5283 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5284 }
5285
5286 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5287 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5288 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5289 }
5290
5291 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5292 txd_lower |= E1000_TXD_CMD_VLE;
5293 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5294 }
5295
943146de
BG		 5296 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5297 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5298
b67e1913
BA		 5299 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5300 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5301 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5302 }
5303
bc7f75fa
AK		 5304 i = tx_ring->next_to_use;
5305
36b973df 5306 do {
bc7f75fa
AK		 5307 buffer_info = &tx_ring->buffer_info[i];
5308 tx_desc = E1000_TX_DESC(*tx_ring, i);
5309 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5310 tx_desc->lower.data =
5311 cpu_to_le32(txd_lower | buffer_info->length);
5312 tx_desc->upper.data = cpu_to_le32(txd_upper);
5313
5314 i++;
5315 if (i == tx_ring->count)
5316 i = 0;
36b973df 5317 } while (--count > 0);
bc7f75fa
AK		 5318
5319 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5320
943146de
BG		 5321 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5322 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5323 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5324
e921eb1a 5325 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5326 * know there are new descriptors to fetch. (Only
5327 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5328 * such as IA-64).
5329 */
bc7f75fa
AK		 5330 wmb();
5331
5332 tx_ring->next_to_use = i;
c6e7f51e
BA		 5333
5334 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5335 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5336 else
c5083cf6 5337 writel(i, tx_ring->tail);
c6e7f51e 5338
e921eb1a 5339 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5340 * at a time, it synchronizes IO on IA64/Altix systems
5341 */
bc7f75fa
AK		 5342 mmiowb();
5343}
5344
5345#define MINIMUM_DHCP_PACKET_SIZE 282
5346static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5347 struct sk_buff *skb)
5348{
5349 struct e1000_hw *hw = &adapter->hw;
5350 u16 length, offset;
5351
d60923c4
BA		 5352 if (vlan_tx_tag_present(skb) &&
5353 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5354 (adapter->hw.mng_cookie.status &
5355 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5356 return 0;
bc7f75fa
AK		 5357
5358 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5359 return 0;
5360
5361 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
5362 return 0;
5363
5364 {
5365 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
5366 struct udphdr *udp;
5367
5368 if (ip->protocol != IPPROTO_UDP)
5369 return 0;
5370
5371 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5372 if (ntohs(udp->dest) != 67)
5373 return 0;
5374
5375 offset = (u8 *)udp + 8 - skb->data;
5376 length = skb->len - offset;
5377 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5378 }
5379
5380 return 0;
5381}
5382
55aa6985 5383static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5384{
55aa6985 5385 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5386
55aa6985 5387 netif_stop_queue(adapter->netdev);
e921eb1a 5388 /* Herbert's original patch had:
bc7f75fa 5389 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5390 * but since that doesn't exist yet, just open code it.
5391 */
bc7f75fa
AK		 5392 smp_mb();
5393
e921eb1a 5394 /* We need to check again in a case another CPU has just
ad68076e
BA		 5395 * made room available.
5396 */
55aa6985 5397 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5398 return -EBUSY;
5399
5400 /* A reprieve! */
55aa6985 5401 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5402 ++adapter->restart_queue;
5403 return 0;
5404}
5405
55aa6985 5406static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5407{
d821a4c4
BA		 5408 BUG_ON(size > tx_ring->count);
5409
55aa6985 5410 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5411 return 0;
55aa6985 5412 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5413}
5414
3b29a56d
SH		 5415static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5416 struct net_device *netdev)
bc7f75fa
AK		 5417{
5418 struct e1000_adapter *adapter = netdev_priv(netdev);
5419 struct e1000_ring *tx_ring = adapter->tx_ring;
5420 unsigned int first;
bc7f75fa 5421 unsigned int tx_flags = 0;
e743d313 5422 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5423 unsigned int nr_frags;
5424 unsigned int mss;
bc7f75fa
AK		 5425 int count = 0;
5426 int tso;
5427 unsigned int f;
bc7f75fa
AK		 5428
5429 if (test_bit(__E1000_DOWN, &adapter->state)) {
5430 dev_kfree_skb_any(skb);
5431 return NETDEV_TX_OK;
5432 }
5433
5434 if (skb->len <= 0) {
5435 dev_kfree_skb_any(skb);
5436 return NETDEV_TX_OK;
5437 }
5438
e921eb1a 5439 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5440 * pad skb in order to meet this minimum size requirement
5441 */
5442 if (unlikely(skb->len < 17)) {
5443 if (skb_pad(skb, 17 - skb->len))
5444 return NETDEV_TX_OK;
5445 skb->len = 17;
5446 skb_set_tail_pointer(skb, 17);
5447 }
5448
bc7f75fa 5449 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5450 if (mss) {
5451 u8 hdr_len;
bc7f75fa 5452
e921eb1a 5453 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5454 * points to just header, pull a few bytes of payload from
5455 * frags into skb->data
5456 */
bc7f75fa 5457 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5458 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5459 * avoiding it could save a lot of cycles
5460 */
4e6c709c 5461 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5462 unsigned int pull_size;
5463
a2a5b323 5464 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5465 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5466 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5467 dev_kfree_skb_any(skb);
5468 return NETDEV_TX_OK;
5469 }
e743d313 5470 len = skb_headlen(skb);
bc7f75fa
AK		 5471 }
5472 }
5473
5474 /* reserve a descriptor for the offload context */
5475 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5476 count++;
5477 count++;
5478
d821a4c4 5479 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5480
5481 nr_frags = skb_shinfo(skb)->nr_frags;
5482 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5483 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5484 adapter->tx_fifo_limit);
bc7f75fa
AK		 5485
5486 if (adapter->hw.mac.tx_pkt_filtering)
5487 e1000_transfer_dhcp_info(adapter, skb);
5488
e921eb1a 5489 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5490 * head, otherwise try next time
5491 */
55aa6985 5492 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5493 return NETDEV_TX_BUSY;
bc7f75fa 5494
eab6d18d 5495 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5496 tx_flags |= E1000_TX_FLAGS_VLAN;
5497 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5498 }
5499
5500 first = tx_ring->next_to_use;
5501
55aa6985 5502 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5503 if (tso < 0) {
5504 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5505 return NETDEV_TX_OK;
5506 }
5507
5508 if (tso)
5509 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5510 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5511 tx_flags |= E1000_TX_FLAGS_CSUM;
5512
e921eb1a 5513 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5514 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5515 * no longer assume, we must.
5516 */
bc7f75fa
AK		 5517 if (skb->protocol == htons(ETH_P_IP))
5518 tx_flags |= E1000_TX_FLAGS_IPV4;
5519
943146de
BG		 5520 if (unlikely(skb->no_fcs))
5521 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5522
25985edc 5523 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5524 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5525 nr_frags);
1b7719c4 5526 if (count) {
b67e1913
BA		 5527 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5528 !adapter->tx_hwtstamp_skb)) {
5529 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5530 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5531 adapter->tx_hwtstamp_skb = skb_get(skb);
5532 schedule_work(&adapter->tx_hwtstamp_work);
5533 } else {
5534 skb_tx_timestamp(skb);
5535 }
80be3129 5536
3f0cfa3b 5537 netdev_sent_queue(netdev, skb->len);
55aa6985 5538 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5539 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5540 e1000_maybe_stop_tx(tx_ring,
5541 (MAX_SKB_FRAGS *
5542 DIV_ROUND_UP(PAGE_SIZE,
5543 adapter->tx_fifo_limit) + 2));
1b7719c4 5544 } else {
bc7f75fa 5545 dev_kfree_skb_any(skb);
1b7719c4
AD		 5546 tx_ring->buffer_info[first].time_stamp = 0;
5547 tx_ring->next_to_use = first;
bc7f75fa
AK		 5548 }
5549
bc7f75fa
AK		 5550 return NETDEV_TX_OK;
5551}
5552
5553/**
5554 * e1000_tx_timeout - Respond to a Tx Hang
5555 * @netdev: network interface device structure
5556 **/
5557static void e1000_tx_timeout(struct net_device *netdev)
5558{
5559 struct e1000_adapter *adapter = netdev_priv(netdev);
5560
5561 /* Do the reset outside of interrupt context */
5562 adapter->tx_timeout_count++;
5563 schedule_work(&adapter->reset_task);
5564}
5565
5566static void e1000_reset_task(struct work_struct *work)
5567{
5568 struct e1000_adapter *adapter;
5569 adapter = container_of(work, struct e1000_adapter, reset_task);
5570
615b32af
JB		 5571 /* don't run the task if already down */
5572 if (test_bit(__E1000_DOWN, &adapter->state))
5573 return;
5574
12d43f7d 5575 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5576 e1000e_dump(adapter);
12d43f7d 5577 e_err("Reset adapter unexpectedly\n");
affa9dfb 5578 }
bc7f75fa
AK		 5579 e1000e_reinit_locked(adapter);
5580}
5581
5582/**
67fd4fcb 5583 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5584 * @netdev: network interface device structure
67fd4fcb 5585 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5586 *
5587 * Returns the address of the device statistics structure.
bc7f75fa 5588 **/
67fd4fcb
JK		 5589struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5590 struct rtnl_link_stats64 *stats)
bc7f75fa 5591{
67fd4fcb
JK		 5592 struct e1000_adapter *adapter = netdev_priv(netdev);
5593
5594 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5595 spin_lock(&adapter->stats64_lock);
5596 e1000e_update_stats(adapter);
5597 /* Fill out the OS statistics structure */
5598 stats->rx_bytes = adapter->stats.gorc;
5599 stats->rx_packets = adapter->stats.gprc;
5600 stats->tx_bytes = adapter->stats.gotc;
5601 stats->tx_packets = adapter->stats.gptc;
5602 stats->multicast = adapter->stats.mprc;
5603 stats->collisions = adapter->stats.colc;
5604
5605 /* Rx Errors */
5606
e921eb1a 5607 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5608 * our own version based on RUC and ROC
5609 */
5610 stats->rx_errors = adapter->stats.rxerrc +
5611 adapter->stats.crcerrs + adapter->stats.algnerrc +
5612 adapter->stats.ruc + adapter->stats.roc +
5613 adapter->stats.cexterr;
5614 stats->rx_length_errors = adapter->stats.ruc +
5615 adapter->stats.roc;
5616 stats->rx_crc_errors = adapter->stats.crcerrs;
5617 stats->rx_frame_errors = adapter->stats.algnerrc;
5618 stats->rx_missed_errors = adapter->stats.mpc;
5619
5620 /* Tx Errors */
5621 stats->tx_errors = adapter->stats.ecol +
5622 adapter->stats.latecol;
5623 stats->tx_aborted_errors = adapter->stats.ecol;
5624 stats->tx_window_errors = adapter->stats.latecol;
5625 stats->tx_carrier_errors = adapter->stats.tncrs;
5626
5627 /* Tx Dropped needs to be maintained elsewhere */
5628
5629 spin_unlock(&adapter->stats64_lock);
5630 return stats;
bc7f75fa
AK		 5631}
5632
5633/**
5634 * e1000_change_mtu - Change the Maximum Transfer Unit
5635 * @netdev: network interface device structure
5636 * @new_mtu: new value for maximum frame size
5637 *
5638 * Returns 0 on success, negative on failure
5639 **/
5640static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5641{
5642 struct e1000_adapter *adapter = netdev_priv(netdev);
5643 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5644
2adc55c9 5645 /* Jumbo frame support */
2e1706f2
BA		 5646 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5647 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5648 e_err("Jumbo Frames not supported.\n");
5649 return -EINVAL;
bc7f75fa
AK		 5650 }
5651
2adc55c9
BA		 5652 /* Supported frame sizes */
5653 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5654 (max_frame > adapter->max_hw_frame_size)) {
5655 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5656 return -EINVAL;
5657 }
5658
2fbe4526
BA		 5659 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5660 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5661 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5662 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5663 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5664 return -EINVAL;
5665 }
5666
bc7f75fa 5667 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5668 usleep_range(1000, 2000);
610c9928 5669 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5670 adapter->max_frame_size = max_frame;
610c9928
BA		 5671 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5672 netdev->mtu = new_mtu;
bc7f75fa
AK		 5673 if (netif_running(netdev))
5674 e1000e_down(adapter);
5675
e921eb1a 5676 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5677 * means we reserve 2 more, this pushes us to allocate from the next
5678 * larger slab size.
ad68076e 5679 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5680 * However with the new *_jumbo_rx* routines, jumbo receives will use
5681 * fragmented skbs
ad68076e 5682 */
bc7f75fa 5683
9926146b 5684 if (max_frame <= 2048)
bc7f75fa
AK		 5685 adapter->rx_buffer_len = 2048;
5686 else
5687 adapter->rx_buffer_len = 4096;
5688
5689 /* adjust allocation if LPE protects us, and we aren't using SBP */
5690 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5691 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5692 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5693 + ETH_FCS_LEN;
bc7f75fa 5694
bc7f75fa
AK		 5695 if (netif_running(netdev))
5696 e1000e_up(adapter);
5697 else
5698 e1000e_reset(adapter);
5699
5700 clear_bit(__E1000_RESETTING, &adapter->state);
5701
5702 return 0;
5703}
5704
5705static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5706 int cmd)
5707{
5708 struct e1000_adapter *adapter = netdev_priv(netdev);
5709 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5710
318a94d6 5711 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5712 return -EOPNOTSUPP;
5713
5714 switch (cmd) {
5715 case SIOCGMIIPHY:
5716 data->phy_id = adapter->hw.phy.addr;
5717 break;
5718 case SIOCGMIIREG:
b16a002e
BA		 5719 e1000_phy_read_status(adapter);
5720
7c25769f
BA		 5721 switch (data->reg_num & 0x1F) {
5722 case MII_BMCR:
5723 data->val_out = adapter->phy_regs.bmcr;
5724 break;
5725 case MII_BMSR:
5726 data->val_out = adapter->phy_regs.bmsr;
5727 break;
5728 case MII_PHYSID1:
5729 data->val_out = (adapter->hw.phy.id >> 16);
5730 break;
5731 case MII_PHYSID2:
5732 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5733 break;
5734 case MII_ADVERTISE:
5735 data->val_out = adapter->phy_regs.advertise;
5736 break;
5737 case MII_LPA:
5738 data->val_out = adapter->phy_regs.lpa;
5739 break;
5740 case MII_EXPANSION:
5741 data->val_out = adapter->phy_regs.expansion;
5742 break;
5743 case MII_CTRL1000:
5744 data->val_out = adapter->phy_regs.ctrl1000;
5745 break;
5746 case MII_STAT1000:
5747 data->val_out = adapter->phy_regs.stat1000;
5748 break;
5749 case MII_ESTATUS:
5750 data->val_out = adapter->phy_regs.estatus;
5751 break;
5752 default:
bc7f75fa
AK		 5753 return -EIO;
5754 }
bc7f75fa
AK		 5755 break;
5756 case SIOCSMIIREG:
5757 default:
5758 return -EOPNOTSUPP;
5759 }
5760 return 0;
5761}
5762
b67e1913
BA		 5763/**
5764 * e1000e_hwtstamp_ioctl - control hardware time stamping
5765 * @netdev: network interface device structure
5766 * @ifreq: interface request
5767 *
5768 * Outgoing time stamping can be enabled and disabled. Play nice and
5769 * disable it when requested, although it shouldn't cause any overhead
5770 * when no packet needs it. At most one packet in the queue may be
5771 * marked for time stamping, otherwise it would be impossible to tell
5772 * for sure to which packet the hardware time stamp belongs.
5773 *
5774 * Incoming time stamping has to be configured via the hardware filters.
5775 * Not all combinations are supported, in particular event type has to be
5776 * specified. Matching the kind of event packet is not supported, with the
5777 * exception of "all V2 events regardless of level 2 or 4".
5778 **/
5779static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5780{
5781 struct e1000_adapter *adapter = netdev_priv(netdev);
5782 struct hwtstamp_config config;
5783 int ret_val;
5784
5785 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5786 return -EFAULT;
5787
5788 adapter->hwtstamp_config = config;
5789
5790 ret_val = e1000e_config_hwtstamp(adapter);
5791 if (ret_val)
5792 return ret_val;
5793
5794 config = adapter->hwtstamp_config;
5795
d89777bf
BA		 5796 switch (config.rx_filter) {
5797 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5798 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5799 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5800 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5801 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5802 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5803 /* With V2 type filters which specify a Sync or Delay Request,
5804 * Path Delay Request/Response messages are also time stamped
5805 * by hardware so notify the caller the requested packets plus
5806 * some others are time stamped.
5807 */
5808 config.rx_filter = HWTSTAMP_FILTER_SOME;
5809 break;
5810 default:
5811 break;
5812 }
5813
b67e1913
BA		 5814 return copy_to_user(ifr->ifr_data, &config,
5815 sizeof(config)) ? -EFAULT : 0;
5816}
5817
bc7f75fa
AK		 5818static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5819{
5820 switch (cmd) {
5821 case SIOCGMIIPHY:
5822 case SIOCGMIIREG:
5823 case SIOCSMIIREG:
5824 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5825 case SIOCSHWTSTAMP:
5826 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5827 default:
5828 return -EOPNOTSUPP;
5829 }
5830}
5831
a4f58f54
BA		 5832static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5833{
5834 struct e1000_hw *hw = &adapter->hw;
5835 u32 i, mac_reg;
2b6b168d 5836 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5837 int retval = 0;
5838
5839 /* copy MAC RARs to PHY RARs */
d3738bb8 5840 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5841
2b6b168d
BA		 5842 retval = hw->phy.ops.acquire(hw);
5843 if (retval) {
5844 e_err("Could not acquire PHY\n");
5845 return retval;
5846 }
5847
5848 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5849 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5850 if (retval)
75ce1532 5851 goto release;
2b6b168d
BA		 5852
5853 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5854 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5855 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5856 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5857 (u16)(mac_reg & 0xFFFF));
5858 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5859 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5860 }
5861
5862 /* configure PHY Rx Control register */
2b6b168d 5863 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5864 mac_reg = er32(RCTL);
5865 if (mac_reg & E1000_RCTL_UPE)
5866 phy_reg |= BM_RCTL_UPE;
5867 if (mac_reg & E1000_RCTL_MPE)
5868 phy_reg |= BM_RCTL_MPE;
5869 phy_reg &= ~(BM_RCTL_MO_MASK);
5870 if (mac_reg & E1000_RCTL_MO_3)
5871 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5872 << BM_RCTL_MO_SHIFT);
5873 if (mac_reg & E1000_RCTL_BAM)
5874 phy_reg |= BM_RCTL_BAM;
5875 if (mac_reg & E1000_RCTL_PMCF)
5876 phy_reg |= BM_RCTL_PMCF;
5877 mac_reg = er32(CTRL);
5878 if (mac_reg & E1000_CTRL_RFCE)
5879 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5880 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5881
5882 /* enable PHY wakeup in MAC register */
5883 ew32(WUFC, wufc);
5884 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5885
5886 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5887 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5888 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5889
5890 /* activate PHY wakeup */
2b6b168d
BA		 5891 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5892 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5893 if (retval)
5894 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5895release:
94d8186a 5896 hw->phy.ops.release(hw);
a4f58f54
BA		 5897
5898 return retval;
5899}
5900
23606cf5
RW		 5901static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5902 bool runtime)
bc7f75fa
AK		 5903{
5904 struct net_device *netdev = pci_get_drvdata(pdev);
5905 struct e1000_adapter *adapter = netdev_priv(netdev);
5906 struct e1000_hw *hw = &adapter->hw;
5907 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5908 /* Runtime suspend should only enable wakeup for link changes */
5909 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5910 int retval = 0;
5911
5912 netif_device_detach(netdev);
5913
5914 if (netif_running(netdev)) {
bb9e44d0
BA		 5915 int count = E1000_CHECK_RESET_COUNT;
5916
5917 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5918 usleep_range(10000, 20000);
5919
bc7f75fa
AK		 5920 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5921 e1000e_down(adapter);
5922 e1000_free_irq(adapter);
5923 }
4662e82b 5924 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5925
5926 retval = pci_save_state(pdev);
5927 if (retval)
5928 return retval;
5929
5930 status = er32(STATUS);
5931 if (status & E1000_STATUS_LU)
5932 wufc &= ~E1000_WUFC_LNKC;
5933
5934 if (wufc) {
5935 e1000_setup_rctl(adapter);
ef9b965a 5936 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5937
5938 /* turn on all-multi mode if wake on multicast is enabled */
5939 if (wufc & E1000_WUFC_MC) {
5940 rctl = er32(RCTL);
5941 rctl |= E1000_RCTL_MPE;
5942 ew32(RCTL, rctl);
5943 }
5944
5945 ctrl = er32(CTRL);
5946 /* advertise wake from D3Cold */
5947 #define E1000_CTRL_ADVD3WUC 0x00100000
5948 /* phy power management enable */
5949 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5950 ctrl |= E1000_CTRL_ADVD3WUC;
5951 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5952 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5953 ew32(CTRL, ctrl);
5954
318a94d6
JK		 5955 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5956 adapter->hw.phy.media_type ==
5957 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5958 /* keep the laser running in D3 */
5959 ctrl_ext = er32(CTRL_EXT);
93a23f48 5960 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5961 ew32(CTRL_EXT, ctrl_ext);
5962 }
5963
97ac8cae 5964 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5965 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5966
bc7f75fa
AK		 5967 /* Allow time for pending master requests to run */
5968 e1000e_disable_pcie_master(&adapter->hw);
5969
82776a4b 5970 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5971 /* enable wakeup by the PHY */
5972 retval = e1000_init_phy_wakeup(adapter, wufc);
5973 if (retval)
5974 return retval;
5975 } else {
5976 /* enable wakeup by the MAC */
5977 ew32(WUFC, wufc);
5978 ew32(WUC, E1000_WUC_PME_EN);
5979 }
bc7f75fa
AK		 5980 } else {
5981 ew32(WUC, 0);
5982 ew32(WUFC, 0);
bc7f75fa
AK		 5983 }
5984
4f9de721
RW		 5985 *enable_wake = !!wufc;
5986
bc7f75fa 5987 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5988 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5989 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5990 *enable_wake = true;
bc7f75fa
AK		 5991
5992 if (adapter->hw.phy.type == e1000_phy_igp_3)
5993 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5994
e921eb1a 5995 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5996 * would have already happened in close and is redundant.
5997 */
31dbe5b4 5998 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5999
6000 pci_disable_device(pdev);
6001
4f9de721
RW		 6002 return 0;
6003}
6004
6005static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
6006{
6007 if (sleep && wake) {
6008 pci_prepare_to_sleep(pdev);
6009 return;
6010 }
6011
6012 pci_wake_from_d3(pdev, wake);
6013 pci_set_power_state(pdev, PCI_D3hot);
6014}
6015
6016static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
6017 bool wake)
6018{
6019 struct net_device *netdev = pci_get_drvdata(pdev);
6020 struct e1000_adapter *adapter = netdev_priv(netdev);
6021
e921eb1a 6022 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6023 * correctable error when the MAC transitions from D0 to D3. To
6024 * prevent this we need to mask off the correctable errors on the
6025 * downstream port of the pci-e switch.
6026 */
6027 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6028 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6029 u16 devctl;
6030
f8c0fcac
JL		 6031 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6032 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6033 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6034
4f9de721 6035 e1000_power_off(pdev, sleep, wake);
005cbdfc 6036
f8c0fcac 6037 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6038 } else {
4f9de721 6039 e1000_power_off(pdev, sleep, wake);
005cbdfc 6040 }
bc7f75fa
AK		 6041}
6042
6f461f6c
BA		 6043#ifdef CONFIG_PCIEASPM
6044static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6045{
9f728f53 6046 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 6047}
6048#else
6049static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 6050{
ffe0b2ff
BH		 6051 u16 aspm_ctl = 0;
6052
6053 if (state & PCIE_LINK_STATE_L0S)
6054 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6055 if (state & PCIE_LINK_STATE_L1)
6056 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6057
e921eb1a 6058 /* Both device and parent should have the same ASPM setting.
6f461f6c 6059 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6060 */
ffe0b2ff 6061 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 6062
f8c0fcac
JL		 6063 if (pdev->bus->self)
6064 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 6065 aspm_ctl);
6f461f6c
BA		 6066}
6067#endif
78cd29d5 6068static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 6069{
6070 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6071 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6072 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6073
6074 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 6075}
6076
aa338601 6077#ifdef CONFIG_PM
23606cf5 6078static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6079{
23606cf5 6080 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6081}
6082
23606cf5 6083static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6084{
6085 struct net_device *netdev = pci_get_drvdata(pdev);
6086 struct e1000_adapter *adapter = netdev_priv(netdev);
6087 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6088 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6089 u32 err;
6090
78cd29d5
BA		 6091 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6092 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6093 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6094 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6095 if (aspm_disable_flag)
6096 e1000e_disable_aspm(pdev, aspm_disable_flag);
6097
bc7f75fa
AK		 6098 pci_set_power_state(pdev, PCI_D0);
6099 pci_restore_state(pdev);
28b8f04a 6100 pci_save_state(pdev);
6e4f6f6b 6101
4662e82b 6102 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 6103 if (netif_running(netdev)) {
6104 err = e1000_request_irq(adapter);
6105 if (err)
6106 return err;
6107 }
6108
2fbe4526 6109 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6110 e1000_resume_workarounds_pchlan(&adapter->hw);
6111
bc7f75fa 6112 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6113
6114 /* report the system wakeup cause from S3/S4 */
6115 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6116 u16 phy_data;
6117
6118 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6119 if (phy_data) {
6120 e_info("PHY Wakeup cause - %s\n",
6121 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6122 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6123 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6124 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 6125 phy_data & E1000_WUS_LNKC ?
6126 "Link Status Change" : "other");
a4f58f54
BA		 6127 }
6128 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6129 } else {
6130 u32 wus = er32(WUS);
6131 if (wus) {
6132 e_info("MAC Wakeup cause - %s\n",
6133 wus & E1000_WUS_EX ? "Unicast Packet" :
6134 wus & E1000_WUS_MC ? "Multicast Packet" :
6135 wus & E1000_WUS_BC ? "Broadcast Packet" :
6136 wus & E1000_WUS_MAG ? "Magic Packet" :
6137 wus & E1000_WUS_LNKC ? "Link Status Change" :
6138 "other");
6139 }
6140 ew32(WUS, ~0);
6141 }
6142
bc7f75fa 6143 e1000e_reset(adapter);
bc7f75fa 6144
cd791618 6145 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6146
6147 if (netif_running(netdev))
6148 e1000e_up(adapter);
6149
6150 netif_device_attach(netdev);
6151
e921eb1a 6152 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6153 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6154 * under the control of the driver.
6155 */
c43bc57e 6156 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6157 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6158
6159 return 0;
6160}
23606cf5 6161
a0340162
RW		 6162#ifdef CONFIG_PM_SLEEP
6163static int e1000_suspend(struct device *dev)
6164{
6165 struct pci_dev *pdev = to_pci_dev(dev);
6166 int retval;
6167 bool wake;
6168
6169 retval = __e1000_shutdown(pdev, &wake, false);
6170 if (!retval)
6171 e1000_complete_shutdown(pdev, true, wake);
6172
6173 return retval;
6174}
6175
23606cf5
RW		 6176static int e1000_resume(struct device *dev)
6177{
6178 struct pci_dev *pdev = to_pci_dev(dev);
6179 struct net_device *netdev = pci_get_drvdata(pdev);
6180 struct e1000_adapter *adapter = netdev_priv(netdev);
6181
6182 if (e1000e_pm_ready(adapter))
6183 adapter->idle_check = true;
6184
6185 return __e1000_resume(pdev);
6186}
a0340162
RW		 6187#endif /* CONFIG_PM_SLEEP */
6188
6189#ifdef CONFIG_PM_RUNTIME
6190static int e1000_runtime_suspend(struct device *dev)
6191{
6192 struct pci_dev *pdev = to_pci_dev(dev);
6193 struct net_device *netdev = pci_get_drvdata(pdev);
6194 struct e1000_adapter *adapter = netdev_priv(netdev);
6195
6196 if (e1000e_pm_ready(adapter)) {
6197 bool wake;
6198
6199 __e1000_shutdown(pdev, &wake, true);
6200 }
6201
6202 return 0;
6203}
6204
6205static int e1000_idle(struct device *dev)
6206{
6207 struct pci_dev *pdev = to_pci_dev(dev);
6208 struct net_device *netdev = pci_get_drvdata(pdev);
6209 struct e1000_adapter *adapter = netdev_priv(netdev);
6210
6211 if (!e1000e_pm_ready(adapter))
6212 return 0;
6213
6214 if (adapter->idle_check) {
6215 adapter->idle_check = false;
6216 if (!e1000e_has_link(adapter))
6217 pm_schedule_suspend(dev, MSEC_PER_SEC);
6218 }
6219
6220 return -EBUSY;
6221}
23606cf5
RW		 6222
6223static int e1000_runtime_resume(struct device *dev)
6224{
6225 struct pci_dev *pdev = to_pci_dev(dev);
6226 struct net_device *netdev = pci_get_drvdata(pdev);
6227 struct e1000_adapter *adapter = netdev_priv(netdev);
6228
6229 if (!e1000e_pm_ready(adapter))
6230 return 0;
6231
6232 adapter->idle_check = !dev->power.runtime_auto;
6233 return __e1000_resume(pdev);
6234}
a0340162 6235#endif /* CONFIG_PM_RUNTIME */
aa338601 6236#endif /* CONFIG_PM */
bc7f75fa
AK		 6237
6238static void e1000_shutdown(struct pci_dev *pdev)
6239{
4f9de721
RW		 6240 bool wake = false;
6241
23606cf5 6242 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 6243
6244 if (system_state == SYSTEM_POWER_OFF)
6245 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 6246}
6247
6248#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 6249
6250static irqreturn_t e1000_intr_msix(int irq, void *data)
6251{
6252 struct net_device *netdev = data;
6253 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6254
6255 if (adapter->msix_entries) {
90da0669
BA		 6256 int vector, msix_irq;
6257
147b2c8c
DD		 6258 vector = 0;
6259 msix_irq = adapter->msix_entries[vector].vector;
6260 disable_irq(msix_irq);
6261 e1000_intr_msix_rx(msix_irq, netdev);
6262 enable_irq(msix_irq);
6263
6264 vector++;
6265 msix_irq = adapter->msix_entries[vector].vector;
6266 disable_irq(msix_irq);
6267 e1000_intr_msix_tx(msix_irq, netdev);
6268 enable_irq(msix_irq);
6269
6270 vector++;
6271 msix_irq = adapter->msix_entries[vector].vector;
6272 disable_irq(msix_irq);
6273 e1000_msix_other(msix_irq, netdev);
6274 enable_irq(msix_irq);
6275 }
6276
6277 return IRQ_HANDLED;
6278}
6279
e921eb1a
BA		 6280/**
6281 * e1000_netpoll
6282 * @netdev: network interface device structure
6283 *
bc7f75fa
AK		 6284 * Polling 'interrupt' - used by things like netconsole to send skbs
6285 * without having to re-enable interrupts. It's not called while
6286 * the interrupt routine is executing.
6287 */
6288static void e1000_netpoll(struct net_device *netdev)
6289{
6290 struct e1000_adapter *adapter = netdev_priv(netdev);
6291
147b2c8c
DD		 6292 switch (adapter->int_mode) {
6293 case E1000E_INT_MODE_MSIX:
6294 e1000_intr_msix(adapter->pdev->irq, netdev);
6295 break;
6296 case E1000E_INT_MODE_MSI:
6297 disable_irq(adapter->pdev->irq);
6298 e1000_intr_msi(adapter->pdev->irq, netdev);
6299 enable_irq(adapter->pdev->irq);
6300 break;
6301 default: /* E1000E_INT_MODE_LEGACY */
6302 disable_irq(adapter->pdev->irq);
6303 e1000_intr(adapter->pdev->irq, netdev);
6304 enable_irq(adapter->pdev->irq);
6305 break;
6306 }
bc7f75fa
AK		 6307}
6308#endif
6309
6310/**
6311 * e1000_io_error_detected - called when PCI error is detected
6312 * @pdev: Pointer to PCI device
6313 * @state: The current pci connection state
6314 *
6315 * This function is called after a PCI bus error affecting
6316 * this device has been detected.
6317 */
6318static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6319 pci_channel_state_t state)
6320{
6321 struct net_device *netdev = pci_get_drvdata(pdev);
6322 struct e1000_adapter *adapter = netdev_priv(netdev);
6323
6324 netif_device_detach(netdev);
6325
c93b5a76
MM		 6326 if (state == pci_channel_io_perm_failure)
6327 return PCI_ERS_RESULT_DISCONNECT;
6328
bc7f75fa
AK		 6329 if (netif_running(netdev))
6330 e1000e_down(adapter);
6331 pci_disable_device(pdev);
6332
6333 /* Request a slot slot reset. */
6334 return PCI_ERS_RESULT_NEED_RESET;
6335}
6336
6337/**
6338 * e1000_io_slot_reset - called after the pci bus has been reset.
6339 * @pdev: Pointer to PCI device
6340 *
6341 * Restart the card from scratch, as if from a cold-boot. Implementation
6342 * resembles the first-half of the e1000_resume routine.
6343 */
6344static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6345{
6346 struct net_device *netdev = pci_get_drvdata(pdev);
6347 struct e1000_adapter *adapter = netdev_priv(netdev);
6348 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6349 u16 aspm_disable_flag = 0;
6e4f6f6b 6350 int err;
111b9dc5 6351 pci_ers_result_t result;
bc7f75fa 6352
78cd29d5
BA		 6353 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6354 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6355 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6356 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6357 if (aspm_disable_flag)
6358 e1000e_disable_aspm(pdev, aspm_disable_flag);
6359
f0f422e5 6360 err = pci_enable_device_mem(pdev);
6e4f6f6b 6361 if (err) {
bc7f75fa
AK		 6362 dev_err(&pdev->dev,
6363 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6364 result = PCI_ERS_RESULT_DISCONNECT;
6365 } else {
6366 pci_set_master(pdev);
23606cf5 6367 pdev->state_saved = true;
111b9dc5 6368 pci_restore_state(pdev);
bc7f75fa 6369
111b9dc5
JB		 6370 pci_enable_wake(pdev, PCI_D3hot, 0);
6371 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6372
111b9dc5
JB		 6373 e1000e_reset(adapter);
6374 ew32(WUS, ~0);
6375 result = PCI_ERS_RESULT_RECOVERED;
6376 }
bc7f75fa 6377
111b9dc5
JB		 6378 pci_cleanup_aer_uncorrect_error_status(pdev);
6379
6380 return result;
bc7f75fa
AK		 6381}
6382
6383/**
6384 * e1000_io_resume - called when traffic can start flowing again.
6385 * @pdev: Pointer to PCI device
6386 *
6387 * This callback is called when the error recovery driver tells us that
6388 * its OK to resume normal operation. Implementation resembles the
6389 * second-half of the e1000_resume routine.
6390 */
6391static void e1000_io_resume(struct pci_dev *pdev)
6392{
6393 struct net_device *netdev = pci_get_drvdata(pdev);
6394 struct e1000_adapter *adapter = netdev_priv(netdev);
6395
cd791618 6396 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6397
6398 if (netif_running(netdev)) {
6399 if (e1000e_up(adapter)) {
6400 dev_err(&pdev->dev,
6401 "can't bring device back up after reset\n");
6402 return;
6403 }
6404 }
6405
6406 netif_device_attach(netdev);
6407
e921eb1a 6408 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6409 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6410 * under the control of the driver.
6411 */
c43bc57e 6412 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6413 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6414
6415}
6416
6417static void e1000_print_device_info(struct e1000_adapter *adapter)
6418{
6419 struct e1000_hw *hw = &adapter->hw;
6420 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6421 u32 ret_val;
6422 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6423
6424 /* print bus type/speed/width info */
a5cc7642 6425 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6426 /* bus width */
6427 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6428 "Width x1"),
6429 /* MAC address */
7c510e4b 6430 netdev->dev_addr);
44defeb3
JK		 6431 e_info("Intel(R) PRO/%s Network Connection\n",
6432 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6433 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6434 E1000_PBANUM_LENGTH);
6435 if (ret_val)
f2315bf1 6436 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6437 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6438 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6439}
6440
10aa4c04
AK		 6441static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6442{
6443 struct e1000_hw *hw = &adapter->hw;
6444 int ret_val;
6445 u16 buf = 0;
6446
6447 if (hw->mac.type != e1000_82573)
6448 return;
6449
6450 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6451 le16_to_cpus(&buf);
6452 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6453 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6454 dev_warn(&adapter->pdev->dev,
6455 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6456 }
10aa4c04
AK		 6457}
6458
c8f44aff 6459static int e1000_set_features(struct net_device *netdev,
70495a50 6460 netdev_features_t features)
dc221294
BA		 6461{
6462 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6463 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6464
6465 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6466 adapter->flags |= FLAG_TSO_FORCE;
6467
6468 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6469 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6470 NETIF_F_RXALL)))
dc221294
BA		 6471 return 0;
6472
0184039a
BG		 6473 if (changed & NETIF_F_RXFCS) {
6474 if (features & NETIF_F_RXFCS) {
6475 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6476 } else {
6477 /* We need to take it back to defaults, which might mean
6478 * stripping is still disabled at the adapter level.
6479 */
6480 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6481 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6482 else
6483 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6484 }
6485 }
6486
70495a50
BA		 6487 netdev->features = features;
6488
dc221294
BA		 6489 if (netif_running(netdev))
6490 e1000e_reinit_locked(adapter);
6491 else
6492 e1000e_reset(adapter);
6493
6494 return 0;
6495}
6496
651c2466
SH		 6497static const struct net_device_ops e1000e_netdev_ops = {
6498 .ndo_open = e1000_open,
6499 .ndo_stop = e1000_close,
00829823 6500 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6501 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6502 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6503 .ndo_set_mac_address = e1000_set_mac,
6504 .ndo_change_mtu = e1000_change_mtu,
6505 .ndo_do_ioctl = e1000_ioctl,
6506 .ndo_tx_timeout = e1000_tx_timeout,
6507 .ndo_validate_addr = eth_validate_addr,
6508
651c2466
SH		 6509 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6510 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6511#ifdef CONFIG_NET_POLL_CONTROLLER
6512 .ndo_poll_controller = e1000_netpoll,
6513#endif
dc221294 6514 .ndo_set_features = e1000_set_features,
651c2466
SH		 6515};
6516
bc7f75fa
AK		 6517/**
6518 * e1000_probe - Device Initialization Routine
6519 * @pdev: PCI device information struct
6520 * @ent: entry in e1000_pci_tbl
6521 *
6522 * Returns 0 on success, negative on failure
6523 *
6524 * e1000_probe initializes an adapter identified by a pci_dev structure.
6525 * The OS initialization, configuring of the adapter private structure,
6526 * and a hardware reset occur.
6527 **/
1dd06ae8 6528static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6529{
6530 struct net_device *netdev;
6531 struct e1000_adapter *adapter;
6532 struct e1000_hw *hw;
6533 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6534 resource_size_t mmio_start, mmio_len;
6535 resource_size_t flash_start, flash_len;
bc7f75fa 6536 static int cards_found;
78cd29d5 6537 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6538 int i, err, pci_using_dac;
6539 u16 eeprom_data = 0;
6540 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6541
78cd29d5
BA		 6542 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6543 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6544 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6545 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6546 if (aspm_disable_flag)
6547 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6548
f0f422e5 6549 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6550 if (err)
6551 return err;
6552
6553 pci_using_dac = 0;
0be3f55f 6554 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6555 if (!err) {
0be3f55f 6556 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6557 if (!err)
6558 pci_using_dac = 1;
6559 } else {
0be3f55f 6560 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6561 if (err) {
0be3f55f
NN		 6562 err = dma_set_coherent_mask(&pdev->dev,
6563 DMA_BIT_MASK(32));
bc7f75fa 6564 if (err) {
ef456f85 6565 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6566 goto err_dma;
6567 }
6568 }
6569 }
6570
e8de1481 6571 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6572 pci_select_bars(pdev, IORESOURCE_MEM),
6573 e1000e_driver_name);
bc7f75fa
AK		 6574 if (err)
6575 goto err_pci_reg;
6576
68eac460 6577 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6578 pci_enable_pcie_error_reporting(pdev);
68eac460 6579
bc7f75fa 6580 pci_set_master(pdev);
438b365a
BA		 6581 /* PCI config space info */
6582 err = pci_save_state(pdev);
6583 if (err)
6584 goto err_alloc_etherdev;
bc7f75fa
AK		 6585
6586 err = -ENOMEM;
6587 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6588 if (!netdev)
6589 goto err_alloc_etherdev;
6590
bc7f75fa
AK		 6591 SET_NETDEV_DEV(netdev, &pdev->dev);
6592
f85e4dfa
TH		 6593 netdev->irq = pdev->irq;
6594
bc7f75fa
AK		 6595 pci_set_drvdata(pdev, netdev);
6596 adapter = netdev_priv(netdev);
6597 hw = &adapter->hw;
6598 adapter->netdev = netdev;
6599 adapter->pdev = pdev;
6600 adapter->ei = ei;
6601 adapter->pba = ei->pba;
6602 adapter->flags = ei->flags;
eb7c3adb 6603 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6604 adapter->hw.adapter = adapter;
6605 adapter->hw.mac.type = ei->mac;
2adc55c9 6606 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6607 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6608
6609 mmio_start = pci_resource_start(pdev, 0);
6610 mmio_len = pci_resource_len(pdev, 0);
6611
6612 err = -EIO;
6613 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6614 if (!adapter->hw.hw_addr)
6615 goto err_ioremap;
6616
6617 if ((adapter->flags & FLAG_HAS_FLASH) &&
6618 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6619 flash_start = pci_resource_start(pdev, 1);
6620 flash_len = pci_resource_len(pdev, 1);
6621 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6622 if (!adapter->hw.flash_address)
6623 goto err_flashmap;
6624 }
6625
6626 /* construct the net_device struct */
651c2466 6627 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6628 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6629 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6630 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6631 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6632
6633 netdev->mem_start = mmio_start;
6634 netdev->mem_end = mmio_start + mmio_len;
6635
6636 adapter->bd_number = cards_found++;
6637
4662e82b
BA		 6638 e1000e_check_options(adapter);
6639
bc7f75fa
AK		 6640 /* setup adapter struct */
6641 err = e1000_sw_init(adapter);
6642 if (err)
6643 goto err_sw_init;
6644
bc7f75fa
AK		 6645 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6646 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6647 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6648
69e3fd8c 6649 err = ei->get_variants(adapter);
bc7f75fa
AK		 6650 if (err)
6651 goto err_hw_init;
6652
4a770358
BA		 6653 if ((adapter->flags & FLAG_IS_ICH) &&
6654 (adapter->flags & FLAG_READ_ONLY_NVM))
6655 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6656
bc7f75fa
AK		 6657 hw->mac.ops.get_bus_info(&adapter->hw);
6658
318a94d6 6659 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6660
6661 /* Copper options */
318a94d6 6662 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6663 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6664 adapter->hw.phy.disable_polarity_correction = 0;
6665 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6666 }
6667
470a5420 6668 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6669 dev_info(&pdev->dev,
6670 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6671
dc221294
BA		 6672 /* Set initial default active device features */
6673 netdev->features = (NETIF_F_SG |
6674 NETIF_F_HW_VLAN_RX |
6675 NETIF_F_HW_VLAN_TX |
6676 NETIF_F_TSO |
6677 NETIF_F_TSO6 |
70495a50 6678 NETIF_F_RXHASH |
dc221294
BA		 6679 NETIF_F_RXCSUM |
6680 NETIF_F_HW_CSUM);
6681
6682 /* Set user-changeable features (subset of all device features) */
6683 netdev->hw_features = netdev->features;
0184039a 6684 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6685 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6686 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6687
6688 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6689 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6690
dc221294
BA		 6691 netdev->vlan_features |= (NETIF_F_SG |
6692 NETIF_F_TSO |
6693 NETIF_F_TSO6 |
6694 NETIF_F_HW_CSUM);
a5136e23 6695
ef9b965a
JB		 6696 netdev->priv_flags |= IFF_UNICAST_FLT;
6697
7b872a55 6698 if (pci_using_dac) {
bc7f75fa 6699 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6700 netdev->vlan_features |= NETIF_F_HIGHDMA;
6701 }
bc7f75fa 6702
bc7f75fa
AK		 6703 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6704 adapter->flags |= FLAG_MNG_PT_ENABLED;
6705
e921eb1a 6706 /* before reading the NVM, reset the controller to
ad68076e
BA		 6707 * put the device in a known good starting state
6708 */
bc7f75fa
AK		 6709 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6710
e921eb1a 6711 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6712 * attempt. Let's give it a few tries
6713 */
6714 for (i = 0;; i++) {
6715 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6716 break;
6717 if (i == 2) {
185095fb 6718 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6719 err = -EIO;
6720 goto err_eeprom;
6721 }
6722 }
6723
10aa4c04
AK		 6724 e1000_eeprom_checks(adapter);
6725
608f8a0d 6726 /* copy the MAC address */
bc7f75fa 6727 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6728 dev_err(&pdev->dev,
6729 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6730
6731 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6732
aaeb6cdf 6733 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6734 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6735 netdev->dev_addr);
bc7f75fa
AK		 6736 err = -EIO;
6737 goto err_eeprom;
6738 }
6739
6740 init_timer(&adapter->watchdog_timer);
c061b18d 6741 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6742 adapter->watchdog_timer.data = (unsigned long) adapter;
6743
6744 init_timer(&adapter->phy_info_timer);
c061b18d 6745 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6746 adapter->phy_info_timer.data = (unsigned long) adapter;
6747
6748 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6749 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6750 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6751 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6752 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6753
bc7f75fa
AK		 6754 /* Initialize link parameters. User can change them with ethtool */
6755 adapter->hw.mac.autoneg = 1;
3db1cd5c 6756 adapter->fc_autoneg = true;
5c48ef3e
BA		 6757 adapter->hw.fc.requested_mode = e1000_fc_default;
6758 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6759 adapter->hw.phy.autoneg_advertised = 0x2f;
6760
6761 /* ring size defaults */
d821a4c4
BA		 6762 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6763 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6764
e921eb1a 6765 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6766 * the EEPROM, enable the ACPI Magic Packet filter
6767 */
6768 if (adapter->flags & FLAG_APME_IN_WUC) {
6769 /* APME bit in EEPROM is mapped to WUC.APME */
6770 eeprom_data = er32(WUC);
6771 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6772 if ((hw->mac.type > e1000_ich10lan) &&
6773 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6774 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6775 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6776 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6777 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6778 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6779 1, &eeprom_data);
bc7f75fa 6780 else
3d3a1676
BA		 6781 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6782 1, &eeprom_data);
bc7f75fa
AK		 6783 }
6784
6785 /* fetch WoL from EEPROM */
6786 if (eeprom_data & eeprom_apme_mask)
6787 adapter->eeprom_wol |= E1000_WUFC_MAG;
6788
e921eb1a 6789 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6790 * where the eeprom may be wrong or the board simply won't support
6791 * wake on lan on a particular port
6792 */
6793 if (!(adapter->flags & FLAG_HAS_WOL))
6794 adapter->eeprom_wol = 0;
6795
6796 /* initialize the wol settings based on the eeprom settings */
6797 adapter->wol = adapter->eeprom_wol;
6ff68026 6798 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6799
84527590
BA		 6800 /* save off EEPROM version number */
6801 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6802
bc7f75fa
AK		 6803 /* reset the hardware with the new settings */
6804 e1000e_reset(adapter);
6805
e921eb1a 6806 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6807 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6808 * under the control of the driver.
6809 */
c43bc57e 6810 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6811 e1000e_get_hw_control(adapter);
bc7f75fa 6812
f2315bf1 6813 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6814 err = register_netdev(netdev);
6815 if (err)
6816 goto err_register;
6817
9c563d20
JB		 6818 /* carrier off reporting is important to ethtool even BEFORE open */
6819 netif_carrier_off(netdev);
6820
d89777bf
BA		 6821 /* init PTP hardware clock */
6822 e1000e_ptp_init(adapter);
6823
bc7f75fa
AK		 6824 e1000_print_device_info(adapter);
6825
f3ec4f87
AS		 6826 if (pci_dev_run_wake(pdev))
6827 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6828
bc7f75fa
AK		 6829 return 0;
6830
6831err_register:
c43bc57e 6832 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6833 e1000e_release_hw_control(adapter);
bc7f75fa 6834err_eeprom:
470a5420 6835 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6836 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6837err_hw_init:
bc7f75fa
AK		 6838 kfree(adapter->tx_ring);
6839 kfree(adapter->rx_ring);
6840err_sw_init:
c43bc57e
JB		 6841 if (adapter->hw.flash_address)
6842 iounmap(adapter->hw.flash_address);
e82f54ba 6843 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6844err_flashmap:
bc7f75fa
AK		 6845 iounmap(adapter->hw.hw_addr);
6846err_ioremap:
6847 free_netdev(netdev);
6848err_alloc_etherdev:
f0f422e5
BA		 6849 pci_release_selected_regions(pdev,
6850 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6851err_pci_reg:
6852err_dma:
6853 pci_disable_device(pdev);
6854 return err;
6855}
6856
6857/**
6858 * e1000_remove - Device Removal Routine
6859 * @pdev: PCI device information struct
6860 *
6861 * e1000_remove is called by the PCI subsystem to alert the driver
6862 * that it should release a PCI device. The could be caused by a
6863 * Hot-Plug event, or because the driver is going to be removed from
6864 * memory.
6865 **/
9f9a12f8 6866static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6867{
6868 struct net_device *netdev = pci_get_drvdata(pdev);
6869 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6870 bool down = test_bit(__E1000_DOWN, &adapter->state);
6871
d89777bf
BA		 6872 e1000e_ptp_remove(adapter);
6873
e921eb1a 6874 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6875 * from being rescheduled.
ad68076e 6876 */
23606cf5
RW		 6877 if (!down)
6878 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6879 del_timer_sync(&adapter->watchdog_timer);
6880 del_timer_sync(&adapter->phy_info_timer);
6881
41cec6f1
BA		 6882 cancel_work_sync(&adapter->reset_task);
6883 cancel_work_sync(&adapter->watchdog_task);
6884 cancel_work_sync(&adapter->downshift_task);
6885 cancel_work_sync(&adapter->update_phy_task);
6886 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6887
b67e1913
BA		 6888 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6889 cancel_work_sync(&adapter->tx_hwtstamp_work);
6890 if (adapter->tx_hwtstamp_skb) {
6891 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6892 adapter->tx_hwtstamp_skb = NULL;
6893 }
6894 }
6895
17f208de
BA		 6896 if (!(netdev->flags & IFF_UP))
6897 e1000_power_down_phy(adapter);
6898
23606cf5
RW		 6899 /* Don't lie to e1000_close() down the road. */
6900 if (!down)
6901 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6902 unregister_netdev(netdev);
6903
f3ec4f87
AS		 6904 if (pci_dev_run_wake(pdev))
6905 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6906
e921eb1a 6907 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6908 * would have already happened in close and is redundant.
6909 */
31dbe5b4 6910 e1000e_release_hw_control(adapter);
bc7f75fa 6911
4662e82b 6912 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6913 kfree(adapter->tx_ring);
6914 kfree(adapter->rx_ring);
6915
6916 iounmap(adapter->hw.hw_addr);
6917 if (adapter->hw.flash_address)
6918 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6919 pci_release_selected_regions(pdev,
6920 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6921
6922 free_netdev(netdev);
6923
111b9dc5 6924 /* AER disable */
19d5afd4 6925 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6926
bc7f75fa
AK		 6927 pci_disable_device(pdev);
6928}
6929
6930/* PCI Error Recovery (ERS) */
3646f0e5 6931static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6932 .error_detected = e1000_io_error_detected,
6933 .slot_reset = e1000_io_slot_reset,
6934 .resume = e1000_io_resume,
6935};
6936
a3aa1884 6937static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6940 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6941 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6943 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6944 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6945 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6947
bc7f75fa
AK		 6948 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6949 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6950 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6951 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6952
bc7f75fa
AK		 6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6954 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6955 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6956
4662e82b 6957 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6959 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6960
bc7f75fa
AK		 6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6962 board_80003es2lan },
6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6964 board_80003es2lan },
6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6966 board_80003es2lan },
6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6968 board_80003es2lan },
ad68076e 6969
bc7f75fa
AK		 6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6973 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6976 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6977 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6978
bc7f75fa
AK		 6979 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6980 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6981 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6982 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6984 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6985 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6987 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6988
6989 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6990 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6991 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6992
f4187b56
BA		 6993 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6994 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6995 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6996
a4f58f54
BA		 6997 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6998 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6999 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7000 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7001
d3738bb8
BA		 7002 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7003 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7004
2fbe4526
BA		 7005 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7006 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7007 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7008 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 7009
f36bb6ca 7010 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7011};
7012MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7013
aa338601 7014#ifdef CONFIG_PM
23606cf5 7015static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 7016 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
7017 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
7018 e1000_runtime_resume, e1000_idle)
23606cf5 7019};
e50208a0 7020#endif
23606cf5 7021
bc7f75fa
AK		 7022/* PCI Device API Driver */
7023static struct pci_driver e1000_driver = {
7024 .name = e1000e_driver_name,
7025 .id_table = e1000_pci_tbl,
7026 .probe = e1000_probe,
9f9a12f8 7027 .remove = e1000_remove,
aa338601 7028#ifdef CONFIG_PM
f36bb6ca
BA		 7029 .driver = {
7030 .pm = &e1000_pm_ops,
7031 },
bc7f75fa
AK		 7032#endif
7033 .shutdown = e1000_shutdown,
7034 .err_handler = &e1000_err_handler
7035};
7036
7037/**
7038 * e1000_init_module - Driver Registration Routine
7039 *
7040 * e1000_init_module is the first routine called when the driver is
7041 * loaded. All it does is register with the PCI subsystem.
7042 **/
7043static int __init e1000_init_module(void)
7044{
7045 int ret;
8544b9f7
BA		 7046 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7047 e1000e_driver_version);
bf67044b 7048 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
bc7f75fa 7049 ret = pci_register_driver(&e1000_driver);
53ec5498 7050
bc7f75fa
AK		 7051 return ret;
7052}
7053module_init(e1000_init_module);
7054
7055/**
7056 * e1000_exit_module - Driver Exit Cleanup Routine
7057 *
7058 * e1000_exit_module is called just before the driver is removed
7059 * from memory.
7060 **/
7061static void __exit e1000_exit_module(void)
7062{
7063 pci_unregister_driver(&e1000_driver);
7064}
7065module_exit(e1000_exit_module);
7066
7067
7068MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7069MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7070MODULE_LICENSE("GPL");
7071MODULE_VERSION(DRV_VERSION);
7072
06c24b91 7073/* netdev.c */
Linux kernel - Deliverables
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