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e1000e: cleanup checkpatch braces checks
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
bf67044b 4 Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
bc7f75fa
AK		 45#include <linux/ethtool.h>
46#include <linux/if_vlan.h>
47#include <linux/cpu.h>
48#include <linux/smp.h>
e8db0be1 49#include <linux/pm_qos.h>
23606cf5 50#include <linux/pm_runtime.h>
111b9dc5 51#include <linux/aer.h>
70c71606 52#include <linux/prefetch.h>
bc7f75fa
AK		 53
54#include "e1000.h"
55
b3ccf267 56#define DRV_EXTRAVERSION "-k"
c14c643b 57
9e019901 58#define DRV_VERSION "2.2.14" DRV_EXTRAVERSION
bc7f75fa
AK		 59char e1000e_driver_name[] = "e1000e";
60const char e1000e_driver_version[] = DRV_VERSION;
61
b3f4d599 62#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
63static int debug = -1;
64module_param(debug, int, 0);
65MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
66
78cd29d5
BA		 67static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
68
bc7f75fa
AK		 69static const struct e1000_info *e1000_info_tbl[] = {
70 [board_82571] = &e1000_82571_info,
71 [board_82572] = &e1000_82572_info,
72 [board_82573] = &e1000_82573_info,
4662e82b 73 [board_82574] = &e1000_82574_info,
8c81c9c3 74 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 75 [board_80003es2lan] = &e1000_es2_info,
76 [board_ich8lan] = &e1000_ich8_info,
77 [board_ich9lan] = &e1000_ich9_info,
f4187b56 78 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 79 [board_pchlan] = &e1000_pch_info,
d3738bb8 80 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 81 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
84f4ee90 89static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 90 /* General Registers */
91 {E1000_CTRL, "CTRL"},
92 {E1000_STATUS, "STATUS"},
93 {E1000_CTRL_EXT, "CTRL_EXT"},
94
95 /* Interrupt Registers */
96 {E1000_ICR, "ICR"},
97
af667a29 98 /* Rx Registers */
84f4ee90 99 {E1000_RCTL, "RCTL"},
1e36052e
BA		 100 {E1000_RDLEN(0), "RDLEN"},
101 {E1000_RDH(0), "RDH"},
102 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 103 {E1000_RDTR, "RDTR"},
104 {E1000_RXDCTL(0), "RXDCTL"},
105 {E1000_ERT, "ERT"},
1e36052e
BA		 106 {E1000_RDBAL(0), "RDBAL"},
107 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 108 {E1000_RDFH, "RDFH"},
109 {E1000_RDFT, "RDFT"},
110 {E1000_RDFHS, "RDFHS"},
111 {E1000_RDFTS, "RDFTS"},
112 {E1000_RDFPC, "RDFPC"},
113
af667a29 114 /* Tx Registers */
84f4ee90 115 {E1000_TCTL, "TCTL"},
1e36052e
BA		 116 {E1000_TDBAL(0), "TDBAL"},
117 {E1000_TDBAH(0), "TDBAH"},
118 {E1000_TDLEN(0), "TDLEN"},
119 {E1000_TDH(0), "TDH"},
120 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 121 {E1000_TIDV, "TIDV"},
122 {E1000_TXDCTL(0), "TXDCTL"},
123 {E1000_TADV, "TADV"},
124 {E1000_TARC(0), "TARC"},
125 {E1000_TDFH, "TDFH"},
126 {E1000_TDFT, "TDFT"},
127 {E1000_TDFHS, "TDFHS"},
128 {E1000_TDFTS, "TDFTS"},
129 {E1000_TDFPC, "TDFPC"},
130
131 /* List Terminator */
f36bb6ca 132 {0, NULL}
84f4ee90
TI		 133};
134
e921eb1a 135/**
84f4ee90 136 * e1000_regdump - register printout routine
e921eb1a
BA		 137 * @hw: pointer to the HW structure
138 * @reginfo: pointer to the register info table
139 **/
84f4ee90
TI		 140static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
141{
142 int n = 0;
143 char rname[16];
144 u32 regs[8];
145
146 switch (reginfo->ofs) {
147 case E1000_RXDCTL(0):
148 for (n = 0; n < 2; n++)
149 regs[n] = __er32(hw, E1000_RXDCTL(n));
150 break;
151 case E1000_TXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_TXDCTL(n));
154 break;
155 case E1000_TARC(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TARC(n));
158 break;
159 default:
ef456f85
JK		 160 pr_info("%-15s %08x\n",
161 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 162 return;
163 }
164
165 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 166 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 167}
168
f0c5dadf
ET		 169static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
170 struct e1000_buffer *bi)
171{
172 int i;
173 struct e1000_ps_page *ps_page;
174
175 for (i = 0; i < adapter->rx_ps_pages; i++) {
176 ps_page = &bi->ps_pages[i];
177
178 if (ps_page->page) {
179 pr_info("packet dump for ps_page %d:\n", i);
180 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
181 16, 1, page_address(ps_page->page),
182 PAGE_SIZE, true);
183 }
184 }
185}
186
e921eb1a 187/**
af667a29 188 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 189 * @adapter: board private structure
190 **/
84f4ee90
TI		 191static void e1000e_dump(struct e1000_adapter *adapter)
192{
193 struct net_device *netdev = adapter->netdev;
194 struct e1000_hw *hw = &adapter->hw;
195 struct e1000_reg_info *reginfo;
196 struct e1000_ring *tx_ring = adapter->tx_ring;
197 struct e1000_tx_desc *tx_desc;
af667a29 198 struct my_u0 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
af667a29 201 } *u0;
84f4ee90
TI		 202 struct e1000_buffer *buffer_info;
203 struct e1000_ring *rx_ring = adapter->rx_ring;
204 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 205 union e1000_rx_desc_extended *rx_desc;
af667a29 206 struct my_u1 {
e885d762
BA		 207 __le64 a;
208 __le64 b;
209 __le64 c;
210 __le64 d;
af667a29 211 } *u1;
84f4ee90
TI		 212 u32 staterr;
213 int i = 0;
214
215 if (!netif_msg_hw(adapter))
216 return;
217
218 /* Print netdevice Info */
219 if (netdev) {
220 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 221 pr_info("Device Name state trans_start last_rx\n");
222 pr_info("%-15s %016lX %016lX %016lX\n",
223 netdev->name, netdev->state, netdev->trans_start,
224 netdev->last_rx);
84f4ee90
TI		 225 }
226
227 /* Print Registers */
228 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 229 pr_info(" Register Name Value\n");
84f4ee90
TI		 230 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
231 reginfo->name; reginfo++) {
232 e1000_regdump(hw, reginfo);
233 }
234
af667a29 235 /* Print Tx Ring Summary */
84f4ee90 236 if (!netdev || !netif_running(netdev))
fe1e980f 237 return;
84f4ee90 238
af667a29 239 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 240 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 241 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 242 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
243 0, tx_ring->next_to_use, tx_ring->next_to_clean,
244 (unsigned long long)buffer_info->dma,
245 buffer_info->length,
246 buffer_info->next_to_watch,
247 (unsigned long long)buffer_info->time_stamp);
84f4ee90 248
af667a29 249 /* Print Tx Ring */
84f4ee90
TI		 250 if (!netif_msg_tx_done(adapter))
251 goto rx_ring_summary;
252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 254
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
256 *
257 * Legacy Transmit Descriptor
258 * +--------------------------------------------------------------+
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
260 * +--------------------------------------------------------------+
261 * 8 | Special | CSS | Status | CMD | CSO | Length |
262 * +--------------------------------------------------------------+
263 * 63 48 47 36 35 32 31 24 23 16 15 0
264 *
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
266 * 63 48 47 40 39 32 31 16 15 8 7 0
267 * +----------------------------------------------------------------+
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
269 * +----------------------------------------------------------------+
270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 *
274 * Extended Data Descriptor (DTYP=0x1)
275 * +----------------------------------------------------------------+
276 * 0 | Buffer Address [63:0] |
277 * +----------------------------------------------------------------+
278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
279 * +----------------------------------------------------------------+
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
281 */
ef456f85
JK		 282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 286 const char *next_desc;
84f4ee90
TI		 287 tx_desc = E1000_TX_DESC(*tx_ring, i);
288 buffer_info = &tx_ring->buffer_info[i];
289 u0 = (struct my_u0 *)tx_desc;
84f4ee90 290 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 291 next_desc = " NTC/U";
84f4ee90 292 else if (i == tx_ring->next_to_use)
ef456f85 293 next_desc = " NTU";
84f4ee90 294 else if (i == tx_ring->next_to_clean)
ef456f85 295 next_desc = " NTC";
84f4ee90 296 else
ef456f85
JK		 297 next_desc = "";
298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
299 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
300 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
301 i,
302 (unsigned long long)le64_to_cpu(u0->a),
303 (unsigned long long)le64_to_cpu(u0->b),
304 (unsigned long long)buffer_info->dma,
305 buffer_info->length, buffer_info->next_to_watch,
306 (unsigned long long)buffer_info->time_stamp,
307 buffer_info->skb, next_desc);
84f4ee90 308
f0c5dadf 309 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 310 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 311 16, 1, buffer_info->skb->data,
312 buffer_info->skb->len, true);
84f4ee90
TI		 313 }
314
af667a29 315 /* Print Rx Ring Summary */
84f4ee90 316rx_ring_summary:
af667a29 317 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 318 pr_info("Queue [NTU] [NTC]\n");
319 pr_info(" %5d %5X %5X\n",
320 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 321
af667a29 322 /* Print Rx Ring */
84f4ee90 323 if (!netif_msg_rx_status(adapter))
fe1e980f 324 return;
84f4ee90 325
af667a29 326 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 327 switch (adapter->rx_ps_pages) {
328 case 1:
329 case 2:
330 case 3:
331 /* [Extended] Packet Split Receive Descriptor Format
332 *
333 * +-----------------------------------------------------+
334 * 0 | Buffer Address 0 [63:0] |
335 * +-----------------------------------------------------+
336 * 8 | Buffer Address 1 [63:0] |
337 * +-----------------------------------------------------+
338 * 16 | Buffer Address 2 [63:0] |
339 * +-----------------------------------------------------+
340 * 24 | Buffer Address 3 [63:0] |
341 * +-----------------------------------------------------+
342 */
ef456f85 343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 344 /* [Extended] Receive Descriptor (Write-Back) Format
345 *
346 * 63 48 47 32 31 13 12 8 7 4 3 0
347 * +------------------------------------------------------+
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
349 * | Checksum | Ident | | Queue | | Type |
350 * +------------------------------------------------------+
351 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
352 * +------------------------------------------------------+
353 * 63 48 47 32 31 20 19 0
354 */
ef456f85 355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 356 for (i = 0; i < rx_ring->count; i++) {
ef456f85 357 const char *next_desc;
84f4ee90
TI		 358 buffer_info = &rx_ring->buffer_info[i];
359 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
360 u1 = (struct my_u1 *)rx_desc_ps;
361 staterr =
af667a29 362 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 363
364 if (i == rx_ring->next_to_use)
365 next_desc = " NTU";
366 else if (i == rx_ring->next_to_clean)
367 next_desc = " NTC";
368 else
369 next_desc = "";
370
84f4ee90
TI		 371 if (staterr & E1000_RXD_STAT_DD) {
372 /* Descriptor Done */
ef456f85
JK		 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
374 "RWB", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 buffer_info->skb, next_desc);
84f4ee90 380 } else {
ef456f85
JK		 381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
382 "R ", i,
383 (unsigned long long)le64_to_cpu(u1->a),
384 (unsigned long long)le64_to_cpu(u1->b),
385 (unsigned long long)le64_to_cpu(u1->c),
386 (unsigned long long)le64_to_cpu(u1->d),
387 (unsigned long long)buffer_info->dma,
388 buffer_info->skb, next_desc);
84f4ee90
TI		 389
390 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 391 e1000e_dump_ps_pages(adapter,
392 buffer_info);
84f4ee90 393 }
84f4ee90
TI		 394 }
395 break;
396 default:
397 case 0:
5f450212 398 /* Extended Receive Descriptor (Read) Format
84f4ee90 399 *
5f450212
BA		 400 * +-----------------------------------------------------+
401 * 0 | Buffer Address [63:0] |
402 * +-----------------------------------------------------+
403 * 8 | Reserved |
404 * +-----------------------------------------------------+
84f4ee90 405 */
ef456f85 406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 407 /* Extended Receive Descriptor (Write-Back) Format
408 *
409 * 63 48 47 32 31 24 23 4 3 0
410 * +------------------------------------------------------+
411 * | RSS Hash | | | |
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
413 * | Packet | IP | | | Type |
414 * | Checksum | Ident | | | |
415 * +------------------------------------------------------+
416 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
417 * +------------------------------------------------------+
418 * 63 48 47 32 31 20 19 0
419 */
ef456f85 420 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 421
422 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 423 const char *next_desc;
424
84f4ee90 425 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
427 u1 = (struct my_u1 *)rx_desc;
428 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 429
430 if (i == rx_ring->next_to_use)
431 next_desc = " NTU";
432 else if (i == rx_ring->next_to_clean)
433 next_desc = " NTC";
434 else
435 next_desc = "";
436
5f450212
BA		 437 if (staterr & E1000_RXD_STAT_DD) {
438 /* Descriptor Done */
ef456f85
JK		 439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
440 "RWB", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 buffer_info->skb, next_desc);
5f450212 444 } else {
ef456f85
JK		 445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
446 "R ", i,
447 (unsigned long long)le64_to_cpu(u1->a),
448 (unsigned long long)le64_to_cpu(u1->b),
449 (unsigned long long)buffer_info->dma,
450 buffer_info->skb, next_desc);
5f450212 451
f0c5dadf
ET		 452 if (netif_msg_pktdata(adapter) &&
453 buffer_info->skb)
5f450212
BA		 454 print_hex_dump(KERN_INFO, "",
455 DUMP_PREFIX_ADDRESS, 16,
456 1,
f0c5dadf 457 buffer_info->skb->data,
5f450212
BA		 458 adapter->rx_buffer_len,
459 true);
460 }
84f4ee90
TI		 461 }
462 }
84f4ee90
TI		 463}
464
bc7f75fa
AK		 465/**
466 * e1000_desc_unused - calculate if we have unused descriptors
467 **/
468static int e1000_desc_unused(struct e1000_ring *ring)
469{
470 if (ring->next_to_clean > ring->next_to_use)
471 return ring->next_to_clean - ring->next_to_use - 1;
472
473 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
474}
475
b67e1913
BA		 476/**
477 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
478 * @adapter: board private structure
479 * @hwtstamps: time stamp structure to update
480 * @systim: unsigned 64bit system time value.
481 *
482 * Convert the system time value stored in the RX/TXSTMP registers into a
483 * hwtstamp which can be used by the upper level time stamping functions.
484 *
485 * The 'systim_lock' spinlock is used to protect the consistency of the
486 * system time value. This is needed because reading the 64 bit time
487 * value involves reading two 32 bit registers. The first read latches the
488 * value.
489 **/
490static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
491 struct skb_shared_hwtstamps *hwtstamps,
492 u64 systim)
493{
494 u64 ns;
495 unsigned long flags;
496
497 spin_lock_irqsave(&adapter->systim_lock, flags);
498 ns = timecounter_cyc2time(&adapter->tc, systim);
499 spin_unlock_irqrestore(&adapter->systim_lock, flags);
500
501 memset(hwtstamps, 0, sizeof(*hwtstamps));
502 hwtstamps->hwtstamp = ns_to_ktime(ns);
503}
504
505/**
506 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
507 * @adapter: board private structure
508 * @status: descriptor extended error and status field
509 * @skb: particular skb to include time stamp
510 *
511 * If the time stamp is valid, convert it into the timecounter ns value
512 * and store that result into the shhwtstamps structure which is passed
513 * up the network stack.
514 **/
515static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
516 struct sk_buff *skb)
517{
518 struct e1000_hw *hw = &adapter->hw;
519 u64 rxstmp;
520
521 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
522 !(status & E1000_RXDEXT_STATERR_TST) ||
523 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
524 return;
525
526 /* The Rx time stamp registers contain the time stamp. No other
527 * received packet will be time stamped until the Rx time stamp
528 * registers are read. Because only one packet can be time stamped
529 * at a time, the register values must belong to this packet and
530 * therefore none of the other additional attributes need to be
531 * compared.
532 */
533 rxstmp = (u64)er32(RXSTMPL);
534 rxstmp |= (u64)er32(RXSTMPH) << 32;
535 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
536
537 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
538}
539
bc7f75fa 540/**
ad68076e 541 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 542 * @adapter: board private structure
b67e1913 543 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
545 * @skb: pointer to sk_buff to be indicated to stack
546 **/
547static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 548 struct net_device *netdev, struct sk_buff *skb,
b67e1913 549 u32 staterr, __le16 vlan)
bc7f75fa 550{
86d70e53 551 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 552
553 e1000e_rx_hwtstamp(adapter, staterr, skb);
554
bc7f75fa
AK		 555 skb->protocol = eth_type_trans(skb, netdev);
556
b67e1913 557 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 558 __vlan_hwaccel_put_tag(skb, tag);
559
560 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 561}
562
563/**
af667a29 564 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 565 * @adapter: board private structure
566 * @status_err: receive descriptor status and error fields
567 * @csum: receive descriptor csum field
568 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 569 **/
570static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 571 struct sk_buff *skb)
bc7f75fa
AK		 572{
573 u16 status = (u16)status_err;
574 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 575
576 skb_checksum_none_assert(skb);
bc7f75fa 577
afd12939
BA		 578 /* Rx checksum disabled */
579 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
580 return;
581
bc7f75fa
AK		 582 /* Ignore Checksum bit is set */
583 if (status & E1000_RXD_STAT_IXSM)
584 return;
afd12939 585
2e1706f2
BA		 586 /* TCP/UDP checksum error bit or IP checksum error bit is set */
587 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 588 /* let the stack verify checksum errors */
589 adapter->hw_csum_err++;
590 return;
591 }
592
593 /* TCP/UDP Checksum has not been calculated */
594 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
595 return;
596
597 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 598 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 599 adapter->hw_csum_good++;
600}
601
55aa6985 602static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 603{
55aa6985 604 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 605 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 606 s32 ret_val = __ew32_prepare(hw);
607
608 writel(i, rx_ring->tail);
c6e7f51e 609
bdc125f7 610 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 611 u32 rctl = er32(RCTL);
612 ew32(RCTL, rctl & ~E1000_RCTL_EN);
613 e_err("ME firmware caused invalid RDT - resetting\n");
614 schedule_work(&adapter->reset_task);
615 }
616}
617
55aa6985 618static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 619{
55aa6985 620 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 621 struct e1000_hw *hw = &adapter->hw;
bdc125f7 622 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 623
bdc125f7
BA		 624 writel(i, tx_ring->tail);
625
626 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 627 u32 tctl = er32(TCTL);
628 ew32(TCTL, tctl & ~E1000_TCTL_EN);
629 e_err("ME firmware caused invalid TDT - resetting\n");
630 schedule_work(&adapter->reset_task);
631 }
632}
633
bc7f75fa 634/**
5f450212 635 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 636 * @rx_ring: Rx descriptor ring
bc7f75fa 637 **/
55aa6985 638static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 639 int cleaned_count, gfp_t gfp)
bc7f75fa 640{
55aa6985 641 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 642 struct net_device *netdev = adapter->netdev;
643 struct pci_dev *pdev = adapter->pdev;
5f450212 644 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 645 struct e1000_buffer *buffer_info;
646 struct sk_buff *skb;
647 unsigned int i;
89d71a66 648 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 649
650 i = rx_ring->next_to_use;
651 buffer_info = &rx_ring->buffer_info[i];
652
653 while (cleaned_count--) {
654 skb = buffer_info->skb;
655 if (skb) {
656 skb_trim(skb, 0);
657 goto map_skb;
658 }
659
c2fed996 660 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 661 if (!skb) {
662 /* Better luck next round */
663 adapter->alloc_rx_buff_failed++;
664 break;
665 }
666
bc7f75fa
AK		 667 buffer_info->skb = skb;
668map_skb:
0be3f55f 669 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 670 adapter->rx_buffer_len,
0be3f55f
NN		 671 DMA_FROM_DEVICE);
672 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 673 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 674 adapter->rx_dma_failed++;
675 break;
676 }
677
5f450212
BA		 678 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
679 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 680
50849d79 681 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 682 /* Force memory writes to complete before letting h/w
50849d79
TH		 683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
685 * such as IA-64).
686 */
687 wmb();
c6e7f51e 688 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 689 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 690 else
c5083cf6 691 writel(i, rx_ring->tail);
50849d79 692 }
bc7f75fa
AK		 693 i++;
694 if (i == rx_ring->count)
695 i = 0;
696 buffer_info = &rx_ring->buffer_info[i];
697 }
698
50849d79 699 rx_ring->next_to_use = i;
bc7f75fa
AK		 700}
701
702/**
703 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 704 * @rx_ring: Rx descriptor ring
bc7f75fa 705 **/
55aa6985 706static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 707 int cleaned_count, gfp_t gfp)
bc7f75fa 708{
55aa6985 709 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 710 struct net_device *netdev = adapter->netdev;
711 struct pci_dev *pdev = adapter->pdev;
712 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 713 struct e1000_buffer *buffer_info;
714 struct e1000_ps_page *ps_page;
715 struct sk_buff *skb;
716 unsigned int i, j;
717
718 i = rx_ring->next_to_use;
719 buffer_info = &rx_ring->buffer_info[i];
720
721 while (cleaned_count--) {
722 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
723
724 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 725 ps_page = &buffer_info->ps_pages[j];
726 if (j >= adapter->rx_ps_pages) {
727 /* all unused desc entries get hw null ptr */
af667a29
BA		 728 rx_desc->read.buffer_addr[j + 1] =
729 ~cpu_to_le64(0);
47f44e40
AK		 730 continue;
731 }
732 if (!ps_page->page) {
c2fed996 733 ps_page->page = alloc_page(gfp);
bc7f75fa 734 if (!ps_page->page) {
47f44e40
AK		 735 adapter->alloc_rx_buff_failed++;
736 goto no_buffers;
737 }
0be3f55f
NN		 738 ps_page->dma = dma_map_page(&pdev->dev,
739 ps_page->page,
740 0, PAGE_SIZE,
741 DMA_FROM_DEVICE);
742 if (dma_mapping_error(&pdev->dev,
743 ps_page->dma)) {
47f44e40 744 dev_err(&adapter->pdev->dev,
af667a29 745 "Rx DMA page map failed\n");
47f44e40
AK		 746 adapter->rx_dma_failed++;
747 goto no_buffers;
bc7f75fa 748 }
bc7f75fa 749 }
e921eb1a 750 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 751 * didn't change because each write-back
752 * erases this info.
753 */
af667a29
BA		 754 rx_desc->read.buffer_addr[j + 1] =
755 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 756 }
757
c2fed996
JK		 758 skb = __netdev_alloc_skb_ip_align(netdev,
759 adapter->rx_ps_bsize0,
760 gfp);
bc7f75fa
AK		 761
762 if (!skb) {
763 adapter->alloc_rx_buff_failed++;
764 break;
765 }
766
bc7f75fa 767 buffer_info->skb = skb;
0be3f55f 768 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 769 adapter->rx_ps_bsize0,
0be3f55f
NN		 770 DMA_FROM_DEVICE);
771 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 772 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 773 adapter->rx_dma_failed++;
774 /* cleanup skb */
775 dev_kfree_skb_any(skb);
776 buffer_info->skb = NULL;
777 break;
778 }
779
780 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
781
50849d79 782 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 783 /* Force memory writes to complete before letting h/w
50849d79
TH		 784 * know there are new descriptors to fetch. (Only
785 * applicable for weak-ordered memory model archs,
786 * such as IA-64).
787 */
788 wmb();
c6e7f51e 789 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 790 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 791 else
c5083cf6 792 writel(i << 1, rx_ring->tail);
50849d79
TH		 793 }
794
bc7f75fa
AK		 795 i++;
796 if (i == rx_ring->count)
797 i = 0;
798 buffer_info = &rx_ring->buffer_info[i];
799 }
800
801no_buffers:
50849d79 802 rx_ring->next_to_use = i;
bc7f75fa
AK		 803}
804
97ac8cae
BA		 805/**
806 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 807 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 808 * @cleaned_count: number of buffers to allocate this pass
809 **/
810
55aa6985 811static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 812 int cleaned_count, gfp_t gfp)
97ac8cae 813{
55aa6985 814 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 815 struct net_device *netdev = adapter->netdev;
816 struct pci_dev *pdev = adapter->pdev;
5f450212 817 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 818 struct e1000_buffer *buffer_info;
819 struct sk_buff *skb;
820 unsigned int i;
2a2293b9 821 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 822
823 i = rx_ring->next_to_use;
824 buffer_info = &rx_ring->buffer_info[i];
825
826 while (cleaned_count--) {
827 skb = buffer_info->skb;
828 if (skb) {
829 skb_trim(skb, 0);
830 goto check_page;
831 }
832
c2fed996 833 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 834 if (unlikely(!skb)) {
835 /* Better luck next round */
836 adapter->alloc_rx_buff_failed++;
837 break;
838 }
839
97ac8cae
BA		 840 buffer_info->skb = skb;
841check_page:
842 /* allocate a new page if necessary */
843 if (!buffer_info->page) {
c2fed996 844 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 845 if (unlikely(!buffer_info->page)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
850
851 if (!buffer_info->dma)
0be3f55f 852 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 853 buffer_info->page, 0,
854 PAGE_SIZE,
0be3f55f 855 DMA_FROM_DEVICE);
97ac8cae 856
5f450212
BA		 857 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
858 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 859
860 if (unlikely(++i == rx_ring->count))
861 i = 0;
862 buffer_info = &rx_ring->buffer_info[i];
863 }
864
865 if (likely(rx_ring->next_to_use != i)) {
866 rx_ring->next_to_use = i;
867 if (unlikely(i-- == 0))
868 i = (rx_ring->count - 1);
869
870 /* Force memory writes to complete before letting h/w
871 * know there are new descriptors to fetch. (Only
872 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 873 * such as IA-64).
874 */
97ac8cae 875 wmb();
c6e7f51e 876 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 877 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 878 else
c5083cf6 879 writel(i, rx_ring->tail);
97ac8cae
BA		 880 }
881}
882
70495a50
BA		 883static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
884 struct sk_buff *skb)
885{
886 if (netdev->features & NETIF_F_RXHASH)
887 skb->rxhash = le32_to_cpu(rss);
888}
889
bc7f75fa 890/**
55aa6985
BA		 891 * e1000_clean_rx_irq - Send received data up the network stack
892 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 893 *
894 * the return value indicates whether actual cleaning was done, there
895 * is no guarantee that everything was cleaned
896 **/
55aa6985
BA		 897static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
898 int work_to_do)
bc7f75fa 899{
55aa6985 900 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 901 struct net_device *netdev = adapter->netdev;
902 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 903 struct e1000_hw *hw = &adapter->hw;
5f450212 904 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 905 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 906 u32 length, staterr;
bc7f75fa
AK		 907 unsigned int i;
908 int cleaned_count = 0;
3db1cd5c 909 bool cleaned = false;
bc7f75fa
AK		 910 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
911
912 i = rx_ring->next_to_clean;
5f450212
BA		 913 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
914 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 915 buffer_info = &rx_ring->buffer_info[i];
916
5f450212 917 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 918 struct sk_buff *skb;
bc7f75fa
AK		 919
920 if (*work_done >= work_to_do)
921 break;
922 (*work_done)++;
2d0bb1c1 923 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 924
bc7f75fa
AK		 925 skb = buffer_info->skb;
926 buffer_info->skb = NULL;
927
928 prefetch(skb->data - NET_IP_ALIGN);
929
930 i++;
931 if (i == rx_ring->count)
932 i = 0;
5f450212 933 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 934 prefetch(next_rxd);
935
936 next_buffer = &rx_ring->buffer_info[i];
937
3db1cd5c 938 cleaned = true;
bc7f75fa 939 cleaned_count++;
0be3f55f 940 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 941 buffer_info->dma,
942 adapter->rx_buffer_len,
0be3f55f 943 DMA_FROM_DEVICE);
bc7f75fa
AK		 944 buffer_info->dma = 0;
945
5f450212 946 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 947
e921eb1a 948 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 949 * packet, if that's the case we need to toss it. In fact, we
950 * need to toss every packet with the EOP bit clear and the
951 * next frame that _does_ have the EOP bit set, as it is by
952 * definition only a frame fragment
953 */
5f450212 954 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 955 adapter->flags2 |= FLAG2_IS_DISCARDING;
956
957 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 958 /* All receives must fit into a single buffer */
3bb99fe2 959 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 960 /* recycle */
961 buffer_info->skb = skb;
5f450212 962 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 963 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 964 goto next_desc;
965 }
966
cf955e6c
BG		 967 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
968 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 969 /* recycle */
970 buffer_info->skb = skb;
971 goto next_desc;
972 }
973
eb7c3adb 974 /* adjust length to remove Ethernet CRC */
0184039a
BG		 975 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
976 /* If configured to store CRC, don't subtract FCS,
977 * but keep the FCS bytes out of the total_rx_bytes
978 * counter
979 */
980 if (netdev->features & NETIF_F_RXFCS)
981 total_rx_bytes -= 4;
982 else
983 length -= 4;
984 }
eb7c3adb 985
bc7f75fa
AK		 986 total_rx_bytes += length;
987 total_rx_packets++;
988
e921eb1a 989 /* code added for copybreak, this should improve
bc7f75fa 990 * performance for small packets with large amounts
ad68076e
BA		 991 * of reassembly being done in the stack
992 */
bc7f75fa
AK		 993 if (length < copybreak) {
994 struct sk_buff *new_skb =
89d71a66 995 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 996 if (new_skb) {
808ff676
BA		 997 skb_copy_to_linear_data_offset(new_skb,
998 -NET_IP_ALIGN,
999 (skb->data -
1000 NET_IP_ALIGN),
1001 (length +
1002 NET_IP_ALIGN));
bc7f75fa
AK		 1003 /* save the skb in buffer_info as good */
1004 buffer_info->skb = skb;
1005 skb = new_skb;
1006 }
1007 /* else just continue with the old one */
1008 }
1009 /* end copybreak code */
1010 skb_put(skb, length);
1011
1012 /* Receive Checksum Offload */
2e1706f2 1013 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1014
70495a50
BA		 1015 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1016
5f450212
BA		 1017 e1000_receive_skb(adapter, netdev, skb, staterr,
1018 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1019
1020next_desc:
5f450212 1021 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1022
1023 /* return some buffers to hardware, one at a time is too slow */
1024 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1025 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1026 GFP_ATOMIC);
bc7f75fa
AK		 1027 cleaned_count = 0;
1028 }
1029
1030 /* use prefetched values */
1031 rx_desc = next_rxd;
1032 buffer_info = next_buffer;
5f450212
BA		 1033
1034 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1035 }
1036 rx_ring->next_to_clean = i;
1037
1038 cleaned_count = e1000_desc_unused(rx_ring);
1039 if (cleaned_count)
55aa6985 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1041
bc7f75fa 1042 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1043 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1044 return cleaned;
1045}
1046
55aa6985
BA		 1047static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1048 struct e1000_buffer *buffer_info)
bc7f75fa 1049{
55aa6985
BA		 1050 struct e1000_adapter *adapter = tx_ring->adapter;
1051
03b1320d
AD		 1052 if (buffer_info->dma) {
1053 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1054 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1055 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1056 else
0be3f55f
NN		 1057 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1058 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1059 buffer_info->dma = 0;
1060 }
bc7f75fa
AK		 1061 if (buffer_info->skb) {
1062 dev_kfree_skb_any(buffer_info->skb);
1063 buffer_info->skb = NULL;
1064 }
1b7719c4 1065 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1066}
1067
41cec6f1 1068static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1069{
41cec6f1
BA		 1070 struct e1000_adapter *adapter = container_of(work,
1071 struct e1000_adapter,
1072 print_hang_task);
09357b00 1073 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1074 struct e1000_ring *tx_ring = adapter->tx_ring;
1075 unsigned int i = tx_ring->next_to_clean;
1076 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1077 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1078 struct e1000_hw *hw = &adapter->hw;
1079 u16 phy_status, phy_1000t_status, phy_ext_status;
1080 u16 pci_status;
1081
615b32af
JB		 1082 if (test_bit(__E1000_DOWN, &adapter->state))
1083 return;
1084
09357b00
JK		 1085 if (!adapter->tx_hang_recheck &&
1086 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1087 /* May be block on write-back, flush and detect again
09357b00
JK		 1088 * flush pending descriptor writebacks to memory
1089 */
1090 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1091 /* execute the writes immediately */
1092 e1e_flush();
e921eb1a 1093 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1094 * the write is successful
1095 */
1096 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1097 /* execute the writes immediately */
1098 e1e_flush();
09357b00
JK		 1099 adapter->tx_hang_recheck = true;
1100 return;
1101 }
1102 /* Real hang detected */
1103 adapter->tx_hang_recheck = false;
1104 netif_stop_queue(netdev);
1105
c2ade1a4
BA		 1106 e1e_rphy(hw, MII_BMSR, &phy_status);
1107 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1108 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1109
41cec6f1
BA		 1110 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1111
1112 /* detected Hardware unit hang */
1113 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1114 " TDH <%x>\n"
1115 " TDT <%x>\n"
1116 " next_to_use <%x>\n"
1117 " next_to_clean <%x>\n"
1118 "buffer_info[next_to_clean]:\n"
1119 " time_stamp <%lx>\n"
1120 " next_to_watch <%x>\n"
1121 " jiffies <%lx>\n"
41cec6f1
BA		 1122 " next_to_watch.status <%x>\n"
1123 "MAC Status <%x>\n"
1124 "PHY Status <%x>\n"
1125 "PHY 1000BASE-T Status <%x>\n"
1126 "PHY Extended Status <%x>\n"
1127 "PCI Status <%x>\n",
c5083cf6
BA		 1128 readl(tx_ring->head),
1129 readl(tx_ring->tail),
44defeb3
JK		 1130 tx_ring->next_to_use,
1131 tx_ring->next_to_clean,
1132 tx_ring->buffer_info[eop].time_stamp,
1133 eop,
1134 jiffies,
41cec6f1
BA		 1135 eop_desc->upper.fields.status,
1136 er32(STATUS),
1137 phy_status,
1138 phy_1000t_status,
1139 phy_ext_status,
1140 pci_status);
7c0427ee
BA		 1141
1142 /* Suggest workaround for known h/w issue */
1143 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1144 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1145}
1146
b67e1913
BA		 1147/**
1148 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1149 * @work: pointer to work struct
1150 *
1151 * This work function polls the TSYNCTXCTL valid bit to determine when a
1152 * timestamp has been taken for the current stored skb. The timestamp must
1153 * be for this skb because only one such packet is allowed in the queue.
1154 */
1155static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1156{
1157 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1158 tx_hwtstamp_work);
1159 struct e1000_hw *hw = &adapter->hw;
1160
1161 if (!adapter->tx_hwtstamp_skb)
1162 return;
1163
1164 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1165 struct skb_shared_hwtstamps shhwtstamps;
1166 u64 txstmp;
1167
1168 txstmp = er32(TXSTMPL);
1169 txstmp |= (u64)er32(TXSTMPH) << 32;
1170
1171 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1172
1173 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1174 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1175 adapter->tx_hwtstamp_skb = NULL;
1176 } else {
1177 /* reschedule to check later */
1178 schedule_work(&adapter->tx_hwtstamp_work);
1179 }
1180}
1181
bc7f75fa
AK		 1182/**
1183 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1184 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1185 *
1186 * the return value indicates whether actual cleaning was done, there
1187 * is no guarantee that everything was cleaned
1188 **/
55aa6985 1189static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1190{
55aa6985 1191 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1192 struct net_device *netdev = adapter->netdev;
1193 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1194 struct e1000_tx_desc *tx_desc, *eop_desc;
1195 struct e1000_buffer *buffer_info;
1196 unsigned int i, eop;
1197 unsigned int count = 0;
bc7f75fa 1198 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1199 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1200
1201 i = tx_ring->next_to_clean;
1202 eop = tx_ring->buffer_info[i].next_to_watch;
1203 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1204
12d04a3c
AD		 1205 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1206 (count < tx_ring->count)) {
a86043c2 1207 bool cleaned = false;
2d0bb1c1 1208 rmb(); /* read buffer_info after eop_desc */
a86043c2 1209 for (; !cleaned; count++) {
bc7f75fa
AK		 1210 tx_desc = E1000_TX_DESC(*tx_ring, i);
1211 buffer_info = &tx_ring->buffer_info[i];
1212 cleaned = (i == eop);
1213
1214 if (cleaned) {
9ed318d5
TH		 1215 total_tx_packets += buffer_info->segs;
1216 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1217 if (buffer_info->skb) {
1218 bytes_compl += buffer_info->skb->len;
1219 pkts_compl++;
1220 }
bc7f75fa
AK		 1221 }
1222
55aa6985 1223 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1224 tx_desc->upper.data = 0;
1225
1226 i++;
1227 if (i == tx_ring->count)
1228 i = 0;
1229 }
1230
dac87619
TL		 1231 if (i == tx_ring->next_to_use)
1232 break;
bc7f75fa
AK		 1233 eop = tx_ring->buffer_info[i].next_to_watch;
1234 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1235 }
1236
1237 tx_ring->next_to_clean = i;
1238
3f0cfa3b
TH		 1239 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1240
bc7f75fa 1241#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1242 if (count && netif_carrier_ok(netdev) &&
1243 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1244 /* Make sure that anybody stopping the queue after this
1245 * sees the new next_to_clean.
1246 */
1247 smp_mb();
1248
1249 if (netif_queue_stopped(netdev) &&
1250 !(test_bit(__E1000_DOWN, &adapter->state))) {
1251 netif_wake_queue(netdev);
1252 ++adapter->restart_queue;
1253 }
1254 }
1255
1256 if (adapter->detect_tx_hung) {
e921eb1a 1257 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1258 * check with the clearing of time_stamp and movement of i
1259 */
3db1cd5c 1260 adapter->detect_tx_hung = false;
12d04a3c
AD		 1261 if (tx_ring->buffer_info[i].time_stamp &&
1262 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1263 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1264 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1265 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1266 else
1267 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1268 }
1269 adapter->total_tx_bytes += total_tx_bytes;
1270 adapter->total_tx_packets += total_tx_packets;
807540ba 1271 return count < tx_ring->count;
bc7f75fa
AK		 1272}
1273
bc7f75fa
AK		 1274/**
1275 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1276 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1277 *
1278 * the return value indicates whether actual cleaning was done, there
1279 * is no guarantee that everything was cleaned
1280 **/
55aa6985
BA		 1281static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1282 int work_to_do)
bc7f75fa 1283{
55aa6985 1284 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1285 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1286 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1287 struct net_device *netdev = adapter->netdev;
1288 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1289 struct e1000_buffer *buffer_info, *next_buffer;
1290 struct e1000_ps_page *ps_page;
1291 struct sk_buff *skb;
1292 unsigned int i, j;
1293 u32 length, staterr;
1294 int cleaned_count = 0;
3db1cd5c 1295 bool cleaned = false;
bc7f75fa
AK		 1296 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1297
1298 i = rx_ring->next_to_clean;
1299 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1300 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1301 buffer_info = &rx_ring->buffer_info[i];
1302
1303 while (staterr & E1000_RXD_STAT_DD) {
1304 if (*work_done >= work_to_do)
1305 break;
1306 (*work_done)++;
1307 skb = buffer_info->skb;
2d0bb1c1 1308 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1309
1310 /* in the packet split case this is header only */
1311 prefetch(skb->data - NET_IP_ALIGN);
1312
1313 i++;
1314 if (i == rx_ring->count)
1315 i = 0;
1316 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1317 prefetch(next_rxd);
1318
1319 next_buffer = &rx_ring->buffer_info[i];
1320
3db1cd5c 1321 cleaned = true;
bc7f75fa 1322 cleaned_count++;
0be3f55f 1323 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1324 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1325 buffer_info->dma = 0;
1326
af667a29 1327 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1328 if (!(staterr & E1000_RXD_STAT_EOP))
1329 adapter->flags2 |= FLAG2_IS_DISCARDING;
1330
1331 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1332 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1333 dev_kfree_skb_irq(skb);
b94b5028
JB		 1334 if (staterr & E1000_RXD_STAT_EOP)
1335 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1336 goto next_desc;
1337 }
1338
cf955e6c
BG		 1339 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1340 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1341 dev_kfree_skb_irq(skb);
1342 goto next_desc;
1343 }
1344
1345 length = le16_to_cpu(rx_desc->wb.middle.length0);
1346
1347 if (!length) {
ef456f85 1348 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1349 dev_kfree_skb_irq(skb);
1350 goto next_desc;
1351 }
1352
1353 /* Good Receive */
1354 skb_put(skb, length);
1355
1356 {
e921eb1a 1357 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1358 * it more efficient than reusing j
1359 */
1360 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1361
e921eb1a 1362 /* page alloc/put takes too long and effects small
0e15df49
BA		 1363 * packet throughput, so unsplit small packets and
1364 * save the alloc/put only valid in softirq (napi)
1365 * context to call kmap_*
ad68076e 1366 */
0e15df49
BA		 1367 if (l1 && (l1 <= copybreak) &&
1368 ((length + l1) <= adapter->rx_ps_bsize0)) {
1369 u8 *vaddr;
1370
1371 ps_page = &buffer_info->ps_pages[0];
1372
e921eb1a 1373 /* there is no documentation about how to call
0e15df49
BA		 1374 * kmap_atomic, so we can't hold the mapping
1375 * very long
1376 */
1377 dma_sync_single_for_cpu(&pdev->dev,
1378 ps_page->dma,
1379 PAGE_SIZE,
1380 DMA_FROM_DEVICE);
9f393834 1381 vaddr = kmap_atomic(ps_page->page);
0e15df49 1382 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1383 kunmap_atomic(vaddr);
0e15df49
BA		 1384 dma_sync_single_for_device(&pdev->dev,
1385 ps_page->dma,
1386 PAGE_SIZE,
1387 DMA_FROM_DEVICE);
1388
1389 /* remove the CRC */
0184039a
BG		 1390 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1391 if (!(netdev->features & NETIF_F_RXFCS))
1392 l1 -= 4;
1393 }
0e15df49
BA		 1394
1395 skb_put(skb, l1);
1396 goto copydone;
1397 } /* if */
bc7f75fa
AK		 1398 }
1399
1400 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1401 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1402 if (!length)
1403 break;
1404
47f44e40 1405 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1406 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1407 DMA_FROM_DEVICE);
bc7f75fa
AK		 1408 ps_page->dma = 0;
1409 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1410 ps_page->page = NULL;
1411 skb->len += length;
1412 skb->data_len += length;
98a045d7 1413 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1414 }
1415
eb7c3adb
JK		 1416 /* strip the ethernet crc, problem is we're using pages now so
1417 * this whole operation can get a little cpu intensive
1418 */
0184039a
BG		 1419 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1420 if (!(netdev->features & NETIF_F_RXFCS))
1421 pskb_trim(skb, skb->len - 4);
1422 }
eb7c3adb 1423
bc7f75fa
AK		 1424copydone:
1425 total_rx_bytes += skb->len;
1426 total_rx_packets++;
1427
2e1706f2 1428 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1429
70495a50
BA		 1430 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1431
bc7f75fa
AK		 1432 if (rx_desc->wb.upper.header_status &
1433 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1434 adapter->rx_hdr_split++;
1435
b67e1913
BA		 1436 e1000_receive_skb(adapter, netdev, skb, staterr,
1437 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1438
1439next_desc:
1440 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1441 buffer_info->skb = NULL;
1442
1443 /* return some buffers to hardware, one at a time is too slow */
1444 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1445 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1446 GFP_ATOMIC);
bc7f75fa
AK		 1447 cleaned_count = 0;
1448 }
1449
1450 /* use prefetched values */
1451 rx_desc = next_rxd;
1452 buffer_info = next_buffer;
1453
1454 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1455 }
1456 rx_ring->next_to_clean = i;
1457
1458 cleaned_count = e1000_desc_unused(rx_ring);
1459 if (cleaned_count)
55aa6985 1460 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1461
bc7f75fa 1462 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1463 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1464 return cleaned;
1465}
1466
97ac8cae
BA		 1467/**
1468 * e1000_consume_page - helper function
1469 **/
1470static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1471 u16 length)
1472{
1473 bi->page = NULL;
1474 skb->len += length;
1475 skb->data_len += length;
98a045d7 1476 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1477}
1478
1479/**
1480 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1481 * @adapter: board private structure
1482 *
1483 * the return value indicates whether actual cleaning was done, there
1484 * is no guarantee that everything was cleaned
1485 **/
55aa6985
BA		 1486static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1487 int work_to_do)
97ac8cae 1488{
55aa6985 1489 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1490 struct net_device *netdev = adapter->netdev;
1491 struct pci_dev *pdev = adapter->pdev;
5f450212 1492 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1493 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1494 u32 length, staterr;
97ac8cae
BA		 1495 unsigned int i;
1496 int cleaned_count = 0;
1497 bool cleaned = false;
1498 unsigned int total_rx_bytes=0, total_rx_packets=0;
1499
1500 i = rx_ring->next_to_clean;
5f450212
BA		 1501 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1502 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1503 buffer_info = &rx_ring->buffer_info[i];
1504
5f450212 1505 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1506 struct sk_buff *skb;
97ac8cae
BA		 1507
1508 if (*work_done >= work_to_do)
1509 break;
1510 (*work_done)++;
2d0bb1c1 1511 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1512
97ac8cae
BA		 1513 skb = buffer_info->skb;
1514 buffer_info->skb = NULL;
1515
1516 ++i;
1517 if (i == rx_ring->count)
1518 i = 0;
5f450212 1519 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1520 prefetch(next_rxd);
1521
1522 next_buffer = &rx_ring->buffer_info[i];
1523
1524 cleaned = true;
1525 cleaned_count++;
0be3f55f
NN		 1526 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1527 DMA_FROM_DEVICE);
97ac8cae
BA		 1528 buffer_info->dma = 0;
1529
5f450212 1530 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1531
1532 /* errors is only valid for DD + EOP descriptors */
5f450212 1533 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1534 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1535 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1536 /* recycle both page and skb */
1537 buffer_info->skb = skb;
1538 /* an error means any chain goes out the window too */
1539 if (rx_ring->rx_skb_top)
1540 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1541 rx_ring->rx_skb_top = NULL;
1542 goto next_desc;
97ac8cae
BA		 1543 }
1544
f0f1a172 1545#define rxtop (rx_ring->rx_skb_top)
5f450212 1546 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1547 /* this descriptor is only the beginning (or middle) */
1548 if (!rxtop) {
1549 /* this is the beginning of a chain */
1550 rxtop = skb;
1551 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1552 0, length);
1553 } else {
1554 /* this is the middle of a chain */
1555 skb_fill_page_desc(rxtop,
1556 skb_shinfo(rxtop)->nr_frags,
1557 buffer_info->page, 0, length);
1558 /* re-use the skb, only consumed the page */
1559 buffer_info->skb = skb;
1560 }
1561 e1000_consume_page(buffer_info, rxtop, length);
1562 goto next_desc;
1563 } else {
1564 if (rxtop) {
1565 /* end of the chain */
1566 skb_fill_page_desc(rxtop,
1567 skb_shinfo(rxtop)->nr_frags,
1568 buffer_info->page, 0, length);
1569 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1570 * page
1571 */
97ac8cae
BA		 1572 buffer_info->skb = skb;
1573 skb = rxtop;
1574 rxtop = NULL;
1575 e1000_consume_page(buffer_info, skb, length);
1576 } else {
1577 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1578 * copybreak to save the put_page/alloc_page
1579 */
97ac8cae
BA		 1580 if (length <= copybreak &&
1581 skb_tailroom(skb) >= length) {
1582 u8 *vaddr;
4679026d 1583 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1584 memcpy(skb_tail_pointer(skb), vaddr,
1585 length);
4679026d 1586 kunmap_atomic(vaddr);
97ac8cae 1587 /* re-use the page, so don't erase
e921eb1a
BA		 1588 * buffer_info->page
1589 */
97ac8cae
BA		 1590 skb_put(skb, length);
1591 } else {
1592 skb_fill_page_desc(skb, 0,
1593 buffer_info->page, 0,
1594 length);
1595 e1000_consume_page(buffer_info, skb,
1596 length);
1597 }
1598 }
1599 }
1600
2e1706f2
BA		 1601 /* Receive Checksum Offload */
1602 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1603
70495a50
BA		 1604 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1605
97ac8cae
BA		 1606 /* probably a little skewed due to removing CRC */
1607 total_rx_bytes += skb->len;
1608 total_rx_packets++;
1609
1610 /* eth type trans needs skb->data to point to something */
1611 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1612 e_err("pskb_may_pull failed.\n");
ef5ab89c 1613 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1614 goto next_desc;
1615 }
1616
5f450212
BA		 1617 e1000_receive_skb(adapter, netdev, skb, staterr,
1618 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1619
1620next_desc:
5f450212 1621 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1622
1623 /* return some buffers to hardware, one at a time is too slow */
1624 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1625 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1626 GFP_ATOMIC);
97ac8cae
BA		 1627 cleaned_count = 0;
1628 }
1629
1630 /* use prefetched values */
1631 rx_desc = next_rxd;
1632 buffer_info = next_buffer;
5f450212
BA		 1633
1634 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1635 }
1636 rx_ring->next_to_clean = i;
1637
1638 cleaned_count = e1000_desc_unused(rx_ring);
1639 if (cleaned_count)
55aa6985 1640 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1641
1642 adapter->total_rx_bytes += total_rx_bytes;
1643 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1644 return cleaned;
1645}
1646
bc7f75fa
AK		 1647/**
1648 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1649 * @rx_ring: Rx descriptor ring
bc7f75fa 1650 **/
55aa6985 1651static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1652{
55aa6985 1653 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1654 struct e1000_buffer *buffer_info;
1655 struct e1000_ps_page *ps_page;
1656 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1657 unsigned int i, j;
1658
1659 /* Free all the Rx ring sk_buffs */
1660 for (i = 0; i < rx_ring->count; i++) {
1661 buffer_info = &rx_ring->buffer_info[i];
1662 if (buffer_info->dma) {
1663 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1664 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1665 adapter->rx_buffer_len,
0be3f55f 1666 DMA_FROM_DEVICE);
97ac8cae 1667 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1668 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1669 PAGE_SIZE,
0be3f55f 1670 DMA_FROM_DEVICE);
bc7f75fa 1671 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1672 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1673 adapter->rx_ps_bsize0,
0be3f55f 1674 DMA_FROM_DEVICE);
bc7f75fa
AK		 1675 buffer_info->dma = 0;
1676 }
1677
97ac8cae
BA		 1678 if (buffer_info->page) {
1679 put_page(buffer_info->page);
1680 buffer_info->page = NULL;
1681 }
1682
bc7f75fa
AK		 1683 if (buffer_info->skb) {
1684 dev_kfree_skb(buffer_info->skb);
1685 buffer_info->skb = NULL;
1686 }
1687
1688 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1689 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1690 if (!ps_page->page)
1691 break;
0be3f55f
NN		 1692 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1693 DMA_FROM_DEVICE);
bc7f75fa
AK		 1694 ps_page->dma = 0;
1695 put_page(ps_page->page);
1696 ps_page->page = NULL;
1697 }
1698 }
1699
1700 /* there also may be some cached data from a chained receive */
1701 if (rx_ring->rx_skb_top) {
1702 dev_kfree_skb(rx_ring->rx_skb_top);
1703 rx_ring->rx_skb_top = NULL;
1704 }
1705
bc7f75fa
AK		 1706 /* Zero out the descriptor ring */
1707 memset(rx_ring->desc, 0, rx_ring->size);
1708
1709 rx_ring->next_to_clean = 0;
1710 rx_ring->next_to_use = 0;
b94b5028 1711 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1712
c5083cf6 1713 writel(0, rx_ring->head);
bdc125f7
BA		 1714 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1715 e1000e_update_rdt_wa(rx_ring, 0);
1716 else
1717 writel(0, rx_ring->tail);
bc7f75fa
AK		 1718}
1719
a8f88ff5
JB		 1720static void e1000e_downshift_workaround(struct work_struct *work)
1721{
1722 struct e1000_adapter *adapter = container_of(work,
1723 struct e1000_adapter, downshift_task);
1724
615b32af
JB		 1725 if (test_bit(__E1000_DOWN, &adapter->state))
1726 return;
1727
a8f88ff5
JB		 1728 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1729}
1730
bc7f75fa
AK		 1731/**
1732 * e1000_intr_msi - Interrupt Handler
1733 * @irq: interrupt number
1734 * @data: pointer to a network interface device structure
1735 **/
8bb62869 1736static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1737{
1738 struct net_device *netdev = data;
1739 struct e1000_adapter *adapter = netdev_priv(netdev);
1740 struct e1000_hw *hw = &adapter->hw;
1741 u32 icr = er32(ICR);
1742
e921eb1a 1743 /* read ICR disables interrupts using IAM */
573cca8c 1744 if (icr & E1000_ICR_LSC) {
f92518dd 1745 hw->mac.get_link_status = true;
e921eb1a 1746 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1747 * disconnect (LSC) before accessing any PHY registers
1748 */
bc7f75fa
AK		 1749 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1750 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1751 schedule_work(&adapter->downshift_task);
bc7f75fa 1752
e921eb1a 1753 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1754 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1755 * adapter in watchdog
1756 */
bc7f75fa
AK		 1757 if (netif_carrier_ok(netdev) &&
1758 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1759 /* disable receives */
1760 u32 rctl = er32(RCTL);
1761 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1762 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1763 }
1764 /* guard against interrupt when we're going down */
1765 if (!test_bit(__E1000_DOWN, &adapter->state))
1766 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1767 }
1768
94fb848b
BA		 1769 /* Reset on uncorrectable ECC error */
1770 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1771 u32 pbeccsts = er32(PBECCSTS);
1772
1773 adapter->corr_errors +=
1774 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1775 adapter->uncorr_errors +=
1776 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1777 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1778
1779 /* Do the reset outside of interrupt context */
1780 schedule_work(&adapter->reset_task);
1781
1782 /* return immediately since reset is imminent */
1783 return IRQ_HANDLED;
1784 }
1785
288379f0 1786 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1787 adapter->total_tx_bytes = 0;
1788 adapter->total_tx_packets = 0;
1789 adapter->total_rx_bytes = 0;
1790 adapter->total_rx_packets = 0;
288379f0 1791 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1792 }
1793
1794 return IRQ_HANDLED;
1795}
1796
1797/**
1798 * e1000_intr - Interrupt Handler
1799 * @irq: interrupt number
1800 * @data: pointer to a network interface device structure
1801 **/
8bb62869 1802static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1803{
1804 struct net_device *netdev = data;
1805 struct e1000_adapter *adapter = netdev_priv(netdev);
1806 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1807 u32 rctl, icr = er32(ICR);
4662e82b 1808
a68ea775 1809 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1810 return IRQ_NONE; /* Not our interrupt */
1811
e921eb1a 1812 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1813 * not set, then the adapter didn't send an interrupt
1814 */
bc7f75fa
AK		 1815 if (!(icr & E1000_ICR_INT_ASSERTED))
1816 return IRQ_NONE;
1817
e921eb1a 1818 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1819 * interrupts are masked. No need for the
1820 * IMC write
1821 */
bc7f75fa 1822
573cca8c 1823 if (icr & E1000_ICR_LSC) {
f92518dd 1824 hw->mac.get_link_status = true;
e921eb1a 1825 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1826 * disconnect (LSC) before accessing any PHY registers
1827 */
bc7f75fa
AK		 1828 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1829 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1830 schedule_work(&adapter->downshift_task);
bc7f75fa 1831
e921eb1a 1832 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1833 * For packet buffer work-around on link down event;
1834 * disable receives here in the ISR and
1835 * reset adapter in watchdog
1836 */
1837 if (netif_carrier_ok(netdev) &&
1838 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1839 /* disable receives */
1840 rctl = er32(RCTL);
1841 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1842 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1843 }
1844 /* guard against interrupt when we're going down */
1845 if (!test_bit(__E1000_DOWN, &adapter->state))
1846 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1847 }
1848
94fb848b
BA		 1849 /* Reset on uncorrectable ECC error */
1850 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1851 u32 pbeccsts = er32(PBECCSTS);
1852
1853 adapter->corr_errors +=
1854 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1855 adapter->uncorr_errors +=
1856 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1857 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1858
1859 /* Do the reset outside of interrupt context */
1860 schedule_work(&adapter->reset_task);
1861
1862 /* return immediately since reset is imminent */
1863 return IRQ_HANDLED;
1864 }
1865
288379f0 1866 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1867 adapter->total_tx_bytes = 0;
1868 adapter->total_tx_packets = 0;
1869 adapter->total_rx_bytes = 0;
1870 adapter->total_rx_packets = 0;
288379f0 1871 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1872 }
1873
1874 return IRQ_HANDLED;
1875}
1876
8bb62869 1877static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1878{
1879 struct net_device *netdev = data;
1880 struct e1000_adapter *adapter = netdev_priv(netdev);
1881 struct e1000_hw *hw = &adapter->hw;
1882 u32 icr = er32(ICR);
1883
1884 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1885 if (!test_bit(__E1000_DOWN, &adapter->state))
1886 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1887 return IRQ_NONE;
1888 }
1889
1890 if (icr & adapter->eiac_mask)
1891 ew32(ICS, (icr & adapter->eiac_mask));
1892
1893 if (icr & E1000_ICR_OTHER) {
1894 if (!(icr & E1000_ICR_LSC))
1895 goto no_link_interrupt;
f92518dd 1896 hw->mac.get_link_status = true;
4662e82b
BA		 1897 /* guard against interrupt when we're going down */
1898 if (!test_bit(__E1000_DOWN, &adapter->state))
1899 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1900 }
1901
1902no_link_interrupt:
a3c69fef
JB		 1903 if (!test_bit(__E1000_DOWN, &adapter->state))
1904 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1905
1906 return IRQ_HANDLED;
1907}
1908
8bb62869 1909static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1910{
1911 struct net_device *netdev = data;
1912 struct e1000_adapter *adapter = netdev_priv(netdev);
1913 struct e1000_hw *hw = &adapter->hw;
1914 struct e1000_ring *tx_ring = adapter->tx_ring;
1915
1916
1917 adapter->total_tx_bytes = 0;
1918 adapter->total_tx_packets = 0;
1919
55aa6985 1920 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1921 /* Ring was not completely cleaned, so fire another interrupt */
1922 ew32(ICS, tx_ring->ims_val);
1923
1924 return IRQ_HANDLED;
1925}
1926
8bb62869 1927static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1928{
1929 struct net_device *netdev = data;
1930 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1931 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1932
1933 /* Write the ITR value calculated at the end of the
1934 * previous interrupt.
1935 */
55aa6985
BA		 1936 if (rx_ring->set_itr) {
1937 writel(1000000000 / (rx_ring->itr_val * 256),
1938 rx_ring->itr_register);
1939 rx_ring->set_itr = 0;
4662e82b
BA		 1940 }
1941
288379f0 1942 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1943 adapter->total_rx_bytes = 0;
1944 adapter->total_rx_packets = 0;
288379f0 1945 __napi_schedule(&adapter->napi);
4662e82b
BA		 1946 }
1947 return IRQ_HANDLED;
1948}
1949
1950/**
1951 * e1000_configure_msix - Configure MSI-X hardware
1952 *
1953 * e1000_configure_msix sets up the hardware to properly
1954 * generate MSI-X interrupts.
1955 **/
1956static void e1000_configure_msix(struct e1000_adapter *adapter)
1957{
1958 struct e1000_hw *hw = &adapter->hw;
1959 struct e1000_ring *rx_ring = adapter->rx_ring;
1960 struct e1000_ring *tx_ring = adapter->tx_ring;
1961 int vector = 0;
1962 u32 ctrl_ext, ivar = 0;
1963
1964 adapter->eiac_mask = 0;
1965
1966 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1967 if (hw->mac.type == e1000_82574) {
1968 u32 rfctl = er32(RFCTL);
1969 rfctl |= E1000_RFCTL_ACK_DIS;
1970 ew32(RFCTL, rfctl);
1971 }
1972
1973#define E1000_IVAR_INT_ALLOC_VALID 0x8
1974 /* Configure Rx vector */
1975 rx_ring->ims_val = E1000_IMS_RXQ0;
1976 adapter->eiac_mask |= rx_ring->ims_val;
1977 if (rx_ring->itr_val)
1978 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1979 rx_ring->itr_register);
4662e82b 1980 else
c5083cf6 1981 writel(1, rx_ring->itr_register);
4662e82b
BA		 1982 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1983
1984 /* Configure Tx vector */
1985 tx_ring->ims_val = E1000_IMS_TXQ0;
1986 vector++;
1987 if (tx_ring->itr_val)
1988 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1989 tx_ring->itr_register);
4662e82b 1990 else
c5083cf6 1991 writel(1, tx_ring->itr_register);
4662e82b
BA		 1992 adapter->eiac_mask |= tx_ring->ims_val;
1993 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1994
1995 /* set vector for Other Causes, e.g. link changes */
1996 vector++;
1997 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1998 if (rx_ring->itr_val)
1999 writel(1000000000 / (rx_ring->itr_val * 256),
2000 hw->hw_addr + E1000_EITR_82574(vector));
2001 else
2002 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2003
2004 /* Cause Tx interrupts on every write back */
2005 ivar |= (1 << 31);
2006
2007 ew32(IVAR, ivar);
2008
2009 /* enable MSI-X PBA support */
2010 ctrl_ext = er32(CTRL_EXT);
2011 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2012
2013 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2014 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2015 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2016 ew32(CTRL_EXT, ctrl_ext);
2017 e1e_flush();
2018}
2019
2020void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2021{
2022 if (adapter->msix_entries) {
2023 pci_disable_msix(adapter->pdev);
2024 kfree(adapter->msix_entries);
2025 adapter->msix_entries = NULL;
2026 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2027 pci_disable_msi(adapter->pdev);
2028 adapter->flags &= ~FLAG_MSI_ENABLED;
2029 }
4662e82b
BA		 2030}
2031
2032/**
2033 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2034 *
2035 * Attempt to configure interrupts using the best available
2036 * capabilities of the hardware and kernel.
2037 **/
2038void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2039{
2040 int err;
8e86acd7 2041 int i;
4662e82b
BA		 2042
2043 switch (adapter->int_mode) {
2044 case E1000E_INT_MODE_MSIX:
2045 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2046 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2047 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 2048 sizeof(struct msix_entry),
2049 GFP_KERNEL);
2050 if (adapter->msix_entries) {
8e86acd7 2051 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2052 adapter->msix_entries[i].entry = i;
2053
2054 err = pci_enable_msix(adapter->pdev,
2055 adapter->msix_entries,
8e86acd7 2056 adapter->num_vectors);
b1cdfead 2057 if (err == 0)
4662e82b
BA		 2058 return;
2059 }
2060 /* MSI-X failed, so fall through and try MSI */
ef456f85 2061 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2062 e1000e_reset_interrupt_capability(adapter);
2063 }
2064 adapter->int_mode = E1000E_INT_MODE_MSI;
2065 /* Fall through */
2066 case E1000E_INT_MODE_MSI:
2067 if (!pci_enable_msi(adapter->pdev)) {
2068 adapter->flags |= FLAG_MSI_ENABLED;
2069 } else {
2070 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2071 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2072 }
2073 /* Fall through */
2074 case E1000E_INT_MODE_LEGACY:
2075 /* Don't do anything; this is the system default */
2076 break;
2077 }
8e86acd7
JK		 2078
2079 /* store the number of vectors being used */
2080 adapter->num_vectors = 1;
4662e82b
BA		 2081}
2082
2083/**
2084 * e1000_request_msix - Initialize MSI-X interrupts
2085 *
2086 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2087 * kernel.
2088 **/
2089static int e1000_request_msix(struct e1000_adapter *adapter)
2090{
2091 struct net_device *netdev = adapter->netdev;
2092 int err = 0, vector = 0;
2093
2094 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2095 snprintf(adapter->rx_ring->name,
2096 sizeof(adapter->rx_ring->name) - 1,
2097 "%s-rx-0", netdev->name);
4662e82b
BA		 2098 else
2099 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2100 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2101 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2102 netdev);
2103 if (err)
5015e53a 2104 return err;
c5083cf6
BA		 2105 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2106 E1000_EITR_82574(vector);
4662e82b
BA		 2107 adapter->rx_ring->itr_val = adapter->itr;
2108 vector++;
2109
2110 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2111 snprintf(adapter->tx_ring->name,
2112 sizeof(adapter->tx_ring->name) - 1,
2113 "%s-tx-0", netdev->name);
4662e82b
BA		 2114 else
2115 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2116 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2117 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2118 netdev);
2119 if (err)
5015e53a 2120 return err;
c5083cf6
BA		 2121 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2122 E1000_EITR_82574(vector);
4662e82b
BA		 2123 adapter->tx_ring->itr_val = adapter->itr;
2124 vector++;
2125
2126 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2127 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2128 if (err)
5015e53a 2129 return err;
4662e82b
BA		 2130
2131 e1000_configure_msix(adapter);
5015e53a 2132
4662e82b 2133 return 0;
4662e82b
BA		 2134}
2135
f8d59f78
BA		 2136/**
2137 * e1000_request_irq - initialize interrupts
2138 *
2139 * Attempts to configure interrupts using the best available
2140 * capabilities of the hardware and kernel.
2141 **/
bc7f75fa
AK		 2142static int e1000_request_irq(struct e1000_adapter *adapter)
2143{
2144 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2145 int err;
2146
4662e82b
BA		 2147 if (adapter->msix_entries) {
2148 err = e1000_request_msix(adapter);
2149 if (!err)
2150 return err;
2151 /* fall back to MSI */
2152 e1000e_reset_interrupt_capability(adapter);
2153 adapter->int_mode = E1000E_INT_MODE_MSI;
2154 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2155 }
4662e82b 2156 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2157 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2158 netdev->name, netdev);
2159 if (!err)
2160 return err;
bc7f75fa 2161
4662e82b
BA		 2162 /* fall back to legacy interrupt */
2163 e1000e_reset_interrupt_capability(adapter);
2164 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2165 }
2166
a0607fd3 2167 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2168 netdev->name, netdev);
2169 if (err)
2170 e_err("Unable to allocate interrupt, Error: %d\n", err);
2171
bc7f75fa
AK		 2172 return err;
2173}
2174
2175static void e1000_free_irq(struct e1000_adapter *adapter)
2176{
2177 struct net_device *netdev = adapter->netdev;
2178
4662e82b
BA		 2179 if (adapter->msix_entries) {
2180 int vector = 0;
2181
2182 free_irq(adapter->msix_entries[vector].vector, netdev);
2183 vector++;
2184
2185 free_irq(adapter->msix_entries[vector].vector, netdev);
2186 vector++;
2187
2188 /* Other Causes interrupt vector */
2189 free_irq(adapter->msix_entries[vector].vector, netdev);
2190 return;
bc7f75fa 2191 }
4662e82b
BA		 2192
2193 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2194}
2195
2196/**
2197 * e1000_irq_disable - Mask off interrupt generation on the NIC
2198 **/
2199static void e1000_irq_disable(struct e1000_adapter *adapter)
2200{
2201 struct e1000_hw *hw = &adapter->hw;
2202
bc7f75fa 2203 ew32(IMC, ~0);
4662e82b
BA		 2204 if (adapter->msix_entries)
2205 ew32(EIAC_82574, 0);
bc7f75fa 2206 e1e_flush();
8e86acd7
JK		 2207
2208 if (adapter->msix_entries) {
2209 int i;
2210 for (i = 0; i < adapter->num_vectors; i++)
2211 synchronize_irq(adapter->msix_entries[i].vector);
2212 } else {
2213 synchronize_irq(adapter->pdev->irq);
2214 }
bc7f75fa
AK		 2215}
2216
2217/**
2218 * e1000_irq_enable - Enable default interrupt generation settings
2219 **/
2220static void e1000_irq_enable(struct e1000_adapter *adapter)
2221{
2222 struct e1000_hw *hw = &adapter->hw;
2223
4662e82b
BA		 2224 if (adapter->msix_entries) {
2225 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2226 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2227 } else if (hw->mac.type == e1000_pch_lpt) {
2228 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2229 } else {
2230 ew32(IMS, IMS_ENABLE_MASK);
2231 }
74ef9c39 2232 e1e_flush();
bc7f75fa
AK		 2233}
2234
2235/**
31dbe5b4 2236 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2237 * @adapter: address of board private structure
2238 *
31dbe5b4 2239 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2240 * For ASF and Pass Through versions of f/w this means that
2241 * the driver is loaded. For AMT version (only with 82573)
2242 * of the f/w this means that the network i/f is open.
2243 **/
31dbe5b4 2244void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2245{
2246 struct e1000_hw *hw = &adapter->hw;
2247 u32 ctrl_ext;
2248 u32 swsm;
2249
2250 /* Let firmware know the driver has taken over */
2251 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2252 swsm = er32(SWSM);
2253 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2254 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2255 ctrl_ext = er32(CTRL_EXT);
ad68076e 2256 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2257 }
2258}
2259
2260/**
31dbe5b4 2261 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2262 * @adapter: address of board private structure
2263 *
31dbe5b4 2264 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2265 * For ASF and Pass Through versions of f/w this means that the
2266 * driver is no longer loaded. For AMT version (only with 82573) i
2267 * of the f/w this means that the network i/f is closed.
2268 *
2269 **/
31dbe5b4 2270void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2271{
2272 struct e1000_hw *hw = &adapter->hw;
2273 u32 ctrl_ext;
2274 u32 swsm;
2275
2276 /* Let firmware taken over control of h/w */
2277 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2278 swsm = er32(SWSM);
2279 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2280 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2281 ctrl_ext = er32(CTRL_EXT);
ad68076e 2282 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2283 }
2284}
2285
bc7f75fa 2286/**
49ce9c2c 2287 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2288 **/
2289static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2290 struct e1000_ring *ring)
2291{
2292 struct pci_dev *pdev = adapter->pdev;
2293
2294 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2295 GFP_KERNEL);
2296 if (!ring->desc)
2297 return -ENOMEM;
2298
2299 return 0;
2300}
2301
2302/**
2303 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2304 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2305 *
2306 * Return 0 on success, negative on failure
2307 **/
55aa6985 2308int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2309{
55aa6985 2310 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2311 int err = -ENOMEM, size;
2312
2313 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2314 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2315 if (!tx_ring->buffer_info)
2316 goto err;
bc7f75fa
AK		 2317
2318 /* round up to nearest 4K */
2319 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2320 tx_ring->size = ALIGN(tx_ring->size, 4096);
2321
2322 err = e1000_alloc_ring_dma(adapter, tx_ring);
2323 if (err)
2324 goto err;
2325
2326 tx_ring->next_to_use = 0;
2327 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2328
2329 return 0;
2330err:
2331 vfree(tx_ring->buffer_info);
44defeb3 2332 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2333 return err;
2334}
2335
2336/**
2337 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2338 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2339 *
2340 * Returns 0 on success, negative on failure
2341 **/
55aa6985 2342int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2343{
55aa6985 2344 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2345 struct e1000_buffer *buffer_info;
2346 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2347
2348 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2349 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2350 if (!rx_ring->buffer_info)
2351 goto err;
bc7f75fa 2352
47f44e40
AK		 2353 for (i = 0; i < rx_ring->count; i++) {
2354 buffer_info = &rx_ring->buffer_info[i];
2355 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2356 sizeof(struct e1000_ps_page),
2357 GFP_KERNEL);
2358 if (!buffer_info->ps_pages)
2359 goto err_pages;
2360 }
bc7f75fa
AK		 2361
2362 desc_len = sizeof(union e1000_rx_desc_packet_split);
2363
2364 /* Round up to nearest 4K */
2365 rx_ring->size = rx_ring->count * desc_len;
2366 rx_ring->size = ALIGN(rx_ring->size, 4096);
2367
2368 err = e1000_alloc_ring_dma(adapter, rx_ring);
2369 if (err)
47f44e40 2370 goto err_pages;
bc7f75fa
AK		 2371
2372 rx_ring->next_to_clean = 0;
2373 rx_ring->next_to_use = 0;
2374 rx_ring->rx_skb_top = NULL;
2375
2376 return 0;
47f44e40
AK		 2377
2378err_pages:
2379 for (i = 0; i < rx_ring->count; i++) {
2380 buffer_info = &rx_ring->buffer_info[i];
2381 kfree(buffer_info->ps_pages);
2382 }
bc7f75fa
AK		 2383err:
2384 vfree(rx_ring->buffer_info);
e9262447 2385 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2386 return err;
2387}
2388
2389/**
2390 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2391 * @tx_ring: Tx descriptor ring
bc7f75fa 2392 **/
55aa6985 2393static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2394{
55aa6985 2395 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2396 struct e1000_buffer *buffer_info;
2397 unsigned long size;
2398 unsigned int i;
2399
2400 for (i = 0; i < tx_ring->count; i++) {
2401 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2402 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2403 }
2404
3f0cfa3b 2405 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2406 size = sizeof(struct e1000_buffer) * tx_ring->count;
2407 memset(tx_ring->buffer_info, 0, size);
2408
2409 memset(tx_ring->desc, 0, tx_ring->size);
2410
2411 tx_ring->next_to_use = 0;
2412 tx_ring->next_to_clean = 0;
2413
c5083cf6 2414 writel(0, tx_ring->head);
bdc125f7
BA		 2415 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2416 e1000e_update_tdt_wa(tx_ring, 0);
2417 else
2418 writel(0, tx_ring->tail);
bc7f75fa
AK		 2419}
2420
2421/**
2422 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2423 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2424 *
2425 * Free all transmit software resources
2426 **/
55aa6985 2427void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2428{
55aa6985 2429 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2430 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2431
55aa6985 2432 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2433
2434 vfree(tx_ring->buffer_info);
2435 tx_ring->buffer_info = NULL;
2436
2437 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2438 tx_ring->dma);
2439 tx_ring->desc = NULL;
2440}
2441
2442/**
2443 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2444 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2445 *
2446 * Free all receive software resources
2447 **/
55aa6985 2448void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2449{
55aa6985 2450 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2451 struct pci_dev *pdev = adapter->pdev;
47f44e40 2452 int i;
bc7f75fa 2453
55aa6985 2454 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2455
b1cdfead 2456 for (i = 0; i < rx_ring->count; i++)
47f44e40 2457 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2458
bc7f75fa
AK		 2459 vfree(rx_ring->buffer_info);
2460 rx_ring->buffer_info = NULL;
2461
bc7f75fa
AK		 2462 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2463 rx_ring->dma);
2464 rx_ring->desc = NULL;
2465}
2466
2467/**
2468 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2469 * @adapter: pointer to adapter
2470 * @itr_setting: current adapter->itr
2471 * @packets: the number of packets during this measurement interval
2472 * @bytes: the number of bytes during this measurement interval
2473 *
bc7f75fa
AK		 2474 * Stores a new ITR value based on packets and byte
2475 * counts during the last interrupt. The advantage of per interrupt
2476 * computation is faster updates and more accurate ITR for the current
2477 * traffic pattern. Constants in this function were computed
2478 * based on theoretical maximum wire speed and thresholds were set based
2479 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2480 * while increasing bulk throughput. This functionality is controlled
2481 * by the InterruptThrottleRate module parameter.
bc7f75fa 2482 **/
8bb62869 2483static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2484{
2485 unsigned int retval = itr_setting;
2486
2487 if (packets == 0)
5015e53a 2488 return itr_setting;
bc7f75fa
AK		 2489
2490 switch (itr_setting) {
2491 case lowest_latency:
2492 /* handle TSO and jumbo frames */
2493 if (bytes/packets > 8000)
2494 retval = bulk_latency;
b1cdfead 2495 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2496 retval = low_latency;
bc7f75fa
AK		 2497 break;
2498 case low_latency: /* 50 usec aka 20000 ints/s */
2499 if (bytes > 10000) {
2500 /* this if handles the TSO accounting */
b1cdfead 2501 if (bytes/packets > 8000)
bc7f75fa 2502 retval = bulk_latency;
b1cdfead 2503 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2504 retval = bulk_latency;
b1cdfead 2505 else if ((packets > 35))
bc7f75fa 2506 retval = lowest_latency;
bc7f75fa
AK		 2507 } else if (bytes/packets > 2000) {
2508 retval = bulk_latency;
2509 } else if (packets <= 2 && bytes < 512) {
2510 retval = lowest_latency;
2511 }
2512 break;
2513 case bulk_latency: /* 250 usec aka 4000 ints/s */
2514 if (bytes > 25000) {
b1cdfead 2515 if (packets > 35)
bc7f75fa 2516 retval = low_latency;
bc7f75fa
AK		 2517 } else if (bytes < 6000) {
2518 retval = low_latency;
2519 }
2520 break;
2521 }
2522
bc7f75fa
AK		 2523 return retval;
2524}
2525
2526static void e1000_set_itr(struct e1000_adapter *adapter)
2527{
bc7f75fa
AK		 2528 u16 current_itr;
2529 u32 new_itr = adapter->itr;
2530
2531 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2532 if (adapter->link_speed != SPEED_1000) {
2533 current_itr = 0;
2534 new_itr = 4000;
2535 goto set_itr_now;
2536 }
2537
828bac87
BA		 2538 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2539 new_itr = 0;
2540 goto set_itr_now;
2541 }
2542
8bb62869
BA		 2543 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2544 adapter->total_tx_packets,
2545 adapter->total_tx_bytes);
bc7f75fa
AK		 2546 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2547 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2548 adapter->tx_itr = low_latency;
2549
8bb62869
BA		 2550 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2551 adapter->total_rx_packets,
2552 adapter->total_rx_bytes);
bc7f75fa
AK		 2553 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2554 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2555 adapter->rx_itr = low_latency;
2556
2557 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2558
2559 switch (current_itr) {
2560 /* counts and packets in update_itr are dependent on these numbers */
2561 case lowest_latency:
2562 new_itr = 70000;
2563 break;
2564 case low_latency:
2565 new_itr = 20000; /* aka hwitr = ~200 */
2566 break;
2567 case bulk_latency:
2568 new_itr = 4000;
2569 break;
2570 default:
2571 break;
2572 }
2573
2574set_itr_now:
2575 if (new_itr != adapter->itr) {
e921eb1a 2576 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2577 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2578 * increasing
2579 */
bc7f75fa
AK		 2580 new_itr = new_itr > adapter->itr ?
2581 min(adapter->itr + (new_itr >> 2), new_itr) :
2582 new_itr;
2583 adapter->itr = new_itr;
4662e82b
BA		 2584 adapter->rx_ring->itr_val = new_itr;
2585 if (adapter->msix_entries)
2586 adapter->rx_ring->set_itr = 1;
2587 else
e3d14b08 2588 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2589 }
2590}
2591
22a4cca2
MV		 2592/**
2593 * e1000e_write_itr - write the ITR value to the appropriate registers
2594 * @adapter: address of board private structure
2595 * @itr: new ITR value to program
2596 *
2597 * e1000e_write_itr determines if the adapter is in MSI-X mode
2598 * and, if so, writes the EITR registers with the ITR value.
2599 * Otherwise, it writes the ITR value into the ITR register.
2600 **/
2601void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2602{
2603 struct e1000_hw *hw = &adapter->hw;
2604 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2605
2606 if (adapter->msix_entries) {
2607 int vector;
2608
2609 for (vector = 0; vector < adapter->num_vectors; vector++)
2610 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2611 } else {
2612 ew32(ITR, new_itr);
2613 }
2614}
2615
4662e82b
BA		 2616/**
2617 * e1000_alloc_queues - Allocate memory for all rings
2618 * @adapter: board private structure to initialize
2619 **/
9f9a12f8 2620static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2621{
55aa6985
BA		 2622 int size = sizeof(struct e1000_ring);
2623
2624 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2625 if (!adapter->tx_ring)
2626 goto err;
55aa6985
BA		 2627 adapter->tx_ring->count = adapter->tx_ring_count;
2628 adapter->tx_ring->adapter = adapter;
4662e82b 2629
55aa6985 2630 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2631 if (!adapter->rx_ring)
2632 goto err;
55aa6985
BA		 2633 adapter->rx_ring->count = adapter->rx_ring_count;
2634 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2635
2636 return 0;
2637err:
2638 e_err("Unable to allocate memory for queues\n");
2639 kfree(adapter->rx_ring);
2640 kfree(adapter->tx_ring);
2641 return -ENOMEM;
2642}
2643
bc7f75fa 2644/**
c58c8a78 2645 * e1000e_poll - NAPI Rx polling callback
ad68076e 2646 * @napi: struct associated with this polling callback
c58c8a78 2647 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2648 **/
c58c8a78 2649static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2650{
c58c8a78
BA		 2651 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2652 napi);
4662e82b 2653 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2654 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2655 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2656
4cf1653a 2657 adapter = netdev_priv(poll_dev);
bc7f75fa 2658
c58c8a78
BA		 2659 if (!adapter->msix_entries ||
2660 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2661 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2662
c58c8a78 2663 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2664
12d04a3c 2665 if (!tx_cleaned)
c58c8a78 2666 work_done = weight;
bc7f75fa 2667
c58c8a78
BA		 2668 /* If weight not fully consumed, exit the polling mode */
2669 if (work_done < weight) {
bc7f75fa
AK		 2670 if (adapter->itr_setting & 3)
2671 e1000_set_itr(adapter);
288379f0 2672 napi_complete(napi);
a3c69fef
JB		 2673 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2674 if (adapter->msix_entries)
2675 ew32(IMS, adapter->rx_ring->ims_val);
2676 else
2677 e1000_irq_enable(adapter);
2678 }
bc7f75fa
AK		 2679 }
2680
2681 return work_done;
2682}
2683
8e586137 2684static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2685{
2686 struct e1000_adapter *adapter = netdev_priv(netdev);
2687 struct e1000_hw *hw = &adapter->hw;
2688 u32 vfta, index;
2689
2690 /* don't update vlan cookie if already programmed */
2691 if ((adapter->hw.mng_cookie.status &
2692 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2693 (vid == adapter->mng_vlan_id))
8e586137 2694 return 0;
caaddaf8 2695
bc7f75fa 2696 /* add VID to filter table */
caaddaf8
BA		 2697 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2698 index = (vid >> 5) & 0x7F;
2699 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2700 vfta |= (1 << (vid & 0x1F));
2701 hw->mac.ops.write_vfta(hw, index, vfta);
2702 }
86d70e53
JK		 2703
2704 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2705
2706 return 0;
bc7f75fa
AK		 2707}
2708
8e586137 2709static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2710{
2711 struct e1000_adapter *adapter = netdev_priv(netdev);
2712 struct e1000_hw *hw = &adapter->hw;
2713 u32 vfta, index;
2714
bc7f75fa
AK		 2715 if ((adapter->hw.mng_cookie.status &
2716 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2717 (vid == adapter->mng_vlan_id)) {
2718 /* release control to f/w */
31dbe5b4 2719 e1000e_release_hw_control(adapter);
8e586137 2720 return 0;
bc7f75fa
AK		 2721 }
2722
2723 /* remove VID from filter table */
caaddaf8
BA		 2724 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2725 index = (vid >> 5) & 0x7F;
2726 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2727 vfta &= ~(1 << (vid & 0x1F));
2728 hw->mac.ops.write_vfta(hw, index, vfta);
2729 }
86d70e53
JK		 2730
2731 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2732
2733 return 0;
bc7f75fa
AK		 2734}
2735
86d70e53
JK		 2736/**
2737 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2738 * @adapter: board private structure to initialize
2739 **/
2740static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2741{
2742 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2743 struct e1000_hw *hw = &adapter->hw;
2744 u32 rctl;
bc7f75fa 2745
86d70e53
JK		 2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2747 /* disable VLAN receive filtering */
2748 rctl = er32(RCTL);
2749 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2750 ew32(RCTL, rctl);
2751
2752 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2753 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2754 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2755 }
bc7f75fa
AK		 2756 }
2757}
2758
86d70e53
JK		 2759/**
2760 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2761 * @adapter: board private structure to initialize
2762 **/
2763static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2764{
2765 struct e1000_hw *hw = &adapter->hw;
2766 u32 rctl;
2767
2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2769 /* enable VLAN receive filtering */
2770 rctl = er32(RCTL);
2771 rctl |= E1000_RCTL_VFE;
2772 rctl &= ~E1000_RCTL_CFIEN;
2773 ew32(RCTL, rctl);
2774 }
2775}
bc7f75fa 2776
86d70e53
JK		 2777/**
2778 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2779 * @adapter: board private structure to initialize
2780 **/
2781static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2782{
bc7f75fa 2783 struct e1000_hw *hw = &adapter->hw;
86d70e53 2784 u32 ctrl;
bc7f75fa 2785
86d70e53
JK		 2786 /* disable VLAN tag insert/strip */
2787 ctrl = er32(CTRL);
2788 ctrl &= ~E1000_CTRL_VME;
2789 ew32(CTRL, ctrl);
2790}
bc7f75fa 2791
86d70e53
JK		 2792/**
2793 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2794 * @adapter: board private structure to initialize
2795 **/
2796static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2797{
2798 struct e1000_hw *hw = &adapter->hw;
2799 u32 ctrl;
bc7f75fa 2800
86d70e53
JK		 2801 /* enable VLAN tag insert/strip */
2802 ctrl = er32(CTRL);
2803 ctrl |= E1000_CTRL_VME;
2804 ew32(CTRL, ctrl);
2805}
bc7f75fa 2806
86d70e53
JK		 2807static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2808{
2809 struct net_device *netdev = adapter->netdev;
2810 u16 vid = adapter->hw.mng_cookie.vlan_id;
2811 u16 old_vid = adapter->mng_vlan_id;
2812
2813 if (adapter->hw.mng_cookie.status &
2814 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2815 e1000_vlan_rx_add_vid(netdev, vid);
2816 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2817 }
2818
86d70e53
JK		 2819 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2820 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2821}
2822
2823static void e1000_restore_vlan(struct e1000_adapter *adapter)
2824{
2825 u16 vid;
2826
86d70e53 2827 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2828
86d70e53 2829 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2830 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2831}
2832
cd791618 2833static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2834{
2835 struct e1000_hw *hw = &adapter->hw;
cd791618 2836 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2837
2838 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2839 return;
2840
2841 manc = er32(MANC);
2842
e921eb1a 2843 /* enable receiving management packets to the host. this will probably
bc7f75fa 2844 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2845 * the packets will be handled on SMBUS
2846 */
bc7f75fa
AK		 2847 manc |= E1000_MANC_EN_MNG2HOST;
2848 manc2h = er32(MANC2H);
cd791618
BA		 2849
2850 switch (hw->mac.type) {
2851 default:
2852 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2853 break;
2854 case e1000_82574:
2855 case e1000_82583:
e921eb1a 2856 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2857 * if so, enable it.
2858 */
2859 for (i = 0, j = 0; i < 8; i++) {
2860 mdef = er32(MDEF(i));
2861
2862 /* Ignore filters with anything other than IPMI ports */
3b21b508 2863 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2864 continue;
2865
2866 /* Enable this decision filter in MANC2H */
2867 if (mdef)
2868 manc2h |= (1 << i);
2869
2870 j |= mdef;
2871 }
2872
2873 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2874 break;
2875
2876 /* Create new decision filter in an empty filter */
2877 for (i = 0, j = 0; i < 8; i++)
2878 if (er32(MDEF(i)) == 0) {
2879 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2880 E1000_MDEF_PORT_664));
2881 manc2h |= (1 << 1);
2882 j++;
2883 break;
2884 }
2885
2886 if (!j)
2887 e_warn("Unable to create IPMI pass-through filter\n");
2888 break;
2889 }
2890
bc7f75fa
AK		 2891 ew32(MANC2H, manc2h);
2892 ew32(MANC, manc);
2893}
2894
2895/**
af667a29 2896 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2897 * @adapter: board private structure
2898 *
2899 * Configure the Tx unit of the MAC after a reset.
2900 **/
2901static void e1000_configure_tx(struct e1000_adapter *adapter)
2902{
2903 struct e1000_hw *hw = &adapter->hw;
2904 struct e1000_ring *tx_ring = adapter->tx_ring;
2905 u64 tdba;
c550b121 2906 u32 tdlen, tarc;
bc7f75fa
AK		 2907
2908 /* Setup the HW Tx Head and Tail descriptor pointers */
2909 tdba = tx_ring->dma;
2910 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2911 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2912 ew32(TDBAH(0), (tdba >> 32));
2913 ew32(TDLEN(0), tdlen);
2914 ew32(TDH(0), 0);
2915 ew32(TDT(0), 0);
2916 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2917 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2918
bc7f75fa
AK		 2919 /* Set the Tx Interrupt Delay register */
2920 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2921 /* Tx irq moderation */
bc7f75fa
AK		 2922 ew32(TADV, adapter->tx_abs_int_delay);
2923
3a3b7586
JB		 2924 if (adapter->flags2 & FLAG2_DMA_BURST) {
2925 u32 txdctl = er32(TXDCTL(0));
2926 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2927 E1000_TXDCTL_WTHRESH);
e921eb1a 2928 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2929 * hardware to use the bus more efficiently in bursts, depends
2930 * on the tx_int_delay to be enabled,
8edc0e62 2931 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2932 * hthresh = 1 ==> prefetch when one or more available
2933 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2934 * BEWARE: this seems to work but should be considered first if
af667a29 2935 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2936 */
2937 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2938 ew32(TXDCTL(0), txdctl);
3a3b7586 2939 }
56032be7
BA		 2940 /* erratum work around: set txdctl the same for both queues */
2941 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2942
bc7f75fa 2943 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2944 tarc = er32(TARC(0));
e921eb1a 2945 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2946 * gigabit link later
2947 */
bc7f75fa
AK		 2948#define SPEED_MODE_BIT (1 << 21)
2949 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2950 ew32(TARC(0), tarc);
bc7f75fa
AK		 2951 }
2952
2953 /* errata: program both queues to unweighted RR */
2954 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2955 tarc = er32(TARC(0));
bc7f75fa 2956 tarc |= 1;
e9ec2c0f
JK		 2957 ew32(TARC(0), tarc);
2958 tarc = er32(TARC(1));
bc7f75fa 2959 tarc |= 1;
e9ec2c0f 2960 ew32(TARC(1), tarc);
bc7f75fa
AK		 2961 }
2962
bc7f75fa
AK		 2963 /* Setup Transmit Descriptor Settings for eop descriptor */
2964 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2965
2966 /* only set IDE if we are delaying interrupts using the timers */
2967 if (adapter->tx_int_delay)
2968 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2969
2970 /* enable Report Status bit */
2971 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2972
57cde763 2973 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2974}
2975
2976/**
2977 * e1000_setup_rctl - configure the receive control registers
2978 * @adapter: Board private structure
2979 **/
2980#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2981 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2982static void e1000_setup_rctl(struct e1000_adapter *adapter)
2983{
2984 struct e1000_hw *hw = &adapter->hw;
2985 u32 rctl, rfctl;
bc7f75fa
AK		 2986 u32 pages = 0;
2987
2fbe4526
BA		 2988 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2989 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2990 s32 ret_val;
2991
2992 if (adapter->netdev->mtu > ETH_DATA_LEN)
2993 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2994 else
2995 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2996
2997 if (ret_val)
2998 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2999 }
3000
bc7f75fa
AK		 3001 /* Program MC offset vector base */
3002 rctl = er32(RCTL);
3003 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3004 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3005 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3006 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3007
3008 /* Do not Store bad packets */
3009 rctl &= ~E1000_RCTL_SBP;
3010
3011 /* Enable Long Packet receive */
3012 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3013 rctl &= ~E1000_RCTL_LPE;
3014 else
3015 rctl |= E1000_RCTL_LPE;
3016
eb7c3adb
JK		 3017 /* Some systems expect that the CRC is included in SMBUS traffic. The
3018 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3019 * host memory when this is enabled
3020 */
3021 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3022 rctl |= E1000_RCTL_SECRC;
5918bd88 3023
a4f58f54
BA		 3024 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3025 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3026 u16 phy_data;
3027
3028 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3029 phy_data &= 0xfff8;
3030 phy_data |= (1 << 2);
3031 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3032
3033 e1e_rphy(hw, 22, &phy_data);
3034 phy_data &= 0x0fff;
3035 phy_data |= (1 << 14);
3036 e1e_wphy(hw, 0x10, 0x2823);
3037 e1e_wphy(hw, 0x11, 0x0003);
3038 e1e_wphy(hw, 22, phy_data);
3039 }
3040
bc7f75fa
AK		 3041 /* Setup buffer sizes */
3042 rctl &= ~E1000_RCTL_SZ_4096;
3043 rctl |= E1000_RCTL_BSEX;
3044 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3045 case 2048:
3046 default:
3047 rctl |= E1000_RCTL_SZ_2048;
3048 rctl &= ~E1000_RCTL_BSEX;
3049 break;
3050 case 4096:
3051 rctl |= E1000_RCTL_SZ_4096;
3052 break;
3053 case 8192:
3054 rctl |= E1000_RCTL_SZ_8192;
3055 break;
3056 case 16384:
3057 rctl |= E1000_RCTL_SZ_16384;
3058 break;
3059 }
3060
5f450212
BA		 3061 /* Enable Extended Status in all Receive Descriptors */
3062 rfctl = er32(RFCTL);
3063 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3064 ew32(RFCTL, rfctl);
5f450212 3065
e921eb1a 3066 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3067 * header is placed in skb->data and the packet data is
3068 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3069 * In the case of a non-split, skb->data is linearly filled,
3070 * followed by the page buffers. Therefore, skb->data is
3071 * sized to hold the largest protocol header.
3072 *
3073 * allocations using alloc_page take too long for regular MTU
3074 * so only enable packet split for jumbo frames
3075 *
3076 * Using pages when the page size is greater than 16k wastes
3077 * a lot of memory, since we allocate 3 pages at all times
3078 * per packet.
3079 */
bc7f75fa 3080 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3081 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3082 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3083 else
3084 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3085
3086 if (adapter->rx_ps_pages) {
90da0669
BA		 3087 u32 psrctl = 0;
3088
140a7480
AK		 3089 /* Enable Packet split descriptors */
3090 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 3091
3092 psrctl |= adapter->rx_ps_bsize0 >>
3093 E1000_PSRCTL_BSIZE0_SHIFT;
3094
3095 switch (adapter->rx_ps_pages) {
3096 case 3:
3097 psrctl |= PAGE_SIZE <<
3098 E1000_PSRCTL_BSIZE3_SHIFT;
3099 case 2:
3100 psrctl |= PAGE_SIZE <<
3101 E1000_PSRCTL_BSIZE2_SHIFT;
3102 case 1:
3103 psrctl |= PAGE_SIZE >>
3104 E1000_PSRCTL_BSIZE1_SHIFT;
3105 break;
3106 }
3107
3108 ew32(PSRCTL, psrctl);
3109 }
3110
cf955e6c
BG		 3111 /* This is useful for sniffing bad packets. */
3112 if (adapter->netdev->features & NETIF_F_RXALL) {
3113 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3114 * in e1000e_set_rx_mode
3115 */
cf955e6c
BG		 3116 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3117 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3118 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3119
3120 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3121 E1000_RCTL_DPF | /* Allow filtered pause */
3122 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3123 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3124 * and that breaks VLANs.
3125 */
3126 }
3127
bc7f75fa 3128 ew32(RCTL, rctl);
318a94d6 3129 /* just started the receive unit, no need to restart */
12d43f7d 3130 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3131}
3132
3133/**
3134 * e1000_configure_rx - Configure Receive Unit after Reset
3135 * @adapter: board private structure
3136 *
3137 * Configure the Rx unit of the MAC after a reset.
3138 **/
3139static void e1000_configure_rx(struct e1000_adapter *adapter)
3140{
3141 struct e1000_hw *hw = &adapter->hw;
3142 struct e1000_ring *rx_ring = adapter->rx_ring;
3143 u64 rdba;
3144 u32 rdlen, rctl, rxcsum, ctrl_ext;
3145
3146 if (adapter->rx_ps_pages) {
3147 /* this is a 32 byte descriptor */
3148 rdlen = rx_ring->count *
af667a29 3149 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3150 adapter->clean_rx = e1000_clean_rx_irq_ps;
3151 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3152 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3153 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3154 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3155 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3156 } else {
5f450212 3157 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3158 adapter->clean_rx = e1000_clean_rx_irq;
3159 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3160 }
3161
3162 /* disable receives while setting up the descriptors */
3163 rctl = er32(RCTL);
7f99ae63
BA		 3164 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3165 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3166 e1e_flush();
1bba4386 3167 usleep_range(10000, 20000);
bc7f75fa 3168
3a3b7586 3169 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3170 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3171 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3172 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3173 * granularity = 01
3174 * wthresh = 04,
3175 * hthresh = 04,
3176 * pthresh = 0x20
3177 */
3178 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3179 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3180
e921eb1a 3181 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3182 * the value was not set by the user via module options
3183 */
3184 if (adapter->rx_int_delay == DEFAULT_RDTR)
3185 adapter->rx_int_delay = BURST_RDTR;
3186 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3187 adapter->rx_abs_int_delay = BURST_RADV;
3188 }
3189
bc7f75fa
AK		 3190 /* set the Receive Delay Timer Register */
3191 ew32(RDTR, adapter->rx_int_delay);
3192
3193 /* irq moderation */
3194 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3195 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3196 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3197
3198 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3199 /* Auto-Mask interrupts upon ICR access */
3200 ctrl_ext |= E1000_CTRL_EXT_IAME;
3201 ew32(IAM, 0xffffffff);
3202 ew32(CTRL_EXT, ctrl_ext);
3203 e1e_flush();
3204
e921eb1a 3205 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3206 * the Base and Length of the Rx Descriptor Ring
3207 */
bc7f75fa 3208 rdba = rx_ring->dma;
1e36052e
BA		 3209 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3210 ew32(RDBAH(0), (rdba >> 32));
3211 ew32(RDLEN(0), rdlen);
3212 ew32(RDH(0), 0);
3213 ew32(RDT(0), 0);
3214 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3215 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3216
3217 /* Enable Receive Checksum Offload for TCP and UDP */
3218 rxcsum = er32(RXCSUM);
2e1706f2 3219 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3220 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3221 else
bc7f75fa 3222 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3223 ew32(RXCSUM, rxcsum);
3224
3e35d991
BA		 3225 /* With jumbo frames, excessive C-state transition latencies result
3226 * in dropped transactions.
3227 */
3228 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3229 u32 lat =
3230 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3231 adapter->max_frame_size) * 8 / 1000;
3232
3233 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3234 u32 rxdctl = er32(RXDCTL(0));
3235 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3236 }
3e35d991
BA		 3237
3238 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3239 } else {
3240 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3241 PM_QOS_DEFAULT_VALUE);
97ac8cae 3242 }
bc7f75fa
AK		 3243
3244 /* Enable Receives */
3245 ew32(RCTL, rctl);
3246}
3247
3248/**
ef9b965a
JB		 3249 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3250 * @netdev: network interface device structure
bc7f75fa 3251 *
ef9b965a
JB		 3252 * Writes multicast address list to the MTA hash table.
3253 * Returns: -ENOMEM on failure
3254 * 0 on no addresses written
3255 * X on writing X addresses to MTA
3256 */
3257static int e1000e_write_mc_addr_list(struct net_device *netdev)
3258{
3259 struct e1000_adapter *adapter = netdev_priv(netdev);
3260 struct e1000_hw *hw = &adapter->hw;
3261 struct netdev_hw_addr *ha;
3262 u8 *mta_list;
3263 int i;
3264
3265 if (netdev_mc_empty(netdev)) {
3266 /* nothing to program, so clear mc list */
3267 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3268 return 0;
3269 }
3270
3271 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3272 if (!mta_list)
3273 return -ENOMEM;
3274
3275 /* update_mc_addr_list expects a packed array of only addresses. */
3276 i = 0;
3277 netdev_for_each_mc_addr(ha, netdev)
3278 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3279
3280 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3281 kfree(mta_list);
3282
3283 return netdev_mc_count(netdev);
3284}
3285
3286/**
3287 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3288 * @netdev: network interface device structure
bc7f75fa 3289 *
ef9b965a
JB		 3290 * Writes unicast address list to the RAR table.
3291 * Returns: -ENOMEM on failure/insufficient address space
3292 * 0 on no addresses written
3293 * X on writing X addresses to the RAR table
bc7f75fa 3294 **/
ef9b965a 3295static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3296{
ef9b965a
JB		 3297 struct e1000_adapter *adapter = netdev_priv(netdev);
3298 struct e1000_hw *hw = &adapter->hw;
3299 unsigned int rar_entries = hw->mac.rar_entry_count;
3300 int count = 0;
3301
3302 /* save a rar entry for our hardware address */
3303 rar_entries--;
3304
3305 /* save a rar entry for the LAA workaround */
3306 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3307 rar_entries--;
3308
3309 /* return ENOMEM indicating insufficient memory for addresses */
3310 if (netdev_uc_count(netdev) > rar_entries)
3311 return -ENOMEM;
3312
3313 if (!netdev_uc_empty(netdev) && rar_entries) {
3314 struct netdev_hw_addr *ha;
3315
e921eb1a 3316 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3317 * combining
3318 */
3319 netdev_for_each_uc_addr(ha, netdev) {
3320 if (!rar_entries)
3321 break;
69e1e019 3322 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3323 count++;
3324 }
3325 }
3326
3327 /* zero out the remaining RAR entries not used above */
3328 for (; rar_entries > 0; rar_entries--) {
3329 ew32(RAH(rar_entries), 0);
3330 ew32(RAL(rar_entries), 0);
3331 }
3332 e1e_flush();
3333
3334 return count;
bc7f75fa
AK		 3335}
3336
3337/**
ef9b965a 3338 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3339 * @netdev: network interface device structure
3340 *
ef9b965a
JB		 3341 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3342 * address list or the network interface flags are updated. This routine is
3343 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3344 * promiscuous mode, and all-multi behavior.
3345 **/
ef9b965a 3346static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3347{
3348 struct e1000_adapter *adapter = netdev_priv(netdev);
3349 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3350 u32 rctl;
bc7f75fa
AK		 3351
3352 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3353 rctl = er32(RCTL);
3354
ef9b965a
JB		 3355 /* clear the affected bits */
3356 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3357
bc7f75fa
AK		 3358 if (netdev->flags & IFF_PROMISC) {
3359 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3360 /* Do not hardware filter VLANs in promisc mode */
3361 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3362 } else {
ef9b965a 3363 int count;
3d3a1676 3364
746b9f02
PM		 3365 if (netdev->flags & IFF_ALLMULTI) {
3366 rctl |= E1000_RCTL_MPE;
746b9f02 3367 } else {
e921eb1a 3368 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3369 * then we should just turn on promiscuous mode so
3370 * that we can at least receive multicast traffic
3371 */
3372 count = e1000e_write_mc_addr_list(netdev);
3373 if (count < 0)
3374 rctl |= E1000_RCTL_MPE;
746b9f02 3375 }
86d70e53 3376 e1000e_vlan_filter_enable(adapter);
e921eb1a 3377 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3378 * sufficient space to store all the addresses then enable
3379 * unicast promiscuous mode
bc7f75fa 3380 */
ef9b965a
JB		 3381 count = e1000e_write_uc_addr_list(netdev);
3382 if (count < 0)
3383 rctl |= E1000_RCTL_UPE;
bc7f75fa 3384 }
86d70e53 3385
ef9b965a
JB		 3386 ew32(RCTL, rctl);
3387
86d70e53
JK		 3388 if (netdev->features & NETIF_F_HW_VLAN_RX)
3389 e1000e_vlan_strip_enable(adapter);
3390 else
3391 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3392}
3393
70495a50
BA		 3394static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3395{
3396 struct e1000_hw *hw = &adapter->hw;
3397 u32 mrqc, rxcsum;
3398 int i;
3399 static const u32 rsskey[10] = {
3400 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3401 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3402 };
3403
3404 /* Fill out hash function seed */
3405 for (i = 0; i < 10; i++)
3406 ew32(RSSRK(i), rsskey[i]);
3407
3408 /* Direct all traffic to queue 0 */
3409 for (i = 0; i < 32; i++)
3410 ew32(RETA(i), 0);
3411
e921eb1a 3412 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3413 * descriptor on writeback.
3414 */
3415 rxcsum = er32(RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 ew32(RXCSUM, rxcsum);
3419
3420 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3421 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6 |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3425
3426 ew32(MRQC, mrqc);
3427}
3428
b67e1913
BA		 3429/**
3430 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3431 * @adapter: board private structure
3432 * @timinca: pointer to returned time increment attributes
3433 *
3434 * Get attributes for incrementing the System Time Register SYSTIML/H at
3435 * the default base frequency, and set the cyclecounter shift value.
3436 **/
d89777bf 3437s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3438{
3439 struct e1000_hw *hw = &adapter->hw;
3440 u32 incvalue, incperiod, shift;
3441
3442 /* Make sure clock is enabled on I217 before checking the frequency */
3443 if ((hw->mac.type == e1000_pch_lpt) &&
3444 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3445 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3446 u32 fextnvm7 = er32(FEXTNVM7);
3447
3448 if (!(fextnvm7 & (1 << 0))) {
3449 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3450 e1e_flush();
3451 }
3452 }
3453
3454 switch (hw->mac.type) {
3455 case e1000_pch2lan:
3456 case e1000_pch_lpt:
3457 /* On I217, the clock frequency is 25MHz or 96MHz as
3458 * indicated by the System Clock Frequency Indication
3459 */
3460 if ((hw->mac.type != e1000_pch_lpt) ||
3461 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3462 /* Stable 96MHz frequency */
3463 incperiod = INCPERIOD_96MHz;
3464 incvalue = INCVALUE_96MHz;
3465 shift = INCVALUE_SHIFT_96MHz;
3466 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3467 break;
3468 }
3469 /* fall-through */
3470 case e1000_82574:
3471 case e1000_82583:
3472 /* Stable 25MHz frequency */
3473 incperiod = INCPERIOD_25MHz;
3474 incvalue = INCVALUE_25MHz;
3475 shift = INCVALUE_SHIFT_25MHz;
3476 adapter->cc.shift = shift;
3477 break;
3478 default:
3479 return -EINVAL;
3480 }
3481
3482 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3483 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3484
3485 return 0;
3486}
3487
3488/**
3489 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3490 * @adapter: board private structure
3491 *
3492 * Outgoing time stamping can be enabled and disabled. Play nice and
3493 * disable it when requested, although it shouldn't cause any overhead
3494 * when no packet needs it. At most one packet in the queue may be
3495 * marked for time stamping, otherwise it would be impossible to tell
3496 * for sure to which packet the hardware time stamp belongs.
3497 *
3498 * Incoming time stamping has to be configured via the hardware filters.
3499 * Not all combinations are supported, in particular event type has to be
3500 * specified. Matching the kind of event packet is not supported, with the
3501 * exception of "all V2 events regardless of level 2 or 4".
3502 **/
3503static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3504{
3505 struct e1000_hw *hw = &adapter->hw;
3506 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3507 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3508 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3509 u32 rxmtrl = 0;
3510 u16 rxudp = 0;
3511 bool is_l4 = false;
3512 bool is_l2 = false;
b67e1913
BA		 3513 u32 regval;
3514 s32 ret_val;
3515
3516 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3517 return -EINVAL;
3518
3519 /* flags reserved for future extensions - must be zero */
3520 if (config->flags)
3521 return -EINVAL;
3522
3523 switch (config->tx_type) {
3524 case HWTSTAMP_TX_OFF:
3525 tsync_tx_ctl = 0;
3526 break;
3527 case HWTSTAMP_TX_ON:
3528 break;
3529 default:
3530 return -ERANGE;
3531 }
3532
3533 switch (config->rx_filter) {
3534 case HWTSTAMP_FILTER_NONE:
3535 tsync_rx_ctl = 0;
3536 break;
d89777bf
BA		 3537 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3538 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3539 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3540 is_l4 = true;
3541 break;
3542 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3543 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3544 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3545 is_l4 = true;
3546 break;
3547 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3548 /* Also time stamps V2 L2 Path Delay Request/Response */
3549 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3550 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3551 is_l2 = true;
3552 break;
3553 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3554 /* Also time stamps V2 L2 Path Delay Request/Response. */
3555 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3556 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3557 is_l2 = true;
3558 break;
3559 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3560 /* Hardware cannot filter just V2 L4 Sync messages;
3561 * fall-through to V2 (both L2 and L4) Sync.
3562 */
3563 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3564 /* Also time stamps V2 Path Delay Request/Response. */
3565 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3566 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3567 is_l2 = true;
3568 is_l4 = true;
3569 break;
3570 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3571 /* Hardware cannot filter just V2 L4 Delay Request messages;
3572 * fall-through to V2 (both L2 and L4) Delay Request.
3573 */
3574 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3575 /* Also time stamps V2 Path Delay Request/Response. */
3576 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3577 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3578 is_l2 = true;
3579 is_l4 = true;
3580 break;
3581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3582 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3583 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3584 * fall-through to all V2 (both L2 and L4) Events.
3585 */
3586 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3587 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3588 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3589 is_l2 = true;
3590 is_l4 = true;
3591 break;
3592 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3593 /* For V1, the hardware can only filter Sync messages or
3594 * Delay Request messages but not both so fall-through to
3595 * time stamp all packets.
3596 */
b67e1913 3597 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3598 is_l2 = true;
3599 is_l4 = true;
b67e1913
BA		 3600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3601 config->rx_filter = HWTSTAMP_FILTER_ALL;
3602 break;
3603 default:
3604 return -ERANGE;
3605 }
3606
3607 /* enable/disable Tx h/w time stamping */
3608 regval = er32(TSYNCTXCTL);
3609 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3610 regval |= tsync_tx_ctl;
3611 ew32(TSYNCTXCTL, regval);
3612 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3613 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3614 e_err("Timesync Tx Control register not set as expected\n");
3615 return -EAGAIN;
3616 }
3617
3618 /* enable/disable Rx h/w time stamping */
3619 regval = er32(TSYNCRXCTL);
3620 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3621 regval |= tsync_rx_ctl;
3622 ew32(TSYNCRXCTL, regval);
3623 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3624 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3625 (regval & (E1000_TSYNCRXCTL_ENABLED |
3626 E1000_TSYNCRXCTL_TYPE_MASK))) {
3627 e_err("Timesync Rx Control register not set as expected\n");
3628 return -EAGAIN;
3629 }
3630
d89777bf
BA		 3631 /* L2: define ethertype filter for time stamped packets */
3632 if (is_l2)
3633 rxmtrl |= ETH_P_1588;
3634
3635 /* define which PTP packets get time stamped */
3636 ew32(RXMTRL, rxmtrl);
3637
3638 /* Filter by destination port */
3639 if (is_l4) {
3640 rxudp = PTP_EV_PORT;
3641 cpu_to_be16s(&rxudp);
3642 }
3643 ew32(RXUDP, rxudp);
3644
3645 e1e_flush();
3646
b67e1913 3647 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3648 er32(RXSTMPH);
3649 er32(TXSTMPH);
b67e1913
BA		 3650
3651 /* Get and set the System Time Register SYSTIM base frequency */
3652 ret_val = e1000e_get_base_timinca(adapter, &regval);
3653 if (ret_val)
3654 return ret_val;
3655 ew32(TIMINCA, regval);
3656
3657 /* reset the ns time counter */
3658 timecounter_init(&adapter->tc, &adapter->cc,
3659 ktime_to_ns(ktime_get_real()));
3660
3661 return 0;
3662}
3663
bc7f75fa 3664/**
ad68076e 3665 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3666 * @adapter: private board structure
3667 **/
3668static void e1000_configure(struct e1000_adapter *adapter)
3669{
55aa6985
BA		 3670 struct e1000_ring *rx_ring = adapter->rx_ring;
3671
ef9b965a 3672 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3673
3674 e1000_restore_vlan(adapter);
cd791618 3675 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3676
3677 e1000_configure_tx(adapter);
70495a50
BA		 3678
3679 if (adapter->netdev->features & NETIF_F_RXHASH)
3680 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3681 e1000_setup_rctl(adapter);
3682 e1000_configure_rx(adapter);
55aa6985 3683 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3684}
3685
3686/**
3687 * e1000e_power_up_phy - restore link in case the phy was powered down
3688 * @adapter: address of board private structure
3689 *
3690 * The phy may be powered down to save power and turn off link when the
3691 * driver is unloaded and wake on lan is not enabled (among others)
3692 * *** this routine MUST be followed by a call to e1000e_reset ***
3693 **/
3694void e1000e_power_up_phy(struct e1000_adapter *adapter)
3695{
17f208de
BA		 3696 if (adapter->hw.phy.ops.power_up)
3697 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3698
3699 adapter->hw.mac.ops.setup_link(&adapter->hw);
3700}
3701
3702/**
3703 * e1000_power_down_phy - Power down the PHY
3704 *
17f208de
BA		 3705 * Power down the PHY so no link is implied when interface is down.
3706 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3707 */
3708static void e1000_power_down_phy(struct e1000_adapter *adapter)
3709{
bc7f75fa 3710 /* WoL is enabled */
23b66e2b 3711 if (adapter->wol)
bc7f75fa
AK		 3712 return;
3713
17f208de
BA		 3714 if (adapter->hw.phy.ops.power_down)
3715 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3716}
3717
3718/**
3719 * e1000e_reset - bring the hardware into a known good state
3720 *
3721 * This function boots the hardware and enables some settings that
3722 * require a configuration cycle of the hardware - those cannot be
3723 * set/changed during runtime. After reset the device needs to be
ad68076e 3724 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3725 */
3726void e1000e_reset(struct e1000_adapter *adapter)
3727{
3728 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3729 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3730 struct e1000_hw *hw = &adapter->hw;
3731 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3732 u32 pba = adapter->pba;
bc7f75fa
AK		 3733 u16 hwm;
3734
ad68076e 3735 /* reset Packet Buffer Allocation to default */
318a94d6 3736 ew32(PBA, pba);
df762464 3737
318a94d6 3738 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3739 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3740 * large enough to accommodate two full transmit packets,
3741 * rounded up to the next 1KB and expressed in KB. Likewise,
3742 * the Rx FIFO should be large enough to accommodate at least
3743 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3744 * expressed in KB.
3745 */
df762464 3746 pba = er32(PBA);
bc7f75fa 3747 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3748 tx_space = pba >> 16;
bc7f75fa 3749 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3750 pba &= 0xffff;
e921eb1a 3751 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3752 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3753 */
3754 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3755 sizeof(struct e1000_tx_desc) -
3756 ETH_FCS_LEN) * 2;
3757 min_tx_space = ALIGN(min_tx_space, 1024);
3758 min_tx_space >>= 10;
3759 /* software strips receive CRC, so leave room for it */
318a94d6 3760 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3761 min_rx_space = ALIGN(min_rx_space, 1024);
3762 min_rx_space >>= 10;
3763
e921eb1a 3764 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3765 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3766 * allocation, take space away from current Rx allocation
3767 */
df762464
AK		 3768 if ((tx_space < min_tx_space) &&
3769 ((min_tx_space - tx_space) < pba)) {
3770 pba -= min_tx_space - tx_space;
bc7f75fa 3771
e921eb1a 3772 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3773 * adjustment
ad68076e 3774 */
79d4e908 3775 if (pba < min_rx_space)
df762464 3776 pba = min_rx_space;
bc7f75fa 3777 }
df762464
AK		 3778
3779 ew32(PBA, pba);
bc7f75fa
AK		 3780 }
3781
e921eb1a 3782 /* flow control settings
ad68076e 3783 *
38eb394e 3784 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3785 * (or the size used for early receive) above it in the Rx FIFO.
3786 * Set it to the lower of:
3787 * - 90% of the Rx FIFO size, and
38eb394e 3788 * - the full Rx FIFO size minus one full frame
ad68076e 3789 */
d3738bb8
BA		 3790 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3791 fc->pause_time = 0xFFFF;
3792 else
3793 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3794 fc->send_xon = true;
d3738bb8
BA		 3795 fc->current_mode = fc->requested_mode;
3796
3797 switch (hw->mac.type) {
79d4e908
BA		 3798 case e1000_ich9lan:
3799 case e1000_ich10lan:
3800 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3801 pba = 14;
3802 ew32(PBA, pba);
3803 fc->high_water = 0x2800;
3804 fc->low_water = fc->high_water - 8;
3805 break;
3806 }
3807 /* fall-through */
d3738bb8 3808 default:
79d4e908
BA		 3809 hwm = min(((pba << 10) * 9 / 10),
3810 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3811
3812 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3813 fc->low_water = fc->high_water - 8;
3814 break;
3815 case e1000_pchlan:
e921eb1a 3816 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3817 * loads. If hangs persist, try disabling Tx flow control.
3818 */
3819 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3820 fc->high_water = 0x3500;
3821 fc->low_water = 0x1500;
3822 } else {
3823 fc->high_water = 0x5000;
3824 fc->low_water = 0x3000;
3825 }
a305595b 3826 fc->refresh_time = 0x1000;
d3738bb8
BA		 3827 break;
3828 case e1000_pch2lan:
2fbe4526 3829 case e1000_pch_lpt:
d3738bb8 3830 fc->refresh_time = 0x0400;
347b5201
BA		 3831
3832 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3833 fc->high_water = 0x05C20;
3834 fc->low_water = 0x05048;
3835 fc->pause_time = 0x0650;
3836 break;
828bac87 3837 }
347b5201
BA		 3838
3839 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3840 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3841 break;
38eb394e 3842 }
bc7f75fa 3843
e921eb1a 3844 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3845 * maximum size per Tx descriptor limited only to the transmit
3846 * allocation of the packet buffer minus 96 bytes with an upper
3847 * limit of 24KB due to receive synchronization limitations.
3848 */
3849 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3850 24 << 10);
3851
e921eb1a 3852 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3853 * fit in receive buffer.
828bac87
BA		 3854 */
3855 if (adapter->itr_setting & 0x3) {
79d4e908 3856 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3857 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3858 dev_info(&adapter->pdev->dev,
3859 "Interrupt Throttle Rate turned off\n");
3860 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3861 e1000e_write_itr(adapter, 0);
828bac87
BA		 3862 }
3863 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3864 dev_info(&adapter->pdev->dev,
3865 "Interrupt Throttle Rate turned on\n");
3866 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3867 adapter->itr = 20000;
22a4cca2 3868 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3869 }
3870 }
3871
bc7f75fa
AK		 3872 /* Allow time for pending master requests to run */
3873 mac->ops.reset_hw(hw);
97ac8cae 3874
e921eb1a 3875 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3876 * that the network interface is in control
3877 */
c43bc57e 3878 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3879 e1000e_get_hw_control(adapter);
97ac8cae 3880
bc7f75fa
AK		 3881 ew32(WUC, 0);
3882
3883 if (mac->ops.init_hw(hw))
44defeb3 3884 e_err("Hardware Error\n");
bc7f75fa
AK		 3885
3886 e1000_update_mng_vlan(adapter);
3887
3888 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3889 ew32(VET, ETH_P_8021Q);
3890
3891 e1000e_reset_adaptive(hw);
31dbe5b4 3892
b67e1913
BA		 3893 /* initialize systim and reset the ns time counter */
3894 e1000e_config_hwtstamp(adapter);
3895
31dbe5b4
BA		 3896 if (!netif_running(adapter->netdev) &&
3897 !test_bit(__E1000_TESTING, &adapter->state)) {
3898 e1000_power_down_phy(adapter);
3899 return;
3900 }
3901
bc7f75fa
AK		 3902 e1000_get_phy_info(hw);
3903
918d7197
BA		 3904 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3905 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3906 u16 phy_data = 0;
e921eb1a 3907 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3908 * the return value of this function because there is nothing
ad68076e
BA		 3909 * different we would do if it failed
3910 */
bc7f75fa
AK		 3911 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3912 phy_data &= ~IGP02E1000_PM_SPD;
3913 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3914 }
bc7f75fa
AK		 3915}
3916
3917int e1000e_up(struct e1000_adapter *adapter)
3918{
3919 struct e1000_hw *hw = &adapter->hw;
3920
3921 /* hardware has been reset, we need to reload some things */
3922 e1000_configure(adapter);
3923
3924 clear_bit(__E1000_DOWN, &adapter->state);
3925
4662e82b
BA		 3926 if (adapter->msix_entries)
3927 e1000_configure_msix(adapter);
bc7f75fa
AK		 3928 e1000_irq_enable(adapter);
3929
400484fa 3930 netif_start_queue(adapter->netdev);
4cb9be7a 3931
bc7f75fa 3932 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3933 if (adapter->msix_entries)
3934 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3935 else
3936 ew32(ICS, E1000_ICS_LSC);
3937
bc7f75fa
AK		 3938 return 0;
3939}
3940
713b3c9e
JB		 3941static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3942{
3943 struct e1000_hw *hw = &adapter->hw;
3944
3945 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3946 return;
3947
3948 /* flush pending descriptor writebacks to memory */
3949 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3950 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3951
3952 /* execute the writes immediately */
3953 e1e_flush();
bf03085f 3954
e921eb1a 3955 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3956 * write is successful
3957 */
3958 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3959 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3960
3961 /* execute the writes immediately */
3962 e1e_flush();
3963}
3964
67fd4fcb
JK		 3965static void e1000e_update_stats(struct e1000_adapter *adapter);
3966
bc7f75fa
AK		 3967void e1000e_down(struct e1000_adapter *adapter)
3968{
3969 struct net_device *netdev = adapter->netdev;
3970 struct e1000_hw *hw = &adapter->hw;
3971 u32 tctl, rctl;
3972
e921eb1a 3973 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3974 * reschedule our watchdog timer
3975 */
bc7f75fa
AK		 3976 set_bit(__E1000_DOWN, &adapter->state);
3977
3978 /* disable receives in the hardware */
3979 rctl = er32(RCTL);
7f99ae63
BA		 3980 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3981 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3982 /* flush and sleep below */
3983
4cb9be7a 3984 netif_stop_queue(netdev);
bc7f75fa
AK		 3985
3986 /* disable transmits in the hardware */
3987 tctl = er32(TCTL);
3988 tctl &= ~E1000_TCTL_EN;
3989 ew32(TCTL, tctl);
7f99ae63 3990
bc7f75fa
AK		 3991 /* flush both disables and wait for them to finish */
3992 e1e_flush();
1bba4386 3993 usleep_range(10000, 20000);
bc7f75fa 3994
bc7f75fa
AK		 3995 e1000_irq_disable(adapter);
3996
3997 del_timer_sync(&adapter->watchdog_timer);
3998 del_timer_sync(&adapter->phy_info_timer);
3999
bc7f75fa 4000 netif_carrier_off(netdev);
67fd4fcb
JK		 4001
4002 spin_lock(&adapter->stats64_lock);
4003 e1000e_update_stats(adapter);
4004 spin_unlock(&adapter->stats64_lock);
4005
400484fa 4006 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4007 e1000_clean_tx_ring(adapter->tx_ring);
4008 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4009
bc7f75fa
AK		 4010 adapter->link_speed = 0;
4011 adapter->link_duplex = 0;
4012
52cc3086
JK		 4013 if (!pci_channel_offline(adapter->pdev))
4014 e1000e_reset(adapter);
713b3c9e 4015
e921eb1a 4016 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 4017 * pci_disable_device here.
4018 */
4019}
4020
4021void e1000e_reinit_locked(struct e1000_adapter *adapter)
4022{
4023 might_sleep();
4024 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4025 usleep_range(1000, 2000);
bc7f75fa
AK		 4026 e1000e_down(adapter);
4027 e1000e_up(adapter);
4028 clear_bit(__E1000_RESETTING, &adapter->state);
4029}
4030
b67e1913
BA		 4031/**
4032 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4033 * @cc: cyclecounter structure
4034 **/
4035static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4036{
4037 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4038 cc);
4039 struct e1000_hw *hw = &adapter->hw;
4040 cycle_t systim;
4041
4042 /* latch SYSTIMH on read of SYSTIML */
4043 systim = (cycle_t)er32(SYSTIML);
4044 systim |= (cycle_t)er32(SYSTIMH) << 32;
4045
4046 return systim;
4047}
4048
bc7f75fa
AK		 4049/**
4050 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4051 * @adapter: board private structure to initialize
4052 *
4053 * e1000_sw_init initializes the Adapter private data structure.
4054 * Fields are initialized based on PCI device information and
4055 * OS network device settings (MTU size).
4056 **/
9f9a12f8 4057static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4058{
bc7f75fa
AK		 4059 struct net_device *netdev = adapter->netdev;
4060
4061 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4062 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4063 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4064 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4065 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4066 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4067
67fd4fcb
JK		 4068 spin_lock_init(&adapter->stats64_lock);
4069
4662e82b 4070 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4071
4662e82b
BA		 4072 if (e1000_alloc_queues(adapter))
4073 return -ENOMEM;
bc7f75fa 4074
b67e1913
BA		 4075 /* Setup hardware time stamping cyclecounter */
4076 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4077 adapter->cc.read = e1000e_cyclecounter_read;
4078 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4079 adapter->cc.mult = 1;
4080 /* cc.shift set in e1000e_get_base_tininca() */
4081
4082 spin_lock_init(&adapter->systim_lock);
4083 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4084 }
4085
bc7f75fa 4086 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4087 e1000_irq_disable(adapter);
4088
bc7f75fa
AK		 4089 set_bit(__E1000_DOWN, &adapter->state);
4090 return 0;
bc7f75fa
AK		 4091}
4092
f8d59f78
BA		 4093/**
4094 * e1000_intr_msi_test - Interrupt Handler
4095 * @irq: interrupt number
4096 * @data: pointer to a network interface device structure
4097 **/
8bb62869 4098static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4099{
4100 struct net_device *netdev = data;
4101 struct e1000_adapter *adapter = netdev_priv(netdev);
4102 struct e1000_hw *hw = &adapter->hw;
4103 u32 icr = er32(ICR);
4104
3bb99fe2 4105 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4106 if (icr & E1000_ICR_RXSEQ) {
4107 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4108 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4109 * interrupt is handled.
4110 */
f8d59f78
BA		 4111 wmb();
4112 }
4113
4114 return IRQ_HANDLED;
4115}
4116
4117/**
4118 * e1000_test_msi_interrupt - Returns 0 for successful test
4119 * @adapter: board private struct
4120 *
4121 * code flow taken from tg3.c
4122 **/
4123static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4124{
4125 struct net_device *netdev = adapter->netdev;
4126 struct e1000_hw *hw = &adapter->hw;
4127 int err;
4128
4129 /* poll_enable hasn't been called yet, so don't need disable */
4130 /* clear any pending events */
4131 er32(ICR);
4132
4133 /* free the real vector and request a test handler */
4134 e1000_free_irq(adapter);
4662e82b 4135 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4136
4137 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4138 * MSI irq handler will unset this flag
4139 */
f8d59f78
BA		 4140 adapter->flags |= FLAG_MSI_TEST_FAILED;
4141
4142 err = pci_enable_msi(adapter->pdev);
4143 if (err)
4144 goto msi_test_failed;
4145
a0607fd3 4146 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4147 netdev->name, netdev);
4148 if (err) {
4149 pci_disable_msi(adapter->pdev);
4150 goto msi_test_failed;
4151 }
4152
e921eb1a 4153 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4154 * interrupt.
4155 */
f8d59f78
BA		 4156 wmb();
4157
4158 e1000_irq_enable(adapter);
4159
4160 /* fire an unusual interrupt on the test handler */
4161 ew32(ICS, E1000_ICS_RXSEQ);
4162 e1e_flush();
569a3aff 4163 msleep(100);
f8d59f78
BA		 4164
4165 e1000_irq_disable(adapter);
4166
bc76329d 4167 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4168
4169 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4170 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4171 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4172 } else {
068e8a30 4173 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4174 }
f8d59f78
BA		 4175
4176 free_irq(adapter->pdev->irq, netdev);
4177 pci_disable_msi(adapter->pdev);
4178
f8d59f78 4179msi_test_failed:
4662e82b 4180 e1000e_set_interrupt_capability(adapter);
068e8a30 4181 return e1000_request_irq(adapter);
f8d59f78
BA		 4182}
4183
4184/**
4185 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4186 * @adapter: board private struct
4187 *
4188 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4189 **/
4190static int e1000_test_msi(struct e1000_adapter *adapter)
4191{
4192 int err;
4193 u16 pci_cmd;
4194
4195 if (!(adapter->flags & FLAG_MSI_ENABLED))
4196 return 0;
4197
4198 /* disable SERR in case the MSI write causes a master abort */
4199 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4200 if (pci_cmd & PCI_COMMAND_SERR)
4201 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4202 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4203
4204 err = e1000_test_msi_interrupt(adapter);
4205
36f2407f
DN		 4206 /* re-enable SERR */
4207 if (pci_cmd & PCI_COMMAND_SERR) {
4208 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4209 pci_cmd |= PCI_COMMAND_SERR;
4210 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4211 }
f8d59f78 4212
f8d59f78
BA		 4213 return err;
4214}
4215
bc7f75fa
AK		 4216/**
4217 * e1000_open - Called when a network interface is made active
4218 * @netdev: network interface device structure
4219 *
4220 * Returns 0 on success, negative value on failure
4221 *
4222 * The open entry point is called when a network interface is made
4223 * active by the system (IFF_UP). At this point all resources needed
4224 * for transmit and receive operations are allocated, the interrupt
4225 * handler is registered with the OS, the watchdog timer is started,
4226 * and the stack is notified that the interface is ready.
4227 **/
4228static int e1000_open(struct net_device *netdev)
4229{
4230 struct e1000_adapter *adapter = netdev_priv(netdev);
4231 struct e1000_hw *hw = &adapter->hw;
23606cf5 4232 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4233 int err;
4234
4235 /* disallow open during test */
4236 if (test_bit(__E1000_TESTING, &adapter->state))
4237 return -EBUSY;
4238
23606cf5
RW		 4239 pm_runtime_get_sync(&pdev->dev);
4240
9c563d20
JB		 4241 netif_carrier_off(netdev);
4242
bc7f75fa 4243 /* allocate transmit descriptors */
55aa6985 4244 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4245 if (err)
4246 goto err_setup_tx;
4247
4248 /* allocate receive descriptors */
55aa6985 4249 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4250 if (err)
4251 goto err_setup_rx;
4252
e921eb1a 4253 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4254 * interface is now open and reset the part to a known state.
4255 */
4256 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4257 e1000e_get_hw_control(adapter);
11b08be8
BA		 4258 e1000e_reset(adapter);
4259 }
4260
bc7f75fa
AK		 4261 e1000e_power_up_phy(adapter);
4262
4263 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4264 if ((adapter->hw.mng_cookie.status &
4265 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4266 e1000_update_mng_vlan(adapter);
4267
79d4e908 4268 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4269 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4270 PM_QOS_DEFAULT_VALUE);
c128ec29 4271
e921eb1a 4272 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4273 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4274 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4275 * clean_rx handler before we do so.
4276 */
bc7f75fa
AK		 4277 e1000_configure(adapter);
4278
4279 err = e1000_request_irq(adapter);
4280 if (err)
4281 goto err_req_irq;
4282
e921eb1a 4283 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4284 * ignore e1000e MSI messages, which means we need to test our MSI
4285 * interrupt now
4286 */
4662e82b 4287 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4288 err = e1000_test_msi(adapter);
4289 if (err) {
4290 e_err("Interrupt allocation failed\n");
4291 goto err_req_irq;
4292 }
4293 }
4294
bc7f75fa
AK		 4295 /* From here on the code is the same as e1000e_up() */
4296 clear_bit(__E1000_DOWN, &adapter->state);
4297
4298 napi_enable(&adapter->napi);
4299
4300 e1000_irq_enable(adapter);
4301
09357b00 4302 adapter->tx_hang_recheck = false;
4cb9be7a 4303 netif_start_queue(netdev);
d55b53ff 4304
23606cf5
RW		 4305 adapter->idle_check = true;
4306 pm_runtime_put(&pdev->dev);
4307
bc7f75fa 4308 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4309 if (adapter->msix_entries)
4310 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4311 else
4312 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4313
4314 return 0;
4315
4316err_req_irq:
31dbe5b4 4317 e1000e_release_hw_control(adapter);
bc7f75fa 4318 e1000_power_down_phy(adapter);
55aa6985 4319 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4320err_setup_rx:
55aa6985 4321 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4322err_setup_tx:
4323 e1000e_reset(adapter);
23606cf5 4324 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4325
4326 return err;
4327}
4328
4329/**
4330 * e1000_close - Disables a network interface
4331 * @netdev: network interface device structure
4332 *
4333 * Returns 0, this is not allowed to fail
4334 *
4335 * The close entry point is called when an interface is de-activated
4336 * by the OS. The hardware is still under the drivers control, but
4337 * needs to be disabled. A global MAC reset is issued to stop the
4338 * hardware, and all transmit and receive resources are freed.
4339 **/
4340static int e1000_close(struct net_device *netdev)
4341{
4342 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4343 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4344 int count = E1000_CHECK_RESET_COUNT;
4345
4346 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4347 usleep_range(10000, 20000);
bc7f75fa
AK		 4348
4349 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4350
4351 pm_runtime_get_sync(&pdev->dev);
4352
5f4a780d
BA		 4353 napi_disable(&adapter->napi);
4354
23606cf5
RW		 4355 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4356 e1000e_down(adapter);
4357 e1000_free_irq(adapter);
4358 }
bc7f75fa 4359 e1000_power_down_phy(adapter);
bc7f75fa 4360
55aa6985
BA		 4361 e1000e_free_tx_resources(adapter->tx_ring);
4362 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4363
e921eb1a 4364 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4365 * the same ID is registered on the host OS (let 8021q kill it)
4366 */
86d70e53
JK		 4367 if (adapter->hw.mng_cookie.status &
4368 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4369 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4370
e921eb1a 4371 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4372 * interface is now closed
4373 */
31dbe5b4
BA		 4374 if ((adapter->flags & FLAG_HAS_AMT) &&
4375 !test_bit(__E1000_TESTING, &adapter->state))
4376 e1000e_release_hw_control(adapter);
bc7f75fa 4377
3e35d991 4378 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4379
23606cf5
RW		 4380 pm_runtime_put_sync(&pdev->dev);
4381
bc7f75fa
AK		 4382 return 0;
4383}
4384/**
4385 * e1000_set_mac - Change the Ethernet Address of the NIC
4386 * @netdev: network interface device structure
4387 * @p: pointer to an address structure
4388 *
4389 * Returns 0 on success, negative on failure
4390 **/
4391static int e1000_set_mac(struct net_device *netdev, void *p)
4392{
4393 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4394 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4395 struct sockaddr *addr = p;
4396
4397 if (!is_valid_ether_addr(addr->sa_data))
4398 return -EADDRNOTAVAIL;
4399
4400 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4401 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4402
69e1e019 4403 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4404
4405 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4406 /* activate the work around */
4407 e1000e_set_laa_state_82571(&adapter->hw, 1);
4408
e921eb1a 4409 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4410 * between the time RAR[0] gets clobbered and the time it
4411 * gets fixed (in e1000_watchdog), the actual LAA is in one
4412 * of the RARs and no incoming packets directed to this port
4413 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4414 * RAR[14]
4415 */
69e1e019
BA		 4416 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4417 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4418 }
4419
4420 return 0;
4421}
4422
a8f88ff5
JB		 4423/**
4424 * e1000e_update_phy_task - work thread to update phy
4425 * @work: pointer to our work struct
4426 *
4427 * this worker thread exists because we must acquire a
4428 * semaphore to read the phy, which we could msleep while
4429 * waiting for it, and we can't msleep in a timer.
4430 **/
4431static void e1000e_update_phy_task(struct work_struct *work)
4432{
4433 struct e1000_adapter *adapter = container_of(work,
4434 struct e1000_adapter, update_phy_task);
615b32af
JB		 4435
4436 if (test_bit(__E1000_DOWN, &adapter->state))
4437 return;
4438
a8f88ff5
JB		 4439 e1000_get_phy_info(&adapter->hw);
4440}
4441
e921eb1a
BA		 4442/**
4443 * e1000_update_phy_info - timre call-back to update PHY info
4444 * @data: pointer to adapter cast into an unsigned long
4445 *
ad68076e
BA		 4446 * Need to wait a few seconds after link up to get diagnostic information from
4447 * the phy
e921eb1a 4448 **/
bc7f75fa
AK		 4449static void e1000_update_phy_info(unsigned long data)
4450{
4451 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4452
4453 if (test_bit(__E1000_DOWN, &adapter->state))
4454 return;
4455
a8f88ff5 4456 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4457}
4458
8c7bbb92
BA		 4459/**
4460 * e1000e_update_phy_stats - Update the PHY statistics counters
4461 * @adapter: board private structure
2b6b168d
BA		 4462 *
4463 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4464 **/
4465static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4466{
4467 struct e1000_hw *hw = &adapter->hw;
4468 s32 ret_val;
4469 u16 phy_data;
4470
4471 ret_val = hw->phy.ops.acquire(hw);
4472 if (ret_val)
4473 return;
4474
e921eb1a 4475 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4476 * If not, set to the page with the PHY status registers.
4477 */
2b6b168d 4478 hw->phy.addr = 1;
8c7bbb92
BA		 4479 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4480 &phy_data);
4481 if (ret_val)
4482 goto release;
2b6b168d
BA		 4483 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4484 ret_val = hw->phy.ops.set_page(hw,
4485 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4486 if (ret_val)
4487 goto release;
4488 }
4489
8c7bbb92 4490 /* Single Collision Count */
2b6b168d
BA		 4491 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4492 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4493 if (!ret_val)
4494 adapter->stats.scc += phy_data;
4495
4496 /* Excessive Collision Count */
2b6b168d
BA		 4497 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4498 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4499 if (!ret_val)
4500 adapter->stats.ecol += phy_data;
4501
4502 /* Multiple Collision Count */
2b6b168d
BA		 4503 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4504 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4505 if (!ret_val)
4506 adapter->stats.mcc += phy_data;
4507
4508 /* Late Collision Count */
2b6b168d
BA		 4509 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4510 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4511 if (!ret_val)
4512 adapter->stats.latecol += phy_data;
4513
4514 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4515 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4516 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4517 if (!ret_val)
4518 hw->mac.collision_delta = phy_data;
4519
4520 /* Defer Count */
2b6b168d
BA		 4521 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4522 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4523 if (!ret_val)
4524 adapter->stats.dc += phy_data;
4525
4526 /* Transmit with no CRS */
2b6b168d
BA		 4527 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4528 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4529 if (!ret_val)
4530 adapter->stats.tncrs += phy_data;
4531
4532release:
4533 hw->phy.ops.release(hw);
4534}
4535
bc7f75fa
AK		 4536/**
4537 * e1000e_update_stats - Update the board statistics counters
4538 * @adapter: board private structure
4539 **/
67fd4fcb 4540static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4541{
7274c20f 4542 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4543 struct e1000_hw *hw = &adapter->hw;
4544 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4545
e921eb1a 4546 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4547 * connection is down.
4548 */
4549 if (adapter->link_speed == 0)
4550 return;
4551 if (pci_channel_offline(pdev))
4552 return;
4553
bc7f75fa
AK		 4554 adapter->stats.crcerrs += er32(CRCERRS);
4555 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4556 adapter->stats.gorc += er32(GORCL);
4557 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4558 adapter->stats.bprc += er32(BPRC);
4559 adapter->stats.mprc += er32(MPRC);
4560 adapter->stats.roc += er32(ROC);
4561
bc7f75fa 4562 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4563
4564 /* Half-duplex statistics */
4565 if (adapter->link_duplex == HALF_DUPLEX) {
4566 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4567 e1000e_update_phy_stats(adapter);
4568 } else {
4569 adapter->stats.scc += er32(SCC);
4570 adapter->stats.ecol += er32(ECOL);
4571 adapter->stats.mcc += er32(MCC);
4572 adapter->stats.latecol += er32(LATECOL);
4573 adapter->stats.dc += er32(DC);
4574
4575 hw->mac.collision_delta = er32(COLC);
4576
4577 if ((hw->mac.type != e1000_82574) &&
4578 (hw->mac.type != e1000_82583))
4579 adapter->stats.tncrs += er32(TNCRS);
4580 }
4581 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4582 }
8c7bbb92 4583
bc7f75fa
AK		 4584 adapter->stats.xonrxc += er32(XONRXC);
4585 adapter->stats.xontxc += er32(XONTXC);
4586 adapter->stats.xoffrxc += er32(XOFFRXC);
4587 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4588 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4589 adapter->stats.gotc += er32(GOTCL);
4590 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4591 adapter->stats.rnbc += er32(RNBC);
4592 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4593
4594 adapter->stats.mptc += er32(MPTC);
4595 adapter->stats.bptc += er32(BPTC);
4596
4597 /* used for adaptive IFS */
4598
4599 hw->mac.tx_packet_delta = er32(TPT);
4600 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4601
4602 adapter->stats.algnerrc += er32(ALGNERRC);
4603 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4604 adapter->stats.cexterr += er32(CEXTERR);
4605 adapter->stats.tsctc += er32(TSCTC);
4606 adapter->stats.tsctfc += er32(TSCTFC);
4607
bc7f75fa 4608 /* Fill out the OS statistics structure */
7274c20f
AK		 4609 netdev->stats.multicast = adapter->stats.mprc;
4610 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4611
4612 /* Rx Errors */
4613
e921eb1a 4614 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4615 * our own version based on RUC and ROC
4616 */
7274c20f 4617 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4618 adapter->stats.crcerrs + adapter->stats.algnerrc +
4619 adapter->stats.ruc + adapter->stats.roc +
4620 adapter->stats.cexterr;
7274c20f 4621 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4622 adapter->stats.roc;
7274c20f
AK		 4623 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4624 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4625 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4626
4627 /* Tx Errors */
7274c20f 4628 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4629 adapter->stats.latecol;
7274c20f
AK		 4630 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4631 netdev->stats.tx_window_errors = adapter->stats.latecol;
4632 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4633
4634 /* Tx Dropped needs to be maintained elsewhere */
4635
bc7f75fa
AK		 4636 /* Management Stats */
4637 adapter->stats.mgptc += er32(MGTPTC);
4638 adapter->stats.mgprc += er32(MGTPRC);
4639 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4640
4641 /* Correctable ECC Errors */
4642 if (hw->mac.type == e1000_pch_lpt) {
4643 u32 pbeccsts = er32(PBECCSTS);
4644 adapter->corr_errors +=
4645 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4646 adapter->uncorr_errors +=
4647 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4648 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4649 }
bc7f75fa
AK		 4650}
4651
7c25769f
BA		 4652/**
4653 * e1000_phy_read_status - Update the PHY register status snapshot
4654 * @adapter: board private structure
4655 **/
4656static void e1000_phy_read_status(struct e1000_adapter *adapter)
4657{
4658 struct e1000_hw *hw = &adapter->hw;
4659 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4660
4661 if ((er32(STATUS) & E1000_STATUS_LU) &&
4662 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4663 int ret_val;
4664
c2ade1a4
BA		 4665 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4666 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4667 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4668 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4669 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4670 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4671 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4672 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4673 if (ret_val)
44defeb3 4674 e_warn("Error reading PHY register\n");
7c25769f 4675 } else {
e921eb1a 4676 /* Do not read PHY registers if link is not up
7c25769f
BA		 4677 * Set values to typical power-on defaults
4678 */
4679 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4680 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4681 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4682 BMSR_ERCAP);
4683 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4684 ADVERTISE_ALL | ADVERTISE_CSMA);
4685 phy->lpa = 0;
4686 phy->expansion = EXPANSION_ENABLENPAGE;
4687 phy->ctrl1000 = ADVERTISE_1000FULL;
4688 phy->stat1000 = 0;
4689 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4690 }
7c25769f
BA		 4691}
4692
bc7f75fa
AK		 4693static void e1000_print_link_info(struct e1000_adapter *adapter)
4694{
bc7f75fa
AK		 4695 struct e1000_hw *hw = &adapter->hw;
4696 u32 ctrl = er32(CTRL);
4697
8f12fe86 4698 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4699 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4700 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4701 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4702 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4703 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4704 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4705}
4706
0c6bdb30 4707static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4708{
4709 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4710 bool link_active = false;
318a94d6
JK		 4711 s32 ret_val = 0;
4712
e921eb1a 4713 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4714 * Rx sequence error interrupt. get_link_status will stay
4715 * false until the check_for_link establishes link
4716 * for copper adapters ONLY
4717 */
4718 switch (hw->phy.media_type) {
4719 case e1000_media_type_copper:
4720 if (hw->mac.get_link_status) {
4721 ret_val = hw->mac.ops.check_for_link(hw);
4722 link_active = !hw->mac.get_link_status;
4723 } else {
3db1cd5c 4724 link_active = true;
318a94d6
JK		 4725 }
4726 break;
4727 case e1000_media_type_fiber:
4728 ret_val = hw->mac.ops.check_for_link(hw);
4729 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4730 break;
4731 case e1000_media_type_internal_serdes:
4732 ret_val = hw->mac.ops.check_for_link(hw);
4733 link_active = adapter->hw.mac.serdes_has_link;
4734 break;
4735 default:
4736 case e1000_media_type_unknown:
4737 break;
4738 }
4739
4740 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4741 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4742 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4743 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4744 }
4745
4746 return link_active;
4747}
4748
4749static void e1000e_enable_receives(struct e1000_adapter *adapter)
4750{
4751 /* make sure the receive unit is started */
4752 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4753 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4754 struct e1000_hw *hw = &adapter->hw;
4755 u32 rctl = er32(RCTL);
4756 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4757 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4758 }
4759}
4760
ff10e13c
CW		 4761static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4762{
4763 struct e1000_hw *hw = &adapter->hw;
4764
e921eb1a 4765 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4766 * for hung state and reset, if two calls return true
4767 */
4768 if (e1000_check_phy_82574(hw))
4769 adapter->phy_hang_count++;
4770 else
4771 adapter->phy_hang_count = 0;
4772
4773 if (adapter->phy_hang_count > 1) {
4774 adapter->phy_hang_count = 0;
4775 schedule_work(&adapter->reset_task);
4776 }
4777}
4778
bc7f75fa
AK		 4779/**
4780 * e1000_watchdog - Timer Call-back
4781 * @data: pointer to adapter cast into an unsigned long
4782 **/
4783static void e1000_watchdog(unsigned long data)
4784{
4785 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4786
4787 /* Do the rest outside of interrupt context */
4788 schedule_work(&adapter->watchdog_task);
4789
4790 /* TODO: make this use queue_delayed_work() */
4791}
4792
4793static void e1000_watchdog_task(struct work_struct *work)
4794{
4795 struct e1000_adapter *adapter = container_of(work,
4796 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4797 struct net_device *netdev = adapter->netdev;
4798 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4799 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4800 struct e1000_ring *tx_ring = adapter->tx_ring;
4801 struct e1000_hw *hw = &adapter->hw;
4802 u32 link, tctl;
bc7f75fa 4803
615b32af
JB		 4804 if (test_bit(__E1000_DOWN, &adapter->state))
4805 return;
4806
b405e8df 4807 link = e1000e_has_link(adapter);
318a94d6 4808 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4809 /* Cancel scheduled suspend requests. */
4810 pm_runtime_resume(netdev->dev.parent);
4811
318a94d6 4812 e1000e_enable_receives(adapter);
bc7f75fa 4813 goto link_up;
bc7f75fa
AK		 4814 }
4815
4816 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4817 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4818 e1000_update_mng_vlan(adapter);
4819
bc7f75fa
AK		 4820 if (link) {
4821 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4822 bool txb2b = true;
23606cf5
RW		 4823
4824 /* Cancel scheduled suspend requests. */
4825 pm_runtime_resume(netdev->dev.parent);
4826
318a94d6 4827 /* update snapshot of PHY registers on LSC */
7c25769f 4828 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4829 mac->ops.get_link_up_info(&adapter->hw,
4830 &adapter->link_speed,
4831 &adapter->link_duplex);
4832 e1000_print_link_info(adapter);
e921eb1a 4833 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4834 * if link has autonegotiated at 10/100 half
4835 */
4836 if ((hw->phy.type == e1000_phy_igp_3 ||
4837 hw->phy.type == e1000_phy_bm) &&
4838 (hw->mac.autoneg == true) &&
4839 (adapter->link_speed == SPEED_10 ||
4840 adapter->link_speed == SPEED_100) &&
4841 (adapter->link_duplex == HALF_DUPLEX)) {
4842 u16 autoneg_exp;
4843
c2ade1a4 4844 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4845
c2ade1a4 4846 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4847 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4848 }
4849
f49c57e1 4850 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4851 adapter->tx_timeout_factor = 1;
4852 switch (adapter->link_speed) {
4853 case SPEED_10:
3db1cd5c 4854 txb2b = false;
10f1b492 4855 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4856 break;
4857 case SPEED_100:
3db1cd5c 4858 txb2b = false;
4c86e0b9 4859 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4860 break;
4861 }
4862
e921eb1a 4863 /* workaround: re-program speed mode bit after
ad68076e
BA		 4864 * link-up event
4865 */
bc7f75fa
AK		 4866 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4867 !txb2b) {
4868 u32 tarc0;
e9ec2c0f 4869 tarc0 = er32(TARC(0));
bc7f75fa 4870 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4871 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4872 }
4873
e921eb1a 4874 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4875 * some hardware issues
4876 */
bc7f75fa
AK		 4877 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4878 switch (adapter->link_speed) {
4879 case SPEED_10:
4880 case SPEED_100:
44defeb3 4881 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4882 netdev->features &= ~NETIF_F_TSO;
4883 netdev->features &= ~NETIF_F_TSO6;
4884 break;
4885 case SPEED_1000:
4886 netdev->features |= NETIF_F_TSO;
4887 netdev->features |= NETIF_F_TSO6;
4888 break;
4889 default:
4890 /* oops */
4891 break;
4892 }
4893 }
4894
e921eb1a 4895 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4896 * after setting TARC(0)
4897 */
bc7f75fa
AK		 4898 tctl = er32(TCTL);
4899 tctl |= E1000_TCTL_EN;
4900 ew32(TCTL, tctl);
4901
e921eb1a 4902 /* Perform any post-link-up configuration before
75eb0fad
BA		 4903 * reporting link up.
4904 */
4905 if (phy->ops.cfg_on_link_up)
4906 phy->ops.cfg_on_link_up(hw);
4907
bc7f75fa 4908 netif_carrier_on(netdev);
bc7f75fa
AK		 4909
4910 if (!test_bit(__E1000_DOWN, &adapter->state))
4911 mod_timer(&adapter->phy_info_timer,
4912 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4913 }
4914 } else {
4915 if (netif_carrier_ok(netdev)) {
4916 adapter->link_speed = 0;
4917 adapter->link_duplex = 0;
8f12fe86 4918 /* Link status message must follow this format */
7dbc1672 4919 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4920 netif_carrier_off(netdev);
bc7f75fa
AK		 4921 if (!test_bit(__E1000_DOWN, &adapter->state))
4922 mod_timer(&adapter->phy_info_timer,
4923 round_jiffies(jiffies + 2 * HZ));
4924
12d43f7d
BA		 4925 /* The link is lost so the controller stops DMA.
4926 * If there is queued Tx work that cannot be done
4927 * or if on an 8000ES2LAN which requires a Rx packet
4928 * buffer work-around on link down event, reset the
4929 * controller to flush the Tx/Rx packet buffers.
4930 * (Do the reset outside of interrupt context).
4931 */
4932 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4933 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4934 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4935 else
4936 pm_schedule_suspend(netdev->dev.parent,
4937 LINK_TIMEOUT);
bc7f75fa
AK		 4938 }
4939 }
4940
4941link_up:
67fd4fcb 4942 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4943 e1000e_update_stats(adapter);
4944
4945 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4946 adapter->tpt_old = adapter->stats.tpt;
4947 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4948 adapter->colc_old = adapter->stats.colc;
4949
7c25769f
BA		 4950 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4951 adapter->gorc_old = adapter->stats.gorc;
4952 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4953 adapter->gotc_old = adapter->stats.gotc;
2084b114 4954 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4955
12d43f7d 4956 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4957 schedule_work(&adapter->reset_task);
4958 /* return immediately since reset is imminent */
4959 return;
bc7f75fa
AK		 4960 }
4961
12d43f7d
BA		 4962 e1000e_update_adaptive(&adapter->hw);
4963
eab2abf5
JB		 4964 /* Simple mode for Interrupt Throttle Rate (ITR) */
4965 if (adapter->itr_setting == 4) {
e921eb1a 4966 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4967 * Total asymmetrical Tx or Rx gets ITR=8000;
4968 * everyone else is between 2000-8000.
4969 */
4970 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4971 u32 dif = (adapter->gotc > adapter->gorc ?
4972 adapter->gotc - adapter->gorc :
4973 adapter->gorc - adapter->gotc) / 10000;
4974 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4975
22a4cca2 4976 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4977 }
4978
ad68076e 4979 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4980 if (adapter->msix_entries)
4981 ew32(ICS, adapter->rx_ring->ims_val);
4982 else
4983 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4984
713b3c9e
JB		 4985 /* flush pending descriptors to memory before detecting Tx hang */
4986 e1000e_flush_descriptors(adapter);
4987
bc7f75fa 4988 /* Force detection of hung controller every watchdog period */
3db1cd5c 4989 adapter->detect_tx_hung = true;
bc7f75fa 4990
e921eb1a 4991 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 4992 * reset from the other port. Set the appropriate LAA in RAR[0]
4993 */
bc7f75fa 4994 if (e1000e_get_laa_state_82571(hw))
69e1e019 4995 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4996
ff10e13c
CW		 4997 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4998 e1000e_check_82574_phy_workaround(adapter);
4999
b67e1913
BA		 5000 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5001 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5002 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5003 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5004 er32(RXSTMPH);
5005 adapter->rx_hwtstamp_cleared++;
5006 } else {
5007 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5008 }
5009 }
5010
bc7f75fa
AK		 5011 /* Reset the timer */
5012 if (!test_bit(__E1000_DOWN, &adapter->state))
5013 mod_timer(&adapter->watchdog_timer,
5014 round_jiffies(jiffies + 2 * HZ));
5015}
5016
5017#define E1000_TX_FLAGS_CSUM 0x00000001
5018#define E1000_TX_FLAGS_VLAN 0x00000002
5019#define E1000_TX_FLAGS_TSO 0x00000004
5020#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5021#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5022#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5023#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5024#define E1000_TX_FLAGS_VLAN_SHIFT 16
5025
55aa6985 5026static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5027{
bc7f75fa
AK		 5028 struct e1000_context_desc *context_desc;
5029 struct e1000_buffer *buffer_info;
5030 unsigned int i;
5031 u32 cmd_length = 0;
70443ae9 5032 u16 ipcse = 0, mss;
bc7f75fa 5033 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5034
3d5e33c9
BA		 5035 if (!skb_is_gso(skb))
5036 return 0;
bc7f75fa 5037
3d5e33c9 5038 if (skb_header_cloned(skb)) {
90da0669
BA		 5039 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5040
3d5e33c9
BA		 5041 if (err)
5042 return err;
bc7f75fa
AK		 5043 }
5044
3d5e33c9
BA		 5045 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5046 mss = skb_shinfo(skb)->gso_size;
5047 if (skb->protocol == htons(ETH_P_IP)) {
5048 struct iphdr *iph = ip_hdr(skb);
5049 iph->tot_len = 0;
5050 iph->check = 0;
5051 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5052 0, IPPROTO_TCP, 0);
5053 cmd_length = E1000_TXD_CMD_IP;
5054 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5055 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5056 ipv6_hdr(skb)->payload_len = 0;
5057 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5058 &ipv6_hdr(skb)->daddr,
5059 0, IPPROTO_TCP, 0);
5060 ipcse = 0;
5061 }
5062 ipcss = skb_network_offset(skb);
5063 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5064 tucss = skb_transport_offset(skb);
5065 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5066
5067 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5068 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5069
5070 i = tx_ring->next_to_use;
5071 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5072 buffer_info = &tx_ring->buffer_info[i];
5073
5074 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5075 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5076 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5077 context_desc->upper_setup.tcp_fields.tucss = tucss;
5078 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5079 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 5080 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5081 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5082 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5083
5084 buffer_info->time_stamp = jiffies;
5085 buffer_info->next_to_watch = i;
5086
5087 i++;
5088 if (i == tx_ring->count)
5089 i = 0;
5090 tx_ring->next_to_use = i;
5091
5092 return 1;
bc7f75fa
AK		 5093}
5094
55aa6985 5095static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5096{
55aa6985 5097 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5098 struct e1000_context_desc *context_desc;
5099 struct e1000_buffer *buffer_info;
5100 unsigned int i;
5101 u8 css;
af807c82 5102 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5103 __be16 protocol;
bc7f75fa 5104
af807c82
DG		 5105 if (skb->ip_summed != CHECKSUM_PARTIAL)
5106 return 0;
bc7f75fa 5107
5f66f208
AJ		 5108 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5109 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5110 else
5111 protocol = skb->protocol;
5112
3f518390 5113 switch (protocol) {
09640e63 5114 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5115 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5116 cmd_len |= E1000_TXD_CMD_TCP;
5117 break;
09640e63 5118 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5119 /* XXX not handling all IPV6 headers */
5120 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5121 cmd_len |= E1000_TXD_CMD_TCP;
5122 break;
5123 default:
5124 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5125 e_warn("checksum_partial proto=%x!\n",
5126 be16_to_cpu(protocol));
af807c82 5127 break;
bc7f75fa
AK		 5128 }
5129
0d0b1672 5130 css = skb_checksum_start_offset(skb);
af807c82
DG		 5131
5132 i = tx_ring->next_to_use;
5133 buffer_info = &tx_ring->buffer_info[i];
5134 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5135
5136 context_desc->lower_setup.ip_config = 0;
5137 context_desc->upper_setup.tcp_fields.tucss = css;
5138 context_desc->upper_setup.tcp_fields.tucso =
5139 css + skb->csum_offset;
5140 context_desc->upper_setup.tcp_fields.tucse = 0;
5141 context_desc->tcp_seg_setup.data = 0;
5142 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5143
5144 buffer_info->time_stamp = jiffies;
5145 buffer_info->next_to_watch = i;
5146
5147 i++;
5148 if (i == tx_ring->count)
5149 i = 0;
5150 tx_ring->next_to_use = i;
5151
5152 return 1;
bc7f75fa
AK		 5153}
5154
55aa6985
BA		 5155static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5156 unsigned int first, unsigned int max_per_txd,
d821a4c4 5157 unsigned int nr_frags)
bc7f75fa 5158{
55aa6985 5159 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5160 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5161 struct e1000_buffer *buffer_info;
8ddc951c 5162 unsigned int len = skb_headlen(skb);
03b1320d 5163 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5164 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5165
5166 i = tx_ring->next_to_use;
5167
5168 while (len) {
1b7719c4 5169 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5170 size = min(len, max_per_txd);
5171
bc7f75fa 5172 buffer_info->length = size;
bc7f75fa 5173 buffer_info->time_stamp = jiffies;
bc7f75fa 5174 buffer_info->next_to_watch = i;
0be3f55f
NN		 5175 buffer_info->dma = dma_map_single(&pdev->dev,
5176 skb->data + offset,
af667a29 5177 size, DMA_TO_DEVICE);
03b1320d 5178 buffer_info->mapped_as_page = false;
0be3f55f 5179 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5180 goto dma_error;
bc7f75fa
AK		 5181
5182 len -= size;
5183 offset += size;
03b1320d 5184 count++;
1b7719c4
AD		 5185
5186 if (len) {
5187 i++;
5188 if (i == tx_ring->count)
5189 i = 0;
5190 }
bc7f75fa
AK		 5191 }
5192
5193 for (f = 0; f < nr_frags; f++) {
9e903e08 5194 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5195
5196 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5197 len = skb_frag_size(frag);
877749bf 5198 offset = 0;
bc7f75fa
AK		 5199
5200 while (len) {
1b7719c4
AD		 5201 i++;
5202 if (i == tx_ring->count)
5203 i = 0;
5204
bc7f75fa
AK		 5205 buffer_info = &tx_ring->buffer_info[i];
5206 size = min(len, max_per_txd);
bc7f75fa
AK		 5207
5208 buffer_info->length = size;
5209 buffer_info->time_stamp = jiffies;
bc7f75fa 5210 buffer_info->next_to_watch = i;
877749bf
IC		 5211 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5212 offset, size, DMA_TO_DEVICE);
03b1320d 5213 buffer_info->mapped_as_page = true;
0be3f55f 5214 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5215 goto dma_error;
bc7f75fa
AK		 5216
5217 len -= size;
5218 offset += size;
5219 count++;
bc7f75fa
AK		 5220 }
5221 }
5222
af667a29 5223 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5224 /* multiply data chunks by size of headers */
5225 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5226
bc7f75fa 5227 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5228 tx_ring->buffer_info[i].segs = segs;
5229 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5230 tx_ring->buffer_info[first].next_to_watch = i;
5231
5232 return count;
03b1320d
AD		 5233
5234dma_error:
af667a29 5235 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5236 buffer_info->dma = 0;
c1fa347f 5237 if (count)
03b1320d 5238 count--;
c1fa347f
RK		 5239
5240 while (count--) {
af667a29 5241 if (i == 0)
03b1320d 5242 i += tx_ring->count;
c1fa347f 5243 i--;
03b1320d 5244 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5245 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5246 }
5247
5248 return 0;
bc7f75fa
AK		 5249}
5250
55aa6985 5251static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5252{
55aa6985 5253 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5254 struct e1000_tx_desc *tx_desc = NULL;
5255 struct e1000_buffer *buffer_info;
5256 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5257 unsigned int i;
5258
5259 if (tx_flags & E1000_TX_FLAGS_TSO) {
5260 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5261 E1000_TXD_CMD_TSE;
5262 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5263
5264 if (tx_flags & E1000_TX_FLAGS_IPV4)
5265 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5266 }
5267
5268 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5269 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5270 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5271 }
5272
5273 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5274 txd_lower |= E1000_TXD_CMD_VLE;
5275 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5276 }
5277
943146de
BG		 5278 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5279 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5280
b67e1913
BA		 5281 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5282 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5283 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5284 }
5285
bc7f75fa
AK		 5286 i = tx_ring->next_to_use;
5287
36b973df 5288 do {
bc7f75fa
AK		 5289 buffer_info = &tx_ring->buffer_info[i];
5290 tx_desc = E1000_TX_DESC(*tx_ring, i);
5291 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5292 tx_desc->lower.data =
5293 cpu_to_le32(txd_lower | buffer_info->length);
5294 tx_desc->upper.data = cpu_to_le32(txd_upper);
5295
5296 i++;
5297 if (i == tx_ring->count)
5298 i = 0;
36b973df 5299 } while (--count > 0);
bc7f75fa
AK		 5300
5301 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5302
943146de
BG		 5303 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5304 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5305 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5306
e921eb1a 5307 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5308 * know there are new descriptors to fetch. (Only
5309 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5310 * such as IA-64).
5311 */
bc7f75fa
AK		 5312 wmb();
5313
5314 tx_ring->next_to_use = i;
c6e7f51e
BA		 5315
5316 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5317 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5318 else
c5083cf6 5319 writel(i, tx_ring->tail);
c6e7f51e 5320
e921eb1a 5321 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5322 * at a time, it synchronizes IO on IA64/Altix systems
5323 */
bc7f75fa
AK		 5324 mmiowb();
5325}
5326
5327#define MINIMUM_DHCP_PACKET_SIZE 282
5328static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5329 struct sk_buff *skb)
5330{
5331 struct e1000_hw *hw = &adapter->hw;
5332 u16 length, offset;
5333
d60923c4
BA		 5334 if (vlan_tx_tag_present(skb) &&
5335 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5336 (adapter->hw.mng_cookie.status &
5337 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5338 return 0;
bc7f75fa
AK		 5339
5340 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5341 return 0;
5342
5343 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
5344 return 0;
5345
5346 {
5347 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
5348 struct udphdr *udp;
5349
5350 if (ip->protocol != IPPROTO_UDP)
5351 return 0;
5352
5353 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5354 if (ntohs(udp->dest) != 67)
5355 return 0;
5356
5357 offset = (u8 *)udp + 8 - skb->data;
5358 length = skb->len - offset;
5359 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5360 }
5361
5362 return 0;
5363}
5364
55aa6985 5365static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5366{
55aa6985 5367 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5368
55aa6985 5369 netif_stop_queue(adapter->netdev);
e921eb1a 5370 /* Herbert's original patch had:
bc7f75fa 5371 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5372 * but since that doesn't exist yet, just open code it.
5373 */
bc7f75fa
AK		 5374 smp_mb();
5375
e921eb1a 5376 /* We need to check again in a case another CPU has just
ad68076e
BA		 5377 * made room available.
5378 */
55aa6985 5379 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5380 return -EBUSY;
5381
5382 /* A reprieve! */
55aa6985 5383 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5384 ++adapter->restart_queue;
5385 return 0;
5386}
5387
55aa6985 5388static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5389{
d821a4c4
BA		 5390 BUG_ON(size > tx_ring->count);
5391
55aa6985 5392 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5393 return 0;
55aa6985 5394 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5395}
5396
3b29a56d
SH		 5397static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5398 struct net_device *netdev)
bc7f75fa
AK		 5399{
5400 struct e1000_adapter *adapter = netdev_priv(netdev);
5401 struct e1000_ring *tx_ring = adapter->tx_ring;
5402 unsigned int first;
bc7f75fa 5403 unsigned int tx_flags = 0;
e743d313 5404 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5405 unsigned int nr_frags;
5406 unsigned int mss;
bc7f75fa
AK		 5407 int count = 0;
5408 int tso;
5409 unsigned int f;
bc7f75fa
AK		 5410
5411 if (test_bit(__E1000_DOWN, &adapter->state)) {
5412 dev_kfree_skb_any(skb);
5413 return NETDEV_TX_OK;
5414 }
5415
5416 if (skb->len <= 0) {
5417 dev_kfree_skb_any(skb);
5418 return NETDEV_TX_OK;
5419 }
5420
e921eb1a 5421 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5422 * pad skb in order to meet this minimum size requirement
5423 */
5424 if (unlikely(skb->len < 17)) {
5425 if (skb_pad(skb, 17 - skb->len))
5426 return NETDEV_TX_OK;
5427 skb->len = 17;
5428 skb_set_tail_pointer(skb, 17);
5429 }
5430
bc7f75fa 5431 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5432 if (mss) {
5433 u8 hdr_len;
bc7f75fa 5434
e921eb1a 5435 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5436 * points to just header, pull a few bytes of payload from
5437 * frags into skb->data
5438 */
bc7f75fa 5439 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5440 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5441 * avoiding it could save a lot of cycles
5442 */
4e6c709c 5443 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5444 unsigned int pull_size;
5445
a2a5b323 5446 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5447 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5448 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5449 dev_kfree_skb_any(skb);
5450 return NETDEV_TX_OK;
5451 }
e743d313 5452 len = skb_headlen(skb);
bc7f75fa
AK		 5453 }
5454 }
5455
5456 /* reserve a descriptor for the offload context */
5457 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5458 count++;
5459 count++;
5460
d821a4c4 5461 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5462
5463 nr_frags = skb_shinfo(skb)->nr_frags;
5464 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5465 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5466 adapter->tx_fifo_limit);
bc7f75fa
AK		 5467
5468 if (adapter->hw.mac.tx_pkt_filtering)
5469 e1000_transfer_dhcp_info(adapter, skb);
5470
e921eb1a 5471 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5472 * head, otherwise try next time
5473 */
55aa6985 5474 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5475 return NETDEV_TX_BUSY;
bc7f75fa 5476
eab6d18d 5477 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5478 tx_flags |= E1000_TX_FLAGS_VLAN;
5479 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5480 }
5481
5482 first = tx_ring->next_to_use;
5483
55aa6985 5484 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5485 if (tso < 0) {
5486 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5487 return NETDEV_TX_OK;
5488 }
5489
5490 if (tso)
5491 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5492 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5493 tx_flags |= E1000_TX_FLAGS_CSUM;
5494
e921eb1a 5495 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5496 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5497 * no longer assume, we must.
5498 */
bc7f75fa
AK		 5499 if (skb->protocol == htons(ETH_P_IP))
5500 tx_flags |= E1000_TX_FLAGS_IPV4;
5501
943146de
BG		 5502 if (unlikely(skb->no_fcs))
5503 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5504
25985edc 5505 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5506 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5507 nr_frags);
1b7719c4 5508 if (count) {
b67e1913
BA		 5509 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5510 !adapter->tx_hwtstamp_skb)) {
5511 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5512 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5513 adapter->tx_hwtstamp_skb = skb_get(skb);
5514 schedule_work(&adapter->tx_hwtstamp_work);
5515 } else {
5516 skb_tx_timestamp(skb);
5517 }
80be3129 5518
3f0cfa3b 5519 netdev_sent_queue(netdev, skb->len);
55aa6985 5520 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5521 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5522 e1000_maybe_stop_tx(tx_ring,
5523 (MAX_SKB_FRAGS *
5524 DIV_ROUND_UP(PAGE_SIZE,
5525 adapter->tx_fifo_limit) + 2));
1b7719c4 5526 } else {
bc7f75fa 5527 dev_kfree_skb_any(skb);
1b7719c4
AD		 5528 tx_ring->buffer_info[first].time_stamp = 0;
5529 tx_ring->next_to_use = first;
bc7f75fa
AK		 5530 }
5531
bc7f75fa
AK		 5532 return NETDEV_TX_OK;
5533}
5534
5535/**
5536 * e1000_tx_timeout - Respond to a Tx Hang
5537 * @netdev: network interface device structure
5538 **/
5539static void e1000_tx_timeout(struct net_device *netdev)
5540{
5541 struct e1000_adapter *adapter = netdev_priv(netdev);
5542
5543 /* Do the reset outside of interrupt context */
5544 adapter->tx_timeout_count++;
5545 schedule_work(&adapter->reset_task);
5546}
5547
5548static void e1000_reset_task(struct work_struct *work)
5549{
5550 struct e1000_adapter *adapter;
5551 adapter = container_of(work, struct e1000_adapter, reset_task);
5552
615b32af
JB		 5553 /* don't run the task if already down */
5554 if (test_bit(__E1000_DOWN, &adapter->state))
5555 return;
5556
12d43f7d 5557 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5558 e1000e_dump(adapter);
12d43f7d 5559 e_err("Reset adapter unexpectedly\n");
affa9dfb 5560 }
bc7f75fa
AK		 5561 e1000e_reinit_locked(adapter);
5562}
5563
5564/**
67fd4fcb 5565 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5566 * @netdev: network interface device structure
67fd4fcb 5567 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5568 *
5569 * Returns the address of the device statistics structure.
bc7f75fa 5570 **/
67fd4fcb
JK		 5571struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5572 struct rtnl_link_stats64 *stats)
bc7f75fa 5573{
67fd4fcb
JK		 5574 struct e1000_adapter *adapter = netdev_priv(netdev);
5575
5576 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5577 spin_lock(&adapter->stats64_lock);
5578 e1000e_update_stats(adapter);
5579 /* Fill out the OS statistics structure */
5580 stats->rx_bytes = adapter->stats.gorc;
5581 stats->rx_packets = adapter->stats.gprc;
5582 stats->tx_bytes = adapter->stats.gotc;
5583 stats->tx_packets = adapter->stats.gptc;
5584 stats->multicast = adapter->stats.mprc;
5585 stats->collisions = adapter->stats.colc;
5586
5587 /* Rx Errors */
5588
e921eb1a 5589 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5590 * our own version based on RUC and ROC
5591 */
5592 stats->rx_errors = adapter->stats.rxerrc +
5593 adapter->stats.crcerrs + adapter->stats.algnerrc +
5594 adapter->stats.ruc + adapter->stats.roc +
5595 adapter->stats.cexterr;
5596 stats->rx_length_errors = adapter->stats.ruc +
5597 adapter->stats.roc;
5598 stats->rx_crc_errors = adapter->stats.crcerrs;
5599 stats->rx_frame_errors = adapter->stats.algnerrc;
5600 stats->rx_missed_errors = adapter->stats.mpc;
5601
5602 /* Tx Errors */
5603 stats->tx_errors = adapter->stats.ecol +
5604 adapter->stats.latecol;
5605 stats->tx_aborted_errors = adapter->stats.ecol;
5606 stats->tx_window_errors = adapter->stats.latecol;
5607 stats->tx_carrier_errors = adapter->stats.tncrs;
5608
5609 /* Tx Dropped needs to be maintained elsewhere */
5610
5611 spin_unlock(&adapter->stats64_lock);
5612 return stats;
bc7f75fa
AK		 5613}
5614
5615/**
5616 * e1000_change_mtu - Change the Maximum Transfer Unit
5617 * @netdev: network interface device structure
5618 * @new_mtu: new value for maximum frame size
5619 *
5620 * Returns 0 on success, negative on failure
5621 **/
5622static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5623{
5624 struct e1000_adapter *adapter = netdev_priv(netdev);
5625 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5626
2adc55c9 5627 /* Jumbo frame support */
2e1706f2
BA		 5628 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5629 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5630 e_err("Jumbo Frames not supported.\n");
5631 return -EINVAL;
bc7f75fa
AK		 5632 }
5633
2adc55c9
BA		 5634 /* Supported frame sizes */
5635 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5636 (max_frame > adapter->max_hw_frame_size)) {
5637 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5638 return -EINVAL;
5639 }
5640
2fbe4526
BA		 5641 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5642 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5643 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5644 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5645 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5646 return -EINVAL;
5647 }
5648
bc7f75fa 5649 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5650 usleep_range(1000, 2000);
610c9928 5651 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5652 adapter->max_frame_size = max_frame;
610c9928
BA		 5653 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5654 netdev->mtu = new_mtu;
bc7f75fa
AK		 5655 if (netif_running(netdev))
5656 e1000e_down(adapter);
5657
e921eb1a 5658 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5659 * means we reserve 2 more, this pushes us to allocate from the next
5660 * larger slab size.
ad68076e 5661 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5662 * However with the new *_jumbo_rx* routines, jumbo receives will use
5663 * fragmented skbs
ad68076e 5664 */
bc7f75fa 5665
9926146b 5666 if (max_frame <= 2048)
bc7f75fa
AK		 5667 adapter->rx_buffer_len = 2048;
5668 else
5669 adapter->rx_buffer_len = 4096;
5670
5671 /* adjust allocation if LPE protects us, and we aren't using SBP */
5672 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5673 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5674 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5675 + ETH_FCS_LEN;
bc7f75fa 5676
bc7f75fa
AK		 5677 if (netif_running(netdev))
5678 e1000e_up(adapter);
5679 else
5680 e1000e_reset(adapter);
5681
5682 clear_bit(__E1000_RESETTING, &adapter->state);
5683
5684 return 0;
5685}
5686
5687static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5688 int cmd)
5689{
5690 struct e1000_adapter *adapter = netdev_priv(netdev);
5691 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5692
318a94d6 5693 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5694 return -EOPNOTSUPP;
5695
5696 switch (cmd) {
5697 case SIOCGMIIPHY:
5698 data->phy_id = adapter->hw.phy.addr;
5699 break;
5700 case SIOCGMIIREG:
b16a002e
BA		 5701 e1000_phy_read_status(adapter);
5702
7c25769f
BA		 5703 switch (data->reg_num & 0x1F) {
5704 case MII_BMCR:
5705 data->val_out = adapter->phy_regs.bmcr;
5706 break;
5707 case MII_BMSR:
5708 data->val_out = adapter->phy_regs.bmsr;
5709 break;
5710 case MII_PHYSID1:
5711 data->val_out = (adapter->hw.phy.id >> 16);
5712 break;
5713 case MII_PHYSID2:
5714 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5715 break;
5716 case MII_ADVERTISE:
5717 data->val_out = adapter->phy_regs.advertise;
5718 break;
5719 case MII_LPA:
5720 data->val_out = adapter->phy_regs.lpa;
5721 break;
5722 case MII_EXPANSION:
5723 data->val_out = adapter->phy_regs.expansion;
5724 break;
5725 case MII_CTRL1000:
5726 data->val_out = adapter->phy_regs.ctrl1000;
5727 break;
5728 case MII_STAT1000:
5729 data->val_out = adapter->phy_regs.stat1000;
5730 break;
5731 case MII_ESTATUS:
5732 data->val_out = adapter->phy_regs.estatus;
5733 break;
5734 default:
bc7f75fa
AK		 5735 return -EIO;
5736 }
bc7f75fa
AK		 5737 break;
5738 case SIOCSMIIREG:
5739 default:
5740 return -EOPNOTSUPP;
5741 }
5742 return 0;
5743}
5744
b67e1913
BA		 5745/**
5746 * e1000e_hwtstamp_ioctl - control hardware time stamping
5747 * @netdev: network interface device structure
5748 * @ifreq: interface request
5749 *
5750 * Outgoing time stamping can be enabled and disabled. Play nice and
5751 * disable it when requested, although it shouldn't cause any overhead
5752 * when no packet needs it. At most one packet in the queue may be
5753 * marked for time stamping, otherwise it would be impossible to tell
5754 * for sure to which packet the hardware time stamp belongs.
5755 *
5756 * Incoming time stamping has to be configured via the hardware filters.
5757 * Not all combinations are supported, in particular event type has to be
5758 * specified. Matching the kind of event packet is not supported, with the
5759 * exception of "all V2 events regardless of level 2 or 4".
5760 **/
5761static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5762{
5763 struct e1000_adapter *adapter = netdev_priv(netdev);
5764 struct hwtstamp_config config;
5765 int ret_val;
5766
5767 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5768 return -EFAULT;
5769
5770 adapter->hwtstamp_config = config;
5771
5772 ret_val = e1000e_config_hwtstamp(adapter);
5773 if (ret_val)
5774 return ret_val;
5775
5776 config = adapter->hwtstamp_config;
5777
d89777bf
BA		 5778 switch (config.rx_filter) {
5779 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5780 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5781 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5782 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5783 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5784 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5785 /* With V2 type filters which specify a Sync or Delay Request,
5786 * Path Delay Request/Response messages are also time stamped
5787 * by hardware so notify the caller the requested packets plus
5788 * some others are time stamped.
5789 */
5790 config.rx_filter = HWTSTAMP_FILTER_SOME;
5791 break;
5792 default:
5793 break;
5794 }
5795
b67e1913
BA		 5796 return copy_to_user(ifr->ifr_data, &config,
5797 sizeof(config)) ? -EFAULT : 0;
5798}
5799
bc7f75fa
AK		 5800static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5801{
5802 switch (cmd) {
5803 case SIOCGMIIPHY:
5804 case SIOCGMIIREG:
5805 case SIOCSMIIREG:
5806 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5807 case SIOCSHWTSTAMP:
5808 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5809 default:
5810 return -EOPNOTSUPP;
5811 }
5812}
5813
a4f58f54
BA		 5814static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5815{
5816 struct e1000_hw *hw = &adapter->hw;
5817 u32 i, mac_reg;
2b6b168d 5818 u16 phy_reg, wuc_enable;
70806a7f 5819 int retval;
a4f58f54
BA		 5820
5821 /* copy MAC RARs to PHY RARs */
d3738bb8 5822 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5823
2b6b168d
BA		 5824 retval = hw->phy.ops.acquire(hw);
5825 if (retval) {
5826 e_err("Could not acquire PHY\n");
5827 return retval;
5828 }
5829
5830 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5831 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5832 if (retval)
75ce1532 5833 goto release;
2b6b168d
BA		 5834
5835 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5836 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5837 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5838 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5839 (u16)(mac_reg & 0xFFFF));
5840 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5841 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5842 }
5843
5844 /* configure PHY Rx Control register */
2b6b168d 5845 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5846 mac_reg = er32(RCTL);
5847 if (mac_reg & E1000_RCTL_UPE)
5848 phy_reg |= BM_RCTL_UPE;
5849 if (mac_reg & E1000_RCTL_MPE)
5850 phy_reg |= BM_RCTL_MPE;
5851 phy_reg &= ~(BM_RCTL_MO_MASK);
5852 if (mac_reg & E1000_RCTL_MO_3)
5853 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5854 << BM_RCTL_MO_SHIFT);
5855 if (mac_reg & E1000_RCTL_BAM)
5856 phy_reg |= BM_RCTL_BAM;
5857 if (mac_reg & E1000_RCTL_PMCF)
5858 phy_reg |= BM_RCTL_PMCF;
5859 mac_reg = er32(CTRL);
5860 if (mac_reg & E1000_CTRL_RFCE)
5861 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5862 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5863
5864 /* enable PHY wakeup in MAC register */
5865 ew32(WUFC, wufc);
5866 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5867
5868 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5869 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5870 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5871
5872 /* activate PHY wakeup */
2b6b168d
BA		 5873 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5874 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5875 if (retval)
5876 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5877release:
94d8186a 5878 hw->phy.ops.release(hw);
a4f58f54
BA		 5879
5880 return retval;
5881}
5882
23606cf5
RW		 5883static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5884 bool runtime)
bc7f75fa
AK		 5885{
5886 struct net_device *netdev = pci_get_drvdata(pdev);
5887 struct e1000_adapter *adapter = netdev_priv(netdev);
5888 struct e1000_hw *hw = &adapter->hw;
5889 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5890 /* Runtime suspend should only enable wakeup for link changes */
5891 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5892 int retval = 0;
5893
5894 netif_device_detach(netdev);
5895
5896 if (netif_running(netdev)) {
bb9e44d0
BA		 5897 int count = E1000_CHECK_RESET_COUNT;
5898
5899 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5900 usleep_range(10000, 20000);
5901
bc7f75fa
AK		 5902 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5903 e1000e_down(adapter);
5904 e1000_free_irq(adapter);
5905 }
4662e82b 5906 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5907
5908 retval = pci_save_state(pdev);
5909 if (retval)
5910 return retval;
5911
5912 status = er32(STATUS);
5913 if (status & E1000_STATUS_LU)
5914 wufc &= ~E1000_WUFC_LNKC;
5915
5916 if (wufc) {
5917 e1000_setup_rctl(adapter);
ef9b965a 5918 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5919
5920 /* turn on all-multi mode if wake on multicast is enabled */
5921 if (wufc & E1000_WUFC_MC) {
5922 rctl = er32(RCTL);
5923 rctl |= E1000_RCTL_MPE;
5924 ew32(RCTL, rctl);
5925 }
5926
5927 ctrl = er32(CTRL);
5928 /* advertise wake from D3Cold */
5929 #define E1000_CTRL_ADVD3WUC 0x00100000
5930 /* phy power management enable */
5931 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5932 ctrl |= E1000_CTRL_ADVD3WUC;
5933 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5934 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5935 ew32(CTRL, ctrl);
5936
318a94d6
JK		 5937 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5938 adapter->hw.phy.media_type ==
5939 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5940 /* keep the laser running in D3 */
5941 ctrl_ext = er32(CTRL_EXT);
93a23f48 5942 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5943 ew32(CTRL_EXT, ctrl_ext);
5944 }
5945
97ac8cae 5946 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5947 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5948
bc7f75fa
AK		 5949 /* Allow time for pending master requests to run */
5950 e1000e_disable_pcie_master(&adapter->hw);
5951
82776a4b 5952 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5953 /* enable wakeup by the PHY */
5954 retval = e1000_init_phy_wakeup(adapter, wufc);
5955 if (retval)
5956 return retval;
5957 } else {
5958 /* enable wakeup by the MAC */
5959 ew32(WUFC, wufc);
5960 ew32(WUC, E1000_WUC_PME_EN);
5961 }
bc7f75fa
AK		 5962 } else {
5963 ew32(WUC, 0);
5964 ew32(WUFC, 0);
bc7f75fa
AK		 5965 }
5966
4f9de721
RW		 5967 *enable_wake = !!wufc;
5968
bc7f75fa 5969 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5970 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5971 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5972 *enable_wake = true;
bc7f75fa
AK		 5973
5974 if (adapter->hw.phy.type == e1000_phy_igp_3)
5975 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5976
e921eb1a 5977 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5978 * would have already happened in close and is redundant.
5979 */
31dbe5b4 5980 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5981
5982 pci_disable_device(pdev);
5983
4f9de721
RW		 5984 return 0;
5985}
5986
5987static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5988{
5989 if (sleep && wake) {
5990 pci_prepare_to_sleep(pdev);
5991 return;
5992 }
5993
5994 pci_wake_from_d3(pdev, wake);
5995 pci_set_power_state(pdev, PCI_D3hot);
5996}
5997
5998static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5999 bool wake)
6000{
6001 struct net_device *netdev = pci_get_drvdata(pdev);
6002 struct e1000_adapter *adapter = netdev_priv(netdev);
6003
e921eb1a 6004 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6005 * correctable error when the MAC transitions from D0 to D3. To
6006 * prevent this we need to mask off the correctable errors on the
6007 * downstream port of the pci-e switch.
6008 */
6009 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6010 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6011 u16 devctl;
6012
f8c0fcac
JL		 6013 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6014 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6015 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6016
4f9de721 6017 e1000_power_off(pdev, sleep, wake);
005cbdfc 6018
f8c0fcac 6019 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6020 } else {
4f9de721 6021 e1000_power_off(pdev, sleep, wake);
005cbdfc 6022 }
bc7f75fa
AK		 6023}
6024
6f461f6c
BA		 6025#ifdef CONFIG_PCIEASPM
6026static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6027{
9f728f53 6028 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 6029}
6030#else
6031static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 6032{
ffe0b2ff
BH		 6033 u16 aspm_ctl = 0;
6034
6035 if (state & PCIE_LINK_STATE_L0S)
6036 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
6037 if (state & PCIE_LINK_STATE_L1)
6038 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
6039
e921eb1a 6040 /* Both device and parent should have the same ASPM setting.
6f461f6c 6041 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6042 */
ffe0b2ff 6043 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 6044
f8c0fcac
JL		 6045 if (pdev->bus->self)
6046 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 6047 aspm_ctl);
6f461f6c
BA		 6048}
6049#endif
78cd29d5 6050static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 6051{
6052 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6053 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
6054 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
6055
6056 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 6057}
6058
aa338601 6059#ifdef CONFIG_PM
23606cf5 6060static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 6061{
23606cf5 6062 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 6063}
6064
23606cf5 6065static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6066{
6067 struct net_device *netdev = pci_get_drvdata(pdev);
6068 struct e1000_adapter *adapter = netdev_priv(netdev);
6069 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6070 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6071 u32 err;
6072
78cd29d5
BA		 6073 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6074 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6075 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6076 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6077 if (aspm_disable_flag)
6078 e1000e_disable_aspm(pdev, aspm_disable_flag);
6079
bc7f75fa
AK		 6080 pci_set_power_state(pdev, PCI_D0);
6081 pci_restore_state(pdev);
28b8f04a 6082 pci_save_state(pdev);
6e4f6f6b 6083
4662e82b 6084 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 6085 if (netif_running(netdev)) {
6086 err = e1000_request_irq(adapter);
6087 if (err)
6088 return err;
6089 }
6090
2fbe4526 6091 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6092 e1000_resume_workarounds_pchlan(&adapter->hw);
6093
bc7f75fa 6094 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6095
6096 /* report the system wakeup cause from S3/S4 */
6097 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6098 u16 phy_data;
6099
6100 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6101 if (phy_data) {
6102 e_info("PHY Wakeup cause - %s\n",
6103 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6104 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6105 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6106 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 6107 phy_data & E1000_WUS_LNKC ?
6108 "Link Status Change" : "other");
a4f58f54
BA		 6109 }
6110 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6111 } else {
6112 u32 wus = er32(WUS);
6113 if (wus) {
6114 e_info("MAC Wakeup cause - %s\n",
6115 wus & E1000_WUS_EX ? "Unicast Packet" :
6116 wus & E1000_WUS_MC ? "Multicast Packet" :
6117 wus & E1000_WUS_BC ? "Broadcast Packet" :
6118 wus & E1000_WUS_MAG ? "Magic Packet" :
6119 wus & E1000_WUS_LNKC ? "Link Status Change" :
6120 "other");
6121 }
6122 ew32(WUS, ~0);
6123 }
6124
bc7f75fa 6125 e1000e_reset(adapter);
bc7f75fa 6126
cd791618 6127 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6128
6129 if (netif_running(netdev))
6130 e1000e_up(adapter);
6131
6132 netif_device_attach(netdev);
6133
e921eb1a 6134 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6135 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6136 * under the control of the driver.
6137 */
c43bc57e 6138 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6139 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6140
6141 return 0;
6142}
23606cf5 6143
a0340162
RW		 6144#ifdef CONFIG_PM_SLEEP
6145static int e1000_suspend(struct device *dev)
6146{
6147 struct pci_dev *pdev = to_pci_dev(dev);
6148 int retval;
6149 bool wake;
6150
6151 retval = __e1000_shutdown(pdev, &wake, false);
6152 if (!retval)
6153 e1000_complete_shutdown(pdev, true, wake);
6154
6155 return retval;
6156}
6157
23606cf5
RW		 6158static int e1000_resume(struct device *dev)
6159{
6160 struct pci_dev *pdev = to_pci_dev(dev);
6161 struct net_device *netdev = pci_get_drvdata(pdev);
6162 struct e1000_adapter *adapter = netdev_priv(netdev);
6163
6164 if (e1000e_pm_ready(adapter))
6165 adapter->idle_check = true;
6166
6167 return __e1000_resume(pdev);
6168}
a0340162
RW		 6169#endif /* CONFIG_PM_SLEEP */
6170
6171#ifdef CONFIG_PM_RUNTIME
6172static int e1000_runtime_suspend(struct device *dev)
6173{
6174 struct pci_dev *pdev = to_pci_dev(dev);
6175 struct net_device *netdev = pci_get_drvdata(pdev);
6176 struct e1000_adapter *adapter = netdev_priv(netdev);
6177
6178 if (e1000e_pm_ready(adapter)) {
6179 bool wake;
6180
6181 __e1000_shutdown(pdev, &wake, true);
6182 }
6183
6184 return 0;
6185}
6186
6187static int e1000_idle(struct device *dev)
6188{
6189 struct pci_dev *pdev = to_pci_dev(dev);
6190 struct net_device *netdev = pci_get_drvdata(pdev);
6191 struct e1000_adapter *adapter = netdev_priv(netdev);
6192
6193 if (!e1000e_pm_ready(adapter))
6194 return 0;
6195
6196 if (adapter->idle_check) {
6197 adapter->idle_check = false;
6198 if (!e1000e_has_link(adapter))
6199 pm_schedule_suspend(dev, MSEC_PER_SEC);
6200 }
6201
6202 return -EBUSY;
6203}
23606cf5
RW		 6204
6205static int e1000_runtime_resume(struct device *dev)
6206{
6207 struct pci_dev *pdev = to_pci_dev(dev);
6208 struct net_device *netdev = pci_get_drvdata(pdev);
6209 struct e1000_adapter *adapter = netdev_priv(netdev);
6210
6211 if (!e1000e_pm_ready(adapter))
6212 return 0;
6213
6214 adapter->idle_check = !dev->power.runtime_auto;
6215 return __e1000_resume(pdev);
6216}
a0340162 6217#endif /* CONFIG_PM_RUNTIME */
aa338601 6218#endif /* CONFIG_PM */
bc7f75fa
AK		 6219
6220static void e1000_shutdown(struct pci_dev *pdev)
6221{
4f9de721
RW		 6222 bool wake = false;
6223
23606cf5 6224 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 6225
6226 if (system_state == SYSTEM_POWER_OFF)
6227 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 6228}
6229
6230#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6231
8bb62869 6232static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6233{
6234 struct net_device *netdev = data;
6235 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6236
6237 if (adapter->msix_entries) {
90da0669
BA		 6238 int vector, msix_irq;
6239
147b2c8c
DD		 6240 vector = 0;
6241 msix_irq = adapter->msix_entries[vector].vector;
6242 disable_irq(msix_irq);
6243 e1000_intr_msix_rx(msix_irq, netdev);
6244 enable_irq(msix_irq);
6245
6246 vector++;
6247 msix_irq = adapter->msix_entries[vector].vector;
6248 disable_irq(msix_irq);
6249 e1000_intr_msix_tx(msix_irq, netdev);
6250 enable_irq(msix_irq);
6251
6252 vector++;
6253 msix_irq = adapter->msix_entries[vector].vector;
6254 disable_irq(msix_irq);
6255 e1000_msix_other(msix_irq, netdev);
6256 enable_irq(msix_irq);
6257 }
6258
6259 return IRQ_HANDLED;
6260}
6261
e921eb1a
BA		 6262/**
6263 * e1000_netpoll
6264 * @netdev: network interface device structure
6265 *
bc7f75fa
AK		 6266 * Polling 'interrupt' - used by things like netconsole to send skbs
6267 * without having to re-enable interrupts. It's not called while
6268 * the interrupt routine is executing.
6269 */
6270static void e1000_netpoll(struct net_device *netdev)
6271{
6272 struct e1000_adapter *adapter = netdev_priv(netdev);
6273
147b2c8c
DD		 6274 switch (adapter->int_mode) {
6275 case E1000E_INT_MODE_MSIX:
6276 e1000_intr_msix(adapter->pdev->irq, netdev);
6277 break;
6278 case E1000E_INT_MODE_MSI:
6279 disable_irq(adapter->pdev->irq);
6280 e1000_intr_msi(adapter->pdev->irq, netdev);
6281 enable_irq(adapter->pdev->irq);
6282 break;
6283 default: /* E1000E_INT_MODE_LEGACY */
6284 disable_irq(adapter->pdev->irq);
6285 e1000_intr(adapter->pdev->irq, netdev);
6286 enable_irq(adapter->pdev->irq);
6287 break;
6288 }
bc7f75fa
AK		 6289}
6290#endif
6291
6292/**
6293 * e1000_io_error_detected - called when PCI error is detected
6294 * @pdev: Pointer to PCI device
6295 * @state: The current pci connection state
6296 *
6297 * This function is called after a PCI bus error affecting
6298 * this device has been detected.
6299 */
6300static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6301 pci_channel_state_t state)
6302{
6303 struct net_device *netdev = pci_get_drvdata(pdev);
6304 struct e1000_adapter *adapter = netdev_priv(netdev);
6305
6306 netif_device_detach(netdev);
6307
c93b5a76
MM		 6308 if (state == pci_channel_io_perm_failure)
6309 return PCI_ERS_RESULT_DISCONNECT;
6310
bc7f75fa
AK		 6311 if (netif_running(netdev))
6312 e1000e_down(adapter);
6313 pci_disable_device(pdev);
6314
6315 /* Request a slot slot reset. */
6316 return PCI_ERS_RESULT_NEED_RESET;
6317}
6318
6319/**
6320 * e1000_io_slot_reset - called after the pci bus has been reset.
6321 * @pdev: Pointer to PCI device
6322 *
6323 * Restart the card from scratch, as if from a cold-boot. Implementation
6324 * resembles the first-half of the e1000_resume routine.
6325 */
6326static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6327{
6328 struct net_device *netdev = pci_get_drvdata(pdev);
6329 struct e1000_adapter *adapter = netdev_priv(netdev);
6330 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6331 u16 aspm_disable_flag = 0;
6e4f6f6b 6332 int err;
111b9dc5 6333 pci_ers_result_t result;
bc7f75fa 6334
78cd29d5
BA		 6335 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6336 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6337 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6338 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6339 if (aspm_disable_flag)
6340 e1000e_disable_aspm(pdev, aspm_disable_flag);
6341
f0f422e5 6342 err = pci_enable_device_mem(pdev);
6e4f6f6b 6343 if (err) {
bc7f75fa
AK		 6344 dev_err(&pdev->dev,
6345 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6346 result = PCI_ERS_RESULT_DISCONNECT;
6347 } else {
6348 pci_set_master(pdev);
23606cf5 6349 pdev->state_saved = true;
111b9dc5 6350 pci_restore_state(pdev);
bc7f75fa 6351
111b9dc5
JB		 6352 pci_enable_wake(pdev, PCI_D3hot, 0);
6353 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6354
111b9dc5
JB		 6355 e1000e_reset(adapter);
6356 ew32(WUS, ~0);
6357 result = PCI_ERS_RESULT_RECOVERED;
6358 }
bc7f75fa 6359
111b9dc5
JB		 6360 pci_cleanup_aer_uncorrect_error_status(pdev);
6361
6362 return result;
bc7f75fa
AK		 6363}
6364
6365/**
6366 * e1000_io_resume - called when traffic can start flowing again.
6367 * @pdev: Pointer to PCI device
6368 *
6369 * This callback is called when the error recovery driver tells us that
6370 * its OK to resume normal operation. Implementation resembles the
6371 * second-half of the e1000_resume routine.
6372 */
6373static void e1000_io_resume(struct pci_dev *pdev)
6374{
6375 struct net_device *netdev = pci_get_drvdata(pdev);
6376 struct e1000_adapter *adapter = netdev_priv(netdev);
6377
cd791618 6378 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6379
6380 if (netif_running(netdev)) {
6381 if (e1000e_up(adapter)) {
6382 dev_err(&pdev->dev,
6383 "can't bring device back up after reset\n");
6384 return;
6385 }
6386 }
6387
6388 netif_device_attach(netdev);
6389
e921eb1a 6390 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6391 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6392 * under the control of the driver.
6393 */
c43bc57e 6394 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6395 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6396}
6397
6398static void e1000_print_device_info(struct e1000_adapter *adapter)
6399{
6400 struct e1000_hw *hw = &adapter->hw;
6401 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6402 u32 ret_val;
6403 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6404
6405 /* print bus type/speed/width info */
a5cc7642 6406 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6407 /* bus width */
6408 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6409 "Width x1"),
6410 /* MAC address */
7c510e4b 6411 netdev->dev_addr);
44defeb3
JK		 6412 e_info("Intel(R) PRO/%s Network Connection\n",
6413 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6414 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6415 E1000_PBANUM_LENGTH);
6416 if (ret_val)
f2315bf1 6417 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6418 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6419 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6420}
6421
10aa4c04
AK		 6422static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6423{
6424 struct e1000_hw *hw = &adapter->hw;
6425 int ret_val;
6426 u16 buf = 0;
6427
6428 if (hw->mac.type != e1000_82573)
6429 return;
6430
6431 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6432 le16_to_cpus(&buf);
6433 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6434 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6435 dev_warn(&adapter->pdev->dev,
6436 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6437 }
10aa4c04
AK		 6438}
6439
c8f44aff 6440static int e1000_set_features(struct net_device *netdev,
70495a50 6441 netdev_features_t features)
dc221294
BA		 6442{
6443 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6444 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6445
6446 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6447 adapter->flags |= FLAG_TSO_FORCE;
6448
6449 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6450 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6451 NETIF_F_RXALL)))
dc221294
BA		 6452 return 0;
6453
0184039a
BG		 6454 if (changed & NETIF_F_RXFCS) {
6455 if (features & NETIF_F_RXFCS) {
6456 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6457 } else {
6458 /* We need to take it back to defaults, which might mean
6459 * stripping is still disabled at the adapter level.
6460 */
6461 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6462 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6463 else
6464 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6465 }
6466 }
6467
70495a50
BA		 6468 netdev->features = features;
6469
dc221294
BA		 6470 if (netif_running(netdev))
6471 e1000e_reinit_locked(adapter);
6472 else
6473 e1000e_reset(adapter);
6474
6475 return 0;
6476}
6477
651c2466
SH		 6478static const struct net_device_ops e1000e_netdev_ops = {
6479 .ndo_open = e1000_open,
6480 .ndo_stop = e1000_close,
00829823 6481 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6482 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6483 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6484 .ndo_set_mac_address = e1000_set_mac,
6485 .ndo_change_mtu = e1000_change_mtu,
6486 .ndo_do_ioctl = e1000_ioctl,
6487 .ndo_tx_timeout = e1000_tx_timeout,
6488 .ndo_validate_addr = eth_validate_addr,
6489
651c2466
SH		 6490 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6491 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6492#ifdef CONFIG_NET_POLL_CONTROLLER
6493 .ndo_poll_controller = e1000_netpoll,
6494#endif
dc221294 6495 .ndo_set_features = e1000_set_features,
651c2466
SH		 6496};
6497
bc7f75fa
AK		 6498/**
6499 * e1000_probe - Device Initialization Routine
6500 * @pdev: PCI device information struct
6501 * @ent: entry in e1000_pci_tbl
6502 *
6503 * Returns 0 on success, negative on failure
6504 *
6505 * e1000_probe initializes an adapter identified by a pci_dev structure.
6506 * The OS initialization, configuring of the adapter private structure,
6507 * and a hardware reset occur.
6508 **/
1dd06ae8 6509static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6510{
6511 struct net_device *netdev;
6512 struct e1000_adapter *adapter;
6513 struct e1000_hw *hw;
6514 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6515 resource_size_t mmio_start, mmio_len;
6516 resource_size_t flash_start, flash_len;
bc7f75fa 6517 static int cards_found;
78cd29d5 6518 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6519 int i, err, pci_using_dac;
6520 u16 eeprom_data = 0;
6521 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6522
78cd29d5
BA		 6523 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6524 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6525 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6526 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6527 if (aspm_disable_flag)
6528 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6529
f0f422e5 6530 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6531 if (err)
6532 return err;
6533
6534 pci_using_dac = 0;
0be3f55f 6535 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6536 if (!err) {
0be3f55f 6537 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6538 if (!err)
6539 pci_using_dac = 1;
6540 } else {
0be3f55f 6541 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6542 if (err) {
0be3f55f
NN		 6543 err = dma_set_coherent_mask(&pdev->dev,
6544 DMA_BIT_MASK(32));
bc7f75fa 6545 if (err) {
ef456f85 6546 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6547 goto err_dma;
6548 }
6549 }
6550 }
6551
e8de1481 6552 err = pci_request_selected_regions_exclusive(pdev,
55c5f55e
BA		 6553 pci_select_bars(pdev, IORESOURCE_MEM),
6554 e1000e_driver_name);
bc7f75fa
AK		 6555 if (err)
6556 goto err_pci_reg;
6557
68eac460 6558 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6559 pci_enable_pcie_error_reporting(pdev);
68eac460 6560
bc7f75fa 6561 pci_set_master(pdev);
438b365a
BA		 6562 /* PCI config space info */
6563 err = pci_save_state(pdev);
6564 if (err)
6565 goto err_alloc_etherdev;
bc7f75fa
AK		 6566
6567 err = -ENOMEM;
6568 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6569 if (!netdev)
6570 goto err_alloc_etherdev;
6571
bc7f75fa
AK		 6572 SET_NETDEV_DEV(netdev, &pdev->dev);
6573
f85e4dfa
TH		 6574 netdev->irq = pdev->irq;
6575
bc7f75fa
AK		 6576 pci_set_drvdata(pdev, netdev);
6577 adapter = netdev_priv(netdev);
6578 hw = &adapter->hw;
6579 adapter->netdev = netdev;
6580 adapter->pdev = pdev;
6581 adapter->ei = ei;
6582 adapter->pba = ei->pba;
6583 adapter->flags = ei->flags;
eb7c3adb 6584 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6585 adapter->hw.adapter = adapter;
6586 adapter->hw.mac.type = ei->mac;
2adc55c9 6587 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6588 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6589
6590 mmio_start = pci_resource_start(pdev, 0);
6591 mmio_len = pci_resource_len(pdev, 0);
6592
6593 err = -EIO;
6594 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6595 if (!adapter->hw.hw_addr)
6596 goto err_ioremap;
6597
6598 if ((adapter->flags & FLAG_HAS_FLASH) &&
6599 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6600 flash_start = pci_resource_start(pdev, 1);
6601 flash_len = pci_resource_len(pdev, 1);
6602 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6603 if (!adapter->hw.flash_address)
6604 goto err_flashmap;
6605 }
6606
6607 /* construct the net_device struct */
651c2466 6608 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6609 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6610 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6611 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6612 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6613
6614 netdev->mem_start = mmio_start;
6615 netdev->mem_end = mmio_start + mmio_len;
6616
6617 adapter->bd_number = cards_found++;
6618
4662e82b
BA		 6619 e1000e_check_options(adapter);
6620
bc7f75fa
AK		 6621 /* setup adapter struct */
6622 err = e1000_sw_init(adapter);
6623 if (err)
6624 goto err_sw_init;
6625
bc7f75fa
AK		 6626 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6627 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6628 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6629
69e3fd8c 6630 err = ei->get_variants(adapter);
bc7f75fa
AK		 6631 if (err)
6632 goto err_hw_init;
6633
4a770358
BA		 6634 if ((adapter->flags & FLAG_IS_ICH) &&
6635 (adapter->flags & FLAG_READ_ONLY_NVM))
6636 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6637
bc7f75fa
AK		 6638 hw->mac.ops.get_bus_info(&adapter->hw);
6639
318a94d6 6640 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6641
6642 /* Copper options */
318a94d6 6643 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6644 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6645 adapter->hw.phy.disable_polarity_correction = 0;
6646 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6647 }
6648
470a5420 6649 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6650 dev_info(&pdev->dev,
6651 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6652
dc221294
BA		 6653 /* Set initial default active device features */
6654 netdev->features = (NETIF_F_SG |
6655 NETIF_F_HW_VLAN_RX |
6656 NETIF_F_HW_VLAN_TX |
6657 NETIF_F_TSO |
6658 NETIF_F_TSO6 |
70495a50 6659 NETIF_F_RXHASH |
dc221294
BA		 6660 NETIF_F_RXCSUM |
6661 NETIF_F_HW_CSUM);
6662
6663 /* Set user-changeable features (subset of all device features) */
6664 netdev->hw_features = netdev->features;
0184039a 6665 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6666 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6667 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6668
6669 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6670 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6671
dc221294
BA		 6672 netdev->vlan_features |= (NETIF_F_SG |
6673 NETIF_F_TSO |
6674 NETIF_F_TSO6 |
6675 NETIF_F_HW_CSUM);
a5136e23 6676
ef9b965a
JB		 6677 netdev->priv_flags |= IFF_UNICAST_FLT;
6678
7b872a55 6679 if (pci_using_dac) {
bc7f75fa 6680 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6681 netdev->vlan_features |= NETIF_F_HIGHDMA;
6682 }
bc7f75fa 6683
bc7f75fa
AK		 6684 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6685 adapter->flags |= FLAG_MNG_PT_ENABLED;
6686
e921eb1a 6687 /* before reading the NVM, reset the controller to
ad68076e
BA		 6688 * put the device in a known good starting state
6689 */
bc7f75fa
AK		 6690 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6691
e921eb1a 6692 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6693 * attempt. Let's give it a few tries
6694 */
6695 for (i = 0;; i++) {
6696 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6697 break;
6698 if (i == 2) {
185095fb 6699 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6700 err = -EIO;
6701 goto err_eeprom;
6702 }
6703 }
6704
10aa4c04
AK		 6705 e1000_eeprom_checks(adapter);
6706
608f8a0d 6707 /* copy the MAC address */
bc7f75fa 6708 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6709 dev_err(&pdev->dev,
6710 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6711
6712 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6713
aaeb6cdf 6714 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6715 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6716 netdev->dev_addr);
bc7f75fa
AK		 6717 err = -EIO;
6718 goto err_eeprom;
6719 }
6720
6721 init_timer(&adapter->watchdog_timer);
c061b18d 6722 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6723 adapter->watchdog_timer.data = (unsigned long) adapter;
6724
6725 init_timer(&adapter->phy_info_timer);
c061b18d 6726 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6727 adapter->phy_info_timer.data = (unsigned long) adapter;
6728
6729 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6730 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6731 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6732 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6733 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6734
bc7f75fa
AK		 6735 /* Initialize link parameters. User can change them with ethtool */
6736 adapter->hw.mac.autoneg = 1;
3db1cd5c 6737 adapter->fc_autoneg = true;
5c48ef3e
BA		 6738 adapter->hw.fc.requested_mode = e1000_fc_default;
6739 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6740 adapter->hw.phy.autoneg_advertised = 0x2f;
6741
6742 /* ring size defaults */
d821a4c4
BA		 6743 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6744 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6745
e921eb1a 6746 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6747 * the EEPROM, enable the ACPI Magic Packet filter
6748 */
6749 if (adapter->flags & FLAG_APME_IN_WUC) {
6750 /* APME bit in EEPROM is mapped to WUC.APME */
6751 eeprom_data = er32(WUC);
6752 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6753 if ((hw->mac.type > e1000_ich10lan) &&
6754 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6755 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6756 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6757 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6758 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6759 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6760 1, &eeprom_data);
bc7f75fa 6761 else
3d3a1676
BA		 6762 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6763 1, &eeprom_data);
bc7f75fa
AK		 6764 }
6765
6766 /* fetch WoL from EEPROM */
6767 if (eeprom_data & eeprom_apme_mask)
6768 adapter->eeprom_wol |= E1000_WUFC_MAG;
6769
e921eb1a 6770 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6771 * where the eeprom may be wrong or the board simply won't support
6772 * wake on lan on a particular port
6773 */
6774 if (!(adapter->flags & FLAG_HAS_WOL))
6775 adapter->eeprom_wol = 0;
6776
6777 /* initialize the wol settings based on the eeprom settings */
6778 adapter->wol = adapter->eeprom_wol;
6ff68026 6779 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6780
84527590
BA		 6781 /* save off EEPROM version number */
6782 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6783
bc7f75fa
AK		 6784 /* reset the hardware with the new settings */
6785 e1000e_reset(adapter);
6786
e921eb1a 6787 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6788 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6789 * under the control of the driver.
6790 */
c43bc57e 6791 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6792 e1000e_get_hw_control(adapter);
bc7f75fa 6793
f2315bf1 6794 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6795 err = register_netdev(netdev);
6796 if (err)
6797 goto err_register;
6798
9c563d20
JB		 6799 /* carrier off reporting is important to ethtool even BEFORE open */
6800 netif_carrier_off(netdev);
6801
d89777bf
BA		 6802 /* init PTP hardware clock */
6803 e1000e_ptp_init(adapter);
6804
bc7f75fa
AK		 6805 e1000_print_device_info(adapter);
6806
f3ec4f87
AS		 6807 if (pci_dev_run_wake(pdev))
6808 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6809
bc7f75fa
AK		 6810 return 0;
6811
6812err_register:
c43bc57e 6813 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6814 e1000e_release_hw_control(adapter);
bc7f75fa 6815err_eeprom:
470a5420 6816 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6817 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6818err_hw_init:
bc7f75fa
AK		 6819 kfree(adapter->tx_ring);
6820 kfree(adapter->rx_ring);
6821err_sw_init:
c43bc57e
JB		 6822 if (adapter->hw.flash_address)
6823 iounmap(adapter->hw.flash_address);
e82f54ba 6824 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6825err_flashmap:
bc7f75fa
AK		 6826 iounmap(adapter->hw.hw_addr);
6827err_ioremap:
6828 free_netdev(netdev);
6829err_alloc_etherdev:
f0f422e5
BA		 6830 pci_release_selected_regions(pdev,
6831 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6832err_pci_reg:
6833err_dma:
6834 pci_disable_device(pdev);
6835 return err;
6836}
6837
6838/**
6839 * e1000_remove - Device Removal Routine
6840 * @pdev: PCI device information struct
6841 *
6842 * e1000_remove is called by the PCI subsystem to alert the driver
6843 * that it should release a PCI device. The could be caused by a
6844 * Hot-Plug event, or because the driver is going to be removed from
6845 * memory.
6846 **/
9f9a12f8 6847static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6848{
6849 struct net_device *netdev = pci_get_drvdata(pdev);
6850 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6851 bool down = test_bit(__E1000_DOWN, &adapter->state);
6852
d89777bf
BA		 6853 e1000e_ptp_remove(adapter);
6854
e921eb1a 6855 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6856 * from being rescheduled.
ad68076e 6857 */
23606cf5
RW		 6858 if (!down)
6859 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6860 del_timer_sync(&adapter->watchdog_timer);
6861 del_timer_sync(&adapter->phy_info_timer);
6862
41cec6f1
BA		 6863 cancel_work_sync(&adapter->reset_task);
6864 cancel_work_sync(&adapter->watchdog_task);
6865 cancel_work_sync(&adapter->downshift_task);
6866 cancel_work_sync(&adapter->update_phy_task);
6867 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6868
b67e1913
BA		 6869 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6870 cancel_work_sync(&adapter->tx_hwtstamp_work);
6871 if (adapter->tx_hwtstamp_skb) {
6872 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6873 adapter->tx_hwtstamp_skb = NULL;
6874 }
6875 }
6876
17f208de
BA		 6877 if (!(netdev->flags & IFF_UP))
6878 e1000_power_down_phy(adapter);
6879
23606cf5
RW		 6880 /* Don't lie to e1000_close() down the road. */
6881 if (!down)
6882 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6883 unregister_netdev(netdev);
6884
f3ec4f87
AS		 6885 if (pci_dev_run_wake(pdev))
6886 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6887
e921eb1a 6888 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6889 * would have already happened in close and is redundant.
6890 */
31dbe5b4 6891 e1000e_release_hw_control(adapter);
bc7f75fa 6892
4662e82b 6893 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6894 kfree(adapter->tx_ring);
6895 kfree(adapter->rx_ring);
6896
6897 iounmap(adapter->hw.hw_addr);
6898 if (adapter->hw.flash_address)
6899 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6900 pci_release_selected_regions(pdev,
6901 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6902
6903 free_netdev(netdev);
6904
111b9dc5 6905 /* AER disable */
19d5afd4 6906 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6907
bc7f75fa
AK		 6908 pci_disable_device(pdev);
6909}
6910
6911/* PCI Error Recovery (ERS) */
3646f0e5 6912static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6913 .error_detected = e1000_io_error_detected,
6914 .slot_reset = e1000_io_slot_reset,
6915 .resume = e1000_io_resume,
6916};
6917
a3aa1884 6918static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6928
bc7f75fa
AK		 6929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6933
bc7f75fa
AK		 6934 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6935 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6936 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6937
4662e82b 6938 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6939 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6940 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6941
bc7f75fa
AK		 6942 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6943 board_80003es2lan },
6944 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6945 board_80003es2lan },
6946 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6947 board_80003es2lan },
6948 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6949 board_80003es2lan },
ad68076e 6950
bc7f75fa
AK		 6951 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6952 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6953 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6954 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6955 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6956 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6957 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6958 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6959
bc7f75fa
AK		 6960 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6961 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6962 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6963 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6964 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6965 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6966 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6967 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6968 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6969
6970 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6971 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6972 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6973
f4187b56
BA		 6974 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6975 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6976 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6977
a4f58f54
BA		 6978 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6979 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6980 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6981 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6982
d3738bb8
BA		 6983 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6984 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6985
2fbe4526
BA		 6986 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6987 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6988 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6989 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6990
f36bb6ca 6991 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6992};
6993MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6994
aa338601 6995#ifdef CONFIG_PM
23606cf5 6996static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6997 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6998 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6999 e1000_runtime_resume, e1000_idle)
23606cf5 7000};
e50208a0 7001#endif
23606cf5 7002
bc7f75fa
AK		 7003/* PCI Device API Driver */
7004static struct pci_driver e1000_driver = {
7005 .name = e1000e_driver_name,
7006 .id_table = e1000_pci_tbl,
7007 .probe = e1000_probe,
9f9a12f8 7008 .remove = e1000_remove,
aa338601 7009#ifdef CONFIG_PM
f36bb6ca
BA		 7010 .driver = {
7011 .pm = &e1000_pm_ops,
7012 },
bc7f75fa
AK		 7013#endif
7014 .shutdown = e1000_shutdown,
7015 .err_handler = &e1000_err_handler
7016};
7017
7018/**
7019 * e1000_init_module - Driver Registration Routine
7020 *
7021 * e1000_init_module is the first routine called when the driver is
7022 * loaded. All it does is register with the PCI subsystem.
7023 **/
7024static int __init e1000_init_module(void)
7025{
7026 int ret;
8544b9f7
BA		 7027 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7028 e1000e_driver_version);
bf67044b 7029 pr_info("Copyright(c) 1999 - 2013 Intel Corporation.\n");
bc7f75fa 7030 ret = pci_register_driver(&e1000_driver);
53ec5498 7031
bc7f75fa
AK		 7032 return ret;
7033}
7034module_init(e1000_init_module);
7035
7036/**
7037 * e1000_exit_module - Driver Exit Cleanup Routine
7038 *
7039 * e1000_exit_module is called just before the driver is removed
7040 * from memory.
7041 **/
7042static void __exit e1000_exit_module(void)
7043{
7044 pci_unregister_driver(&e1000_driver);
7045}
7046module_exit(e1000_exit_module);
7047
7048
7049MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7050MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7051MODULE_LICENSE("GPL");
7052MODULE_VERSION(DRV_VERSION);
7053
06c24b91 7054/* netdev.c */
Linux kernel - Deliverables
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