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e1000e: fix ethtool offline register test for I217
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
076d8070 59#define DRV_VERSION "2.1.4" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 82 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 83};
84
84f4ee90
TI		 85struct e1000_reg_info {
86 u32 ofs;
87 char *name;
88};
89
af667a29
BA		 90#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
91#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
92#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
93#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
94#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
95
96#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
97#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
98#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
99#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
100#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 101
102static const struct e1000_reg_info e1000_reg_info_tbl[] = {
103
104 /* General Registers */
105 {E1000_CTRL, "CTRL"},
106 {E1000_STATUS, "STATUS"},
107 {E1000_CTRL_EXT, "CTRL_EXT"},
108
109 /* Interrupt Registers */
110 {E1000_ICR, "ICR"},
111
af667a29 112 /* Rx Registers */
84f4ee90 113 {E1000_RCTL, "RCTL"},
1e36052e
BA		 114 {E1000_RDLEN(0), "RDLEN"},
115 {E1000_RDH(0), "RDH"},
116 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 117 {E1000_RDTR, "RDTR"},
118 {E1000_RXDCTL(0), "RXDCTL"},
119 {E1000_ERT, "ERT"},
1e36052e
BA		 120 {E1000_RDBAL(0), "RDBAL"},
121 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 122 {E1000_RDFH, "RDFH"},
123 {E1000_RDFT, "RDFT"},
124 {E1000_RDFHS, "RDFHS"},
125 {E1000_RDFTS, "RDFTS"},
126 {E1000_RDFPC, "RDFPC"},
127
af667a29 128 /* Tx Registers */
84f4ee90 129 {E1000_TCTL, "TCTL"},
1e36052e
BA		 130 {E1000_TDBAL(0), "TDBAL"},
131 {E1000_TDBAH(0), "TDBAH"},
132 {E1000_TDLEN(0), "TDLEN"},
133 {E1000_TDH(0), "TDH"},
134 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 135 {E1000_TIDV, "TIDV"},
136 {E1000_TXDCTL(0), "TXDCTL"},
137 {E1000_TADV, "TADV"},
138 {E1000_TARC(0), "TARC"},
139 {E1000_TDFH, "TDFH"},
140 {E1000_TDFT, "TDFT"},
141 {E1000_TDFHS, "TDFHS"},
142 {E1000_TDFTS, "TDFTS"},
143 {E1000_TDFPC, "TDFPC"},
144
145 /* List Terminator */
f36bb6ca 146 {0, NULL}
84f4ee90
TI		 147};
148
e921eb1a 149/**
84f4ee90 150 * e1000_regdump - register printout routine
e921eb1a
BA		 151 * @hw: pointer to the HW structure
152 * @reginfo: pointer to the register info table
153 **/
84f4ee90
TI		 154static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
155{
156 int n = 0;
157 char rname[16];
158 u32 regs[8];
159
160 switch (reginfo->ofs) {
161 case E1000_RXDCTL(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_RXDCTL(n));
164 break;
165 case E1000_TXDCTL(0):
166 for (n = 0; n < 2; n++)
167 regs[n] = __er32(hw, E1000_TXDCTL(n));
168 break;
169 case E1000_TARC(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_TARC(n));
172 break;
173 default:
ef456f85
JK		 174 pr_info("%-15s %08x\n",
175 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 176 return;
177 }
178
179 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 180 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 181}
182
f0c5dadf
ET		 183static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
184 struct e1000_buffer *bi)
185{
186 int i;
187 struct e1000_ps_page *ps_page;
188
189 for (i = 0; i < adapter->rx_ps_pages; i++) {
190 ps_page = &bi->ps_pages[i];
191
192 if (ps_page->page) {
193 pr_info("packet dump for ps_page %d:\n", i);
194 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
195 16, 1, page_address(ps_page->page),
196 PAGE_SIZE, true);
197 }
198 }
199}
200
e921eb1a 201/**
af667a29 202 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 203 * @adapter: board private structure
204 **/
84f4ee90
TI		 205static void e1000e_dump(struct e1000_adapter *adapter)
206{
207 struct net_device *netdev = adapter->netdev;
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_reg_info *reginfo;
210 struct e1000_ring *tx_ring = adapter->tx_ring;
211 struct e1000_tx_desc *tx_desc;
af667a29 212 struct my_u0 {
e885d762
BA		 213 __le64 a;
214 __le64 b;
af667a29 215 } *u0;
84f4ee90
TI		 216 struct e1000_buffer *buffer_info;
217 struct e1000_ring *rx_ring = adapter->rx_ring;
218 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 219 union e1000_rx_desc_extended *rx_desc;
af667a29 220 struct my_u1 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
223 __le64 c;
224 __le64 d;
af667a29 225 } *u1;
84f4ee90
TI		 226 u32 staterr;
227 int i = 0;
228
229 if (!netif_msg_hw(adapter))
230 return;
231
232 /* Print netdevice Info */
233 if (netdev) {
234 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 235 pr_info("Device Name state trans_start last_rx\n");
236 pr_info("%-15s %016lX %016lX %016lX\n",
237 netdev->name, netdev->state, netdev->trans_start,
238 netdev->last_rx);
84f4ee90
TI		 239 }
240
241 /* Print Registers */
242 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 243 pr_info(" Register Name Value\n");
84f4ee90
TI		 244 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
245 reginfo->name; reginfo++) {
246 e1000_regdump(hw, reginfo);
247 }
248
af667a29 249 /* Print Tx Ring Summary */
84f4ee90 250 if (!netdev || !netif_running(netdev))
fe1e980f 251 return;
84f4ee90 252
af667a29 253 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 254 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 255 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 256 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
257 0, tx_ring->next_to_use, tx_ring->next_to_clean,
258 (unsigned long long)buffer_info->dma,
259 buffer_info->length,
260 buffer_info->next_to_watch,
261 (unsigned long long)buffer_info->time_stamp);
84f4ee90 262
af667a29 263 /* Print Tx Ring */
84f4ee90
TI		 264 if (!netif_msg_tx_done(adapter))
265 goto rx_ring_summary;
266
af667a29 267 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 268
269 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
270 *
271 * Legacy Transmit Descriptor
272 * +--------------------------------------------------------------+
273 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
274 * +--------------------------------------------------------------+
275 * 8 | Special | CSS | Status | CMD | CSO | Length |
276 * +--------------------------------------------------------------+
277 * 63 48 47 36 35 32 31 24 23 16 15 0
278 *
279 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
280 * 63 48 47 40 39 32 31 16 15 8 7 0
281 * +----------------------------------------------------------------+
282 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
283 * +----------------------------------------------------------------+
284 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
285 * +----------------------------------------------------------------+
286 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
287 *
288 * Extended Data Descriptor (DTYP=0x1)
289 * +----------------------------------------------------------------+
290 * 0 | Buffer Address [63:0] |
291 * +----------------------------------------------------------------+
292 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
293 * +----------------------------------------------------------------+
294 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
295 */
ef456f85
JK		 296 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
297 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
298 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 299 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 300 const char *next_desc;
84f4ee90
TI		 301 tx_desc = E1000_TX_DESC(*tx_ring, i);
302 buffer_info = &tx_ring->buffer_info[i];
303 u0 = (struct my_u0 *)tx_desc;
84f4ee90 304 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 305 next_desc = " NTC/U";
84f4ee90 306 else if (i == tx_ring->next_to_use)
ef456f85 307 next_desc = " NTU";
84f4ee90 308 else if (i == tx_ring->next_to_clean)
ef456f85 309 next_desc = " NTC";
84f4ee90 310 else
ef456f85
JK		 311 next_desc = "";
312 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
313 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
314 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
315 i,
316 (unsigned long long)le64_to_cpu(u0->a),
317 (unsigned long long)le64_to_cpu(u0->b),
318 (unsigned long long)buffer_info->dma,
319 buffer_info->length, buffer_info->next_to_watch,
320 (unsigned long long)buffer_info->time_stamp,
321 buffer_info->skb, next_desc);
84f4ee90 322
f0c5dadf 323 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 324 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 325 16, 1, buffer_info->skb->data,
326 buffer_info->skb->len, true);
84f4ee90
TI		 327 }
328
af667a29 329 /* Print Rx Ring Summary */
84f4ee90 330rx_ring_summary:
af667a29 331 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 332 pr_info("Queue [NTU] [NTC]\n");
333 pr_info(" %5d %5X %5X\n",
334 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 335
af667a29 336 /* Print Rx Ring */
84f4ee90 337 if (!netif_msg_rx_status(adapter))
fe1e980f 338 return;
84f4ee90 339
af667a29 340 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 341 switch (adapter->rx_ps_pages) {
342 case 1:
343 case 2:
344 case 3:
345 /* [Extended] Packet Split Receive Descriptor Format
346 *
347 * +-----------------------------------------------------+
348 * 0 | Buffer Address 0 [63:0] |
349 * +-----------------------------------------------------+
350 * 8 | Buffer Address 1 [63:0] |
351 * +-----------------------------------------------------+
352 * 16 | Buffer Address 2 [63:0] |
353 * +-----------------------------------------------------+
354 * 24 | Buffer Address 3 [63:0] |
355 * +-----------------------------------------------------+
356 */
ef456f85 357 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 358 /* [Extended] Receive Descriptor (Write-Back) Format
359 *
360 * 63 48 47 32 31 13 12 8 7 4 3 0
361 * +------------------------------------------------------+
362 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
363 * | Checksum | Ident | | Queue | | Type |
364 * +------------------------------------------------------+
365 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
366 * +------------------------------------------------------+
367 * 63 48 47 32 31 20 19 0
368 */
ef456f85 369 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 370 for (i = 0; i < rx_ring->count; i++) {
ef456f85 371 const char *next_desc;
84f4ee90
TI		 372 buffer_info = &rx_ring->buffer_info[i];
373 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
374 u1 = (struct my_u1 *)rx_desc_ps;
375 staterr =
af667a29 376 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 377
378 if (i == rx_ring->next_to_use)
379 next_desc = " NTU";
380 else if (i == rx_ring->next_to_clean)
381 next_desc = " NTC";
382 else
383 next_desc = "";
384
84f4ee90
TI		 385 if (staterr & E1000_RXD_STAT_DD) {
386 /* Descriptor Done */
ef456f85
JK		 387 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
388 "RWB", i,
389 (unsigned long long)le64_to_cpu(u1->a),
390 (unsigned long long)le64_to_cpu(u1->b),
391 (unsigned long long)le64_to_cpu(u1->c),
392 (unsigned long long)le64_to_cpu(u1->d),
393 buffer_info->skb, next_desc);
84f4ee90 394 } else {
ef456f85
JK		 395 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
396 "R ", i,
397 (unsigned long long)le64_to_cpu(u1->a),
398 (unsigned long long)le64_to_cpu(u1->b),
399 (unsigned long long)le64_to_cpu(u1->c),
400 (unsigned long long)le64_to_cpu(u1->d),
401 (unsigned long long)buffer_info->dma,
402 buffer_info->skb, next_desc);
84f4ee90
TI		 403
404 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 405 e1000e_dump_ps_pages(adapter,
406 buffer_info);
84f4ee90 407 }
84f4ee90
TI		 408 }
409 break;
410 default:
411 case 0:
5f450212 412 /* Extended Receive Descriptor (Read) Format
84f4ee90 413 *
5f450212
BA		 414 * +-----------------------------------------------------+
415 * 0 | Buffer Address [63:0] |
416 * +-----------------------------------------------------+
417 * 8 | Reserved |
418 * +-----------------------------------------------------+
84f4ee90 419 */
ef456f85 420 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 421 /* Extended Receive Descriptor (Write-Back) Format
422 *
423 * 63 48 47 32 31 24 23 4 3 0
424 * +------------------------------------------------------+
425 * | RSS Hash | | | |
426 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
427 * | Packet | IP | | | Type |
428 * | Checksum | Ident | | | |
429 * +------------------------------------------------------+
430 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
431 * +------------------------------------------------------+
432 * 63 48 47 32 31 20 19 0
433 */
ef456f85 434 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 435
436 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 437 const char *next_desc;
438
84f4ee90 439 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 440 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
441 u1 = (struct my_u1 *)rx_desc;
442 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 443
444 if (i == rx_ring->next_to_use)
445 next_desc = " NTU";
446 else if (i == rx_ring->next_to_clean)
447 next_desc = " NTC";
448 else
449 next_desc = "";
450
5f450212
BA		 451 if (staterr & E1000_RXD_STAT_DD) {
452 /* Descriptor Done */
ef456f85
JK		 453 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
454 "RWB", i,
455 (unsigned long long)le64_to_cpu(u1->a),
456 (unsigned long long)le64_to_cpu(u1->b),
457 buffer_info->skb, next_desc);
5f450212 458 } else {
ef456f85
JK		 459 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
460 "R ", i,
461 (unsigned long long)le64_to_cpu(u1->a),
462 (unsigned long long)le64_to_cpu(u1->b),
463 (unsigned long long)buffer_info->dma,
464 buffer_info->skb, next_desc);
5f450212 465
f0c5dadf
ET		 466 if (netif_msg_pktdata(adapter) &&
467 buffer_info->skb)
5f450212
BA		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16,
470 1,
f0c5dadf 471 buffer_info->skb->data,
5f450212
BA		 472 adapter->rx_buffer_len,
473 true);
474 }
84f4ee90
TI		 475 }
476 }
84f4ee90
TI		 477}
478
bc7f75fa
AK		 479/**
480 * e1000_desc_unused - calculate if we have unused descriptors
481 **/
482static int e1000_desc_unused(struct e1000_ring *ring)
483{
484 if (ring->next_to_clean > ring->next_to_use)
485 return ring->next_to_clean - ring->next_to_use - 1;
486
487 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
488}
489
b67e1913
BA		 490/**
491 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
492 * @adapter: board private structure
493 * @hwtstamps: time stamp structure to update
494 * @systim: unsigned 64bit system time value.
495 *
496 * Convert the system time value stored in the RX/TXSTMP registers into a
497 * hwtstamp which can be used by the upper level time stamping functions.
498 *
499 * The 'systim_lock' spinlock is used to protect the consistency of the
500 * system time value. This is needed because reading the 64 bit time
501 * value involves reading two 32 bit registers. The first read latches the
502 * value.
503 **/
504static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
505 struct skb_shared_hwtstamps *hwtstamps,
506 u64 systim)
507{
508 u64 ns;
509 unsigned long flags;
510
511 spin_lock_irqsave(&adapter->systim_lock, flags);
512 ns = timecounter_cyc2time(&adapter->tc, systim);
513 spin_unlock_irqrestore(&adapter->systim_lock, flags);
514
515 memset(hwtstamps, 0, sizeof(*hwtstamps));
516 hwtstamps->hwtstamp = ns_to_ktime(ns);
517}
518
519/**
520 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
521 * @adapter: board private structure
522 * @status: descriptor extended error and status field
523 * @skb: particular skb to include time stamp
524 *
525 * If the time stamp is valid, convert it into the timecounter ns value
526 * and store that result into the shhwtstamps structure which is passed
527 * up the network stack.
528 **/
529static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
530 struct sk_buff *skb)
531{
532 struct e1000_hw *hw = &adapter->hw;
533 u64 rxstmp;
534
535 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
536 !(status & E1000_RXDEXT_STATERR_TST) ||
537 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
538 return;
539
540 /* The Rx time stamp registers contain the time stamp. No other
541 * received packet will be time stamped until the Rx time stamp
542 * registers are read. Because only one packet can be time stamped
543 * at a time, the register values must belong to this packet and
544 * therefore none of the other additional attributes need to be
545 * compared.
546 */
547 rxstmp = (u64)er32(RXSTMPL);
548 rxstmp |= (u64)er32(RXSTMPH) << 32;
549 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
550
551 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
552}
553
bc7f75fa 554/**
ad68076e 555 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 556 * @adapter: board private structure
b67e1913 557 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 558 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
559 * @skb: pointer to sk_buff to be indicated to stack
560 **/
561static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 562 struct net_device *netdev, struct sk_buff *skb,
b67e1913 563 u32 staterr, __le16 vlan)
bc7f75fa 564{
86d70e53 565 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 566
567 e1000e_rx_hwtstamp(adapter, staterr, skb);
568
bc7f75fa
AK		 569 skb->protocol = eth_type_trans(skb, netdev);
570
b67e1913 571 if (staterr & E1000_RXD_STAT_VP)
86d70e53
JK		 572 __vlan_hwaccel_put_tag(skb, tag);
573
574 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 575}
576
577/**
af667a29 578 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 579 * @adapter: board private structure
580 * @status_err: receive descriptor status and error fields
581 * @csum: receive descriptor csum field
582 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 583 **/
584static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 585 struct sk_buff *skb)
bc7f75fa
AK		 586{
587 u16 status = (u16)status_err;
588 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 589
590 skb_checksum_none_assert(skb);
bc7f75fa 591
afd12939
BA		 592 /* Rx checksum disabled */
593 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
594 return;
595
bc7f75fa
AK		 596 /* Ignore Checksum bit is set */
597 if (status & E1000_RXD_STAT_IXSM)
598 return;
afd12939 599
2e1706f2
BA		 600 /* TCP/UDP checksum error bit or IP checksum error bit is set */
601 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 602 /* let the stack verify checksum errors */
603 adapter->hw_csum_err++;
604 return;
605 }
606
607 /* TCP/UDP Checksum has not been calculated */
608 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
609 return;
610
611 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 612 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 613 adapter->hw_csum_good++;
614}
615
55aa6985 616static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 617{
55aa6985 618 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 619 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 620 s32 ret_val = __ew32_prepare(hw);
621
622 writel(i, rx_ring->tail);
c6e7f51e 623
bdc125f7 624 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 625 u32 rctl = er32(RCTL);
626 ew32(RCTL, rctl & ~E1000_RCTL_EN);
627 e_err("ME firmware caused invalid RDT - resetting\n");
628 schedule_work(&adapter->reset_task);
629 }
630}
631
55aa6985 632static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 633{
55aa6985 634 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 635 struct e1000_hw *hw = &adapter->hw;
bdc125f7 636 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 637
bdc125f7
BA		 638 writel(i, tx_ring->tail);
639
640 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 641 u32 tctl = er32(TCTL);
642 ew32(TCTL, tctl & ~E1000_TCTL_EN);
643 e_err("ME firmware caused invalid TDT - resetting\n");
644 schedule_work(&adapter->reset_task);
645 }
646}
647
bc7f75fa 648/**
5f450212 649 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 650 * @rx_ring: Rx descriptor ring
bc7f75fa 651 **/
55aa6985 652static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 653 int cleaned_count, gfp_t gfp)
bc7f75fa 654{
55aa6985 655 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 656 struct net_device *netdev = adapter->netdev;
657 struct pci_dev *pdev = adapter->pdev;
5f450212 658 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 659 struct e1000_buffer *buffer_info;
660 struct sk_buff *skb;
661 unsigned int i;
89d71a66 662 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 663
664 i = rx_ring->next_to_use;
665 buffer_info = &rx_ring->buffer_info[i];
666
667 while (cleaned_count--) {
668 skb = buffer_info->skb;
669 if (skb) {
670 skb_trim(skb, 0);
671 goto map_skb;
672 }
673
c2fed996 674 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 675 if (!skb) {
676 /* Better luck next round */
677 adapter->alloc_rx_buff_failed++;
678 break;
679 }
680
bc7f75fa
AK		 681 buffer_info->skb = skb;
682map_skb:
0be3f55f 683 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 684 adapter->rx_buffer_len,
0be3f55f
NN		 685 DMA_FROM_DEVICE);
686 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 687 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 688 adapter->rx_dma_failed++;
689 break;
690 }
691
5f450212
BA		 692 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
693 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 694
50849d79 695 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 696 /* Force memory writes to complete before letting h/w
50849d79
TH		 697 * know there are new descriptors to fetch. (Only
698 * applicable for weak-ordered memory model archs,
699 * such as IA-64).
700 */
701 wmb();
c6e7f51e 702 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 703 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 704 else
c5083cf6 705 writel(i, rx_ring->tail);
50849d79 706 }
bc7f75fa
AK		 707 i++;
708 if (i == rx_ring->count)
709 i = 0;
710 buffer_info = &rx_ring->buffer_info[i];
711 }
712
50849d79 713 rx_ring->next_to_use = i;
bc7f75fa
AK		 714}
715
716/**
717 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 718 * @rx_ring: Rx descriptor ring
bc7f75fa 719 **/
55aa6985 720static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 721 int cleaned_count, gfp_t gfp)
bc7f75fa 722{
55aa6985 723 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 724 struct net_device *netdev = adapter->netdev;
725 struct pci_dev *pdev = adapter->pdev;
726 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 727 struct e1000_buffer *buffer_info;
728 struct e1000_ps_page *ps_page;
729 struct sk_buff *skb;
730 unsigned int i, j;
731
732 i = rx_ring->next_to_use;
733 buffer_info = &rx_ring->buffer_info[i];
734
735 while (cleaned_count--) {
736 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
737
738 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 739 ps_page = &buffer_info->ps_pages[j];
740 if (j >= adapter->rx_ps_pages) {
741 /* all unused desc entries get hw null ptr */
af667a29
BA		 742 rx_desc->read.buffer_addr[j + 1] =
743 ~cpu_to_le64(0);
47f44e40
AK		 744 continue;
745 }
746 if (!ps_page->page) {
c2fed996 747 ps_page->page = alloc_page(gfp);
bc7f75fa 748 if (!ps_page->page) {
47f44e40
AK		 749 adapter->alloc_rx_buff_failed++;
750 goto no_buffers;
751 }
0be3f55f
NN		 752 ps_page->dma = dma_map_page(&pdev->dev,
753 ps_page->page,
754 0, PAGE_SIZE,
755 DMA_FROM_DEVICE);
756 if (dma_mapping_error(&pdev->dev,
757 ps_page->dma)) {
47f44e40 758 dev_err(&adapter->pdev->dev,
af667a29 759 "Rx DMA page map failed\n");
47f44e40
AK		 760 adapter->rx_dma_failed++;
761 goto no_buffers;
bc7f75fa 762 }
bc7f75fa 763 }
e921eb1a 764 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 765 * didn't change because each write-back
766 * erases this info.
767 */
af667a29
BA		 768 rx_desc->read.buffer_addr[j + 1] =
769 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 770 }
771
c2fed996
JK		 772 skb = __netdev_alloc_skb_ip_align(netdev,
773 adapter->rx_ps_bsize0,
774 gfp);
bc7f75fa
AK		 775
776 if (!skb) {
777 adapter->alloc_rx_buff_failed++;
778 break;
779 }
780
bc7f75fa 781 buffer_info->skb = skb;
0be3f55f 782 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 783 adapter->rx_ps_bsize0,
0be3f55f
NN		 784 DMA_FROM_DEVICE);
785 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 786 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 787 adapter->rx_dma_failed++;
788 /* cleanup skb */
789 dev_kfree_skb_any(skb);
790 buffer_info->skb = NULL;
791 break;
792 }
793
794 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
795
50849d79 796 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 797 /* Force memory writes to complete before letting h/w
50849d79
TH		 798 * know there are new descriptors to fetch. (Only
799 * applicable for weak-ordered memory model archs,
800 * such as IA-64).
801 */
802 wmb();
c6e7f51e 803 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 804 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 805 else
c5083cf6 806 writel(i << 1, rx_ring->tail);
50849d79
TH		 807 }
808
bc7f75fa
AK		 809 i++;
810 if (i == rx_ring->count)
811 i = 0;
812 buffer_info = &rx_ring->buffer_info[i];
813 }
814
815no_buffers:
50849d79 816 rx_ring->next_to_use = i;
bc7f75fa
AK		 817}
818
97ac8cae
BA		 819/**
820 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 821 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 822 * @cleaned_count: number of buffers to allocate this pass
823 **/
824
55aa6985 825static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 826 int cleaned_count, gfp_t gfp)
97ac8cae 827{
55aa6985 828 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 829 struct net_device *netdev = adapter->netdev;
830 struct pci_dev *pdev = adapter->pdev;
5f450212 831 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 832 struct e1000_buffer *buffer_info;
833 struct sk_buff *skb;
834 unsigned int i;
2a2293b9 835 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 836
837 i = rx_ring->next_to_use;
838 buffer_info = &rx_ring->buffer_info[i];
839
840 while (cleaned_count--) {
841 skb = buffer_info->skb;
842 if (skb) {
843 skb_trim(skb, 0);
844 goto check_page;
845 }
846
c2fed996 847 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 848 if (unlikely(!skb)) {
849 /* Better luck next round */
850 adapter->alloc_rx_buff_failed++;
851 break;
852 }
853
97ac8cae
BA		 854 buffer_info->skb = skb;
855check_page:
856 /* allocate a new page if necessary */
857 if (!buffer_info->page) {
c2fed996 858 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 859 if (unlikely(!buffer_info->page)) {
860 adapter->alloc_rx_buff_failed++;
861 break;
862 }
863 }
864
865 if (!buffer_info->dma)
0be3f55f 866 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 867 buffer_info->page, 0,
868 PAGE_SIZE,
0be3f55f 869 DMA_FROM_DEVICE);
97ac8cae 870
5f450212
BA		 871 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
872 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 873
874 if (unlikely(++i == rx_ring->count))
875 i = 0;
876 buffer_info = &rx_ring->buffer_info[i];
877 }
878
879 if (likely(rx_ring->next_to_use != i)) {
880 rx_ring->next_to_use = i;
881 if (unlikely(i-- == 0))
882 i = (rx_ring->count - 1);
883
884 /* Force memory writes to complete before letting h/w
885 * know there are new descriptors to fetch. (Only
886 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 887 * such as IA-64).
888 */
97ac8cae 889 wmb();
c6e7f51e 890 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 891 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 892 else
c5083cf6 893 writel(i, rx_ring->tail);
97ac8cae
BA		 894 }
895}
896
70495a50
BA		 897static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
898 struct sk_buff *skb)
899{
900 if (netdev->features & NETIF_F_RXHASH)
901 skb->rxhash = le32_to_cpu(rss);
902}
903
bc7f75fa 904/**
55aa6985
BA		 905 * e1000_clean_rx_irq - Send received data up the network stack
906 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 907 *
908 * the return value indicates whether actual cleaning was done, there
909 * is no guarantee that everything was cleaned
910 **/
55aa6985
BA		 911static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
912 int work_to_do)
bc7f75fa 913{
55aa6985 914 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 915 struct net_device *netdev = adapter->netdev;
916 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 917 struct e1000_hw *hw = &adapter->hw;
5f450212 918 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 919 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 920 u32 length, staterr;
bc7f75fa
AK		 921 unsigned int i;
922 int cleaned_count = 0;
3db1cd5c 923 bool cleaned = false;
bc7f75fa
AK		 924 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
925
926 i = rx_ring->next_to_clean;
5f450212
BA		 927 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 929 buffer_info = &rx_ring->buffer_info[i];
930
5f450212 931 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 932 struct sk_buff *skb;
bc7f75fa
AK		 933
934 if (*work_done >= work_to_do)
935 break;
936 (*work_done)++;
2d0bb1c1 937 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 938
bc7f75fa
AK		 939 skb = buffer_info->skb;
940 buffer_info->skb = NULL;
941
942 prefetch(skb->data - NET_IP_ALIGN);
943
944 i++;
945 if (i == rx_ring->count)
946 i = 0;
5f450212 947 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 948 prefetch(next_rxd);
949
950 next_buffer = &rx_ring->buffer_info[i];
951
3db1cd5c 952 cleaned = true;
bc7f75fa 953 cleaned_count++;
0be3f55f 954 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 955 buffer_info->dma,
956 adapter->rx_buffer_len,
0be3f55f 957 DMA_FROM_DEVICE);
bc7f75fa
AK		 958 buffer_info->dma = 0;
959
5f450212 960 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 961
e921eb1a 962 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 963 * packet, if that's the case we need to toss it. In fact, we
964 * need to toss every packet with the EOP bit clear and the
965 * next frame that _does_ have the EOP bit set, as it is by
966 * definition only a frame fragment
967 */
5f450212 968 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 969 adapter->flags2 |= FLAG2_IS_DISCARDING;
970
971 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 972 /* All receives must fit into a single buffer */
3bb99fe2 973 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 974 /* recycle */
975 buffer_info->skb = skb;
5f450212 976 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 977 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 978 goto next_desc;
979 }
980
cf955e6c
BG		 981 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
982 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 983 /* recycle */
984 buffer_info->skb = skb;
985 goto next_desc;
986 }
987
eb7c3adb 988 /* adjust length to remove Ethernet CRC */
0184039a
BG		 989 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
990 /* If configured to store CRC, don't subtract FCS,
991 * but keep the FCS bytes out of the total_rx_bytes
992 * counter
993 */
994 if (netdev->features & NETIF_F_RXFCS)
995 total_rx_bytes -= 4;
996 else
997 length -= 4;
998 }
eb7c3adb 999
bc7f75fa
AK		 1000 total_rx_bytes += length;
1001 total_rx_packets++;
1002
e921eb1a 1003 /* code added for copybreak, this should improve
bc7f75fa 1004 * performance for small packets with large amounts
ad68076e
BA		 1005 * of reassembly being done in the stack
1006 */
bc7f75fa
AK		 1007 if (length < copybreak) {
1008 struct sk_buff *new_skb =
89d71a66 1009 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 1010 if (new_skb) {
808ff676
BA		 1011 skb_copy_to_linear_data_offset(new_skb,
1012 -NET_IP_ALIGN,
1013 (skb->data -
1014 NET_IP_ALIGN),
1015 (length +
1016 NET_IP_ALIGN));
bc7f75fa
AK		 1017 /* save the skb in buffer_info as good */
1018 buffer_info->skb = skb;
1019 skb = new_skb;
1020 }
1021 /* else just continue with the old one */
1022 }
1023 /* end copybreak code */
1024 skb_put(skb, length);
1025
1026 /* Receive Checksum Offload */
2e1706f2 1027 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1028
70495a50
BA		 1029 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1030
5f450212
BA		 1031 e1000_receive_skb(adapter, netdev, skb, staterr,
1032 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1033
1034next_desc:
5f450212 1035 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1036
1037 /* return some buffers to hardware, one at a time is too slow */
1038 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1039 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1040 GFP_ATOMIC);
bc7f75fa
AK		 1041 cleaned_count = 0;
1042 }
1043
1044 /* use prefetched values */
1045 rx_desc = next_rxd;
1046 buffer_info = next_buffer;
5f450212
BA		 1047
1048 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1049 }
1050 rx_ring->next_to_clean = i;
1051
1052 cleaned_count = e1000_desc_unused(rx_ring);
1053 if (cleaned_count)
55aa6985 1054 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1055
bc7f75fa 1056 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1057 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1058 return cleaned;
1059}
1060
55aa6985
BA		 1061static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1062 struct e1000_buffer *buffer_info)
bc7f75fa 1063{
55aa6985
BA		 1064 struct e1000_adapter *adapter = tx_ring->adapter;
1065
03b1320d
AD		 1066 if (buffer_info->dma) {
1067 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1068 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1069 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1070 else
0be3f55f
NN		 1071 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1072 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1073 buffer_info->dma = 0;
1074 }
bc7f75fa
AK		 1075 if (buffer_info->skb) {
1076 dev_kfree_skb_any(buffer_info->skb);
1077 buffer_info->skb = NULL;
1078 }
1b7719c4 1079 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1080}
1081
41cec6f1 1082static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1083{
41cec6f1
BA		 1084 struct e1000_adapter *adapter = container_of(work,
1085 struct e1000_adapter,
1086 print_hang_task);
09357b00 1087 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1088 struct e1000_ring *tx_ring = adapter->tx_ring;
1089 unsigned int i = tx_ring->next_to_clean;
1090 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1091 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1092 struct e1000_hw *hw = &adapter->hw;
1093 u16 phy_status, phy_1000t_status, phy_ext_status;
1094 u16 pci_status;
1095
615b32af
JB		 1096 if (test_bit(__E1000_DOWN, &adapter->state))
1097 return;
1098
09357b00
JK		 1099 if (!adapter->tx_hang_recheck &&
1100 (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1101 /* May be block on write-back, flush and detect again
09357b00
JK		 1102 * flush pending descriptor writebacks to memory
1103 */
1104 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1105 /* execute the writes immediately */
1106 e1e_flush();
e921eb1a 1107 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1108 * the write is successful
1109 */
1110 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1111 /* execute the writes immediately */
1112 e1e_flush();
09357b00
JK		 1113 adapter->tx_hang_recheck = true;
1114 return;
1115 }
1116 /* Real hang detected */
1117 adapter->tx_hang_recheck = false;
1118 netif_stop_queue(netdev);
1119
41cec6f1
BA		 1120 e1e_rphy(hw, PHY_STATUS, &phy_status);
1121 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1122 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1123
41cec6f1
BA		 1124 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1125
1126 /* detected Hardware unit hang */
1127 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1128 " TDH <%x>\n"
1129 " TDT <%x>\n"
1130 " next_to_use <%x>\n"
1131 " next_to_clean <%x>\n"
1132 "buffer_info[next_to_clean]:\n"
1133 " time_stamp <%lx>\n"
1134 " next_to_watch <%x>\n"
1135 " jiffies <%lx>\n"
41cec6f1
BA		 1136 " next_to_watch.status <%x>\n"
1137 "MAC Status <%x>\n"
1138 "PHY Status <%x>\n"
1139 "PHY 1000BASE-T Status <%x>\n"
1140 "PHY Extended Status <%x>\n"
1141 "PCI Status <%x>\n",
c5083cf6
BA		 1142 readl(tx_ring->head),
1143 readl(tx_ring->tail),
44defeb3
JK		 1144 tx_ring->next_to_use,
1145 tx_ring->next_to_clean,
1146 tx_ring->buffer_info[eop].time_stamp,
1147 eop,
1148 jiffies,
41cec6f1
BA		 1149 eop_desc->upper.fields.status,
1150 er32(STATUS),
1151 phy_status,
1152 phy_1000t_status,
1153 phy_ext_status,
1154 pci_status);
7c0427ee
BA		 1155
1156 /* Suggest workaround for known h/w issue */
1157 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1158 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1159}
1160
b67e1913
BA		 1161/**
1162 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1163 * @work: pointer to work struct
1164 *
1165 * This work function polls the TSYNCTXCTL valid bit to determine when a
1166 * timestamp has been taken for the current stored skb. The timestamp must
1167 * be for this skb because only one such packet is allowed in the queue.
1168 */
1169static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1170{
1171 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1172 tx_hwtstamp_work);
1173 struct e1000_hw *hw = &adapter->hw;
1174
1175 if (!adapter->tx_hwtstamp_skb)
1176 return;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct skb_shared_hwtstamps shhwtstamps;
1180 u64 txstmp;
1181
1182 txstmp = er32(TXSTMPL);
1183 txstmp |= (u64)er32(TXSTMPH) << 32;
1184
1185 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1186
1187 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1188 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1189 adapter->tx_hwtstamp_skb = NULL;
1190 } else {
1191 /* reschedule to check later */
1192 schedule_work(&adapter->tx_hwtstamp_work);
1193 }
1194}
1195
bc7f75fa
AK		 1196/**
1197 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1198 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1199 *
1200 * the return value indicates whether actual cleaning was done, there
1201 * is no guarantee that everything was cleaned
1202 **/
55aa6985 1203static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1204{
55aa6985 1205 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1206 struct net_device *netdev = adapter->netdev;
1207 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1208 struct e1000_tx_desc *tx_desc, *eop_desc;
1209 struct e1000_buffer *buffer_info;
1210 unsigned int i, eop;
1211 unsigned int count = 0;
bc7f75fa 1212 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1213 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1214
1215 i = tx_ring->next_to_clean;
1216 eop = tx_ring->buffer_info[i].next_to_watch;
1217 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1218
12d04a3c
AD		 1219 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1220 (count < tx_ring->count)) {
a86043c2 1221 bool cleaned = false;
2d0bb1c1 1222 rmb(); /* read buffer_info after eop_desc */
a86043c2 1223 for (; !cleaned; count++) {
bc7f75fa
AK		 1224 tx_desc = E1000_TX_DESC(*tx_ring, i);
1225 buffer_info = &tx_ring->buffer_info[i];
1226 cleaned = (i == eop);
1227
1228 if (cleaned) {
9ed318d5
TH		 1229 total_tx_packets += buffer_info->segs;
1230 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1231 if (buffer_info->skb) {
1232 bytes_compl += buffer_info->skb->len;
1233 pkts_compl++;
1234 }
bc7f75fa
AK		 1235 }
1236
55aa6985 1237 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1238 tx_desc->upper.data = 0;
1239
1240 i++;
1241 if (i == tx_ring->count)
1242 i = 0;
1243 }
1244
dac87619
TL		 1245 if (i == tx_ring->next_to_use)
1246 break;
bc7f75fa
AK		 1247 eop = tx_ring->buffer_info[i].next_to_watch;
1248 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1249 }
1250
1251 tx_ring->next_to_clean = i;
1252
3f0cfa3b
TH		 1253 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1254
bc7f75fa 1255#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1256 if (count && netif_carrier_ok(netdev) &&
1257 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1258 /* Make sure that anybody stopping the queue after this
1259 * sees the new next_to_clean.
1260 */
1261 smp_mb();
1262
1263 if (netif_queue_stopped(netdev) &&
1264 !(test_bit(__E1000_DOWN, &adapter->state))) {
1265 netif_wake_queue(netdev);
1266 ++adapter->restart_queue;
1267 }
1268 }
1269
1270 if (adapter->detect_tx_hung) {
e921eb1a 1271 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1272 * check with the clearing of time_stamp and movement of i
1273 */
3db1cd5c 1274 adapter->detect_tx_hung = false;
12d04a3c
AD		 1275 if (tx_ring->buffer_info[i].time_stamp &&
1276 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1277 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1278 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1279 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1280 else
1281 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1282 }
1283 adapter->total_tx_bytes += total_tx_bytes;
1284 adapter->total_tx_packets += total_tx_packets;
807540ba 1285 return count < tx_ring->count;
bc7f75fa
AK		 1286}
1287
bc7f75fa
AK		 1288/**
1289 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1290 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1291 *
1292 * the return value indicates whether actual cleaning was done, there
1293 * is no guarantee that everything was cleaned
1294 **/
55aa6985
BA		 1295static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1296 int work_to_do)
bc7f75fa 1297{
55aa6985 1298 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1299 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1300 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1301 struct net_device *netdev = adapter->netdev;
1302 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1303 struct e1000_buffer *buffer_info, *next_buffer;
1304 struct e1000_ps_page *ps_page;
1305 struct sk_buff *skb;
1306 unsigned int i, j;
1307 u32 length, staterr;
1308 int cleaned_count = 0;
3db1cd5c 1309 bool cleaned = false;
bc7f75fa
AK		 1310 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1311
1312 i = rx_ring->next_to_clean;
1313 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1314 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1315 buffer_info = &rx_ring->buffer_info[i];
1316
1317 while (staterr & E1000_RXD_STAT_DD) {
1318 if (*work_done >= work_to_do)
1319 break;
1320 (*work_done)++;
1321 skb = buffer_info->skb;
2d0bb1c1 1322 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1323
1324 /* in the packet split case this is header only */
1325 prefetch(skb->data - NET_IP_ALIGN);
1326
1327 i++;
1328 if (i == rx_ring->count)
1329 i = 0;
1330 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1331 prefetch(next_rxd);
1332
1333 next_buffer = &rx_ring->buffer_info[i];
1334
3db1cd5c 1335 cleaned = true;
bc7f75fa 1336 cleaned_count++;
0be3f55f 1337 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1338 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1339 buffer_info->dma = 0;
1340
af667a29 1341 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1342 if (!(staterr & E1000_RXD_STAT_EOP))
1343 adapter->flags2 |= FLAG2_IS_DISCARDING;
1344
1345 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1346 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1347 dev_kfree_skb_irq(skb);
b94b5028
JB		 1348 if (staterr & E1000_RXD_STAT_EOP)
1349 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1350 goto next_desc;
1351 }
1352
cf955e6c
BG		 1353 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1354 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1355 dev_kfree_skb_irq(skb);
1356 goto next_desc;
1357 }
1358
1359 length = le16_to_cpu(rx_desc->wb.middle.length0);
1360
1361 if (!length) {
ef456f85 1362 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1363 dev_kfree_skb_irq(skb);
1364 goto next_desc;
1365 }
1366
1367 /* Good Receive */
1368 skb_put(skb, length);
1369
1370 {
e921eb1a 1371 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1372 * it more efficient than reusing j
1373 */
1374 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1375
e921eb1a 1376 /* page alloc/put takes too long and effects small
0e15df49
BA		 1377 * packet throughput, so unsplit small packets and
1378 * save the alloc/put only valid in softirq (napi)
1379 * context to call kmap_*
ad68076e 1380 */
0e15df49
BA		 1381 if (l1 && (l1 <= copybreak) &&
1382 ((length + l1) <= adapter->rx_ps_bsize0)) {
1383 u8 *vaddr;
1384
1385 ps_page = &buffer_info->ps_pages[0];
1386
e921eb1a 1387 /* there is no documentation about how to call
0e15df49
BA		 1388 * kmap_atomic, so we can't hold the mapping
1389 * very long
1390 */
1391 dma_sync_single_for_cpu(&pdev->dev,
1392 ps_page->dma,
1393 PAGE_SIZE,
1394 DMA_FROM_DEVICE);
9f393834 1395 vaddr = kmap_atomic(ps_page->page);
0e15df49 1396 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1397 kunmap_atomic(vaddr);
0e15df49
BA		 1398 dma_sync_single_for_device(&pdev->dev,
1399 ps_page->dma,
1400 PAGE_SIZE,
1401 DMA_FROM_DEVICE);
1402
1403 /* remove the CRC */
0184039a
BG		 1404 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1405 if (!(netdev->features & NETIF_F_RXFCS))
1406 l1 -= 4;
1407 }
0e15df49
BA		 1408
1409 skb_put(skb, l1);
1410 goto copydone;
1411 } /* if */
bc7f75fa
AK		 1412 }
1413
1414 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1415 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1416 if (!length)
1417 break;
1418
47f44e40 1419 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1420 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1421 DMA_FROM_DEVICE);
bc7f75fa
AK		 1422 ps_page->dma = 0;
1423 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1424 ps_page->page = NULL;
1425 skb->len += length;
1426 skb->data_len += length;
98a045d7 1427 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1428 }
1429
eb7c3adb
JK		 1430 /* strip the ethernet crc, problem is we're using pages now so
1431 * this whole operation can get a little cpu intensive
1432 */
0184039a
BG		 1433 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1434 if (!(netdev->features & NETIF_F_RXFCS))
1435 pskb_trim(skb, skb->len - 4);
1436 }
eb7c3adb 1437
bc7f75fa
AK		 1438copydone:
1439 total_rx_bytes += skb->len;
1440 total_rx_packets++;
1441
2e1706f2 1442 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1443
70495a50
BA		 1444 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1445
bc7f75fa
AK		 1446 if (rx_desc->wb.upper.header_status &
1447 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1448 adapter->rx_hdr_split++;
1449
b67e1913
BA		 1450 e1000_receive_skb(adapter, netdev, skb, staterr,
1451 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1452
1453next_desc:
1454 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1455 buffer_info->skb = NULL;
1456
1457 /* return some buffers to hardware, one at a time is too slow */
1458 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1459 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1460 GFP_ATOMIC);
bc7f75fa
AK		 1461 cleaned_count = 0;
1462 }
1463
1464 /* use prefetched values */
1465 rx_desc = next_rxd;
1466 buffer_info = next_buffer;
1467
1468 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1469 }
1470 rx_ring->next_to_clean = i;
1471
1472 cleaned_count = e1000_desc_unused(rx_ring);
1473 if (cleaned_count)
55aa6985 1474 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1475
bc7f75fa 1476 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1477 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1478 return cleaned;
1479}
1480
97ac8cae
BA		 1481/**
1482 * e1000_consume_page - helper function
1483 **/
1484static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1485 u16 length)
1486{
1487 bi->page = NULL;
1488 skb->len += length;
1489 skb->data_len += length;
98a045d7 1490 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1491}
1492
1493/**
1494 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1495 * @adapter: board private structure
1496 *
1497 * the return value indicates whether actual cleaning was done, there
1498 * is no guarantee that everything was cleaned
1499 **/
55aa6985
BA		 1500static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1501 int work_to_do)
97ac8cae 1502{
55aa6985 1503 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1504 struct net_device *netdev = adapter->netdev;
1505 struct pci_dev *pdev = adapter->pdev;
5f450212 1506 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1507 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1508 u32 length, staterr;
97ac8cae
BA		 1509 unsigned int i;
1510 int cleaned_count = 0;
1511 bool cleaned = false;
1512 unsigned int total_rx_bytes=0, total_rx_packets=0;
1513
1514 i = rx_ring->next_to_clean;
5f450212
BA		 1515 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1516 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1517 buffer_info = &rx_ring->buffer_info[i];
1518
5f450212 1519 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1520 struct sk_buff *skb;
97ac8cae
BA		 1521
1522 if (*work_done >= work_to_do)
1523 break;
1524 (*work_done)++;
2d0bb1c1 1525 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1526
97ac8cae
BA		 1527 skb = buffer_info->skb;
1528 buffer_info->skb = NULL;
1529
1530 ++i;
1531 if (i == rx_ring->count)
1532 i = 0;
5f450212 1533 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1534 prefetch(next_rxd);
1535
1536 next_buffer = &rx_ring->buffer_info[i];
1537
1538 cleaned = true;
1539 cleaned_count++;
0be3f55f
NN		 1540 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1541 DMA_FROM_DEVICE);
97ac8cae
BA		 1542 buffer_info->dma = 0;
1543
5f450212 1544 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1545
1546 /* errors is only valid for DD + EOP descriptors */
5f450212 1547 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1548 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1549 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1550 /* recycle both page and skb */
1551 buffer_info->skb = skb;
1552 /* an error means any chain goes out the window too */
1553 if (rx_ring->rx_skb_top)
1554 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1555 rx_ring->rx_skb_top = NULL;
1556 goto next_desc;
97ac8cae
BA		 1557 }
1558
f0f1a172 1559#define rxtop (rx_ring->rx_skb_top)
5f450212 1560 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1561 /* this descriptor is only the beginning (or middle) */
1562 if (!rxtop) {
1563 /* this is the beginning of a chain */
1564 rxtop = skb;
1565 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1566 0, length);
1567 } else {
1568 /* this is the middle of a chain */
1569 skb_fill_page_desc(rxtop,
1570 skb_shinfo(rxtop)->nr_frags,
1571 buffer_info->page, 0, length);
1572 /* re-use the skb, only consumed the page */
1573 buffer_info->skb = skb;
1574 }
1575 e1000_consume_page(buffer_info, rxtop, length);
1576 goto next_desc;
1577 } else {
1578 if (rxtop) {
1579 /* end of the chain */
1580 skb_fill_page_desc(rxtop,
1581 skb_shinfo(rxtop)->nr_frags,
1582 buffer_info->page, 0, length);
1583 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1584 * page
1585 */
97ac8cae
BA		 1586 buffer_info->skb = skb;
1587 skb = rxtop;
1588 rxtop = NULL;
1589 e1000_consume_page(buffer_info, skb, length);
1590 } else {
1591 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1592 * copybreak to save the put_page/alloc_page
1593 */
97ac8cae
BA		 1594 if (length <= copybreak &&
1595 skb_tailroom(skb) >= length) {
1596 u8 *vaddr;
4679026d 1597 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1598 memcpy(skb_tail_pointer(skb), vaddr,
1599 length);
4679026d 1600 kunmap_atomic(vaddr);
97ac8cae 1601 /* re-use the page, so don't erase
e921eb1a
BA		 1602 * buffer_info->page
1603 */
97ac8cae
BA		 1604 skb_put(skb, length);
1605 } else {
1606 skb_fill_page_desc(skb, 0,
1607 buffer_info->page, 0,
1608 length);
1609 e1000_consume_page(buffer_info, skb,
1610 length);
1611 }
1612 }
1613 }
1614
2e1706f2
BA		 1615 /* Receive Checksum Offload */
1616 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1617
70495a50
BA		 1618 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1619
97ac8cae
BA		 1620 /* probably a little skewed due to removing CRC */
1621 total_rx_bytes += skb->len;
1622 total_rx_packets++;
1623
1624 /* eth type trans needs skb->data to point to something */
1625 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1626 e_err("pskb_may_pull failed.\n");
ef5ab89c 1627 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1628 goto next_desc;
1629 }
1630
5f450212
BA		 1631 e1000_receive_skb(adapter, netdev, skb, staterr,
1632 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1633
1634next_desc:
5f450212 1635 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1636
1637 /* return some buffers to hardware, one at a time is too slow */
1638 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1639 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1640 GFP_ATOMIC);
97ac8cae
BA		 1641 cleaned_count = 0;
1642 }
1643
1644 /* use prefetched values */
1645 rx_desc = next_rxd;
1646 buffer_info = next_buffer;
5f450212
BA		 1647
1648 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1649 }
1650 rx_ring->next_to_clean = i;
1651
1652 cleaned_count = e1000_desc_unused(rx_ring);
1653 if (cleaned_count)
55aa6985 1654 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1655
1656 adapter->total_rx_bytes += total_rx_bytes;
1657 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1658 return cleaned;
1659}
1660
bc7f75fa
AK		 1661/**
1662 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1663 * @rx_ring: Rx descriptor ring
bc7f75fa 1664 **/
55aa6985 1665static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1666{
55aa6985 1667 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1668 struct e1000_buffer *buffer_info;
1669 struct e1000_ps_page *ps_page;
1670 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1671 unsigned int i, j;
1672
1673 /* Free all the Rx ring sk_buffs */
1674 for (i = 0; i < rx_ring->count; i++) {
1675 buffer_info = &rx_ring->buffer_info[i];
1676 if (buffer_info->dma) {
1677 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1678 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1679 adapter->rx_buffer_len,
0be3f55f 1680 DMA_FROM_DEVICE);
97ac8cae 1681 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1682 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1683 PAGE_SIZE,
0be3f55f 1684 DMA_FROM_DEVICE);
bc7f75fa 1685 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1686 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1687 adapter->rx_ps_bsize0,
0be3f55f 1688 DMA_FROM_DEVICE);
bc7f75fa
AK		 1689 buffer_info->dma = 0;
1690 }
1691
97ac8cae
BA		 1692 if (buffer_info->page) {
1693 put_page(buffer_info->page);
1694 buffer_info->page = NULL;
1695 }
1696
bc7f75fa
AK		 1697 if (buffer_info->skb) {
1698 dev_kfree_skb(buffer_info->skb);
1699 buffer_info->skb = NULL;
1700 }
1701
1702 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1703 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1704 if (!ps_page->page)
1705 break;
0be3f55f
NN		 1706 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1707 DMA_FROM_DEVICE);
bc7f75fa
AK		 1708 ps_page->dma = 0;
1709 put_page(ps_page->page);
1710 ps_page->page = NULL;
1711 }
1712 }
1713
1714 /* there also may be some cached data from a chained receive */
1715 if (rx_ring->rx_skb_top) {
1716 dev_kfree_skb(rx_ring->rx_skb_top);
1717 rx_ring->rx_skb_top = NULL;
1718 }
1719
bc7f75fa
AK		 1720 /* Zero out the descriptor ring */
1721 memset(rx_ring->desc, 0, rx_ring->size);
1722
1723 rx_ring->next_to_clean = 0;
1724 rx_ring->next_to_use = 0;
b94b5028 1725 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1726
c5083cf6 1727 writel(0, rx_ring->head);
bdc125f7
BA		 1728 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1729 e1000e_update_rdt_wa(rx_ring, 0);
1730 else
1731 writel(0, rx_ring->tail);
bc7f75fa
AK		 1732}
1733
a8f88ff5
JB		 1734static void e1000e_downshift_workaround(struct work_struct *work)
1735{
1736 struct e1000_adapter *adapter = container_of(work,
1737 struct e1000_adapter, downshift_task);
1738
615b32af
JB		 1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
a8f88ff5
JB		 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
bc7f75fa
AK		 1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
e921eb1a 1757 /* read ICR disables interrupts using IAM */
573cca8c 1758 if (icr & E1000_ICR_LSC) {
f92518dd 1759 hw->mac.get_link_status = true;
e921eb1a 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1761 * disconnect (LSC) before accessing any PHY registers
1762 */
bc7f75fa
AK		 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1765 schedule_work(&adapter->downshift_task);
bc7f75fa 1766
e921eb1a 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1768 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1769 * adapter in watchdog
1770 */
bc7f75fa
AK		 1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1776 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1777 }
1778 /* guard against interrupt when we're going down */
1779 if (!test_bit(__E1000_DOWN, &adapter->state))
1780 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1781 }
1782
288379f0 1783 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1784 adapter->total_tx_bytes = 0;
1785 adapter->total_tx_packets = 0;
1786 adapter->total_rx_bytes = 0;
1787 adapter->total_rx_packets = 0;
288379f0 1788 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1789 }
1790
1791 return IRQ_HANDLED;
1792}
1793
1794/**
1795 * e1000_intr - Interrupt Handler
1796 * @irq: interrupt number
1797 * @data: pointer to a network interface device structure
1798 **/
1799static irqreturn_t e1000_intr(int irq, void *data)
1800{
1801 struct net_device *netdev = data;
1802 struct e1000_adapter *adapter = netdev_priv(netdev);
1803 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1804 u32 rctl, icr = er32(ICR);
4662e82b 1805
a68ea775 1806 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1807 return IRQ_NONE; /* Not our interrupt */
1808
e921eb1a 1809 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1810 * not set, then the adapter didn't send an interrupt
1811 */
bc7f75fa
AK		 1812 if (!(icr & E1000_ICR_INT_ASSERTED))
1813 return IRQ_NONE;
1814
e921eb1a 1815 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1816 * interrupts are masked. No need for the
1817 * IMC write
1818 */
bc7f75fa 1819
573cca8c 1820 if (icr & E1000_ICR_LSC) {
f92518dd 1821 hw->mac.get_link_status = true;
e921eb1a 1822 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1823 * disconnect (LSC) before accessing any PHY registers
1824 */
bc7f75fa
AK		 1825 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1826 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1827 schedule_work(&adapter->downshift_task);
bc7f75fa 1828
e921eb1a 1829 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1830 * For packet buffer work-around on link down event;
1831 * disable receives here in the ISR and
1832 * reset adapter in watchdog
1833 */
1834 if (netif_carrier_ok(netdev) &&
1835 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1836 /* disable receives */
1837 rctl = er32(RCTL);
1838 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1839 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1840 }
1841 /* guard against interrupt when we're going down */
1842 if (!test_bit(__E1000_DOWN, &adapter->state))
1843 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1844 }
1845
288379f0 1846 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1847 adapter->total_tx_bytes = 0;
1848 adapter->total_tx_packets = 0;
1849 adapter->total_rx_bytes = 0;
1850 adapter->total_rx_packets = 0;
288379f0 1851 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1852 }
1853
1854 return IRQ_HANDLED;
1855}
1856
4662e82b
BA		 1857static irqreturn_t e1000_msix_other(int irq, void *data)
1858{
1859 struct net_device *netdev = data;
1860 struct e1000_adapter *adapter = netdev_priv(netdev);
1861 struct e1000_hw *hw = &adapter->hw;
1862 u32 icr = er32(ICR);
1863
1864 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1865 if (!test_bit(__E1000_DOWN, &adapter->state))
1866 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1867 return IRQ_NONE;
1868 }
1869
1870 if (icr & adapter->eiac_mask)
1871 ew32(ICS, (icr & adapter->eiac_mask));
1872
1873 if (icr & E1000_ICR_OTHER) {
1874 if (!(icr & E1000_ICR_LSC))
1875 goto no_link_interrupt;
f92518dd 1876 hw->mac.get_link_status = true;
4662e82b
BA		 1877 /* guard against interrupt when we're going down */
1878 if (!test_bit(__E1000_DOWN, &adapter->state))
1879 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1880 }
1881
1882no_link_interrupt:
a3c69fef
JB		 1883 if (!test_bit(__E1000_DOWN, &adapter->state))
1884 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1885
1886 return IRQ_HANDLED;
1887}
1888
1889
1890static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1891{
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 struct e1000_ring *tx_ring = adapter->tx_ring;
1896
1897
1898 adapter->total_tx_bytes = 0;
1899 adapter->total_tx_packets = 0;
1900
55aa6985 1901 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1902 /* Ring was not completely cleaned, so fire another interrupt */
1903 ew32(ICS, tx_ring->ims_val);
1904
1905 return IRQ_HANDLED;
1906}
1907
1908static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1909{
1910 struct net_device *netdev = data;
1911 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1912 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1913
1914 /* Write the ITR value calculated at the end of the
1915 * previous interrupt.
1916 */
55aa6985
BA		 1917 if (rx_ring->set_itr) {
1918 writel(1000000000 / (rx_ring->itr_val * 256),
1919 rx_ring->itr_register);
1920 rx_ring->set_itr = 0;
4662e82b
BA		 1921 }
1922
288379f0 1923 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1924 adapter->total_rx_bytes = 0;
1925 adapter->total_rx_packets = 0;
288379f0 1926 __napi_schedule(&adapter->napi);
4662e82b
BA		 1927 }
1928 return IRQ_HANDLED;
1929}
1930
1931/**
1932 * e1000_configure_msix - Configure MSI-X hardware
1933 *
1934 * e1000_configure_msix sets up the hardware to properly
1935 * generate MSI-X interrupts.
1936 **/
1937static void e1000_configure_msix(struct e1000_adapter *adapter)
1938{
1939 struct e1000_hw *hw = &adapter->hw;
1940 struct e1000_ring *rx_ring = adapter->rx_ring;
1941 struct e1000_ring *tx_ring = adapter->tx_ring;
1942 int vector = 0;
1943 u32 ctrl_ext, ivar = 0;
1944
1945 adapter->eiac_mask = 0;
1946
1947 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1948 if (hw->mac.type == e1000_82574) {
1949 u32 rfctl = er32(RFCTL);
1950 rfctl |= E1000_RFCTL_ACK_DIS;
1951 ew32(RFCTL, rfctl);
1952 }
1953
1954#define E1000_IVAR_INT_ALLOC_VALID 0x8
1955 /* Configure Rx vector */
1956 rx_ring->ims_val = E1000_IMS_RXQ0;
1957 adapter->eiac_mask |= rx_ring->ims_val;
1958 if (rx_ring->itr_val)
1959 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1960 rx_ring->itr_register);
4662e82b 1961 else
c5083cf6 1962 writel(1, rx_ring->itr_register);
4662e82b
BA		 1963 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1964
1965 /* Configure Tx vector */
1966 tx_ring->ims_val = E1000_IMS_TXQ0;
1967 vector++;
1968 if (tx_ring->itr_val)
1969 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1970 tx_ring->itr_register);
4662e82b 1971 else
c5083cf6 1972 writel(1, tx_ring->itr_register);
4662e82b
BA		 1973 adapter->eiac_mask |= tx_ring->ims_val;
1974 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1975
1976 /* set vector for Other Causes, e.g. link changes */
1977 vector++;
1978 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1979 if (rx_ring->itr_val)
1980 writel(1000000000 / (rx_ring->itr_val * 256),
1981 hw->hw_addr + E1000_EITR_82574(vector));
1982 else
1983 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1984
1985 /* Cause Tx interrupts on every write back */
1986 ivar |= (1 << 31);
1987
1988 ew32(IVAR, ivar);
1989
1990 /* enable MSI-X PBA support */
1991 ctrl_ext = er32(CTRL_EXT);
1992 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1993
1994 /* Auto-Mask Other interrupts upon ICR read */
1995#define E1000_EIAC_MASK_82574 0x01F00000
1996 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1997 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1998 ew32(CTRL_EXT, ctrl_ext);
1999 e1e_flush();
2000}
2001
2002void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2003{
2004 if (adapter->msix_entries) {
2005 pci_disable_msix(adapter->pdev);
2006 kfree(adapter->msix_entries);
2007 adapter->msix_entries = NULL;
2008 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2009 pci_disable_msi(adapter->pdev);
2010 adapter->flags &= ~FLAG_MSI_ENABLED;
2011 }
4662e82b
BA		 2012}
2013
2014/**
2015 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2016 *
2017 * Attempt to configure interrupts using the best available
2018 * capabilities of the hardware and kernel.
2019 **/
2020void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2021{
2022 int err;
8e86acd7 2023 int i;
4662e82b
BA		 2024
2025 switch (adapter->int_mode) {
2026 case E1000E_INT_MODE_MSIX:
2027 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2028 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2029 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 2030 sizeof(struct msix_entry),
2031 GFP_KERNEL);
2032 if (adapter->msix_entries) {
8e86acd7 2033 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2034 adapter->msix_entries[i].entry = i;
2035
2036 err = pci_enable_msix(adapter->pdev,
2037 adapter->msix_entries,
8e86acd7 2038 adapter->num_vectors);
b1cdfead 2039 if (err == 0)
4662e82b
BA		 2040 return;
2041 }
2042 /* MSI-X failed, so fall through and try MSI */
ef456f85 2043 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2044 e1000e_reset_interrupt_capability(adapter);
2045 }
2046 adapter->int_mode = E1000E_INT_MODE_MSI;
2047 /* Fall through */
2048 case E1000E_INT_MODE_MSI:
2049 if (!pci_enable_msi(adapter->pdev)) {
2050 adapter->flags |= FLAG_MSI_ENABLED;
2051 } else {
2052 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2053 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2054 }
2055 /* Fall through */
2056 case E1000E_INT_MODE_LEGACY:
2057 /* Don't do anything; this is the system default */
2058 break;
2059 }
8e86acd7
JK		 2060
2061 /* store the number of vectors being used */
2062 adapter->num_vectors = 1;
4662e82b
BA		 2063}
2064
2065/**
2066 * e1000_request_msix - Initialize MSI-X interrupts
2067 *
2068 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2069 * kernel.
2070 **/
2071static int e1000_request_msix(struct e1000_adapter *adapter)
2072{
2073 struct net_device *netdev = adapter->netdev;
2074 int err = 0, vector = 0;
2075
2076 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2077 snprintf(adapter->rx_ring->name,
2078 sizeof(adapter->rx_ring->name) - 1,
2079 "%s-rx-0", netdev->name);
4662e82b
BA		 2080 else
2081 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2082 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2083 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2084 netdev);
2085 if (err)
5015e53a 2086 return err;
c5083cf6
BA		 2087 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2088 E1000_EITR_82574(vector);
4662e82b
BA		 2089 adapter->rx_ring->itr_val = adapter->itr;
2090 vector++;
2091
2092 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2093 snprintf(adapter->tx_ring->name,
2094 sizeof(adapter->tx_ring->name) - 1,
2095 "%s-tx-0", netdev->name);
4662e82b
BA		 2096 else
2097 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2098 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2099 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2100 netdev);
2101 if (err)
5015e53a 2102 return err;
c5083cf6
BA		 2103 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2104 E1000_EITR_82574(vector);
4662e82b
BA		 2105 adapter->tx_ring->itr_val = adapter->itr;
2106 vector++;
2107
2108 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2109 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2110 if (err)
5015e53a 2111 return err;
4662e82b
BA		 2112
2113 e1000_configure_msix(adapter);
5015e53a 2114
4662e82b 2115 return 0;
4662e82b
BA		 2116}
2117
f8d59f78
BA		 2118/**
2119 * e1000_request_irq - initialize interrupts
2120 *
2121 * Attempts to configure interrupts using the best available
2122 * capabilities of the hardware and kernel.
2123 **/
bc7f75fa
AK		 2124static int e1000_request_irq(struct e1000_adapter *adapter)
2125{
2126 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2127 int err;
2128
4662e82b
BA		 2129 if (adapter->msix_entries) {
2130 err = e1000_request_msix(adapter);
2131 if (!err)
2132 return err;
2133 /* fall back to MSI */
2134 e1000e_reset_interrupt_capability(adapter);
2135 adapter->int_mode = E1000E_INT_MODE_MSI;
2136 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2137 }
4662e82b 2138 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2139 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2140 netdev->name, netdev);
2141 if (!err)
2142 return err;
bc7f75fa 2143
4662e82b
BA		 2144 /* fall back to legacy interrupt */
2145 e1000e_reset_interrupt_capability(adapter);
2146 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2147 }
2148
a0607fd3 2149 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2150 netdev->name, netdev);
2151 if (err)
2152 e_err("Unable to allocate interrupt, Error: %d\n", err);
2153
bc7f75fa
AK		 2154 return err;
2155}
2156
2157static void e1000_free_irq(struct e1000_adapter *adapter)
2158{
2159 struct net_device *netdev = adapter->netdev;
2160
4662e82b
BA		 2161 if (adapter->msix_entries) {
2162 int vector = 0;
2163
2164 free_irq(adapter->msix_entries[vector].vector, netdev);
2165 vector++;
2166
2167 free_irq(adapter->msix_entries[vector].vector, netdev);
2168 vector++;
2169
2170 /* Other Causes interrupt vector */
2171 free_irq(adapter->msix_entries[vector].vector, netdev);
2172 return;
bc7f75fa 2173 }
4662e82b
BA		 2174
2175 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2176}
2177
2178/**
2179 * e1000_irq_disable - Mask off interrupt generation on the NIC
2180 **/
2181static void e1000_irq_disable(struct e1000_adapter *adapter)
2182{
2183 struct e1000_hw *hw = &adapter->hw;
2184
bc7f75fa 2185 ew32(IMC, ~0);
4662e82b
BA		 2186 if (adapter->msix_entries)
2187 ew32(EIAC_82574, 0);
bc7f75fa 2188 e1e_flush();
8e86acd7
JK		 2189
2190 if (adapter->msix_entries) {
2191 int i;
2192 for (i = 0; i < adapter->num_vectors; i++)
2193 synchronize_irq(adapter->msix_entries[i].vector);
2194 } else {
2195 synchronize_irq(adapter->pdev->irq);
2196 }
bc7f75fa
AK		 2197}
2198
2199/**
2200 * e1000_irq_enable - Enable default interrupt generation settings
2201 **/
2202static void e1000_irq_enable(struct e1000_adapter *adapter)
2203{
2204 struct e1000_hw *hw = &adapter->hw;
2205
4662e82b
BA		 2206 if (adapter->msix_entries) {
2207 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2208 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2209 } else {
2210 ew32(IMS, IMS_ENABLE_MASK);
2211 }
74ef9c39 2212 e1e_flush();
bc7f75fa
AK		 2213}
2214
2215/**
31dbe5b4 2216 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2217 * @adapter: address of board private structure
2218 *
31dbe5b4 2219 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2220 * For ASF and Pass Through versions of f/w this means that
2221 * the driver is loaded. For AMT version (only with 82573)
2222 * of the f/w this means that the network i/f is open.
2223 **/
31dbe5b4 2224void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2225{
2226 struct e1000_hw *hw = &adapter->hw;
2227 u32 ctrl_ext;
2228 u32 swsm;
2229
2230 /* Let firmware know the driver has taken over */
2231 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2232 swsm = er32(SWSM);
2233 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2234 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2235 ctrl_ext = er32(CTRL_EXT);
ad68076e 2236 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2237 }
2238}
2239
2240/**
31dbe5b4 2241 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2242 * @adapter: address of board private structure
2243 *
31dbe5b4 2244 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2245 * For ASF and Pass Through versions of f/w this means that the
2246 * driver is no longer loaded. For AMT version (only with 82573) i
2247 * of the f/w this means that the network i/f is closed.
2248 *
2249 **/
31dbe5b4 2250void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2251{
2252 struct e1000_hw *hw = &adapter->hw;
2253 u32 ctrl_ext;
2254 u32 swsm;
2255
2256 /* Let firmware taken over control of h/w */
2257 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2258 swsm = er32(SWSM);
2259 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2260 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2261 ctrl_ext = er32(CTRL_EXT);
ad68076e 2262 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2263 }
2264}
2265
bc7f75fa 2266/**
49ce9c2c 2267 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2268 **/
2269static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2270 struct e1000_ring *ring)
2271{
2272 struct pci_dev *pdev = adapter->pdev;
2273
2274 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2275 GFP_KERNEL);
2276 if (!ring->desc)
2277 return -ENOMEM;
2278
2279 return 0;
2280}
2281
2282/**
2283 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2284 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2285 *
2286 * Return 0 on success, negative on failure
2287 **/
55aa6985 2288int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2289{
55aa6985 2290 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2291 int err = -ENOMEM, size;
2292
2293 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2294 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2295 if (!tx_ring->buffer_info)
2296 goto err;
bc7f75fa
AK		 2297
2298 /* round up to nearest 4K */
2299 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2300 tx_ring->size = ALIGN(tx_ring->size, 4096);
2301
2302 err = e1000_alloc_ring_dma(adapter, tx_ring);
2303 if (err)
2304 goto err;
2305
2306 tx_ring->next_to_use = 0;
2307 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2308
2309 return 0;
2310err:
2311 vfree(tx_ring->buffer_info);
44defeb3 2312 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2313 return err;
2314}
2315
2316/**
2317 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2318 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2319 *
2320 * Returns 0 on success, negative on failure
2321 **/
55aa6985 2322int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2323{
55aa6985 2324 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2325 struct e1000_buffer *buffer_info;
2326 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2327
2328 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2329 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2330 if (!rx_ring->buffer_info)
2331 goto err;
bc7f75fa 2332
47f44e40
AK		 2333 for (i = 0; i < rx_ring->count; i++) {
2334 buffer_info = &rx_ring->buffer_info[i];
2335 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2336 sizeof(struct e1000_ps_page),
2337 GFP_KERNEL);
2338 if (!buffer_info->ps_pages)
2339 goto err_pages;
2340 }
bc7f75fa
AK		 2341
2342 desc_len = sizeof(union e1000_rx_desc_packet_split);
2343
2344 /* Round up to nearest 4K */
2345 rx_ring->size = rx_ring->count * desc_len;
2346 rx_ring->size = ALIGN(rx_ring->size, 4096);
2347
2348 err = e1000_alloc_ring_dma(adapter, rx_ring);
2349 if (err)
47f44e40 2350 goto err_pages;
bc7f75fa
AK		 2351
2352 rx_ring->next_to_clean = 0;
2353 rx_ring->next_to_use = 0;
2354 rx_ring->rx_skb_top = NULL;
2355
2356 return 0;
47f44e40
AK		 2357
2358err_pages:
2359 for (i = 0; i < rx_ring->count; i++) {
2360 buffer_info = &rx_ring->buffer_info[i];
2361 kfree(buffer_info->ps_pages);
2362 }
bc7f75fa
AK		 2363err:
2364 vfree(rx_ring->buffer_info);
e9262447 2365 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2366 return err;
2367}
2368
2369/**
2370 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2371 * @tx_ring: Tx descriptor ring
bc7f75fa 2372 **/
55aa6985 2373static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2374{
55aa6985 2375 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2376 struct e1000_buffer *buffer_info;
2377 unsigned long size;
2378 unsigned int i;
2379
2380 for (i = 0; i < tx_ring->count; i++) {
2381 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2382 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2383 }
2384
3f0cfa3b 2385 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2386 size = sizeof(struct e1000_buffer) * tx_ring->count;
2387 memset(tx_ring->buffer_info, 0, size);
2388
2389 memset(tx_ring->desc, 0, tx_ring->size);
2390
2391 tx_ring->next_to_use = 0;
2392 tx_ring->next_to_clean = 0;
2393
c5083cf6 2394 writel(0, tx_ring->head);
bdc125f7
BA		 2395 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2396 e1000e_update_tdt_wa(tx_ring, 0);
2397 else
2398 writel(0, tx_ring->tail);
bc7f75fa
AK		 2399}
2400
2401/**
2402 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2403 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2404 *
2405 * Free all transmit software resources
2406 **/
55aa6985 2407void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2408{
55aa6985 2409 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2410 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2411
55aa6985 2412 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2413
2414 vfree(tx_ring->buffer_info);
2415 tx_ring->buffer_info = NULL;
2416
2417 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2418 tx_ring->dma);
2419 tx_ring->desc = NULL;
2420}
2421
2422/**
2423 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2424 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2425 *
2426 * Free all receive software resources
2427 **/
55aa6985 2428void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2429{
55aa6985 2430 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2431 struct pci_dev *pdev = adapter->pdev;
47f44e40 2432 int i;
bc7f75fa 2433
55aa6985 2434 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2435
b1cdfead 2436 for (i = 0; i < rx_ring->count; i++)
47f44e40 2437 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2438
bc7f75fa
AK		 2439 vfree(rx_ring->buffer_info);
2440 rx_ring->buffer_info = NULL;
2441
bc7f75fa
AK		 2442 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2443 rx_ring->dma);
2444 rx_ring->desc = NULL;
2445}
2446
2447/**
2448 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2449 * @adapter: pointer to adapter
2450 * @itr_setting: current adapter->itr
2451 * @packets: the number of packets during this measurement interval
2452 * @bytes: the number of bytes during this measurement interval
2453 *
bc7f75fa
AK		 2454 * Stores a new ITR value based on packets and byte
2455 * counts during the last interrupt. The advantage of per interrupt
2456 * computation is faster updates and more accurate ITR for the current
2457 * traffic pattern. Constants in this function were computed
2458 * based on theoretical maximum wire speed and thresholds were set based
2459 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2460 * while increasing bulk throughput. This functionality is controlled
2461 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2462 **/
2463static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2464 u16 itr_setting, int packets,
2465 int bytes)
2466{
2467 unsigned int retval = itr_setting;
2468
2469 if (packets == 0)
5015e53a 2470 return itr_setting;
bc7f75fa
AK		 2471
2472 switch (itr_setting) {
2473 case lowest_latency:
2474 /* handle TSO and jumbo frames */
2475 if (bytes/packets > 8000)
2476 retval = bulk_latency;
b1cdfead 2477 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2478 retval = low_latency;
bc7f75fa
AK		 2479 break;
2480 case low_latency: /* 50 usec aka 20000 ints/s */
2481 if (bytes > 10000) {
2482 /* this if handles the TSO accounting */
b1cdfead 2483 if (bytes/packets > 8000)
bc7f75fa 2484 retval = bulk_latency;
b1cdfead 2485 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2486 retval = bulk_latency;
b1cdfead 2487 else if ((packets > 35))
bc7f75fa 2488 retval = lowest_latency;
bc7f75fa
AK		 2489 } else if (bytes/packets > 2000) {
2490 retval = bulk_latency;
2491 } else if (packets <= 2 && bytes < 512) {
2492 retval = lowest_latency;
2493 }
2494 break;
2495 case bulk_latency: /* 250 usec aka 4000 ints/s */
2496 if (bytes > 25000) {
b1cdfead 2497 if (packets > 35)
bc7f75fa 2498 retval = low_latency;
bc7f75fa
AK		 2499 } else if (bytes < 6000) {
2500 retval = low_latency;
2501 }
2502 break;
2503 }
2504
bc7f75fa
AK		 2505 return retval;
2506}
2507
2508static void e1000_set_itr(struct e1000_adapter *adapter)
2509{
bc7f75fa
AK		 2510 u16 current_itr;
2511 u32 new_itr = adapter->itr;
2512
2513 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2514 if (adapter->link_speed != SPEED_1000) {
2515 current_itr = 0;
2516 new_itr = 4000;
2517 goto set_itr_now;
2518 }
2519
828bac87
BA		 2520 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2521 new_itr = 0;
2522 goto set_itr_now;
2523 }
2524
bc7f75fa
AK		 2525 adapter->tx_itr = e1000_update_itr(adapter,
2526 adapter->tx_itr,
2527 adapter->total_tx_packets,
2528 adapter->total_tx_bytes);
2529 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2530 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2531 adapter->tx_itr = low_latency;
2532
2533 adapter->rx_itr = e1000_update_itr(adapter,
2534 adapter->rx_itr,
2535 adapter->total_rx_packets,
2536 adapter->total_rx_bytes);
2537 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2538 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2539 adapter->rx_itr = low_latency;
2540
2541 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2542
2543 switch (current_itr) {
2544 /* counts and packets in update_itr are dependent on these numbers */
2545 case lowest_latency:
2546 new_itr = 70000;
2547 break;
2548 case low_latency:
2549 new_itr = 20000; /* aka hwitr = ~200 */
2550 break;
2551 case bulk_latency:
2552 new_itr = 4000;
2553 break;
2554 default:
2555 break;
2556 }
2557
2558set_itr_now:
2559 if (new_itr != adapter->itr) {
e921eb1a 2560 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2561 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2562 * increasing
2563 */
bc7f75fa
AK		 2564 new_itr = new_itr > adapter->itr ?
2565 min(adapter->itr + (new_itr >> 2), new_itr) :
2566 new_itr;
2567 adapter->itr = new_itr;
4662e82b
BA		 2568 adapter->rx_ring->itr_val = new_itr;
2569 if (adapter->msix_entries)
2570 adapter->rx_ring->set_itr = 1;
2571 else
e3d14b08 2572 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2573 }
2574}
2575
22a4cca2
MV		 2576/**
2577 * e1000e_write_itr - write the ITR value to the appropriate registers
2578 * @adapter: address of board private structure
2579 * @itr: new ITR value to program
2580 *
2581 * e1000e_write_itr determines if the adapter is in MSI-X mode
2582 * and, if so, writes the EITR registers with the ITR value.
2583 * Otherwise, it writes the ITR value into the ITR register.
2584 **/
2585void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2586{
2587 struct e1000_hw *hw = &adapter->hw;
2588 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2589
2590 if (adapter->msix_entries) {
2591 int vector;
2592
2593 for (vector = 0; vector < adapter->num_vectors; vector++)
2594 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2595 } else {
2596 ew32(ITR, new_itr);
2597 }
2598}
2599
4662e82b
BA		 2600/**
2601 * e1000_alloc_queues - Allocate memory for all rings
2602 * @adapter: board private structure to initialize
2603 **/
9f9a12f8 2604static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2605{
55aa6985
BA		 2606 int size = sizeof(struct e1000_ring);
2607
2608 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2609 if (!adapter->tx_ring)
2610 goto err;
55aa6985
BA		 2611 adapter->tx_ring->count = adapter->tx_ring_count;
2612 adapter->tx_ring->adapter = adapter;
4662e82b 2613
55aa6985 2614 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2615 if (!adapter->rx_ring)
2616 goto err;
55aa6985
BA		 2617 adapter->rx_ring->count = adapter->rx_ring_count;
2618 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2619
2620 return 0;
2621err:
2622 e_err("Unable to allocate memory for queues\n");
2623 kfree(adapter->rx_ring);
2624 kfree(adapter->tx_ring);
2625 return -ENOMEM;
2626}
2627
bc7f75fa 2628/**
c58c8a78 2629 * e1000e_poll - NAPI Rx polling callback
ad68076e 2630 * @napi: struct associated with this polling callback
c58c8a78 2631 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2632 **/
c58c8a78 2633static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2634{
c58c8a78
BA		 2635 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2636 napi);
4662e82b 2637 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2638 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2639 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2640
4cf1653a 2641 adapter = netdev_priv(poll_dev);
bc7f75fa 2642
c58c8a78
BA		 2643 if (!adapter->msix_entries ||
2644 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2645 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2646
c58c8a78 2647 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2648
12d04a3c 2649 if (!tx_cleaned)
c58c8a78 2650 work_done = weight;
bc7f75fa 2651
c58c8a78
BA		 2652 /* If weight not fully consumed, exit the polling mode */
2653 if (work_done < weight) {
bc7f75fa
AK		 2654 if (adapter->itr_setting & 3)
2655 e1000_set_itr(adapter);
288379f0 2656 napi_complete(napi);
a3c69fef
JB		 2657 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2658 if (adapter->msix_entries)
2659 ew32(IMS, adapter->rx_ring->ims_val);
2660 else
2661 e1000_irq_enable(adapter);
2662 }
bc7f75fa
AK		 2663 }
2664
2665 return work_done;
2666}
2667
8e586137 2668static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2669{
2670 struct e1000_adapter *adapter = netdev_priv(netdev);
2671 struct e1000_hw *hw = &adapter->hw;
2672 u32 vfta, index;
2673
2674 /* don't update vlan cookie if already programmed */
2675 if ((adapter->hw.mng_cookie.status &
2676 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2677 (vid == adapter->mng_vlan_id))
8e586137 2678 return 0;
caaddaf8 2679
bc7f75fa 2680 /* add VID to filter table */
caaddaf8
BA		 2681 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2682 index = (vid >> 5) & 0x7F;
2683 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2684 vfta |= (1 << (vid & 0x1F));
2685 hw->mac.ops.write_vfta(hw, index, vfta);
2686 }
86d70e53
JK		 2687
2688 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2689
2690 return 0;
bc7f75fa
AK		 2691}
2692
8e586137 2693static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2694{
2695 struct e1000_adapter *adapter = netdev_priv(netdev);
2696 struct e1000_hw *hw = &adapter->hw;
2697 u32 vfta, index;
2698
bc7f75fa
AK		 2699 if ((adapter->hw.mng_cookie.status &
2700 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2701 (vid == adapter->mng_vlan_id)) {
2702 /* release control to f/w */
31dbe5b4 2703 e1000e_release_hw_control(adapter);
8e586137 2704 return 0;
bc7f75fa
AK		 2705 }
2706
2707 /* remove VID from filter table */
caaddaf8
BA		 2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2711 vfta &= ~(1 << (vid & 0x1F));
2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
86d70e53
JK		 2714
2715 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2716
2717 return 0;
bc7f75fa
AK		 2718}
2719
86d70e53
JK		 2720/**
2721 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2722 * @adapter: board private structure to initialize
2723 **/
2724static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2725{
2726 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2727 struct e1000_hw *hw = &adapter->hw;
2728 u32 rctl;
bc7f75fa 2729
86d70e53
JK		 2730 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2731 /* disable VLAN receive filtering */
2732 rctl = er32(RCTL);
2733 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2734 ew32(RCTL, rctl);
2735
2736 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2737 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2738 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2739 }
bc7f75fa
AK		 2740 }
2741}
2742
86d70e53
JK		 2743/**
2744 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2745 * @adapter: board private structure to initialize
2746 **/
2747static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2748{
2749 struct e1000_hw *hw = &adapter->hw;
2750 u32 rctl;
2751
2752 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2753 /* enable VLAN receive filtering */
2754 rctl = er32(RCTL);
2755 rctl |= E1000_RCTL_VFE;
2756 rctl &= ~E1000_RCTL_CFIEN;
2757 ew32(RCTL, rctl);
2758 }
2759}
bc7f75fa 2760
86d70e53
JK		 2761/**
2762 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2763 * @adapter: board private structure to initialize
2764 **/
2765static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2766{
bc7f75fa 2767 struct e1000_hw *hw = &adapter->hw;
86d70e53 2768 u32 ctrl;
bc7f75fa 2769
86d70e53
JK		 2770 /* disable VLAN tag insert/strip */
2771 ctrl = er32(CTRL);
2772 ctrl &= ~E1000_CTRL_VME;
2773 ew32(CTRL, ctrl);
2774}
bc7f75fa 2775
86d70e53
JK		 2776/**
2777 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2778 * @adapter: board private structure to initialize
2779 **/
2780static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2781{
2782 struct e1000_hw *hw = &adapter->hw;
2783 u32 ctrl;
bc7f75fa 2784
86d70e53
JK		 2785 /* enable VLAN tag insert/strip */
2786 ctrl = er32(CTRL);
2787 ctrl |= E1000_CTRL_VME;
2788 ew32(CTRL, ctrl);
2789}
bc7f75fa 2790
86d70e53
JK		 2791static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2792{
2793 struct net_device *netdev = adapter->netdev;
2794 u16 vid = adapter->hw.mng_cookie.vlan_id;
2795 u16 old_vid = adapter->mng_vlan_id;
2796
2797 if (adapter->hw.mng_cookie.status &
2798 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2799 e1000_vlan_rx_add_vid(netdev, vid);
2800 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2801 }
2802
86d70e53
JK		 2803 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2804 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2805}
2806
2807static void e1000_restore_vlan(struct e1000_adapter *adapter)
2808{
2809 u16 vid;
2810
86d70e53 2811 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2812
86d70e53 2813 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2814 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2815}
2816
cd791618 2817static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2818{
2819 struct e1000_hw *hw = &adapter->hw;
cd791618 2820 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2821
2822 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2823 return;
2824
2825 manc = er32(MANC);
2826
e921eb1a 2827 /* enable receiving management packets to the host. this will probably
bc7f75fa 2828 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2829 * the packets will be handled on SMBUS
2830 */
bc7f75fa
AK		 2831 manc |= E1000_MANC_EN_MNG2HOST;
2832 manc2h = er32(MANC2H);
cd791618
BA		 2833
2834 switch (hw->mac.type) {
2835 default:
2836 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2837 break;
2838 case e1000_82574:
2839 case e1000_82583:
e921eb1a 2840 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2841 * if so, enable it.
2842 */
2843 for (i = 0, j = 0; i < 8; i++) {
2844 mdef = er32(MDEF(i));
2845
2846 /* Ignore filters with anything other than IPMI ports */
3b21b508 2847 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2848 continue;
2849
2850 /* Enable this decision filter in MANC2H */
2851 if (mdef)
2852 manc2h |= (1 << i);
2853
2854 j |= mdef;
2855 }
2856
2857 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2858 break;
2859
2860 /* Create new decision filter in an empty filter */
2861 for (i = 0, j = 0; i < 8; i++)
2862 if (er32(MDEF(i)) == 0) {
2863 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2864 E1000_MDEF_PORT_664));
2865 manc2h |= (1 << 1);
2866 j++;
2867 break;
2868 }
2869
2870 if (!j)
2871 e_warn("Unable to create IPMI pass-through filter\n");
2872 break;
2873 }
2874
bc7f75fa
AK		 2875 ew32(MANC2H, manc2h);
2876 ew32(MANC, manc);
2877}
2878
2879/**
af667a29 2880 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2881 * @adapter: board private structure
2882 *
2883 * Configure the Tx unit of the MAC after a reset.
2884 **/
2885static void e1000_configure_tx(struct e1000_adapter *adapter)
2886{
2887 struct e1000_hw *hw = &adapter->hw;
2888 struct e1000_ring *tx_ring = adapter->tx_ring;
2889 u64 tdba;
c550b121 2890 u32 tdlen, tarc;
bc7f75fa
AK		 2891
2892 /* Setup the HW Tx Head and Tail descriptor pointers */
2893 tdba = tx_ring->dma;
2894 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2895 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2896 ew32(TDBAH(0), (tdba >> 32));
2897 ew32(TDLEN(0), tdlen);
2898 ew32(TDH(0), 0);
2899 ew32(TDT(0), 0);
2900 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2901 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2902
bc7f75fa
AK		 2903 /* Set the Tx Interrupt Delay register */
2904 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2905 /* Tx irq moderation */
bc7f75fa
AK		 2906 ew32(TADV, adapter->tx_abs_int_delay);
2907
3a3b7586
JB		 2908 if (adapter->flags2 & FLAG2_DMA_BURST) {
2909 u32 txdctl = er32(TXDCTL(0));
2910 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2911 E1000_TXDCTL_WTHRESH);
e921eb1a 2912 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2913 * hardware to use the bus more efficiently in bursts, depends
2914 * on the tx_int_delay to be enabled,
8edc0e62 2915 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2916 * hthresh = 1 ==> prefetch when one or more available
2917 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2918 * BEWARE: this seems to work but should be considered first if
af667a29 2919 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2920 */
2921 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2922 ew32(TXDCTL(0), txdctl);
3a3b7586 2923 }
56032be7
BA		 2924 /* erratum work around: set txdctl the same for both queues */
2925 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2926
bc7f75fa 2927 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2928 tarc = er32(TARC(0));
e921eb1a 2929 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2930 * gigabit link later
2931 */
bc7f75fa
AK		 2932#define SPEED_MODE_BIT (1 << 21)
2933 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2934 ew32(TARC(0), tarc);
bc7f75fa
AK		 2935 }
2936
2937 /* errata: program both queues to unweighted RR */
2938 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2939 tarc = er32(TARC(0));
bc7f75fa 2940 tarc |= 1;
e9ec2c0f
JK		 2941 ew32(TARC(0), tarc);
2942 tarc = er32(TARC(1));
bc7f75fa 2943 tarc |= 1;
e9ec2c0f 2944 ew32(TARC(1), tarc);
bc7f75fa
AK		 2945 }
2946
bc7f75fa
AK		 2947 /* Setup Transmit Descriptor Settings for eop descriptor */
2948 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2949
2950 /* only set IDE if we are delaying interrupts using the timers */
2951 if (adapter->tx_int_delay)
2952 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2953
2954 /* enable Report Status bit */
2955 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2956
57cde763 2957 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2958}
2959
2960/**
2961 * e1000_setup_rctl - configure the receive control registers
2962 * @adapter: Board private structure
2963 **/
2964#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2965 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2966static void e1000_setup_rctl(struct e1000_adapter *adapter)
2967{
2968 struct e1000_hw *hw = &adapter->hw;
2969 u32 rctl, rfctl;
bc7f75fa
AK		 2970 u32 pages = 0;
2971
2fbe4526
BA		 2972 /* Workaround Si errata on PCHx - configure jumbo frame flow */
2973 if (hw->mac.type >= e1000_pch2lan) {
a1ce6473
BA		 2974 s32 ret_val;
2975
2976 if (adapter->netdev->mtu > ETH_DATA_LEN)
2977 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2978 else
2979 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2980
2981 if (ret_val)
2982 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2983 }
2984
bc7f75fa
AK		 2985 /* Program MC offset vector base */
2986 rctl = er32(RCTL);
2987 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2988 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2989 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2990 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2991
2992 /* Do not Store bad packets */
2993 rctl &= ~E1000_RCTL_SBP;
2994
2995 /* Enable Long Packet receive */
2996 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2997 rctl &= ~E1000_RCTL_LPE;
2998 else
2999 rctl |= E1000_RCTL_LPE;
3000
eb7c3adb
JK		 3001 /* Some systems expect that the CRC is included in SMBUS traffic. The
3002 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3003 * host memory when this is enabled
3004 */
3005 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3006 rctl |= E1000_RCTL_SECRC;
5918bd88 3007
a4f58f54
BA		 3008 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3009 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3010 u16 phy_data;
3011
3012 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3013 phy_data &= 0xfff8;
3014 phy_data |= (1 << 2);
3015 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3016
3017 e1e_rphy(hw, 22, &phy_data);
3018 phy_data &= 0x0fff;
3019 phy_data |= (1 << 14);
3020 e1e_wphy(hw, 0x10, 0x2823);
3021 e1e_wphy(hw, 0x11, 0x0003);
3022 e1e_wphy(hw, 22, phy_data);
3023 }
3024
bc7f75fa
AK		 3025 /* Setup buffer sizes */
3026 rctl &= ~E1000_RCTL_SZ_4096;
3027 rctl |= E1000_RCTL_BSEX;
3028 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3029 case 2048:
3030 default:
3031 rctl |= E1000_RCTL_SZ_2048;
3032 rctl &= ~E1000_RCTL_BSEX;
3033 break;
3034 case 4096:
3035 rctl |= E1000_RCTL_SZ_4096;
3036 break;
3037 case 8192:
3038 rctl |= E1000_RCTL_SZ_8192;
3039 break;
3040 case 16384:
3041 rctl |= E1000_RCTL_SZ_16384;
3042 break;
3043 }
3044
5f450212
BA		 3045 /* Enable Extended Status in all Receive Descriptors */
3046 rfctl = er32(RFCTL);
3047 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3048 ew32(RFCTL, rfctl);
5f450212 3049
e921eb1a 3050 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3051 * header is placed in skb->data and the packet data is
3052 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3053 * In the case of a non-split, skb->data is linearly filled,
3054 * followed by the page buffers. Therefore, skb->data is
3055 * sized to hold the largest protocol header.
3056 *
3057 * allocations using alloc_page take too long for regular MTU
3058 * so only enable packet split for jumbo frames
3059 *
3060 * Using pages when the page size is greater than 16k wastes
3061 * a lot of memory, since we allocate 3 pages at all times
3062 * per packet.
3063 */
bc7f75fa 3064 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3065 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3066 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3067 else
3068 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3069
3070 if (adapter->rx_ps_pages) {
90da0669
BA		 3071 u32 psrctl = 0;
3072
140a7480
AK		 3073 /* Enable Packet split descriptors */
3074 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 3075
3076 psrctl |= adapter->rx_ps_bsize0 >>
3077 E1000_PSRCTL_BSIZE0_SHIFT;
3078
3079 switch (adapter->rx_ps_pages) {
3080 case 3:
3081 psrctl |= PAGE_SIZE <<
3082 E1000_PSRCTL_BSIZE3_SHIFT;
3083 case 2:
3084 psrctl |= PAGE_SIZE <<
3085 E1000_PSRCTL_BSIZE2_SHIFT;
3086 case 1:
3087 psrctl |= PAGE_SIZE >>
3088 E1000_PSRCTL_BSIZE1_SHIFT;
3089 break;
3090 }
3091
3092 ew32(PSRCTL, psrctl);
3093 }
3094
cf955e6c
BG		 3095 /* This is useful for sniffing bad packets. */
3096 if (adapter->netdev->features & NETIF_F_RXALL) {
3097 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3098 * in e1000e_set_rx_mode
3099 */
cf955e6c
BG		 3100 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3101 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3102 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3103
3104 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3105 E1000_RCTL_DPF | /* Allow filtered pause */
3106 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3107 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3108 * and that breaks VLANs.
3109 */
3110 }
3111
bc7f75fa 3112 ew32(RCTL, rctl);
318a94d6 3113 /* just started the receive unit, no need to restart */
12d43f7d 3114 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3115}
3116
3117/**
3118 * e1000_configure_rx - Configure Receive Unit after Reset
3119 * @adapter: board private structure
3120 *
3121 * Configure the Rx unit of the MAC after a reset.
3122 **/
3123static void e1000_configure_rx(struct e1000_adapter *adapter)
3124{
3125 struct e1000_hw *hw = &adapter->hw;
3126 struct e1000_ring *rx_ring = adapter->rx_ring;
3127 u64 rdba;
3128 u32 rdlen, rctl, rxcsum, ctrl_ext;
3129
3130 if (adapter->rx_ps_pages) {
3131 /* this is a 32 byte descriptor */
3132 rdlen = rx_ring->count *
af667a29 3133 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3134 adapter->clean_rx = e1000_clean_rx_irq_ps;
3135 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3136 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3137 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3138 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3139 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3140 } else {
5f450212 3141 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3142 adapter->clean_rx = e1000_clean_rx_irq;
3143 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3144 }
3145
3146 /* disable receives while setting up the descriptors */
3147 rctl = er32(RCTL);
7f99ae63
BA		 3148 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3149 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3150 e1e_flush();
1bba4386 3151 usleep_range(10000, 20000);
bc7f75fa 3152
3a3b7586 3153 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3154 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3155 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3156 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3157 * granularity = 01
3158 * wthresh = 04,
3159 * hthresh = 04,
3160 * pthresh = 0x20
3161 */
3162 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3163 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3164
e921eb1a 3165 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3166 * the value was not set by the user via module options
3167 */
3168 if (adapter->rx_int_delay == DEFAULT_RDTR)
3169 adapter->rx_int_delay = BURST_RDTR;
3170 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3171 adapter->rx_abs_int_delay = BURST_RADV;
3172 }
3173
bc7f75fa
AK		 3174 /* set the Receive Delay Timer Register */
3175 ew32(RDTR, adapter->rx_int_delay);
3176
3177 /* irq moderation */
3178 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3179 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3180 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3181
3182 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3183 /* Auto-Mask interrupts upon ICR access */
3184 ctrl_ext |= E1000_CTRL_EXT_IAME;
3185 ew32(IAM, 0xffffffff);
3186 ew32(CTRL_EXT, ctrl_ext);
3187 e1e_flush();
3188
e921eb1a 3189 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3190 * the Base and Length of the Rx Descriptor Ring
3191 */
bc7f75fa 3192 rdba = rx_ring->dma;
1e36052e
BA		 3193 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3194 ew32(RDBAH(0), (rdba >> 32));
3195 ew32(RDLEN(0), rdlen);
3196 ew32(RDH(0), 0);
3197 ew32(RDT(0), 0);
3198 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3199 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3200
3201 /* Enable Receive Checksum Offload for TCP and UDP */
3202 rxcsum = er32(RXCSUM);
2e1706f2 3203 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3204 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3205 else
bc7f75fa 3206 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3207 ew32(RXCSUM, rxcsum);
3208
79d4e908 3209 if (adapter->hw.mac.type == e1000_pch2lan) {
e921eb1a 3210 /* With jumbo frames, excessive C-state transition
79d4e908
BA		 3211 * latencies result in dropped transactions.
3212 */
53ec5498
BA		 3213 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3214 u32 rxdctl = er32(RXDCTL(0));
3215 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3216 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3217 } else {
af667a29
BA		 3218 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3219 PM_QOS_DEFAULT_VALUE);
53ec5498 3220 }
97ac8cae 3221 }
bc7f75fa
AK		 3222
3223 /* Enable Receives */
3224 ew32(RCTL, rctl);
3225}
3226
3227/**
ef9b965a
JB		 3228 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3229 * @netdev: network interface device structure
bc7f75fa 3230 *
ef9b965a
JB		 3231 * Writes multicast address list to the MTA hash table.
3232 * Returns: -ENOMEM on failure
3233 * 0 on no addresses written
3234 * X on writing X addresses to MTA
3235 */
3236static int e1000e_write_mc_addr_list(struct net_device *netdev)
3237{
3238 struct e1000_adapter *adapter = netdev_priv(netdev);
3239 struct e1000_hw *hw = &adapter->hw;
3240 struct netdev_hw_addr *ha;
3241 u8 *mta_list;
3242 int i;
3243
3244 if (netdev_mc_empty(netdev)) {
3245 /* nothing to program, so clear mc list */
3246 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3247 return 0;
3248 }
3249
3250 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3251 if (!mta_list)
3252 return -ENOMEM;
3253
3254 /* update_mc_addr_list expects a packed array of only addresses. */
3255 i = 0;
3256 netdev_for_each_mc_addr(ha, netdev)
3257 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3258
3259 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3260 kfree(mta_list);
3261
3262 return netdev_mc_count(netdev);
3263}
3264
3265/**
3266 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3267 * @netdev: network interface device structure
bc7f75fa 3268 *
ef9b965a
JB		 3269 * Writes unicast address list to the RAR table.
3270 * Returns: -ENOMEM on failure/insufficient address space
3271 * 0 on no addresses written
3272 * X on writing X addresses to the RAR table
bc7f75fa 3273 **/
ef9b965a 3274static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3275{
ef9b965a
JB		 3276 struct e1000_adapter *adapter = netdev_priv(netdev);
3277 struct e1000_hw *hw = &adapter->hw;
3278 unsigned int rar_entries = hw->mac.rar_entry_count;
3279 int count = 0;
3280
3281 /* save a rar entry for our hardware address */
3282 rar_entries--;
3283
3284 /* save a rar entry for the LAA workaround */
3285 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3286 rar_entries--;
3287
3288 /* return ENOMEM indicating insufficient memory for addresses */
3289 if (netdev_uc_count(netdev) > rar_entries)
3290 return -ENOMEM;
3291
3292 if (!netdev_uc_empty(netdev) && rar_entries) {
3293 struct netdev_hw_addr *ha;
3294
e921eb1a 3295 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3296 * combining
3297 */
3298 netdev_for_each_uc_addr(ha, netdev) {
3299 if (!rar_entries)
3300 break;
69e1e019 3301 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3302 count++;
3303 }
3304 }
3305
3306 /* zero out the remaining RAR entries not used above */
3307 for (; rar_entries > 0; rar_entries--) {
3308 ew32(RAH(rar_entries), 0);
3309 ew32(RAL(rar_entries), 0);
3310 }
3311 e1e_flush();
3312
3313 return count;
bc7f75fa
AK		 3314}
3315
3316/**
ef9b965a 3317 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3318 * @netdev: network interface device structure
3319 *
ef9b965a
JB		 3320 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3321 * address list or the network interface flags are updated. This routine is
3322 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3323 * promiscuous mode, and all-multi behavior.
3324 **/
ef9b965a 3325static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3326{
3327 struct e1000_adapter *adapter = netdev_priv(netdev);
3328 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3329 u32 rctl;
bc7f75fa
AK		 3330
3331 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3332 rctl = er32(RCTL);
3333
ef9b965a
JB		 3334 /* clear the affected bits */
3335 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3336
bc7f75fa
AK		 3337 if (netdev->flags & IFF_PROMISC) {
3338 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3339 /* Do not hardware filter VLANs in promisc mode */
3340 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3341 } else {
ef9b965a 3342 int count;
3d3a1676 3343
746b9f02
PM		 3344 if (netdev->flags & IFF_ALLMULTI) {
3345 rctl |= E1000_RCTL_MPE;
746b9f02 3346 } else {
e921eb1a 3347 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3348 * then we should just turn on promiscuous mode so
3349 * that we can at least receive multicast traffic
3350 */
3351 count = e1000e_write_mc_addr_list(netdev);
3352 if (count < 0)
3353 rctl |= E1000_RCTL_MPE;
746b9f02 3354 }
86d70e53 3355 e1000e_vlan_filter_enable(adapter);
e921eb1a 3356 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3357 * sufficient space to store all the addresses then enable
3358 * unicast promiscuous mode
bc7f75fa 3359 */
ef9b965a
JB		 3360 count = e1000e_write_uc_addr_list(netdev);
3361 if (count < 0)
3362 rctl |= E1000_RCTL_UPE;
bc7f75fa 3363 }
86d70e53 3364
ef9b965a
JB		 3365 ew32(RCTL, rctl);
3366
86d70e53
JK		 3367 if (netdev->features & NETIF_F_HW_VLAN_RX)
3368 e1000e_vlan_strip_enable(adapter);
3369 else
3370 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3371}
3372
70495a50
BA		 3373static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3374{
3375 struct e1000_hw *hw = &adapter->hw;
3376 u32 mrqc, rxcsum;
3377 int i;
3378 static const u32 rsskey[10] = {
3379 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3380 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3381 };
3382
3383 /* Fill out hash function seed */
3384 for (i = 0; i < 10; i++)
3385 ew32(RSSRK(i), rsskey[i]);
3386
3387 /* Direct all traffic to queue 0 */
3388 for (i = 0; i < 32; i++)
3389 ew32(RETA(i), 0);
3390
e921eb1a 3391 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3392 * descriptor on writeback.
3393 */
3394 rxcsum = er32(RXCSUM);
3395 rxcsum |= E1000_RXCSUM_PCSD;
3396
3397 ew32(RXCSUM, rxcsum);
3398
3399 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3400 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3401 E1000_MRQC_RSS_FIELD_IPV6 |
3402 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3403 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3404
3405 ew32(MRQC, mrqc);
3406}
3407
b67e1913
BA		 3408/**
3409 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3410 * @adapter: board private structure
3411 * @timinca: pointer to returned time increment attributes
3412 *
3413 * Get attributes for incrementing the System Time Register SYSTIML/H at
3414 * the default base frequency, and set the cyclecounter shift value.
3415 **/
3416static s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3417{
3418 struct e1000_hw *hw = &adapter->hw;
3419 u32 incvalue, incperiod, shift;
3420
3421 /* Make sure clock is enabled on I217 before checking the frequency */
3422 if ((hw->mac.type == e1000_pch_lpt) &&
3423 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3424 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3425 u32 fextnvm7 = er32(FEXTNVM7);
3426
3427 if (!(fextnvm7 & (1 << 0))) {
3428 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3429 e1e_flush();
3430 }
3431 }
3432
3433 switch (hw->mac.type) {
3434 case e1000_pch2lan:
3435 case e1000_pch_lpt:
3436 /* On I217, the clock frequency is 25MHz or 96MHz as
3437 * indicated by the System Clock Frequency Indication
3438 */
3439 if ((hw->mac.type != e1000_pch_lpt) ||
3440 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3441 /* Stable 96MHz frequency */
3442 incperiod = INCPERIOD_96MHz;
3443 incvalue = INCVALUE_96MHz;
3444 shift = INCVALUE_SHIFT_96MHz;
3445 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3446 break;
3447 }
3448 /* fall-through */
3449 case e1000_82574:
3450 case e1000_82583:
3451 /* Stable 25MHz frequency */
3452 incperiod = INCPERIOD_25MHz;
3453 incvalue = INCVALUE_25MHz;
3454 shift = INCVALUE_SHIFT_25MHz;
3455 adapter->cc.shift = shift;
3456 break;
3457 default:
3458 return -EINVAL;
3459 }
3460
3461 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3462 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3463
3464 return 0;
3465}
3466
3467/**
3468 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3469 * @adapter: board private structure
3470 *
3471 * Outgoing time stamping can be enabled and disabled. Play nice and
3472 * disable it when requested, although it shouldn't cause any overhead
3473 * when no packet needs it. At most one packet in the queue may be
3474 * marked for time stamping, otherwise it would be impossible to tell
3475 * for sure to which packet the hardware time stamp belongs.
3476 *
3477 * Incoming time stamping has to be configured via the hardware filters.
3478 * Not all combinations are supported, in particular event type has to be
3479 * specified. Matching the kind of event packet is not supported, with the
3480 * exception of "all V2 events regardless of level 2 or 4".
3481 **/
3482static int e1000e_config_hwtstamp(struct e1000_adapter *adapter)
3483{
3484 struct e1000_hw *hw = &adapter->hw;
3485 struct hwtstamp_config *config = &adapter->hwtstamp_config;
3486 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3487 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3488 u32 regval;
3489 s32 ret_val;
3490
3491 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3492 return -EINVAL;
3493
3494 /* flags reserved for future extensions - must be zero */
3495 if (config->flags)
3496 return -EINVAL;
3497
3498 switch (config->tx_type) {
3499 case HWTSTAMP_TX_OFF:
3500 tsync_tx_ctl = 0;
3501 break;
3502 case HWTSTAMP_TX_ON:
3503 break;
3504 default:
3505 return -ERANGE;
3506 }
3507
3508 switch (config->rx_filter) {
3509 case HWTSTAMP_FILTER_NONE:
3510 tsync_rx_ctl = 0;
3511 break;
3512 case HWTSTAMP_FILTER_ALL:
3513 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3514 config->rx_filter = HWTSTAMP_FILTER_ALL;
3515 break;
3516 default:
3517 return -ERANGE;
3518 }
3519
3520 /* enable/disable Tx h/w time stamping */
3521 regval = er32(TSYNCTXCTL);
3522 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3523 regval |= tsync_tx_ctl;
3524 ew32(TSYNCTXCTL, regval);
3525 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3526 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3527 e_err("Timesync Tx Control register not set as expected\n");
3528 return -EAGAIN;
3529 }
3530
3531 /* enable/disable Rx h/w time stamping */
3532 regval = er32(TSYNCRXCTL);
3533 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3534 regval |= tsync_rx_ctl;
3535 ew32(TSYNCRXCTL, regval);
3536 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3537 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3538 (regval & (E1000_TSYNCRXCTL_ENABLED |
3539 E1000_TSYNCRXCTL_TYPE_MASK))) {
3540 e_err("Timesync Rx Control register not set as expected\n");
3541 return -EAGAIN;
3542 }
3543
3544 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3545 regval = er32(RXSTMPH);
3546 regval = er32(TXSTMPH);
3547
3548 /* Get and set the System Time Register SYSTIM base frequency */
3549 ret_val = e1000e_get_base_timinca(adapter, &regval);
3550 if (ret_val)
3551 return ret_val;
3552 ew32(TIMINCA, regval);
3553
3554 /* reset the ns time counter */
3555 timecounter_init(&adapter->tc, &adapter->cc,
3556 ktime_to_ns(ktime_get_real()));
3557
3558 return 0;
3559}
3560
bc7f75fa 3561/**
ad68076e 3562 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3563 * @adapter: private board structure
3564 **/
3565static void e1000_configure(struct e1000_adapter *adapter)
3566{
55aa6985
BA		 3567 struct e1000_ring *rx_ring = adapter->rx_ring;
3568
ef9b965a 3569 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3570
3571 e1000_restore_vlan(adapter);
cd791618 3572 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3573
3574 e1000_configure_tx(adapter);
70495a50
BA		 3575
3576 if (adapter->netdev->features & NETIF_F_RXHASH)
3577 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3578 e1000_setup_rctl(adapter);
3579 e1000_configure_rx(adapter);
55aa6985 3580 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3581}
3582
3583/**
3584 * e1000e_power_up_phy - restore link in case the phy was powered down
3585 * @adapter: address of board private structure
3586 *
3587 * The phy may be powered down to save power and turn off link when the
3588 * driver is unloaded and wake on lan is not enabled (among others)
3589 * *** this routine MUST be followed by a call to e1000e_reset ***
3590 **/
3591void e1000e_power_up_phy(struct e1000_adapter *adapter)
3592{
17f208de
BA		 3593 if (adapter->hw.phy.ops.power_up)
3594 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3595
3596 adapter->hw.mac.ops.setup_link(&adapter->hw);
3597}
3598
3599/**
3600 * e1000_power_down_phy - Power down the PHY
3601 *
17f208de
BA		 3602 * Power down the PHY so no link is implied when interface is down.
3603 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3604 */
3605static void e1000_power_down_phy(struct e1000_adapter *adapter)
3606{
bc7f75fa 3607 /* WoL is enabled */
23b66e2b 3608 if (adapter->wol)
bc7f75fa
AK		 3609 return;
3610
17f208de
BA		 3611 if (adapter->hw.phy.ops.power_down)
3612 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3613}
3614
3615/**
3616 * e1000e_reset - bring the hardware into a known good state
3617 *
3618 * This function boots the hardware and enables some settings that
3619 * require a configuration cycle of the hardware - those cannot be
3620 * set/changed during runtime. After reset the device needs to be
ad68076e 3621 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3622 */
3623void e1000e_reset(struct e1000_adapter *adapter)
3624{
3625 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3626 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3627 struct e1000_hw *hw = &adapter->hw;
3628 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3629 u32 pba = adapter->pba;
bc7f75fa
AK		 3630 u16 hwm;
3631
ad68076e 3632 /* reset Packet Buffer Allocation to default */
318a94d6 3633 ew32(PBA, pba);
df762464 3634
318a94d6 3635 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3636 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3637 * large enough to accommodate two full transmit packets,
3638 * rounded up to the next 1KB and expressed in KB. Likewise,
3639 * the Rx FIFO should be large enough to accommodate at least
3640 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3641 * expressed in KB.
3642 */
df762464 3643 pba = er32(PBA);
bc7f75fa 3644 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3645 tx_space = pba >> 16;
bc7f75fa 3646 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3647 pba &= 0xffff;
e921eb1a 3648 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3649 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3650 */
3651 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3652 sizeof(struct e1000_tx_desc) -
3653 ETH_FCS_LEN) * 2;
3654 min_tx_space = ALIGN(min_tx_space, 1024);
3655 min_tx_space >>= 10;
3656 /* software strips receive CRC, so leave room for it */
318a94d6 3657 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3658 min_rx_space = ALIGN(min_rx_space, 1024);
3659 min_rx_space >>= 10;
3660
e921eb1a 3661 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3662 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3663 * allocation, take space away from current Rx allocation
3664 */
df762464
AK		 3665 if ((tx_space < min_tx_space) &&
3666 ((min_tx_space - tx_space) < pba)) {
3667 pba -= min_tx_space - tx_space;
bc7f75fa 3668
e921eb1a 3669 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3670 * adjustment
ad68076e 3671 */
79d4e908 3672 if (pba < min_rx_space)
df762464 3673 pba = min_rx_space;
bc7f75fa 3674 }
df762464
AK		 3675
3676 ew32(PBA, pba);
bc7f75fa
AK		 3677 }
3678
e921eb1a 3679 /* flow control settings
ad68076e 3680 *
38eb394e 3681 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3682 * (or the size used for early receive) above it in the Rx FIFO.
3683 * Set it to the lower of:
3684 * - 90% of the Rx FIFO size, and
38eb394e 3685 * - the full Rx FIFO size minus one full frame
ad68076e 3686 */
d3738bb8
BA		 3687 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3688 fc->pause_time = 0xFFFF;
3689 else
3690 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3691 fc->send_xon = true;
d3738bb8
BA		 3692 fc->current_mode = fc->requested_mode;
3693
3694 switch (hw->mac.type) {
79d4e908
BA		 3695 case e1000_ich9lan:
3696 case e1000_ich10lan:
3697 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3698 pba = 14;
3699 ew32(PBA, pba);
3700 fc->high_water = 0x2800;
3701 fc->low_water = fc->high_water - 8;
3702 break;
3703 }
3704 /* fall-through */
d3738bb8 3705 default:
79d4e908
BA		 3706 hwm = min(((pba << 10) * 9 / 10),
3707 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3708
3709 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3710 fc->low_water = fc->high_water - 8;
3711 break;
3712 case e1000_pchlan:
e921eb1a 3713 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3714 * loads. If hangs persist, try disabling Tx flow control.
3715 */
3716 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3717 fc->high_water = 0x3500;
3718 fc->low_water = 0x1500;
3719 } else {
3720 fc->high_water = 0x5000;
3721 fc->low_water = 0x3000;
3722 }
a305595b 3723 fc->refresh_time = 0x1000;
d3738bb8
BA		 3724 break;
3725 case e1000_pch2lan:
2fbe4526 3726 case e1000_pch_lpt:
d3738bb8
BA		 3727 fc->high_water = 0x05C20;
3728 fc->low_water = 0x05048;
3729 fc->pause_time = 0x0650;
3730 fc->refresh_time = 0x0400;
828bac87
BA		 3731 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3732 pba = 14;
3733 ew32(PBA, pba);
3734 }
d3738bb8 3735 break;
38eb394e 3736 }
bc7f75fa 3737
e921eb1a 3738 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3739 * maximum size per Tx descriptor limited only to the transmit
3740 * allocation of the packet buffer minus 96 bytes with an upper
3741 * limit of 24KB due to receive synchronization limitations.
3742 */
3743 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3744 24 << 10);
3745
e921eb1a 3746 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3747 * fit in receive buffer.
828bac87
BA		 3748 */
3749 if (adapter->itr_setting & 0x3) {
79d4e908 3750 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3751 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3752 dev_info(&adapter->pdev->dev,
3753 "Interrupt Throttle Rate turned off\n");
3754 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3755 e1000e_write_itr(adapter, 0);
828bac87
BA		 3756 }
3757 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3758 dev_info(&adapter->pdev->dev,
3759 "Interrupt Throttle Rate turned on\n");
3760 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3761 adapter->itr = 20000;
22a4cca2 3762 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3763 }
3764 }
3765
bc7f75fa
AK		 3766 /* Allow time for pending master requests to run */
3767 mac->ops.reset_hw(hw);
97ac8cae 3768
e921eb1a 3769 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3770 * that the network interface is in control
3771 */
c43bc57e 3772 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3773 e1000e_get_hw_control(adapter);
97ac8cae 3774
bc7f75fa
AK		 3775 ew32(WUC, 0);
3776
3777 if (mac->ops.init_hw(hw))
44defeb3 3778 e_err("Hardware Error\n");
bc7f75fa
AK		 3779
3780 e1000_update_mng_vlan(adapter);
3781
3782 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3783 ew32(VET, ETH_P_8021Q);
3784
3785 e1000e_reset_adaptive(hw);
31dbe5b4 3786
b67e1913
BA		 3787 /* initialize systim and reset the ns time counter */
3788 e1000e_config_hwtstamp(adapter);
3789
31dbe5b4
BA		 3790 if (!netif_running(adapter->netdev) &&
3791 !test_bit(__E1000_TESTING, &adapter->state)) {
3792 e1000_power_down_phy(adapter);
3793 return;
3794 }
3795
bc7f75fa
AK		 3796 e1000_get_phy_info(hw);
3797
918d7197
BA		 3798 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3799 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3800 u16 phy_data = 0;
e921eb1a 3801 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3802 * the return value of this function because there is nothing
ad68076e
BA		 3803 * different we would do if it failed
3804 */
bc7f75fa
AK		 3805 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3806 phy_data &= ~IGP02E1000_PM_SPD;
3807 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3808 }
bc7f75fa
AK		 3809}
3810
3811int e1000e_up(struct e1000_adapter *adapter)
3812{
3813 struct e1000_hw *hw = &adapter->hw;
3814
3815 /* hardware has been reset, we need to reload some things */
3816 e1000_configure(adapter);
3817
3818 clear_bit(__E1000_DOWN, &adapter->state);
3819
4662e82b
BA		 3820 if (adapter->msix_entries)
3821 e1000_configure_msix(adapter);
bc7f75fa
AK		 3822 e1000_irq_enable(adapter);
3823
400484fa 3824 netif_start_queue(adapter->netdev);
4cb9be7a 3825
bc7f75fa 3826 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3827 if (adapter->msix_entries)
3828 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3829 else
3830 ew32(ICS, E1000_ICS_LSC);
3831
bc7f75fa
AK		 3832 return 0;
3833}
3834
713b3c9e
JB		 3835static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3836{
3837 struct e1000_hw *hw = &adapter->hw;
3838
3839 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3840 return;
3841
3842 /* flush pending descriptor writebacks to memory */
3843 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3844 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3845
3846 /* execute the writes immediately */
3847 e1e_flush();
bf03085f 3848
e921eb1a 3849 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3850 * write is successful
3851 */
3852 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3853 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3854
3855 /* execute the writes immediately */
3856 e1e_flush();
3857}
3858
67fd4fcb
JK		 3859static void e1000e_update_stats(struct e1000_adapter *adapter);
3860
bc7f75fa
AK		 3861void e1000e_down(struct e1000_adapter *adapter)
3862{
3863 struct net_device *netdev = adapter->netdev;
3864 struct e1000_hw *hw = &adapter->hw;
3865 u32 tctl, rctl;
3866
e921eb1a 3867 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3868 * reschedule our watchdog timer
3869 */
bc7f75fa
AK		 3870 set_bit(__E1000_DOWN, &adapter->state);
3871
3872 /* disable receives in the hardware */
3873 rctl = er32(RCTL);
7f99ae63
BA		 3874 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3875 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3876 /* flush and sleep below */
3877
4cb9be7a 3878 netif_stop_queue(netdev);
bc7f75fa
AK		 3879
3880 /* disable transmits in the hardware */
3881 tctl = er32(TCTL);
3882 tctl &= ~E1000_TCTL_EN;
3883 ew32(TCTL, tctl);
7f99ae63 3884
bc7f75fa
AK		 3885 /* flush both disables and wait for them to finish */
3886 e1e_flush();
1bba4386 3887 usleep_range(10000, 20000);
bc7f75fa 3888
bc7f75fa
AK		 3889 e1000_irq_disable(adapter);
3890
3891 del_timer_sync(&adapter->watchdog_timer);
3892 del_timer_sync(&adapter->phy_info_timer);
3893
bc7f75fa 3894 netif_carrier_off(netdev);
67fd4fcb
JK		 3895
3896 spin_lock(&adapter->stats64_lock);
3897 e1000e_update_stats(adapter);
3898 spin_unlock(&adapter->stats64_lock);
3899
400484fa 3900 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3901 e1000_clean_tx_ring(adapter->tx_ring);
3902 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3903
bc7f75fa
AK		 3904 adapter->link_speed = 0;
3905 adapter->link_duplex = 0;
3906
52cc3086
JK		 3907 if (!pci_channel_offline(adapter->pdev))
3908 e1000e_reset(adapter);
713b3c9e 3909
e921eb1a 3910 /* TODO: for power management, we could drop the link and
bc7f75fa
AK		 3911 * pci_disable_device here.
3912 */
3913}
3914
3915void e1000e_reinit_locked(struct e1000_adapter *adapter)
3916{
3917 might_sleep();
3918 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3919 usleep_range(1000, 2000);
bc7f75fa
AK		 3920 e1000e_down(adapter);
3921 e1000e_up(adapter);
3922 clear_bit(__E1000_RESETTING, &adapter->state);
3923}
3924
b67e1913
BA		 3925/**
3926 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
3927 * @cc: cyclecounter structure
3928 **/
3929static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
3930{
3931 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
3932 cc);
3933 struct e1000_hw *hw = &adapter->hw;
3934 cycle_t systim;
3935
3936 /* latch SYSTIMH on read of SYSTIML */
3937 systim = (cycle_t)er32(SYSTIML);
3938 systim |= (cycle_t)er32(SYSTIMH) << 32;
3939
3940 return systim;
3941}
3942
bc7f75fa
AK		 3943/**
3944 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3945 * @adapter: board private structure to initialize
3946 *
3947 * e1000_sw_init initializes the Adapter private data structure.
3948 * Fields are initialized based on PCI device information and
3949 * OS network device settings (MTU size).
3950 **/
9f9a12f8 3951static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 3952{
bc7f75fa
AK		 3953 struct net_device *netdev = adapter->netdev;
3954
3955 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3956 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3957 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3958 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3959 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3960 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3961
67fd4fcb
JK		 3962 spin_lock_init(&adapter->stats64_lock);
3963
4662e82b 3964 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3965
4662e82b
BA		 3966 if (e1000_alloc_queues(adapter))
3967 return -ENOMEM;
bc7f75fa 3968
b67e1913
BA		 3969 /* Setup hardware time stamping cyclecounter */
3970 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
3971 adapter->cc.read = e1000e_cyclecounter_read;
3972 adapter->cc.mask = CLOCKSOURCE_MASK(64);
3973 adapter->cc.mult = 1;
3974 /* cc.shift set in e1000e_get_base_tininca() */
3975
3976 spin_lock_init(&adapter->systim_lock);
3977 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
3978 }
3979
bc7f75fa 3980 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3981 e1000_irq_disable(adapter);
3982
bc7f75fa
AK		 3983 set_bit(__E1000_DOWN, &adapter->state);
3984 return 0;
bc7f75fa
AK		 3985}
3986
f8d59f78
BA		 3987/**
3988 * e1000_intr_msi_test - Interrupt Handler
3989 * @irq: interrupt number
3990 * @data: pointer to a network interface device structure
3991 **/
3992static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3993{
3994 struct net_device *netdev = data;
3995 struct e1000_adapter *adapter = netdev_priv(netdev);
3996 struct e1000_hw *hw = &adapter->hw;
3997 u32 icr = er32(ICR);
3998
3bb99fe2 3999 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4000 if (icr & E1000_ICR_RXSEQ) {
4001 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4002 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4003 * interrupt is handled.
4004 */
f8d59f78
BA		 4005 wmb();
4006 }
4007
4008 return IRQ_HANDLED;
4009}
4010
4011/**
4012 * e1000_test_msi_interrupt - Returns 0 for successful test
4013 * @adapter: board private struct
4014 *
4015 * code flow taken from tg3.c
4016 **/
4017static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4018{
4019 struct net_device *netdev = adapter->netdev;
4020 struct e1000_hw *hw = &adapter->hw;
4021 int err;
4022
4023 /* poll_enable hasn't been called yet, so don't need disable */
4024 /* clear any pending events */
4025 er32(ICR);
4026
4027 /* free the real vector and request a test handler */
4028 e1000_free_irq(adapter);
4662e82b 4029 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4030
4031 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4032 * MSI irq handler will unset this flag
4033 */
f8d59f78
BA		 4034 adapter->flags |= FLAG_MSI_TEST_FAILED;
4035
4036 err = pci_enable_msi(adapter->pdev);
4037 if (err)
4038 goto msi_test_failed;
4039
a0607fd3 4040 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4041 netdev->name, netdev);
4042 if (err) {
4043 pci_disable_msi(adapter->pdev);
4044 goto msi_test_failed;
4045 }
4046
e921eb1a 4047 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4048 * interrupt.
4049 */
f8d59f78
BA		 4050 wmb();
4051
4052 e1000_irq_enable(adapter);
4053
4054 /* fire an unusual interrupt on the test handler */
4055 ew32(ICS, E1000_ICS_RXSEQ);
4056 e1e_flush();
569a3aff 4057 msleep(100);
f8d59f78
BA		 4058
4059 e1000_irq_disable(adapter);
4060
bc76329d 4061 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4062
4063 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4064 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4065 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4066 } else {
068e8a30 4067 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4068 }
f8d59f78
BA		 4069
4070 free_irq(adapter->pdev->irq, netdev);
4071 pci_disable_msi(adapter->pdev);
4072
f8d59f78 4073msi_test_failed:
4662e82b 4074 e1000e_set_interrupt_capability(adapter);
068e8a30 4075 return e1000_request_irq(adapter);
f8d59f78
BA		 4076}
4077
4078/**
4079 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4080 * @adapter: board private struct
4081 *
4082 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4083 **/
4084static int e1000_test_msi(struct e1000_adapter *adapter)
4085{
4086 int err;
4087 u16 pci_cmd;
4088
4089 if (!(adapter->flags & FLAG_MSI_ENABLED))
4090 return 0;
4091
4092 /* disable SERR in case the MSI write causes a master abort */
4093 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4094 if (pci_cmd & PCI_COMMAND_SERR)
4095 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4096 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4097
4098 err = e1000_test_msi_interrupt(adapter);
4099
36f2407f
DN		 4100 /* re-enable SERR */
4101 if (pci_cmd & PCI_COMMAND_SERR) {
4102 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4103 pci_cmd |= PCI_COMMAND_SERR;
4104 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4105 }
f8d59f78 4106
f8d59f78
BA		 4107 return err;
4108}
4109
bc7f75fa
AK		 4110/**
4111 * e1000_open - Called when a network interface is made active
4112 * @netdev: network interface device structure
4113 *
4114 * Returns 0 on success, negative value on failure
4115 *
4116 * The open entry point is called when a network interface is made
4117 * active by the system (IFF_UP). At this point all resources needed
4118 * for transmit and receive operations are allocated, the interrupt
4119 * handler is registered with the OS, the watchdog timer is started,
4120 * and the stack is notified that the interface is ready.
4121 **/
4122static int e1000_open(struct net_device *netdev)
4123{
4124 struct e1000_adapter *adapter = netdev_priv(netdev);
4125 struct e1000_hw *hw = &adapter->hw;
23606cf5 4126 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4127 int err;
4128
4129 /* disallow open during test */
4130 if (test_bit(__E1000_TESTING, &adapter->state))
4131 return -EBUSY;
4132
23606cf5
RW		 4133 pm_runtime_get_sync(&pdev->dev);
4134
9c563d20
JB		 4135 netif_carrier_off(netdev);
4136
bc7f75fa 4137 /* allocate transmit descriptors */
55aa6985 4138 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4139 if (err)
4140 goto err_setup_tx;
4141
4142 /* allocate receive descriptors */
55aa6985 4143 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4144 if (err)
4145 goto err_setup_rx;
4146
e921eb1a 4147 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4148 * interface is now open and reset the part to a known state.
4149 */
4150 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4151 e1000e_get_hw_control(adapter);
11b08be8
BA		 4152 e1000e_reset(adapter);
4153 }
4154
bc7f75fa
AK		 4155 e1000e_power_up_phy(adapter);
4156
4157 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4158 if ((adapter->hw.mng_cookie.status &
4159 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4160 e1000_update_mng_vlan(adapter);
4161
79d4e908
BA		 4162 /* DMA latency requirement to workaround jumbo issue */
4163 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 4164 pm_qos_add_request(&adapter->netdev->pm_qos_req,
4165 PM_QOS_CPU_DMA_LATENCY,
4166 PM_QOS_DEFAULT_VALUE);
c128ec29 4167
e921eb1a 4168 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4169 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4170 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4171 * clean_rx handler before we do so.
4172 */
bc7f75fa
AK		 4173 e1000_configure(adapter);
4174
4175 err = e1000_request_irq(adapter);
4176 if (err)
4177 goto err_req_irq;
4178
e921eb1a 4179 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4180 * ignore e1000e MSI messages, which means we need to test our MSI
4181 * interrupt now
4182 */
4662e82b 4183 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4184 err = e1000_test_msi(adapter);
4185 if (err) {
4186 e_err("Interrupt allocation failed\n");
4187 goto err_req_irq;
4188 }
4189 }
4190
bc7f75fa
AK		 4191 /* From here on the code is the same as e1000e_up() */
4192 clear_bit(__E1000_DOWN, &adapter->state);
4193
4194 napi_enable(&adapter->napi);
4195
4196 e1000_irq_enable(adapter);
4197
09357b00 4198 adapter->tx_hang_recheck = false;
4cb9be7a 4199 netif_start_queue(netdev);
d55b53ff 4200
23606cf5
RW		 4201 adapter->idle_check = true;
4202 pm_runtime_put(&pdev->dev);
4203
bc7f75fa 4204 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4205 if (adapter->msix_entries)
4206 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4207 else
4208 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4209
4210 return 0;
4211
4212err_req_irq:
31dbe5b4 4213 e1000e_release_hw_control(adapter);
bc7f75fa 4214 e1000_power_down_phy(adapter);
55aa6985 4215 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4216err_setup_rx:
55aa6985 4217 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4218err_setup_tx:
4219 e1000e_reset(adapter);
23606cf5 4220 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4221
4222 return err;
4223}
4224
4225/**
4226 * e1000_close - Disables a network interface
4227 * @netdev: network interface device structure
4228 *
4229 * Returns 0, this is not allowed to fail
4230 *
4231 * The close entry point is called when an interface is de-activated
4232 * by the OS. The hardware is still under the drivers control, but
4233 * needs to be disabled. A global MAC reset is issued to stop the
4234 * hardware, and all transmit and receive resources are freed.
4235 **/
4236static int e1000_close(struct net_device *netdev)
4237{
4238 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4239 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4240 int count = E1000_CHECK_RESET_COUNT;
4241
4242 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4243 usleep_range(10000, 20000);
bc7f75fa
AK		 4244
4245 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4246
4247 pm_runtime_get_sync(&pdev->dev);
4248
5f4a780d
BA		 4249 napi_disable(&adapter->napi);
4250
23606cf5
RW		 4251 if (!test_bit(__E1000_DOWN, &adapter->state)) {
4252 e1000e_down(adapter);
4253 e1000_free_irq(adapter);
4254 }
bc7f75fa 4255 e1000_power_down_phy(adapter);
bc7f75fa 4256
55aa6985
BA		 4257 e1000e_free_tx_resources(adapter->tx_ring);
4258 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4259
e921eb1a 4260 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4261 * the same ID is registered on the host OS (let 8021q kill it)
4262 */
86d70e53
JK		 4263 if (adapter->hw.mng_cookie.status &
4264 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 4265 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4266
e921eb1a 4267 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4268 * interface is now closed
4269 */
31dbe5b4
BA		 4270 if ((adapter->flags & FLAG_HAS_AMT) &&
4271 !test_bit(__E1000_TESTING, &adapter->state))
4272 e1000e_release_hw_control(adapter);
bc7f75fa 4273
79d4e908 4274 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4275 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4276
23606cf5
RW		 4277 pm_runtime_put_sync(&pdev->dev);
4278
bc7f75fa
AK		 4279 return 0;
4280}
4281/**
4282 * e1000_set_mac - Change the Ethernet Address of the NIC
4283 * @netdev: network interface device structure
4284 * @p: pointer to an address structure
4285 *
4286 * Returns 0 on success, negative on failure
4287 **/
4288static int e1000_set_mac(struct net_device *netdev, void *p)
4289{
4290 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4291 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4292 struct sockaddr *addr = p;
4293
4294 if (!is_valid_ether_addr(addr->sa_data))
4295 return -EADDRNOTAVAIL;
4296
4297 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4298 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4299
69e1e019 4300 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4301
4302 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4303 /* activate the work around */
4304 e1000e_set_laa_state_82571(&adapter->hw, 1);
4305
e921eb1a 4306 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4307 * between the time RAR[0] gets clobbered and the time it
4308 * gets fixed (in e1000_watchdog), the actual LAA is in one
4309 * of the RARs and no incoming packets directed to this port
4310 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4311 * RAR[14]
4312 */
69e1e019
BA		 4313 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4314 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4315 }
4316
4317 return 0;
4318}
4319
a8f88ff5
JB		 4320/**
4321 * e1000e_update_phy_task - work thread to update phy
4322 * @work: pointer to our work struct
4323 *
4324 * this worker thread exists because we must acquire a
4325 * semaphore to read the phy, which we could msleep while
4326 * waiting for it, and we can't msleep in a timer.
4327 **/
4328static void e1000e_update_phy_task(struct work_struct *work)
4329{
4330 struct e1000_adapter *adapter = container_of(work,
4331 struct e1000_adapter, update_phy_task);
615b32af
JB		 4332
4333 if (test_bit(__E1000_DOWN, &adapter->state))
4334 return;
4335
a8f88ff5
JB		 4336 e1000_get_phy_info(&adapter->hw);
4337}
4338
e921eb1a
BA		 4339/**
4340 * e1000_update_phy_info - timre call-back to update PHY info
4341 * @data: pointer to adapter cast into an unsigned long
4342 *
ad68076e
BA		 4343 * Need to wait a few seconds after link up to get diagnostic information from
4344 * the phy
e921eb1a 4345 **/
bc7f75fa
AK		 4346static void e1000_update_phy_info(unsigned long data)
4347{
4348 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4349
4350 if (test_bit(__E1000_DOWN, &adapter->state))
4351 return;
4352
a8f88ff5 4353 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4354}
4355
8c7bbb92
BA		 4356/**
4357 * e1000e_update_phy_stats - Update the PHY statistics counters
4358 * @adapter: board private structure
2b6b168d
BA		 4359 *
4360 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4361 **/
4362static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4363{
4364 struct e1000_hw *hw = &adapter->hw;
4365 s32 ret_val;
4366 u16 phy_data;
4367
4368 ret_val = hw->phy.ops.acquire(hw);
4369 if (ret_val)
4370 return;
4371
e921eb1a 4372 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4373 * If not, set to the page with the PHY status registers.
4374 */
2b6b168d 4375 hw->phy.addr = 1;
8c7bbb92
BA		 4376 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4377 &phy_data);
4378 if (ret_val)
4379 goto release;
2b6b168d
BA		 4380 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4381 ret_val = hw->phy.ops.set_page(hw,
4382 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4383 if (ret_val)
4384 goto release;
4385 }
4386
8c7bbb92 4387 /* Single Collision Count */
2b6b168d
BA		 4388 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4389 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4390 if (!ret_val)
4391 adapter->stats.scc += phy_data;
4392
4393 /* Excessive Collision Count */
2b6b168d
BA		 4394 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4395 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4396 if (!ret_val)
4397 adapter->stats.ecol += phy_data;
4398
4399 /* Multiple Collision Count */
2b6b168d
BA		 4400 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4401 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4402 if (!ret_val)
4403 adapter->stats.mcc += phy_data;
4404
4405 /* Late Collision Count */
2b6b168d
BA		 4406 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4407 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4408 if (!ret_val)
4409 adapter->stats.latecol += phy_data;
4410
4411 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4412 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4413 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4414 if (!ret_val)
4415 hw->mac.collision_delta = phy_data;
4416
4417 /* Defer Count */
2b6b168d
BA		 4418 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4419 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4420 if (!ret_val)
4421 adapter->stats.dc += phy_data;
4422
4423 /* Transmit with no CRS */
2b6b168d
BA		 4424 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4425 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4426 if (!ret_val)
4427 adapter->stats.tncrs += phy_data;
4428
4429release:
4430 hw->phy.ops.release(hw);
4431}
4432
bc7f75fa
AK		 4433/**
4434 * e1000e_update_stats - Update the board statistics counters
4435 * @adapter: board private structure
4436 **/
67fd4fcb 4437static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4438{
7274c20f 4439 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4440 struct e1000_hw *hw = &adapter->hw;
4441 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4442
e921eb1a 4443 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4444 * connection is down.
4445 */
4446 if (adapter->link_speed == 0)
4447 return;
4448 if (pci_channel_offline(pdev))
4449 return;
4450
bc7f75fa
AK		 4451 adapter->stats.crcerrs += er32(CRCERRS);
4452 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4453 adapter->stats.gorc += er32(GORCL);
4454 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4455 adapter->stats.bprc += er32(BPRC);
4456 adapter->stats.mprc += er32(MPRC);
4457 adapter->stats.roc += er32(ROC);
4458
bc7f75fa 4459 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4460
4461 /* Half-duplex statistics */
4462 if (adapter->link_duplex == HALF_DUPLEX) {
4463 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4464 e1000e_update_phy_stats(adapter);
4465 } else {
4466 adapter->stats.scc += er32(SCC);
4467 adapter->stats.ecol += er32(ECOL);
4468 adapter->stats.mcc += er32(MCC);
4469 adapter->stats.latecol += er32(LATECOL);
4470 adapter->stats.dc += er32(DC);
4471
4472 hw->mac.collision_delta = er32(COLC);
4473
4474 if ((hw->mac.type != e1000_82574) &&
4475 (hw->mac.type != e1000_82583))
4476 adapter->stats.tncrs += er32(TNCRS);
4477 }
4478 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4479 }
8c7bbb92 4480
bc7f75fa
AK		 4481 adapter->stats.xonrxc += er32(XONRXC);
4482 adapter->stats.xontxc += er32(XONTXC);
4483 adapter->stats.xoffrxc += er32(XOFFRXC);
4484 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4485 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4486 adapter->stats.gotc += er32(GOTCL);
4487 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4488 adapter->stats.rnbc += er32(RNBC);
4489 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4490
4491 adapter->stats.mptc += er32(MPTC);
4492 adapter->stats.bptc += er32(BPTC);
4493
4494 /* used for adaptive IFS */
4495
4496 hw->mac.tx_packet_delta = er32(TPT);
4497 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4498
4499 adapter->stats.algnerrc += er32(ALGNERRC);
4500 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4501 adapter->stats.cexterr += er32(CEXTERR);
4502 adapter->stats.tsctc += er32(TSCTC);
4503 adapter->stats.tsctfc += er32(TSCTFC);
4504
bc7f75fa 4505 /* Fill out the OS statistics structure */
7274c20f
AK		 4506 netdev->stats.multicast = adapter->stats.mprc;
4507 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4508
4509 /* Rx Errors */
4510
e921eb1a 4511 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4512 * our own version based on RUC and ROC
4513 */
7274c20f 4514 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4515 adapter->stats.crcerrs + adapter->stats.algnerrc +
4516 adapter->stats.ruc + adapter->stats.roc +
4517 adapter->stats.cexterr;
7274c20f 4518 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4519 adapter->stats.roc;
7274c20f
AK		 4520 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4521 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4522 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4523
4524 /* Tx Errors */
7274c20f 4525 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4526 adapter->stats.latecol;
7274c20f
AK		 4527 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4528 netdev->stats.tx_window_errors = adapter->stats.latecol;
4529 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4530
4531 /* Tx Dropped needs to be maintained elsewhere */
4532
bc7f75fa
AK		 4533 /* Management Stats */
4534 adapter->stats.mgptc += er32(MGTPTC);
4535 adapter->stats.mgprc += er32(MGTPRC);
4536 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4537}
4538
7c25769f
BA		 4539/**
4540 * e1000_phy_read_status - Update the PHY register status snapshot
4541 * @adapter: board private structure
4542 **/
4543static void e1000_phy_read_status(struct e1000_adapter *adapter)
4544{
4545 struct e1000_hw *hw = &adapter->hw;
4546 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4547
4548 if ((er32(STATUS) & E1000_STATUS_LU) &&
4549 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4550 int ret_val;
4551
7c25769f
BA		 4552 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4553 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4554 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4555 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4556 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4557 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4558 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4559 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4560 if (ret_val)
44defeb3 4561 e_warn("Error reading PHY register\n");
7c25769f 4562 } else {
e921eb1a 4563 /* Do not read PHY registers if link is not up
7c25769f
BA		 4564 * Set values to typical power-on defaults
4565 */
4566 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4567 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4568 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4569 BMSR_ERCAP);
4570 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4571 ADVERTISE_ALL | ADVERTISE_CSMA);
4572 phy->lpa = 0;
4573 phy->expansion = EXPANSION_ENABLENPAGE;
4574 phy->ctrl1000 = ADVERTISE_1000FULL;
4575 phy->stat1000 = 0;
4576 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4577 }
7c25769f
BA		 4578}
4579
bc7f75fa
AK		 4580static void e1000_print_link_info(struct e1000_adapter *adapter)
4581{
bc7f75fa
AK		 4582 struct e1000_hw *hw = &adapter->hw;
4583 u32 ctrl = er32(CTRL);
4584
8f12fe86 4585 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4586 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4587 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4588 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4589 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4590 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4591 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4592}
4593
0c6bdb30 4594static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4595{
4596 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4597 bool link_active = false;
318a94d6
JK		 4598 s32 ret_val = 0;
4599
e921eb1a 4600 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4601 * Rx sequence error interrupt. get_link_status will stay
4602 * false until the check_for_link establishes link
4603 * for copper adapters ONLY
4604 */
4605 switch (hw->phy.media_type) {
4606 case e1000_media_type_copper:
4607 if (hw->mac.get_link_status) {
4608 ret_val = hw->mac.ops.check_for_link(hw);
4609 link_active = !hw->mac.get_link_status;
4610 } else {
3db1cd5c 4611 link_active = true;
318a94d6
JK		 4612 }
4613 break;
4614 case e1000_media_type_fiber:
4615 ret_val = hw->mac.ops.check_for_link(hw);
4616 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4617 break;
4618 case e1000_media_type_internal_serdes:
4619 ret_val = hw->mac.ops.check_for_link(hw);
4620 link_active = adapter->hw.mac.serdes_has_link;
4621 break;
4622 default:
4623 case e1000_media_type_unknown:
4624 break;
4625 }
4626
4627 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4628 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4629 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4630 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4631 }
4632
4633 return link_active;
4634}
4635
4636static void e1000e_enable_receives(struct e1000_adapter *adapter)
4637{
4638 /* make sure the receive unit is started */
4639 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4640 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4641 struct e1000_hw *hw = &adapter->hw;
4642 u32 rctl = er32(RCTL);
4643 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4644 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4645 }
4646}
4647
ff10e13c
CW		 4648static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4649{
4650 struct e1000_hw *hw = &adapter->hw;
4651
e921eb1a 4652 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4653 * for hung state and reset, if two calls return true
4654 */
4655 if (e1000_check_phy_82574(hw))
4656 adapter->phy_hang_count++;
4657 else
4658 adapter->phy_hang_count = 0;
4659
4660 if (adapter->phy_hang_count > 1) {
4661 adapter->phy_hang_count = 0;
4662 schedule_work(&adapter->reset_task);
4663 }
4664}
4665
bc7f75fa
AK		 4666/**
4667 * e1000_watchdog - Timer Call-back
4668 * @data: pointer to adapter cast into an unsigned long
4669 **/
4670static void e1000_watchdog(unsigned long data)
4671{
4672 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4673
4674 /* Do the rest outside of interrupt context */
4675 schedule_work(&adapter->watchdog_task);
4676
4677 /* TODO: make this use queue_delayed_work() */
4678}
4679
4680static void e1000_watchdog_task(struct work_struct *work)
4681{
4682 struct e1000_adapter *adapter = container_of(work,
4683 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4684 struct net_device *netdev = adapter->netdev;
4685 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4686 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4687 struct e1000_ring *tx_ring = adapter->tx_ring;
4688 struct e1000_hw *hw = &adapter->hw;
4689 u32 link, tctl;
bc7f75fa 4690
615b32af
JB		 4691 if (test_bit(__E1000_DOWN, &adapter->state))
4692 return;
4693
b405e8df 4694 link = e1000e_has_link(adapter);
318a94d6 4695 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4696 /* Cancel scheduled suspend requests. */
4697 pm_runtime_resume(netdev->dev.parent);
4698
318a94d6 4699 e1000e_enable_receives(adapter);
bc7f75fa 4700 goto link_up;
bc7f75fa
AK		 4701 }
4702
4703 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4704 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4705 e1000_update_mng_vlan(adapter);
4706
bc7f75fa
AK		 4707 if (link) {
4708 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4709 bool txb2b = true;
23606cf5
RW		 4710
4711 /* Cancel scheduled suspend requests. */
4712 pm_runtime_resume(netdev->dev.parent);
4713
318a94d6 4714 /* update snapshot of PHY registers on LSC */
7c25769f 4715 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4716 mac->ops.get_link_up_info(&adapter->hw,
4717 &adapter->link_speed,
4718 &adapter->link_duplex);
4719 e1000_print_link_info(adapter);
e921eb1a 4720 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4721 * if link has autonegotiated at 10/100 half
4722 */
4723 if ((hw->phy.type == e1000_phy_igp_3 ||
4724 hw->phy.type == e1000_phy_bm) &&
4725 (hw->mac.autoneg == true) &&
4726 (adapter->link_speed == SPEED_10 ||
4727 adapter->link_speed == SPEED_100) &&
4728 (adapter->link_duplex == HALF_DUPLEX)) {
4729 u16 autoneg_exp;
4730
4731 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4732
4733 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4734 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4735 }
4736
f49c57e1 4737 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4738 adapter->tx_timeout_factor = 1;
4739 switch (adapter->link_speed) {
4740 case SPEED_10:
3db1cd5c 4741 txb2b = false;
10f1b492 4742 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4743 break;
4744 case SPEED_100:
3db1cd5c 4745 txb2b = false;
4c86e0b9 4746 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4747 break;
4748 }
4749
e921eb1a 4750 /* workaround: re-program speed mode bit after
ad68076e
BA		 4751 * link-up event
4752 */
bc7f75fa
AK		 4753 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4754 !txb2b) {
4755 u32 tarc0;
e9ec2c0f 4756 tarc0 = er32(TARC(0));
bc7f75fa 4757 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4758 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4759 }
4760
e921eb1a 4761 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4762 * some hardware issues
4763 */
bc7f75fa
AK		 4764 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4765 switch (adapter->link_speed) {
4766 case SPEED_10:
4767 case SPEED_100:
44defeb3 4768 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4769 netdev->features &= ~NETIF_F_TSO;
4770 netdev->features &= ~NETIF_F_TSO6;
4771 break;
4772 case SPEED_1000:
4773 netdev->features |= NETIF_F_TSO;
4774 netdev->features |= NETIF_F_TSO6;
4775 break;
4776 default:
4777 /* oops */
4778 break;
4779 }
4780 }
4781
e921eb1a 4782 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4783 * after setting TARC(0)
4784 */
bc7f75fa
AK		 4785 tctl = er32(TCTL);
4786 tctl |= E1000_TCTL_EN;
4787 ew32(TCTL, tctl);
4788
e921eb1a 4789 /* Perform any post-link-up configuration before
75eb0fad
BA		 4790 * reporting link up.
4791 */
4792 if (phy->ops.cfg_on_link_up)
4793 phy->ops.cfg_on_link_up(hw);
4794
bc7f75fa 4795 netif_carrier_on(netdev);
bc7f75fa
AK		 4796
4797 if (!test_bit(__E1000_DOWN, &adapter->state))
4798 mod_timer(&adapter->phy_info_timer,
4799 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4800 }
4801 } else {
4802 if (netif_carrier_ok(netdev)) {
4803 adapter->link_speed = 0;
4804 adapter->link_duplex = 0;
8f12fe86 4805 /* Link status message must follow this format */
7dbc1672 4806 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4807 netif_carrier_off(netdev);
bc7f75fa
AK		 4808 if (!test_bit(__E1000_DOWN, &adapter->state))
4809 mod_timer(&adapter->phy_info_timer,
4810 round_jiffies(jiffies + 2 * HZ));
4811
12d43f7d
BA		 4812 /* The link is lost so the controller stops DMA.
4813 * If there is queued Tx work that cannot be done
4814 * or if on an 8000ES2LAN which requires a Rx packet
4815 * buffer work-around on link down event, reset the
4816 * controller to flush the Tx/Rx packet buffers.
4817 * (Do the reset outside of interrupt context).
4818 */
4819 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4820 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4821 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4822 else
4823 pm_schedule_suspend(netdev->dev.parent,
4824 LINK_TIMEOUT);
bc7f75fa
AK		 4825 }
4826 }
4827
4828link_up:
67fd4fcb 4829 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4830 e1000e_update_stats(adapter);
4831
4832 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4833 adapter->tpt_old = adapter->stats.tpt;
4834 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4835 adapter->colc_old = adapter->stats.colc;
4836
7c25769f
BA		 4837 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4838 adapter->gorc_old = adapter->stats.gorc;
4839 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4840 adapter->gotc_old = adapter->stats.gotc;
2084b114 4841 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4842
12d43f7d 4843 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4844 schedule_work(&adapter->reset_task);
4845 /* return immediately since reset is imminent */
4846 return;
bc7f75fa
AK		 4847 }
4848
12d43f7d
BA		 4849 e1000e_update_adaptive(&adapter->hw);
4850
eab2abf5
JB		 4851 /* Simple mode for Interrupt Throttle Rate (ITR) */
4852 if (adapter->itr_setting == 4) {
e921eb1a 4853 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 4854 * Total asymmetrical Tx or Rx gets ITR=8000;
4855 * everyone else is between 2000-8000.
4856 */
4857 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4858 u32 dif = (adapter->gotc > adapter->gorc ?
4859 adapter->gotc - adapter->gorc :
4860 adapter->gorc - adapter->gotc) / 10000;
4861 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4862
22a4cca2 4863 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 4864 }
4865
ad68076e 4866 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4867 if (adapter->msix_entries)
4868 ew32(ICS, adapter->rx_ring->ims_val);
4869 else
4870 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4871
713b3c9e
JB		 4872 /* flush pending descriptors to memory before detecting Tx hang */
4873 e1000e_flush_descriptors(adapter);
4874
bc7f75fa 4875 /* Force detection of hung controller every watchdog period */
3db1cd5c 4876 adapter->detect_tx_hung = true;
bc7f75fa 4877
e921eb1a 4878 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 4879 * reset from the other port. Set the appropriate LAA in RAR[0]
4880 */
bc7f75fa 4881 if (e1000e_get_laa_state_82571(hw))
69e1e019 4882 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4883
ff10e13c
CW		 4884 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4885 e1000e_check_82574_phy_workaround(adapter);
4886
b67e1913
BA		 4887 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
4888 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
4889 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
4890 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
4891 er32(RXSTMPH);
4892 adapter->rx_hwtstamp_cleared++;
4893 } else {
4894 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
4895 }
4896 }
4897
bc7f75fa
AK		 4898 /* Reset the timer */
4899 if (!test_bit(__E1000_DOWN, &adapter->state))
4900 mod_timer(&adapter->watchdog_timer,
4901 round_jiffies(jiffies + 2 * HZ));
4902}
4903
4904#define E1000_TX_FLAGS_CSUM 0x00000001
4905#define E1000_TX_FLAGS_VLAN 0x00000002
4906#define E1000_TX_FLAGS_TSO 0x00000004
4907#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4908#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 4909#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 4910#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4911#define E1000_TX_FLAGS_VLAN_SHIFT 16
4912
55aa6985 4913static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4914{
bc7f75fa
AK		 4915 struct e1000_context_desc *context_desc;
4916 struct e1000_buffer *buffer_info;
4917 unsigned int i;
4918 u32 cmd_length = 0;
70443ae9 4919 u16 ipcse = 0, mss;
bc7f75fa 4920 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4921
3d5e33c9
BA		 4922 if (!skb_is_gso(skb))
4923 return 0;
bc7f75fa 4924
3d5e33c9 4925 if (skb_header_cloned(skb)) {
90da0669
BA		 4926 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4927
3d5e33c9
BA		 4928 if (err)
4929 return err;
bc7f75fa
AK		 4930 }
4931
3d5e33c9
BA		 4932 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4933 mss = skb_shinfo(skb)->gso_size;
4934 if (skb->protocol == htons(ETH_P_IP)) {
4935 struct iphdr *iph = ip_hdr(skb);
4936 iph->tot_len = 0;
4937 iph->check = 0;
4938 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4939 0, IPPROTO_TCP, 0);
4940 cmd_length = E1000_TXD_CMD_IP;
4941 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4942 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4943 ipv6_hdr(skb)->payload_len = 0;
4944 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4945 &ipv6_hdr(skb)->daddr,
4946 0, IPPROTO_TCP, 0);
4947 ipcse = 0;
4948 }
4949 ipcss = skb_network_offset(skb);
4950 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4951 tucss = skb_transport_offset(skb);
4952 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 4953
4954 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4955 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4956
4957 i = tx_ring->next_to_use;
4958 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4959 buffer_info = &tx_ring->buffer_info[i];
4960
4961 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4962 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4963 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4964 context_desc->upper_setup.tcp_fields.tucss = tucss;
4965 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 4966 context_desc->upper_setup.tcp_fields.tucse = 0;
3d5e33c9
BA		 4967 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4968 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4969 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4970
4971 buffer_info->time_stamp = jiffies;
4972 buffer_info->next_to_watch = i;
4973
4974 i++;
4975 if (i == tx_ring->count)
4976 i = 0;
4977 tx_ring->next_to_use = i;
4978
4979 return 1;
bc7f75fa
AK		 4980}
4981
55aa6985 4982static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4983{
55aa6985 4984 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4985 struct e1000_context_desc *context_desc;
4986 struct e1000_buffer *buffer_info;
4987 unsigned int i;
4988 u8 css;
af807c82 4989 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4990 __be16 protocol;
bc7f75fa 4991
af807c82
DG		 4992 if (skb->ip_summed != CHECKSUM_PARTIAL)
4993 return 0;
bc7f75fa 4994
5f66f208
AJ		 4995 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4996 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4997 else
4998 protocol = skb->protocol;
4999
3f518390 5000 switch (protocol) {
09640e63 5001 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5002 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5003 cmd_len |= E1000_TXD_CMD_TCP;
5004 break;
09640e63 5005 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5006 /* XXX not handling all IPV6 headers */
5007 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5008 cmd_len |= E1000_TXD_CMD_TCP;
5009 break;
5010 default:
5011 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5012 e_warn("checksum_partial proto=%x!\n",
5013 be16_to_cpu(protocol));
af807c82 5014 break;
bc7f75fa
AK		 5015 }
5016
0d0b1672 5017 css = skb_checksum_start_offset(skb);
af807c82
DG		 5018
5019 i = tx_ring->next_to_use;
5020 buffer_info = &tx_ring->buffer_info[i];
5021 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5022
5023 context_desc->lower_setup.ip_config = 0;
5024 context_desc->upper_setup.tcp_fields.tucss = css;
5025 context_desc->upper_setup.tcp_fields.tucso =
5026 css + skb->csum_offset;
5027 context_desc->upper_setup.tcp_fields.tucse = 0;
5028 context_desc->tcp_seg_setup.data = 0;
5029 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5030
5031 buffer_info->time_stamp = jiffies;
5032 buffer_info->next_to_watch = i;
5033
5034 i++;
5035 if (i == tx_ring->count)
5036 i = 0;
5037 tx_ring->next_to_use = i;
5038
5039 return 1;
bc7f75fa
AK		 5040}
5041
55aa6985
BA		 5042static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5043 unsigned int first, unsigned int max_per_txd,
d821a4c4 5044 unsigned int nr_frags)
bc7f75fa 5045{
55aa6985 5046 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5047 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5048 struct e1000_buffer *buffer_info;
8ddc951c 5049 unsigned int len = skb_headlen(skb);
03b1320d 5050 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5051 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5052
5053 i = tx_ring->next_to_use;
5054
5055 while (len) {
1b7719c4 5056 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5057 size = min(len, max_per_txd);
5058
bc7f75fa 5059 buffer_info->length = size;
bc7f75fa 5060 buffer_info->time_stamp = jiffies;
bc7f75fa 5061 buffer_info->next_to_watch = i;
0be3f55f
NN		 5062 buffer_info->dma = dma_map_single(&pdev->dev,
5063 skb->data + offset,
af667a29 5064 size, DMA_TO_DEVICE);
03b1320d 5065 buffer_info->mapped_as_page = false;
0be3f55f 5066 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5067 goto dma_error;
bc7f75fa
AK		 5068
5069 len -= size;
5070 offset += size;
03b1320d 5071 count++;
1b7719c4
AD		 5072
5073 if (len) {
5074 i++;
5075 if (i == tx_ring->count)
5076 i = 0;
5077 }
bc7f75fa
AK		 5078 }
5079
5080 for (f = 0; f < nr_frags; f++) {
9e903e08 5081 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5082
5083 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5084 len = skb_frag_size(frag);
877749bf 5085 offset = 0;
bc7f75fa
AK		 5086
5087 while (len) {
1b7719c4
AD		 5088 i++;
5089 if (i == tx_ring->count)
5090 i = 0;
5091
bc7f75fa
AK		 5092 buffer_info = &tx_ring->buffer_info[i];
5093 size = min(len, max_per_txd);
bc7f75fa
AK		 5094
5095 buffer_info->length = size;
5096 buffer_info->time_stamp = jiffies;
bc7f75fa 5097 buffer_info->next_to_watch = i;
877749bf
IC		 5098 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5099 offset, size, DMA_TO_DEVICE);
03b1320d 5100 buffer_info->mapped_as_page = true;
0be3f55f 5101 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5102 goto dma_error;
bc7f75fa
AK		 5103
5104 len -= size;
5105 offset += size;
5106 count++;
bc7f75fa
AK		 5107 }
5108 }
5109
af667a29 5110 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5111 /* multiply data chunks by size of headers */
5112 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5113
bc7f75fa 5114 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5115 tx_ring->buffer_info[i].segs = segs;
5116 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5117 tx_ring->buffer_info[first].next_to_watch = i;
5118
5119 return count;
03b1320d
AD		 5120
5121dma_error:
af667a29 5122 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5123 buffer_info->dma = 0;
c1fa347f 5124 if (count)
03b1320d 5125 count--;
c1fa347f
RK		 5126
5127 while (count--) {
af667a29 5128 if (i == 0)
03b1320d 5129 i += tx_ring->count;
c1fa347f 5130 i--;
03b1320d 5131 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5132 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5133 }
5134
5135 return 0;
bc7f75fa
AK		 5136}
5137
55aa6985 5138static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5139{
55aa6985 5140 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5141 struct e1000_tx_desc *tx_desc = NULL;
5142 struct e1000_buffer *buffer_info;
5143 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5144 unsigned int i;
5145
5146 if (tx_flags & E1000_TX_FLAGS_TSO) {
5147 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5148 E1000_TXD_CMD_TSE;
5149 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5150
5151 if (tx_flags & E1000_TX_FLAGS_IPV4)
5152 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5153 }
5154
5155 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5156 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5157 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5158 }
5159
5160 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5161 txd_lower |= E1000_TXD_CMD_VLE;
5162 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5163 }
5164
943146de
BG		 5165 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5166 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5167
b67e1913
BA		 5168 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5169 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5170 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5171 }
5172
bc7f75fa
AK		 5173 i = tx_ring->next_to_use;
5174
36b973df 5175 do {
bc7f75fa
AK		 5176 buffer_info = &tx_ring->buffer_info[i];
5177 tx_desc = E1000_TX_DESC(*tx_ring, i);
5178 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5179 tx_desc->lower.data =
5180 cpu_to_le32(txd_lower | buffer_info->length);
5181 tx_desc->upper.data = cpu_to_le32(txd_upper);
5182
5183 i++;
5184 if (i == tx_ring->count)
5185 i = 0;
36b973df 5186 } while (--count > 0);
bc7f75fa
AK		 5187
5188 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5189
943146de
BG		 5190 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5191 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5192 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5193
e921eb1a 5194 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5195 * know there are new descriptors to fetch. (Only
5196 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5197 * such as IA-64).
5198 */
bc7f75fa
AK		 5199 wmb();
5200
5201 tx_ring->next_to_use = i;
c6e7f51e
BA		 5202
5203 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5204 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5205 else
c5083cf6 5206 writel(i, tx_ring->tail);
c6e7f51e 5207
e921eb1a 5208 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5209 * at a time, it synchronizes IO on IA64/Altix systems
5210 */
bc7f75fa
AK		 5211 mmiowb();
5212}
5213
5214#define MINIMUM_DHCP_PACKET_SIZE 282
5215static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5216 struct sk_buff *skb)
5217{
5218 struct e1000_hw *hw = &adapter->hw;
5219 u16 length, offset;
5220
d60923c4
BA		 5221 if (vlan_tx_tag_present(skb) &&
5222 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5223 (adapter->hw.mng_cookie.status &
5224 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5225 return 0;
bc7f75fa
AK		 5226
5227 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5228 return 0;
5229
5230 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
5231 return 0;
5232
5233 {
5234 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
5235 struct udphdr *udp;
5236
5237 if (ip->protocol != IPPROTO_UDP)
5238 return 0;
5239
5240 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5241 if (ntohs(udp->dest) != 67)
5242 return 0;
5243
5244 offset = (u8 *)udp + 8 - skb->data;
5245 length = skb->len - offset;
5246 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5247 }
5248
5249 return 0;
5250}
5251
55aa6985 5252static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5253{
55aa6985 5254 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5255
55aa6985 5256 netif_stop_queue(adapter->netdev);
e921eb1a 5257 /* Herbert's original patch had:
bc7f75fa 5258 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5259 * but since that doesn't exist yet, just open code it.
5260 */
bc7f75fa
AK		 5261 smp_mb();
5262
e921eb1a 5263 /* We need to check again in a case another CPU has just
ad68076e
BA		 5264 * made room available.
5265 */
55aa6985 5266 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5267 return -EBUSY;
5268
5269 /* A reprieve! */
55aa6985 5270 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5271 ++adapter->restart_queue;
5272 return 0;
5273}
5274
55aa6985 5275static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5276{
d821a4c4
BA		 5277 BUG_ON(size > tx_ring->count);
5278
55aa6985 5279 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5280 return 0;
55aa6985 5281 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5282}
5283
3b29a56d
SH		 5284static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5285 struct net_device *netdev)
bc7f75fa
AK		 5286{
5287 struct e1000_adapter *adapter = netdev_priv(netdev);
5288 struct e1000_ring *tx_ring = adapter->tx_ring;
5289 unsigned int first;
bc7f75fa 5290 unsigned int tx_flags = 0;
e743d313 5291 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5292 unsigned int nr_frags;
5293 unsigned int mss;
bc7f75fa
AK		 5294 int count = 0;
5295 int tso;
5296 unsigned int f;
bc7f75fa
AK		 5297
5298 if (test_bit(__E1000_DOWN, &adapter->state)) {
5299 dev_kfree_skb_any(skb);
5300 return NETDEV_TX_OK;
5301 }
5302
5303 if (skb->len <= 0) {
5304 dev_kfree_skb_any(skb);
5305 return NETDEV_TX_OK;
5306 }
5307
e921eb1a 5308 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5309 * pad skb in order to meet this minimum size requirement
5310 */
5311 if (unlikely(skb->len < 17)) {
5312 if (skb_pad(skb, 17 - skb->len))
5313 return NETDEV_TX_OK;
5314 skb->len = 17;
5315 skb_set_tail_pointer(skb, 17);
5316 }
5317
bc7f75fa 5318 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5319 if (mss) {
5320 u8 hdr_len;
bc7f75fa 5321
e921eb1a 5322 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5323 * points to just header, pull a few bytes of payload from
5324 * frags into skb->data
5325 */
bc7f75fa 5326 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5327 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5328 * avoiding it could save a lot of cycles
5329 */
4e6c709c 5330 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5331 unsigned int pull_size;
5332
a2a5b323 5333 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5334 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5335 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5336 dev_kfree_skb_any(skb);
5337 return NETDEV_TX_OK;
5338 }
e743d313 5339 len = skb_headlen(skb);
bc7f75fa
AK		 5340 }
5341 }
5342
5343 /* reserve a descriptor for the offload context */
5344 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5345 count++;
5346 count++;
5347
d821a4c4 5348 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5349
5350 nr_frags = skb_shinfo(skb)->nr_frags;
5351 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5352 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5353 adapter->tx_fifo_limit);
bc7f75fa
AK		 5354
5355 if (adapter->hw.mac.tx_pkt_filtering)
5356 e1000_transfer_dhcp_info(adapter, skb);
5357
e921eb1a 5358 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5359 * head, otherwise try next time
5360 */
55aa6985 5361 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5362 return NETDEV_TX_BUSY;
bc7f75fa 5363
eab6d18d 5364 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5365 tx_flags |= E1000_TX_FLAGS_VLAN;
5366 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5367 }
5368
5369 first = tx_ring->next_to_use;
5370
55aa6985 5371 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5372 if (tso < 0) {
5373 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5374 return NETDEV_TX_OK;
5375 }
5376
5377 if (tso)
5378 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5379 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5380 tx_flags |= E1000_TX_FLAGS_CSUM;
5381
e921eb1a 5382 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5383 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5384 * no longer assume, we must.
5385 */
bc7f75fa
AK		 5386 if (skb->protocol == htons(ETH_P_IP))
5387 tx_flags |= E1000_TX_FLAGS_IPV4;
5388
943146de
BG		 5389 if (unlikely(skb->no_fcs))
5390 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5391
25985edc 5392 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5393 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5394 nr_frags);
1b7719c4 5395 if (count) {
b67e1913
BA		 5396 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5397 !adapter->tx_hwtstamp_skb)) {
5398 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5399 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5400 adapter->tx_hwtstamp_skb = skb_get(skb);
5401 schedule_work(&adapter->tx_hwtstamp_work);
5402 } else {
5403 skb_tx_timestamp(skb);
5404 }
80be3129 5405
3f0cfa3b 5406 netdev_sent_queue(netdev, skb->len);
55aa6985 5407 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5408 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5409 e1000_maybe_stop_tx(tx_ring,
5410 (MAX_SKB_FRAGS *
5411 DIV_ROUND_UP(PAGE_SIZE,
5412 adapter->tx_fifo_limit) + 2));
1b7719c4 5413 } else {
bc7f75fa 5414 dev_kfree_skb_any(skb);
1b7719c4
AD		 5415 tx_ring->buffer_info[first].time_stamp = 0;
5416 tx_ring->next_to_use = first;
bc7f75fa
AK		 5417 }
5418
bc7f75fa
AK		 5419 return NETDEV_TX_OK;
5420}
5421
5422/**
5423 * e1000_tx_timeout - Respond to a Tx Hang
5424 * @netdev: network interface device structure
5425 **/
5426static void e1000_tx_timeout(struct net_device *netdev)
5427{
5428 struct e1000_adapter *adapter = netdev_priv(netdev);
5429
5430 /* Do the reset outside of interrupt context */
5431 adapter->tx_timeout_count++;
5432 schedule_work(&adapter->reset_task);
5433}
5434
5435static void e1000_reset_task(struct work_struct *work)
5436{
5437 struct e1000_adapter *adapter;
5438 adapter = container_of(work, struct e1000_adapter, reset_task);
5439
615b32af
JB		 5440 /* don't run the task if already down */
5441 if (test_bit(__E1000_DOWN, &adapter->state))
5442 return;
5443
12d43f7d 5444 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5445 e1000e_dump(adapter);
12d43f7d 5446 e_err("Reset adapter unexpectedly\n");
affa9dfb 5447 }
bc7f75fa
AK		 5448 e1000e_reinit_locked(adapter);
5449}
5450
5451/**
67fd4fcb 5452 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5453 * @netdev: network interface device structure
67fd4fcb 5454 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5455 *
5456 * Returns the address of the device statistics structure.
bc7f75fa 5457 **/
67fd4fcb
JK		 5458struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5459 struct rtnl_link_stats64 *stats)
bc7f75fa 5460{
67fd4fcb
JK		 5461 struct e1000_adapter *adapter = netdev_priv(netdev);
5462
5463 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5464 spin_lock(&adapter->stats64_lock);
5465 e1000e_update_stats(adapter);
5466 /* Fill out the OS statistics structure */
5467 stats->rx_bytes = adapter->stats.gorc;
5468 stats->rx_packets = adapter->stats.gprc;
5469 stats->tx_bytes = adapter->stats.gotc;
5470 stats->tx_packets = adapter->stats.gptc;
5471 stats->multicast = adapter->stats.mprc;
5472 stats->collisions = adapter->stats.colc;
5473
5474 /* Rx Errors */
5475
e921eb1a 5476 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5477 * our own version based on RUC and ROC
5478 */
5479 stats->rx_errors = adapter->stats.rxerrc +
5480 adapter->stats.crcerrs + adapter->stats.algnerrc +
5481 adapter->stats.ruc + adapter->stats.roc +
5482 adapter->stats.cexterr;
5483 stats->rx_length_errors = adapter->stats.ruc +
5484 adapter->stats.roc;
5485 stats->rx_crc_errors = adapter->stats.crcerrs;
5486 stats->rx_frame_errors = adapter->stats.algnerrc;
5487 stats->rx_missed_errors = adapter->stats.mpc;
5488
5489 /* Tx Errors */
5490 stats->tx_errors = adapter->stats.ecol +
5491 adapter->stats.latecol;
5492 stats->tx_aborted_errors = adapter->stats.ecol;
5493 stats->tx_window_errors = adapter->stats.latecol;
5494 stats->tx_carrier_errors = adapter->stats.tncrs;
5495
5496 /* Tx Dropped needs to be maintained elsewhere */
5497
5498 spin_unlock(&adapter->stats64_lock);
5499 return stats;
bc7f75fa
AK		 5500}
5501
5502/**
5503 * e1000_change_mtu - Change the Maximum Transfer Unit
5504 * @netdev: network interface device structure
5505 * @new_mtu: new value for maximum frame size
5506 *
5507 * Returns 0 on success, negative on failure
5508 **/
5509static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5510{
5511 struct e1000_adapter *adapter = netdev_priv(netdev);
5512 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5513
2adc55c9 5514 /* Jumbo frame support */
2e1706f2
BA		 5515 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5516 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5517 e_err("Jumbo Frames not supported.\n");
5518 return -EINVAL;
bc7f75fa
AK		 5519 }
5520
2adc55c9
BA		 5521 /* Supported frame sizes */
5522 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5523 (max_frame > adapter->max_hw_frame_size)) {
5524 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5525 return -EINVAL;
5526 }
5527
2fbe4526
BA		 5528 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5529 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5530 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5531 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5532 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5533 return -EINVAL;
5534 }
5535
bc7f75fa 5536 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5537 usleep_range(1000, 2000);
610c9928 5538 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5539 adapter->max_frame_size = max_frame;
610c9928
BA		 5540 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5541 netdev->mtu = new_mtu;
bc7f75fa
AK		 5542 if (netif_running(netdev))
5543 e1000e_down(adapter);
5544
e921eb1a 5545 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5546 * means we reserve 2 more, this pushes us to allocate from the next
5547 * larger slab size.
ad68076e 5548 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5549 * However with the new *_jumbo_rx* routines, jumbo receives will use
5550 * fragmented skbs
ad68076e 5551 */
bc7f75fa 5552
9926146b 5553 if (max_frame <= 2048)
bc7f75fa
AK		 5554 adapter->rx_buffer_len = 2048;
5555 else
5556 adapter->rx_buffer_len = 4096;
5557
5558 /* adjust allocation if LPE protects us, and we aren't using SBP */
5559 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5560 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5561 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5562 + ETH_FCS_LEN;
bc7f75fa 5563
bc7f75fa
AK		 5564 if (netif_running(netdev))
5565 e1000e_up(adapter);
5566 else
5567 e1000e_reset(adapter);
5568
5569 clear_bit(__E1000_RESETTING, &adapter->state);
5570
5571 return 0;
5572}
5573
5574static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5575 int cmd)
5576{
5577 struct e1000_adapter *adapter = netdev_priv(netdev);
5578 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5579
318a94d6 5580 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5581 return -EOPNOTSUPP;
5582
5583 switch (cmd) {
5584 case SIOCGMIIPHY:
5585 data->phy_id = adapter->hw.phy.addr;
5586 break;
5587 case SIOCGMIIREG:
b16a002e
BA		 5588 e1000_phy_read_status(adapter);
5589
7c25769f
BA		 5590 switch (data->reg_num & 0x1F) {
5591 case MII_BMCR:
5592 data->val_out = adapter->phy_regs.bmcr;
5593 break;
5594 case MII_BMSR:
5595 data->val_out = adapter->phy_regs.bmsr;
5596 break;
5597 case MII_PHYSID1:
5598 data->val_out = (adapter->hw.phy.id >> 16);
5599 break;
5600 case MII_PHYSID2:
5601 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5602 break;
5603 case MII_ADVERTISE:
5604 data->val_out = adapter->phy_regs.advertise;
5605 break;
5606 case MII_LPA:
5607 data->val_out = adapter->phy_regs.lpa;
5608 break;
5609 case MII_EXPANSION:
5610 data->val_out = adapter->phy_regs.expansion;
5611 break;
5612 case MII_CTRL1000:
5613 data->val_out = adapter->phy_regs.ctrl1000;
5614 break;
5615 case MII_STAT1000:
5616 data->val_out = adapter->phy_regs.stat1000;
5617 break;
5618 case MII_ESTATUS:
5619 data->val_out = adapter->phy_regs.estatus;
5620 break;
5621 default:
bc7f75fa
AK		 5622 return -EIO;
5623 }
bc7f75fa
AK		 5624 break;
5625 case SIOCSMIIREG:
5626 default:
5627 return -EOPNOTSUPP;
5628 }
5629 return 0;
5630}
5631
b67e1913
BA		 5632/**
5633 * e1000e_hwtstamp_ioctl - control hardware time stamping
5634 * @netdev: network interface device structure
5635 * @ifreq: interface request
5636 *
5637 * Outgoing time stamping can be enabled and disabled. Play nice and
5638 * disable it when requested, although it shouldn't cause any overhead
5639 * when no packet needs it. At most one packet in the queue may be
5640 * marked for time stamping, otherwise it would be impossible to tell
5641 * for sure to which packet the hardware time stamp belongs.
5642 *
5643 * Incoming time stamping has to be configured via the hardware filters.
5644 * Not all combinations are supported, in particular event type has to be
5645 * specified. Matching the kind of event packet is not supported, with the
5646 * exception of "all V2 events regardless of level 2 or 4".
5647 **/
5648static int e1000e_hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr)
5649{
5650 struct e1000_adapter *adapter = netdev_priv(netdev);
5651 struct hwtstamp_config config;
5652 int ret_val;
5653
5654 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5655 return -EFAULT;
5656
5657 adapter->hwtstamp_config = config;
5658
5659 ret_val = e1000e_config_hwtstamp(adapter);
5660 if (ret_val)
5661 return ret_val;
5662
5663 config = adapter->hwtstamp_config;
5664
5665 return copy_to_user(ifr->ifr_data, &config,
5666 sizeof(config)) ? -EFAULT : 0;
5667}
5668
bc7f75fa
AK		 5669static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5670{
5671 switch (cmd) {
5672 case SIOCGMIIPHY:
5673 case SIOCGMIIREG:
5674 case SIOCSMIIREG:
5675 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913
BA		 5676 case SIOCSHWTSTAMP:
5677 return e1000e_hwtstamp_ioctl(netdev, ifr);
bc7f75fa
AK		 5678 default:
5679 return -EOPNOTSUPP;
5680 }
5681}
5682
a4f58f54
BA		 5683static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5684{
5685 struct e1000_hw *hw = &adapter->hw;
5686 u32 i, mac_reg;
2b6b168d 5687 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5688 int retval = 0;
5689
5690 /* copy MAC RARs to PHY RARs */
d3738bb8 5691 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5692
2b6b168d
BA		 5693 retval = hw->phy.ops.acquire(hw);
5694 if (retval) {
5695 e_err("Could not acquire PHY\n");
5696 return retval;
5697 }
5698
5699 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5700 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5701 if (retval)
75ce1532 5702 goto release;
2b6b168d
BA		 5703
5704 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5705 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5706 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5707 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5708 (u16)(mac_reg & 0xFFFF));
5709 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5710 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5711 }
5712
5713 /* configure PHY Rx Control register */
2b6b168d 5714 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5715 mac_reg = er32(RCTL);
5716 if (mac_reg & E1000_RCTL_UPE)
5717 phy_reg |= BM_RCTL_UPE;
5718 if (mac_reg & E1000_RCTL_MPE)
5719 phy_reg |= BM_RCTL_MPE;
5720 phy_reg &= ~(BM_RCTL_MO_MASK);
5721 if (mac_reg & E1000_RCTL_MO_3)
5722 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5723 << BM_RCTL_MO_SHIFT);
5724 if (mac_reg & E1000_RCTL_BAM)
5725 phy_reg |= BM_RCTL_BAM;
5726 if (mac_reg & E1000_RCTL_PMCF)
5727 phy_reg |= BM_RCTL_PMCF;
5728 mac_reg = er32(CTRL);
5729 if (mac_reg & E1000_CTRL_RFCE)
5730 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5731 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5732
5733 /* enable PHY wakeup in MAC register */
5734 ew32(WUFC, wufc);
5735 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5736
5737 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5738 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5739 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5740
5741 /* activate PHY wakeup */
2b6b168d
BA		 5742 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5743 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5744 if (retval)
5745 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5746release:
94d8186a 5747 hw->phy.ops.release(hw);
a4f58f54
BA		 5748
5749 return retval;
5750}
5751
23606cf5
RW		 5752static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5753 bool runtime)
bc7f75fa
AK		 5754{
5755 struct net_device *netdev = pci_get_drvdata(pdev);
5756 struct e1000_adapter *adapter = netdev_priv(netdev);
5757 struct e1000_hw *hw = &adapter->hw;
5758 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5759 /* Runtime suspend should only enable wakeup for link changes */
5760 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5761 int retval = 0;
5762
5763 netif_device_detach(netdev);
5764
5765 if (netif_running(netdev)) {
bb9e44d0
BA		 5766 int count = E1000_CHECK_RESET_COUNT;
5767
5768 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5769 usleep_range(10000, 20000);
5770
bc7f75fa
AK		 5771 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5772 e1000e_down(adapter);
5773 e1000_free_irq(adapter);
5774 }
4662e82b 5775 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5776
5777 retval = pci_save_state(pdev);
5778 if (retval)
5779 return retval;
5780
5781 status = er32(STATUS);
5782 if (status & E1000_STATUS_LU)
5783 wufc &= ~E1000_WUFC_LNKC;
5784
5785 if (wufc) {
5786 e1000_setup_rctl(adapter);
ef9b965a 5787 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5788
5789 /* turn on all-multi mode if wake on multicast is enabled */
5790 if (wufc & E1000_WUFC_MC) {
5791 rctl = er32(RCTL);
5792 rctl |= E1000_RCTL_MPE;
5793 ew32(RCTL, rctl);
5794 }
5795
5796 ctrl = er32(CTRL);
5797 /* advertise wake from D3Cold */
5798 #define E1000_CTRL_ADVD3WUC 0x00100000
5799 /* phy power management enable */
5800 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5801 ctrl |= E1000_CTRL_ADVD3WUC;
5802 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5803 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5804 ew32(CTRL, ctrl);
5805
318a94d6
JK		 5806 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5807 adapter->hw.phy.media_type ==
5808 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5809 /* keep the laser running in D3 */
5810 ctrl_ext = er32(CTRL_EXT);
93a23f48 5811 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5812 ew32(CTRL_EXT, ctrl_ext);
5813 }
5814
97ac8cae 5815 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5816 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5817
bc7f75fa
AK		 5818 /* Allow time for pending master requests to run */
5819 e1000e_disable_pcie_master(&adapter->hw);
5820
82776a4b 5821 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5822 /* enable wakeup by the PHY */
5823 retval = e1000_init_phy_wakeup(adapter, wufc);
5824 if (retval)
5825 return retval;
5826 } else {
5827 /* enable wakeup by the MAC */
5828 ew32(WUFC, wufc);
5829 ew32(WUC, E1000_WUC_PME_EN);
5830 }
bc7f75fa
AK		 5831 } else {
5832 ew32(WUC, 0);
5833 ew32(WUFC, 0);
bc7f75fa
AK		 5834 }
5835
4f9de721
RW		 5836 *enable_wake = !!wufc;
5837
bc7f75fa 5838 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5839 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5840 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5841 *enable_wake = true;
bc7f75fa
AK		 5842
5843 if (adapter->hw.phy.type == e1000_phy_igp_3)
5844 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5845
e921eb1a 5846 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 5847 * would have already happened in close and is redundant.
5848 */
31dbe5b4 5849 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5850
5851 pci_disable_device(pdev);
5852
4f9de721
RW		 5853 return 0;
5854}
5855
5856static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5857{
5858 if (sleep && wake) {
5859 pci_prepare_to_sleep(pdev);
5860 return;
5861 }
5862
5863 pci_wake_from_d3(pdev, wake);
5864 pci_set_power_state(pdev, PCI_D3hot);
5865}
5866
5867static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5868 bool wake)
5869{
5870 struct net_device *netdev = pci_get_drvdata(pdev);
5871 struct e1000_adapter *adapter = netdev_priv(netdev);
5872
e921eb1a 5873 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 5874 * correctable error when the MAC transitions from D0 to D3. To
5875 * prevent this we need to mask off the correctable errors on the
5876 * downstream port of the pci-e switch.
5877 */
5878 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5879 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 5880 u16 devctl;
5881
f8c0fcac
JL		 5882 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
5883 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
5884 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 5885
4f9de721 5886 e1000_power_off(pdev, sleep, wake);
005cbdfc 5887
f8c0fcac 5888 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 5889 } else {
4f9de721 5890 e1000_power_off(pdev, sleep, wake);
005cbdfc 5891 }
bc7f75fa
AK		 5892}
5893
6f461f6c
BA		 5894#ifdef CONFIG_PCIEASPM
5895static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5896{
9f728f53 5897 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5898}
5899#else
5900static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2 5901{
ffe0b2ff
BH		 5902 u16 aspm_ctl = 0;
5903
5904 if (state & PCIE_LINK_STATE_L0S)
5905 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L0S;
5906 if (state & PCIE_LINK_STATE_L1)
5907 aspm_ctl |= PCI_EXP_LNKCTL_ASPM_L1;
5908
e921eb1a 5909 /* Both device and parent should have the same ASPM setting.
6f461f6c 5910 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5911 */
ffe0b2ff 5912 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_ctl);
0c75ba22 5913
f8c0fcac
JL		 5914 if (pdev->bus->self)
5915 pcie_capability_clear_word(pdev->bus->self, PCI_EXP_LNKCTL,
ffe0b2ff 5916 aspm_ctl);
6f461f6c
BA		 5917}
5918#endif
78cd29d5 5919static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5920{
5921 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5922 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5923 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5924
5925 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5926}
5927
aa338601 5928#ifdef CONFIG_PM
23606cf5 5929static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5930{
23606cf5 5931 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5932}
5933
23606cf5 5934static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5935{
5936 struct net_device *netdev = pci_get_drvdata(pdev);
5937 struct e1000_adapter *adapter = netdev_priv(netdev);
5938 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5939 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5940 u32 err;
5941
78cd29d5
BA		 5942 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5943 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5944 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5945 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5946 if (aspm_disable_flag)
5947 e1000e_disable_aspm(pdev, aspm_disable_flag);
5948
bc7f75fa
AK		 5949 pci_set_power_state(pdev, PCI_D0);
5950 pci_restore_state(pdev);
28b8f04a 5951 pci_save_state(pdev);
6e4f6f6b 5952
4662e82b 5953 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5954 if (netif_running(netdev)) {
5955 err = e1000_request_irq(adapter);
5956 if (err)
5957 return err;
5958 }
5959
2fbe4526 5960 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 5961 e1000_resume_workarounds_pchlan(&adapter->hw);
5962
bc7f75fa 5963 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5964
5965 /* report the system wakeup cause from S3/S4 */
5966 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5967 u16 phy_data;
5968
5969 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5970 if (phy_data) {
5971 e_info("PHY Wakeup cause - %s\n",
5972 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5973 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5974 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5975 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5976 phy_data & E1000_WUS_LNKC ?
5977 "Link Status Change" : "other");
a4f58f54
BA		 5978 }
5979 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5980 } else {
5981 u32 wus = er32(WUS);
5982 if (wus) {
5983 e_info("MAC Wakeup cause - %s\n",
5984 wus & E1000_WUS_EX ? "Unicast Packet" :
5985 wus & E1000_WUS_MC ? "Multicast Packet" :
5986 wus & E1000_WUS_BC ? "Broadcast Packet" :
5987 wus & E1000_WUS_MAG ? "Magic Packet" :
5988 wus & E1000_WUS_LNKC ? "Link Status Change" :
5989 "other");
5990 }
5991 ew32(WUS, ~0);
5992 }
5993
bc7f75fa 5994 e1000e_reset(adapter);
bc7f75fa 5995
cd791618 5996 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5997
5998 if (netif_running(netdev))
5999 e1000e_up(adapter);
6000
6001 netif_device_attach(netdev);
6002
e921eb1a 6003 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6004 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6005 * under the control of the driver.
6006 */
c43bc57e 6007 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6008 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6009
6010 return 0;
6011}
23606cf5 6012
a0340162
RW		 6013#ifdef CONFIG_PM_SLEEP
6014static int e1000_suspend(struct device *dev)
6015{
6016 struct pci_dev *pdev = to_pci_dev(dev);
6017 int retval;
6018 bool wake;
6019
6020 retval = __e1000_shutdown(pdev, &wake, false);
6021 if (!retval)
6022 e1000_complete_shutdown(pdev, true, wake);
6023
6024 return retval;
6025}
6026
23606cf5
RW		 6027static int e1000_resume(struct device *dev)
6028{
6029 struct pci_dev *pdev = to_pci_dev(dev);
6030 struct net_device *netdev = pci_get_drvdata(pdev);
6031 struct e1000_adapter *adapter = netdev_priv(netdev);
6032
6033 if (e1000e_pm_ready(adapter))
6034 adapter->idle_check = true;
6035
6036 return __e1000_resume(pdev);
6037}
a0340162
RW		 6038#endif /* CONFIG_PM_SLEEP */
6039
6040#ifdef CONFIG_PM_RUNTIME
6041static int e1000_runtime_suspend(struct device *dev)
6042{
6043 struct pci_dev *pdev = to_pci_dev(dev);
6044 struct net_device *netdev = pci_get_drvdata(pdev);
6045 struct e1000_adapter *adapter = netdev_priv(netdev);
6046
6047 if (e1000e_pm_ready(adapter)) {
6048 bool wake;
6049
6050 __e1000_shutdown(pdev, &wake, true);
6051 }
6052
6053 return 0;
6054}
6055
6056static int e1000_idle(struct device *dev)
6057{
6058 struct pci_dev *pdev = to_pci_dev(dev);
6059 struct net_device *netdev = pci_get_drvdata(pdev);
6060 struct e1000_adapter *adapter = netdev_priv(netdev);
6061
6062 if (!e1000e_pm_ready(adapter))
6063 return 0;
6064
6065 if (adapter->idle_check) {
6066 adapter->idle_check = false;
6067 if (!e1000e_has_link(adapter))
6068 pm_schedule_suspend(dev, MSEC_PER_SEC);
6069 }
6070
6071 return -EBUSY;
6072}
23606cf5
RW		 6073
6074static int e1000_runtime_resume(struct device *dev)
6075{
6076 struct pci_dev *pdev = to_pci_dev(dev);
6077 struct net_device *netdev = pci_get_drvdata(pdev);
6078 struct e1000_adapter *adapter = netdev_priv(netdev);
6079
6080 if (!e1000e_pm_ready(adapter))
6081 return 0;
6082
6083 adapter->idle_check = !dev->power.runtime_auto;
6084 return __e1000_resume(pdev);
6085}
a0340162 6086#endif /* CONFIG_PM_RUNTIME */
aa338601 6087#endif /* CONFIG_PM */
bc7f75fa
AK		 6088
6089static void e1000_shutdown(struct pci_dev *pdev)
6090{
4f9de721
RW		 6091 bool wake = false;
6092
23606cf5 6093 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 6094
6095 if (system_state == SYSTEM_POWER_OFF)
6096 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 6097}
6098
6099#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 6100
6101static irqreturn_t e1000_intr_msix(int irq, void *data)
6102{
6103 struct net_device *netdev = data;
6104 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6105
6106 if (adapter->msix_entries) {
90da0669
BA		 6107 int vector, msix_irq;
6108
147b2c8c
DD		 6109 vector = 0;
6110 msix_irq = adapter->msix_entries[vector].vector;
6111 disable_irq(msix_irq);
6112 e1000_intr_msix_rx(msix_irq, netdev);
6113 enable_irq(msix_irq);
6114
6115 vector++;
6116 msix_irq = adapter->msix_entries[vector].vector;
6117 disable_irq(msix_irq);
6118 e1000_intr_msix_tx(msix_irq, netdev);
6119 enable_irq(msix_irq);
6120
6121 vector++;
6122 msix_irq = adapter->msix_entries[vector].vector;
6123 disable_irq(msix_irq);
6124 e1000_msix_other(msix_irq, netdev);
6125 enable_irq(msix_irq);
6126 }
6127
6128 return IRQ_HANDLED;
6129}
6130
e921eb1a
BA		 6131/**
6132 * e1000_netpoll
6133 * @netdev: network interface device structure
6134 *
bc7f75fa
AK		 6135 * Polling 'interrupt' - used by things like netconsole to send skbs
6136 * without having to re-enable interrupts. It's not called while
6137 * the interrupt routine is executing.
6138 */
6139static void e1000_netpoll(struct net_device *netdev)
6140{
6141 struct e1000_adapter *adapter = netdev_priv(netdev);
6142
147b2c8c
DD		 6143 switch (adapter->int_mode) {
6144 case E1000E_INT_MODE_MSIX:
6145 e1000_intr_msix(adapter->pdev->irq, netdev);
6146 break;
6147 case E1000E_INT_MODE_MSI:
6148 disable_irq(adapter->pdev->irq);
6149 e1000_intr_msi(adapter->pdev->irq, netdev);
6150 enable_irq(adapter->pdev->irq);
6151 break;
6152 default: /* E1000E_INT_MODE_LEGACY */
6153 disable_irq(adapter->pdev->irq);
6154 e1000_intr(adapter->pdev->irq, netdev);
6155 enable_irq(adapter->pdev->irq);
6156 break;
6157 }
bc7f75fa
AK		 6158}
6159#endif
6160
6161/**
6162 * e1000_io_error_detected - called when PCI error is detected
6163 * @pdev: Pointer to PCI device
6164 * @state: The current pci connection state
6165 *
6166 * This function is called after a PCI bus error affecting
6167 * this device has been detected.
6168 */
6169static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6170 pci_channel_state_t state)
6171{
6172 struct net_device *netdev = pci_get_drvdata(pdev);
6173 struct e1000_adapter *adapter = netdev_priv(netdev);
6174
6175 netif_device_detach(netdev);
6176
c93b5a76
MM		 6177 if (state == pci_channel_io_perm_failure)
6178 return PCI_ERS_RESULT_DISCONNECT;
6179
bc7f75fa
AK		 6180 if (netif_running(netdev))
6181 e1000e_down(adapter);
6182 pci_disable_device(pdev);
6183
6184 /* Request a slot slot reset. */
6185 return PCI_ERS_RESULT_NEED_RESET;
6186}
6187
6188/**
6189 * e1000_io_slot_reset - called after the pci bus has been reset.
6190 * @pdev: Pointer to PCI device
6191 *
6192 * Restart the card from scratch, as if from a cold-boot. Implementation
6193 * resembles the first-half of the e1000_resume routine.
6194 */
6195static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6196{
6197 struct net_device *netdev = pci_get_drvdata(pdev);
6198 struct e1000_adapter *adapter = netdev_priv(netdev);
6199 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6200 u16 aspm_disable_flag = 0;
6e4f6f6b 6201 int err;
111b9dc5 6202 pci_ers_result_t result;
bc7f75fa 6203
78cd29d5
BA		 6204 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6205 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6206 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6207 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6208 if (aspm_disable_flag)
6209 e1000e_disable_aspm(pdev, aspm_disable_flag);
6210
f0f422e5 6211 err = pci_enable_device_mem(pdev);
6e4f6f6b 6212 if (err) {
bc7f75fa
AK		 6213 dev_err(&pdev->dev,
6214 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6215 result = PCI_ERS_RESULT_DISCONNECT;
6216 } else {
6217 pci_set_master(pdev);
23606cf5 6218 pdev->state_saved = true;
111b9dc5 6219 pci_restore_state(pdev);
bc7f75fa 6220
111b9dc5
JB		 6221 pci_enable_wake(pdev, PCI_D3hot, 0);
6222 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6223
111b9dc5
JB		 6224 e1000e_reset(adapter);
6225 ew32(WUS, ~0);
6226 result = PCI_ERS_RESULT_RECOVERED;
6227 }
bc7f75fa 6228
111b9dc5
JB		 6229 pci_cleanup_aer_uncorrect_error_status(pdev);
6230
6231 return result;
bc7f75fa
AK		 6232}
6233
6234/**
6235 * e1000_io_resume - called when traffic can start flowing again.
6236 * @pdev: Pointer to PCI device
6237 *
6238 * This callback is called when the error recovery driver tells us that
6239 * its OK to resume normal operation. Implementation resembles the
6240 * second-half of the e1000_resume routine.
6241 */
6242static void e1000_io_resume(struct pci_dev *pdev)
6243{
6244 struct net_device *netdev = pci_get_drvdata(pdev);
6245 struct e1000_adapter *adapter = netdev_priv(netdev);
6246
cd791618 6247 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6248
6249 if (netif_running(netdev)) {
6250 if (e1000e_up(adapter)) {
6251 dev_err(&pdev->dev,
6252 "can't bring device back up after reset\n");
6253 return;
6254 }
6255 }
6256
6257 netif_device_attach(netdev);
6258
e921eb1a 6259 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6260 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6261 * under the control of the driver.
6262 */
c43bc57e 6263 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6264 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6265
6266}
6267
6268static void e1000_print_device_info(struct e1000_adapter *adapter)
6269{
6270 struct e1000_hw *hw = &adapter->hw;
6271 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6272 u32 ret_val;
6273 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6274
6275 /* print bus type/speed/width info */
a5cc7642 6276 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6277 /* bus width */
6278 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
6279 "Width x1"),
6280 /* MAC address */
7c510e4b 6281 netdev->dev_addr);
44defeb3
JK		 6282 e_info("Intel(R) PRO/%s Network Connection\n",
6283 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6284 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6285 E1000_PBANUM_LENGTH);
6286 if (ret_val)
f2315bf1 6287 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6288 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6289 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6290}
6291
10aa4c04
AK		 6292static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6293{
6294 struct e1000_hw *hw = &adapter->hw;
6295 int ret_val;
6296 u16 buf = 0;
6297
6298 if (hw->mac.type != e1000_82573)
6299 return;
6300
6301 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6302 le16_to_cpus(&buf);
6303 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6304 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6305 dev_warn(&adapter->pdev->dev,
6306 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6307 }
10aa4c04
AK		 6308}
6309
c8f44aff 6310static int e1000_set_features(struct net_device *netdev,
70495a50 6311 netdev_features_t features)
dc221294
BA		 6312{
6313 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6314 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6315
6316 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6317 adapter->flags |= FLAG_TSO_FORCE;
6318
6319 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6320 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6321 NETIF_F_RXALL)))
dc221294
BA		 6322 return 0;
6323
0184039a
BG		 6324 if (changed & NETIF_F_RXFCS) {
6325 if (features & NETIF_F_RXFCS) {
6326 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6327 } else {
6328 /* We need to take it back to defaults, which might mean
6329 * stripping is still disabled at the adapter level.
6330 */
6331 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6332 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6333 else
6334 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6335 }
6336 }
6337
70495a50
BA		 6338 netdev->features = features;
6339
dc221294
BA		 6340 if (netif_running(netdev))
6341 e1000e_reinit_locked(adapter);
6342 else
6343 e1000e_reset(adapter);
6344
6345 return 0;
6346}
6347
651c2466
SH		 6348static const struct net_device_ops e1000e_netdev_ops = {
6349 .ndo_open = e1000_open,
6350 .ndo_stop = e1000_close,
00829823 6351 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6352 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6353 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6354 .ndo_set_mac_address = e1000_set_mac,
6355 .ndo_change_mtu = e1000_change_mtu,
6356 .ndo_do_ioctl = e1000_ioctl,
6357 .ndo_tx_timeout = e1000_tx_timeout,
6358 .ndo_validate_addr = eth_validate_addr,
6359
651c2466
SH		 6360 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6361 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6362#ifdef CONFIG_NET_POLL_CONTROLLER
6363 .ndo_poll_controller = e1000_netpoll,
6364#endif
dc221294 6365 .ndo_set_features = e1000_set_features,
651c2466
SH		 6366};
6367
bc7f75fa
AK		 6368/**
6369 * e1000_probe - Device Initialization Routine
6370 * @pdev: PCI device information struct
6371 * @ent: entry in e1000_pci_tbl
6372 *
6373 * Returns 0 on success, negative on failure
6374 *
6375 * e1000_probe initializes an adapter identified by a pci_dev structure.
6376 * The OS initialization, configuring of the adapter private structure,
6377 * and a hardware reset occur.
6378 **/
1dd06ae8 6379static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6380{
6381 struct net_device *netdev;
6382 struct e1000_adapter *adapter;
6383 struct e1000_hw *hw;
6384 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6385 resource_size_t mmio_start, mmio_len;
6386 resource_size_t flash_start, flash_len;
bc7f75fa 6387 static int cards_found;
78cd29d5 6388 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6389 int i, err, pci_using_dac;
6390 u16 eeprom_data = 0;
6391 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6392
78cd29d5
BA		 6393 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6394 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6395 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6396 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6397 if (aspm_disable_flag)
6398 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6399
f0f422e5 6400 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6401 if (err)
6402 return err;
6403
6404 pci_using_dac = 0;
0be3f55f 6405 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6406 if (!err) {
0be3f55f 6407 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6408 if (!err)
6409 pci_using_dac = 1;
6410 } else {
0be3f55f 6411 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6412 if (err) {
0be3f55f
NN		 6413 err = dma_set_coherent_mask(&pdev->dev,
6414 DMA_BIT_MASK(32));
bc7f75fa 6415 if (err) {
ef456f85 6416 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6417 goto err_dma;
6418 }
6419 }
6420 }
6421
e8de1481 6422 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6423 pci_select_bars(pdev, IORESOURCE_MEM),
6424 e1000e_driver_name);
bc7f75fa
AK		 6425 if (err)
6426 goto err_pci_reg;
6427
68eac460 6428 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6429 pci_enable_pcie_error_reporting(pdev);
68eac460 6430
bc7f75fa 6431 pci_set_master(pdev);
438b365a
BA		 6432 /* PCI config space info */
6433 err = pci_save_state(pdev);
6434 if (err)
6435 goto err_alloc_etherdev;
bc7f75fa
AK		 6436
6437 err = -ENOMEM;
6438 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6439 if (!netdev)
6440 goto err_alloc_etherdev;
6441
bc7f75fa
AK		 6442 SET_NETDEV_DEV(netdev, &pdev->dev);
6443
f85e4dfa
TH		 6444 netdev->irq = pdev->irq;
6445
bc7f75fa
AK		 6446 pci_set_drvdata(pdev, netdev);
6447 adapter = netdev_priv(netdev);
6448 hw = &adapter->hw;
6449 adapter->netdev = netdev;
6450 adapter->pdev = pdev;
6451 adapter->ei = ei;
6452 adapter->pba = ei->pba;
6453 adapter->flags = ei->flags;
eb7c3adb 6454 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6455 adapter->hw.adapter = adapter;
6456 adapter->hw.mac.type = ei->mac;
2adc55c9 6457 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6458 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6459
6460 mmio_start = pci_resource_start(pdev, 0);
6461 mmio_len = pci_resource_len(pdev, 0);
6462
6463 err = -EIO;
6464 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6465 if (!adapter->hw.hw_addr)
6466 goto err_ioremap;
6467
6468 if ((adapter->flags & FLAG_HAS_FLASH) &&
6469 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6470 flash_start = pci_resource_start(pdev, 1);
6471 flash_len = pci_resource_len(pdev, 1);
6472 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6473 if (!adapter->hw.flash_address)
6474 goto err_flashmap;
6475 }
6476
6477 /* construct the net_device struct */
651c2466 6478 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6479 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6480 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6481 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6482 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6483
6484 netdev->mem_start = mmio_start;
6485 netdev->mem_end = mmio_start + mmio_len;
6486
6487 adapter->bd_number = cards_found++;
6488
4662e82b
BA		 6489 e1000e_check_options(adapter);
6490
bc7f75fa
AK		 6491 /* setup adapter struct */
6492 err = e1000_sw_init(adapter);
6493 if (err)
6494 goto err_sw_init;
6495
bc7f75fa
AK		 6496 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6497 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6498 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6499
69e3fd8c 6500 err = ei->get_variants(adapter);
bc7f75fa
AK		 6501 if (err)
6502 goto err_hw_init;
6503
4a770358
BA		 6504 if ((adapter->flags & FLAG_IS_ICH) &&
6505 (adapter->flags & FLAG_READ_ONLY_NVM))
6506 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6507
bc7f75fa
AK		 6508 hw->mac.ops.get_bus_info(&adapter->hw);
6509
318a94d6 6510 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6511
6512 /* Copper options */
318a94d6 6513 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6514 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6515 adapter->hw.phy.disable_polarity_correction = 0;
6516 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6517 }
6518
470a5420 6519 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6520 dev_info(&pdev->dev,
6521 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6522
dc221294
BA		 6523 /* Set initial default active device features */
6524 netdev->features = (NETIF_F_SG |
6525 NETIF_F_HW_VLAN_RX |
6526 NETIF_F_HW_VLAN_TX |
6527 NETIF_F_TSO |
6528 NETIF_F_TSO6 |
70495a50 6529 NETIF_F_RXHASH |
dc221294
BA		 6530 NETIF_F_RXCSUM |
6531 NETIF_F_HW_CSUM);
6532
6533 /* Set user-changeable features (subset of all device features) */
6534 netdev->hw_features = netdev->features;
0184039a 6535 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6536 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6537 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6538
6539 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6540 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6541
dc221294
BA		 6542 netdev->vlan_features |= (NETIF_F_SG |
6543 NETIF_F_TSO |
6544 NETIF_F_TSO6 |
6545 NETIF_F_HW_CSUM);
a5136e23 6546
ef9b965a
JB		 6547 netdev->priv_flags |= IFF_UNICAST_FLT;
6548
7b872a55 6549 if (pci_using_dac) {
bc7f75fa 6550 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6551 netdev->vlan_features |= NETIF_F_HIGHDMA;
6552 }
bc7f75fa 6553
bc7f75fa
AK		 6554 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6555 adapter->flags |= FLAG_MNG_PT_ENABLED;
6556
e921eb1a 6557 /* before reading the NVM, reset the controller to
ad68076e
BA		 6558 * put the device in a known good starting state
6559 */
bc7f75fa
AK		 6560 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6561
e921eb1a 6562 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6563 * attempt. Let's give it a few tries
6564 */
6565 for (i = 0;; i++) {
6566 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6567 break;
6568 if (i == 2) {
185095fb 6569 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6570 err = -EIO;
6571 goto err_eeprom;
6572 }
6573 }
6574
10aa4c04
AK		 6575 e1000_eeprom_checks(adapter);
6576
608f8a0d 6577 /* copy the MAC address */
bc7f75fa 6578 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6579 dev_err(&pdev->dev,
6580 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6581
6582 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6583
aaeb6cdf 6584 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6585 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6586 netdev->dev_addr);
bc7f75fa
AK		 6587 err = -EIO;
6588 goto err_eeprom;
6589 }
6590
6591 init_timer(&adapter->watchdog_timer);
c061b18d 6592 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6593 adapter->watchdog_timer.data = (unsigned long) adapter;
6594
6595 init_timer(&adapter->phy_info_timer);
c061b18d 6596 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6597 adapter->phy_info_timer.data = (unsigned long) adapter;
6598
6599 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6600 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6601 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6602 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6603 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6604
bc7f75fa
AK		 6605 /* Initialize link parameters. User can change them with ethtool */
6606 adapter->hw.mac.autoneg = 1;
3db1cd5c 6607 adapter->fc_autoneg = true;
5c48ef3e
BA		 6608 adapter->hw.fc.requested_mode = e1000_fc_default;
6609 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6610 adapter->hw.phy.autoneg_advertised = 0x2f;
6611
6612 /* ring size defaults */
d821a4c4
BA		 6613 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6614 adapter->tx_ring->count = E1000_DEFAULT_TXD;
bc7f75fa 6615
e921eb1a 6616 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6617 * the EEPROM, enable the ACPI Magic Packet filter
6618 */
6619 if (adapter->flags & FLAG_APME_IN_WUC) {
6620 /* APME bit in EEPROM is mapped to WUC.APME */
6621 eeprom_data = er32(WUC);
6622 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6623 if ((hw->mac.type > e1000_ich10lan) &&
6624 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6625 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6626 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6627 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6628 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6629 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6630 1, &eeprom_data);
bc7f75fa 6631 else
3d3a1676
BA		 6632 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6633 1, &eeprom_data);
bc7f75fa
AK		 6634 }
6635
6636 /* fetch WoL from EEPROM */
6637 if (eeprom_data & eeprom_apme_mask)
6638 adapter->eeprom_wol |= E1000_WUFC_MAG;
6639
e921eb1a 6640 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6641 * where the eeprom may be wrong or the board simply won't support
6642 * wake on lan on a particular port
6643 */
6644 if (!(adapter->flags & FLAG_HAS_WOL))
6645 adapter->eeprom_wol = 0;
6646
6647 /* initialize the wol settings based on the eeprom settings */
6648 adapter->wol = adapter->eeprom_wol;
6ff68026 6649 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6650
84527590
BA		 6651 /* save off EEPROM version number */
6652 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6653
bc7f75fa
AK		 6654 /* reset the hardware with the new settings */
6655 e1000e_reset(adapter);
6656
e921eb1a 6657 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6658 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6659 * under the control of the driver.
6660 */
c43bc57e 6661 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6662 e1000e_get_hw_control(adapter);
bc7f75fa 6663
f2315bf1 6664 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6665 err = register_netdev(netdev);
6666 if (err)
6667 goto err_register;
6668
9c563d20
JB		 6669 /* carrier off reporting is important to ethtool even BEFORE open */
6670 netif_carrier_off(netdev);
6671
bc7f75fa
AK		 6672 e1000_print_device_info(adapter);
6673
f3ec4f87
AS		 6674 if (pci_dev_run_wake(pdev))
6675 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6676
bc7f75fa
AK		 6677 return 0;
6678
6679err_register:
c43bc57e 6680 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6681 e1000e_release_hw_control(adapter);
bc7f75fa 6682err_eeprom:
470a5420 6683 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6684 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6685err_hw_init:
bc7f75fa
AK		 6686 kfree(adapter->tx_ring);
6687 kfree(adapter->rx_ring);
6688err_sw_init:
c43bc57e
JB		 6689 if (adapter->hw.flash_address)
6690 iounmap(adapter->hw.flash_address);
e82f54ba 6691 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6692err_flashmap:
bc7f75fa
AK		 6693 iounmap(adapter->hw.hw_addr);
6694err_ioremap:
6695 free_netdev(netdev);
6696err_alloc_etherdev:
f0f422e5
BA		 6697 pci_release_selected_regions(pdev,
6698 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6699err_pci_reg:
6700err_dma:
6701 pci_disable_device(pdev);
6702 return err;
6703}
6704
6705/**
6706 * e1000_remove - Device Removal Routine
6707 * @pdev: PCI device information struct
6708 *
6709 * e1000_remove is called by the PCI subsystem to alert the driver
6710 * that it should release a PCI device. The could be caused by a
6711 * Hot-Plug event, or because the driver is going to be removed from
6712 * memory.
6713 **/
9f9a12f8 6714static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6715{
6716 struct net_device *netdev = pci_get_drvdata(pdev);
6717 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6718 bool down = test_bit(__E1000_DOWN, &adapter->state);
6719
e921eb1a 6720 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6721 * from being rescheduled.
ad68076e 6722 */
23606cf5
RW		 6723 if (!down)
6724 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6725 del_timer_sync(&adapter->watchdog_timer);
6726 del_timer_sync(&adapter->phy_info_timer);
6727
41cec6f1
BA		 6728 cancel_work_sync(&adapter->reset_task);
6729 cancel_work_sync(&adapter->watchdog_task);
6730 cancel_work_sync(&adapter->downshift_task);
6731 cancel_work_sync(&adapter->update_phy_task);
6732 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6733
b67e1913
BA		 6734 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6735 cancel_work_sync(&adapter->tx_hwtstamp_work);
6736 if (adapter->tx_hwtstamp_skb) {
6737 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6738 adapter->tx_hwtstamp_skb = NULL;
6739 }
6740 }
6741
17f208de
BA		 6742 if (!(netdev->flags & IFF_UP))
6743 e1000_power_down_phy(adapter);
6744
23606cf5
RW		 6745 /* Don't lie to e1000_close() down the road. */
6746 if (!down)
6747 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6748 unregister_netdev(netdev);
6749
f3ec4f87
AS		 6750 if (pci_dev_run_wake(pdev))
6751 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6752
e921eb1a 6753 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6754 * would have already happened in close and is redundant.
6755 */
31dbe5b4 6756 e1000e_release_hw_control(adapter);
bc7f75fa 6757
4662e82b 6758 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6759 kfree(adapter->tx_ring);
6760 kfree(adapter->rx_ring);
6761
6762 iounmap(adapter->hw.hw_addr);
6763 if (adapter->hw.flash_address)
6764 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6765 pci_release_selected_regions(pdev,
6766 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6767
6768 free_netdev(netdev);
6769
111b9dc5 6770 /* AER disable */
19d5afd4 6771 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6772
bc7f75fa
AK		 6773 pci_disable_device(pdev);
6774}
6775
6776/* PCI Error Recovery (ERS) */
3646f0e5 6777static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6778 .error_detected = e1000_io_error_detected,
6779 .slot_reset = e1000_io_slot_reset,
6780 .resume = e1000_io_resume,
6781};
6782
a3aa1884 6783static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6785 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6788 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6790 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6793
bc7f75fa
AK		 6794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6798
bc7f75fa
AK		 6799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6802
4662e82b 6803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6806
bc7f75fa
AK		 6807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6808 board_80003es2lan },
6809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6810 board_80003es2lan },
6811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6812 board_80003es2lan },
6813 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6814 board_80003es2lan },
ad68076e 6815
bc7f75fa
AK		 6816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6824
bc7f75fa
AK		 6825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6834
6835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6838
f4187b56
BA		 6839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6842
a4f58f54
BA		 6843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6847
d3738bb8
BA		 6848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6850
2fbe4526
BA		 6851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
6852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 6853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
6854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
2fbe4526 6855
f36bb6ca 6856 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6857};
6858MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6859
aa338601 6860#ifdef CONFIG_PM
23606cf5 6861static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6862 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6863 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6864 e1000_runtime_resume, e1000_idle)
23606cf5 6865};
e50208a0 6866#endif
23606cf5 6867
bc7f75fa
AK		 6868/* PCI Device API Driver */
6869static struct pci_driver e1000_driver = {
6870 .name = e1000e_driver_name,
6871 .id_table = e1000_pci_tbl,
6872 .probe = e1000_probe,
9f9a12f8 6873 .remove = e1000_remove,
aa338601 6874#ifdef CONFIG_PM
f36bb6ca
BA		 6875 .driver = {
6876 .pm = &e1000_pm_ops,
6877 },
bc7f75fa
AK		 6878#endif
6879 .shutdown = e1000_shutdown,
6880 .err_handler = &e1000_err_handler
6881};
6882
6883/**
6884 * e1000_init_module - Driver Registration Routine
6885 *
6886 * e1000_init_module is the first routine called when the driver is
6887 * loaded. All it does is register with the PCI subsystem.
6888 **/
6889static int __init e1000_init_module(void)
6890{
6891 int ret;
8544b9f7
BA		 6892 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6893 e1000e_driver_version);
f5e261e6 6894 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6895 ret = pci_register_driver(&e1000_driver);
53ec5498 6896
bc7f75fa
AK		 6897 return ret;
6898}
6899module_init(e1000_init_module);
6900
6901/**
6902 * e1000_exit_module - Driver Exit Cleanup Routine
6903 *
6904 * e1000_exit_module is called just before the driver is removed
6905 * from memory.
6906 **/
6907static void __exit e1000_exit_module(void)
6908{
6909 pci_unregister_driver(&e1000_driver);
6910}
6911module_exit(e1000_exit_module);
6912
6913
6914MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6915MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6916MODULE_LICENSE("GPL");
6917MODULE_VERSION(DRV_VERSION);
6918
06c24b91 6919/* netdev.c */
Linux kernel - Deliverables
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