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ixgbe: Fix use after free on module remove
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
fad59b0d 59#define DRV_VERSION "1.10.6" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
af667a29
BA		 89#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
90#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
91#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
92#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
93#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
94
95#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
96#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
97#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
98#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
99#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 100
101static const struct e1000_reg_info e1000_reg_info_tbl[] = {
102
103 /* General Registers */
104 {E1000_CTRL, "CTRL"},
105 {E1000_STATUS, "STATUS"},
106 {E1000_CTRL_EXT, "CTRL_EXT"},
107
108 /* Interrupt Registers */
109 {E1000_ICR, "ICR"},
110
af667a29 111 /* Rx Registers */
84f4ee90 112 {E1000_RCTL, "RCTL"},
1e36052e
BA		 113 {E1000_RDLEN(0), "RDLEN"},
114 {E1000_RDH(0), "RDH"},
115 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 116 {E1000_RDTR, "RDTR"},
117 {E1000_RXDCTL(0), "RXDCTL"},
118 {E1000_ERT, "ERT"},
1e36052e
BA		 119 {E1000_RDBAL(0), "RDBAL"},
120 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 121 {E1000_RDFH, "RDFH"},
122 {E1000_RDFT, "RDFT"},
123 {E1000_RDFHS, "RDFHS"},
124 {E1000_RDFTS, "RDFTS"},
125 {E1000_RDFPC, "RDFPC"},
126
af667a29 127 /* Tx Registers */
84f4ee90 128 {E1000_TCTL, "TCTL"},
1e36052e
BA		 129 {E1000_TDBAL(0), "TDBAL"},
130 {E1000_TDBAH(0), "TDBAH"},
131 {E1000_TDLEN(0), "TDLEN"},
132 {E1000_TDH(0), "TDH"},
133 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 134 {E1000_TIDV, "TIDV"},
135 {E1000_TXDCTL(0), "TXDCTL"},
136 {E1000_TADV, "TADV"},
137 {E1000_TARC(0), "TARC"},
138 {E1000_TDFH, "TDFH"},
139 {E1000_TDFT, "TDFT"},
140 {E1000_TDFHS, "TDFHS"},
141 {E1000_TDFTS, "TDFTS"},
142 {E1000_TDFPC, "TDFPC"},
143
144 /* List Terminator */
f36bb6ca 145 {0, NULL}
84f4ee90
TI		 146};
147
148/*
149 * e1000_regdump - register printout routine
150 */
151static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
152{
153 int n = 0;
154 char rname[16];
155 u32 regs[8];
156
157 switch (reginfo->ofs) {
158 case E1000_RXDCTL(0):
159 for (n = 0; n < 2; n++)
160 regs[n] = __er32(hw, E1000_RXDCTL(n));
161 break;
162 case E1000_TXDCTL(0):
163 for (n = 0; n < 2; n++)
164 regs[n] = __er32(hw, E1000_TXDCTL(n));
165 break;
166 case E1000_TARC(0):
167 for (n = 0; n < 2; n++)
168 regs[n] = __er32(hw, E1000_TARC(n));
169 break;
170 default:
ef456f85
JK		 171 pr_info("%-15s %08x\n",
172 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 173 return;
174 }
175
176 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 177 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 178}
179
84f4ee90 180/*
af667a29 181 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 182 */
183static void e1000e_dump(struct e1000_adapter *adapter)
184{
185 struct net_device *netdev = adapter->netdev;
186 struct e1000_hw *hw = &adapter->hw;
187 struct e1000_reg_info *reginfo;
188 struct e1000_ring *tx_ring = adapter->tx_ring;
189 struct e1000_tx_desc *tx_desc;
af667a29 190 struct my_u0 {
e885d762
BA		 191 __le64 a;
192 __le64 b;
af667a29 193 } *u0;
84f4ee90
TI		 194 struct e1000_buffer *buffer_info;
195 struct e1000_ring *rx_ring = adapter->rx_ring;
196 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 197 union e1000_rx_desc_extended *rx_desc;
af667a29 198 struct my_u1 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
201 __le64 c;
202 __le64 d;
af667a29 203 } *u1;
84f4ee90
TI		 204 u32 staterr;
205 int i = 0;
206
207 if (!netif_msg_hw(adapter))
208 return;
209
210 /* Print netdevice Info */
211 if (netdev) {
212 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 213 pr_info("Device Name state trans_start last_rx\n");
214 pr_info("%-15s %016lX %016lX %016lX\n",
215 netdev->name, netdev->state, netdev->trans_start,
216 netdev->last_rx);
84f4ee90
TI		 217 }
218
219 /* Print Registers */
220 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 221 pr_info(" Register Name Value\n");
84f4ee90
TI		 222 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
223 reginfo->name; reginfo++) {
224 e1000_regdump(hw, reginfo);
225 }
226
af667a29 227 /* Print Tx Ring Summary */
84f4ee90 228 if (!netdev || !netif_running(netdev))
fe1e980f 229 return;
84f4ee90 230
af667a29 231 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 232 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 233 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 234 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
235 0, tx_ring->next_to_use, tx_ring->next_to_clean,
236 (unsigned long long)buffer_info->dma,
237 buffer_info->length,
238 buffer_info->next_to_watch,
239 (unsigned long long)buffer_info->time_stamp);
84f4ee90 240
af667a29 241 /* Print Tx Ring */
84f4ee90
TI		 242 if (!netif_msg_tx_done(adapter))
243 goto rx_ring_summary;
244
af667a29 245 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 246
247 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
248 *
249 * Legacy Transmit Descriptor
250 * +--------------------------------------------------------------+
251 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
252 * +--------------------------------------------------------------+
253 * 8 | Special | CSS | Status | CMD | CSO | Length |
254 * +--------------------------------------------------------------+
255 * 63 48 47 36 35 32 31 24 23 16 15 0
256 *
257 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
258 * 63 48 47 40 39 32 31 16 15 8 7 0
259 * +----------------------------------------------------------------+
260 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
261 * +----------------------------------------------------------------+
262 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
263 * +----------------------------------------------------------------+
264 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
265 *
266 * Extended Data Descriptor (DTYP=0x1)
267 * +----------------------------------------------------------------+
268 * 0 | Buffer Address [63:0] |
269 * +----------------------------------------------------------------+
270 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 */
ef456f85
JK		 274 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
275 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
276 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 277 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 278 const char *next_desc;
84f4ee90
TI		 279 tx_desc = E1000_TX_DESC(*tx_ring, i);
280 buffer_info = &tx_ring->buffer_info[i];
281 u0 = (struct my_u0 *)tx_desc;
84f4ee90 282 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 283 next_desc = " NTC/U";
84f4ee90 284 else if (i == tx_ring->next_to_use)
ef456f85 285 next_desc = " NTU";
84f4ee90 286 else if (i == tx_ring->next_to_clean)
ef456f85 287 next_desc = " NTC";
84f4ee90 288 else
ef456f85
JK		 289 next_desc = "";
290 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
291 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
292 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
293 i,
294 (unsigned long long)le64_to_cpu(u0->a),
295 (unsigned long long)le64_to_cpu(u0->b),
296 (unsigned long long)buffer_info->dma,
297 buffer_info->length, buffer_info->next_to_watch,
298 (unsigned long long)buffer_info->time_stamp,
299 buffer_info->skb, next_desc);
84f4ee90
TI		 300
301 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
302 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 303 16, 1, phys_to_virt(buffer_info->dma),
304 buffer_info->length, true);
84f4ee90
TI		 305 }
306
af667a29 307 /* Print Rx Ring Summary */
84f4ee90 308rx_ring_summary:
af667a29 309 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 310 pr_info("Queue [NTU] [NTC]\n");
311 pr_info(" %5d %5X %5X\n",
312 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 313
af667a29 314 /* Print Rx Ring */
84f4ee90 315 if (!netif_msg_rx_status(adapter))
fe1e980f 316 return;
84f4ee90 317
af667a29 318 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 319 switch (adapter->rx_ps_pages) {
320 case 1:
321 case 2:
322 case 3:
323 /* [Extended] Packet Split Receive Descriptor Format
324 *
325 * +-----------------------------------------------------+
326 * 0 | Buffer Address 0 [63:0] |
327 * +-----------------------------------------------------+
328 * 8 | Buffer Address 1 [63:0] |
329 * +-----------------------------------------------------+
330 * 16 | Buffer Address 2 [63:0] |
331 * +-----------------------------------------------------+
332 * 24 | Buffer Address 3 [63:0] |
333 * +-----------------------------------------------------+
334 */
ef456f85 335 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 336 /* [Extended] Receive Descriptor (Write-Back) Format
337 *
338 * 63 48 47 32 31 13 12 8 7 4 3 0
339 * +------------------------------------------------------+
340 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
341 * | Checksum | Ident | | Queue | | Type |
342 * +------------------------------------------------------+
343 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
344 * +------------------------------------------------------+
345 * 63 48 47 32 31 20 19 0
346 */
ef456f85 347 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 348 for (i = 0; i < rx_ring->count; i++) {
ef456f85 349 const char *next_desc;
84f4ee90
TI		 350 buffer_info = &rx_ring->buffer_info[i];
351 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
352 u1 = (struct my_u1 *)rx_desc_ps;
353 staterr =
af667a29 354 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 355
356 if (i == rx_ring->next_to_use)
357 next_desc = " NTU";
358 else if (i == rx_ring->next_to_clean)
359 next_desc = " NTC";
360 else
361 next_desc = "";
362
84f4ee90
TI		 363 if (staterr & E1000_RXD_STAT_DD) {
364 /* Descriptor Done */
ef456f85
JK		 365 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
366 "RWB", i,
367 (unsigned long long)le64_to_cpu(u1->a),
368 (unsigned long long)le64_to_cpu(u1->b),
369 (unsigned long long)le64_to_cpu(u1->c),
370 (unsigned long long)le64_to_cpu(u1->d),
371 buffer_info->skb, next_desc);
84f4ee90 372 } else {
ef456f85
JK		 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
374 "R ", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 (unsigned long long)buffer_info->dma,
380 buffer_info->skb, next_desc);
84f4ee90
TI		 381
382 if (netif_msg_pktdata(adapter))
383 print_hex_dump(KERN_INFO, "",
384 DUMP_PREFIX_ADDRESS, 16, 1,
385 phys_to_virt(buffer_info->dma),
386 adapter->rx_ps_bsize0, true);
387 }
84f4ee90
TI		 388 }
389 break;
390 default:
391 case 0:
5f450212 392 /* Extended Receive Descriptor (Read) Format
84f4ee90 393 *
5f450212
BA		 394 * +-----------------------------------------------------+
395 * 0 | Buffer Address [63:0] |
396 * +-----------------------------------------------------+
397 * 8 | Reserved |
398 * +-----------------------------------------------------+
84f4ee90 399 */
ef456f85 400 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 401 /* Extended Receive Descriptor (Write-Back) Format
402 *
403 * 63 48 47 32 31 24 23 4 3 0
404 * +------------------------------------------------------+
405 * | RSS Hash | | | |
406 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
407 * | Packet | IP | | | Type |
408 * | Checksum | Ident | | | |
409 * +------------------------------------------------------+
410 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
411 * +------------------------------------------------------+
412 * 63 48 47 32 31 20 19 0
413 */
ef456f85 414 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 415
416 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 417 const char *next_desc;
418
84f4ee90 419 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 420 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
421 u1 = (struct my_u1 *)rx_desc;
422 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 423
424 if (i == rx_ring->next_to_use)
425 next_desc = " NTU";
426 else if (i == rx_ring->next_to_clean)
427 next_desc = " NTC";
428 else
429 next_desc = "";
430
5f450212
BA		 431 if (staterr & E1000_RXD_STAT_DD) {
432 /* Descriptor Done */
ef456f85
JK		 433 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
434 "RWB", i,
435 (unsigned long long)le64_to_cpu(u1->a),
436 (unsigned long long)le64_to_cpu(u1->b),
437 buffer_info->skb, next_desc);
5f450212 438 } else {
ef456f85
JK		 439 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
440 "R ", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 (unsigned long long)buffer_info->dma,
444 buffer_info->skb, next_desc);
5f450212
BA		 445
446 if (netif_msg_pktdata(adapter))
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16,
449 1,
450 phys_to_virt
451 (buffer_info->dma),
452 adapter->rx_buffer_len,
453 true);
454 }
84f4ee90
TI		 455 }
456 }
84f4ee90
TI		 457}
458
bc7f75fa
AK		 459/**
460 * e1000_desc_unused - calculate if we have unused descriptors
461 **/
462static int e1000_desc_unused(struct e1000_ring *ring)
463{
464 if (ring->next_to_clean > ring->next_to_use)
465 return ring->next_to_clean - ring->next_to_use - 1;
466
467 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
468}
469
470/**
ad68076e 471 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 472 * @adapter: board private structure
473 * @status: descriptor status field as written by hardware
474 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
475 * @skb: pointer to sk_buff to be indicated to stack
476 **/
477static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 478 struct net_device *netdev, struct sk_buff *skb,
a39fe742 479 u8 status, __le16 vlan)
bc7f75fa 480{
86d70e53 481 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 482 skb->protocol = eth_type_trans(skb, netdev);
483
86d70e53
JK		 484 if (status & E1000_RXD_STAT_VP)
485 __vlan_hwaccel_put_tag(skb, tag);
486
487 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 488}
489
490/**
af667a29 491 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 492 * @adapter: board private structure
493 * @status_err: receive descriptor status and error fields
494 * @csum: receive descriptor csum field
495 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 496 **/
497static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 498 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 499{
500 u16 status = (u16)status_err;
501 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 502
503 skb_checksum_none_assert(skb);
bc7f75fa 504
afd12939
BA		 505 /* Rx checksum disabled */
506 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
507 return;
508
bc7f75fa
AK		 509 /* Ignore Checksum bit is set */
510 if (status & E1000_RXD_STAT_IXSM)
511 return;
afd12939 512
bc7f75fa
AK		 513 /* TCP/UDP checksum error bit is set */
514 if (errors & E1000_RXD_ERR_TCPE) {
515 /* let the stack verify checksum errors */
516 adapter->hw_csum_err++;
517 return;
518 }
519
520 /* TCP/UDP Checksum has not been calculated */
521 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
522 return;
523
524 /* It must be a TCP or UDP packet with a valid checksum */
525 if (status & E1000_RXD_STAT_TCPCS) {
526 /* TCP checksum is good */
527 skb->ip_summed = CHECKSUM_UNNECESSARY;
528 } else {
ad68076e
BA		 529 /*
530 * IP fragment with UDP payload
531 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 532 * and then put the value in host order for further stack use.
533 */
afd12939 534 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 535 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 536 skb->ip_summed = CHECKSUM_COMPLETE;
537 }
538 adapter->hw_csum_good++;
539}
540
55aa6985 541static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 542{
55aa6985 543 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 544 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 545 s32 ret_val = __ew32_prepare(hw);
546
547 writel(i, rx_ring->tail);
c6e7f51e 548
bdc125f7 549 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 550 u32 rctl = er32(RCTL);
551 ew32(RCTL, rctl & ~E1000_RCTL_EN);
552 e_err("ME firmware caused invalid RDT - resetting\n");
553 schedule_work(&adapter->reset_task);
554 }
555}
556
55aa6985 557static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 558{
55aa6985 559 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 560 struct e1000_hw *hw = &adapter->hw;
bdc125f7 561 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 562
bdc125f7
BA		 563 writel(i, tx_ring->tail);
564
565 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 566 u32 tctl = er32(TCTL);
567 ew32(TCTL, tctl & ~E1000_TCTL_EN);
568 e_err("ME firmware caused invalid TDT - resetting\n");
569 schedule_work(&adapter->reset_task);
570 }
571}
572
bc7f75fa 573/**
5f450212 574 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 575 * @rx_ring: Rx descriptor ring
bc7f75fa 576 **/
55aa6985 577static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 578 int cleaned_count, gfp_t gfp)
bc7f75fa 579{
55aa6985 580 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 581 struct net_device *netdev = adapter->netdev;
582 struct pci_dev *pdev = adapter->pdev;
5f450212 583 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 584 struct e1000_buffer *buffer_info;
585 struct sk_buff *skb;
586 unsigned int i;
89d71a66 587 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 588
589 i = rx_ring->next_to_use;
590 buffer_info = &rx_ring->buffer_info[i];
591
592 while (cleaned_count--) {
593 skb = buffer_info->skb;
594 if (skb) {
595 skb_trim(skb, 0);
596 goto map_skb;
597 }
598
c2fed996 599 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 600 if (!skb) {
601 /* Better luck next round */
602 adapter->alloc_rx_buff_failed++;
603 break;
604 }
605
bc7f75fa
AK		 606 buffer_info->skb = skb;
607map_skb:
0be3f55f 608 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 609 adapter->rx_buffer_len,
0be3f55f
NN		 610 DMA_FROM_DEVICE);
611 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 612 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 613 adapter->rx_dma_failed++;
614 break;
615 }
616
5f450212
BA		 617 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
618 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 619
50849d79
TH		 620 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
621 /*
622 * Force memory writes to complete before letting h/w
623 * know there are new descriptors to fetch. (Only
624 * applicable for weak-ordered memory model archs,
625 * such as IA-64).
626 */
627 wmb();
c6e7f51e 628 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 629 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 630 else
c5083cf6 631 writel(i, rx_ring->tail);
50849d79 632 }
bc7f75fa
AK		 633 i++;
634 if (i == rx_ring->count)
635 i = 0;
636 buffer_info = &rx_ring->buffer_info[i];
637 }
638
50849d79 639 rx_ring->next_to_use = i;
bc7f75fa
AK		 640}
641
642/**
643 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 644 * @rx_ring: Rx descriptor ring
bc7f75fa 645 **/
55aa6985 646static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 647 int cleaned_count, gfp_t gfp)
bc7f75fa 648{
55aa6985 649 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 653 struct e1000_buffer *buffer_info;
654 struct e1000_ps_page *ps_page;
655 struct sk_buff *skb;
656 unsigned int i, j;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
663
664 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 665 ps_page = &buffer_info->ps_pages[j];
666 if (j >= adapter->rx_ps_pages) {
667 /* all unused desc entries get hw null ptr */
af667a29
BA		 668 rx_desc->read.buffer_addr[j + 1] =
669 ~cpu_to_le64(0);
47f44e40
AK		 670 continue;
671 }
672 if (!ps_page->page) {
c2fed996 673 ps_page->page = alloc_page(gfp);
bc7f75fa 674 if (!ps_page->page) {
47f44e40
AK		 675 adapter->alloc_rx_buff_failed++;
676 goto no_buffers;
677 }
0be3f55f
NN		 678 ps_page->dma = dma_map_page(&pdev->dev,
679 ps_page->page,
680 0, PAGE_SIZE,
681 DMA_FROM_DEVICE);
682 if (dma_mapping_error(&pdev->dev,
683 ps_page->dma)) {
47f44e40 684 dev_err(&adapter->pdev->dev,
af667a29 685 "Rx DMA page map failed\n");
47f44e40
AK		 686 adapter->rx_dma_failed++;
687 goto no_buffers;
bc7f75fa 688 }
bc7f75fa 689 }
47f44e40
AK		 690 /*
691 * Refresh the desc even if buffer_addrs
692 * didn't change because each write-back
693 * erases this info.
694 */
af667a29
BA		 695 rx_desc->read.buffer_addr[j + 1] =
696 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 697 }
698
c2fed996
JK		 699 skb = __netdev_alloc_skb_ip_align(netdev,
700 adapter->rx_ps_bsize0,
701 gfp);
bc7f75fa
AK		 702
703 if (!skb) {
704 adapter->alloc_rx_buff_failed++;
705 break;
706 }
707
bc7f75fa 708 buffer_info->skb = skb;
0be3f55f 709 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 710 adapter->rx_ps_bsize0,
0be3f55f
NN		 711 DMA_FROM_DEVICE);
712 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 713 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 714 adapter->rx_dma_failed++;
715 /* cleanup skb */
716 dev_kfree_skb_any(skb);
717 buffer_info->skb = NULL;
718 break;
719 }
720
721 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
722
50849d79
TH		 723 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
724 /*
725 * Force memory writes to complete before letting h/w
726 * know there are new descriptors to fetch. (Only
727 * applicable for weak-ordered memory model archs,
728 * such as IA-64).
729 */
730 wmb();
c6e7f51e 731 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 732 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 733 else
c5083cf6 734 writel(i << 1, rx_ring->tail);
50849d79
TH		 735 }
736
bc7f75fa
AK		 737 i++;
738 if (i == rx_ring->count)
739 i = 0;
740 buffer_info = &rx_ring->buffer_info[i];
741 }
742
743no_buffers:
50849d79 744 rx_ring->next_to_use = i;
bc7f75fa
AK		 745}
746
97ac8cae
BA		 747/**
748 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 749 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 750 * @cleaned_count: number of buffers to allocate this pass
751 **/
752
55aa6985 753static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 754 int cleaned_count, gfp_t gfp)
97ac8cae 755{
55aa6985 756 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 757 struct net_device *netdev = adapter->netdev;
758 struct pci_dev *pdev = adapter->pdev;
5f450212 759 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 760 struct e1000_buffer *buffer_info;
761 struct sk_buff *skb;
762 unsigned int i;
89d71a66 763 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 764
765 i = rx_ring->next_to_use;
766 buffer_info = &rx_ring->buffer_info[i];
767
768 while (cleaned_count--) {
769 skb = buffer_info->skb;
770 if (skb) {
771 skb_trim(skb, 0);
772 goto check_page;
773 }
774
c2fed996 775 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 776 if (unlikely(!skb)) {
777 /* Better luck next round */
778 adapter->alloc_rx_buff_failed++;
779 break;
780 }
781
97ac8cae
BA		 782 buffer_info->skb = skb;
783check_page:
784 /* allocate a new page if necessary */
785 if (!buffer_info->page) {
c2fed996 786 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 787 if (unlikely(!buffer_info->page)) {
788 adapter->alloc_rx_buff_failed++;
789 break;
790 }
791 }
792
793 if (!buffer_info->dma)
0be3f55f 794 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 795 buffer_info->page, 0,
796 PAGE_SIZE,
0be3f55f 797 DMA_FROM_DEVICE);
97ac8cae 798
5f450212
BA		 799 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
800 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 801
802 if (unlikely(++i == rx_ring->count))
803 i = 0;
804 buffer_info = &rx_ring->buffer_info[i];
805 }
806
807 if (likely(rx_ring->next_to_use != i)) {
808 rx_ring->next_to_use = i;
809 if (unlikely(i-- == 0))
810 i = (rx_ring->count - 1);
811
812 /* Force memory writes to complete before letting h/w
813 * know there are new descriptors to fetch. (Only
814 * applicable for weak-ordered memory model archs,
815 * such as IA-64). */
816 wmb();
c6e7f51e 817 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 818 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 819 else
c5083cf6 820 writel(i, rx_ring->tail);
97ac8cae
BA		 821 }
822}
823
70495a50
BA		 824static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
825 struct sk_buff *skb)
826{
827 if (netdev->features & NETIF_F_RXHASH)
828 skb->rxhash = le32_to_cpu(rss);
829}
830
bc7f75fa 831/**
55aa6985
BA		 832 * e1000_clean_rx_irq - Send received data up the network stack
833 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 834 *
835 * the return value indicates whether actual cleaning was done, there
836 * is no guarantee that everything was cleaned
837 **/
55aa6985
BA		 838static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
839 int work_to_do)
bc7f75fa 840{
55aa6985 841 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 842 struct net_device *netdev = adapter->netdev;
843 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 844 struct e1000_hw *hw = &adapter->hw;
5f450212 845 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 846 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 847 u32 length, staterr;
bc7f75fa
AK		 848 unsigned int i;
849 int cleaned_count = 0;
3db1cd5c 850 bool cleaned = false;
bc7f75fa
AK		 851 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
852
853 i = rx_ring->next_to_clean;
5f450212
BA		 854 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
855 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 856 buffer_info = &rx_ring->buffer_info[i];
857
5f450212 858 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 859 struct sk_buff *skb;
bc7f75fa
AK		 860
861 if (*work_done >= work_to_do)
862 break;
863 (*work_done)++;
2d0bb1c1 864 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 865
bc7f75fa
AK		 866 skb = buffer_info->skb;
867 buffer_info->skb = NULL;
868
869 prefetch(skb->data - NET_IP_ALIGN);
870
871 i++;
872 if (i == rx_ring->count)
873 i = 0;
5f450212 874 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 875 prefetch(next_rxd);
876
877 next_buffer = &rx_ring->buffer_info[i];
878
3db1cd5c 879 cleaned = true;
bc7f75fa 880 cleaned_count++;
0be3f55f 881 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 882 buffer_info->dma,
883 adapter->rx_buffer_len,
0be3f55f 884 DMA_FROM_DEVICE);
bc7f75fa
AK		 885 buffer_info->dma = 0;
886
5f450212 887 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 888
b94b5028
JB		 889 /*
890 * !EOP means multiple descriptors were used to store a single
891 * packet, if that's the case we need to toss it. In fact, we
892 * need to toss every packet with the EOP bit clear and the
893 * next frame that _does_ have the EOP bit set, as it is by
894 * definition only a frame fragment
895 */
5f450212 896 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 897 adapter->flags2 |= FLAG2_IS_DISCARDING;
898
899 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 900 /* All receives must fit into a single buffer */
3bb99fe2 901 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 902 /* recycle */
903 buffer_info->skb = skb;
5f450212 904 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 905 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 906 goto next_desc;
907 }
908
cf955e6c
BG		 909 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
910 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 911 /* recycle */
912 buffer_info->skb = skb;
913 goto next_desc;
914 }
915
eb7c3adb 916 /* adjust length to remove Ethernet CRC */
0184039a
BG		 917 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
918 /* If configured to store CRC, don't subtract FCS,
919 * but keep the FCS bytes out of the total_rx_bytes
920 * counter
921 */
922 if (netdev->features & NETIF_F_RXFCS)
923 total_rx_bytes -= 4;
924 else
925 length -= 4;
926 }
eb7c3adb 927
bc7f75fa
AK		 928 total_rx_bytes += length;
929 total_rx_packets++;
930
ad68076e
BA		 931 /*
932 * code added for copybreak, this should improve
bc7f75fa 933 * performance for small packets with large amounts
ad68076e
BA		 934 * of reassembly being done in the stack
935 */
bc7f75fa
AK		 936 if (length < copybreak) {
937 struct sk_buff *new_skb =
89d71a66 938 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 939 if (new_skb) {
808ff676
BA		 940 skb_copy_to_linear_data_offset(new_skb,
941 -NET_IP_ALIGN,
942 (skb->data -
943 NET_IP_ALIGN),
944 (length +
945 NET_IP_ALIGN));
bc7f75fa
AK		 946 /* save the skb in buffer_info as good */
947 buffer_info->skb = skb;
948 skb = new_skb;
949 }
950 /* else just continue with the old one */
951 }
952 /* end copybreak code */
953 skb_put(skb, length);
954
955 /* Receive Checksum Offload */
5f450212 956 e1000_rx_checksum(adapter, staterr,
afd12939 957 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 958
70495a50
BA		 959 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
960
5f450212
BA		 961 e1000_receive_skb(adapter, netdev, skb, staterr,
962 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 963
964next_desc:
5f450212 965 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 966
967 /* return some buffers to hardware, one at a time is too slow */
968 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 969 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 970 GFP_ATOMIC);
bc7f75fa
AK		 971 cleaned_count = 0;
972 }
973
974 /* use prefetched values */
975 rx_desc = next_rxd;
976 buffer_info = next_buffer;
5f450212
BA		 977
978 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 979 }
980 rx_ring->next_to_clean = i;
981
982 cleaned_count = e1000_desc_unused(rx_ring);
983 if (cleaned_count)
55aa6985 984 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 985
bc7f75fa 986 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 987 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 988 return cleaned;
989}
990
55aa6985
BA		 991static void e1000_put_txbuf(struct e1000_ring *tx_ring,
992 struct e1000_buffer *buffer_info)
bc7f75fa 993{
55aa6985
BA		 994 struct e1000_adapter *adapter = tx_ring->adapter;
995
03b1320d
AD		 996 if (buffer_info->dma) {
997 if (buffer_info->mapped_as_page)
0be3f55f
NN		 998 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
999 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1000 else
0be3f55f
NN		 1001 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1002 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1003 buffer_info->dma = 0;
1004 }
bc7f75fa
AK		 1005 if (buffer_info->skb) {
1006 dev_kfree_skb_any(buffer_info->skb);
1007 buffer_info->skb = NULL;
1008 }
1b7719c4 1009 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1010}
1011
41cec6f1 1012static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1013{
41cec6f1
BA		 1014 struct e1000_adapter *adapter = container_of(work,
1015 struct e1000_adapter,
1016 print_hang_task);
09357b00 1017 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1018 struct e1000_ring *tx_ring = adapter->tx_ring;
1019 unsigned int i = tx_ring->next_to_clean;
1020 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1021 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1022 struct e1000_hw *hw = &adapter->hw;
1023 u16 phy_status, phy_1000t_status, phy_ext_status;
1024 u16 pci_status;
1025
615b32af
JB		 1026 if (test_bit(__E1000_DOWN, &adapter->state))
1027 return;
1028
09357b00
JK		 1029 if (!adapter->tx_hang_recheck &&
1030 (adapter->flags2 & FLAG2_DMA_BURST)) {
397c020a
MV		 1031 /*
1032 * May be block on write-back, flush and detect again
09357b00
JK		 1033 * flush pending descriptor writebacks to memory
1034 */
1035 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1036 /* execute the writes immediately */
1037 e1e_flush();
bf03085f
MV		 1038 /*
1039 * Due to rare timing issues, write to TIDV again to ensure
1040 * the write is successful
1041 */
1042 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1043 /* execute the writes immediately */
1044 e1e_flush();
09357b00
JK		 1045 adapter->tx_hang_recheck = true;
1046 return;
1047 }
1048 /* Real hang detected */
1049 adapter->tx_hang_recheck = false;
1050 netif_stop_queue(netdev);
1051
41cec6f1
BA		 1052 e1e_rphy(hw, PHY_STATUS, &phy_status);
1053 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1054 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1055
41cec6f1
BA		 1056 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1057
1058 /* detected Hardware unit hang */
1059 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1060 " TDH <%x>\n"
1061 " TDT <%x>\n"
1062 " next_to_use <%x>\n"
1063 " next_to_clean <%x>\n"
1064 "buffer_info[next_to_clean]:\n"
1065 " time_stamp <%lx>\n"
1066 " next_to_watch <%x>\n"
1067 " jiffies <%lx>\n"
41cec6f1
BA		 1068 " next_to_watch.status <%x>\n"
1069 "MAC Status <%x>\n"
1070 "PHY Status <%x>\n"
1071 "PHY 1000BASE-T Status <%x>\n"
1072 "PHY Extended Status <%x>\n"
1073 "PCI Status <%x>\n",
c5083cf6
BA		 1074 readl(tx_ring->head),
1075 readl(tx_ring->tail),
44defeb3
JK		 1076 tx_ring->next_to_use,
1077 tx_ring->next_to_clean,
1078 tx_ring->buffer_info[eop].time_stamp,
1079 eop,
1080 jiffies,
41cec6f1
BA		 1081 eop_desc->upper.fields.status,
1082 er32(STATUS),
1083 phy_status,
1084 phy_1000t_status,
1085 phy_ext_status,
1086 pci_status);
bc7f75fa
AK		 1087}
1088
1089/**
1090 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1091 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1092 *
1093 * the return value indicates whether actual cleaning was done, there
1094 * is no guarantee that everything was cleaned
1095 **/
55aa6985 1096static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1097{
55aa6985 1098 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1099 struct net_device *netdev = adapter->netdev;
1100 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1101 struct e1000_tx_desc *tx_desc, *eop_desc;
1102 struct e1000_buffer *buffer_info;
1103 unsigned int i, eop;
1104 unsigned int count = 0;
bc7f75fa 1105 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1106 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1107
1108 i = tx_ring->next_to_clean;
1109 eop = tx_ring->buffer_info[i].next_to_watch;
1110 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1111
12d04a3c
AD		 1112 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1113 (count < tx_ring->count)) {
a86043c2 1114 bool cleaned = false;
2d0bb1c1 1115 rmb(); /* read buffer_info after eop_desc */
a86043c2 1116 for (; !cleaned; count++) {
bc7f75fa
AK		 1117 tx_desc = E1000_TX_DESC(*tx_ring, i);
1118 buffer_info = &tx_ring->buffer_info[i];
1119 cleaned = (i == eop);
1120
1121 if (cleaned) {
9ed318d5
TH		 1122 total_tx_packets += buffer_info->segs;
1123 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1124 if (buffer_info->skb) {
1125 bytes_compl += buffer_info->skb->len;
1126 pkts_compl++;
1127 }
bc7f75fa
AK		 1128 }
1129
55aa6985 1130 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1131 tx_desc->upper.data = 0;
1132
1133 i++;
1134 if (i == tx_ring->count)
1135 i = 0;
1136 }
1137
dac87619
TL		 1138 if (i == tx_ring->next_to_use)
1139 break;
bc7f75fa
AK		 1140 eop = tx_ring->buffer_info[i].next_to_watch;
1141 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1142 }
1143
1144 tx_ring->next_to_clean = i;
1145
3f0cfa3b
TH		 1146 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1147
bc7f75fa 1148#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1149 if (count && netif_carrier_ok(netdev) &&
1150 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1151 /* Make sure that anybody stopping the queue after this
1152 * sees the new next_to_clean.
1153 */
1154 smp_mb();
1155
1156 if (netif_queue_stopped(netdev) &&
1157 !(test_bit(__E1000_DOWN, &adapter->state))) {
1158 netif_wake_queue(netdev);
1159 ++adapter->restart_queue;
1160 }
1161 }
1162
1163 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1164 /*
1165 * Detect a transmit hang in hardware, this serializes the
1166 * check with the clearing of time_stamp and movement of i
1167 */
3db1cd5c 1168 adapter->detect_tx_hung = false;
12d04a3c
AD		 1169 if (tx_ring->buffer_info[i].time_stamp &&
1170 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1171 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1172 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1173 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1174 else
1175 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1176 }
1177 adapter->total_tx_bytes += total_tx_bytes;
1178 adapter->total_tx_packets += total_tx_packets;
807540ba 1179 return count < tx_ring->count;
bc7f75fa
AK		 1180}
1181
bc7f75fa
AK		 1182/**
1183 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1184 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1185 *
1186 * the return value indicates whether actual cleaning was done, there
1187 * is no guarantee that everything was cleaned
1188 **/
55aa6985
BA		 1189static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1190 int work_to_do)
bc7f75fa 1191{
55aa6985 1192 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1193 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1194 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1195 struct net_device *netdev = adapter->netdev;
1196 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1197 struct e1000_buffer *buffer_info, *next_buffer;
1198 struct e1000_ps_page *ps_page;
1199 struct sk_buff *skb;
1200 unsigned int i, j;
1201 u32 length, staterr;
1202 int cleaned_count = 0;
3db1cd5c 1203 bool cleaned = false;
bc7f75fa
AK		 1204 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1205
1206 i = rx_ring->next_to_clean;
1207 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1208 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1209 buffer_info = &rx_ring->buffer_info[i];
1210
1211 while (staterr & E1000_RXD_STAT_DD) {
1212 if (*work_done >= work_to_do)
1213 break;
1214 (*work_done)++;
1215 skb = buffer_info->skb;
2d0bb1c1 1216 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1217
1218 /* in the packet split case this is header only */
1219 prefetch(skb->data - NET_IP_ALIGN);
1220
1221 i++;
1222 if (i == rx_ring->count)
1223 i = 0;
1224 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1225 prefetch(next_rxd);
1226
1227 next_buffer = &rx_ring->buffer_info[i];
1228
3db1cd5c 1229 cleaned = true;
bc7f75fa 1230 cleaned_count++;
0be3f55f 1231 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1232 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1233 buffer_info->dma = 0;
1234
af667a29 1235 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1236 if (!(staterr & E1000_RXD_STAT_EOP))
1237 adapter->flags2 |= FLAG2_IS_DISCARDING;
1238
1239 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1240 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1241 dev_kfree_skb_irq(skb);
b94b5028
JB		 1242 if (staterr & E1000_RXD_STAT_EOP)
1243 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1244 goto next_desc;
1245 }
1246
cf955e6c
BG		 1247 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1248 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1249 dev_kfree_skb_irq(skb);
1250 goto next_desc;
1251 }
1252
1253 length = le16_to_cpu(rx_desc->wb.middle.length0);
1254
1255 if (!length) {
ef456f85 1256 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1257 dev_kfree_skb_irq(skb);
1258 goto next_desc;
1259 }
1260
1261 /* Good Receive */
1262 skb_put(skb, length);
1263
1264 {
0e15df49
BA		 1265 /*
1266 * this looks ugly, but it seems compiler issues make
1267 * it more efficient than reusing j
1268 */
1269 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1270
ad68076e 1271 /*
0e15df49
BA		 1272 * page alloc/put takes too long and effects small
1273 * packet throughput, so unsplit small packets and
1274 * save the alloc/put only valid in softirq (napi)
1275 * context to call kmap_*
ad68076e 1276 */
0e15df49
BA		 1277 if (l1 && (l1 <= copybreak) &&
1278 ((length + l1) <= adapter->rx_ps_bsize0)) {
1279 u8 *vaddr;
1280
1281 ps_page = &buffer_info->ps_pages[0];
1282
1283 /*
1284 * there is no documentation about how to call
1285 * kmap_atomic, so we can't hold the mapping
1286 * very long
1287 */
1288 dma_sync_single_for_cpu(&pdev->dev,
1289 ps_page->dma,
1290 PAGE_SIZE,
1291 DMA_FROM_DEVICE);
9f393834 1292 vaddr = kmap_atomic(ps_page->page);
0e15df49 1293 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1294 kunmap_atomic(vaddr);
0e15df49
BA		 1295 dma_sync_single_for_device(&pdev->dev,
1296 ps_page->dma,
1297 PAGE_SIZE,
1298 DMA_FROM_DEVICE);
1299
1300 /* remove the CRC */
0184039a
BG		 1301 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1302 if (!(netdev->features & NETIF_F_RXFCS))
1303 l1 -= 4;
1304 }
0e15df49
BA		 1305
1306 skb_put(skb, l1);
1307 goto copydone;
1308 } /* if */
bc7f75fa
AK		 1309 }
1310
1311 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1312 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1313 if (!length)
1314 break;
1315
47f44e40 1316 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1317 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1318 DMA_FROM_DEVICE);
bc7f75fa
AK		 1319 ps_page->dma = 0;
1320 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1321 ps_page->page = NULL;
1322 skb->len += length;
1323 skb->data_len += length;
98a045d7 1324 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1325 }
1326
eb7c3adb
JK		 1327 /* strip the ethernet crc, problem is we're using pages now so
1328 * this whole operation can get a little cpu intensive
1329 */
0184039a
BG		 1330 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1331 if (!(netdev->features & NETIF_F_RXFCS))
1332 pskb_trim(skb, skb->len - 4);
1333 }
eb7c3adb 1334
bc7f75fa
AK		 1335copydone:
1336 total_rx_bytes += skb->len;
1337 total_rx_packets++;
1338
afd12939
BA		 1339 e1000_rx_checksum(adapter, staterr,
1340 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1341
70495a50
BA		 1342 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1343
bc7f75fa
AK		 1344 if (rx_desc->wb.upper.header_status &
1345 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1346 adapter->rx_hdr_split++;
1347
1348 e1000_receive_skb(adapter, netdev, skb,
1349 staterr, rx_desc->wb.middle.vlan);
1350
1351next_desc:
1352 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1353 buffer_info->skb = NULL;
1354
1355 /* return some buffers to hardware, one at a time is too slow */
1356 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1357 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1358 GFP_ATOMIC);
bc7f75fa
AK		 1359 cleaned_count = 0;
1360 }
1361
1362 /* use prefetched values */
1363 rx_desc = next_rxd;
1364 buffer_info = next_buffer;
1365
1366 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1367 }
1368 rx_ring->next_to_clean = i;
1369
1370 cleaned_count = e1000_desc_unused(rx_ring);
1371 if (cleaned_count)
55aa6985 1372 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1373
bc7f75fa 1374 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1375 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1376 return cleaned;
1377}
1378
97ac8cae
BA		 1379/**
1380 * e1000_consume_page - helper function
1381 **/
1382static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1383 u16 length)
1384{
1385 bi->page = NULL;
1386 skb->len += length;
1387 skb->data_len += length;
98a045d7 1388 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1389}
1390
1391/**
1392 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1393 * @adapter: board private structure
1394 *
1395 * the return value indicates whether actual cleaning was done, there
1396 * is no guarantee that everything was cleaned
1397 **/
55aa6985
BA		 1398static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1399 int work_to_do)
97ac8cae 1400{
55aa6985 1401 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1402 struct net_device *netdev = adapter->netdev;
1403 struct pci_dev *pdev = adapter->pdev;
5f450212 1404 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1405 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1406 u32 length, staterr;
97ac8cae
BA		 1407 unsigned int i;
1408 int cleaned_count = 0;
1409 bool cleaned = false;
1410 unsigned int total_rx_bytes=0, total_rx_packets=0;
1411
1412 i = rx_ring->next_to_clean;
5f450212
BA		 1413 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1414 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1415 buffer_info = &rx_ring->buffer_info[i];
1416
5f450212 1417 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1418 struct sk_buff *skb;
97ac8cae
BA		 1419
1420 if (*work_done >= work_to_do)
1421 break;
1422 (*work_done)++;
2d0bb1c1 1423 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1424
97ac8cae
BA		 1425 skb = buffer_info->skb;
1426 buffer_info->skb = NULL;
1427
1428 ++i;
1429 if (i == rx_ring->count)
1430 i = 0;
5f450212 1431 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1432 prefetch(next_rxd);
1433
1434 next_buffer = &rx_ring->buffer_info[i];
1435
1436 cleaned = true;
1437 cleaned_count++;
0be3f55f
NN		 1438 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1439 DMA_FROM_DEVICE);
97ac8cae
BA		 1440 buffer_info->dma = 0;
1441
5f450212 1442 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1443
1444 /* errors is only valid for DD + EOP descriptors */
5f450212 1445 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1446 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1447 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1448 /* recycle both page and skb */
1449 buffer_info->skb = skb;
1450 /* an error means any chain goes out the window too */
1451 if (rx_ring->rx_skb_top)
1452 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1453 rx_ring->rx_skb_top = NULL;
1454 goto next_desc;
97ac8cae
BA		 1455 }
1456
f0f1a172 1457#define rxtop (rx_ring->rx_skb_top)
5f450212 1458 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1459 /* this descriptor is only the beginning (or middle) */
1460 if (!rxtop) {
1461 /* this is the beginning of a chain */
1462 rxtop = skb;
1463 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1464 0, length);
1465 } else {
1466 /* this is the middle of a chain */
1467 skb_fill_page_desc(rxtop,
1468 skb_shinfo(rxtop)->nr_frags,
1469 buffer_info->page, 0, length);
1470 /* re-use the skb, only consumed the page */
1471 buffer_info->skb = skb;
1472 }
1473 e1000_consume_page(buffer_info, rxtop, length);
1474 goto next_desc;
1475 } else {
1476 if (rxtop) {
1477 /* end of the chain */
1478 skb_fill_page_desc(rxtop,
1479 skb_shinfo(rxtop)->nr_frags,
1480 buffer_info->page, 0, length);
1481 /* re-use the current skb, we only consumed the
1482 * page */
1483 buffer_info->skb = skb;
1484 skb = rxtop;
1485 rxtop = NULL;
1486 e1000_consume_page(buffer_info, skb, length);
1487 } else {
1488 /* no chain, got EOP, this buf is the packet
1489 * copybreak to save the put_page/alloc_page */
1490 if (length <= copybreak &&
1491 skb_tailroom(skb) >= length) {
1492 u8 *vaddr;
4679026d 1493 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1494 memcpy(skb_tail_pointer(skb), vaddr,
1495 length);
4679026d 1496 kunmap_atomic(vaddr);
97ac8cae
BA		 1497 /* re-use the page, so don't erase
1498 * buffer_info->page */
1499 skb_put(skb, length);
1500 } else {
1501 skb_fill_page_desc(skb, 0,
1502 buffer_info->page, 0,
1503 length);
1504 e1000_consume_page(buffer_info, skb,
1505 length);
1506 }
1507 }
1508 }
1509
1510 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1511 e1000_rx_checksum(adapter, staterr,
afd12939 1512 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1513
70495a50
BA		 1514 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1515
97ac8cae
BA		 1516 /* probably a little skewed due to removing CRC */
1517 total_rx_bytes += skb->len;
1518 total_rx_packets++;
1519
1520 /* eth type trans needs skb->data to point to something */
1521 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1522 e_err("pskb_may_pull failed.\n");
ef5ab89c 1523 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1524 goto next_desc;
1525 }
1526
5f450212
BA		 1527 e1000_receive_skb(adapter, netdev, skb, staterr,
1528 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1529
1530next_desc:
5f450212 1531 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1532
1533 /* return some buffers to hardware, one at a time is too slow */
1534 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1535 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1536 GFP_ATOMIC);
97ac8cae
BA		 1537 cleaned_count = 0;
1538 }
1539
1540 /* use prefetched values */
1541 rx_desc = next_rxd;
1542 buffer_info = next_buffer;
5f450212
BA		 1543
1544 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1545 }
1546 rx_ring->next_to_clean = i;
1547
1548 cleaned_count = e1000_desc_unused(rx_ring);
1549 if (cleaned_count)
55aa6985 1550 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1551
1552 adapter->total_rx_bytes += total_rx_bytes;
1553 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1554 return cleaned;
1555}
1556
bc7f75fa
AK		 1557/**
1558 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1559 * @rx_ring: Rx descriptor ring
bc7f75fa 1560 **/
55aa6985 1561static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1562{
55aa6985 1563 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1564 struct e1000_buffer *buffer_info;
1565 struct e1000_ps_page *ps_page;
1566 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1567 unsigned int i, j;
1568
1569 /* Free all the Rx ring sk_buffs */
1570 for (i = 0; i < rx_ring->count; i++) {
1571 buffer_info = &rx_ring->buffer_info[i];
1572 if (buffer_info->dma) {
1573 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1574 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1575 adapter->rx_buffer_len,
0be3f55f 1576 DMA_FROM_DEVICE);
97ac8cae 1577 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1578 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1579 PAGE_SIZE,
0be3f55f 1580 DMA_FROM_DEVICE);
bc7f75fa 1581 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1582 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1583 adapter->rx_ps_bsize0,
0be3f55f 1584 DMA_FROM_DEVICE);
bc7f75fa
AK		 1585 buffer_info->dma = 0;
1586 }
1587
97ac8cae
BA		 1588 if (buffer_info->page) {
1589 put_page(buffer_info->page);
1590 buffer_info->page = NULL;
1591 }
1592
bc7f75fa
AK		 1593 if (buffer_info->skb) {
1594 dev_kfree_skb(buffer_info->skb);
1595 buffer_info->skb = NULL;
1596 }
1597
1598 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1599 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1600 if (!ps_page->page)
1601 break;
0be3f55f
NN		 1602 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1603 DMA_FROM_DEVICE);
bc7f75fa
AK		 1604 ps_page->dma = 0;
1605 put_page(ps_page->page);
1606 ps_page->page = NULL;
1607 }
1608 }
1609
1610 /* there also may be some cached data from a chained receive */
1611 if (rx_ring->rx_skb_top) {
1612 dev_kfree_skb(rx_ring->rx_skb_top);
1613 rx_ring->rx_skb_top = NULL;
1614 }
1615
bc7f75fa
AK		 1616 /* Zero out the descriptor ring */
1617 memset(rx_ring->desc, 0, rx_ring->size);
1618
1619 rx_ring->next_to_clean = 0;
1620 rx_ring->next_to_use = 0;
b94b5028 1621 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1622
c5083cf6 1623 writel(0, rx_ring->head);
bdc125f7
BA		 1624 if (rx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
1625 e1000e_update_rdt_wa(rx_ring, 0);
1626 else
1627 writel(0, rx_ring->tail);
bc7f75fa
AK		 1628}
1629
a8f88ff5
JB		 1630static void e1000e_downshift_workaround(struct work_struct *work)
1631{
1632 struct e1000_adapter *adapter = container_of(work,
1633 struct e1000_adapter, downshift_task);
1634
615b32af
JB		 1635 if (test_bit(__E1000_DOWN, &adapter->state))
1636 return;
1637
a8f88ff5
JB		 1638 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1639}
1640
bc7f75fa
AK		 1641/**
1642 * e1000_intr_msi - Interrupt Handler
1643 * @irq: interrupt number
1644 * @data: pointer to a network interface device structure
1645 **/
1646static irqreturn_t e1000_intr_msi(int irq, void *data)
1647{
1648 struct net_device *netdev = data;
1649 struct e1000_adapter *adapter = netdev_priv(netdev);
1650 struct e1000_hw *hw = &adapter->hw;
1651 u32 icr = er32(ICR);
1652
ad68076e
BA		 1653 /*
1654 * read ICR disables interrupts using IAM
1655 */
bc7f75fa 1656
573cca8c 1657 if (icr & E1000_ICR_LSC) {
f92518dd 1658 hw->mac.get_link_status = true;
ad68076e
BA		 1659 /*
1660 * ICH8 workaround-- Call gig speed drop workaround on cable
1661 * disconnect (LSC) before accessing any PHY registers
1662 */
bc7f75fa
AK		 1663 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1664 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1665 schedule_work(&adapter->downshift_task);
bc7f75fa 1666
ad68076e
BA		 1667 /*
1668 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1669 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1670 * adapter in watchdog
1671 */
bc7f75fa
AK		 1672 if (netif_carrier_ok(netdev) &&
1673 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1674 /* disable receives */
1675 u32 rctl = er32(RCTL);
1676 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1677 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1678 }
1679 /* guard against interrupt when we're going down */
1680 if (!test_bit(__E1000_DOWN, &adapter->state))
1681 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1682 }
1683
288379f0 1684 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1685 adapter->total_tx_bytes = 0;
1686 adapter->total_tx_packets = 0;
1687 adapter->total_rx_bytes = 0;
1688 adapter->total_rx_packets = 0;
288379f0 1689 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1690 }
1691
1692 return IRQ_HANDLED;
1693}
1694
1695/**
1696 * e1000_intr - Interrupt Handler
1697 * @irq: interrupt number
1698 * @data: pointer to a network interface device structure
1699 **/
1700static irqreturn_t e1000_intr(int irq, void *data)
1701{
1702 struct net_device *netdev = data;
1703 struct e1000_adapter *adapter = netdev_priv(netdev);
1704 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1705 u32 rctl, icr = er32(ICR);
4662e82b 1706
a68ea775 1707 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1708 return IRQ_NONE; /* Not our interrupt */
1709
ad68076e
BA		 1710 /*
1711 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1712 * not set, then the adapter didn't send an interrupt
1713 */
bc7f75fa
AK		 1714 if (!(icr & E1000_ICR_INT_ASSERTED))
1715 return IRQ_NONE;
1716
ad68076e
BA		 1717 /*
1718 * Interrupt Auto-Mask...upon reading ICR,
1719 * interrupts are masked. No need for the
1720 * IMC write
1721 */
bc7f75fa 1722
573cca8c 1723 if (icr & E1000_ICR_LSC) {
f92518dd 1724 hw->mac.get_link_status = true;
ad68076e
BA		 1725 /*
1726 * ICH8 workaround-- Call gig speed drop workaround on cable
1727 * disconnect (LSC) before accessing any PHY registers
1728 */
bc7f75fa
AK		 1729 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1730 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1731 schedule_work(&adapter->downshift_task);
bc7f75fa 1732
ad68076e
BA		 1733 /*
1734 * 80003ES2LAN workaround--
bc7f75fa
AK		 1735 * For packet buffer work-around on link down event;
1736 * disable receives here in the ISR and
1737 * reset adapter in watchdog
1738 */
1739 if (netif_carrier_ok(netdev) &&
1740 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1741 /* disable receives */
1742 rctl = er32(RCTL);
1743 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1744 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1745 }
1746 /* guard against interrupt when we're going down */
1747 if (!test_bit(__E1000_DOWN, &adapter->state))
1748 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1749 }
1750
288379f0 1751 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1752 adapter->total_tx_bytes = 0;
1753 adapter->total_tx_packets = 0;
1754 adapter->total_rx_bytes = 0;
1755 adapter->total_rx_packets = 0;
288379f0 1756 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1757 }
1758
1759 return IRQ_HANDLED;
1760}
1761
4662e82b
BA		 1762static irqreturn_t e1000_msix_other(int irq, void *data)
1763{
1764 struct net_device *netdev = data;
1765 struct e1000_adapter *adapter = netdev_priv(netdev);
1766 struct e1000_hw *hw = &adapter->hw;
1767 u32 icr = er32(ICR);
1768
1769 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1770 if (!test_bit(__E1000_DOWN, &adapter->state))
1771 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1772 return IRQ_NONE;
1773 }
1774
1775 if (icr & adapter->eiac_mask)
1776 ew32(ICS, (icr & adapter->eiac_mask));
1777
1778 if (icr & E1000_ICR_OTHER) {
1779 if (!(icr & E1000_ICR_LSC))
1780 goto no_link_interrupt;
f92518dd 1781 hw->mac.get_link_status = true;
4662e82b
BA		 1782 /* guard against interrupt when we're going down */
1783 if (!test_bit(__E1000_DOWN, &adapter->state))
1784 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1785 }
1786
1787no_link_interrupt:
a3c69fef
JB		 1788 if (!test_bit(__E1000_DOWN, &adapter->state))
1789 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1790
1791 return IRQ_HANDLED;
1792}
1793
1794
1795static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1796{
1797 struct net_device *netdev = data;
1798 struct e1000_adapter *adapter = netdev_priv(netdev);
1799 struct e1000_hw *hw = &adapter->hw;
1800 struct e1000_ring *tx_ring = adapter->tx_ring;
1801
1802
1803 adapter->total_tx_bytes = 0;
1804 adapter->total_tx_packets = 0;
1805
55aa6985 1806 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1807 /* Ring was not completely cleaned, so fire another interrupt */
1808 ew32(ICS, tx_ring->ims_val);
1809
1810 return IRQ_HANDLED;
1811}
1812
1813static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1814{
1815 struct net_device *netdev = data;
1816 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1817 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1818
1819 /* Write the ITR value calculated at the end of the
1820 * previous interrupt.
1821 */
55aa6985
BA		 1822 if (rx_ring->set_itr) {
1823 writel(1000000000 / (rx_ring->itr_val * 256),
1824 rx_ring->itr_register);
1825 rx_ring->set_itr = 0;
4662e82b
BA		 1826 }
1827
288379f0 1828 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1829 adapter->total_rx_bytes = 0;
1830 adapter->total_rx_packets = 0;
288379f0 1831 __napi_schedule(&adapter->napi);
4662e82b
BA		 1832 }
1833 return IRQ_HANDLED;
1834}
1835
1836/**
1837 * e1000_configure_msix - Configure MSI-X hardware
1838 *
1839 * e1000_configure_msix sets up the hardware to properly
1840 * generate MSI-X interrupts.
1841 **/
1842static void e1000_configure_msix(struct e1000_adapter *adapter)
1843{
1844 struct e1000_hw *hw = &adapter->hw;
1845 struct e1000_ring *rx_ring = adapter->rx_ring;
1846 struct e1000_ring *tx_ring = adapter->tx_ring;
1847 int vector = 0;
1848 u32 ctrl_ext, ivar = 0;
1849
1850 adapter->eiac_mask = 0;
1851
1852 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1853 if (hw->mac.type == e1000_82574) {
1854 u32 rfctl = er32(RFCTL);
1855 rfctl |= E1000_RFCTL_ACK_DIS;
1856 ew32(RFCTL, rfctl);
1857 }
1858
1859#define E1000_IVAR_INT_ALLOC_VALID 0x8
1860 /* Configure Rx vector */
1861 rx_ring->ims_val = E1000_IMS_RXQ0;
1862 adapter->eiac_mask |= rx_ring->ims_val;
1863 if (rx_ring->itr_val)
1864 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1865 rx_ring->itr_register);
4662e82b 1866 else
c5083cf6 1867 writel(1, rx_ring->itr_register);
4662e82b
BA		 1868 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1869
1870 /* Configure Tx vector */
1871 tx_ring->ims_val = E1000_IMS_TXQ0;
1872 vector++;
1873 if (tx_ring->itr_val)
1874 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1875 tx_ring->itr_register);
4662e82b 1876 else
c5083cf6 1877 writel(1, tx_ring->itr_register);
4662e82b
BA		 1878 adapter->eiac_mask |= tx_ring->ims_val;
1879 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1880
1881 /* set vector for Other Causes, e.g. link changes */
1882 vector++;
1883 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1884 if (rx_ring->itr_val)
1885 writel(1000000000 / (rx_ring->itr_val * 256),
1886 hw->hw_addr + E1000_EITR_82574(vector));
1887 else
1888 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1889
1890 /* Cause Tx interrupts on every write back */
1891 ivar |= (1 << 31);
1892
1893 ew32(IVAR, ivar);
1894
1895 /* enable MSI-X PBA support */
1896 ctrl_ext = er32(CTRL_EXT);
1897 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1898
1899 /* Auto-Mask Other interrupts upon ICR read */
1900#define E1000_EIAC_MASK_82574 0x01F00000
1901 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1902 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1903 ew32(CTRL_EXT, ctrl_ext);
1904 e1e_flush();
1905}
1906
1907void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1908{
1909 if (adapter->msix_entries) {
1910 pci_disable_msix(adapter->pdev);
1911 kfree(adapter->msix_entries);
1912 adapter->msix_entries = NULL;
1913 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1914 pci_disable_msi(adapter->pdev);
1915 adapter->flags &= ~FLAG_MSI_ENABLED;
1916 }
4662e82b
BA		 1917}
1918
1919/**
1920 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1921 *
1922 * Attempt to configure interrupts using the best available
1923 * capabilities of the hardware and kernel.
1924 **/
1925void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1926{
1927 int err;
8e86acd7 1928 int i;
4662e82b
BA		 1929
1930 switch (adapter->int_mode) {
1931 case E1000E_INT_MODE_MSIX:
1932 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1933 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1934 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1935 sizeof(struct msix_entry),
1936 GFP_KERNEL);
1937 if (adapter->msix_entries) {
8e86acd7 1938 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1939 adapter->msix_entries[i].entry = i;
1940
1941 err = pci_enable_msix(adapter->pdev,
1942 adapter->msix_entries,
8e86acd7 1943 adapter->num_vectors);
b1cdfead 1944 if (err == 0)
4662e82b
BA		 1945 return;
1946 }
1947 /* MSI-X failed, so fall through and try MSI */
ef456f85 1948 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1949 e1000e_reset_interrupt_capability(adapter);
1950 }
1951 adapter->int_mode = E1000E_INT_MODE_MSI;
1952 /* Fall through */
1953 case E1000E_INT_MODE_MSI:
1954 if (!pci_enable_msi(adapter->pdev)) {
1955 adapter->flags |= FLAG_MSI_ENABLED;
1956 } else {
1957 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1958 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1959 }
1960 /* Fall through */
1961 case E1000E_INT_MODE_LEGACY:
1962 /* Don't do anything; this is the system default */
1963 break;
1964 }
8e86acd7
JK		 1965
1966 /* store the number of vectors being used */
1967 adapter->num_vectors = 1;
4662e82b
BA		 1968}
1969
1970/**
1971 * e1000_request_msix - Initialize MSI-X interrupts
1972 *
1973 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1974 * kernel.
1975 **/
1976static int e1000_request_msix(struct e1000_adapter *adapter)
1977{
1978 struct net_device *netdev = adapter->netdev;
1979 int err = 0, vector = 0;
1980
1981 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1982 snprintf(adapter->rx_ring->name,
1983 sizeof(adapter->rx_ring->name) - 1,
1984 "%s-rx-0", netdev->name);
4662e82b
BA		 1985 else
1986 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1987 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1988 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1989 netdev);
1990 if (err)
5015e53a 1991 return err;
c5083cf6
BA		 1992 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1993 E1000_EITR_82574(vector);
4662e82b
BA		 1994 adapter->rx_ring->itr_val = adapter->itr;
1995 vector++;
1996
1997 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1998 snprintf(adapter->tx_ring->name,
1999 sizeof(adapter->tx_ring->name) - 1,
2000 "%s-tx-0", netdev->name);
4662e82b
BA		 2001 else
2002 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2003 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2004 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2005 netdev);
2006 if (err)
5015e53a 2007 return err;
c5083cf6
BA		 2008 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2009 E1000_EITR_82574(vector);
4662e82b
BA		 2010 adapter->tx_ring->itr_val = adapter->itr;
2011 vector++;
2012
2013 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2014 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2015 if (err)
5015e53a 2016 return err;
4662e82b
BA		 2017
2018 e1000_configure_msix(adapter);
5015e53a 2019
4662e82b 2020 return 0;
4662e82b
BA		 2021}
2022
f8d59f78
BA		 2023/**
2024 * e1000_request_irq - initialize interrupts
2025 *
2026 * Attempts to configure interrupts using the best available
2027 * capabilities of the hardware and kernel.
2028 **/
bc7f75fa
AK		 2029static int e1000_request_irq(struct e1000_adapter *adapter)
2030{
2031 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2032 int err;
2033
4662e82b
BA		 2034 if (adapter->msix_entries) {
2035 err = e1000_request_msix(adapter);
2036 if (!err)
2037 return err;
2038 /* fall back to MSI */
2039 e1000e_reset_interrupt_capability(adapter);
2040 adapter->int_mode = E1000E_INT_MODE_MSI;
2041 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2042 }
4662e82b 2043 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2044 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2045 netdev->name, netdev);
2046 if (!err)
2047 return err;
bc7f75fa 2048
4662e82b
BA		 2049 /* fall back to legacy interrupt */
2050 e1000e_reset_interrupt_capability(adapter);
2051 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2052 }
2053
a0607fd3 2054 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2055 netdev->name, netdev);
2056 if (err)
2057 e_err("Unable to allocate interrupt, Error: %d\n", err);
2058
bc7f75fa
AK		 2059 return err;
2060}
2061
2062static void e1000_free_irq(struct e1000_adapter *adapter)
2063{
2064 struct net_device *netdev = adapter->netdev;
2065
4662e82b
BA		 2066 if (adapter->msix_entries) {
2067 int vector = 0;
2068
2069 free_irq(adapter->msix_entries[vector].vector, netdev);
2070 vector++;
2071
2072 free_irq(adapter->msix_entries[vector].vector, netdev);
2073 vector++;
2074
2075 /* Other Causes interrupt vector */
2076 free_irq(adapter->msix_entries[vector].vector, netdev);
2077 return;
bc7f75fa 2078 }
4662e82b
BA		 2079
2080 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2081}
2082
2083/**
2084 * e1000_irq_disable - Mask off interrupt generation on the NIC
2085 **/
2086static void e1000_irq_disable(struct e1000_adapter *adapter)
2087{
2088 struct e1000_hw *hw = &adapter->hw;
2089
bc7f75fa 2090 ew32(IMC, ~0);
4662e82b
BA		 2091 if (adapter->msix_entries)
2092 ew32(EIAC_82574, 0);
bc7f75fa 2093 e1e_flush();
8e86acd7
JK		 2094
2095 if (adapter->msix_entries) {
2096 int i;
2097 for (i = 0; i < adapter->num_vectors; i++)
2098 synchronize_irq(adapter->msix_entries[i].vector);
2099 } else {
2100 synchronize_irq(adapter->pdev->irq);
2101 }
bc7f75fa
AK		 2102}
2103
2104/**
2105 * e1000_irq_enable - Enable default interrupt generation settings
2106 **/
2107static void e1000_irq_enable(struct e1000_adapter *adapter)
2108{
2109 struct e1000_hw *hw = &adapter->hw;
2110
4662e82b
BA		 2111 if (adapter->msix_entries) {
2112 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2113 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2114 } else {
2115 ew32(IMS, IMS_ENABLE_MASK);
2116 }
74ef9c39 2117 e1e_flush();
bc7f75fa
AK		 2118}
2119
2120/**
31dbe5b4 2121 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2122 * @adapter: address of board private structure
2123 *
31dbe5b4 2124 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2125 * For ASF and Pass Through versions of f/w this means that
2126 * the driver is loaded. For AMT version (only with 82573)
2127 * of the f/w this means that the network i/f is open.
2128 **/
31dbe5b4 2129void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2130{
2131 struct e1000_hw *hw = &adapter->hw;
2132 u32 ctrl_ext;
2133 u32 swsm;
2134
2135 /* Let firmware know the driver has taken over */
2136 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2137 swsm = er32(SWSM);
2138 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2139 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2140 ctrl_ext = er32(CTRL_EXT);
ad68076e 2141 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2142 }
2143}
2144
2145/**
31dbe5b4 2146 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2147 * @adapter: address of board private structure
2148 *
31dbe5b4 2149 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2150 * For ASF and Pass Through versions of f/w this means that the
2151 * driver is no longer loaded. For AMT version (only with 82573) i
2152 * of the f/w this means that the network i/f is closed.
2153 *
2154 **/
31dbe5b4 2155void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2156{
2157 struct e1000_hw *hw = &adapter->hw;
2158 u32 ctrl_ext;
2159 u32 swsm;
2160
2161 /* Let firmware taken over control of h/w */
2162 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2163 swsm = er32(SWSM);
2164 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2165 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2166 ctrl_ext = er32(CTRL_EXT);
ad68076e 2167 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2168 }
2169}
2170
bc7f75fa
AK		 2171/**
2172 * @e1000_alloc_ring - allocate memory for a ring structure
2173 **/
2174static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2175 struct e1000_ring *ring)
2176{
2177 struct pci_dev *pdev = adapter->pdev;
2178
2179 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2180 GFP_KERNEL);
2181 if (!ring->desc)
2182 return -ENOMEM;
2183
2184 return 0;
2185}
2186
2187/**
2188 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2189 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2190 *
2191 * Return 0 on success, negative on failure
2192 **/
55aa6985 2193int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2194{
55aa6985 2195 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2196 int err = -ENOMEM, size;
2197
2198 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2199 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2200 if (!tx_ring->buffer_info)
2201 goto err;
bc7f75fa
AK		 2202
2203 /* round up to nearest 4K */
2204 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2205 tx_ring->size = ALIGN(tx_ring->size, 4096);
2206
2207 err = e1000_alloc_ring_dma(adapter, tx_ring);
2208 if (err)
2209 goto err;
2210
2211 tx_ring->next_to_use = 0;
2212 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2213
2214 return 0;
2215err:
2216 vfree(tx_ring->buffer_info);
44defeb3 2217 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2218 return err;
2219}
2220
2221/**
2222 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2223 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2224 *
2225 * Returns 0 on success, negative on failure
2226 **/
55aa6985 2227int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2228{
55aa6985 2229 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2230 struct e1000_buffer *buffer_info;
2231 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2232
2233 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2234 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2235 if (!rx_ring->buffer_info)
2236 goto err;
bc7f75fa 2237
47f44e40
AK		 2238 for (i = 0; i < rx_ring->count; i++) {
2239 buffer_info = &rx_ring->buffer_info[i];
2240 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2241 sizeof(struct e1000_ps_page),
2242 GFP_KERNEL);
2243 if (!buffer_info->ps_pages)
2244 goto err_pages;
2245 }
bc7f75fa
AK		 2246
2247 desc_len = sizeof(union e1000_rx_desc_packet_split);
2248
2249 /* Round up to nearest 4K */
2250 rx_ring->size = rx_ring->count * desc_len;
2251 rx_ring->size = ALIGN(rx_ring->size, 4096);
2252
2253 err = e1000_alloc_ring_dma(adapter, rx_ring);
2254 if (err)
47f44e40 2255 goto err_pages;
bc7f75fa
AK		 2256
2257 rx_ring->next_to_clean = 0;
2258 rx_ring->next_to_use = 0;
2259 rx_ring->rx_skb_top = NULL;
2260
2261 return 0;
47f44e40
AK		 2262
2263err_pages:
2264 for (i = 0; i < rx_ring->count; i++) {
2265 buffer_info = &rx_ring->buffer_info[i];
2266 kfree(buffer_info->ps_pages);
2267 }
bc7f75fa
AK		 2268err:
2269 vfree(rx_ring->buffer_info);
e9262447 2270 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2271 return err;
2272}
2273
2274/**
2275 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2276 * @tx_ring: Tx descriptor ring
bc7f75fa 2277 **/
55aa6985 2278static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2279{
55aa6985 2280 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2281 struct e1000_buffer *buffer_info;
2282 unsigned long size;
2283 unsigned int i;
2284
2285 for (i = 0; i < tx_ring->count; i++) {
2286 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2287 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2288 }
2289
3f0cfa3b 2290 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2291 size = sizeof(struct e1000_buffer) * tx_ring->count;
2292 memset(tx_ring->buffer_info, 0, size);
2293
2294 memset(tx_ring->desc, 0, tx_ring->size);
2295
2296 tx_ring->next_to_use = 0;
2297 tx_ring->next_to_clean = 0;
2298
c5083cf6 2299 writel(0, tx_ring->head);
bdc125f7
BA		 2300 if (tx_ring->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2301 e1000e_update_tdt_wa(tx_ring, 0);
2302 else
2303 writel(0, tx_ring->tail);
bc7f75fa
AK		 2304}
2305
2306/**
2307 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2308 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2309 *
2310 * Free all transmit software resources
2311 **/
55aa6985 2312void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2313{
55aa6985 2314 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2315 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2316
55aa6985 2317 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2318
2319 vfree(tx_ring->buffer_info);
2320 tx_ring->buffer_info = NULL;
2321
2322 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2323 tx_ring->dma);
2324 tx_ring->desc = NULL;
2325}
2326
2327/**
2328 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2329 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2330 *
2331 * Free all receive software resources
2332 **/
55aa6985 2333void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2334{
55aa6985 2335 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2336 struct pci_dev *pdev = adapter->pdev;
47f44e40 2337 int i;
bc7f75fa 2338
55aa6985 2339 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2340
b1cdfead 2341 for (i = 0; i < rx_ring->count; i++)
47f44e40 2342 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2343
bc7f75fa
AK		 2344 vfree(rx_ring->buffer_info);
2345 rx_ring->buffer_info = NULL;
2346
bc7f75fa
AK		 2347 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2348 rx_ring->dma);
2349 rx_ring->desc = NULL;
2350}
2351
2352/**
2353 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2354 * @adapter: pointer to adapter
2355 * @itr_setting: current adapter->itr
2356 * @packets: the number of packets during this measurement interval
2357 * @bytes: the number of bytes during this measurement interval
2358 *
bc7f75fa
AK		 2359 * Stores a new ITR value based on packets and byte
2360 * counts during the last interrupt. The advantage of per interrupt
2361 * computation is faster updates and more accurate ITR for the current
2362 * traffic pattern. Constants in this function were computed
2363 * based on theoretical maximum wire speed and thresholds were set based
2364 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2365 * while increasing bulk throughput. This functionality is controlled
2366 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2367 **/
2368static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2369 u16 itr_setting, int packets,
2370 int bytes)
2371{
2372 unsigned int retval = itr_setting;
2373
2374 if (packets == 0)
5015e53a 2375 return itr_setting;
bc7f75fa
AK		 2376
2377 switch (itr_setting) {
2378 case lowest_latency:
2379 /* handle TSO and jumbo frames */
2380 if (bytes/packets > 8000)
2381 retval = bulk_latency;
b1cdfead 2382 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2383 retval = low_latency;
bc7f75fa
AK		 2384 break;
2385 case low_latency: /* 50 usec aka 20000 ints/s */
2386 if (bytes > 10000) {
2387 /* this if handles the TSO accounting */
b1cdfead 2388 if (bytes/packets > 8000)
bc7f75fa 2389 retval = bulk_latency;
b1cdfead 2390 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2391 retval = bulk_latency;
b1cdfead 2392 else if ((packets > 35))
bc7f75fa 2393 retval = lowest_latency;
bc7f75fa
AK		 2394 } else if (bytes/packets > 2000) {
2395 retval = bulk_latency;
2396 } else if (packets <= 2 && bytes < 512) {
2397 retval = lowest_latency;
2398 }
2399 break;
2400 case bulk_latency: /* 250 usec aka 4000 ints/s */
2401 if (bytes > 25000) {
b1cdfead 2402 if (packets > 35)
bc7f75fa 2403 retval = low_latency;
bc7f75fa
AK		 2404 } else if (bytes < 6000) {
2405 retval = low_latency;
2406 }
2407 break;
2408 }
2409
bc7f75fa
AK		 2410 return retval;
2411}
2412
2413static void e1000_set_itr(struct e1000_adapter *adapter)
2414{
2415 struct e1000_hw *hw = &adapter->hw;
2416 u16 current_itr;
2417 u32 new_itr = adapter->itr;
2418
2419 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2420 if (adapter->link_speed != SPEED_1000) {
2421 current_itr = 0;
2422 new_itr = 4000;
2423 goto set_itr_now;
2424 }
2425
828bac87
BA		 2426 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2427 new_itr = 0;
2428 goto set_itr_now;
2429 }
2430
bc7f75fa
AK		 2431 adapter->tx_itr = e1000_update_itr(adapter,
2432 adapter->tx_itr,
2433 adapter->total_tx_packets,
2434 adapter->total_tx_bytes);
2435 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2436 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2437 adapter->tx_itr = low_latency;
2438
2439 adapter->rx_itr = e1000_update_itr(adapter,
2440 adapter->rx_itr,
2441 adapter->total_rx_packets,
2442 adapter->total_rx_bytes);
2443 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2444 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2445 adapter->rx_itr = low_latency;
2446
2447 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2448
2449 switch (current_itr) {
2450 /* counts and packets in update_itr are dependent on these numbers */
2451 case lowest_latency:
2452 new_itr = 70000;
2453 break;
2454 case low_latency:
2455 new_itr = 20000; /* aka hwitr = ~200 */
2456 break;
2457 case bulk_latency:
2458 new_itr = 4000;
2459 break;
2460 default:
2461 break;
2462 }
2463
2464set_itr_now:
2465 if (new_itr != adapter->itr) {
ad68076e
BA		 2466 /*
2467 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2468 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2469 * increasing
2470 */
bc7f75fa
AK		 2471 new_itr = new_itr > adapter->itr ?
2472 min(adapter->itr + (new_itr >> 2), new_itr) :
2473 new_itr;
2474 adapter->itr = new_itr;
4662e82b
BA		 2475 adapter->rx_ring->itr_val = new_itr;
2476 if (adapter->msix_entries)
2477 adapter->rx_ring->set_itr = 1;
2478 else
828bac87
BA		 2479 if (new_itr)
2480 ew32(ITR, 1000000000 / (new_itr * 256));
2481 else
2482 ew32(ITR, 0);
bc7f75fa
AK		 2483 }
2484}
2485
4662e82b
BA		 2486/**
2487 * e1000_alloc_queues - Allocate memory for all rings
2488 * @adapter: board private structure to initialize
2489 **/
2490static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2491{
55aa6985
BA		 2492 int size = sizeof(struct e1000_ring);
2493
2494 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2495 if (!adapter->tx_ring)
2496 goto err;
55aa6985
BA		 2497 adapter->tx_ring->count = adapter->tx_ring_count;
2498 adapter->tx_ring->adapter = adapter;
4662e82b 2499
55aa6985 2500 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2501 if (!adapter->rx_ring)
2502 goto err;
55aa6985
BA		 2503 adapter->rx_ring->count = adapter->rx_ring_count;
2504 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2505
2506 return 0;
2507err:
2508 e_err("Unable to allocate memory for queues\n");
2509 kfree(adapter->rx_ring);
2510 kfree(adapter->tx_ring);
2511 return -ENOMEM;
2512}
2513
bc7f75fa 2514/**
c58c8a78 2515 * e1000e_poll - NAPI Rx polling callback
ad68076e 2516 * @napi: struct associated with this polling callback
c58c8a78 2517 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2518 **/
c58c8a78 2519static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2520{
c58c8a78
BA		 2521 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2522 napi);
4662e82b 2523 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2524 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2525 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2526
4cf1653a 2527 adapter = netdev_priv(poll_dev);
bc7f75fa 2528
c58c8a78
BA		 2529 if (!adapter->msix_entries ||
2530 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2531 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2532
c58c8a78 2533 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2534
12d04a3c 2535 if (!tx_cleaned)
c58c8a78 2536 work_done = weight;
bc7f75fa 2537
c58c8a78
BA		 2538 /* If weight not fully consumed, exit the polling mode */
2539 if (work_done < weight) {
bc7f75fa
AK		 2540 if (adapter->itr_setting & 3)
2541 e1000_set_itr(adapter);
288379f0 2542 napi_complete(napi);
a3c69fef
JB		 2543 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2544 if (adapter->msix_entries)
2545 ew32(IMS, adapter->rx_ring->ims_val);
2546 else
2547 e1000_irq_enable(adapter);
2548 }
bc7f75fa
AK		 2549 }
2550
2551 return work_done;
2552}
2553
8e586137 2554static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2555{
2556 struct e1000_adapter *adapter = netdev_priv(netdev);
2557 struct e1000_hw *hw = &adapter->hw;
2558 u32 vfta, index;
2559
2560 /* don't update vlan cookie if already programmed */
2561 if ((adapter->hw.mng_cookie.status &
2562 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2563 (vid == adapter->mng_vlan_id))
8e586137 2564 return 0;
caaddaf8 2565
bc7f75fa 2566 /* add VID to filter table */
caaddaf8
BA		 2567 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2568 index = (vid >> 5) & 0x7F;
2569 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2570 vfta |= (1 << (vid & 0x1F));
2571 hw->mac.ops.write_vfta(hw, index, vfta);
2572 }
86d70e53
JK		 2573
2574 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2575
2576 return 0;
bc7f75fa
AK		 2577}
2578
8e586137 2579static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2580{
2581 struct e1000_adapter *adapter = netdev_priv(netdev);
2582 struct e1000_hw *hw = &adapter->hw;
2583 u32 vfta, index;
2584
bc7f75fa
AK		 2585 if ((adapter->hw.mng_cookie.status &
2586 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2587 (vid == adapter->mng_vlan_id)) {
2588 /* release control to f/w */
31dbe5b4 2589 e1000e_release_hw_control(adapter);
8e586137 2590 return 0;
bc7f75fa
AK		 2591 }
2592
2593 /* remove VID from filter table */
caaddaf8
BA		 2594 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2595 index = (vid >> 5) & 0x7F;
2596 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2597 vfta &= ~(1 << (vid & 0x1F));
2598 hw->mac.ops.write_vfta(hw, index, vfta);
2599 }
86d70e53
JK		 2600
2601 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2602
2603 return 0;
bc7f75fa
AK		 2604}
2605
86d70e53
JK		 2606/**
2607 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2608 * @adapter: board private structure to initialize
2609 **/
2610static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2611{
2612 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2613 struct e1000_hw *hw = &adapter->hw;
2614 u32 rctl;
bc7f75fa 2615
86d70e53
JK		 2616 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2617 /* disable VLAN receive filtering */
2618 rctl = er32(RCTL);
2619 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2620 ew32(RCTL, rctl);
2621
2622 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2623 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2624 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2625 }
bc7f75fa
AK		 2626 }
2627}
2628
86d70e53
JK		 2629/**
2630 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2631 * @adapter: board private structure to initialize
2632 **/
2633static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2634{
2635 struct e1000_hw *hw = &adapter->hw;
2636 u32 rctl;
2637
2638 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2639 /* enable VLAN receive filtering */
2640 rctl = er32(RCTL);
2641 rctl |= E1000_RCTL_VFE;
2642 rctl &= ~E1000_RCTL_CFIEN;
2643 ew32(RCTL, rctl);
2644 }
2645}
bc7f75fa 2646
86d70e53
JK		 2647/**
2648 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2649 * @adapter: board private structure to initialize
2650 **/
2651static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2652{
bc7f75fa 2653 struct e1000_hw *hw = &adapter->hw;
86d70e53 2654 u32 ctrl;
bc7f75fa 2655
86d70e53
JK		 2656 /* disable VLAN tag insert/strip */
2657 ctrl = er32(CTRL);
2658 ctrl &= ~E1000_CTRL_VME;
2659 ew32(CTRL, ctrl);
2660}
bc7f75fa 2661
86d70e53
JK		 2662/**
2663 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2664 * @adapter: board private structure to initialize
2665 **/
2666static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2667{
2668 struct e1000_hw *hw = &adapter->hw;
2669 u32 ctrl;
bc7f75fa 2670
86d70e53
JK		 2671 /* enable VLAN tag insert/strip */
2672 ctrl = er32(CTRL);
2673 ctrl |= E1000_CTRL_VME;
2674 ew32(CTRL, ctrl);
2675}
bc7f75fa 2676
86d70e53
JK		 2677static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2678{
2679 struct net_device *netdev = adapter->netdev;
2680 u16 vid = adapter->hw.mng_cookie.vlan_id;
2681 u16 old_vid = adapter->mng_vlan_id;
2682
2683 if (adapter->hw.mng_cookie.status &
2684 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2685 e1000_vlan_rx_add_vid(netdev, vid);
2686 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2687 }
2688
86d70e53
JK		 2689 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2690 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2691}
2692
2693static void e1000_restore_vlan(struct e1000_adapter *adapter)
2694{
2695 u16 vid;
2696
86d70e53 2697 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2698
86d70e53 2699 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2700 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2701}
2702
cd791618 2703static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2704{
2705 struct e1000_hw *hw = &adapter->hw;
cd791618 2706 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2707
2708 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2709 return;
2710
2711 manc = er32(MANC);
2712
ad68076e
BA		 2713 /*
2714 * enable receiving management packets to the host. this will probably
bc7f75fa 2715 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2716 * the packets will be handled on SMBUS
2717 */
bc7f75fa
AK		 2718 manc |= E1000_MANC_EN_MNG2HOST;
2719 manc2h = er32(MANC2H);
cd791618
BA		 2720
2721 switch (hw->mac.type) {
2722 default:
2723 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2724 break;
2725 case e1000_82574:
2726 case e1000_82583:
2727 /*
2728 * Check if IPMI pass-through decision filter already exists;
2729 * if so, enable it.
2730 */
2731 for (i = 0, j = 0; i < 8; i++) {
2732 mdef = er32(MDEF(i));
2733
2734 /* Ignore filters with anything other than IPMI ports */
3b21b508 2735 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2736 continue;
2737
2738 /* Enable this decision filter in MANC2H */
2739 if (mdef)
2740 manc2h |= (1 << i);
2741
2742 j |= mdef;
2743 }
2744
2745 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2746 break;
2747
2748 /* Create new decision filter in an empty filter */
2749 for (i = 0, j = 0; i < 8; i++)
2750 if (er32(MDEF(i)) == 0) {
2751 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2752 E1000_MDEF_PORT_664));
2753 manc2h |= (1 << 1);
2754 j++;
2755 break;
2756 }
2757
2758 if (!j)
2759 e_warn("Unable to create IPMI pass-through filter\n");
2760 break;
2761 }
2762
bc7f75fa
AK		 2763 ew32(MANC2H, manc2h);
2764 ew32(MANC, manc);
2765}
2766
2767/**
af667a29 2768 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2769 * @adapter: board private structure
2770 *
2771 * Configure the Tx unit of the MAC after a reset.
2772 **/
2773static void e1000_configure_tx(struct e1000_adapter *adapter)
2774{
2775 struct e1000_hw *hw = &adapter->hw;
2776 struct e1000_ring *tx_ring = adapter->tx_ring;
2777 u64 tdba;
c550b121 2778 u32 tdlen, tarc;
bc7f75fa
AK		 2779
2780 /* Setup the HW Tx Head and Tail descriptor pointers */
2781 tdba = tx_ring->dma;
2782 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2783 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2784 ew32(TDBAH(0), (tdba >> 32));
2785 ew32(TDLEN(0), tdlen);
2786 ew32(TDH(0), 0);
2787 ew32(TDT(0), 0);
2788 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2789 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2790
bc7f75fa
AK		 2791 /* Set the Tx Interrupt Delay register */
2792 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2793 /* Tx irq moderation */
bc7f75fa
AK		 2794 ew32(TADV, adapter->tx_abs_int_delay);
2795
3a3b7586
JB		 2796 if (adapter->flags2 & FLAG2_DMA_BURST) {
2797 u32 txdctl = er32(TXDCTL(0));
2798 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2799 E1000_TXDCTL_WTHRESH);
2800 /*
2801 * set up some performance related parameters to encourage the
2802 * hardware to use the bus more efficiently in bursts, depends
2803 * on the tx_int_delay to be enabled,
2804 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2805 * hthresh = 1 ==> prefetch when one or more available
2806 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2807 * BEWARE: this seems to work but should be considered first if
af667a29 2808 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2809 */
2810 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2811 ew32(TXDCTL(0), txdctl);
3a3b7586 2812 }
56032be7
BA		 2813 /* erratum work around: set txdctl the same for both queues */
2814 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2815
bc7f75fa 2816 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2817 tarc = er32(TARC(0));
ad68076e
BA		 2818 /*
2819 * set the speed mode bit, we'll clear it if we're not at
2820 * gigabit link later
2821 */
bc7f75fa
AK		 2822#define SPEED_MODE_BIT (1 << 21)
2823 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2824 ew32(TARC(0), tarc);
bc7f75fa
AK		 2825 }
2826
2827 /* errata: program both queues to unweighted RR */
2828 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2829 tarc = er32(TARC(0));
bc7f75fa 2830 tarc |= 1;
e9ec2c0f
JK		 2831 ew32(TARC(0), tarc);
2832 tarc = er32(TARC(1));
bc7f75fa 2833 tarc |= 1;
e9ec2c0f 2834 ew32(TARC(1), tarc);
bc7f75fa
AK		 2835 }
2836
bc7f75fa
AK		 2837 /* Setup Transmit Descriptor Settings for eop descriptor */
2838 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2839
2840 /* only set IDE if we are delaying interrupts using the timers */
2841 if (adapter->tx_int_delay)
2842 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2843
2844 /* enable Report Status bit */
2845 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2846
57cde763 2847 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2848}
2849
2850/**
2851 * e1000_setup_rctl - configure the receive control registers
2852 * @adapter: Board private structure
2853 **/
2854#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2855 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2856static void e1000_setup_rctl(struct e1000_adapter *adapter)
2857{
2858 struct e1000_hw *hw = &adapter->hw;
2859 u32 rctl, rfctl;
bc7f75fa
AK		 2860 u32 pages = 0;
2861
a1ce6473
BA		 2862 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2863 if (hw->mac.type == e1000_pch2lan) {
2864 s32 ret_val;
2865
2866 if (adapter->netdev->mtu > ETH_DATA_LEN)
2867 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2868 else
2869 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2870
2871 if (ret_val)
2872 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2873 }
2874
bc7f75fa
AK		 2875 /* Program MC offset vector base */
2876 rctl = er32(RCTL);
2877 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2878 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2879 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2880 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2881
2882 /* Do not Store bad packets */
2883 rctl &= ~E1000_RCTL_SBP;
2884
2885 /* Enable Long Packet receive */
2886 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2887 rctl &= ~E1000_RCTL_LPE;
2888 else
2889 rctl |= E1000_RCTL_LPE;
2890
eb7c3adb
JK		 2891 /* Some systems expect that the CRC is included in SMBUS traffic. The
2892 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2893 * host memory when this is enabled
2894 */
2895 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2896 rctl |= E1000_RCTL_SECRC;
5918bd88 2897
a4f58f54
BA		 2898 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2899 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2900 u16 phy_data;
2901
2902 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2903 phy_data &= 0xfff8;
2904 phy_data |= (1 << 2);
2905 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2906
2907 e1e_rphy(hw, 22, &phy_data);
2908 phy_data &= 0x0fff;
2909 phy_data |= (1 << 14);
2910 e1e_wphy(hw, 0x10, 0x2823);
2911 e1e_wphy(hw, 0x11, 0x0003);
2912 e1e_wphy(hw, 22, phy_data);
2913 }
2914
bc7f75fa
AK		 2915 /* Setup buffer sizes */
2916 rctl &= ~E1000_RCTL_SZ_4096;
2917 rctl |= E1000_RCTL_BSEX;
2918 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2919 case 2048:
2920 default:
2921 rctl |= E1000_RCTL_SZ_2048;
2922 rctl &= ~E1000_RCTL_BSEX;
2923 break;
2924 case 4096:
2925 rctl |= E1000_RCTL_SZ_4096;
2926 break;
2927 case 8192:
2928 rctl |= E1000_RCTL_SZ_8192;
2929 break;
2930 case 16384:
2931 rctl |= E1000_RCTL_SZ_16384;
2932 break;
2933 }
2934
5f450212
BA		 2935 /* Enable Extended Status in all Receive Descriptors */
2936 rfctl = er32(RFCTL);
2937 rfctl |= E1000_RFCTL_EXTEN;
2938
bc7f75fa
AK		 2939 /*
2940 * 82571 and greater support packet-split where the protocol
2941 * header is placed in skb->data and the packet data is
2942 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2943 * In the case of a non-split, skb->data is linearly filled,
2944 * followed by the page buffers. Therefore, skb->data is
2945 * sized to hold the largest protocol header.
2946 *
2947 * allocations using alloc_page take too long for regular MTU
2948 * so only enable packet split for jumbo frames
2949 *
2950 * Using pages when the page size is greater than 16k wastes
2951 * a lot of memory, since we allocate 3 pages at all times
2952 * per packet.
2953 */
bc7f75fa 2954 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2955 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2956 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2957 else
2958 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2959
2960 if (adapter->rx_ps_pages) {
90da0669
BA		 2961 u32 psrctl = 0;
2962
ad68076e
BA		 2963 /*
2964 * disable packet split support for IPv6 extension headers,
2965 * because some malformed IPv6 headers can hang the Rx
2966 */
bc7f75fa
AK		 2967 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2968 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2969
140a7480
AK		 2970 /* Enable Packet split descriptors */
2971 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2972
2973 psrctl |= adapter->rx_ps_bsize0 >>
2974 E1000_PSRCTL_BSIZE0_SHIFT;
2975
2976 switch (adapter->rx_ps_pages) {
2977 case 3:
2978 psrctl |= PAGE_SIZE <<
2979 E1000_PSRCTL_BSIZE3_SHIFT;
2980 case 2:
2981 psrctl |= PAGE_SIZE <<
2982 E1000_PSRCTL_BSIZE2_SHIFT;
2983 case 1:
2984 psrctl |= PAGE_SIZE >>
2985 E1000_PSRCTL_BSIZE1_SHIFT;
2986 break;
2987 }
2988
2989 ew32(PSRCTL, psrctl);
2990 }
2991
cf955e6c
BG		 2992 /* This is useful for sniffing bad packets. */
2993 if (adapter->netdev->features & NETIF_F_RXALL) {
2994 /* UPE and MPE will be handled by normal PROMISC logic
2995 * in e1000e_set_rx_mode */
2996 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2997 E1000_RCTL_BAM | /* RX All Bcast Pkts */
2998 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2999
3000 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3001 E1000_RCTL_DPF | /* Allow filtered pause */
3002 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3003 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3004 * and that breaks VLANs.
3005 */
3006 }
3007
5f450212 3008 ew32(RFCTL, rfctl);
bc7f75fa 3009 ew32(RCTL, rctl);
318a94d6
JK		 3010 /* just started the receive unit, no need to restart */
3011 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3012}
3013
3014/**
3015 * e1000_configure_rx - Configure Receive Unit after Reset
3016 * @adapter: board private structure
3017 *
3018 * Configure the Rx unit of the MAC after a reset.
3019 **/
3020static void e1000_configure_rx(struct e1000_adapter *adapter)
3021{
3022 struct e1000_hw *hw = &adapter->hw;
3023 struct e1000_ring *rx_ring = adapter->rx_ring;
3024 u64 rdba;
3025 u32 rdlen, rctl, rxcsum, ctrl_ext;
3026
3027 if (adapter->rx_ps_pages) {
3028 /* this is a 32 byte descriptor */
3029 rdlen = rx_ring->count *
af667a29 3030 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3031 adapter->clean_rx = e1000_clean_rx_irq_ps;
3032 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3033 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3034 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3035 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3036 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3037 } else {
5f450212 3038 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3039 adapter->clean_rx = e1000_clean_rx_irq;
3040 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3041 }
3042
3043 /* disable receives while setting up the descriptors */
3044 rctl = er32(RCTL);
7f99ae63
BA		 3045 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3046 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3047 e1e_flush();
1bba4386 3048 usleep_range(10000, 20000);
bc7f75fa 3049
3a3b7586
JB		 3050 if (adapter->flags2 & FLAG2_DMA_BURST) {
3051 /*
3052 * set the writeback threshold (only takes effect if the RDTR
3053 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3054 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3055 * granularity = 01
3056 * wthresh = 04,
3057 * hthresh = 04,
3058 * pthresh = 0x20
3059 */
3060 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3061 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3062
3063 /*
3064 * override the delay timers for enabling bursting, only if
3065 * the value was not set by the user via module options
3066 */
3067 if (adapter->rx_int_delay == DEFAULT_RDTR)
3068 adapter->rx_int_delay = BURST_RDTR;
3069 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3070 adapter->rx_abs_int_delay = BURST_RADV;
3071 }
3072
bc7f75fa
AK		 3073 /* set the Receive Delay Timer Register */
3074 ew32(RDTR, adapter->rx_int_delay);
3075
3076 /* irq moderation */
3077 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3078 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3079 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3080
3081 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3082 /* Auto-Mask interrupts upon ICR access */
3083 ctrl_ext |= E1000_CTRL_EXT_IAME;
3084 ew32(IAM, 0xffffffff);
3085 ew32(CTRL_EXT, ctrl_ext);
3086 e1e_flush();
3087
ad68076e
BA		 3088 /*
3089 * Setup the HW Rx Head and Tail Descriptor Pointers and
3090 * the Base and Length of the Rx Descriptor Ring
3091 */
bc7f75fa 3092 rdba = rx_ring->dma;
1e36052e
BA		 3093 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3094 ew32(RDBAH(0), (rdba >> 32));
3095 ew32(RDLEN(0), rdlen);
3096 ew32(RDH(0), 0);
3097 ew32(RDT(0), 0);
3098 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3099 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3100
3101 /* Enable Receive Checksum Offload for TCP and UDP */
3102 rxcsum = er32(RXCSUM);
dc221294 3103 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3104 rxcsum |= E1000_RXCSUM_TUOFL;
3105
ad68076e
BA		 3106 /*
3107 * IPv4 payload checksum for UDP fragments must be
3108 * used in conjunction with packet-split.
3109 */
bc7f75fa
AK		 3110 if (adapter->rx_ps_pages)
3111 rxcsum |= E1000_RXCSUM_IPPCSE;
3112 } else {
3113 rxcsum &= ~E1000_RXCSUM_TUOFL;
3114 /* no need to clear IPPCSE as it defaults to 0 */
3115 }
3116 ew32(RXCSUM, rxcsum);
3117
79d4e908
BA		 3118 if (adapter->hw.mac.type == e1000_pch2lan) {
3119 /*
3120 * With jumbo frames, excessive C-state transition
3121 * latencies result in dropped transactions.
3122 */
53ec5498
BA		 3123 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3124 u32 rxdctl = er32(RXDCTL(0));
3125 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3126 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3127 } else {
af667a29
BA		 3128 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3129 PM_QOS_DEFAULT_VALUE);
53ec5498 3130 }
97ac8cae 3131 }
bc7f75fa
AK		 3132
3133 /* Enable Receives */
3134 ew32(RCTL, rctl);
3135}
3136
3137/**
ef9b965a
JB		 3138 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3139 * @netdev: network interface device structure
bc7f75fa 3140 *
ef9b965a
JB		 3141 * Writes multicast address list to the MTA hash table.
3142 * Returns: -ENOMEM on failure
3143 * 0 on no addresses written
3144 * X on writing X addresses to MTA
3145 */
3146static int e1000e_write_mc_addr_list(struct net_device *netdev)
3147{
3148 struct e1000_adapter *adapter = netdev_priv(netdev);
3149 struct e1000_hw *hw = &adapter->hw;
3150 struct netdev_hw_addr *ha;
3151 u8 *mta_list;
3152 int i;
3153
3154 if (netdev_mc_empty(netdev)) {
3155 /* nothing to program, so clear mc list */
3156 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3157 return 0;
3158 }
3159
3160 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3161 if (!mta_list)
3162 return -ENOMEM;
3163
3164 /* update_mc_addr_list expects a packed array of only addresses. */
3165 i = 0;
3166 netdev_for_each_mc_addr(ha, netdev)
3167 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3168
3169 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3170 kfree(mta_list);
3171
3172 return netdev_mc_count(netdev);
3173}
3174
3175/**
3176 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3177 * @netdev: network interface device structure
bc7f75fa 3178 *
ef9b965a
JB		 3179 * Writes unicast address list to the RAR table.
3180 * Returns: -ENOMEM on failure/insufficient address space
3181 * 0 on no addresses written
3182 * X on writing X addresses to the RAR table
bc7f75fa 3183 **/
ef9b965a 3184static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3185{
ef9b965a
JB		 3186 struct e1000_adapter *adapter = netdev_priv(netdev);
3187 struct e1000_hw *hw = &adapter->hw;
3188 unsigned int rar_entries = hw->mac.rar_entry_count;
3189 int count = 0;
3190
3191 /* save a rar entry for our hardware address */
3192 rar_entries--;
3193
3194 /* save a rar entry for the LAA workaround */
3195 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3196 rar_entries--;
3197
3198 /* return ENOMEM indicating insufficient memory for addresses */
3199 if (netdev_uc_count(netdev) > rar_entries)
3200 return -ENOMEM;
3201
3202 if (!netdev_uc_empty(netdev) && rar_entries) {
3203 struct netdev_hw_addr *ha;
3204
3205 /*
3206 * write the addresses in reverse order to avoid write
3207 * combining
3208 */
3209 netdev_for_each_uc_addr(ha, netdev) {
3210 if (!rar_entries)
3211 break;
69e1e019 3212 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3213 count++;
3214 }
3215 }
3216
3217 /* zero out the remaining RAR entries not used above */
3218 for (; rar_entries > 0; rar_entries--) {
3219 ew32(RAH(rar_entries), 0);
3220 ew32(RAL(rar_entries), 0);
3221 }
3222 e1e_flush();
3223
3224 return count;
bc7f75fa
AK		 3225}
3226
3227/**
ef9b965a 3228 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3229 * @netdev: network interface device structure
3230 *
ef9b965a
JB		 3231 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3232 * address list or the network interface flags are updated. This routine is
3233 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3234 * promiscuous mode, and all-multi behavior.
3235 **/
ef9b965a 3236static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3237{
3238 struct e1000_adapter *adapter = netdev_priv(netdev);
3239 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3240 u32 rctl;
bc7f75fa
AK		 3241
3242 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3243 rctl = er32(RCTL);
3244
ef9b965a
JB		 3245 /* clear the affected bits */
3246 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3247
bc7f75fa
AK		 3248 if (netdev->flags & IFF_PROMISC) {
3249 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3250 /* Do not hardware filter VLANs in promisc mode */
3251 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3252 } else {
ef9b965a 3253 int count;
3d3a1676 3254
746b9f02
PM		 3255 if (netdev->flags & IFF_ALLMULTI) {
3256 rctl |= E1000_RCTL_MPE;
746b9f02 3257 } else {
ef9b965a
JB		 3258 /*
3259 * Write addresses to the MTA, if the attempt fails
3260 * then we should just turn on promiscuous mode so
3261 * that we can at least receive multicast traffic
3262 */
3263 count = e1000e_write_mc_addr_list(netdev);
3264 if (count < 0)
3265 rctl |= E1000_RCTL_MPE;
746b9f02 3266 }
86d70e53 3267 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3268 /*
ef9b965a
JB		 3269 * Write addresses to available RAR registers, if there is not
3270 * sufficient space to store all the addresses then enable
3271 * unicast promiscuous mode
bc7f75fa 3272 */
ef9b965a
JB		 3273 count = e1000e_write_uc_addr_list(netdev);
3274 if (count < 0)
3275 rctl |= E1000_RCTL_UPE;
bc7f75fa 3276 }
86d70e53 3277
ef9b965a
JB		 3278 ew32(RCTL, rctl);
3279
86d70e53
JK		 3280 if (netdev->features & NETIF_F_HW_VLAN_RX)
3281 e1000e_vlan_strip_enable(adapter);
3282 else
3283 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3284}
3285
70495a50
BA		 3286static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3287{
3288 struct e1000_hw *hw = &adapter->hw;
3289 u32 mrqc, rxcsum;
3290 int i;
3291 static const u32 rsskey[10] = {
3292 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3293 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3294 };
3295
3296 /* Fill out hash function seed */
3297 for (i = 0; i < 10; i++)
3298 ew32(RSSRK(i), rsskey[i]);
3299
3300 /* Direct all traffic to queue 0 */
3301 for (i = 0; i < 32; i++)
3302 ew32(RETA(i), 0);
3303
3304 /*
3305 * Disable raw packet checksumming so that RSS hash is placed in
3306 * descriptor on writeback.
3307 */
3308 rxcsum = er32(RXCSUM);
3309 rxcsum |= E1000_RXCSUM_PCSD;
3310
3311 ew32(RXCSUM, rxcsum);
3312
3313 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3314 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3315 E1000_MRQC_RSS_FIELD_IPV6 |
3316 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3317 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3318
3319 ew32(MRQC, mrqc);
3320}
3321
bc7f75fa 3322/**
ad68076e 3323 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3324 * @adapter: private board structure
3325 **/
3326static void e1000_configure(struct e1000_adapter *adapter)
3327{
55aa6985
BA		 3328 struct e1000_ring *rx_ring = adapter->rx_ring;
3329
ef9b965a 3330 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3331
3332 e1000_restore_vlan(adapter);
cd791618 3333 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3334
3335 e1000_configure_tx(adapter);
70495a50
BA		 3336
3337 if (adapter->netdev->features & NETIF_F_RXHASH)
3338 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3339 e1000_setup_rctl(adapter);
3340 e1000_configure_rx(adapter);
55aa6985 3341 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3342}
3343
3344/**
3345 * e1000e_power_up_phy - restore link in case the phy was powered down
3346 * @adapter: address of board private structure
3347 *
3348 * The phy may be powered down to save power and turn off link when the
3349 * driver is unloaded and wake on lan is not enabled (among others)
3350 * *** this routine MUST be followed by a call to e1000e_reset ***
3351 **/
3352void e1000e_power_up_phy(struct e1000_adapter *adapter)
3353{
17f208de
BA		 3354 if (adapter->hw.phy.ops.power_up)
3355 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3356
3357 adapter->hw.mac.ops.setup_link(&adapter->hw);
3358}
3359
3360/**
3361 * e1000_power_down_phy - Power down the PHY
3362 *
17f208de
BA		 3363 * Power down the PHY so no link is implied when interface is down.
3364 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3365 */
3366static void e1000_power_down_phy(struct e1000_adapter *adapter)
3367{
bc7f75fa 3368 /* WoL is enabled */
23b66e2b 3369 if (adapter->wol)
bc7f75fa
AK		 3370 return;
3371
17f208de
BA		 3372 if (adapter->hw.phy.ops.power_down)
3373 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3374}
3375
3376/**
3377 * e1000e_reset - bring the hardware into a known good state
3378 *
3379 * This function boots the hardware and enables some settings that
3380 * require a configuration cycle of the hardware - those cannot be
3381 * set/changed during runtime. After reset the device needs to be
ad68076e 3382 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3383 */
3384void e1000e_reset(struct e1000_adapter *adapter)
3385{
3386 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3387 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3388 struct e1000_hw *hw = &adapter->hw;
3389 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3390 u32 pba = adapter->pba;
bc7f75fa
AK		 3391 u16 hwm;
3392
ad68076e 3393 /* reset Packet Buffer Allocation to default */
318a94d6 3394 ew32(PBA, pba);
df762464 3395
318a94d6 3396 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3397 /*
3398 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3399 * large enough to accommodate two full transmit packets,
3400 * rounded up to the next 1KB and expressed in KB. Likewise,
3401 * the Rx FIFO should be large enough to accommodate at least
3402 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3403 * expressed in KB.
3404 */
df762464 3405 pba = er32(PBA);
bc7f75fa 3406 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3407 tx_space = pba >> 16;
bc7f75fa 3408 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3409 pba &= 0xffff;
ad68076e 3410 /*
af667a29 3411 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3412 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3413 */
3414 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3415 sizeof(struct e1000_tx_desc) -
3416 ETH_FCS_LEN) * 2;
3417 min_tx_space = ALIGN(min_tx_space, 1024);
3418 min_tx_space >>= 10;
3419 /* software strips receive CRC, so leave room for it */
318a94d6 3420 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3421 min_rx_space = ALIGN(min_rx_space, 1024);
3422 min_rx_space >>= 10;
3423
ad68076e
BA		 3424 /*
3425 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3426 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3427 * allocation, take space away from current Rx allocation
3428 */
df762464
AK		 3429 if ((tx_space < min_tx_space) &&
3430 ((min_tx_space - tx_space) < pba)) {
3431 pba -= min_tx_space - tx_space;
bc7f75fa 3432
ad68076e 3433 /*
af667a29 3434 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3435 * adjustment or use Early Receive if available
3436 */
79d4e908 3437 if (pba < min_rx_space)
df762464 3438 pba = min_rx_space;
bc7f75fa 3439 }
df762464
AK		 3440
3441 ew32(PBA, pba);
bc7f75fa
AK		 3442 }
3443
ad68076e
BA		 3444 /*
3445 * flow control settings
3446 *
38eb394e 3447 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3448 * (or the size used for early receive) above it in the Rx FIFO.
3449 * Set it to the lower of:
3450 * - 90% of the Rx FIFO size, and
38eb394e 3451 * - the full Rx FIFO size minus one full frame
ad68076e 3452 */
d3738bb8
BA		 3453 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3454 fc->pause_time = 0xFFFF;
3455 else
3456 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3457 fc->send_xon = true;
d3738bb8
BA		 3458 fc->current_mode = fc->requested_mode;
3459
3460 switch (hw->mac.type) {
79d4e908
BA		 3461 case e1000_ich9lan:
3462 case e1000_ich10lan:
3463 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3464 pba = 14;
3465 ew32(PBA, pba);
3466 fc->high_water = 0x2800;
3467 fc->low_water = fc->high_water - 8;
3468 break;
3469 }
3470 /* fall-through */
d3738bb8 3471 default:
79d4e908
BA		 3472 hwm = min(((pba << 10) * 9 / 10),
3473 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3474
3475 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3476 fc->low_water = fc->high_water - 8;
3477 break;
3478 case e1000_pchlan:
38eb394e
BA		 3479 /*
3480 * Workaround PCH LOM adapter hangs with certain network
3481 * loads. If hangs persist, try disabling Tx flow control.
3482 */
3483 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3484 fc->high_water = 0x3500;
3485 fc->low_water = 0x1500;
3486 } else {
3487 fc->high_water = 0x5000;
3488 fc->low_water = 0x3000;
3489 }
a305595b 3490 fc->refresh_time = 0x1000;
d3738bb8
BA		 3491 break;
3492 case e1000_pch2lan:
3493 fc->high_water = 0x05C20;
3494 fc->low_water = 0x05048;
3495 fc->pause_time = 0x0650;
3496 fc->refresh_time = 0x0400;
828bac87
BA		 3497 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3498 pba = 14;
3499 ew32(PBA, pba);
3500 }
d3738bb8 3501 break;
38eb394e 3502 }
bc7f75fa 3503
828bac87
BA		 3504 /*
3505 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3506 * fit in receive buffer.
828bac87
BA		 3507 */
3508 if (adapter->itr_setting & 0x3) {
79d4e908 3509 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3510 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3511 dev_info(&adapter->pdev->dev,
3512 "Interrupt Throttle Rate turned off\n");
3513 adapter->flags2 |= FLAG2_DISABLE_AIM;
3514 ew32(ITR, 0);
3515 }
3516 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3517 dev_info(&adapter->pdev->dev,
3518 "Interrupt Throttle Rate turned on\n");
3519 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3520 adapter->itr = 20000;
3521 ew32(ITR, 1000000000 / (adapter->itr * 256));
3522 }
3523 }
3524
bc7f75fa
AK		 3525 /* Allow time for pending master requests to run */
3526 mac->ops.reset_hw(hw);
97ac8cae
BA		 3527
3528 /*
3529 * For parts with AMT enabled, let the firmware know
3530 * that the network interface is in control
3531 */
c43bc57e 3532 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3533 e1000e_get_hw_control(adapter);
97ac8cae 3534
bc7f75fa
AK		 3535 ew32(WUC, 0);
3536
3537 if (mac->ops.init_hw(hw))
44defeb3 3538 e_err("Hardware Error\n");
bc7f75fa
AK		 3539
3540 e1000_update_mng_vlan(adapter);
3541
3542 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3543 ew32(VET, ETH_P_8021Q);
3544
3545 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3546
3547 if (!netif_running(adapter->netdev) &&
3548 !test_bit(__E1000_TESTING, &adapter->state)) {
3549 e1000_power_down_phy(adapter);
3550 return;
3551 }
3552
bc7f75fa
AK		 3553 e1000_get_phy_info(hw);
3554
918d7197
BA		 3555 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3556 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3557 u16 phy_data = 0;
ad68076e
BA		 3558 /*
3559 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3560 * the return value of this function because there is nothing
ad68076e
BA		 3561 * different we would do if it failed
3562 */
bc7f75fa
AK		 3563 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3564 phy_data &= ~IGP02E1000_PM_SPD;
3565 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3566 }
bc7f75fa
AK		 3567}
3568
3569int e1000e_up(struct e1000_adapter *adapter)
3570{
3571 struct e1000_hw *hw = &adapter->hw;
3572
3573 /* hardware has been reset, we need to reload some things */
3574 e1000_configure(adapter);
3575
3576 clear_bit(__E1000_DOWN, &adapter->state);
3577
4662e82b
BA		 3578 if (adapter->msix_entries)
3579 e1000_configure_msix(adapter);
bc7f75fa
AK		 3580 e1000_irq_enable(adapter);
3581
400484fa 3582 netif_start_queue(adapter->netdev);
4cb9be7a 3583
bc7f75fa 3584 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3585 if (adapter->msix_entries)
3586 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3587 else
3588 ew32(ICS, E1000_ICS_LSC);
3589
bc7f75fa
AK		 3590 return 0;
3591}
3592
713b3c9e
JB		 3593static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3594{
3595 struct e1000_hw *hw = &adapter->hw;
3596
3597 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3598 return;
3599
3600 /* flush pending descriptor writebacks to memory */
3601 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3602 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3603
3604 /* execute the writes immediately */
3605 e1e_flush();
bf03085f
MV		 3606
3607 /*
3608 * due to rare timing issues, write to TIDV/RDTR again to ensure the
3609 * write is successful
3610 */
3611 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3612 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3613
3614 /* execute the writes immediately */
3615 e1e_flush();
3616}
3617
67fd4fcb
JK		 3618static void e1000e_update_stats(struct e1000_adapter *adapter);
3619
bc7f75fa
AK		 3620void e1000e_down(struct e1000_adapter *adapter)
3621{
3622 struct net_device *netdev = adapter->netdev;
3623 struct e1000_hw *hw = &adapter->hw;
3624 u32 tctl, rctl;
3625
ad68076e
BA		 3626 /*
3627 * signal that we're down so the interrupt handler does not
3628 * reschedule our watchdog timer
3629 */
bc7f75fa
AK		 3630 set_bit(__E1000_DOWN, &adapter->state);
3631
3632 /* disable receives in the hardware */
3633 rctl = er32(RCTL);
7f99ae63
BA		 3634 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3635 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3636 /* flush and sleep below */
3637
4cb9be7a 3638 netif_stop_queue(netdev);
bc7f75fa
AK		 3639
3640 /* disable transmits in the hardware */
3641 tctl = er32(TCTL);
3642 tctl &= ~E1000_TCTL_EN;
3643 ew32(TCTL, tctl);
7f99ae63 3644
bc7f75fa
AK		 3645 /* flush both disables and wait for them to finish */
3646 e1e_flush();
1bba4386 3647 usleep_range(10000, 20000);
bc7f75fa 3648
bc7f75fa
AK		 3649 e1000_irq_disable(adapter);
3650
3651 del_timer_sync(&adapter->watchdog_timer);
3652 del_timer_sync(&adapter->phy_info_timer);
3653
bc7f75fa 3654 netif_carrier_off(netdev);
67fd4fcb
JK		 3655
3656 spin_lock(&adapter->stats64_lock);
3657 e1000e_update_stats(adapter);
3658 spin_unlock(&adapter->stats64_lock);
3659
400484fa 3660 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3661 e1000_clean_tx_ring(adapter->tx_ring);
3662 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3663
bc7f75fa
AK		 3664 adapter->link_speed = 0;
3665 adapter->link_duplex = 0;
3666
52cc3086
JK		 3667 if (!pci_channel_offline(adapter->pdev))
3668 e1000e_reset(adapter);
713b3c9e 3669
bc7f75fa
AK		 3670 /*
3671 * TODO: for power management, we could drop the link and
3672 * pci_disable_device here.
3673 */
3674}
3675
3676void e1000e_reinit_locked(struct e1000_adapter *adapter)
3677{
3678 might_sleep();
3679 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3680 usleep_range(1000, 2000);
bc7f75fa
AK		 3681 e1000e_down(adapter);
3682 e1000e_up(adapter);
3683 clear_bit(__E1000_RESETTING, &adapter->state);
3684}
3685
3686/**
3687 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3688 * @adapter: board private structure to initialize
3689 *
3690 * e1000_sw_init initializes the Adapter private data structure.
3691 * Fields are initialized based on PCI device information and
3692 * OS network device settings (MTU size).
3693 **/
3694static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3695{
bc7f75fa
AK		 3696 struct net_device *netdev = adapter->netdev;
3697
3698 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3699 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3700 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3701 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3702 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3703 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3704
67fd4fcb
JK		 3705 spin_lock_init(&adapter->stats64_lock);
3706
4662e82b 3707 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3708
4662e82b
BA		 3709 if (e1000_alloc_queues(adapter))
3710 return -ENOMEM;
bc7f75fa 3711
bc7f75fa 3712 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3713 e1000_irq_disable(adapter);
3714
bc7f75fa
AK		 3715 set_bit(__E1000_DOWN, &adapter->state);
3716 return 0;
bc7f75fa
AK		 3717}
3718
f8d59f78
BA		 3719/**
3720 * e1000_intr_msi_test - Interrupt Handler
3721 * @irq: interrupt number
3722 * @data: pointer to a network interface device structure
3723 **/
3724static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3725{
3726 struct net_device *netdev = data;
3727 struct e1000_adapter *adapter = netdev_priv(netdev);
3728 struct e1000_hw *hw = &adapter->hw;
3729 u32 icr = er32(ICR);
3730
3bb99fe2 3731 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3732 if (icr & E1000_ICR_RXSEQ) {
3733 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3734 wmb();
3735 }
3736
3737 return IRQ_HANDLED;
3738}
3739
3740/**
3741 * e1000_test_msi_interrupt - Returns 0 for successful test
3742 * @adapter: board private struct
3743 *
3744 * code flow taken from tg3.c
3745 **/
3746static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3747{
3748 struct net_device *netdev = adapter->netdev;
3749 struct e1000_hw *hw = &adapter->hw;
3750 int err;
3751
3752 /* poll_enable hasn't been called yet, so don't need disable */
3753 /* clear any pending events */
3754 er32(ICR);
3755
3756 /* free the real vector and request a test handler */
3757 e1000_free_irq(adapter);
4662e82b 3758 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3759
3760 /* Assume that the test fails, if it succeeds then the test
3761 * MSI irq handler will unset this flag */
3762 adapter->flags |= FLAG_MSI_TEST_FAILED;
3763
3764 err = pci_enable_msi(adapter->pdev);
3765 if (err)
3766 goto msi_test_failed;
3767
a0607fd3 3768 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3769 netdev->name, netdev);
3770 if (err) {
3771 pci_disable_msi(adapter->pdev);
3772 goto msi_test_failed;
3773 }
3774
3775 wmb();
3776
3777 e1000_irq_enable(adapter);
3778
3779 /* fire an unusual interrupt on the test handler */
3780 ew32(ICS, E1000_ICS_RXSEQ);
3781 e1e_flush();
3782 msleep(50);
3783
3784 e1000_irq_disable(adapter);
3785
3786 rmb();
3787
3788 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3789 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3790 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3791 } else {
068e8a30 3792 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3793 }
f8d59f78
BA		 3794
3795 free_irq(adapter->pdev->irq, netdev);
3796 pci_disable_msi(adapter->pdev);
3797
f8d59f78 3798msi_test_failed:
4662e82b 3799 e1000e_set_interrupt_capability(adapter);
068e8a30 3800 return e1000_request_irq(adapter);
f8d59f78
BA		 3801}
3802
3803/**
3804 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3805 * @adapter: board private struct
3806 *
3807 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3808 **/
3809static int e1000_test_msi(struct e1000_adapter *adapter)
3810{
3811 int err;
3812 u16 pci_cmd;
3813
3814 if (!(adapter->flags & FLAG_MSI_ENABLED))
3815 return 0;
3816
3817 /* disable SERR in case the MSI write causes a master abort */
3818 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3819 if (pci_cmd & PCI_COMMAND_SERR)
3820 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3821 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3822
3823 err = e1000_test_msi_interrupt(adapter);
3824
36f2407f
DN		 3825 /* re-enable SERR */
3826 if (pci_cmd & PCI_COMMAND_SERR) {
3827 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3828 pci_cmd |= PCI_COMMAND_SERR;
3829 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3830 }
f8d59f78 3831
f8d59f78
BA		 3832 return err;
3833}
3834
bc7f75fa
AK		 3835/**
3836 * e1000_open - Called when a network interface is made active
3837 * @netdev: network interface device structure
3838 *
3839 * Returns 0 on success, negative value on failure
3840 *
3841 * The open entry point is called when a network interface is made
3842 * active by the system (IFF_UP). At this point all resources needed
3843 * for transmit and receive operations are allocated, the interrupt
3844 * handler is registered with the OS, the watchdog timer is started,
3845 * and the stack is notified that the interface is ready.
3846 **/
3847static int e1000_open(struct net_device *netdev)
3848{
3849 struct e1000_adapter *adapter = netdev_priv(netdev);
3850 struct e1000_hw *hw = &adapter->hw;
23606cf5 3851 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3852 int err;
3853
3854 /* disallow open during test */
3855 if (test_bit(__E1000_TESTING, &adapter->state))
3856 return -EBUSY;
3857
23606cf5
RW		 3858 pm_runtime_get_sync(&pdev->dev);
3859
9c563d20
JB		 3860 netif_carrier_off(netdev);
3861
bc7f75fa 3862 /* allocate transmit descriptors */
55aa6985 3863 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3864 if (err)
3865 goto err_setup_tx;
3866
3867 /* allocate receive descriptors */
55aa6985 3868 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3869 if (err)
3870 goto err_setup_rx;
3871
11b08be8
BA		 3872 /*
3873 * If AMT is enabled, let the firmware know that the network
3874 * interface is now open and reset the part to a known state.
3875 */
3876 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3877 e1000e_get_hw_control(adapter);
11b08be8
BA		 3878 e1000e_reset(adapter);
3879 }
3880
bc7f75fa
AK		 3881 e1000e_power_up_phy(adapter);
3882
3883 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3884 if ((adapter->hw.mng_cookie.status &
3885 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3886 e1000_update_mng_vlan(adapter);
3887
79d4e908
BA		 3888 /* DMA latency requirement to workaround jumbo issue */
3889 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3890 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3891 PM_QOS_CPU_DMA_LATENCY,
3892 PM_QOS_DEFAULT_VALUE);
c128ec29 3893
ad68076e
BA		 3894 /*
3895 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3896 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3897 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3898 * clean_rx handler before we do so.
3899 */
bc7f75fa
AK		 3900 e1000_configure(adapter);
3901
3902 err = e1000_request_irq(adapter);
3903 if (err)
3904 goto err_req_irq;
3905
f8d59f78
BA		 3906 /*
3907 * Work around PCIe errata with MSI interrupts causing some chipsets to
3908 * ignore e1000e MSI messages, which means we need to test our MSI
3909 * interrupt now
3910 */
4662e82b 3911 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3912 err = e1000_test_msi(adapter);
3913 if (err) {
3914 e_err("Interrupt allocation failed\n");
3915 goto err_req_irq;
3916 }
3917 }
3918
bc7f75fa
AK		 3919 /* From here on the code is the same as e1000e_up() */
3920 clear_bit(__E1000_DOWN, &adapter->state);
3921
3922 napi_enable(&adapter->napi);
3923
3924 e1000_irq_enable(adapter);
3925
09357b00 3926 adapter->tx_hang_recheck = false;
4cb9be7a 3927 netif_start_queue(netdev);
d55b53ff 3928
23606cf5
RW		 3929 adapter->idle_check = true;
3930 pm_runtime_put(&pdev->dev);
3931
bc7f75fa 3932 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3933 if (adapter->msix_entries)
3934 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3935 else
3936 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3937
3938 return 0;
3939
3940err_req_irq:
31dbe5b4 3941 e1000e_release_hw_control(adapter);
bc7f75fa 3942 e1000_power_down_phy(adapter);
55aa6985 3943 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3944err_setup_rx:
55aa6985 3945 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3946err_setup_tx:
3947 e1000e_reset(adapter);
23606cf5 3948 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3949
3950 return err;
3951}
3952
3953/**
3954 * e1000_close - Disables a network interface
3955 * @netdev: network interface device structure
3956 *
3957 * Returns 0, this is not allowed to fail
3958 *
3959 * The close entry point is called when an interface is de-activated
3960 * by the OS. The hardware is still under the drivers control, but
3961 * needs to be disabled. A global MAC reset is issued to stop the
3962 * hardware, and all transmit and receive resources are freed.
3963 **/
3964static int e1000_close(struct net_device *netdev)
3965{
3966 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3967 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 3968 int count = E1000_CHECK_RESET_COUNT;
3969
3970 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
3971 usleep_range(10000, 20000);
bc7f75fa
AK		 3972
3973 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3974
3975 pm_runtime_get_sync(&pdev->dev);
3976
5f4a780d
BA		 3977 napi_disable(&adapter->napi);
3978
23606cf5
RW		 3979 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3980 e1000e_down(adapter);
3981 e1000_free_irq(adapter);
3982 }
bc7f75fa 3983 e1000_power_down_phy(adapter);
bc7f75fa 3984
55aa6985
BA		 3985 e1000e_free_tx_resources(adapter->tx_ring);
3986 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3987
ad68076e
BA		 3988 /*
3989 * kill manageability vlan ID if supported, but not if a vlan with
3990 * the same ID is registered on the host OS (let 8021q kill it)
3991 */
86d70e53
JK		 3992 if (adapter->hw.mng_cookie.status &
3993 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3994 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3995
ad68076e
BA		 3996 /*
3997 * If AMT is enabled, let the firmware know that the network
3998 * interface is now closed
3999 */
31dbe5b4
BA		 4000 if ((adapter->flags & FLAG_HAS_AMT) &&
4001 !test_bit(__E1000_TESTING, &adapter->state))
4002 e1000e_release_hw_control(adapter);
bc7f75fa 4003
79d4e908 4004 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4005 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4006
23606cf5
RW		 4007 pm_runtime_put_sync(&pdev->dev);
4008
bc7f75fa
AK		 4009 return 0;
4010}
4011/**
4012 * e1000_set_mac - Change the Ethernet Address of the NIC
4013 * @netdev: network interface device structure
4014 * @p: pointer to an address structure
4015 *
4016 * Returns 0 on success, negative on failure
4017 **/
4018static int e1000_set_mac(struct net_device *netdev, void *p)
4019{
4020 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4021 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4022 struct sockaddr *addr = p;
4023
4024 if (!is_valid_ether_addr(addr->sa_data))
4025 return -EADDRNOTAVAIL;
4026
4027 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4028 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4029
69e1e019 4030 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4031
4032 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4033 /* activate the work around */
4034 e1000e_set_laa_state_82571(&adapter->hw, 1);
4035
ad68076e
BA		 4036 /*
4037 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4038 * between the time RAR[0] gets clobbered and the time it
4039 * gets fixed (in e1000_watchdog), the actual LAA is in one
4040 * of the RARs and no incoming packets directed to this port
4041 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4042 * RAR[14]
4043 */
69e1e019
BA		 4044 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4045 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4046 }
4047
4048 return 0;
4049}
4050
a8f88ff5
JB		 4051/**
4052 * e1000e_update_phy_task - work thread to update phy
4053 * @work: pointer to our work struct
4054 *
4055 * this worker thread exists because we must acquire a
4056 * semaphore to read the phy, which we could msleep while
4057 * waiting for it, and we can't msleep in a timer.
4058 **/
4059static void e1000e_update_phy_task(struct work_struct *work)
4060{
4061 struct e1000_adapter *adapter = container_of(work,
4062 struct e1000_adapter, update_phy_task);
615b32af
JB		 4063
4064 if (test_bit(__E1000_DOWN, &adapter->state))
4065 return;
4066
a8f88ff5
JB		 4067 e1000_get_phy_info(&adapter->hw);
4068}
4069
ad68076e
BA		 4070/*
4071 * Need to wait a few seconds after link up to get diagnostic information from
4072 * the phy
4073 */
bc7f75fa
AK		 4074static void e1000_update_phy_info(unsigned long data)
4075{
4076 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4077
4078 if (test_bit(__E1000_DOWN, &adapter->state))
4079 return;
4080
a8f88ff5 4081 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4082}
4083
8c7bbb92
BA		 4084/**
4085 * e1000e_update_phy_stats - Update the PHY statistics counters
4086 * @adapter: board private structure
2b6b168d
BA		 4087 *
4088 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4089 **/
4090static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4091{
4092 struct e1000_hw *hw = &adapter->hw;
4093 s32 ret_val;
4094 u16 phy_data;
4095
4096 ret_val = hw->phy.ops.acquire(hw);
4097 if (ret_val)
4098 return;
4099
8c7bbb92
BA		 4100 /*
4101 * A page set is expensive so check if already on desired page.
4102 * If not, set to the page with the PHY status registers.
4103 */
2b6b168d 4104 hw->phy.addr = 1;
8c7bbb92
BA		 4105 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4106 &phy_data);
4107 if (ret_val)
4108 goto release;
2b6b168d
BA		 4109 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4110 ret_val = hw->phy.ops.set_page(hw,
4111 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4112 if (ret_val)
4113 goto release;
4114 }
4115
8c7bbb92 4116 /* Single Collision Count */
2b6b168d
BA		 4117 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4118 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4119 if (!ret_val)
4120 adapter->stats.scc += phy_data;
4121
4122 /* Excessive Collision Count */
2b6b168d
BA		 4123 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4124 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4125 if (!ret_val)
4126 adapter->stats.ecol += phy_data;
4127
4128 /* Multiple Collision Count */
2b6b168d
BA		 4129 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4130 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4131 if (!ret_val)
4132 adapter->stats.mcc += phy_data;
4133
4134 /* Late Collision Count */
2b6b168d
BA		 4135 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4136 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4137 if (!ret_val)
4138 adapter->stats.latecol += phy_data;
4139
4140 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4141 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4142 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4143 if (!ret_val)
4144 hw->mac.collision_delta = phy_data;
4145
4146 /* Defer Count */
2b6b168d
BA		 4147 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4148 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4149 if (!ret_val)
4150 adapter->stats.dc += phy_data;
4151
4152 /* Transmit with no CRS */
2b6b168d
BA		 4153 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4154 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4155 if (!ret_val)
4156 adapter->stats.tncrs += phy_data;
4157
4158release:
4159 hw->phy.ops.release(hw);
4160}
4161
bc7f75fa
AK		 4162/**
4163 * e1000e_update_stats - Update the board statistics counters
4164 * @adapter: board private structure
4165 **/
67fd4fcb 4166static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4167{
7274c20f 4168 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4169 struct e1000_hw *hw = &adapter->hw;
4170 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4171
4172 /*
4173 * Prevent stats update while adapter is being reset, or if the pci
4174 * connection is down.
4175 */
4176 if (adapter->link_speed == 0)
4177 return;
4178 if (pci_channel_offline(pdev))
4179 return;
4180
bc7f75fa
AK		 4181 adapter->stats.crcerrs += er32(CRCERRS);
4182 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4183 adapter->stats.gorc += er32(GORCL);
4184 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4185 adapter->stats.bprc += er32(BPRC);
4186 adapter->stats.mprc += er32(MPRC);
4187 adapter->stats.roc += er32(ROC);
4188
bc7f75fa 4189 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4190
4191 /* Half-duplex statistics */
4192 if (adapter->link_duplex == HALF_DUPLEX) {
4193 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4194 e1000e_update_phy_stats(adapter);
4195 } else {
4196 adapter->stats.scc += er32(SCC);
4197 adapter->stats.ecol += er32(ECOL);
4198 adapter->stats.mcc += er32(MCC);
4199 adapter->stats.latecol += er32(LATECOL);
4200 adapter->stats.dc += er32(DC);
4201
4202 hw->mac.collision_delta = er32(COLC);
4203
4204 if ((hw->mac.type != e1000_82574) &&
4205 (hw->mac.type != e1000_82583))
4206 adapter->stats.tncrs += er32(TNCRS);
4207 }
4208 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4209 }
8c7bbb92 4210
bc7f75fa
AK		 4211 adapter->stats.xonrxc += er32(XONRXC);
4212 adapter->stats.xontxc += er32(XONTXC);
4213 adapter->stats.xoffrxc += er32(XOFFRXC);
4214 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4215 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4216 adapter->stats.gotc += er32(GOTCL);
4217 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4218 adapter->stats.rnbc += er32(RNBC);
4219 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4220
4221 adapter->stats.mptc += er32(MPTC);
4222 adapter->stats.bptc += er32(BPTC);
4223
4224 /* used for adaptive IFS */
4225
4226 hw->mac.tx_packet_delta = er32(TPT);
4227 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4228
4229 adapter->stats.algnerrc += er32(ALGNERRC);
4230 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4231 adapter->stats.cexterr += er32(CEXTERR);
4232 adapter->stats.tsctc += er32(TSCTC);
4233 adapter->stats.tsctfc += er32(TSCTFC);
4234
bc7f75fa 4235 /* Fill out the OS statistics structure */
7274c20f
AK		 4236 netdev->stats.multicast = adapter->stats.mprc;
4237 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4238
4239 /* Rx Errors */
4240
ad68076e
BA		 4241 /*
4242 * RLEC on some newer hardware can be incorrect so build
4243 * our own version based on RUC and ROC
4244 */
7274c20f 4245 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4246 adapter->stats.crcerrs + adapter->stats.algnerrc +
4247 adapter->stats.ruc + adapter->stats.roc +
4248 adapter->stats.cexterr;
7274c20f 4249 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4250 adapter->stats.roc;
7274c20f
AK		 4251 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4252 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4253 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4254
4255 /* Tx Errors */
7274c20f 4256 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4257 adapter->stats.latecol;
7274c20f
AK		 4258 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4259 netdev->stats.tx_window_errors = adapter->stats.latecol;
4260 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4261
4262 /* Tx Dropped needs to be maintained elsewhere */
4263
bc7f75fa
AK		 4264 /* Management Stats */
4265 adapter->stats.mgptc += er32(MGTPTC);
4266 adapter->stats.mgprc += er32(MGTPRC);
4267 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4268}
4269
7c25769f
BA		 4270/**
4271 * e1000_phy_read_status - Update the PHY register status snapshot
4272 * @adapter: board private structure
4273 **/
4274static void e1000_phy_read_status(struct e1000_adapter *adapter)
4275{
4276 struct e1000_hw *hw = &adapter->hw;
4277 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4278
4279 if ((er32(STATUS) & E1000_STATUS_LU) &&
4280 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4281 int ret_val;
4282
7c25769f
BA		 4283 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4284 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4285 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4286 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4287 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4288 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4289 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4290 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4291 if (ret_val)
44defeb3 4292 e_warn("Error reading PHY register\n");
7c25769f
BA		 4293 } else {
4294 /*
4295 * Do not read PHY registers if link is not up
4296 * Set values to typical power-on defaults
4297 */
4298 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4299 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4300 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4301 BMSR_ERCAP);
4302 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4303 ADVERTISE_ALL | ADVERTISE_CSMA);
4304 phy->lpa = 0;
4305 phy->expansion = EXPANSION_ENABLENPAGE;
4306 phy->ctrl1000 = ADVERTISE_1000FULL;
4307 phy->stat1000 = 0;
4308 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4309 }
7c25769f
BA		 4310}
4311
bc7f75fa
AK		 4312static void e1000_print_link_info(struct e1000_adapter *adapter)
4313{
bc7f75fa
AK		 4314 struct e1000_hw *hw = &adapter->hw;
4315 u32 ctrl = er32(CTRL);
4316
8f12fe86 4317 /* Link status message must follow this format for user tools */
ef456f85
JK		 4318 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4319 adapter->netdev->name,
4320 adapter->link_speed,
4321 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4322 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4323 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4324 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4325}
4326
0c6bdb30 4327static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4328{
4329 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4330 bool link_active = false;
318a94d6
JK		 4331 s32 ret_val = 0;
4332
4333 /*
4334 * get_link_status is set on LSC (link status) interrupt or
4335 * Rx sequence error interrupt. get_link_status will stay
4336 * false until the check_for_link establishes link
4337 * for copper adapters ONLY
4338 */
4339 switch (hw->phy.media_type) {
4340 case e1000_media_type_copper:
4341 if (hw->mac.get_link_status) {
4342 ret_val = hw->mac.ops.check_for_link(hw);
4343 link_active = !hw->mac.get_link_status;
4344 } else {
3db1cd5c 4345 link_active = true;
318a94d6
JK		 4346 }
4347 break;
4348 case e1000_media_type_fiber:
4349 ret_val = hw->mac.ops.check_for_link(hw);
4350 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4351 break;
4352 case e1000_media_type_internal_serdes:
4353 ret_val = hw->mac.ops.check_for_link(hw);
4354 link_active = adapter->hw.mac.serdes_has_link;
4355 break;
4356 default:
4357 case e1000_media_type_unknown:
4358 break;
4359 }
4360
4361 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4362 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4363 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4364 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4365 }
4366
4367 return link_active;
4368}
4369
4370static void e1000e_enable_receives(struct e1000_adapter *adapter)
4371{
4372 /* make sure the receive unit is started */
4373 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4374 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4375 struct e1000_hw *hw = &adapter->hw;
4376 u32 rctl = er32(RCTL);
4377 ew32(RCTL, rctl | E1000_RCTL_EN);
4378 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4379 }
4380}
4381
ff10e13c
CW		 4382static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4383{
4384 struct e1000_hw *hw = &adapter->hw;
4385
4386 /*
4387 * With 82574 controllers, PHY needs to be checked periodically
4388 * for hung state and reset, if two calls return true
4389 */
4390 if (e1000_check_phy_82574(hw))
4391 adapter->phy_hang_count++;
4392 else
4393 adapter->phy_hang_count = 0;
4394
4395 if (adapter->phy_hang_count > 1) {
4396 adapter->phy_hang_count = 0;
4397 schedule_work(&adapter->reset_task);
4398 }
4399}
4400
bc7f75fa
AK		 4401/**
4402 * e1000_watchdog - Timer Call-back
4403 * @data: pointer to adapter cast into an unsigned long
4404 **/
4405static void e1000_watchdog(unsigned long data)
4406{
4407 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4408
4409 /* Do the rest outside of interrupt context */
4410 schedule_work(&adapter->watchdog_task);
4411
4412 /* TODO: make this use queue_delayed_work() */
4413}
4414
4415static void e1000_watchdog_task(struct work_struct *work)
4416{
4417 struct e1000_adapter *adapter = container_of(work,
4418 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4419 struct net_device *netdev = adapter->netdev;
4420 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4421 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4422 struct e1000_ring *tx_ring = adapter->tx_ring;
4423 struct e1000_hw *hw = &adapter->hw;
4424 u32 link, tctl;
bc7f75fa 4425
615b32af
JB		 4426 if (test_bit(__E1000_DOWN, &adapter->state))
4427 return;
4428
b405e8df 4429 link = e1000e_has_link(adapter);
318a94d6 4430 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4431 /* Cancel scheduled suspend requests. */
4432 pm_runtime_resume(netdev->dev.parent);
4433
318a94d6 4434 e1000e_enable_receives(adapter);
bc7f75fa 4435 goto link_up;
bc7f75fa
AK		 4436 }
4437
4438 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4439 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4440 e1000_update_mng_vlan(adapter);
4441
bc7f75fa
AK		 4442 if (link) {
4443 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4444 bool txb2b = true;
23606cf5
RW		 4445
4446 /* Cancel scheduled suspend requests. */
4447 pm_runtime_resume(netdev->dev.parent);
4448
318a94d6 4449 /* update snapshot of PHY registers on LSC */
7c25769f 4450 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4451 mac->ops.get_link_up_info(&adapter->hw,
4452 &adapter->link_speed,
4453 &adapter->link_duplex);
4454 e1000_print_link_info(adapter);
f4187b56
BA		 4455 /*
4456 * On supported PHYs, check for duplex mismatch only
4457 * if link has autonegotiated at 10/100 half
4458 */
4459 if ((hw->phy.type == e1000_phy_igp_3 ||
4460 hw->phy.type == e1000_phy_bm) &&
4461 (hw->mac.autoneg == true) &&
4462 (adapter->link_speed == SPEED_10 ||
4463 adapter->link_speed == SPEED_100) &&
4464 (adapter->link_duplex == HALF_DUPLEX)) {
4465 u16 autoneg_exp;
4466
4467 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4468
4469 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4470 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4471 }
4472
f49c57e1 4473 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4474 adapter->tx_timeout_factor = 1;
4475 switch (adapter->link_speed) {
4476 case SPEED_10:
3db1cd5c 4477 txb2b = false;
10f1b492 4478 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4479 break;
4480 case SPEED_100:
3db1cd5c 4481 txb2b = false;
4c86e0b9 4482 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4483 break;
4484 }
4485
ad68076e
BA		 4486 /*
4487 * workaround: re-program speed mode bit after
4488 * link-up event
4489 */
bc7f75fa
AK		 4490 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4491 !txb2b) {
4492 u32 tarc0;
e9ec2c0f 4493 tarc0 = er32(TARC(0));
bc7f75fa 4494 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4495 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4496 }
4497
ad68076e
BA		 4498 /*
4499 * disable TSO for pcie and 10/100 speeds, to avoid
4500 * some hardware issues
4501 */
bc7f75fa
AK		 4502 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4503 switch (adapter->link_speed) {
4504 case SPEED_10:
4505 case SPEED_100:
44defeb3 4506 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4507 netdev->features &= ~NETIF_F_TSO;
4508 netdev->features &= ~NETIF_F_TSO6;
4509 break;
4510 case SPEED_1000:
4511 netdev->features |= NETIF_F_TSO;
4512 netdev->features |= NETIF_F_TSO6;
4513 break;
4514 default:
4515 /* oops */
4516 break;
4517 }
4518 }
4519
ad68076e
BA		 4520 /*
4521 * enable transmits in the hardware, need to do this
4522 * after setting TARC(0)
4523 */
bc7f75fa
AK		 4524 tctl = er32(TCTL);
4525 tctl |= E1000_TCTL_EN;
4526 ew32(TCTL, tctl);
4527
75eb0fad
BA		 4528 /*
4529 * Perform any post-link-up configuration before
4530 * reporting link up.
4531 */
4532 if (phy->ops.cfg_on_link_up)
4533 phy->ops.cfg_on_link_up(hw);
4534
bc7f75fa 4535 netif_carrier_on(netdev);
bc7f75fa
AK		 4536
4537 if (!test_bit(__E1000_DOWN, &adapter->state))
4538 mod_timer(&adapter->phy_info_timer,
4539 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4540 }
4541 } else {
4542 if (netif_carrier_ok(netdev)) {
4543 adapter->link_speed = 0;
4544 adapter->link_duplex = 0;
8f12fe86
BA		 4545 /* Link status message must follow this format */
4546 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4547 adapter->netdev->name);
bc7f75fa 4548 netif_carrier_off(netdev);
bc7f75fa
AK		 4549 if (!test_bit(__E1000_DOWN, &adapter->state))
4550 mod_timer(&adapter->phy_info_timer,
4551 round_jiffies(jiffies + 2 * HZ));
4552
4553 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4554 schedule_work(&adapter->reset_task);
23606cf5
RW		 4555 else
4556 pm_schedule_suspend(netdev->dev.parent,
4557 LINK_TIMEOUT);
bc7f75fa
AK		 4558 }
4559 }
4560
4561link_up:
67fd4fcb 4562 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4563 e1000e_update_stats(adapter);
4564
4565 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4566 adapter->tpt_old = adapter->stats.tpt;
4567 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4568 adapter->colc_old = adapter->stats.colc;
4569
7c25769f
BA		 4570 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4571 adapter->gorc_old = adapter->stats.gorc;
4572 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4573 adapter->gotc_old = adapter->stats.gotc;
2084b114 4574 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4575
4576 e1000e_update_adaptive(&adapter->hw);
4577
90da0669
BA		 4578 if (!netif_carrier_ok(netdev) &&
4579 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4580 /*
4581 * We've lost link, so the controller stops DMA,
4582 * but we've got queued Tx work that's never going
4583 * to get done, so reset controller to flush Tx.
4584 * (Do the reset outside of interrupt context).
4585 */
90da0669
BA		 4586 schedule_work(&adapter->reset_task);
4587 /* return immediately since reset is imminent */
4588 return;
bc7f75fa
AK		 4589 }
4590
eab2abf5
JB		 4591 /* Simple mode for Interrupt Throttle Rate (ITR) */
4592 if (adapter->itr_setting == 4) {
4593 /*
4594 * Symmetric Tx/Rx gets a reduced ITR=2000;
4595 * Total asymmetrical Tx or Rx gets ITR=8000;
4596 * everyone else is between 2000-8000.
4597 */
4598 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4599 u32 dif = (adapter->gotc > adapter->gorc ?
4600 adapter->gotc - adapter->gorc :
4601 adapter->gorc - adapter->gotc) / 10000;
4602 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4603
4604 ew32(ITR, 1000000000 / (itr * 256));
4605 }
4606
ad68076e 4607 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4608 if (adapter->msix_entries)
4609 ew32(ICS, adapter->rx_ring->ims_val);
4610 else
4611 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4612
713b3c9e
JB		 4613 /* flush pending descriptors to memory before detecting Tx hang */
4614 e1000e_flush_descriptors(adapter);
4615
bc7f75fa 4616 /* Force detection of hung controller every watchdog period */
3db1cd5c 4617 adapter->detect_tx_hung = true;
bc7f75fa 4618
ad68076e
BA		 4619 /*
4620 * With 82571 controllers, LAA may be overwritten due to controller
4621 * reset from the other port. Set the appropriate LAA in RAR[0]
4622 */
bc7f75fa 4623 if (e1000e_get_laa_state_82571(hw))
69e1e019 4624 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 4625
ff10e13c
CW		 4626 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4627 e1000e_check_82574_phy_workaround(adapter);
4628
bc7f75fa
AK		 4629 /* Reset the timer */
4630 if (!test_bit(__E1000_DOWN, &adapter->state))
4631 mod_timer(&adapter->watchdog_timer,
4632 round_jiffies(jiffies + 2 * HZ));
4633}
4634
4635#define E1000_TX_FLAGS_CSUM 0x00000001
4636#define E1000_TX_FLAGS_VLAN 0x00000002
4637#define E1000_TX_FLAGS_TSO 0x00000004
4638#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4639#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4640#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4641#define E1000_TX_FLAGS_VLAN_SHIFT 16
4642
55aa6985 4643static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4644{
bc7f75fa
AK		 4645 struct e1000_context_desc *context_desc;
4646 struct e1000_buffer *buffer_info;
4647 unsigned int i;
4648 u32 cmd_length = 0;
4649 u16 ipcse = 0, tucse, mss;
4650 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4651
3d5e33c9
BA		 4652 if (!skb_is_gso(skb))
4653 return 0;
bc7f75fa 4654
3d5e33c9 4655 if (skb_header_cloned(skb)) {
90da0669
BA		 4656 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4657
3d5e33c9
BA		 4658 if (err)
4659 return err;
bc7f75fa
AK		 4660 }
4661
3d5e33c9
BA		 4662 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4663 mss = skb_shinfo(skb)->gso_size;
4664 if (skb->protocol == htons(ETH_P_IP)) {
4665 struct iphdr *iph = ip_hdr(skb);
4666 iph->tot_len = 0;
4667 iph->check = 0;
4668 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4669 0, IPPROTO_TCP, 0);
4670 cmd_length = E1000_TXD_CMD_IP;
4671 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4672 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4673 ipv6_hdr(skb)->payload_len = 0;
4674 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4675 &ipv6_hdr(skb)->daddr,
4676 0, IPPROTO_TCP, 0);
4677 ipcse = 0;
4678 }
4679 ipcss = skb_network_offset(skb);
4680 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4681 tucss = skb_transport_offset(skb);
4682 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4683 tucse = 0;
4684
4685 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4686 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4687
4688 i = tx_ring->next_to_use;
4689 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4690 buffer_info = &tx_ring->buffer_info[i];
4691
4692 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4693 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4694 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4695 context_desc->upper_setup.tcp_fields.tucss = tucss;
4696 context_desc->upper_setup.tcp_fields.tucso = tucso;
4697 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4698 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4699 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4700 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4701
4702 buffer_info->time_stamp = jiffies;
4703 buffer_info->next_to_watch = i;
4704
4705 i++;
4706 if (i == tx_ring->count)
4707 i = 0;
4708 tx_ring->next_to_use = i;
4709
4710 return 1;
bc7f75fa
AK		 4711}
4712
55aa6985 4713static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4714{
55aa6985 4715 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4716 struct e1000_context_desc *context_desc;
4717 struct e1000_buffer *buffer_info;
4718 unsigned int i;
4719 u8 css;
af807c82 4720 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4721 __be16 protocol;
bc7f75fa 4722
af807c82
DG		 4723 if (skb->ip_summed != CHECKSUM_PARTIAL)
4724 return 0;
bc7f75fa 4725
5f66f208
AJ		 4726 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4727 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4728 else
4729 protocol = skb->protocol;
4730
3f518390 4731 switch (protocol) {
09640e63 4732 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4733 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4734 cmd_len |= E1000_TXD_CMD_TCP;
4735 break;
09640e63 4736 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4737 /* XXX not handling all IPV6 headers */
4738 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4739 cmd_len |= E1000_TXD_CMD_TCP;
4740 break;
4741 default:
4742 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4743 e_warn("checksum_partial proto=%x!\n",
4744 be16_to_cpu(protocol));
af807c82 4745 break;
bc7f75fa
AK		 4746 }
4747
0d0b1672 4748 css = skb_checksum_start_offset(skb);
af807c82
DG		 4749
4750 i = tx_ring->next_to_use;
4751 buffer_info = &tx_ring->buffer_info[i];
4752 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4753
4754 context_desc->lower_setup.ip_config = 0;
4755 context_desc->upper_setup.tcp_fields.tucss = css;
4756 context_desc->upper_setup.tcp_fields.tucso =
4757 css + skb->csum_offset;
4758 context_desc->upper_setup.tcp_fields.tucse = 0;
4759 context_desc->tcp_seg_setup.data = 0;
4760 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4761
4762 buffer_info->time_stamp = jiffies;
4763 buffer_info->next_to_watch = i;
4764
4765 i++;
4766 if (i == tx_ring->count)
4767 i = 0;
4768 tx_ring->next_to_use = i;
4769
4770 return 1;
bc7f75fa
AK		 4771}
4772
4773#define E1000_MAX_PER_TXD 8192
4774#define E1000_MAX_TXD_PWR 12
4775
55aa6985
BA		 4776static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4777 unsigned int first, unsigned int max_per_txd,
4778 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4779{
55aa6985 4780 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4781 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4782 struct e1000_buffer *buffer_info;
8ddc951c 4783 unsigned int len = skb_headlen(skb);
03b1320d 4784 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4785 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4786
4787 i = tx_ring->next_to_use;
4788
4789 while (len) {
1b7719c4 4790 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4791 size = min(len, max_per_txd);
4792
bc7f75fa 4793 buffer_info->length = size;
bc7f75fa 4794 buffer_info->time_stamp = jiffies;
bc7f75fa 4795 buffer_info->next_to_watch = i;
0be3f55f
NN		 4796 buffer_info->dma = dma_map_single(&pdev->dev,
4797 skb->data + offset,
af667a29 4798 size, DMA_TO_DEVICE);
03b1320d 4799 buffer_info->mapped_as_page = false;
0be3f55f 4800 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4801 goto dma_error;
bc7f75fa
AK		 4802
4803 len -= size;
4804 offset += size;
03b1320d 4805 count++;
1b7719c4
AD		 4806
4807 if (len) {
4808 i++;
4809 if (i == tx_ring->count)
4810 i = 0;
4811 }
bc7f75fa
AK		 4812 }
4813
4814 for (f = 0; f < nr_frags; f++) {
9e903e08 4815 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4816
4817 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4818 len = skb_frag_size(frag);
877749bf 4819 offset = 0;
bc7f75fa
AK		 4820
4821 while (len) {
1b7719c4
AD		 4822 i++;
4823 if (i == tx_ring->count)
4824 i = 0;
4825
bc7f75fa
AK		 4826 buffer_info = &tx_ring->buffer_info[i];
4827 size = min(len, max_per_txd);
bc7f75fa
AK		 4828
4829 buffer_info->length = size;
4830 buffer_info->time_stamp = jiffies;
bc7f75fa 4831 buffer_info->next_to_watch = i;
877749bf
IC		 4832 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4833 offset, size, DMA_TO_DEVICE);
03b1320d 4834 buffer_info->mapped_as_page = true;
0be3f55f 4835 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4836 goto dma_error;
bc7f75fa
AK		 4837
4838 len -= size;
4839 offset += size;
4840 count++;
bc7f75fa
AK		 4841 }
4842 }
4843
af667a29 4844 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4845 /* multiply data chunks by size of headers */
4846 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4847
bc7f75fa 4848 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4849 tx_ring->buffer_info[i].segs = segs;
4850 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4851 tx_ring->buffer_info[first].next_to_watch = i;
4852
4853 return count;
03b1320d
AD		 4854
4855dma_error:
af667a29 4856 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4857 buffer_info->dma = 0;
c1fa347f 4858 if (count)
03b1320d 4859 count--;
c1fa347f
RK		 4860
4861 while (count--) {
af667a29 4862 if (i == 0)
03b1320d 4863 i += tx_ring->count;
c1fa347f 4864 i--;
03b1320d 4865 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4866 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4867 }
4868
4869 return 0;
bc7f75fa
AK		 4870}
4871
55aa6985 4872static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4873{
55aa6985 4874 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4875 struct e1000_tx_desc *tx_desc = NULL;
4876 struct e1000_buffer *buffer_info;
4877 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4878 unsigned int i;
4879
4880 if (tx_flags & E1000_TX_FLAGS_TSO) {
4881 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4882 E1000_TXD_CMD_TSE;
4883 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4884
4885 if (tx_flags & E1000_TX_FLAGS_IPV4)
4886 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4887 }
4888
4889 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4890 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4891 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4892 }
4893
4894 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4895 txd_lower |= E1000_TXD_CMD_VLE;
4896 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4897 }
4898
943146de
BG		 4899 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4900 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4901
bc7f75fa
AK		 4902 i = tx_ring->next_to_use;
4903
36b973df 4904 do {
bc7f75fa
AK		 4905 buffer_info = &tx_ring->buffer_info[i];
4906 tx_desc = E1000_TX_DESC(*tx_ring, i);
4907 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4908 tx_desc->lower.data =
4909 cpu_to_le32(txd_lower | buffer_info->length);
4910 tx_desc->upper.data = cpu_to_le32(txd_upper);
4911
4912 i++;
4913 if (i == tx_ring->count)
4914 i = 0;
36b973df 4915 } while (--count > 0);
bc7f75fa
AK		 4916
4917 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4918
943146de
BG		 4919 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4920 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4921 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4922
ad68076e
BA		 4923 /*
4924 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4925 * know there are new descriptors to fetch. (Only
4926 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4927 * such as IA-64).
4928 */
bc7f75fa
AK		 4929 wmb();
4930
4931 tx_ring->next_to_use = i;
c6e7f51e
BA		 4932
4933 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4934 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4935 else
c5083cf6 4936 writel(i, tx_ring->tail);
c6e7f51e 4937
ad68076e
BA		 4938 /*
4939 * we need this if more than one processor can write to our tail
4940 * at a time, it synchronizes IO on IA64/Altix systems
4941 */
bc7f75fa
AK		 4942 mmiowb();
4943}
4944
4945#define MINIMUM_DHCP_PACKET_SIZE 282
4946static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4947 struct sk_buff *skb)
4948{
4949 struct e1000_hw *hw = &adapter->hw;
4950 u16 length, offset;
4951
4952 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4953 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4954 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4955 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4956 return 0;
4957 }
4958
4959 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4960 return 0;
4961
4962 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4963 return 0;
4964
4965 {
4966 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4967 struct udphdr *udp;
4968
4969 if (ip->protocol != IPPROTO_UDP)
4970 return 0;
4971
4972 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4973 if (ntohs(udp->dest) != 67)
4974 return 0;
4975
4976 offset = (u8 *)udp + 8 - skb->data;
4977 length = skb->len - offset;
4978 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4979 }
4980
4981 return 0;
4982}
4983
55aa6985 4984static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4985{
55aa6985 4986 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4987
55aa6985 4988 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4989 /*
4990 * Herbert's original patch had:
bc7f75fa 4991 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4992 * but since that doesn't exist yet, just open code it.
4993 */
bc7f75fa
AK		 4994 smp_mb();
4995
ad68076e
BA		 4996 /*
4997 * We need to check again in a case another CPU has just
4998 * made room available.
4999 */
55aa6985 5000 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5001 return -EBUSY;
5002
5003 /* A reprieve! */
55aa6985 5004 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5005 ++adapter->restart_queue;
5006 return 0;
5007}
5008
55aa6985 5009static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5010{
55aa6985 5011 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5012 return 0;
55aa6985 5013 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5014}
5015
0e15df49 5016#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 5017static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5018 struct net_device *netdev)
bc7f75fa
AK		 5019{
5020 struct e1000_adapter *adapter = netdev_priv(netdev);
5021 struct e1000_ring *tx_ring = adapter->tx_ring;
5022 unsigned int first;
5023 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5024 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5025 unsigned int tx_flags = 0;
e743d313 5026 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5027 unsigned int nr_frags;
5028 unsigned int mss;
bc7f75fa
AK		 5029 int count = 0;
5030 int tso;
5031 unsigned int f;
bc7f75fa
AK		 5032
5033 if (test_bit(__E1000_DOWN, &adapter->state)) {
5034 dev_kfree_skb_any(skb);
5035 return NETDEV_TX_OK;
5036 }
5037
5038 if (skb->len <= 0) {
5039 dev_kfree_skb_any(skb);
5040 return NETDEV_TX_OK;
5041 }
5042
5043 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5044 /*
5045 * The controller does a simple calculation to
bc7f75fa
AK		 5046 * make sure there is enough room in the FIFO before
5047 * initiating the DMA for each buffer. The calc is:
5048 * 4 = ceil(buffer len/mss). To make sure we don't
5049 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5050 * drops.
5051 */
bc7f75fa
AK		 5052 if (mss) {
5053 u8 hdr_len;
5054 max_per_txd = min(mss << 2, max_per_txd);
5055 max_txd_pwr = fls(max_per_txd) - 1;
5056
ad68076e
BA		 5057 /*
5058 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5059 * points to just header, pull a few bytes of payload from
5060 * frags into skb->data
5061 */
bc7f75fa 5062 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5063 /*
5064 * we do this workaround for ES2LAN, but it is un-necessary,
5065 * avoiding it could save a lot of cycles
5066 */
4e6c709c 5067 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5068 unsigned int pull_size;
5069
a2a5b323 5070 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5071 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5072 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5073 dev_kfree_skb_any(skb);
5074 return NETDEV_TX_OK;
5075 }
e743d313 5076 len = skb_headlen(skb);
bc7f75fa
AK		 5077 }
5078 }
5079
5080 /* reserve a descriptor for the offload context */
5081 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5082 count++;
5083 count++;
5084
5085 count += TXD_USE_COUNT(len, max_txd_pwr);
5086
5087 nr_frags = skb_shinfo(skb)->nr_frags;
5088 for (f = 0; f < nr_frags; f++)
9e903e08 5089 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5090 max_txd_pwr);
5091
5092 if (adapter->hw.mac.tx_pkt_filtering)
5093 e1000_transfer_dhcp_info(adapter, skb);
5094
ad68076e
BA		 5095 /*
5096 * need: count + 2 desc gap to keep tail from touching
5097 * head, otherwise try next time
5098 */
55aa6985 5099 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5100 return NETDEV_TX_BUSY;
bc7f75fa 5101
eab6d18d 5102 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5103 tx_flags |= E1000_TX_FLAGS_VLAN;
5104 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5105 }
5106
5107 first = tx_ring->next_to_use;
5108
55aa6985 5109 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5110 if (tso < 0) {
5111 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5112 return NETDEV_TX_OK;
5113 }
5114
5115 if (tso)
5116 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5117 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5118 tx_flags |= E1000_TX_FLAGS_CSUM;
5119
ad68076e
BA		 5120 /*
5121 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5122 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5123 * no longer assume, we must.
5124 */
bc7f75fa
AK		 5125 if (skb->protocol == htons(ETH_P_IP))
5126 tx_flags |= E1000_TX_FLAGS_IPV4;
5127
943146de
BG		 5128 if (unlikely(skb->no_fcs))
5129 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5130
25985edc 5131 /* if count is 0 then mapping error has occurred */
55aa6985 5132 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5133 if (count) {
80be3129
WB		 5134 skb_tx_timestamp(skb);
5135
3f0cfa3b 5136 netdev_sent_queue(netdev, skb->len);
55aa6985 5137 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5138 /* Make sure there is space in the ring for the next send. */
55aa6985 5139 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5140
5141 } else {
bc7f75fa 5142 dev_kfree_skb_any(skb);
1b7719c4
AD		 5143 tx_ring->buffer_info[first].time_stamp = 0;
5144 tx_ring->next_to_use = first;
bc7f75fa
AK		 5145 }
5146
bc7f75fa
AK		 5147 return NETDEV_TX_OK;
5148}
5149
5150/**
5151 * e1000_tx_timeout - Respond to a Tx Hang
5152 * @netdev: network interface device structure
5153 **/
5154static void e1000_tx_timeout(struct net_device *netdev)
5155{
5156 struct e1000_adapter *adapter = netdev_priv(netdev);
5157
5158 /* Do the reset outside of interrupt context */
5159 adapter->tx_timeout_count++;
5160 schedule_work(&adapter->reset_task);
5161}
5162
5163static void e1000_reset_task(struct work_struct *work)
5164{
5165 struct e1000_adapter *adapter;
5166 adapter = container_of(work, struct e1000_adapter, reset_task);
5167
615b32af
JB		 5168 /* don't run the task if already down */
5169 if (test_bit(__E1000_DOWN, &adapter->state))
5170 return;
5171
affa9dfb
CW		 5172 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5173 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5174 e1000e_dump(adapter);
5175 e_err("Reset adapter\n");
5176 }
bc7f75fa
AK		 5177 e1000e_reinit_locked(adapter);
5178}
5179
5180/**
67fd4fcb 5181 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5182 * @netdev: network interface device structure
67fd4fcb 5183 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5184 *
5185 * Returns the address of the device statistics structure.
bc7f75fa 5186 **/
67fd4fcb
JK		 5187struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5188 struct rtnl_link_stats64 *stats)
bc7f75fa 5189{
67fd4fcb
JK		 5190 struct e1000_adapter *adapter = netdev_priv(netdev);
5191
5192 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5193 spin_lock(&adapter->stats64_lock);
5194 e1000e_update_stats(adapter);
5195 /* Fill out the OS statistics structure */
5196 stats->rx_bytes = adapter->stats.gorc;
5197 stats->rx_packets = adapter->stats.gprc;
5198 stats->tx_bytes = adapter->stats.gotc;
5199 stats->tx_packets = adapter->stats.gptc;
5200 stats->multicast = adapter->stats.mprc;
5201 stats->collisions = adapter->stats.colc;
5202
5203 /* Rx Errors */
5204
5205 /*
5206 * RLEC on some newer hardware can be incorrect so build
5207 * our own version based on RUC and ROC
5208 */
5209 stats->rx_errors = adapter->stats.rxerrc +
5210 adapter->stats.crcerrs + adapter->stats.algnerrc +
5211 adapter->stats.ruc + adapter->stats.roc +
5212 adapter->stats.cexterr;
5213 stats->rx_length_errors = adapter->stats.ruc +
5214 adapter->stats.roc;
5215 stats->rx_crc_errors = adapter->stats.crcerrs;
5216 stats->rx_frame_errors = adapter->stats.algnerrc;
5217 stats->rx_missed_errors = adapter->stats.mpc;
5218
5219 /* Tx Errors */
5220 stats->tx_errors = adapter->stats.ecol +
5221 adapter->stats.latecol;
5222 stats->tx_aborted_errors = adapter->stats.ecol;
5223 stats->tx_window_errors = adapter->stats.latecol;
5224 stats->tx_carrier_errors = adapter->stats.tncrs;
5225
5226 /* Tx Dropped needs to be maintained elsewhere */
5227
5228 spin_unlock(&adapter->stats64_lock);
5229 return stats;
bc7f75fa
AK		 5230}
5231
5232/**
5233 * e1000_change_mtu - Change the Maximum Transfer Unit
5234 * @netdev: network interface device structure
5235 * @new_mtu: new value for maximum frame size
5236 *
5237 * Returns 0 on success, negative on failure
5238 **/
5239static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5240{
5241 struct e1000_adapter *adapter = netdev_priv(netdev);
5242 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5243
2adc55c9 5244 /* Jumbo frame support */
70495a50
BA		 5245 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5246 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5247 e_err("Jumbo Frames not supported.\n");
5248 return -EINVAL;
5249 }
5250
5251 /*
5252 * IP payload checksum (enabled with jumbos/packet-split when
5253 * Rx checksum is enabled) and generation of RSS hash is
5254 * mutually exclusive in the hardware.
5255 */
5256 if ((netdev->features & NETIF_F_RXCSUM) &&
5257 (netdev->features & NETIF_F_RXHASH)) {
5258 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5259 return -EINVAL;
5260 }
bc7f75fa
AK		 5261 }
5262
2adc55c9
BA		 5263 /* Supported frame sizes */
5264 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5265 (max_frame > adapter->max_hw_frame_size)) {
5266 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5267 return -EINVAL;
5268 }
5269
a1ce6473
BA		 5270 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5271 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5272 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5273 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5274 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5275 return -EINVAL;
5276 }
5277
6f461f6c
BA		 5278 /* 82573 Errata 17 */
5279 if (((adapter->hw.mac.type == e1000_82573) ||
5280 (adapter->hw.mac.type == e1000_82574)) &&
5281 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5282 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5283 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5284 }
5285
bc7f75fa 5286 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5287 usleep_range(1000, 2000);
610c9928 5288 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5289 adapter->max_frame_size = max_frame;
610c9928
BA		 5290 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5291 netdev->mtu = new_mtu;
bc7f75fa
AK		 5292 if (netif_running(netdev))
5293 e1000e_down(adapter);
5294
ad68076e
BA		 5295 /*
5296 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5297 * means we reserve 2 more, this pushes us to allocate from the next
5298 * larger slab size.
ad68076e 5299 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5300 * However with the new *_jumbo_rx* routines, jumbo receives will use
5301 * fragmented skbs
ad68076e 5302 */
bc7f75fa 5303
9926146b 5304 if (max_frame <= 2048)
bc7f75fa
AK		 5305 adapter->rx_buffer_len = 2048;
5306 else
5307 adapter->rx_buffer_len = 4096;
5308
5309 /* adjust allocation if LPE protects us, and we aren't using SBP */
5310 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5311 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5312 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5313 + ETH_FCS_LEN;
bc7f75fa 5314
bc7f75fa
AK		 5315 if (netif_running(netdev))
5316 e1000e_up(adapter);
5317 else
5318 e1000e_reset(adapter);
5319
5320 clear_bit(__E1000_RESETTING, &adapter->state);
5321
5322 return 0;
5323}
5324
5325static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5326 int cmd)
5327{
5328 struct e1000_adapter *adapter = netdev_priv(netdev);
5329 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5330
318a94d6 5331 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5332 return -EOPNOTSUPP;
5333
5334 switch (cmd) {
5335 case SIOCGMIIPHY:
5336 data->phy_id = adapter->hw.phy.addr;
5337 break;
5338 case SIOCGMIIREG:
b16a002e
BA		 5339 e1000_phy_read_status(adapter);
5340
7c25769f
BA		 5341 switch (data->reg_num & 0x1F) {
5342 case MII_BMCR:
5343 data->val_out = adapter->phy_regs.bmcr;
5344 break;
5345 case MII_BMSR:
5346 data->val_out = adapter->phy_regs.bmsr;
5347 break;
5348 case MII_PHYSID1:
5349 data->val_out = (adapter->hw.phy.id >> 16);
5350 break;
5351 case MII_PHYSID2:
5352 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5353 break;
5354 case MII_ADVERTISE:
5355 data->val_out = adapter->phy_regs.advertise;
5356 break;
5357 case MII_LPA:
5358 data->val_out = adapter->phy_regs.lpa;
5359 break;
5360 case MII_EXPANSION:
5361 data->val_out = adapter->phy_regs.expansion;
5362 break;
5363 case MII_CTRL1000:
5364 data->val_out = adapter->phy_regs.ctrl1000;
5365 break;
5366 case MII_STAT1000:
5367 data->val_out = adapter->phy_regs.stat1000;
5368 break;
5369 case MII_ESTATUS:
5370 data->val_out = adapter->phy_regs.estatus;
5371 break;
5372 default:
bc7f75fa
AK		 5373 return -EIO;
5374 }
bc7f75fa
AK		 5375 break;
5376 case SIOCSMIIREG:
5377 default:
5378 return -EOPNOTSUPP;
5379 }
5380 return 0;
5381}
5382
5383static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5384{
5385 switch (cmd) {
5386 case SIOCGMIIPHY:
5387 case SIOCGMIIREG:
5388 case SIOCSMIIREG:
5389 return e1000_mii_ioctl(netdev, ifr, cmd);
5390 default:
5391 return -EOPNOTSUPP;
5392 }
5393}
5394
a4f58f54
BA		 5395static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5396{
5397 struct e1000_hw *hw = &adapter->hw;
5398 u32 i, mac_reg;
2b6b168d 5399 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5400 int retval = 0;
5401
5402 /* copy MAC RARs to PHY RARs */
d3738bb8 5403 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5404
2b6b168d
BA		 5405 retval = hw->phy.ops.acquire(hw);
5406 if (retval) {
5407 e_err("Could not acquire PHY\n");
5408 return retval;
5409 }
5410
5411 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5412 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5413 if (retval)
75ce1532 5414 goto release;
2b6b168d
BA		 5415
5416 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5417 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5418 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5419 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5420 (u16)(mac_reg & 0xFFFF));
5421 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5422 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5423 }
5424
5425 /* configure PHY Rx Control register */
2b6b168d 5426 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5427 mac_reg = er32(RCTL);
5428 if (mac_reg & E1000_RCTL_UPE)
5429 phy_reg |= BM_RCTL_UPE;
5430 if (mac_reg & E1000_RCTL_MPE)
5431 phy_reg |= BM_RCTL_MPE;
5432 phy_reg &= ~(BM_RCTL_MO_MASK);
5433 if (mac_reg & E1000_RCTL_MO_3)
5434 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5435 << BM_RCTL_MO_SHIFT);
5436 if (mac_reg & E1000_RCTL_BAM)
5437 phy_reg |= BM_RCTL_BAM;
5438 if (mac_reg & E1000_RCTL_PMCF)
5439 phy_reg |= BM_RCTL_PMCF;
5440 mac_reg = er32(CTRL);
5441 if (mac_reg & E1000_CTRL_RFCE)
5442 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5443 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5444
5445 /* enable PHY wakeup in MAC register */
5446 ew32(WUFC, wufc);
5447 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5448
5449 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5450 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5451 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5452
5453 /* activate PHY wakeup */
2b6b168d
BA		 5454 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5455 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5456 if (retval)
5457 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5458release:
94d8186a 5459 hw->phy.ops.release(hw);
a4f58f54
BA		 5460
5461 return retval;
5462}
5463
23606cf5
RW		 5464static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5465 bool runtime)
bc7f75fa
AK		 5466{
5467 struct net_device *netdev = pci_get_drvdata(pdev);
5468 struct e1000_adapter *adapter = netdev_priv(netdev);
5469 struct e1000_hw *hw = &adapter->hw;
5470 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5471 /* Runtime suspend should only enable wakeup for link changes */
5472 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5473 int retval = 0;
5474
5475 netif_device_detach(netdev);
5476
5477 if (netif_running(netdev)) {
bb9e44d0
BA		 5478 int count = E1000_CHECK_RESET_COUNT;
5479
5480 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5481 usleep_range(10000, 20000);
5482
bc7f75fa
AK		 5483 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5484 e1000e_down(adapter);
5485 e1000_free_irq(adapter);
5486 }
4662e82b 5487 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5488
5489 retval = pci_save_state(pdev);
5490 if (retval)
5491 return retval;
5492
5493 status = er32(STATUS);
5494 if (status & E1000_STATUS_LU)
5495 wufc &= ~E1000_WUFC_LNKC;
5496
5497 if (wufc) {
5498 e1000_setup_rctl(adapter);
ef9b965a 5499 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5500
5501 /* turn on all-multi mode if wake on multicast is enabled */
5502 if (wufc & E1000_WUFC_MC) {
5503 rctl = er32(RCTL);
5504 rctl |= E1000_RCTL_MPE;
5505 ew32(RCTL, rctl);
5506 }
5507
5508 ctrl = er32(CTRL);
5509 /* advertise wake from D3Cold */
5510 #define E1000_CTRL_ADVD3WUC 0x00100000
5511 /* phy power management enable */
5512 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5513 ctrl |= E1000_CTRL_ADVD3WUC;
5514 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5515 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5516 ew32(CTRL, ctrl);
5517
318a94d6
JK		 5518 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5519 adapter->hw.phy.media_type ==
5520 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5521 /* keep the laser running in D3 */
5522 ctrl_ext = er32(CTRL_EXT);
93a23f48 5523 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5524 ew32(CTRL_EXT, ctrl_ext);
5525 }
5526
97ac8cae 5527 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5528 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5529
bc7f75fa
AK		 5530 /* Allow time for pending master requests to run */
5531 e1000e_disable_pcie_master(&adapter->hw);
5532
82776a4b 5533 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5534 /* enable wakeup by the PHY */
5535 retval = e1000_init_phy_wakeup(adapter, wufc);
5536 if (retval)
5537 return retval;
5538 } else {
5539 /* enable wakeup by the MAC */
5540 ew32(WUFC, wufc);
5541 ew32(WUC, E1000_WUC_PME_EN);
5542 }
bc7f75fa
AK		 5543 } else {
5544 ew32(WUC, 0);
5545 ew32(WUFC, 0);
bc7f75fa
AK		 5546 }
5547
4f9de721
RW		 5548 *enable_wake = !!wufc;
5549
bc7f75fa 5550 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5551 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5552 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5553 *enable_wake = true;
bc7f75fa
AK		 5554
5555 if (adapter->hw.phy.type == e1000_phy_igp_3)
5556 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5557
ad68076e
BA		 5558 /*
5559 * Release control of h/w to f/w. If f/w is AMT enabled, this
5560 * would have already happened in close and is redundant.
5561 */
31dbe5b4 5562 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5563
5564 pci_disable_device(pdev);
5565
4f9de721
RW		 5566 return 0;
5567}
5568
5569static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5570{
5571 if (sleep && wake) {
5572 pci_prepare_to_sleep(pdev);
5573 return;
5574 }
5575
5576 pci_wake_from_d3(pdev, wake);
5577 pci_set_power_state(pdev, PCI_D3hot);
5578}
5579
5580static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5581 bool wake)
5582{
5583 struct net_device *netdev = pci_get_drvdata(pdev);
5584 struct e1000_adapter *adapter = netdev_priv(netdev);
5585
005cbdfc
AD		 5586 /*
5587 * The pci-e switch on some quad port adapters will report a
5588 * correctable error when the MAC transitions from D0 to D3. To
5589 * prevent this we need to mask off the correctable errors on the
5590 * downstream port of the pci-e switch.
5591 */
5592 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5593 struct pci_dev *us_dev = pdev->bus->self;
353064de 5594 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5595 u16 devctl;
5596
5597 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5598 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5599 (devctl & ~PCI_EXP_DEVCTL_CERE));
5600
4f9de721 5601 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5602
5603 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5604 } else {
4f9de721 5605 e1000_power_off(pdev, sleep, wake);
005cbdfc 5606 }
bc7f75fa
AK		 5607}
5608
6f461f6c
BA		 5609#ifdef CONFIG_PCIEASPM
5610static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5611{
9f728f53 5612 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5613}
5614#else
5615static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5616{
5617 int pos;
6f461f6c 5618 u16 reg16;
1eae4eb2
AK		 5619
5620 /*
6f461f6c
BA		 5621 * Both device and parent should have the same ASPM setting.
5622 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5623 */
6f461f6c
BA		 5624 pos = pci_pcie_cap(pdev);
5625 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5626 reg16 &= ~state;
5627 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5628
0c75ba22
AB		 5629 if (!pdev->bus->self)
5630 return;
5631
6f461f6c
BA		 5632 pos = pci_pcie_cap(pdev->bus->self);
5633 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5634 reg16 &= ~state;
5635 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5636}
5637#endif
78cd29d5 5638static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5639{
5640 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5641 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5642 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5643
5644 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5645}
5646
aa338601 5647#ifdef CONFIG_PM
23606cf5 5648static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5649{
23606cf5 5650 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5651}
5652
23606cf5 5653static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5654{
5655 struct net_device *netdev = pci_get_drvdata(pdev);
5656 struct e1000_adapter *adapter = netdev_priv(netdev);
5657 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5658 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5659 u32 err;
5660
78cd29d5
BA		 5661 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5662 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5663 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5664 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5665 if (aspm_disable_flag)
5666 e1000e_disable_aspm(pdev, aspm_disable_flag);
5667
bc7f75fa
AK		 5668 pci_set_power_state(pdev, PCI_D0);
5669 pci_restore_state(pdev);
28b8f04a 5670 pci_save_state(pdev);
6e4f6f6b 5671
4662e82b 5672 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5673 if (netif_running(netdev)) {
5674 err = e1000_request_irq(adapter);
5675 if (err)
5676 return err;
5677 }
5678
99730e4c
BA		 5679 if (hw->mac.type == e1000_pch2lan)
5680 e1000_resume_workarounds_pchlan(&adapter->hw);
5681
bc7f75fa 5682 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5683
5684 /* report the system wakeup cause from S3/S4 */
5685 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5686 u16 phy_data;
5687
5688 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5689 if (phy_data) {
5690 e_info("PHY Wakeup cause - %s\n",
5691 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5692 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5693 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5694 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5695 phy_data & E1000_WUS_LNKC ?
5696 "Link Status Change" : "other");
a4f58f54
BA		 5697 }
5698 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5699 } else {
5700 u32 wus = er32(WUS);
5701 if (wus) {
5702 e_info("MAC Wakeup cause - %s\n",
5703 wus & E1000_WUS_EX ? "Unicast Packet" :
5704 wus & E1000_WUS_MC ? "Multicast Packet" :
5705 wus & E1000_WUS_BC ? "Broadcast Packet" :
5706 wus & E1000_WUS_MAG ? "Magic Packet" :
5707 wus & E1000_WUS_LNKC ? "Link Status Change" :
5708 "other");
5709 }
5710 ew32(WUS, ~0);
5711 }
5712
bc7f75fa 5713 e1000e_reset(adapter);
bc7f75fa 5714
cd791618 5715 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5716
5717 if (netif_running(netdev))
5718 e1000e_up(adapter);
5719
5720 netif_device_attach(netdev);
5721
ad68076e
BA		 5722 /*
5723 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5724 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5725 * under the control of the driver.
5726 */
c43bc57e 5727 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5728 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5729
5730 return 0;
5731}
23606cf5 5732
a0340162
RW		 5733#ifdef CONFIG_PM_SLEEP
5734static int e1000_suspend(struct device *dev)
5735{
5736 struct pci_dev *pdev = to_pci_dev(dev);
5737 int retval;
5738 bool wake;
5739
5740 retval = __e1000_shutdown(pdev, &wake, false);
5741 if (!retval)
5742 e1000_complete_shutdown(pdev, true, wake);
5743
5744 return retval;
5745}
5746
23606cf5
RW		 5747static int e1000_resume(struct device *dev)
5748{
5749 struct pci_dev *pdev = to_pci_dev(dev);
5750 struct net_device *netdev = pci_get_drvdata(pdev);
5751 struct e1000_adapter *adapter = netdev_priv(netdev);
5752
5753 if (e1000e_pm_ready(adapter))
5754 adapter->idle_check = true;
5755
5756 return __e1000_resume(pdev);
5757}
a0340162
RW		 5758#endif /* CONFIG_PM_SLEEP */
5759
5760#ifdef CONFIG_PM_RUNTIME
5761static int e1000_runtime_suspend(struct device *dev)
5762{
5763 struct pci_dev *pdev = to_pci_dev(dev);
5764 struct net_device *netdev = pci_get_drvdata(pdev);
5765 struct e1000_adapter *adapter = netdev_priv(netdev);
5766
5767 if (e1000e_pm_ready(adapter)) {
5768 bool wake;
5769
5770 __e1000_shutdown(pdev, &wake, true);
5771 }
5772
5773 return 0;
5774}
5775
5776static int e1000_idle(struct device *dev)
5777{
5778 struct pci_dev *pdev = to_pci_dev(dev);
5779 struct net_device *netdev = pci_get_drvdata(pdev);
5780 struct e1000_adapter *adapter = netdev_priv(netdev);
5781
5782 if (!e1000e_pm_ready(adapter))
5783 return 0;
5784
5785 if (adapter->idle_check) {
5786 adapter->idle_check = false;
5787 if (!e1000e_has_link(adapter))
5788 pm_schedule_suspend(dev, MSEC_PER_SEC);
5789 }
5790
5791 return -EBUSY;
5792}
23606cf5
RW		 5793
5794static int e1000_runtime_resume(struct device *dev)
5795{
5796 struct pci_dev *pdev = to_pci_dev(dev);
5797 struct net_device *netdev = pci_get_drvdata(pdev);
5798 struct e1000_adapter *adapter = netdev_priv(netdev);
5799
5800 if (!e1000e_pm_ready(adapter))
5801 return 0;
5802
5803 adapter->idle_check = !dev->power.runtime_auto;
5804 return __e1000_resume(pdev);
5805}
a0340162 5806#endif /* CONFIG_PM_RUNTIME */
aa338601 5807#endif /* CONFIG_PM */
bc7f75fa
AK		 5808
5809static void e1000_shutdown(struct pci_dev *pdev)
5810{
4f9de721
RW		 5811 bool wake = false;
5812
23606cf5 5813 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5814
5815 if (system_state == SYSTEM_POWER_OFF)
5816 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5817}
5818
5819#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5820
5821static irqreturn_t e1000_intr_msix(int irq, void *data)
5822{
5823 struct net_device *netdev = data;
5824 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5825
5826 if (adapter->msix_entries) {
90da0669
BA		 5827 int vector, msix_irq;
5828
147b2c8c
DD		 5829 vector = 0;
5830 msix_irq = adapter->msix_entries[vector].vector;
5831 disable_irq(msix_irq);
5832 e1000_intr_msix_rx(msix_irq, netdev);
5833 enable_irq(msix_irq);
5834
5835 vector++;
5836 msix_irq = adapter->msix_entries[vector].vector;
5837 disable_irq(msix_irq);
5838 e1000_intr_msix_tx(msix_irq, netdev);
5839 enable_irq(msix_irq);
5840
5841 vector++;
5842 msix_irq = adapter->msix_entries[vector].vector;
5843 disable_irq(msix_irq);
5844 e1000_msix_other(msix_irq, netdev);
5845 enable_irq(msix_irq);
5846 }
5847
5848 return IRQ_HANDLED;
5849}
5850
bc7f75fa
AK		 5851/*
5852 * Polling 'interrupt' - used by things like netconsole to send skbs
5853 * without having to re-enable interrupts. It's not called while
5854 * the interrupt routine is executing.
5855 */
5856static void e1000_netpoll(struct net_device *netdev)
5857{
5858 struct e1000_adapter *adapter = netdev_priv(netdev);
5859
147b2c8c
DD		 5860 switch (adapter->int_mode) {
5861 case E1000E_INT_MODE_MSIX:
5862 e1000_intr_msix(adapter->pdev->irq, netdev);
5863 break;
5864 case E1000E_INT_MODE_MSI:
5865 disable_irq(adapter->pdev->irq);
5866 e1000_intr_msi(adapter->pdev->irq, netdev);
5867 enable_irq(adapter->pdev->irq);
5868 break;
5869 default: /* E1000E_INT_MODE_LEGACY */
5870 disable_irq(adapter->pdev->irq);
5871 e1000_intr(adapter->pdev->irq, netdev);
5872 enable_irq(adapter->pdev->irq);
5873 break;
5874 }
bc7f75fa
AK		 5875}
5876#endif
5877
5878/**
5879 * e1000_io_error_detected - called when PCI error is detected
5880 * @pdev: Pointer to PCI device
5881 * @state: The current pci connection state
5882 *
5883 * This function is called after a PCI bus error affecting
5884 * this device has been detected.
5885 */
5886static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5887 pci_channel_state_t state)
5888{
5889 struct net_device *netdev = pci_get_drvdata(pdev);
5890 struct e1000_adapter *adapter = netdev_priv(netdev);
5891
5892 netif_device_detach(netdev);
5893
c93b5a76
MM		 5894 if (state == pci_channel_io_perm_failure)
5895 return PCI_ERS_RESULT_DISCONNECT;
5896
bc7f75fa
AK		 5897 if (netif_running(netdev))
5898 e1000e_down(adapter);
5899 pci_disable_device(pdev);
5900
5901 /* Request a slot slot reset. */
5902 return PCI_ERS_RESULT_NEED_RESET;
5903}
5904
5905/**
5906 * e1000_io_slot_reset - called after the pci bus has been reset.
5907 * @pdev: Pointer to PCI device
5908 *
5909 * Restart the card from scratch, as if from a cold-boot. Implementation
5910 * resembles the first-half of the e1000_resume routine.
5911 */
5912static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5913{
5914 struct net_device *netdev = pci_get_drvdata(pdev);
5915 struct e1000_adapter *adapter = netdev_priv(netdev);
5916 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5917 u16 aspm_disable_flag = 0;
6e4f6f6b 5918 int err;
111b9dc5 5919 pci_ers_result_t result;
bc7f75fa 5920
78cd29d5
BA		 5921 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5922 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5923 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5924 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5925 if (aspm_disable_flag)
5926 e1000e_disable_aspm(pdev, aspm_disable_flag);
5927
f0f422e5 5928 err = pci_enable_device_mem(pdev);
6e4f6f6b 5929 if (err) {
bc7f75fa
AK		 5930 dev_err(&pdev->dev,
5931 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5932 result = PCI_ERS_RESULT_DISCONNECT;
5933 } else {
5934 pci_set_master(pdev);
23606cf5 5935 pdev->state_saved = true;
111b9dc5 5936 pci_restore_state(pdev);
bc7f75fa 5937
111b9dc5
JB		 5938 pci_enable_wake(pdev, PCI_D3hot, 0);
5939 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5940
111b9dc5
JB		 5941 e1000e_reset(adapter);
5942 ew32(WUS, ~0);
5943 result = PCI_ERS_RESULT_RECOVERED;
5944 }
bc7f75fa 5945
111b9dc5
JB		 5946 pci_cleanup_aer_uncorrect_error_status(pdev);
5947
5948 return result;
bc7f75fa
AK		 5949}
5950
5951/**
5952 * e1000_io_resume - called when traffic can start flowing again.
5953 * @pdev: Pointer to PCI device
5954 *
5955 * This callback is called when the error recovery driver tells us that
5956 * its OK to resume normal operation. Implementation resembles the
5957 * second-half of the e1000_resume routine.
5958 */
5959static void e1000_io_resume(struct pci_dev *pdev)
5960{
5961 struct net_device *netdev = pci_get_drvdata(pdev);
5962 struct e1000_adapter *adapter = netdev_priv(netdev);
5963
cd791618 5964 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5965
5966 if (netif_running(netdev)) {
5967 if (e1000e_up(adapter)) {
5968 dev_err(&pdev->dev,
5969 "can't bring device back up after reset\n");
5970 return;
5971 }
5972 }
5973
5974 netif_device_attach(netdev);
5975
ad68076e
BA		 5976 /*
5977 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5978 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5979 * under the control of the driver.
5980 */
c43bc57e 5981 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5982 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5983
5984}
5985
5986static void e1000_print_device_info(struct e1000_adapter *adapter)
5987{
5988 struct e1000_hw *hw = &adapter->hw;
5989 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5990 u32 ret_val;
5991 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5992
5993 /* print bus type/speed/width info */
a5cc7642 5994 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5995 /* bus width */
5996 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5997 "Width x1"),
5998 /* MAC address */
7c510e4b 5999 netdev->dev_addr);
44defeb3
JK		 6000 e_info("Intel(R) PRO/%s Network Connection\n",
6001 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6002 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6003 E1000_PBANUM_LENGTH);
6004 if (ret_val)
f2315bf1 6005 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6006 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6007 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6008}
6009
10aa4c04
AK		 6010static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6011{
6012 struct e1000_hw *hw = &adapter->hw;
6013 int ret_val;
6014 u16 buf = 0;
6015
6016 if (hw->mac.type != e1000_82573)
6017 return;
6018
6019 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6020 le16_to_cpus(&buf);
6021 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6022 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6023 dev_warn(&adapter->pdev->dev,
6024 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6025 }
10aa4c04
AK		 6026}
6027
c8f44aff 6028static int e1000_set_features(struct net_device *netdev,
70495a50 6029 netdev_features_t features)
dc221294
BA		 6030{
6031 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6032 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6033
6034 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6035 adapter->flags |= FLAG_TSO_FORCE;
6036
6037 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6038 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6039 NETIF_F_RXALL)))
dc221294
BA		 6040 return 0;
6041
70495a50
BA		 6042 /*
6043 * IP payload checksum (enabled with jumbos/packet-split when Rx
6044 * checksum is enabled) and generation of RSS hash is mutually
6045 * exclusive in the hardware.
6046 */
6047 if (adapter->rx_ps_pages &&
6048 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6049 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6050 return -EINVAL;
6051 }
6052
0184039a
BG		 6053 if (changed & NETIF_F_RXFCS) {
6054 if (features & NETIF_F_RXFCS) {
6055 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6056 } else {
6057 /* We need to take it back to defaults, which might mean
6058 * stripping is still disabled at the adapter level.
6059 */
6060 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6061 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6062 else
6063 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6064 }
6065 }
6066
70495a50
BA		 6067 netdev->features = features;
6068
dc221294
BA		 6069 if (netif_running(netdev))
6070 e1000e_reinit_locked(adapter);
6071 else
6072 e1000e_reset(adapter);
6073
6074 return 0;
6075}
6076
651c2466
SH		 6077static const struct net_device_ops e1000e_netdev_ops = {
6078 .ndo_open = e1000_open,
6079 .ndo_stop = e1000_close,
00829823 6080 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6081 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6082 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6083 .ndo_set_mac_address = e1000_set_mac,
6084 .ndo_change_mtu = e1000_change_mtu,
6085 .ndo_do_ioctl = e1000_ioctl,
6086 .ndo_tx_timeout = e1000_tx_timeout,
6087 .ndo_validate_addr = eth_validate_addr,
6088
651c2466
SH		 6089 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6090 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6091#ifdef CONFIG_NET_POLL_CONTROLLER
6092 .ndo_poll_controller = e1000_netpoll,
6093#endif
dc221294 6094 .ndo_set_features = e1000_set_features,
651c2466
SH		 6095};
6096
bc7f75fa
AK		 6097/**
6098 * e1000_probe - Device Initialization Routine
6099 * @pdev: PCI device information struct
6100 * @ent: entry in e1000_pci_tbl
6101 *
6102 * Returns 0 on success, negative on failure
6103 *
6104 * e1000_probe initializes an adapter identified by a pci_dev structure.
6105 * The OS initialization, configuring of the adapter private structure,
6106 * and a hardware reset occur.
6107 **/
6108static int __devinit e1000_probe(struct pci_dev *pdev,
6109 const struct pci_device_id *ent)
6110{
6111 struct net_device *netdev;
6112 struct e1000_adapter *adapter;
6113 struct e1000_hw *hw;
6114 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6115 resource_size_t mmio_start, mmio_len;
6116 resource_size_t flash_start, flash_len;
bc7f75fa 6117 static int cards_found;
78cd29d5 6118 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6119 int i, err, pci_using_dac;
6120 u16 eeprom_data = 0;
6121 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6122
78cd29d5
BA		 6123 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6124 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6125 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6126 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6127 if (aspm_disable_flag)
6128 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6129
f0f422e5 6130 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6131 if (err)
6132 return err;
6133
6134 pci_using_dac = 0;
0be3f55f 6135 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6136 if (!err) {
0be3f55f 6137 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6138 if (!err)
6139 pci_using_dac = 1;
6140 } else {
0be3f55f 6141 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6142 if (err) {
0be3f55f
NN		 6143 err = dma_set_coherent_mask(&pdev->dev,
6144 DMA_BIT_MASK(32));
bc7f75fa 6145 if (err) {
ef456f85 6146 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6147 goto err_dma;
6148 }
6149 }
6150 }
6151
e8de1481 6152 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6153 pci_select_bars(pdev, IORESOURCE_MEM),
6154 e1000e_driver_name);
bc7f75fa
AK		 6155 if (err)
6156 goto err_pci_reg;
6157
68eac460 6158 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6159 pci_enable_pcie_error_reporting(pdev);
68eac460 6160
bc7f75fa 6161 pci_set_master(pdev);
438b365a
BA		 6162 /* PCI config space info */
6163 err = pci_save_state(pdev);
6164 if (err)
6165 goto err_alloc_etherdev;
bc7f75fa
AK		 6166
6167 err = -ENOMEM;
6168 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6169 if (!netdev)
6170 goto err_alloc_etherdev;
6171
bc7f75fa
AK		 6172 SET_NETDEV_DEV(netdev, &pdev->dev);
6173
f85e4dfa
TH		 6174 netdev->irq = pdev->irq;
6175
bc7f75fa
AK		 6176 pci_set_drvdata(pdev, netdev);
6177 adapter = netdev_priv(netdev);
6178 hw = &adapter->hw;
6179 adapter->netdev = netdev;
6180 adapter->pdev = pdev;
6181 adapter->ei = ei;
6182 adapter->pba = ei->pba;
6183 adapter->flags = ei->flags;
eb7c3adb 6184 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6185 adapter->hw.adapter = adapter;
6186 adapter->hw.mac.type = ei->mac;
2adc55c9 6187 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6188 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6189
6190 mmio_start = pci_resource_start(pdev, 0);
6191 mmio_len = pci_resource_len(pdev, 0);
6192
6193 err = -EIO;
6194 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6195 if (!adapter->hw.hw_addr)
6196 goto err_ioremap;
6197
6198 if ((adapter->flags & FLAG_HAS_FLASH) &&
6199 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6200 flash_start = pci_resource_start(pdev, 1);
6201 flash_len = pci_resource_len(pdev, 1);
6202 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6203 if (!adapter->hw.flash_address)
6204 goto err_flashmap;
6205 }
6206
6207 /* construct the net_device struct */
651c2466 6208 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6209 e1000e_set_ethtool_ops(netdev);
bc7f75fa 6210 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6211 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6212 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6213
6214 netdev->mem_start = mmio_start;
6215 netdev->mem_end = mmio_start + mmio_len;
6216
6217 adapter->bd_number = cards_found++;
6218
4662e82b
BA		 6219 e1000e_check_options(adapter);
6220
bc7f75fa
AK		 6221 /* setup adapter struct */
6222 err = e1000_sw_init(adapter);
6223 if (err)
6224 goto err_sw_init;
6225
bc7f75fa
AK		 6226 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6227 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6228 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6229
69e3fd8c 6230 err = ei->get_variants(adapter);
bc7f75fa
AK		 6231 if (err)
6232 goto err_hw_init;
6233
4a770358
BA		 6234 if ((adapter->flags & FLAG_IS_ICH) &&
6235 (adapter->flags & FLAG_READ_ONLY_NVM))
6236 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6237
bc7f75fa
AK		 6238 hw->mac.ops.get_bus_info(&adapter->hw);
6239
318a94d6 6240 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6241
6242 /* Copper options */
318a94d6 6243 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6244 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6245 adapter->hw.phy.disable_polarity_correction = 0;
6246 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6247 }
6248
44abd5c1 6249 if (hw->phy.ops.check_reset_block(hw))
44defeb3 6250 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6251
dc221294
BA		 6252 /* Set initial default active device features */
6253 netdev->features = (NETIF_F_SG |
6254 NETIF_F_HW_VLAN_RX |
6255 NETIF_F_HW_VLAN_TX |
6256 NETIF_F_TSO |
6257 NETIF_F_TSO6 |
70495a50 6258 NETIF_F_RXHASH |
dc221294
BA		 6259 NETIF_F_RXCSUM |
6260 NETIF_F_HW_CSUM);
6261
6262 /* Set user-changeable features (subset of all device features) */
6263 netdev->hw_features = netdev->features;
0184039a 6264 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6265 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6266 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6267
6268 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6269 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6270
dc221294
BA		 6271 netdev->vlan_features |= (NETIF_F_SG |
6272 NETIF_F_TSO |
6273 NETIF_F_TSO6 |
6274 NETIF_F_HW_CSUM);
a5136e23 6275
ef9b965a
JB		 6276 netdev->priv_flags |= IFF_UNICAST_FLT;
6277
7b872a55 6278 if (pci_using_dac) {
bc7f75fa 6279 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6280 netdev->vlan_features |= NETIF_F_HIGHDMA;
6281 }
bc7f75fa 6282
bc7f75fa
AK		 6283 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6284 adapter->flags |= FLAG_MNG_PT_ENABLED;
6285
ad68076e
BA		 6286 /*
6287 * before reading the NVM, reset the controller to
6288 * put the device in a known good starting state
6289 */
bc7f75fa
AK		 6290 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6291
6292 /*
6293 * systems with ASPM and others may see the checksum fail on the first
6294 * attempt. Let's give it a few tries
6295 */
6296 for (i = 0;; i++) {
6297 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6298 break;
6299 if (i == 2) {
44defeb3 6300 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6301 err = -EIO;
6302 goto err_eeprom;
6303 }
6304 }
6305
10aa4c04
AK		 6306 e1000_eeprom_checks(adapter);
6307
608f8a0d 6308 /* copy the MAC address */
bc7f75fa 6309 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6310 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6311
6312 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6313 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6314
6315 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6316 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6317 err = -EIO;
6318 goto err_eeprom;
6319 }
6320
6321 init_timer(&adapter->watchdog_timer);
c061b18d 6322 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6323 adapter->watchdog_timer.data = (unsigned long) adapter;
6324
6325 init_timer(&adapter->phy_info_timer);
c061b18d 6326 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6327 adapter->phy_info_timer.data = (unsigned long) adapter;
6328
6329 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6330 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6331 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6332 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6333 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6334
bc7f75fa
AK		 6335 /* Initialize link parameters. User can change them with ethtool */
6336 adapter->hw.mac.autoneg = 1;
3db1cd5c 6337 adapter->fc_autoneg = true;
5c48ef3e
BA		 6338 adapter->hw.fc.requested_mode = e1000_fc_default;
6339 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6340 adapter->hw.phy.autoneg_advertised = 0x2f;
6341
6342 /* ring size defaults */
6343 adapter->rx_ring->count = 256;
6344 adapter->tx_ring->count = 256;
6345
6346 /*
6347 * Initial Wake on LAN setting - If APM wake is enabled in
6348 * the EEPROM, enable the ACPI Magic Packet filter
6349 */
6350 if (adapter->flags & FLAG_APME_IN_WUC) {
6351 /* APME bit in EEPROM is mapped to WUC.APME */
6352 eeprom_data = er32(WUC);
6353 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6354 if ((hw->mac.type > e1000_ich10lan) &&
6355 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6356 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6357 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6358 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6359 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6360 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6361 1, &eeprom_data);
bc7f75fa 6362 else
3d3a1676
BA		 6363 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6364 1, &eeprom_data);
bc7f75fa
AK		 6365 }
6366
6367 /* fetch WoL from EEPROM */
6368 if (eeprom_data & eeprom_apme_mask)
6369 adapter->eeprom_wol |= E1000_WUFC_MAG;
6370
6371 /*
6372 * now that we have the eeprom settings, apply the special cases
6373 * where the eeprom may be wrong or the board simply won't support
6374 * wake on lan on a particular port
6375 */
6376 if (!(adapter->flags & FLAG_HAS_WOL))
6377 adapter->eeprom_wol = 0;
6378
6379 /* initialize the wol settings based on the eeprom settings */
6380 adapter->wol = adapter->eeprom_wol;
6ff68026 6381 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6382
84527590
BA		 6383 /* save off EEPROM version number */
6384 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6385
bc7f75fa
AK		 6386 /* reset the hardware with the new settings */
6387 e1000e_reset(adapter);
6388
ad68076e
BA		 6389 /*
6390 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6391 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6392 * under the control of the driver.
6393 */
c43bc57e 6394 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6395 e1000e_get_hw_control(adapter);
bc7f75fa 6396
f2315bf1 6397 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6398 err = register_netdev(netdev);
6399 if (err)
6400 goto err_register;
6401
9c563d20
JB		 6402 /* carrier off reporting is important to ethtool even BEFORE open */
6403 netif_carrier_off(netdev);
6404
bc7f75fa
AK		 6405 e1000_print_device_info(adapter);
6406
f3ec4f87
AS		 6407 if (pci_dev_run_wake(pdev))
6408 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6409
bc7f75fa
AK		 6410 return 0;
6411
6412err_register:
c43bc57e 6413 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6414 e1000e_release_hw_control(adapter);
bc7f75fa 6415err_eeprom:
44abd5c1 6416 if (!hw->phy.ops.check_reset_block(hw))
bc7f75fa 6417 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6418err_hw_init:
bc7f75fa
AK		 6419 kfree(adapter->tx_ring);
6420 kfree(adapter->rx_ring);
6421err_sw_init:
c43bc57e
JB		 6422 if (adapter->hw.flash_address)
6423 iounmap(adapter->hw.flash_address);
e82f54ba 6424 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6425err_flashmap:
bc7f75fa
AK		 6426 iounmap(adapter->hw.hw_addr);
6427err_ioremap:
6428 free_netdev(netdev);
6429err_alloc_etherdev:
f0f422e5
BA		 6430 pci_release_selected_regions(pdev,
6431 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6432err_pci_reg:
6433err_dma:
6434 pci_disable_device(pdev);
6435 return err;
6436}
6437
6438/**
6439 * e1000_remove - Device Removal Routine
6440 * @pdev: PCI device information struct
6441 *
6442 * e1000_remove is called by the PCI subsystem to alert the driver
6443 * that it should release a PCI device. The could be caused by a
6444 * Hot-Plug event, or because the driver is going to be removed from
6445 * memory.
6446 **/
6447static void __devexit e1000_remove(struct pci_dev *pdev)
6448{
6449 struct net_device *netdev = pci_get_drvdata(pdev);
6450 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6451 bool down = test_bit(__E1000_DOWN, &adapter->state);
6452
ad68076e 6453 /*
23f333a2
TH		 6454 * The timers may be rescheduled, so explicitly disable them
6455 * from being rescheduled.
ad68076e 6456 */
23606cf5
RW		 6457 if (!down)
6458 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6459 del_timer_sync(&adapter->watchdog_timer);
6460 del_timer_sync(&adapter->phy_info_timer);
6461
41cec6f1
BA		 6462 cancel_work_sync(&adapter->reset_task);
6463 cancel_work_sync(&adapter->watchdog_task);
6464 cancel_work_sync(&adapter->downshift_task);
6465 cancel_work_sync(&adapter->update_phy_task);
6466 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6467
17f208de
BA		 6468 if (!(netdev->flags & IFF_UP))
6469 e1000_power_down_phy(adapter);
6470
23606cf5
RW		 6471 /* Don't lie to e1000_close() down the road. */
6472 if (!down)
6473 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6474 unregister_netdev(netdev);
6475
f3ec4f87
AS		 6476 if (pci_dev_run_wake(pdev))
6477 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6478
ad68076e
BA		 6479 /*
6480 * Release control of h/w to f/w. If f/w is AMT enabled, this
6481 * would have already happened in close and is redundant.
6482 */
31dbe5b4 6483 e1000e_release_hw_control(adapter);
bc7f75fa 6484
4662e82b 6485 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6486 kfree(adapter->tx_ring);
6487 kfree(adapter->rx_ring);
6488
6489 iounmap(adapter->hw.hw_addr);
6490 if (adapter->hw.flash_address)
6491 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6492 pci_release_selected_regions(pdev,
6493 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6494
6495 free_netdev(netdev);
6496
111b9dc5 6497 /* AER disable */
19d5afd4 6498 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6499
bc7f75fa
AK		 6500 pci_disable_device(pdev);
6501}
6502
6503/* PCI Error Recovery (ERS) */
6504static struct pci_error_handlers e1000_err_handler = {
6505 .error_detected = e1000_io_error_detected,
6506 .slot_reset = e1000_io_slot_reset,
6507 .resume = e1000_io_resume,
6508};
6509
a3aa1884 6510static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6520
bc7f75fa
AK		 6521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6525
bc7f75fa
AK		 6526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6529
4662e82b 6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6532 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6533
bc7f75fa
AK		 6534 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6535 board_80003es2lan },
6536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6537 board_80003es2lan },
6538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6539 board_80003es2lan },
6540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6541 board_80003es2lan },
ad68076e 6542
bc7f75fa
AK		 6543 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6551
bc7f75fa
AK		 6552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6553 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6557 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6561
6562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6565
f4187b56
BA		 6566 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6567 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6568 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6569
a4f58f54
BA		 6570 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6571 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6572 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6573 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6574
d3738bb8
BA		 6575 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6576 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6577
f36bb6ca 6578 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6579};
6580MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6581
aa338601 6582#ifdef CONFIG_PM
23606cf5 6583static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6584 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6585 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6586 e1000_runtime_resume, e1000_idle)
23606cf5 6587};
e50208a0 6588#endif
23606cf5 6589
bc7f75fa
AK		 6590/* PCI Device API Driver */
6591static struct pci_driver e1000_driver = {
6592 .name = e1000e_driver_name,
6593 .id_table = e1000_pci_tbl,
6594 .probe = e1000_probe,
6595 .remove = __devexit_p(e1000_remove),
aa338601 6596#ifdef CONFIG_PM
f36bb6ca
BA		 6597 .driver = {
6598 .pm = &e1000_pm_ops,
6599 },
bc7f75fa
AK		 6600#endif
6601 .shutdown = e1000_shutdown,
6602 .err_handler = &e1000_err_handler
6603};
6604
6605/**
6606 * e1000_init_module - Driver Registration Routine
6607 *
6608 * e1000_init_module is the first routine called when the driver is
6609 * loaded. All it does is register with the PCI subsystem.
6610 **/
6611static int __init e1000_init_module(void)
6612{
6613 int ret;
8544b9f7
BA		 6614 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6615 e1000e_driver_version);
f5e261e6 6616 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6617 ret = pci_register_driver(&e1000_driver);
53ec5498 6618
bc7f75fa
AK		 6619 return ret;
6620}
6621module_init(e1000_init_module);
6622
6623/**
6624 * e1000_exit_module - Driver Exit Cleanup Routine
6625 *
6626 * e1000_exit_module is called just before the driver is removed
6627 * from memory.
6628 **/
6629static void __exit e1000_exit_module(void)
6630{
6631 pci_unregister_driver(&e1000_driver);
6632}
6633module_exit(e1000_exit_module);
6634
6635
6636MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6637MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6638MODULE_LICENSE("GPL");
6639MODULE_VERSION(DRV_VERSION);
6640
06c24b91 6641/* netdev.c */
Linux kernel - Deliverables
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