[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k.h

/* Intel Ethernet Switch Host Interface Driver
 * Copyright(c) 2013 - 2015 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 */

#ifndef _FM10K_H_
#define _FM10K_H_

#include <linux/types.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>
#include <linux/pci.h>
#include <linux/net_tstamp.h>
#include <linux/clocksource.h>
#include <linux/ptp_clock_kernel.h>

#include "fm10k_pf.h"
#include "fm10k_vf.h"

#define FM10K_MAX_JUMBO_FRAME_SIZE	15358	/* Maximum supported size 15K */

#define MAX_QUEUES	FM10K_MAX_QUEUES_PF

#define FM10K_MIN_RXD		 128
#define FM10K_MAX_RXD		4096
#define FM10K_DEFAULT_RXD	 256

#define FM10K_MIN_TXD		 128
#define FM10K_MAX_TXD		4096
#define FM10K_DEFAULT_TXD	 256
#define FM10K_DEFAULT_TX_WORK	 256

#define FM10K_RXBUFFER_256	  256
#define FM10K_RX_HDR_LEN	FM10K_RXBUFFER_256
#define FM10K_RXBUFFER_2048	 2048
#define FM10K_RX_BUFSZ		FM10K_RXBUFFER_2048

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define FM10K_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define FM10K_MAX_STATIONS	63
struct fm10k_l2_accel {
	int size;
	u16 count;
	u16 dglort;
	struct rcu_head rcu;
	struct net_device *macvlan[0];
};

enum fm10k_ring_state_t {
	__FM10K_TX_DETECT_HANG,
	__FM10K_HANG_CHECK_ARMED,
};

#define check_for_tx_hang(ring) \
	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)

struct fm10k_tx_buffer {
	struct fm10k_tx_desc *next_to_watch;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	u16 tx_flags;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
};

struct fm10k_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	u32 page_offset;
};

struct fm10k_queue_stats {
	u64 packets;
	u64 bytes;
};

struct fm10k_tx_queue_stats {
	u64 restart_queue;
	u64 csum_err;
	u64 tx_busy;
	u64 tx_done_old;
	u64 csum_good;
};

struct fm10k_rx_queue_stats {
	u64 alloc_failed;
	u64 csum_err;
	u64 errors;
	u64 csum_good;
	u64 switch_errors;
	u64 drops;
	u64 pp_errors;
	u64 link_errors;
	u64 length_errors;
};

struct fm10k_ring {
	struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
	struct net_device *netdev;	/* netdev ring belongs to */
	struct device *dev;		/* device for DMA mapping */
	struct fm10k_l2_accel __rcu *l2_accel;	/* L2 acceleration list */
	void *desc;			/* descriptor ring memory */
	union {
		struct fm10k_tx_buffer *tx_buffer;
		struct fm10k_rx_buffer *rx_buffer;
	};
	u32 __iomem *tail;
	unsigned long state;
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */

	u8 queue_index;			/* needed for queue management */
	u8 reg_idx;			/* holds the special value that gets
					 * the hardware register offset
					 * associated with this ring, which is
					 * different for DCB and RSS modes
					 */
	u8 qos_pc;			/* priority class of queue */
	u16 vid;			/* default vlan ID of queue */
	u16 count;			/* amount of descriptors */

	u16 next_to_alloc;
	u16 next_to_use;
	u16 next_to_clean;

	struct fm10k_queue_stats stats;
	struct u64_stats_sync syncp;
	union {
		/* Tx */
		struct fm10k_tx_queue_stats tx_stats;
		/* Rx */
		struct {
			struct fm10k_rx_queue_stats rx_stats;
			struct sk_buff *skb;
		};
	};
} ____cacheline_internodealigned_in_smp;

struct fm10k_ring_container {
	struct fm10k_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u16 itr;			/* interrupt throttle rate value */
	u8 count;			/* total number of rings in vector */
};

#define FM10K_ITR_MAX		0x0FFF	/* maximum value for ITR */
#define FM10K_ITR_10K		100	/* 100us */
#define FM10K_ITR_20K		50	/* 50us */
#define FM10K_ITR_ADAPTIVE	0x8000	/* adaptive interrupt moderation flag */

#define FM10K_ITR_ENABLE	(FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)

static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
{
	return &ring->netdev->_tx[ring->queue_index];
}

/* iterator for handling rings in ring container */
#define fm10k_for_each_ring(pos, head) \
	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)

#define MAX_Q_VECTORS 256
#define MIN_Q_VECTORS	1
enum fm10k_non_q_vectors {
	FM10K_MBX_VECTOR,
#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
	NON_Q_VECTORS_PF
};

#define NON_Q_VECTORS(hw)	(((hw)->mac.type == fm10k_mac_pf) ? \
						NON_Q_VECTORS_PF : \
						NON_Q_VECTORS_VF)
#define MIN_MSIX_COUNT(hw)	(MIN_Q_VECTORS + NON_Q_VECTORS(hw))

struct fm10k_q_vector {
	struct fm10k_intfc *interface;
	u32 __iomem *itr;	/* pointer to ITR register for this vector */
	u16 v_idx;		/* index of q_vector within interface array */
	struct fm10k_ring_container rx, tx;

	struct napi_struct napi;
	char name[IFNAMSIZ + 9];

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_q_vector;
#endif /* CONFIG_DEBUG_FS */
	struct rcu_head rcu;	/* to avoid race with update stats on free */

	/* for dynamic allocation of rings associated with this q_vector */
	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
};

enum fm10k_ring_f_enum {
	RING_F_RSS,
	RING_F_QOS,
	RING_F_ARRAY_SIZE  /* must be last in enum set */
};

struct fm10k_ring_feature {
	u16 limit;	/* upper limit on feature indices */
	u16 indices;	/* current value of indices */
	u16 mask;	/* Mask used for feature to ring mapping */
	u16 offset;	/* offset to start of feature */
};

struct fm10k_iov_data {
	unsigned int		num_vfs;
	unsigned int		next_vf_mbx;
	struct rcu_head		rcu;
	struct fm10k_vf_info	vf_info[0];
};

#define fm10k_vxlan_port_for_each(vp, intfc) \
	list_for_each_entry(vp, &(intfc)->vxlan_port, list)
struct fm10k_vxlan_port {
	struct list_head	list;
	sa_family_t		sa_family;
	__be16			port;
};

/* one work queue for entire driver */
extern struct workqueue_struct *fm10k_workqueue;

struct fm10k_intfc {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct net_device *netdev;
	struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */
	struct pci_dev *pdev;
	unsigned long state;

	u32 flags;
#define FM10K_FLAG_RESET_REQUESTED		(u32)(1 << 0)
#define FM10K_FLAG_RSS_FIELD_IPV4_UDP		(u32)(1 << 1)
#define FM10K_FLAG_RSS_FIELD_IPV6_UDP		(u32)(1 << 2)
#define FM10K_FLAG_RX_TS_ENABLED		(u32)(1 << 3)
#define FM10K_FLAG_SWPRI_CONFIG			(u32)(1 << 4)
#define FM10K_FLAG_DEBUG_STATS			(u32)(1 << 5)
	int xcast_mode;

	/* Tx fast path data */
	int num_tx_queues;
	u16 tx_itr;

	/* Rx fast path data */
	int num_rx_queues;
	u16 rx_itr;

	/* TX */
	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;

	u64 restart_queue;
	u64 tx_busy;
	u64 tx_csum_errors;
	u64 alloc_failed;
	u64 rx_csum_errors;

	u64 tx_bytes_nic;
	u64 tx_packets_nic;
	u64 rx_bytes_nic;
	u64 rx_packets_nic;
	u64 rx_drops_nic;
	u64 rx_overrun_pf;
	u64 rx_overrun_vf;

	/* Debug Statistics */
	u64 hw_sm_mbx_full;
	u64 hw_csum_tx_good;
	u64 hw_csum_rx_good;
	u64 rx_switch_errors;
	u64 rx_drops;
	u64 rx_pp_errors;
	u64 rx_link_errors;
	u64 rx_length_errors;

	u32 tx_timeout_count;

	/* RX */
	struct fm10k_ring *rx_ring[MAX_QUEUES];

	/* Queueing vectors */
	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	int num_q_vectors;	/* current number of q_vectors for device */
	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];

	/* SR-IOV information management structure */
	struct fm10k_iov_data *iov_data;

	struct fm10k_hw_stats stats;
	struct fm10k_hw hw;
	u32 __iomem *uc_addr;
	u32 __iomem *sw_addr;
	u16 msg_enable;
	u16 tx_ring_count;
	u16 rx_ring_count;
	struct timer_list service_timer;
	struct work_struct service_task;
	unsigned long next_stats_update;
	unsigned long next_tx_hang_check;
	unsigned long last_reset;
	unsigned long link_down_event;
	bool host_ready;

	u32 reta[FM10K_RETA_SIZE];
	u32 rssrk[FM10K_RSSRK_SIZE];

	/* VXLAN port tracking information */
	struct list_head vxlan_port;

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_intfc;

#endif /* CONFIG_DEBUG_FS */
	struct ptp_clock_info ptp_caps;
	struct ptp_clock *ptp_clock;

	struct sk_buff_head ts_tx_skb_queue;
	u32 tx_hwtstamp_timeouts;

	struct hwtstamp_config ts_config;
	/* We are unable to actually adjust the clock beyond the frequency
	 * value.  Once the clock is started there is no resetting it.  As
	 * such we maintain a separate offset from the actual hardware clock
	 * to allow for offset adjustment.
	 */
	s64 ptp_adjust;
	rwlock_t systime_lock;
#ifdef CONFIG_DCB
	u8 pfc_en;
#endif
	u8 rx_pause;

	/* GLORT resources in use by PF */
	u16 glort;
	u16 glort_count;

	/* VLAN ID for updating multicast/unicast lists */
	u16 vid;
};

enum fm10k_state_t {
	__FM10K_RESETTING,
	__FM10K_DOWN,
	__FM10K_SERVICE_SCHED,
	__FM10K_SERVICE_DISABLE,
	__FM10K_MBX_LOCK,
	__FM10K_LINK_DOWN,
};

static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
{
	/* busy loop if we cannot obtain the lock as some calls
	 * such as ndo_set_rx_mode may be made in atomic context
	 */
	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
		udelay(20);
}

static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
{
	/* flush memory to make sure state is correct */
	smp_mb__before_atomic();
	clear_bit(__FM10K_MBX_LOCK, &interface->state);
}

static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
{
	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
}

/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
					const u32 stat_err_bits)
{
	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
}

/* fm10k_desc_unused - calculate if we have unused descriptors */
static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
{
	s16 unused = ring->next_to_clean - ring->next_to_use - 1;

	return likely(unused < 0) ? unused + ring->count : unused;
}

#define FM10K_TX_DESC(R, i)	\
	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
#define FM10K_RX_DESC(R, i)	\
	 (&(((union fm10k_rx_desc *)((R)->desc))[i]))

#define FM10K_MAX_TXD_PWR	14
#define FM10K_MAX_DATA_PER_TXD	(1 << FM10K_MAX_TXD_PWR)

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
#define DESC_NEEDED	(MAX_SKB_FRAGS + 4)

enum fm10k_tx_flags {
	/* Tx offload flags */
	FM10K_TX_FLAGS_CSUM	= 0x01,
};

/* This structure is stored as little endian values as that is the native
 * format of the Rx descriptor.  The ordering of these fields is reversed
 * from the actual ftag header to allow for a single bswap to take care
 * of placing all of the values in network order
 */
union fm10k_ftag_info {
	__le64 ftag;
	struct {
		/* dglort and sglort combined into a single 32bit desc read */
		__le32 glort;
		/* upper 16 bits of vlan are reserved 0 for swpri_type_user */
		__le32 vlan;
	} d;
	struct {
		__le16 dglort;
		__le16 sglort;
		__le16 vlan;
		__le16 swpri_type_user;
	} w;
};

struct fm10k_cb {
	union {
		__le64 tstamp;
		unsigned long ts_tx_timeout;
	};
	union fm10k_ftag_info fi;
};

#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)

/* main */
extern char fm10k_driver_name[];
extern const char fm10k_driver_version[];
int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
				  struct fm10k_ring *tx_ring);
void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);

/* PCI */
void fm10k_mbx_free_irq(struct fm10k_intfc *);
int fm10k_mbx_request_irq(struct fm10k_intfc *);
void fm10k_qv_free_irq(struct fm10k_intfc *interface);
int fm10k_qv_request_irq(struct fm10k_intfc *interface);
int fm10k_register_pci_driver(void);
void fm10k_unregister_pci_driver(void);
void fm10k_up(struct fm10k_intfc *interface);
void fm10k_down(struct fm10k_intfc *interface);
void fm10k_update_stats(struct fm10k_intfc *interface);
void fm10k_service_event_schedule(struct fm10k_intfc *interface);
void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
#ifdef CONFIG_NET_POLL_CONTROLLER
void fm10k_netpoll(struct net_device *netdev);
#endif

/* Netdev */
struct net_device *fm10k_alloc_netdev(void);
int fm10k_setup_rx_resources(struct fm10k_ring *);
int fm10k_setup_tx_resources(struct fm10k_ring *);
void fm10k_free_rx_resources(struct fm10k_ring *);
void fm10k_free_tx_resources(struct fm10k_ring *);
void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
				      struct fm10k_tx_buffer *);
void fm10k_restore_rx_state(struct fm10k_intfc *);
void fm10k_reset_rx_state(struct fm10k_intfc *);
int fm10k_setup_tc(struct net_device *dev, u8 tc);
int fm10k_open(struct net_device *netdev);
int fm10k_close(struct net_device *netdev);

/* Ethtool */
void fm10k_set_ethtool_ops(struct net_device *dev);

/* IOV */
s32 fm10k_iov_event(struct fm10k_intfc *interface);
s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
void fm10k_iov_suspend(struct pci_dev *pdev);
int fm10k_iov_resume(struct pci_dev *pdev);
void fm10k_iov_disable(struct pci_dev *pdev);
int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
int fm10k_ndo_set_vf_mac(struct net_device *netdev, int vf_idx, u8 *mac);
int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
			  int vf_idx, u16 vid, u8 qos);
int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
			int unused);
int fm10k_ndo_get_vf_config(struct net_device *netdev,
			    int vf_idx, struct ifla_vf_info *ivi);

/* DebugFS */
#ifdef CONFIG_DEBUG_FS
void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
void fm10k_dbg_init(void);
void fm10k_dbg_exit(void);
#else
static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_init(void) {}
static inline void fm10k_dbg_exit(void) {}
#endif /* CONFIG_DEBUG_FS */

/* Time Stamping */
void fm10k_systime_to_hwtstamp(struct fm10k_intfc *interface,
			       struct skb_shared_hwtstamps *hwtstamp,
			       u64 systime);
void fm10k_ts_tx_enqueue(struct fm10k_intfc *interface, struct sk_buff *skb);
void fm10k_ts_tx_hwtstamp(struct fm10k_intfc *interface, __le16 dglort,
			  u64 systime);
void fm10k_ts_reset(struct fm10k_intfc *interface);
void fm10k_ts_init(struct fm10k_intfc *interface);
void fm10k_ts_tx_subtask(struct fm10k_intfc *interface);
void fm10k_ptp_register(struct fm10k_intfc *interface);
void fm10k_ptp_unregister(struct fm10k_intfc *interface);
int fm10k_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
int fm10k_set_ts_config(struct net_device *netdev, struct ifreq *ifr);

/* DCB */
void fm10k_dcbnl_set_ops(struct net_device *dev);
#endif /* _FM10K_H_ */
Commit	Line	Data
b3890e30	1	/* Intel Ethernet Switch Host Interface Driver
97c71e3c	2	* Copyright(c) 2013 - 2015 Intel Corporation.
b3890e30 AD	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	* Contact Information:
	17	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	18	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	19	*/
	20
	21	#ifndef _FM10K_H_
	22	#define _FM10K_H_
	23
	24	#include <linux/types.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/rtnetlink.h>
	27	#include <linux/if_vlan.h>
	28	#include <linux/pci.h>
a211e013 AD	29	#include <linux/net_tstamp.h>
	30	#include <linux/clocksource.h>
	31	#include <linux/ptp_clock_kernel.h>
b3890e30	32
0e7b3644	33	#include "fm10k_pf.h"
5cb8db4a	34	#include "fm10k_vf.h"
0e7b3644 AD	35
	36	#define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */
	37
e27ef599 AD	38	#define MAX_QUEUES FM10K_MAX_QUEUES_PF
	39
	40	#define FM10K_MIN_RXD 128
	41	#define FM10K_MAX_RXD 4096
	42	#define FM10K_DEFAULT_RXD 256
	43
	44	#define FM10K_MIN_TXD 128
	45	#define FM10K_MAX_TXD 4096
	46	#define FM10K_DEFAULT_TXD 256
	47	#define FM10K_DEFAULT_TX_WORK 256
	48
	49	#define FM10K_RXBUFFER_256 256
e27ef599	50	#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
fd333962 AD	51	#define FM10K_RXBUFFER_2048 2048
fd333962 AD	52	#define FM10K_RX_BUFSZ FM10K_RXBUFFER_2048
e27ef599 AD	53
	54	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	55	#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	56
5cd5e2e9 AD	57	#define FM10K_MAX_STATIONS 63
	58	struct fm10k_l2_accel {
	59	int size;
	60	u16 count;
	61	u16 dglort;
	62	struct rcu_head rcu;
	63	struct net_device *macvlan[0];
	64	};
	65
e27ef599 AD	66	enum fm10k_ring_state_t {
	67	__FM10K_TX_DETECT_HANG,
	68	__FM10K_HANG_CHECK_ARMED,
	69	};
	70
	71	#define check_for_tx_hang(ring) \
	72	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	73	#define set_check_for_tx_hang(ring) \
	74	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	75	#define clear_check_for_tx_hang(ring) \
	76	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	77
	78	struct fm10k_tx_buffer {
	79	struct fm10k_tx_desc *next_to_watch;
	80	struct sk_buff *skb;
	81	unsigned int bytecount;
	82	u16 gso_segs;
	83	u16 tx_flags;
	84	DEFINE_DMA_UNMAP_ADDR(dma);
	85	DEFINE_DMA_UNMAP_LEN(len);
	86	};
	87
	88	struct fm10k_rx_buffer {
	89	dma_addr_t dma;
	90	struct page *page;
	91	u32 page_offset;
	92	};
	93
	94	struct fm10k_queue_stats {
	95	u64 packets;
	96	u64 bytes;
	97	};
	98
	99	struct fm10k_tx_queue_stats {
	100	u64 restart_queue;
	101	u64 csum_err;
	102	u64 tx_busy;
	103	u64 tx_done_old;
80043f3b	104	u64 csum_good;
e27ef599 AD	105	};
	106
	107	struct fm10k_rx_queue_stats {
	108	u64 alloc_failed;
	109	u64 csum_err;
	110	u64 errors;
80043f3b JK	111	u64 csum_good;
	112	u64 switch_errors;
	113	u64 drops;
	114	u64 pp_errors;
	115	u64 link_errors;
	116	u64 length_errors;
e27ef599 AD	117	};
	118
	119	struct fm10k_ring {
	120	struct fm10k_q_vector q_vector;/ backpointer to host q_vector */
	121	struct net_device netdev; / netdev ring belongs to */
	122	struct device dev; / device for DMA mapping */
5cd5e2e9	123	struct fm10k_l2_accel __rcu l2_accel; / L2 acceleration list */
e27ef599 AD	124	void desc; / descriptor ring memory */
	125	union {
	126	struct fm10k_tx_buffer *tx_buffer;
	127	struct fm10k_rx_buffer *rx_buffer;
	128	};
	129	u32 __iomem *tail;
	130	unsigned long state;
	131	dma_addr_t dma; /* phys. address of descriptor ring */
	132	unsigned int size; /* length in bytes */
	133
	134	u8 queue_index; /* needed for queue management */
	135	u8 reg_idx; /* holds the special value that gets
	136	* the hardware register offset
	137	* associated with this ring, which is
	138	* different for DCB and RSS modes
	139	*/
	140	u8 qos_pc; /* priority class of queue */
	141	u16 vid; /* default vlan ID of queue */
	142	u16 count; /* amount of descriptors */
	143
	144	u16 next_to_alloc;
	145	u16 next_to_use;
	146	u16 next_to_clean;
	147
	148	struct fm10k_queue_stats stats;
	149	struct u64_stats_sync syncp;
	150	union {
	151	/* Tx */
	152	struct fm10k_tx_queue_stats tx_stats;
	153	/* Rx */
	154	struct {
	155	struct fm10k_rx_queue_stats rx_stats;
	156	struct sk_buff *skb;
	157	};
	158	};
	159	} ____cacheline_internodealigned_in_smp;
	160
18283cad	161	struct fm10k_ring_container {
e27ef599	162	struct fm10k_ring ring; / pointer to linked list of rings */
18283cad AD	163	unsigned int total_bytes; /* total bytes processed this int */
	164	unsigned int total_packets; /* total packets processed this int */
	165	u16 work_limit; /* total work allowed per interrupt */
	166	u16 itr; /* interrupt throttle rate value */
	167	u8 count; /* total number of rings in vector */
	168	};
	169
	170	#define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
	171	#define FM10K_ITR_10K 100 /* 100us */
	172	#define FM10K_ITR_20K 50 /* 50us */
	173	#define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
	174
	175	#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK \| FM10K_ITR_MASK_CLEAR)
	176
e27ef599 AD	177	static inline struct netdev_queue txring_txq(const struct fm10k_ring ring)
	178	{
	179	return &ring->netdev->_tx[ring->queue_index];
	180	}
	181
	182	/* iterator for handling rings in ring container */
	183	#define fm10k_for_each_ring(pos, head) \
	184	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
	185
18283cad AD	186	#define MAX_Q_VECTORS 256
	187	#define MIN_Q_VECTORS 1
	188	enum fm10k_non_q_vectors {
	189	FM10K_MBX_VECTOR,
5cb8db4a	190	#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
18283cad AD	191	NON_Q_VECTORS_PF
	192	};
	193
	194	#define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
	195	NON_Q_VECTORS_PF : \
5cb8db4a	196	NON_Q_VECTORS_VF)
18283cad AD	197	#define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
	198
	199	struct fm10k_q_vector {
	200	struct fm10k_intfc *interface;
	201	u32 __iomem itr; / pointer to ITR register for this vector */
	202	u16 v_idx; /* index of q_vector within interface array */
	203	struct fm10k_ring_container rx, tx;
	204
	205	struct napi_struct napi;
	206	char name[IFNAMSIZ + 9];
	207
7461fd91 AD	208	#ifdef CONFIG_DEBUG_FS
	209	struct dentry *dbg_q_vector;
	210	#endif /* CONFIG_DEBUG_FS */
18283cad	211	struct rcu_head rcu; /* to avoid race with update stats on free */
e27ef599 AD	212
	213	/* for dynamic allocation of rings associated with this q_vector */
	214	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
18283cad AD	215	};
18283cad AD	216
0e7b3644 AD	217	enum fm10k_ring_f_enum {
	218	RING_F_RSS,
	219	RING_F_QOS,
	220	RING_F_ARRAY_SIZE /* must be last in enum set */
	221	};
	222
	223	struct fm10k_ring_feature {
	224	u16 limit; /* upper limit on feature indices */
	225	u16 indices; /* current value of indices */
	226	u16 mask; /* Mask used for feature to ring mapping */
	227	u16 offset; /* offset to start of feature */
	228	};
	229
883a9ccb AD	230	struct fm10k_iov_data {
	231	unsigned int num_vfs;
	232	unsigned int next_vf_mbx;
	233	struct rcu_head rcu;
	234	struct fm10k_vf_info vf_info[0];
	235	};
	236
0e7b3644 AD	237	#define fm10k_vxlan_port_for_each(vp, intfc) \
	238	list_for_each_entry(vp, &(intfc)->vxlan_port, list)
	239	struct fm10k_vxlan_port {
	240	struct list_head list;
	241	sa_family_t sa_family;
	242	__be16 port;
	243	};
04a5aefb	244
b382bb1b JK	245	/* one work queue for entire driver */
	246	extern struct workqueue_struct *fm10k_workqueue;
	247
04a5aefb	248	struct fm10k_intfc {
0e7b3644 AD	249	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0e7b3644 AD	250	struct net_device *netdev;
5cd5e2e9	251	struct fm10k_l2_accel l2_accel; / pointer to L2 acceleration list */
04a5aefb	252	struct pci_dev *pdev;
0e7b3644 AD	253	unsigned long state;
	254
	255	u32 flags;
	256	#define FM10K_FLAG_RESET_REQUESTED (u32)(1 << 0)
	257	#define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(1 << 1)
	258	#define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(1 << 2)
	259	#define FM10K_FLAG_RX_TS_ENABLED (u32)(1 << 3)
	260	#define FM10K_FLAG_SWPRI_CONFIG (u32)(1 << 4)
80043f3b	261	#define FM10K_FLAG_DEBUG_STATS (u32)(1 << 5)
0e7b3644 AD	262	int xcast_mode;
0e7b3644 AD	263
18283cad AD	264	/* Tx fast path data */
	265	int num_tx_queues;
	266	u16 tx_itr;
	267
	268	/* Rx fast path data */
	269	int num_rx_queues;
	270	u16 rx_itr;
	271
e27ef599 AD	272	/* TX */
	273	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
	274
b7d8514c AD	275	u64 restart_queue;
	276	u64 tx_busy;
	277	u64 tx_csum_errors;
	278	u64 alloc_failed;
	279	u64 rx_csum_errors;
b7d8514c AD	280
	281	u64 tx_bytes_nic;
	282	u64 tx_packets_nic;
	283	u64 rx_bytes_nic;
	284	u64 rx_packets_nic;
	285	u64 rx_drops_nic;
0e7b3644 AD	286	u64 rx_overrun_pf;
0e7b3644 AD	287	u64 rx_overrun_vf;
80043f3b JK	288
	289	/* Debug Statistics */
	290	u64 hw_sm_mbx_full;
	291	u64 hw_csum_tx_good;
	292	u64 hw_csum_rx_good;
	293	u64 rx_switch_errors;
	294	u64 rx_drops;
	295	u64 rx_pp_errors;
	296	u64 rx_link_errors;
	297	u64 rx_length_errors;
	298
b7d8514c	299	u32 tx_timeout_count;
04a5aefb	300
e27ef599 AD	301	/* RX */
	302	struct fm10k_ring *rx_ring[MAX_QUEUES];
	303
18283cad AD	304	/* Queueing vectors */
	305	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	306	struct msix_entry *msix_entries;
	307	int num_q_vectors; /* current number of q_vectors for device */
0e7b3644 AD	308	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
0e7b3644 AD	309
883a9ccb AD	310	/* SR-IOV information management structure */
	311	struct fm10k_iov_data *iov_data;
	312
0e7b3644	313	struct fm10k_hw_stats stats;
04a5aefb AD	314	struct fm10k_hw hw;
04a5aefb AD	315	u32 __iomem *uc_addr;
a211e013	316	u32 __iomem *sw_addr;
0e7b3644	317	u16 msg_enable;
18283cad AD	318	u16 tx_ring_count;
18283cad AD	319	u16 rx_ring_count;
b7d8514c AD	320	struct timer_list service_timer;
	321	struct work_struct service_task;
	322	unsigned long next_stats_update;
	323	unsigned long next_tx_hang_check;
	324	unsigned long last_reset;
	325	unsigned long link_down_event;
	326	bool host_ready;
0e7b3644 AD	327
	328	u32 reta[FM10K_RETA_SIZE];
	329	u32 rssrk[FM10K_RSSRK_SIZE];
	330
	331	/* VXLAN port tracking information */
	332	struct list_head vxlan_port;
	333
7461fd91 AD	334	#ifdef CONFIG_DEBUG_FS
	335	struct dentry *dbg_intfc;
	336
	337	#endif /* CONFIG_DEBUG_FS */
a211e013 AD	338	struct ptp_clock_info ptp_caps;
	339	struct ptp_clock *ptp_clock;
	340
	341	struct sk_buff_head ts_tx_skb_queue;
	342	u32 tx_hwtstamp_timeouts;
	343
	344	struct hwtstamp_config ts_config;
	345	/* We are unable to actually adjust the clock beyond the frequency
	346	* value. Once the clock is started there is no resetting it. As
	347	* such we maintain a separate offset from the actual hardware clock
	348	* to allow for offset adjustment.
	349	*/
	350	s64 ptp_adjust;
	351	rwlock_t systime_lock;
9f801abc	352	#ifdef CONFIG_DCB
0e7b3644 AD	353	u8 pfc_en;
	354	#endif
	355	u8 rx_pause;
	356
	357	/* GLORT resources in use by PF */
	358	u16 glort;
	359	u16 glort_count;
	360
	361	/* VLAN ID for updating multicast/unicast lists */
	362	u16 vid;
	363	};
	364
	365	enum fm10k_state_t {
	366	__FM10K_RESETTING,
	367	__FM10K_DOWN,
b7d8514c AD	368	__FM10K_SERVICE_SCHED,
b7d8514c AD	369	__FM10K_SERVICE_DISABLE,
0e7b3644 AD	370	__FM10K_MBX_LOCK,
0e7b3644 AD	371	__FM10K_LINK_DOWN,
04a5aefb	372	};
b3890e30	373
0e7b3644 AD	374	static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
	375	{
	376	/* busy loop if we cannot obtain the lock as some calls
	377	* such as ndo_set_rx_mode may be made in atomic context
	378	*/
	379	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
	380	udelay(20);
	381	}
	382
	383	static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
	384	{
	385	/* flush memory to make sure state is correct */
	386	smp_mb__before_atomic();
	387	clear_bit(__FM10K_MBX_LOCK, &interface->state);
	388	}
	389
	390	static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
	391	{
	392	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
	393	}
	394
e27ef599 AD	395	/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
	396	static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
	397	const u32 stat_err_bits)
	398	{
	399	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
	400	}
	401
	402	/* fm10k_desc_unused - calculate if we have unused descriptors */
	403	static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
	404	{
	405	s16 unused = ring->next_to_clean - ring->next_to_use - 1;
	406
	407	return likely(unused < 0) ? unused + ring->count : unused;
	408	}
	409
	410	#define FM10K_TX_DESC(R, i) \
	411	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
	412	#define FM10K_RX_DESC(R, i) \
	413	(&(((union fm10k_rx_desc *)((R)->desc))[i]))
	414
	415	#define FM10K_MAX_TXD_PWR 14
	416	#define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR)
	417
	418	/* Tx Descriptors needed, worst case */
	419	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
	420	#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
	421
	422	enum fm10k_tx_flags {
	423	/* Tx offload flags */
	424	FM10K_TX_FLAGS_CSUM = 0x01,
	425	};
	426
	427	/* This structure is stored as little endian values as that is the native
	428	* format of the Rx descriptor. The ordering of these fields is reversed
	429	* from the actual ftag header to allow for a single bswap to take care
	430	* of placing all of the values in network order
	431	*/
	432	union fm10k_ftag_info {
	433	__le64 ftag;
	434	struct {
	435	/* dglort and sglort combined into a single 32bit desc read */
	436	__le32 glort;
	437	/* upper 16 bits of vlan are reserved 0 for swpri_type_user */
	438	__le32 vlan;
	439	} d;
	440	struct {
	441	__le16 dglort;
	442	__le16 sglort;
	443	__le16 vlan;
	444	__le16 swpri_type_user;
	445	} w;
	446	};
	447
	448	struct fm10k_cb {
a211e013 AD	449	union {
	450	__le64 tstamp;
	451	unsigned long ts_tx_timeout;
	452	};
e27ef599 AD	453	union fm10k_ftag_info fi;
	454	};
	455
	456	#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
	457
b3890e30 AD	458	/* main */
	459	extern char fm10k_driver_name[];
	460	extern const char fm10k_driver_version[];
18283cad AD	461	int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
18283cad AD	462	void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
5bf33dc6	463	__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
b101c962 AD	464	netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
	465	struct fm10k_ring *tx_ring);
	466	void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
	467	bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
	468	void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);
b3890e30 AD	469
b3890e30 AD	470	/* PCI */
18283cad AD	471	void fm10k_mbx_free_irq(struct fm10k_intfc *);
	472	int fm10k_mbx_request_irq(struct fm10k_intfc *);
	473	void fm10k_qv_free_irq(struct fm10k_intfc *interface);
	474	int fm10k_qv_request_irq(struct fm10k_intfc *interface);
b3890e30 AD	475	int fm10k_register_pci_driver(void);
b3890e30 AD	476	void fm10k_unregister_pci_driver(void);
504c5eac AD	477	void fm10k_up(struct fm10k_intfc *interface);
504c5eac AD	478	void fm10k_down(struct fm10k_intfc *interface);
b7d8514c AD	479	void fm10k_update_stats(struct fm10k_intfc *interface);
	480	void fm10k_service_event_schedule(struct fm10k_intfc *interface);
	481	void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
8b4a98c7 JK	482	#ifdef CONFIG_NET_POLL_CONTROLLER
	483	void fm10k_netpoll(struct net_device *netdev);
	484	#endif
0e7b3644 AD	485
	486	/* Netdev */
	487	struct net_device *fm10k_alloc_netdev(void);
3abaae42 AD	488	int fm10k_setup_rx_resources(struct fm10k_ring *);
	489	int fm10k_setup_tx_resources(struct fm10k_ring *);
	490	void fm10k_free_rx_resources(struct fm10k_ring *);
	491	void fm10k_free_tx_resources(struct fm10k_ring *);
	492	void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
	493	void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
	494	void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
	495	struct fm10k_tx_buffer *);
8f5e20d4 AD	496	void fm10k_restore_rx_state(struct fm10k_intfc *);
8f5e20d4 AD	497	void fm10k_reset_rx_state(struct fm10k_intfc *);
aa3ac822	498	int fm10k_setup_tc(struct net_device *dev, u8 tc);
504c5eac AD	499	int fm10k_open(struct net_device *netdev);
504c5eac AD	500	int fm10k_close(struct net_device *netdev);
82dd0f7e AD	501
	502	/* Ethtool */
	503	void fm10k_set_ethtool_ops(struct net_device *dev);
883a9ccb AD	504
	505	/* IOV */
	506	s32 fm10k_iov_event(struct fm10k_intfc *interface);
	507	s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
	508	void fm10k_iov_suspend(struct pci_dev *pdev);
	509	int fm10k_iov_resume(struct pci_dev *pdev);
	510	void fm10k_iov_disable(struct pci_dev *pdev);
	511	int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
	512	s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
	513	int fm10k_ndo_set_vf_mac(struct net_device netdev, int vf_idx, u8 mac);
	514	int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
	515	int vf_idx, u16 vid, u8 qos);
	516	int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
	517	int unused);
	518	int fm10k_ndo_get_vf_config(struct net_device *netdev,
	519	int vf_idx, struct ifla_vf_info *ivi);
9f801abc	520
7461fd91 AD	521	/* DebugFS */
	522	#ifdef CONFIG_DEBUG_FS
	523	void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
	524	void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
	525	void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
	526	void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
	527	void fm10k_dbg_init(void);
	528	void fm10k_dbg_exit(void);
	529	#else
	530	static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
	531	static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
	532	static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
	533	static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
	534	static inline void fm10k_dbg_init(void) {}
	535	static inline void fm10k_dbg_exit(void) {}
	536	#endif /* CONFIG_DEBUG_FS */
	537
a211e013 AD	538	/* Time Stamping */
	539	void fm10k_systime_to_hwtstamp(struct fm10k_intfc *interface,
	540	struct skb_shared_hwtstamps *hwtstamp,
	541	u64 systime);
	542	void fm10k_ts_tx_enqueue(struct fm10k_intfc interface, struct sk_buff skb);
	543	void fm10k_ts_tx_hwtstamp(struct fm10k_intfc *interface, __le16 dglort,
	544	u64 systime);
	545	void fm10k_ts_reset(struct fm10k_intfc *interface);
	546	void fm10k_ts_init(struct fm10k_intfc *interface);
	547	void fm10k_ts_tx_subtask(struct fm10k_intfc *interface);
	548	void fm10k_ptp_register(struct fm10k_intfc *interface);
	549	void fm10k_ptp_unregister(struct fm10k_intfc *interface);
	550	int fm10k_get_ts_config(struct net_device netdev, struct ifreq ifr);
	551	int fm10k_set_ts_config(struct net_device netdev, struct ifreq ifr);
	552
9f801abc AD	553	/* DCB */
9f801abc AD	554	void fm10k_dcbnl_set_ops(struct net_device *dev);
b3890e30	555	#endif /* _FM10K_H_ */