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b3890e30 | 1 | /* Intel Ethernet Switch Host Interface Driver |
97c71e3c | 2 | * Copyright(c) 2013 - 2015 Intel Corporation. |
b3890e30 AD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
19 | */ | |
20 | ||
21 | #ifndef _FM10K_H_ | |
22 | #define _FM10K_H_ | |
23 | ||
24 | #include <linux/types.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/rtnetlink.h> | |
27 | #include <linux/if_vlan.h> | |
28 | #include <linux/pci.h> | |
a211e013 AD |
29 | #include <linux/net_tstamp.h> |
30 | #include <linux/clocksource.h> | |
31 | #include <linux/ptp_clock_kernel.h> | |
b3890e30 | 32 | |
0e7b3644 | 33 | #include "fm10k_pf.h" |
5cb8db4a | 34 | #include "fm10k_vf.h" |
0e7b3644 AD |
35 | |
36 | #define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */ | |
37 | ||
e27ef599 AD |
38 | #define MAX_QUEUES FM10K_MAX_QUEUES_PF |
39 | ||
40 | #define FM10K_MIN_RXD 128 | |
41 | #define FM10K_MAX_RXD 4096 | |
42 | #define FM10K_DEFAULT_RXD 256 | |
43 | ||
44 | #define FM10K_MIN_TXD 128 | |
45 | #define FM10K_MAX_TXD 4096 | |
46 | #define FM10K_DEFAULT_TXD 256 | |
47 | #define FM10K_DEFAULT_TX_WORK 256 | |
48 | ||
49 | #define FM10K_RXBUFFER_256 256 | |
e27ef599 | 50 | #define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256 |
fd333962 AD |
51 | #define FM10K_RXBUFFER_2048 2048 |
52 | #define FM10K_RX_BUFSZ FM10K_RXBUFFER_2048 | |
e27ef599 AD |
53 | |
54 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
55 | #define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
56 | ||
5cd5e2e9 AD |
57 | #define FM10K_MAX_STATIONS 63 |
58 | struct fm10k_l2_accel { | |
59 | int size; | |
60 | u16 count; | |
61 | u16 dglort; | |
62 | struct rcu_head rcu; | |
63 | struct net_device *macvlan[0]; | |
64 | }; | |
65 | ||
e27ef599 AD |
66 | enum fm10k_ring_state_t { |
67 | __FM10K_TX_DETECT_HANG, | |
68 | __FM10K_HANG_CHECK_ARMED, | |
69 | }; | |
70 | ||
71 | #define check_for_tx_hang(ring) \ | |
72 | test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state) | |
73 | #define set_check_for_tx_hang(ring) \ | |
74 | set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state) | |
75 | #define clear_check_for_tx_hang(ring) \ | |
76 | clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state) | |
77 | ||
78 | struct fm10k_tx_buffer { | |
79 | struct fm10k_tx_desc *next_to_watch; | |
80 | struct sk_buff *skb; | |
81 | unsigned int bytecount; | |
82 | u16 gso_segs; | |
83 | u16 tx_flags; | |
84 | DEFINE_DMA_UNMAP_ADDR(dma); | |
85 | DEFINE_DMA_UNMAP_LEN(len); | |
86 | }; | |
87 | ||
88 | struct fm10k_rx_buffer { | |
89 | dma_addr_t dma; | |
90 | struct page *page; | |
91 | u32 page_offset; | |
92 | }; | |
93 | ||
94 | struct fm10k_queue_stats { | |
95 | u64 packets; | |
96 | u64 bytes; | |
97 | }; | |
98 | ||
99 | struct fm10k_tx_queue_stats { | |
100 | u64 restart_queue; | |
101 | u64 csum_err; | |
102 | u64 tx_busy; | |
103 | u64 tx_done_old; | |
104 | }; | |
105 | ||
106 | struct fm10k_rx_queue_stats { | |
107 | u64 alloc_failed; | |
108 | u64 csum_err; | |
109 | u64 errors; | |
110 | }; | |
111 | ||
112 | struct fm10k_ring { | |
113 | struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */ | |
114 | struct net_device *netdev; /* netdev ring belongs to */ | |
115 | struct device *dev; /* device for DMA mapping */ | |
5cd5e2e9 | 116 | struct fm10k_l2_accel __rcu *l2_accel; /* L2 acceleration list */ |
e27ef599 AD |
117 | void *desc; /* descriptor ring memory */ |
118 | union { | |
119 | struct fm10k_tx_buffer *tx_buffer; | |
120 | struct fm10k_rx_buffer *rx_buffer; | |
121 | }; | |
122 | u32 __iomem *tail; | |
123 | unsigned long state; | |
124 | dma_addr_t dma; /* phys. address of descriptor ring */ | |
125 | unsigned int size; /* length in bytes */ | |
126 | ||
127 | u8 queue_index; /* needed for queue management */ | |
128 | u8 reg_idx; /* holds the special value that gets | |
129 | * the hardware register offset | |
130 | * associated with this ring, which is | |
131 | * different for DCB and RSS modes | |
132 | */ | |
133 | u8 qos_pc; /* priority class of queue */ | |
134 | u16 vid; /* default vlan ID of queue */ | |
135 | u16 count; /* amount of descriptors */ | |
136 | ||
137 | u16 next_to_alloc; | |
138 | u16 next_to_use; | |
139 | u16 next_to_clean; | |
140 | ||
141 | struct fm10k_queue_stats stats; | |
142 | struct u64_stats_sync syncp; | |
143 | union { | |
144 | /* Tx */ | |
145 | struct fm10k_tx_queue_stats tx_stats; | |
146 | /* Rx */ | |
147 | struct { | |
148 | struct fm10k_rx_queue_stats rx_stats; | |
149 | struct sk_buff *skb; | |
150 | }; | |
151 | }; | |
152 | } ____cacheline_internodealigned_in_smp; | |
153 | ||
18283cad | 154 | struct fm10k_ring_container { |
e27ef599 | 155 | struct fm10k_ring *ring; /* pointer to linked list of rings */ |
18283cad AD |
156 | unsigned int total_bytes; /* total bytes processed this int */ |
157 | unsigned int total_packets; /* total packets processed this int */ | |
158 | u16 work_limit; /* total work allowed per interrupt */ | |
159 | u16 itr; /* interrupt throttle rate value */ | |
160 | u8 count; /* total number of rings in vector */ | |
161 | }; | |
162 | ||
163 | #define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */ | |
164 | #define FM10K_ITR_10K 100 /* 100us */ | |
165 | #define FM10K_ITR_20K 50 /* 50us */ | |
166 | #define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */ | |
167 | ||
168 | #define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR) | |
169 | ||
e27ef599 AD |
170 | static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring) |
171 | { | |
172 | return &ring->netdev->_tx[ring->queue_index]; | |
173 | } | |
174 | ||
175 | /* iterator for handling rings in ring container */ | |
176 | #define fm10k_for_each_ring(pos, head) \ | |
177 | for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;) | |
178 | ||
18283cad AD |
179 | #define MAX_Q_VECTORS 256 |
180 | #define MIN_Q_VECTORS 1 | |
181 | enum fm10k_non_q_vectors { | |
182 | FM10K_MBX_VECTOR, | |
5cb8db4a | 183 | #define NON_Q_VECTORS_VF NON_Q_VECTORS_PF |
18283cad AD |
184 | NON_Q_VECTORS_PF |
185 | }; | |
186 | ||
187 | #define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \ | |
188 | NON_Q_VECTORS_PF : \ | |
5cb8db4a | 189 | NON_Q_VECTORS_VF) |
18283cad AD |
190 | #define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw)) |
191 | ||
192 | struct fm10k_q_vector { | |
193 | struct fm10k_intfc *interface; | |
194 | u32 __iomem *itr; /* pointer to ITR register for this vector */ | |
195 | u16 v_idx; /* index of q_vector within interface array */ | |
196 | struct fm10k_ring_container rx, tx; | |
197 | ||
198 | struct napi_struct napi; | |
199 | char name[IFNAMSIZ + 9]; | |
200 | ||
7461fd91 AD |
201 | #ifdef CONFIG_DEBUG_FS |
202 | struct dentry *dbg_q_vector; | |
203 | #endif /* CONFIG_DEBUG_FS */ | |
18283cad | 204 | struct rcu_head rcu; /* to avoid race with update stats on free */ |
e27ef599 AD |
205 | |
206 | /* for dynamic allocation of rings associated with this q_vector */ | |
207 | struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp; | |
18283cad AD |
208 | }; |
209 | ||
0e7b3644 AD |
210 | enum fm10k_ring_f_enum { |
211 | RING_F_RSS, | |
212 | RING_F_QOS, | |
213 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
214 | }; | |
215 | ||
216 | struct fm10k_ring_feature { | |
217 | u16 limit; /* upper limit on feature indices */ | |
218 | u16 indices; /* current value of indices */ | |
219 | u16 mask; /* Mask used for feature to ring mapping */ | |
220 | u16 offset; /* offset to start of feature */ | |
221 | }; | |
222 | ||
883a9ccb AD |
223 | struct fm10k_iov_data { |
224 | unsigned int num_vfs; | |
225 | unsigned int next_vf_mbx; | |
226 | struct rcu_head rcu; | |
227 | struct fm10k_vf_info vf_info[0]; | |
228 | }; | |
229 | ||
0e7b3644 AD |
230 | #define fm10k_vxlan_port_for_each(vp, intfc) \ |
231 | list_for_each_entry(vp, &(intfc)->vxlan_port, list) | |
232 | struct fm10k_vxlan_port { | |
233 | struct list_head list; | |
234 | sa_family_t sa_family; | |
235 | __be16 port; | |
236 | }; | |
04a5aefb AD |
237 | |
238 | struct fm10k_intfc { | |
0e7b3644 AD |
239 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
240 | struct net_device *netdev; | |
5cd5e2e9 | 241 | struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */ |
04a5aefb | 242 | struct pci_dev *pdev; |
0e7b3644 AD |
243 | unsigned long state; |
244 | ||
245 | u32 flags; | |
246 | #define FM10K_FLAG_RESET_REQUESTED (u32)(1 << 0) | |
247 | #define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(1 << 1) | |
248 | #define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(1 << 2) | |
249 | #define FM10K_FLAG_RX_TS_ENABLED (u32)(1 << 3) | |
250 | #define FM10K_FLAG_SWPRI_CONFIG (u32)(1 << 4) | |
251 | int xcast_mode; | |
252 | ||
18283cad AD |
253 | /* Tx fast path data */ |
254 | int num_tx_queues; | |
255 | u16 tx_itr; | |
256 | ||
257 | /* Rx fast path data */ | |
258 | int num_rx_queues; | |
259 | u16 rx_itr; | |
260 | ||
e27ef599 AD |
261 | /* TX */ |
262 | struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp; | |
263 | ||
b7d8514c AD |
264 | u64 restart_queue; |
265 | u64 tx_busy; | |
266 | u64 tx_csum_errors; | |
267 | u64 alloc_failed; | |
268 | u64 rx_csum_errors; | |
b7d8514c AD |
269 | |
270 | u64 tx_bytes_nic; | |
271 | u64 tx_packets_nic; | |
272 | u64 rx_bytes_nic; | |
273 | u64 rx_packets_nic; | |
274 | u64 rx_drops_nic; | |
0e7b3644 AD |
275 | u64 rx_overrun_pf; |
276 | u64 rx_overrun_vf; | |
b7d8514c | 277 | u32 tx_timeout_count; |
04a5aefb | 278 | |
e27ef599 AD |
279 | /* RX */ |
280 | struct fm10k_ring *rx_ring[MAX_QUEUES]; | |
281 | ||
18283cad AD |
282 | /* Queueing vectors */ |
283 | struct fm10k_q_vector *q_vector[MAX_Q_VECTORS]; | |
284 | struct msix_entry *msix_entries; | |
285 | int num_q_vectors; /* current number of q_vectors for device */ | |
0e7b3644 AD |
286 | struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE]; |
287 | ||
883a9ccb AD |
288 | /* SR-IOV information management structure */ |
289 | struct fm10k_iov_data *iov_data; | |
290 | ||
0e7b3644 | 291 | struct fm10k_hw_stats stats; |
04a5aefb AD |
292 | struct fm10k_hw hw; |
293 | u32 __iomem *uc_addr; | |
a211e013 | 294 | u32 __iomem *sw_addr; |
0e7b3644 | 295 | u16 msg_enable; |
18283cad AD |
296 | u16 tx_ring_count; |
297 | u16 rx_ring_count; | |
b7d8514c AD |
298 | struct timer_list service_timer; |
299 | struct work_struct service_task; | |
300 | unsigned long next_stats_update; | |
301 | unsigned long next_tx_hang_check; | |
302 | unsigned long last_reset; | |
303 | unsigned long link_down_event; | |
304 | bool host_ready; | |
0e7b3644 AD |
305 | |
306 | u32 reta[FM10K_RETA_SIZE]; | |
307 | u32 rssrk[FM10K_RSSRK_SIZE]; | |
308 | ||
309 | /* VXLAN port tracking information */ | |
310 | struct list_head vxlan_port; | |
311 | ||
7461fd91 AD |
312 | #ifdef CONFIG_DEBUG_FS |
313 | struct dentry *dbg_intfc; | |
314 | ||
315 | #endif /* CONFIG_DEBUG_FS */ | |
a211e013 AD |
316 | struct ptp_clock_info ptp_caps; |
317 | struct ptp_clock *ptp_clock; | |
318 | ||
319 | struct sk_buff_head ts_tx_skb_queue; | |
320 | u32 tx_hwtstamp_timeouts; | |
321 | ||
322 | struct hwtstamp_config ts_config; | |
323 | /* We are unable to actually adjust the clock beyond the frequency | |
324 | * value. Once the clock is started there is no resetting it. As | |
325 | * such we maintain a separate offset from the actual hardware clock | |
326 | * to allow for offset adjustment. | |
327 | */ | |
328 | s64 ptp_adjust; | |
329 | rwlock_t systime_lock; | |
9f801abc | 330 | #ifdef CONFIG_DCB |
0e7b3644 AD |
331 | u8 pfc_en; |
332 | #endif | |
333 | u8 rx_pause; | |
334 | ||
335 | /* GLORT resources in use by PF */ | |
336 | u16 glort; | |
337 | u16 glort_count; | |
338 | ||
339 | /* VLAN ID for updating multicast/unicast lists */ | |
340 | u16 vid; | |
341 | }; | |
342 | ||
343 | enum fm10k_state_t { | |
344 | __FM10K_RESETTING, | |
345 | __FM10K_DOWN, | |
b7d8514c AD |
346 | __FM10K_SERVICE_SCHED, |
347 | __FM10K_SERVICE_DISABLE, | |
0e7b3644 AD |
348 | __FM10K_MBX_LOCK, |
349 | __FM10K_LINK_DOWN, | |
04a5aefb | 350 | }; |
b3890e30 | 351 | |
0e7b3644 AD |
352 | static inline void fm10k_mbx_lock(struct fm10k_intfc *interface) |
353 | { | |
354 | /* busy loop if we cannot obtain the lock as some calls | |
355 | * such as ndo_set_rx_mode may be made in atomic context | |
356 | */ | |
357 | while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state)) | |
358 | udelay(20); | |
359 | } | |
360 | ||
361 | static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface) | |
362 | { | |
363 | /* flush memory to make sure state is correct */ | |
364 | smp_mb__before_atomic(); | |
365 | clear_bit(__FM10K_MBX_LOCK, &interface->state); | |
366 | } | |
367 | ||
368 | static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface) | |
369 | { | |
370 | return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state); | |
371 | } | |
372 | ||
e27ef599 AD |
373 | /* fm10k_test_staterr - test bits in Rx descriptor status and error fields */ |
374 | static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc, | |
375 | const u32 stat_err_bits) | |
376 | { | |
377 | return rx_desc->d.staterr & cpu_to_le32(stat_err_bits); | |
378 | } | |
379 | ||
380 | /* fm10k_desc_unused - calculate if we have unused descriptors */ | |
381 | static inline u16 fm10k_desc_unused(struct fm10k_ring *ring) | |
382 | { | |
383 | s16 unused = ring->next_to_clean - ring->next_to_use - 1; | |
384 | ||
385 | return likely(unused < 0) ? unused + ring->count : unused; | |
386 | } | |
387 | ||
388 | #define FM10K_TX_DESC(R, i) \ | |
389 | (&(((struct fm10k_tx_desc *)((R)->desc))[i])) | |
390 | #define FM10K_RX_DESC(R, i) \ | |
391 | (&(((union fm10k_rx_desc *)((R)->desc))[i])) | |
392 | ||
393 | #define FM10K_MAX_TXD_PWR 14 | |
394 | #define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR) | |
395 | ||
396 | /* Tx Descriptors needed, worst case */ | |
397 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD) | |
398 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) | |
399 | ||
400 | enum fm10k_tx_flags { | |
401 | /* Tx offload flags */ | |
402 | FM10K_TX_FLAGS_CSUM = 0x01, | |
403 | }; | |
404 | ||
405 | /* This structure is stored as little endian values as that is the native | |
406 | * format of the Rx descriptor. The ordering of these fields is reversed | |
407 | * from the actual ftag header to allow for a single bswap to take care | |
408 | * of placing all of the values in network order | |
409 | */ | |
410 | union fm10k_ftag_info { | |
411 | __le64 ftag; | |
412 | struct { | |
413 | /* dglort and sglort combined into a single 32bit desc read */ | |
414 | __le32 glort; | |
415 | /* upper 16 bits of vlan are reserved 0 for swpri_type_user */ | |
416 | __le32 vlan; | |
417 | } d; | |
418 | struct { | |
419 | __le16 dglort; | |
420 | __le16 sglort; | |
421 | __le16 vlan; | |
422 | __le16 swpri_type_user; | |
423 | } w; | |
424 | }; | |
425 | ||
426 | struct fm10k_cb { | |
a211e013 AD |
427 | union { |
428 | __le64 tstamp; | |
429 | unsigned long ts_tx_timeout; | |
430 | }; | |
e27ef599 AD |
431 | union fm10k_ftag_info fi; |
432 | }; | |
433 | ||
434 | #define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb) | |
435 | ||
b3890e30 AD |
436 | /* main */ |
437 | extern char fm10k_driver_name[]; | |
438 | extern const char fm10k_driver_version[]; | |
18283cad AD |
439 | int fm10k_init_queueing_scheme(struct fm10k_intfc *interface); |
440 | void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface); | |
5bf33dc6 | 441 | __be16 fm10k_tx_encap_offload(struct sk_buff *skb); |
b101c962 AD |
442 | netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb, |
443 | struct fm10k_ring *tx_ring); | |
444 | void fm10k_tx_timeout_reset(struct fm10k_intfc *interface); | |
445 | bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring); | |
446 | void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count); | |
b3890e30 AD |
447 | |
448 | /* PCI */ | |
18283cad AD |
449 | void fm10k_mbx_free_irq(struct fm10k_intfc *); |
450 | int fm10k_mbx_request_irq(struct fm10k_intfc *); | |
451 | void fm10k_qv_free_irq(struct fm10k_intfc *interface); | |
452 | int fm10k_qv_request_irq(struct fm10k_intfc *interface); | |
b3890e30 AD |
453 | int fm10k_register_pci_driver(void); |
454 | void fm10k_unregister_pci_driver(void); | |
504c5eac AD |
455 | void fm10k_up(struct fm10k_intfc *interface); |
456 | void fm10k_down(struct fm10k_intfc *interface); | |
b7d8514c AD |
457 | void fm10k_update_stats(struct fm10k_intfc *interface); |
458 | void fm10k_service_event_schedule(struct fm10k_intfc *interface); | |
459 | void fm10k_update_rx_drop_en(struct fm10k_intfc *interface); | |
8b4a98c7 JK |
460 | #ifdef CONFIG_NET_POLL_CONTROLLER |
461 | void fm10k_netpoll(struct net_device *netdev); | |
462 | #endif | |
0e7b3644 AD |
463 | |
464 | /* Netdev */ | |
465 | struct net_device *fm10k_alloc_netdev(void); | |
3abaae42 AD |
466 | int fm10k_setup_rx_resources(struct fm10k_ring *); |
467 | int fm10k_setup_tx_resources(struct fm10k_ring *); | |
468 | void fm10k_free_rx_resources(struct fm10k_ring *); | |
469 | void fm10k_free_tx_resources(struct fm10k_ring *); | |
470 | void fm10k_clean_all_rx_rings(struct fm10k_intfc *); | |
471 | void fm10k_clean_all_tx_rings(struct fm10k_intfc *); | |
472 | void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *, | |
473 | struct fm10k_tx_buffer *); | |
8f5e20d4 AD |
474 | void fm10k_restore_rx_state(struct fm10k_intfc *); |
475 | void fm10k_reset_rx_state(struct fm10k_intfc *); | |
aa3ac822 | 476 | int fm10k_setup_tc(struct net_device *dev, u8 tc); |
504c5eac AD |
477 | int fm10k_open(struct net_device *netdev); |
478 | int fm10k_close(struct net_device *netdev); | |
82dd0f7e AD |
479 | |
480 | /* Ethtool */ | |
481 | void fm10k_set_ethtool_ops(struct net_device *dev); | |
883a9ccb AD |
482 | |
483 | /* IOV */ | |
484 | s32 fm10k_iov_event(struct fm10k_intfc *interface); | |
485 | s32 fm10k_iov_mbx(struct fm10k_intfc *interface); | |
486 | void fm10k_iov_suspend(struct pci_dev *pdev); | |
487 | int fm10k_iov_resume(struct pci_dev *pdev); | |
488 | void fm10k_iov_disable(struct pci_dev *pdev); | |
489 | int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs); | |
490 | s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid); | |
491 | int fm10k_ndo_set_vf_mac(struct net_device *netdev, int vf_idx, u8 *mac); | |
492 | int fm10k_ndo_set_vf_vlan(struct net_device *netdev, | |
493 | int vf_idx, u16 vid, u8 qos); | |
494 | int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate, | |
495 | int unused); | |
496 | int fm10k_ndo_get_vf_config(struct net_device *netdev, | |
497 | int vf_idx, struct ifla_vf_info *ivi); | |
9f801abc | 498 | |
7461fd91 AD |
499 | /* DebugFS */ |
500 | #ifdef CONFIG_DEBUG_FS | |
501 | void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector); | |
502 | void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector); | |
503 | void fm10k_dbg_intfc_init(struct fm10k_intfc *interface); | |
504 | void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface); | |
505 | void fm10k_dbg_init(void); | |
506 | void fm10k_dbg_exit(void); | |
507 | #else | |
508 | static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {} | |
509 | static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {} | |
510 | static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {} | |
511 | static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {} | |
512 | static inline void fm10k_dbg_init(void) {} | |
513 | static inline void fm10k_dbg_exit(void) {} | |
514 | #endif /* CONFIG_DEBUG_FS */ | |
515 | ||
a211e013 AD |
516 | /* Time Stamping */ |
517 | void fm10k_systime_to_hwtstamp(struct fm10k_intfc *interface, | |
518 | struct skb_shared_hwtstamps *hwtstamp, | |
519 | u64 systime); | |
520 | void fm10k_ts_tx_enqueue(struct fm10k_intfc *interface, struct sk_buff *skb); | |
521 | void fm10k_ts_tx_hwtstamp(struct fm10k_intfc *interface, __le16 dglort, | |
522 | u64 systime); | |
523 | void fm10k_ts_reset(struct fm10k_intfc *interface); | |
524 | void fm10k_ts_init(struct fm10k_intfc *interface); | |
525 | void fm10k_ts_tx_subtask(struct fm10k_intfc *interface); | |
526 | void fm10k_ptp_register(struct fm10k_intfc *interface); | |
527 | void fm10k_ptp_unregister(struct fm10k_intfc *interface); | |
528 | int fm10k_get_ts_config(struct net_device *netdev, struct ifreq *ifr); | |
529 | int fm10k_set_ts_config(struct net_device *netdev, struct ifreq *ifr); | |
530 | ||
9f801abc AD |
531 | /* DCB */ |
532 | void fm10k_dcbnl_set_ops(struct net_device *dev); | |
b3890e30 | 533 | #endif /* _FM10K_H_ */ |