[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k.h

/* Intel Ethernet Switch Host Interface Driver
 * Copyright(c) 2013 - 2015 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 */

#ifndef _FM10K_H_
#define _FM10K_H_

#include <linux/types.h>
#include <linux/etherdevice.h>
#include <linux/rtnetlink.h>
#include <linux/if_vlan.h>
#include <linux/pci.h>
#include <linux/net_tstamp.h>
#include <linux/clocksource.h>
#include <linux/ptp_clock_kernel.h>

#include "fm10k_pf.h"
#include "fm10k_vf.h"

#define FM10K_MAX_JUMBO_FRAME_SIZE	15342	/* Maximum supported size 15K */

#define MAX_QUEUES	FM10K_MAX_QUEUES_PF

#define FM10K_MIN_RXD		 128
#define FM10K_MAX_RXD		4096
#define FM10K_DEFAULT_RXD	 256

#define FM10K_MIN_TXD		 128
#define FM10K_MAX_TXD		4096
#define FM10K_DEFAULT_TXD	 256
#define FM10K_DEFAULT_TX_WORK	 256

#define FM10K_RXBUFFER_256	  256
#define FM10K_RX_HDR_LEN	FM10K_RXBUFFER_256
#define FM10K_RXBUFFER_2048	 2048
#define FM10K_RX_BUFSZ		FM10K_RXBUFFER_2048

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define FM10K_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define FM10K_MAX_STATIONS	63
struct fm10k_l2_accel {
	int size;
	u16 count;
	u16 dglort;
	struct rcu_head rcu;
	struct net_device *macvlan[0];
};

enum fm10k_ring_state_t {
	__FM10K_TX_DETECT_HANG,
	__FM10K_HANG_CHECK_ARMED,
};

#define check_for_tx_hang(ring) \
	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define set_check_for_tx_hang(ring) \
	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
#define clear_check_for_tx_hang(ring) \
	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)

struct fm10k_tx_buffer {
	struct fm10k_tx_desc *next_to_watch;
	struct sk_buff *skb;
	unsigned int bytecount;
	u16 gso_segs;
	u16 tx_flags;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
};

struct fm10k_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	u32 page_offset;
};

struct fm10k_queue_stats {
	u64 packets;
	u64 bytes;
};

struct fm10k_tx_queue_stats {
	u64 restart_queue;
	u64 csum_err;
	u64 tx_busy;
	u64 tx_done_old;
	u64 csum_good;
};

struct fm10k_rx_queue_stats {
	u64 alloc_failed;
	u64 csum_err;
	u64 errors;
	u64 csum_good;
	u64 switch_errors;
	u64 drops;
	u64 pp_errors;
	u64 link_errors;
	u64 length_errors;
};

struct fm10k_ring {
	struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
	struct net_device *netdev;	/* netdev ring belongs to */
	struct device *dev;		/* device for DMA mapping */
	struct fm10k_l2_accel __rcu *l2_accel;	/* L2 acceleration list */
	void *desc;			/* descriptor ring memory */
	union {
		struct fm10k_tx_buffer *tx_buffer;
		struct fm10k_rx_buffer *rx_buffer;
	};
	u32 __iomem *tail;
	unsigned long state;
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */

	u8 queue_index;			/* needed for queue management */
	u8 reg_idx;			/* holds the special value that gets
					 * the hardware register offset
					 * associated with this ring, which is
					 * different for DCB and RSS modes
					 */
	u8 qos_pc;			/* priority class of queue */
	u16 vid;			/* default VLAN ID of queue */
	u16 count;			/* amount of descriptors */

	u16 next_to_alloc;
	u16 next_to_use;
	u16 next_to_clean;

	struct fm10k_queue_stats stats;
	struct u64_stats_sync syncp;
	union {
		/* Tx */
		struct fm10k_tx_queue_stats tx_stats;
		/* Rx */
		struct {
			struct fm10k_rx_queue_stats rx_stats;
			struct sk_buff *skb;
		};
	};
} ____cacheline_internodealigned_in_smp;

struct fm10k_ring_container {
	struct fm10k_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u16 work_limit;			/* total work allowed per interrupt */
	u16 itr;			/* interrupt throttle rate value */
	u8 itr_scale;			/* ITR adjustment scaler based on PCI speed */
	u8 count;			/* total number of rings in vector */
};

#define FM10K_ITR_MAX		0x0FFF	/* maximum value for ITR */
#define FM10K_ITR_10K		100	/* 100us */
#define FM10K_ITR_20K		50	/* 50us */
#define FM10K_ITR_40K		25	/* 25us */
#define FM10K_ITR_ADAPTIVE	0x8000	/* adaptive interrupt moderation flag */

#define ITR_IS_ADAPTIVE(itr) (!!(itr & FM10K_ITR_ADAPTIVE))

#define FM10K_TX_ITR_DEFAULT	FM10K_ITR_40K
#define FM10K_RX_ITR_DEFAULT	FM10K_ITR_20K
#define FM10K_ITR_ENABLE	(FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)

static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
{
	return &ring->netdev->_tx[ring->queue_index];
}

/* iterator for handling rings in ring container */
#define fm10k_for_each_ring(pos, head) \
	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)

#define MAX_Q_VECTORS 256
#define MIN_Q_VECTORS	1
enum fm10k_non_q_vectors {
	FM10K_MBX_VECTOR,
#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
	NON_Q_VECTORS_PF
};

#define NON_Q_VECTORS(hw)	(((hw)->mac.type == fm10k_mac_pf) ? \
						NON_Q_VECTORS_PF : \
						NON_Q_VECTORS_VF)
#define MIN_MSIX_COUNT(hw)	(MIN_Q_VECTORS + NON_Q_VECTORS(hw))

struct fm10k_q_vector {
	struct fm10k_intfc *interface;
	u32 __iomem *itr;	/* pointer to ITR register for this vector */
	u16 v_idx;		/* index of q_vector within interface array */
	struct fm10k_ring_container rx, tx;

	struct napi_struct napi;
	char name[IFNAMSIZ + 9];

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_q_vector;
#endif /* CONFIG_DEBUG_FS */
	struct rcu_head rcu;	/* to avoid race with update stats on free */

	/* for dynamic allocation of rings associated with this q_vector */
	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
};

enum fm10k_ring_f_enum {
	RING_F_RSS,
	RING_F_QOS,
	RING_F_ARRAY_SIZE  /* must be last in enum set */
};

struct fm10k_ring_feature {
	u16 limit;	/* upper limit on feature indices */
	u16 indices;	/* current value of indices */
	u16 mask;	/* Mask used for feature to ring mapping */
	u16 offset;	/* offset to start of feature */
};

struct fm10k_iov_data {
	unsigned int		num_vfs;
	unsigned int		next_vf_mbx;
	struct rcu_head		rcu;
	struct fm10k_vf_info	vf_info[0];
};

#define fm10k_vxlan_port_for_each(vp, intfc) \
	list_for_each_entry(vp, &(intfc)->vxlan_port, list)
struct fm10k_vxlan_port {
	struct list_head	list;
	sa_family_t		sa_family;
	__be16			port;
};

/* one work queue for entire driver */
extern struct workqueue_struct *fm10k_workqueue;

struct fm10k_intfc {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct net_device *netdev;
	struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */
	struct pci_dev *pdev;
	unsigned long state;

	u32 flags;
#define FM10K_FLAG_RESET_REQUESTED		(u32)(1 << 0)
#define FM10K_FLAG_RSS_FIELD_IPV4_UDP		(u32)(1 << 1)
#define FM10K_FLAG_RSS_FIELD_IPV6_UDP		(u32)(1 << 2)
#define FM10K_FLAG_RX_TS_ENABLED		(u32)(1 << 3)
#define FM10K_FLAG_SWPRI_CONFIG			(u32)(1 << 4)
#define FM10K_FLAG_DEBUG_STATS			(u32)(1 << 5)
	int xcast_mode;

	/* Tx fast path data */
	int num_tx_queues;
	u16 tx_itr;

	/* Rx fast path data */
	int num_rx_queues;
	u16 rx_itr;

	/* TX */
	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;

	u64 restart_queue;
	u64 tx_busy;
	u64 tx_csum_errors;
	u64 alloc_failed;
	u64 rx_csum_errors;

	u64 tx_bytes_nic;
	u64 tx_packets_nic;
	u64 rx_bytes_nic;
	u64 rx_packets_nic;
	u64 rx_drops_nic;
	u64 rx_overrun_pf;
	u64 rx_overrun_vf;

	/* Debug Statistics */
	u64 hw_sm_mbx_full;
	u64 hw_csum_tx_good;
	u64 hw_csum_rx_good;
	u64 rx_switch_errors;
	u64 rx_drops;
	u64 rx_pp_errors;
	u64 rx_link_errors;
	u64 rx_length_errors;

	u32 tx_timeout_count;

	/* RX */
	struct fm10k_ring *rx_ring[MAX_QUEUES];

	/* Queueing vectors */
	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	struct msix_entry *msix_entries;
	int num_q_vectors;	/* current number of q_vectors for device */
	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];

	/* SR-IOV information management structure */
	struct fm10k_iov_data *iov_data;

	struct fm10k_hw_stats stats;
	struct fm10k_hw hw;
	u32 __iomem *uc_addr;
	u32 __iomem *sw_addr;
	u16 msg_enable;
	u16 tx_ring_count;
	u16 rx_ring_count;
	struct timer_list service_timer;
	struct work_struct service_task;
	unsigned long next_stats_update;
	unsigned long next_tx_hang_check;
	unsigned long last_reset;
	unsigned long link_down_event;
	bool host_ready;

	u32 reta[FM10K_RETA_SIZE];
	u32 rssrk[FM10K_RSSRK_SIZE];

	/* VXLAN port tracking information */
	struct list_head vxlan_port;

#ifdef CONFIG_DEBUG_FS
	struct dentry *dbg_intfc;

#endif /* CONFIG_DEBUG_FS */
	struct ptp_clock_info ptp_caps;
	struct ptp_clock *ptp_clock;

	struct sk_buff_head ts_tx_skb_queue;
	u32 tx_hwtstamp_timeouts;

	struct hwtstamp_config ts_config;
	/* We are unable to actually adjust the clock beyond the frequency
	 * value.  Once the clock is started there is no resetting it.  As
	 * such we maintain a separate offset from the actual hardware clock
	 * to allow for offset adjustment.
	 */
	s64 ptp_adjust;
	rwlock_t systime_lock;
#ifdef CONFIG_DCB
	u8 pfc_en;
#endif
	u8 rx_pause;

	/* GLORT resources in use by PF */
	u16 glort;
	u16 glort_count;

	/* VLAN ID for updating multicast/unicast lists */
	u16 vid;
};

enum fm10k_state_t {
	__FM10K_RESETTING,
	__FM10K_DOWN,
	__FM10K_SERVICE_SCHED,
	__FM10K_SERVICE_DISABLE,
	__FM10K_MBX_LOCK,
	__FM10K_LINK_DOWN,
};

static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
{
	/* busy loop if we cannot obtain the lock as some calls
	 * such as ndo_set_rx_mode may be made in atomic context
	 */
	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
		udelay(20);
}

static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
{
	/* flush memory to make sure state is correct */
	smp_mb__before_atomic();
	clear_bit(__FM10K_MBX_LOCK, &interface->state);
}

static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
{
	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
}

/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
					const u32 stat_err_bits)
{
	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
}

/* fm10k_desc_unused - calculate if we have unused descriptors */
static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
{
	s16 unused = ring->next_to_clean - ring->next_to_use - 1;

	return likely(unused < 0) ? unused + ring->count : unused;
}

#define FM10K_TX_DESC(R, i)	\
	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
#define FM10K_RX_DESC(R, i)	\
	 (&(((union fm10k_rx_desc *)((R)->desc))[i]))

#define FM10K_MAX_TXD_PWR	14
#define FM10K_MAX_DATA_PER_TXD	(1 << FM10K_MAX_TXD_PWR)

/* Tx Descriptors needed, worst case */
#define TXD_USE_COUNT(S)	DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
#define DESC_NEEDED	(MAX_SKB_FRAGS + 4)

enum fm10k_tx_flags {
	/* Tx offload flags */
	FM10K_TX_FLAGS_CSUM	= 0x01,
};

/* This structure is stored as little endian values as that is the native
 * format of the Rx descriptor.  The ordering of these fields is reversed
 * from the actual ftag header to allow for a single bswap to take care
 * of placing all of the values in network order
 */
union fm10k_ftag_info {
	__le64 ftag;
	struct {
		/* dglort and sglort combined into a single 32bit desc read */
		__le32 glort;
		/* upper 16 bits of VLAN are reserved 0 for swpri_type_user */
		__le32 vlan;
	} d;
	struct {
		__le16 dglort;
		__le16 sglort;
		__le16 vlan;
		__le16 swpri_type_user;
	} w;
};

struct fm10k_cb {
	union {
		__le64 tstamp;
		unsigned long ts_tx_timeout;
	};
	union fm10k_ftag_info fi;
};

#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)

/* main */
extern char fm10k_driver_name[];
extern const char fm10k_driver_version[];
int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
				  struct fm10k_ring *tx_ring);
void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);

/* PCI */
void fm10k_mbx_free_irq(struct fm10k_intfc *);
int fm10k_mbx_request_irq(struct fm10k_intfc *);
void fm10k_qv_free_irq(struct fm10k_intfc *interface);
int fm10k_qv_request_irq(struct fm10k_intfc *interface);
int fm10k_register_pci_driver(void);
void fm10k_unregister_pci_driver(void);
void fm10k_up(struct fm10k_intfc *interface);
void fm10k_down(struct fm10k_intfc *interface);
void fm10k_update_stats(struct fm10k_intfc *interface);
void fm10k_service_event_schedule(struct fm10k_intfc *interface);
void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
#ifdef CONFIG_NET_POLL_CONTROLLER
void fm10k_netpoll(struct net_device *netdev);
#endif

/* Netdev */
struct net_device *fm10k_alloc_netdev(const struct fm10k_info *info);
int fm10k_setup_rx_resources(struct fm10k_ring *);
int fm10k_setup_tx_resources(struct fm10k_ring *);
void fm10k_free_rx_resources(struct fm10k_ring *);
void fm10k_free_tx_resources(struct fm10k_ring *);
void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
				      struct fm10k_tx_buffer *);
void fm10k_restore_rx_state(struct fm10k_intfc *);
void fm10k_reset_rx_state(struct fm10k_intfc *);
int fm10k_setup_tc(struct net_device *dev, u8 tc);
int fm10k_open(struct net_device *netdev);
int fm10k_close(struct net_device *netdev);

/* Ethtool */
void fm10k_set_ethtool_ops(struct net_device *dev);

/* IOV */
s32 fm10k_iov_event(struct fm10k_intfc *interface);
s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
void fm10k_iov_suspend(struct pci_dev *pdev);
int fm10k_iov_resume(struct pci_dev *pdev);
void fm10k_iov_disable(struct pci_dev *pdev);
int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
int fm10k_ndo_set_vf_mac(struct net_device *netdev, int vf_idx, u8 *mac);
int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
			  int vf_idx, u16 vid, u8 qos);
int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
			int unused);
int fm10k_ndo_get_vf_config(struct net_device *netdev,
			    int vf_idx, struct ifla_vf_info *ivi);

/* DebugFS */
#ifdef CONFIG_DEBUG_FS
void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
void fm10k_dbg_init(void);
void fm10k_dbg_exit(void);
#else
static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
static inline void fm10k_dbg_init(void) {}
static inline void fm10k_dbg_exit(void) {}
#endif /* CONFIG_DEBUG_FS */

/* Time Stamping */
void fm10k_systime_to_hwtstamp(struct fm10k_intfc *interface,
			       struct skb_shared_hwtstamps *hwtstamp,
			       u64 systime);
void fm10k_ts_tx_enqueue(struct fm10k_intfc *interface, struct sk_buff *skb);
void fm10k_ts_tx_hwtstamp(struct fm10k_intfc *interface, __le16 dglort,
			  u64 systime);
void fm10k_ts_reset(struct fm10k_intfc *interface);
void fm10k_ts_init(struct fm10k_intfc *interface);
void fm10k_ts_tx_subtask(struct fm10k_intfc *interface);
void fm10k_ptp_register(struct fm10k_intfc *interface);
void fm10k_ptp_unregister(struct fm10k_intfc *interface);
int fm10k_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
int fm10k_set_ts_config(struct net_device *netdev, struct ifreq *ifr);

/* DCB */
void fm10k_dcbnl_set_ops(struct net_device *dev);
#endif /* _FM10K_H_ */
Commit	Line	Data
b3890e30	1	/* Intel Ethernet Switch Host Interface Driver
97c71e3c	2	* Copyright(c) 2013 - 2015 Intel Corporation.
b3890e30 AD	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	* Contact Information:
	17	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	18	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	19	*/
	20
	21	#ifndef _FM10K_H_
	22	#define _FM10K_H_
	23
	24	#include <linux/types.h>
	25	#include <linux/etherdevice.h>
	26	#include <linux/rtnetlink.h>
	27	#include <linux/if_vlan.h>
	28	#include <linux/pci.h>
a211e013 AD	29	#include <linux/net_tstamp.h>
	30	#include <linux/clocksource.h>
	31	#include <linux/ptp_clock_kernel.h>
b3890e30	32
0e7b3644	33	#include "fm10k_pf.h"
5cb8db4a	34	#include "fm10k_vf.h"
0e7b3644	35
8c7ee6d2	36	#define FM10K_MAX_JUMBO_FRAME_SIZE 15342 /* Maximum supported size 15K */
0e7b3644	37
e27ef599 AD	38	#define MAX_QUEUES FM10K_MAX_QUEUES_PF
	39
	40	#define FM10K_MIN_RXD 128
	41	#define FM10K_MAX_RXD 4096
	42	#define FM10K_DEFAULT_RXD 256
	43
	44	#define FM10K_MIN_TXD 128
	45	#define FM10K_MAX_TXD 4096
	46	#define FM10K_DEFAULT_TXD 256
	47	#define FM10K_DEFAULT_TX_WORK 256
	48
	49	#define FM10K_RXBUFFER_256 256
e27ef599	50	#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
fd333962 AD	51	#define FM10K_RXBUFFER_2048 2048
fd333962 AD	52	#define FM10K_RX_BUFSZ FM10K_RXBUFFER_2048
e27ef599 AD	53
	54	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	55	#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	56
5cd5e2e9 AD	57	#define FM10K_MAX_STATIONS 63
	58	struct fm10k_l2_accel {
	59	int size;
	60	u16 count;
	61	u16 dglort;
	62	struct rcu_head rcu;
	63	struct net_device *macvlan[0];
	64	};
	65
e27ef599 AD	66	enum fm10k_ring_state_t {
	67	__FM10K_TX_DETECT_HANG,
	68	__FM10K_HANG_CHECK_ARMED,
	69	};
	70
	71	#define check_for_tx_hang(ring) \
	72	test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	73	#define set_check_for_tx_hang(ring) \
	74	set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	75	#define clear_check_for_tx_hang(ring) \
	76	clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
	77
	78	struct fm10k_tx_buffer {
	79	struct fm10k_tx_desc *next_to_watch;
	80	struct sk_buff *skb;
	81	unsigned int bytecount;
	82	u16 gso_segs;
	83	u16 tx_flags;
	84	DEFINE_DMA_UNMAP_ADDR(dma);
	85	DEFINE_DMA_UNMAP_LEN(len);
	86	};
	87
	88	struct fm10k_rx_buffer {
	89	dma_addr_t dma;
	90	struct page *page;
	91	u32 page_offset;
	92	};
	93
	94	struct fm10k_queue_stats {
	95	u64 packets;
	96	u64 bytes;
	97	};
	98
	99	struct fm10k_tx_queue_stats {
	100	u64 restart_queue;
	101	u64 csum_err;
	102	u64 tx_busy;
	103	u64 tx_done_old;
80043f3b	104	u64 csum_good;
e27ef599 AD	105	};
	106
	107	struct fm10k_rx_queue_stats {
	108	u64 alloc_failed;
	109	u64 csum_err;
	110	u64 errors;
80043f3b JK	111	u64 csum_good;
	112	u64 switch_errors;
	113	u64 drops;
	114	u64 pp_errors;
	115	u64 link_errors;
	116	u64 length_errors;
e27ef599 AD	117	};
	118
	119	struct fm10k_ring {
	120	struct fm10k_q_vector q_vector;/ backpointer to host q_vector */
	121	struct net_device netdev; / netdev ring belongs to */
	122	struct device dev; / device for DMA mapping */
5cd5e2e9	123	struct fm10k_l2_accel __rcu l2_accel; / L2 acceleration list */
e27ef599 AD	124	void desc; / descriptor ring memory */
	125	union {
	126	struct fm10k_tx_buffer *tx_buffer;
	127	struct fm10k_rx_buffer *rx_buffer;
	128	};
	129	u32 __iomem *tail;
	130	unsigned long state;
	131	dma_addr_t dma; /* phys. address of descriptor ring */
	132	unsigned int size; /* length in bytes */
	133
	134	u8 queue_index; /* needed for queue management */
	135	u8 reg_idx; /* holds the special value that gets
	136	* the hardware register offset
	137	* associated with this ring, which is
	138	* different for DCB and RSS modes
	139	*/
	140	u8 qos_pc; /* priority class of queue */
aa502b4a	141	u16 vid; /* default VLAN ID of queue */
e27ef599 AD	142	u16 count; /* amount of descriptors */
	143
	144	u16 next_to_alloc;
	145	u16 next_to_use;
	146	u16 next_to_clean;
	147
	148	struct fm10k_queue_stats stats;
	149	struct u64_stats_sync syncp;
	150	union {
	151	/* Tx */
	152	struct fm10k_tx_queue_stats tx_stats;
	153	/* Rx */
	154	struct {
	155	struct fm10k_rx_queue_stats rx_stats;
	156	struct sk_buff *skb;
	157	};
	158	};
	159	} ____cacheline_internodealigned_in_smp;
	160
18283cad	161	struct fm10k_ring_container {
e27ef599	162	struct fm10k_ring ring; / pointer to linked list of rings */
18283cad AD	163	unsigned int total_bytes; /* total bytes processed this int */
	164	unsigned int total_packets; /* total packets processed this int */
	165	u16 work_limit; /* total work allowed per interrupt */
	166	u16 itr; /* interrupt throttle rate value */
242722dd	167	u8 itr_scale; /* ITR adjustment scaler based on PCI speed */
18283cad AD	168	u8 count; /* total number of rings in vector */
	169	};
	170
	171	#define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
	172	#define FM10K_ITR_10K 100 /* 100us */
	173	#define FM10K_ITR_20K 50 /* 50us */
dbf42848	174	#define FM10K_ITR_40K 25 /* 25us */
18283cad AD	175	#define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
18283cad AD	176
584373f5 JK	177	#define ITR_IS_ADAPTIVE(itr) (!!(itr & FM10K_ITR_ADAPTIVE))
584373f5 JK	178
dbf42848	179	#define FM10K_TX_ITR_DEFAULT FM10K_ITR_40K
436ea956	180	#define FM10K_RX_ITR_DEFAULT FM10K_ITR_20K
18283cad AD	181	#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK \| FM10K_ITR_MASK_CLEAR)
18283cad AD	182
e27ef599 AD	183	static inline struct netdev_queue txring_txq(const struct fm10k_ring ring)
	184	{
	185	return &ring->netdev->_tx[ring->queue_index];
	186	}
	187
	188	/* iterator for handling rings in ring container */
	189	#define fm10k_for_each_ring(pos, head) \
	190	for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
	191
18283cad AD	192	#define MAX_Q_VECTORS 256
	193	#define MIN_Q_VECTORS 1
	194	enum fm10k_non_q_vectors {
	195	FM10K_MBX_VECTOR,
5cb8db4a	196	#define NON_Q_VECTORS_VF NON_Q_VECTORS_PF
18283cad AD	197	NON_Q_VECTORS_PF
	198	};
	199
	200	#define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
	201	NON_Q_VECTORS_PF : \
5cb8db4a	202	NON_Q_VECTORS_VF)
18283cad AD	203	#define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
	204
	205	struct fm10k_q_vector {
	206	struct fm10k_intfc *interface;
	207	u32 __iomem itr; / pointer to ITR register for this vector */
	208	u16 v_idx; /* index of q_vector within interface array */
	209	struct fm10k_ring_container rx, tx;
	210
	211	struct napi_struct napi;
	212	char name[IFNAMSIZ + 9];
	213
7461fd91 AD	214	#ifdef CONFIG_DEBUG_FS
	215	struct dentry *dbg_q_vector;
	216	#endif /* CONFIG_DEBUG_FS */
18283cad	217	struct rcu_head rcu; /* to avoid race with update stats on free */
e27ef599 AD	218
	219	/* for dynamic allocation of rings associated with this q_vector */
	220	struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
18283cad AD	221	};
18283cad AD	222
0e7b3644 AD	223	enum fm10k_ring_f_enum {
	224	RING_F_RSS,
	225	RING_F_QOS,
	226	RING_F_ARRAY_SIZE /* must be last in enum set */
	227	};
	228
	229	struct fm10k_ring_feature {
	230	u16 limit; /* upper limit on feature indices */
	231	u16 indices; /* current value of indices */
	232	u16 mask; /* Mask used for feature to ring mapping */
	233	u16 offset; /* offset to start of feature */
	234	};
	235
883a9ccb AD	236	struct fm10k_iov_data {
	237	unsigned int num_vfs;
	238	unsigned int next_vf_mbx;
	239	struct rcu_head rcu;
	240	struct fm10k_vf_info vf_info[0];
	241	};
	242
0e7b3644 AD	243	#define fm10k_vxlan_port_for_each(vp, intfc) \
	244	list_for_each_entry(vp, &(intfc)->vxlan_port, list)
	245	struct fm10k_vxlan_port {
	246	struct list_head list;
	247	sa_family_t sa_family;
	248	__be16 port;
	249	};
04a5aefb	250
b382bb1b JK	251	/* one work queue for entire driver */
	252	extern struct workqueue_struct *fm10k_workqueue;
	253
04a5aefb	254	struct fm10k_intfc {
0e7b3644 AD	255	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
0e7b3644 AD	256	struct net_device *netdev;
5cd5e2e9	257	struct fm10k_l2_accel l2_accel; / pointer to L2 acceleration list */
04a5aefb	258	struct pci_dev *pdev;
0e7b3644 AD	259	unsigned long state;
	260
	261	u32 flags;
	262	#define FM10K_FLAG_RESET_REQUESTED (u32)(1 << 0)
	263	#define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(1 << 1)
	264	#define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(1 << 2)
	265	#define FM10K_FLAG_RX_TS_ENABLED (u32)(1 << 3)
	266	#define FM10K_FLAG_SWPRI_CONFIG (u32)(1 << 4)
80043f3b	267	#define FM10K_FLAG_DEBUG_STATS (u32)(1 << 5)
0e7b3644 AD	268	int xcast_mode;
0e7b3644 AD	269
18283cad AD	270	/* Tx fast path data */
	271	int num_tx_queues;
	272	u16 tx_itr;
	273
	274	/* Rx fast path data */
	275	int num_rx_queues;
	276	u16 rx_itr;
	277
e27ef599 AD	278	/* TX */
	279	struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
	280
b7d8514c AD	281	u64 restart_queue;
	282	u64 tx_busy;
	283	u64 tx_csum_errors;
	284	u64 alloc_failed;
	285	u64 rx_csum_errors;
b7d8514c AD	286
	287	u64 tx_bytes_nic;
	288	u64 tx_packets_nic;
	289	u64 rx_bytes_nic;
	290	u64 rx_packets_nic;
	291	u64 rx_drops_nic;
0e7b3644 AD	292	u64 rx_overrun_pf;
0e7b3644 AD	293	u64 rx_overrun_vf;
80043f3b JK	294
	295	/* Debug Statistics */
	296	u64 hw_sm_mbx_full;
	297	u64 hw_csum_tx_good;
	298	u64 hw_csum_rx_good;
	299	u64 rx_switch_errors;
	300	u64 rx_drops;
	301	u64 rx_pp_errors;
	302	u64 rx_link_errors;
	303	u64 rx_length_errors;
	304
b7d8514c	305	u32 tx_timeout_count;
04a5aefb	306
e27ef599 AD	307	/* RX */
	308	struct fm10k_ring *rx_ring[MAX_QUEUES];
	309
18283cad AD	310	/* Queueing vectors */
	311	struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
	312	struct msix_entry *msix_entries;
	313	int num_q_vectors; /* current number of q_vectors for device */
0e7b3644 AD	314	struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
0e7b3644 AD	315
883a9ccb AD	316	/* SR-IOV information management structure */
	317	struct fm10k_iov_data *iov_data;
	318
0e7b3644	319	struct fm10k_hw_stats stats;
04a5aefb AD	320	struct fm10k_hw hw;
04a5aefb AD	321	u32 __iomem *uc_addr;
a211e013	322	u32 __iomem *sw_addr;
0e7b3644	323	u16 msg_enable;
18283cad AD	324	u16 tx_ring_count;
18283cad AD	325	u16 rx_ring_count;
b7d8514c AD	326	struct timer_list service_timer;
	327	struct work_struct service_task;
	328	unsigned long next_stats_update;
	329	unsigned long next_tx_hang_check;
	330	unsigned long last_reset;
	331	unsigned long link_down_event;
	332	bool host_ready;
0e7b3644 AD	333
	334	u32 reta[FM10K_RETA_SIZE];
	335	u32 rssrk[FM10K_RSSRK_SIZE];
	336
	337	/* VXLAN port tracking information */
	338	struct list_head vxlan_port;
	339
7461fd91 AD	340	#ifdef CONFIG_DEBUG_FS
	341	struct dentry *dbg_intfc;
	342
	343	#endif /* CONFIG_DEBUG_FS */
a211e013 AD	344	struct ptp_clock_info ptp_caps;
	345	struct ptp_clock *ptp_clock;
	346
	347	struct sk_buff_head ts_tx_skb_queue;
	348	u32 tx_hwtstamp_timeouts;
	349
	350	struct hwtstamp_config ts_config;
	351	/* We are unable to actually adjust the clock beyond the frequency
	352	* value. Once the clock is started there is no resetting it. As
	353	* such we maintain a separate offset from the actual hardware clock
	354	* to allow for offset adjustment.
	355	*/
	356	s64 ptp_adjust;
	357	rwlock_t systime_lock;
9f801abc	358	#ifdef CONFIG_DCB
0e7b3644 AD	359	u8 pfc_en;
	360	#endif
	361	u8 rx_pause;
	362
	363	/* GLORT resources in use by PF */
	364	u16 glort;
	365	u16 glort_count;
	366
	367	/* VLAN ID for updating multicast/unicast lists */
	368	u16 vid;
	369	};
	370
	371	enum fm10k_state_t {
	372	__FM10K_RESETTING,
	373	__FM10K_DOWN,
b7d8514c AD	374	__FM10K_SERVICE_SCHED,
b7d8514c AD	375	__FM10K_SERVICE_DISABLE,
0e7b3644 AD	376	__FM10K_MBX_LOCK,
0e7b3644 AD	377	__FM10K_LINK_DOWN,
04a5aefb	378	};
b3890e30	379
0e7b3644 AD	380	static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
	381	{
	382	/* busy loop if we cannot obtain the lock as some calls
	383	* such as ndo_set_rx_mode may be made in atomic context
	384	*/
	385	while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
	386	udelay(20);
	387	}
	388
	389	static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
	390	{
	391	/* flush memory to make sure state is correct */
	392	smp_mb__before_atomic();
	393	clear_bit(__FM10K_MBX_LOCK, &interface->state);
	394	}
	395
	396	static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
	397	{
	398	return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
	399	}
	400
e27ef599 AD	401	/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
	402	static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
	403	const u32 stat_err_bits)
	404	{
	405	return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
	406	}
	407
	408	/* fm10k_desc_unused - calculate if we have unused descriptors */
	409	static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
	410	{
	411	s16 unused = ring->next_to_clean - ring->next_to_use - 1;
	412
	413	return likely(unused < 0) ? unused + ring->count : unused;
	414	}
	415
	416	#define FM10K_TX_DESC(R, i) \
	417	(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
	418	#define FM10K_RX_DESC(R, i) \
	419	(&(((union fm10k_rx_desc *)((R)->desc))[i]))
	420
	421	#define FM10K_MAX_TXD_PWR 14
	422	#define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR)
	423
	424	/* Tx Descriptors needed, worst case */
	425	#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
	426	#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
	427
	428	enum fm10k_tx_flags {
	429	/* Tx offload flags */
	430	FM10K_TX_FLAGS_CSUM = 0x01,
	431	};
	432
	433	/* This structure is stored as little endian values as that is the native
	434	* format of the Rx descriptor. The ordering of these fields is reversed
	435	* from the actual ftag header to allow for a single bswap to take care
	436	* of placing all of the values in network order
	437	*/
	438	union fm10k_ftag_info {
	439	__le64 ftag;
	440	struct {
	441	/* dglort and sglort combined into a single 32bit desc read */
	442	__le32 glort;
aa502b4a	443	/* upper 16 bits of VLAN are reserved 0 for swpri_type_user */
e27ef599 AD	444	__le32 vlan;
	445	} d;
	446	struct {
	447	__le16 dglort;
	448	__le16 sglort;
	449	__le16 vlan;
	450	__le16 swpri_type_user;
	451	} w;
	452	};
	453
	454	struct fm10k_cb {
a211e013 AD	455	union {
	456	__le64 tstamp;
	457	unsigned long ts_tx_timeout;
	458	};
e27ef599 AD	459	union fm10k_ftag_info fi;
	460	};
	461
	462	#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
	463
b3890e30 AD	464	/* main */
	465	extern char fm10k_driver_name[];
	466	extern const char fm10k_driver_version[];
18283cad AD	467	int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
18283cad AD	468	void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
5bf33dc6	469	__be16 fm10k_tx_encap_offload(struct sk_buff *skb);
b101c962 AD	470	netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
	471	struct fm10k_ring *tx_ring);
	472	void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
	473	bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
	474	void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);
b3890e30 AD	475
b3890e30 AD	476	/* PCI */
18283cad AD	477	void fm10k_mbx_free_irq(struct fm10k_intfc *);
	478	int fm10k_mbx_request_irq(struct fm10k_intfc *);
	479	void fm10k_qv_free_irq(struct fm10k_intfc *interface);
	480	int fm10k_qv_request_irq(struct fm10k_intfc *interface);
b3890e30 AD	481	int fm10k_register_pci_driver(void);
b3890e30 AD	482	void fm10k_unregister_pci_driver(void);
504c5eac AD	483	void fm10k_up(struct fm10k_intfc *interface);
504c5eac AD	484	void fm10k_down(struct fm10k_intfc *interface);
b7d8514c AD	485	void fm10k_update_stats(struct fm10k_intfc *interface);
	486	void fm10k_service_event_schedule(struct fm10k_intfc *interface);
	487	void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
8b4a98c7 JK	488	#ifdef CONFIG_NET_POLL_CONTROLLER
	489	void fm10k_netpoll(struct net_device *netdev);
	490	#endif
0e7b3644 AD	491
0e7b3644 AD	492	/* Netdev */
e0244903	493	struct net_device fm10k_alloc_netdev(const struct fm10k_info info);
3abaae42 AD	494	int fm10k_setup_rx_resources(struct fm10k_ring *);
	495	int fm10k_setup_tx_resources(struct fm10k_ring *);
	496	void fm10k_free_rx_resources(struct fm10k_ring *);
	497	void fm10k_free_tx_resources(struct fm10k_ring *);
	498	void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
	499	void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
	500	void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
	501	struct fm10k_tx_buffer *);
8f5e20d4 AD	502	void fm10k_restore_rx_state(struct fm10k_intfc *);
8f5e20d4 AD	503	void fm10k_reset_rx_state(struct fm10k_intfc *);
aa3ac822	504	int fm10k_setup_tc(struct net_device *dev, u8 tc);
504c5eac AD	505	int fm10k_open(struct net_device *netdev);
504c5eac AD	506	int fm10k_close(struct net_device *netdev);
82dd0f7e AD	507
	508	/* Ethtool */
	509	void fm10k_set_ethtool_ops(struct net_device *dev);
883a9ccb AD	510
	511	/* IOV */
	512	s32 fm10k_iov_event(struct fm10k_intfc *interface);
	513	s32 fm10k_iov_mbx(struct fm10k_intfc *interface);
	514	void fm10k_iov_suspend(struct pci_dev *pdev);
	515	int fm10k_iov_resume(struct pci_dev *pdev);
	516	void fm10k_iov_disable(struct pci_dev *pdev);
	517	int fm10k_iov_configure(struct pci_dev *pdev, int num_vfs);
	518	s32 fm10k_iov_update_pvid(struct fm10k_intfc *interface, u16 glort, u16 pvid);
	519	int fm10k_ndo_set_vf_mac(struct net_device netdev, int vf_idx, u8 mac);
	520	int fm10k_ndo_set_vf_vlan(struct net_device *netdev,
	521	int vf_idx, u16 vid, u8 qos);
	522	int fm10k_ndo_set_vf_bw(struct net_device *netdev, int vf_idx, int rate,
	523	int unused);
	524	int fm10k_ndo_get_vf_config(struct net_device *netdev,
	525	int vf_idx, struct ifla_vf_info *ivi);
9f801abc	526
7461fd91 AD	527	/* DebugFS */
	528	#ifdef CONFIG_DEBUG_FS
	529	void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector);
	530	void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector);
	531	void fm10k_dbg_intfc_init(struct fm10k_intfc *interface);
	532	void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface);
	533	void fm10k_dbg_init(void);
	534	void fm10k_dbg_exit(void);
	535	#else
	536	static inline void fm10k_dbg_q_vector_init(struct fm10k_q_vector *q_vector) {}
	537	static inline void fm10k_dbg_q_vector_exit(struct fm10k_q_vector *q_vector) {}
	538	static inline void fm10k_dbg_intfc_init(struct fm10k_intfc *interface) {}
	539	static inline void fm10k_dbg_intfc_exit(struct fm10k_intfc *interface) {}
	540	static inline void fm10k_dbg_init(void) {}
	541	static inline void fm10k_dbg_exit(void) {}
	542	#endif /* CONFIG_DEBUG_FS */
	543
a211e013 AD	544	/* Time Stamping */
	545	void fm10k_systime_to_hwtstamp(struct fm10k_intfc *interface,
	546	struct skb_shared_hwtstamps *hwtstamp,
	547	u64 systime);
	548	void fm10k_ts_tx_enqueue(struct fm10k_intfc interface, struct sk_buff skb);
	549	void fm10k_ts_tx_hwtstamp(struct fm10k_intfc *interface, __le16 dglort,
	550	u64 systime);
	551	void fm10k_ts_reset(struct fm10k_intfc *interface);
	552	void fm10k_ts_init(struct fm10k_intfc *interface);
	553	void fm10k_ts_tx_subtask(struct fm10k_intfc *interface);
	554	void fm10k_ptp_register(struct fm10k_intfc *interface);
	555	void fm10k_ptp_unregister(struct fm10k_intfc *interface);
	556	int fm10k_get_ts_config(struct net_device netdev, struct ifreq ifr);
	557	int fm10k_set_ts_config(struct net_device netdev, struct ifreq ifr);
	558
9f801abc AD	559	/* DCB */
9f801abc AD	560	void fm10k_dcbnl_set_ops(struct net_device *dev);
b3890e30	561	#endif /* _FM10K_H_ */