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b3890e30 | 1 | /* Intel Ethernet Switch Host Interface Driver |
9de6a1a6 | 2 | * Copyright(c) 2013 - 2016 Intel Corporation. |
b3890e30 AD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
19 | */ | |
20 | ||
21 | #include <linux/types.h> | |
22 | #include <linux/module.h> | |
23 | #include <net/ipv6.h> | |
24 | #include <net/ip.h> | |
25 | #include <net/tcp.h> | |
26 | #include <linux/if_macvlan.h> | |
b101c962 | 27 | #include <linux/prefetch.h> |
b3890e30 AD |
28 | |
29 | #include "fm10k.h" | |
30 | ||
e3b6e95d | 31 | #define DRV_VERSION "0.19.3-k" |
2d0f76be | 32 | #define DRV_SUMMARY "Intel(R) Ethernet Switch Host Interface Driver" |
b3890e30 AD |
33 | const char fm10k_driver_version[] = DRV_VERSION; |
34 | char fm10k_driver_name[] = "fm10k"; | |
2d0f76be | 35 | static const char fm10k_driver_string[] = DRV_SUMMARY; |
b3890e30 AD |
36 | static const char fm10k_copyright[] = |
37 | "Copyright (c) 2013 Intel Corporation."; | |
38 | ||
39 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); | |
2d0f76be | 40 | MODULE_DESCRIPTION(DRV_SUMMARY); |
b3890e30 AD |
41 | MODULE_LICENSE("GPL"); |
42 | MODULE_VERSION(DRV_VERSION); | |
43 | ||
b382bb1b | 44 | /* single workqueue for entire fm10k driver */ |
07146e2e | 45 | struct workqueue_struct *fm10k_workqueue; |
b382bb1b | 46 | |
6d2ce900 AD |
47 | /** |
48 | * fm10k_init_module - Driver Registration Routine | |
b3890e30 AD |
49 | * |
50 | * fm10k_init_module is the first routine called when the driver is | |
51 | * loaded. All it does is register with the PCI subsystem. | |
52 | **/ | |
53 | static int __init fm10k_init_module(void) | |
54 | { | |
55 | pr_info("%s - version %s\n", fm10k_driver_string, fm10k_driver_version); | |
56 | pr_info("%s\n", fm10k_copyright); | |
57 | ||
b382bb1b | 58 | /* create driver workqueue */ |
07146e2e | 59 | fm10k_workqueue = create_workqueue("fm10k"); |
b382bb1b | 60 | |
7461fd91 AD |
61 | fm10k_dbg_init(); |
62 | ||
b3890e30 AD |
63 | return fm10k_register_pci_driver(); |
64 | } | |
65 | module_init(fm10k_init_module); | |
66 | ||
67 | /** | |
68 | * fm10k_exit_module - Driver Exit Cleanup Routine | |
69 | * | |
70 | * fm10k_exit_module is called just before the driver is removed | |
71 | * from memory. | |
72 | **/ | |
73 | static void __exit fm10k_exit_module(void) | |
74 | { | |
75 | fm10k_unregister_pci_driver(); | |
7461fd91 AD |
76 | |
77 | fm10k_dbg_exit(); | |
b382bb1b JK |
78 | |
79 | /* destroy driver workqueue */ | |
80 | flush_workqueue(fm10k_workqueue); | |
81 | destroy_workqueue(fm10k_workqueue); | |
b3890e30 AD |
82 | } |
83 | module_exit(fm10k_exit_module); | |
18283cad | 84 | |
b101c962 AD |
85 | static bool fm10k_alloc_mapped_page(struct fm10k_ring *rx_ring, |
86 | struct fm10k_rx_buffer *bi) | |
87 | { | |
88 | struct page *page = bi->page; | |
89 | dma_addr_t dma; | |
90 | ||
91 | /* Only page will be NULL if buffer was consumed */ | |
92 | if (likely(page)) | |
93 | return true; | |
94 | ||
95 | /* alloc new page for storage */ | |
42b17f09 | 96 | page = dev_alloc_page(); |
b101c962 AD |
97 | if (unlikely(!page)) { |
98 | rx_ring->rx_stats.alloc_failed++; | |
99 | return false; | |
100 | } | |
101 | ||
102 | /* map page for use */ | |
103 | dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
104 | ||
105 | /* if mapping failed free memory back to system since | |
106 | * there isn't much point in holding memory we can't use | |
107 | */ | |
108 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
109 | __free_page(page); | |
b101c962 AD |
110 | |
111 | rx_ring->rx_stats.alloc_failed++; | |
112 | return false; | |
113 | } | |
114 | ||
115 | bi->dma = dma; | |
116 | bi->page = page; | |
117 | bi->page_offset = 0; | |
118 | ||
119 | return true; | |
120 | } | |
121 | ||
122 | /** | |
123 | * fm10k_alloc_rx_buffers - Replace used receive buffers | |
124 | * @rx_ring: ring to place buffers on | |
125 | * @cleaned_count: number of buffers to replace | |
126 | **/ | |
127 | void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count) | |
128 | { | |
129 | union fm10k_rx_desc *rx_desc; | |
130 | struct fm10k_rx_buffer *bi; | |
131 | u16 i = rx_ring->next_to_use; | |
132 | ||
133 | /* nothing to do */ | |
134 | if (!cleaned_count) | |
135 | return; | |
136 | ||
137 | rx_desc = FM10K_RX_DESC(rx_ring, i); | |
138 | bi = &rx_ring->rx_buffer[i]; | |
139 | i -= rx_ring->count; | |
140 | ||
141 | do { | |
142 | if (!fm10k_alloc_mapped_page(rx_ring, bi)) | |
143 | break; | |
144 | ||
145 | /* Refresh the desc even if buffer_addrs didn't change | |
146 | * because each write-back erases this info. | |
147 | */ | |
148 | rx_desc->q.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
149 | ||
150 | rx_desc++; | |
151 | bi++; | |
152 | i++; | |
153 | if (unlikely(!i)) { | |
154 | rx_desc = FM10K_RX_DESC(rx_ring, 0); | |
155 | bi = rx_ring->rx_buffer; | |
156 | i -= rx_ring->count; | |
157 | } | |
158 | ||
ba5b8dcd AD |
159 | /* clear the status bits for the next_to_use descriptor */ |
160 | rx_desc->d.staterr = 0; | |
b101c962 AD |
161 | |
162 | cleaned_count--; | |
163 | } while (cleaned_count); | |
164 | ||
165 | i += rx_ring->count; | |
166 | ||
167 | if (rx_ring->next_to_use != i) { | |
168 | /* record the next descriptor to use */ | |
169 | rx_ring->next_to_use = i; | |
170 | ||
171 | /* update next to alloc since we have filled the ring */ | |
172 | rx_ring->next_to_alloc = i; | |
173 | ||
174 | /* Force memory writes to complete before letting h/w | |
175 | * know there are new descriptors to fetch. (Only | |
176 | * applicable for weak-ordered memory model archs, | |
177 | * such as IA-64). | |
178 | */ | |
179 | wmb(); | |
180 | ||
181 | /* notify hardware of new descriptors */ | |
182 | writel(i, rx_ring->tail); | |
183 | } | |
184 | } | |
185 | ||
186 | /** | |
187 | * fm10k_reuse_rx_page - page flip buffer and store it back on the ring | |
188 | * @rx_ring: rx descriptor ring to store buffers on | |
189 | * @old_buff: donor buffer to have page reused | |
190 | * | |
191 | * Synchronizes page for reuse by the interface | |
192 | **/ | |
193 | static void fm10k_reuse_rx_page(struct fm10k_ring *rx_ring, | |
194 | struct fm10k_rx_buffer *old_buff) | |
195 | { | |
196 | struct fm10k_rx_buffer *new_buff; | |
197 | u16 nta = rx_ring->next_to_alloc; | |
198 | ||
199 | new_buff = &rx_ring->rx_buffer[nta]; | |
200 | ||
201 | /* update, and store next to alloc */ | |
202 | nta++; | |
203 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
204 | ||
205 | /* transfer page from old buffer to new buffer */ | |
ba5b8dcd | 206 | *new_buff = *old_buff; |
b101c962 AD |
207 | |
208 | /* sync the buffer for use by the device */ | |
209 | dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, | |
210 | old_buff->page_offset, | |
211 | FM10K_RX_BUFSZ, | |
212 | DMA_FROM_DEVICE); | |
213 | } | |
214 | ||
ba5b8dcd AD |
215 | static inline bool fm10k_page_is_reserved(struct page *page) |
216 | { | |
2f064f34 | 217 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); |
ba5b8dcd AD |
218 | } |
219 | ||
b101c962 AD |
220 | static bool fm10k_can_reuse_rx_page(struct fm10k_rx_buffer *rx_buffer, |
221 | struct page *page, | |
de445199 | 222 | unsigned int __maybe_unused truesize) |
b101c962 AD |
223 | { |
224 | /* avoid re-using remote pages */ | |
ba5b8dcd | 225 | if (unlikely(fm10k_page_is_reserved(page))) |
b101c962 AD |
226 | return false; |
227 | ||
228 | #if (PAGE_SIZE < 8192) | |
229 | /* if we are only owner of page we can reuse it */ | |
230 | if (unlikely(page_count(page) != 1)) | |
231 | return false; | |
232 | ||
233 | /* flip page offset to other buffer */ | |
234 | rx_buffer->page_offset ^= FM10K_RX_BUFSZ; | |
b101c962 AD |
235 | #else |
236 | /* move offset up to the next cache line */ | |
237 | rx_buffer->page_offset += truesize; | |
238 | ||
239 | if (rx_buffer->page_offset > (PAGE_SIZE - FM10K_RX_BUFSZ)) | |
240 | return false; | |
b101c962 AD |
241 | #endif |
242 | ||
ba5b8dcd AD |
243 | /* Even if we own the page, we are not allowed to use atomic_set() |
244 | * This would break get_page_unless_zero() users. | |
245 | */ | |
fe896d18 | 246 | page_ref_inc(page); |
ba5b8dcd | 247 | |
b101c962 AD |
248 | return true; |
249 | } | |
250 | ||
251 | /** | |
252 | * fm10k_add_rx_frag - Add contents of Rx buffer to sk_buff | |
b101c962 AD |
253 | * @rx_buffer: buffer containing page to add |
254 | * @rx_desc: descriptor containing length of buffer written by hardware | |
255 | * @skb: sk_buff to place the data into | |
256 | * | |
257 | * This function will add the data contained in rx_buffer->page to the skb. | |
258 | * This is done either through a direct copy if the data in the buffer is | |
259 | * less than the skb header size, otherwise it will just attach the page as | |
260 | * a frag to the skb. | |
261 | * | |
262 | * The function will then update the page offset if necessary and return | |
263 | * true if the buffer can be reused by the interface. | |
264 | **/ | |
de445199 | 265 | static bool fm10k_add_rx_frag(struct fm10k_rx_buffer *rx_buffer, |
b101c962 AD |
266 | union fm10k_rx_desc *rx_desc, |
267 | struct sk_buff *skb) | |
268 | { | |
269 | struct page *page = rx_buffer->page; | |
1a8782e5 | 270 | unsigned char *va = page_address(page) + rx_buffer->page_offset; |
b101c962 AD |
271 | unsigned int size = le16_to_cpu(rx_desc->w.length); |
272 | #if (PAGE_SIZE < 8192) | |
273 | unsigned int truesize = FM10K_RX_BUFSZ; | |
274 | #else | |
1a8782e5 | 275 | unsigned int truesize = SKB_DATA_ALIGN(size); |
b101c962 | 276 | #endif |
1a8782e5 | 277 | unsigned int pull_len; |
b101c962 | 278 | |
1a8782e5 AD |
279 | if (unlikely(skb_is_nonlinear(skb))) |
280 | goto add_tail_frag; | |
b101c962 | 281 | |
1a8782e5 | 282 | if (likely(size <= FM10K_RX_HDR_LEN)) { |
b101c962 AD |
283 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); |
284 | ||
ba5b8dcd AD |
285 | /* page is not reserved, we can reuse buffer as-is */ |
286 | if (likely(!fm10k_page_is_reserved(page))) | |
b101c962 AD |
287 | return true; |
288 | ||
289 | /* this page cannot be reused so discard it */ | |
ba5b8dcd | 290 | __free_page(page); |
b101c962 AD |
291 | return false; |
292 | } | |
293 | ||
1a8782e5 AD |
294 | /* we need the header to contain the greater of either ETH_HLEN or |
295 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
296 | */ | |
297 | pull_len = eth_get_headlen(va, FM10K_RX_HDR_LEN); | |
298 | ||
299 | /* align pull length to size of long to optimize memcpy performance */ | |
300 | memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long))); | |
301 | ||
302 | /* update all of the pointers */ | |
303 | va += pull_len; | |
304 | size -= pull_len; | |
305 | ||
306 | add_tail_frag: | |
b101c962 | 307 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, |
1a8782e5 | 308 | (unsigned long)va & ~PAGE_MASK, size, truesize); |
b101c962 AD |
309 | |
310 | return fm10k_can_reuse_rx_page(rx_buffer, page, truesize); | |
311 | } | |
312 | ||
313 | static struct sk_buff *fm10k_fetch_rx_buffer(struct fm10k_ring *rx_ring, | |
314 | union fm10k_rx_desc *rx_desc, | |
315 | struct sk_buff *skb) | |
316 | { | |
317 | struct fm10k_rx_buffer *rx_buffer; | |
318 | struct page *page; | |
319 | ||
320 | rx_buffer = &rx_ring->rx_buffer[rx_ring->next_to_clean]; | |
b101c962 AD |
321 | page = rx_buffer->page; |
322 | prefetchw(page); | |
323 | ||
324 | if (likely(!skb)) { | |
325 | void *page_addr = page_address(page) + | |
326 | rx_buffer->page_offset; | |
327 | ||
328 | /* prefetch first cache line of first page */ | |
329 | prefetch(page_addr); | |
330 | #if L1_CACHE_BYTES < 128 | |
331 | prefetch(page_addr + L1_CACHE_BYTES); | |
332 | #endif | |
333 | ||
334 | /* allocate a skb to store the frags */ | |
67fd893e AD |
335 | skb = napi_alloc_skb(&rx_ring->q_vector->napi, |
336 | FM10K_RX_HDR_LEN); | |
b101c962 AD |
337 | if (unlikely(!skb)) { |
338 | rx_ring->rx_stats.alloc_failed++; | |
339 | return NULL; | |
340 | } | |
341 | ||
342 | /* we will be copying header into skb->data in | |
343 | * pskb_may_pull so it is in our interest to prefetch | |
344 | * it now to avoid a possible cache miss | |
345 | */ | |
346 | prefetchw(skb->data); | |
347 | } | |
348 | ||
349 | /* we are reusing so sync this buffer for CPU use */ | |
350 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
351 | rx_buffer->dma, | |
352 | rx_buffer->page_offset, | |
353 | FM10K_RX_BUFSZ, | |
354 | DMA_FROM_DEVICE); | |
355 | ||
356 | /* pull page into skb */ | |
de445199 | 357 | if (fm10k_add_rx_frag(rx_buffer, rx_desc, skb)) { |
b101c962 AD |
358 | /* hand second half of page back to the ring */ |
359 | fm10k_reuse_rx_page(rx_ring, rx_buffer); | |
360 | } else { | |
361 | /* we are not reusing the buffer so unmap it */ | |
362 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
363 | PAGE_SIZE, DMA_FROM_DEVICE); | |
364 | } | |
365 | ||
366 | /* clear contents of rx_buffer */ | |
367 | rx_buffer->page = NULL; | |
368 | ||
369 | return skb; | |
370 | } | |
371 | ||
76a540d4 AD |
372 | static inline void fm10k_rx_checksum(struct fm10k_ring *ring, |
373 | union fm10k_rx_desc *rx_desc, | |
374 | struct sk_buff *skb) | |
375 | { | |
376 | skb_checksum_none_assert(skb); | |
377 | ||
378 | /* Rx checksum disabled via ethtool */ | |
379 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) | |
380 | return; | |
381 | ||
382 | /* TCP/UDP checksum error bit is set */ | |
383 | if (fm10k_test_staterr(rx_desc, | |
384 | FM10K_RXD_STATUS_L4E | | |
385 | FM10K_RXD_STATUS_L4E2 | | |
386 | FM10K_RXD_STATUS_IPE | | |
387 | FM10K_RXD_STATUS_IPE2)) { | |
388 | ring->rx_stats.csum_err++; | |
389 | return; | |
390 | } | |
391 | ||
392 | /* It must be a TCP or UDP packet with a valid checksum */ | |
393 | if (fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS2)) | |
394 | skb->encapsulation = true; | |
395 | else if (!fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS)) | |
396 | return; | |
397 | ||
398 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
80043f3b JK |
399 | |
400 | ring->rx_stats.csum_good++; | |
76a540d4 AD |
401 | } |
402 | ||
403 | #define FM10K_RSS_L4_TYPES_MASK \ | |
fcdb0a99 BA |
404 | (BIT(FM10K_RSSTYPE_IPV4_TCP) | \ |
405 | BIT(FM10K_RSSTYPE_IPV4_UDP) | \ | |
406 | BIT(FM10K_RSSTYPE_IPV6_TCP) | \ | |
407 | BIT(FM10K_RSSTYPE_IPV6_UDP)) | |
76a540d4 AD |
408 | |
409 | static inline void fm10k_rx_hash(struct fm10k_ring *ring, | |
410 | union fm10k_rx_desc *rx_desc, | |
411 | struct sk_buff *skb) | |
412 | { | |
413 | u16 rss_type; | |
414 | ||
415 | if (!(ring->netdev->features & NETIF_F_RXHASH)) | |
416 | return; | |
417 | ||
418 | rss_type = le16_to_cpu(rx_desc->w.pkt_info) & FM10K_RXD_RSSTYPE_MASK; | |
419 | if (!rss_type) | |
420 | return; | |
421 | ||
422 | skb_set_hash(skb, le32_to_cpu(rx_desc->d.rss), | |
fcdb0a99 | 423 | (BIT(rss_type) & FM10K_RSS_L4_TYPES_MASK) ? |
76a540d4 AD |
424 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); |
425 | } | |
426 | ||
5cd5e2e9 | 427 | static void fm10k_type_trans(struct fm10k_ring *rx_ring, |
de445199 | 428 | union fm10k_rx_desc __maybe_unused *rx_desc, |
5cd5e2e9 AD |
429 | struct sk_buff *skb) |
430 | { | |
431 | struct net_device *dev = rx_ring->netdev; | |
432 | struct fm10k_l2_accel *l2_accel = rcu_dereference_bh(rx_ring->l2_accel); | |
433 | ||
434 | /* check to see if DGLORT belongs to a MACVLAN */ | |
435 | if (l2_accel) { | |
436 | u16 idx = le16_to_cpu(FM10K_CB(skb)->fi.w.dglort) - 1; | |
437 | ||
438 | idx -= l2_accel->dglort; | |
439 | if (idx < l2_accel->size && l2_accel->macvlan[idx]) | |
440 | dev = l2_accel->macvlan[idx]; | |
441 | else | |
442 | l2_accel = NULL; | |
443 | } | |
444 | ||
445 | skb->protocol = eth_type_trans(skb, dev); | |
446 | ||
447 | if (!l2_accel) | |
448 | return; | |
449 | ||
450 | /* update MACVLAN statistics */ | |
451 | macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, 1, | |
452 | !!(rx_desc->w.hdr_info & | |
453 | cpu_to_le16(FM10K_RXD_HDR_INFO_XC_MASK))); | |
454 | } | |
455 | ||
b101c962 AD |
456 | /** |
457 | * fm10k_process_skb_fields - Populate skb header fields from Rx descriptor | |
458 | * @rx_ring: rx descriptor ring packet is being transacted on | |
459 | * @rx_desc: pointer to the EOP Rx descriptor | |
460 | * @skb: pointer to current skb being populated | |
461 | * | |
462 | * This function checks the ring, descriptor, and packet information in | |
463 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
464 | * other fields within the skb. | |
465 | **/ | |
466 | static unsigned int fm10k_process_skb_fields(struct fm10k_ring *rx_ring, | |
467 | union fm10k_rx_desc *rx_desc, | |
468 | struct sk_buff *skb) | |
469 | { | |
470 | unsigned int len = skb->len; | |
471 | ||
76a540d4 AD |
472 | fm10k_rx_hash(rx_ring, rx_desc, skb); |
473 | ||
474 | fm10k_rx_checksum(rx_ring, rx_desc, skb); | |
475 | ||
b101c962 AD |
476 | FM10K_CB(skb)->fi.w.vlan = rx_desc->w.vlan; |
477 | ||
478 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
479 | ||
480 | FM10K_CB(skb)->fi.d.glort = rx_desc->d.glort; | |
481 | ||
482 | if (rx_desc->w.vlan) { | |
483 | u16 vid = le16_to_cpu(rx_desc->w.vlan); | |
484 | ||
e71c9318 | 485 | if ((vid & VLAN_VID_MASK) != rx_ring->vid) |
b101c962 | 486 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
e71c9318 JK |
487 | else if (vid & VLAN_PRIO_MASK) |
488 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
489 | vid & VLAN_PRIO_MASK); | |
b101c962 AD |
490 | } |
491 | ||
5cd5e2e9 | 492 | fm10k_type_trans(rx_ring, rx_desc, skb); |
b101c962 AD |
493 | |
494 | return len; | |
495 | } | |
496 | ||
497 | /** | |
498 | * fm10k_is_non_eop - process handling of non-EOP buffers | |
499 | * @rx_ring: Rx ring being processed | |
500 | * @rx_desc: Rx descriptor for current buffer | |
501 | * | |
502 | * This function updates next to clean. If the buffer is an EOP buffer | |
503 | * this function exits returning false, otherwise it will place the | |
504 | * sk_buff in the next buffer to be chained and return true indicating | |
505 | * that this is in fact a non-EOP buffer. | |
506 | **/ | |
507 | static bool fm10k_is_non_eop(struct fm10k_ring *rx_ring, | |
508 | union fm10k_rx_desc *rx_desc) | |
509 | { | |
510 | u32 ntc = rx_ring->next_to_clean + 1; | |
511 | ||
512 | /* fetch, update, and store next to clean */ | |
513 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
514 | rx_ring->next_to_clean = ntc; | |
515 | ||
516 | prefetch(FM10K_RX_DESC(rx_ring, ntc)); | |
517 | ||
518 | if (likely(fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_EOP))) | |
519 | return false; | |
520 | ||
521 | return true; | |
522 | } | |
523 | ||
b101c962 AD |
524 | /** |
525 | * fm10k_cleanup_headers - Correct corrupted or empty headers | |
526 | * @rx_ring: rx descriptor ring packet is being transacted on | |
527 | * @rx_desc: pointer to the EOP Rx descriptor | |
528 | * @skb: pointer to current skb being fixed | |
529 | * | |
530 | * Address the case where we are pulling data in on pages only | |
531 | * and as such no data is present in the skb header. | |
532 | * | |
533 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
534 | * it is large enough to qualify as a valid Ethernet frame. | |
535 | * | |
536 | * Returns true if an error was encountered and skb was freed. | |
537 | **/ | |
538 | static bool fm10k_cleanup_headers(struct fm10k_ring *rx_ring, | |
539 | union fm10k_rx_desc *rx_desc, | |
540 | struct sk_buff *skb) | |
541 | { | |
542 | if (unlikely((fm10k_test_staterr(rx_desc, | |
543 | FM10K_RXD_STATUS_RXE)))) { | |
80043f3b JK |
544 | #define FM10K_TEST_RXD_BIT(rxd, bit) \ |
545 | ((rxd)->w.csum_err & cpu_to_le16(bit)) | |
546 | if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_ERROR)) | |
547 | rx_ring->rx_stats.switch_errors++; | |
548 | if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_NO_DESCRIPTOR)) | |
549 | rx_ring->rx_stats.drops++; | |
550 | if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_PP_ERROR)) | |
551 | rx_ring->rx_stats.pp_errors++; | |
552 | if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_READY)) | |
553 | rx_ring->rx_stats.link_errors++; | |
554 | if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_TOO_BIG)) | |
555 | rx_ring->rx_stats.length_errors++; | |
b101c962 AD |
556 | dev_kfree_skb_any(skb); |
557 | rx_ring->rx_stats.errors++; | |
558 | return true; | |
559 | } | |
560 | ||
a94d9e22 AD |
561 | /* if eth_skb_pad returns an error the skb was freed */ |
562 | if (eth_skb_pad(skb)) | |
563 | return true; | |
b101c962 AD |
564 | |
565 | return false; | |
566 | } | |
567 | ||
568 | /** | |
569 | * fm10k_receive_skb - helper function to handle rx indications | |
570 | * @q_vector: structure containing interrupt and ring information | |
571 | * @skb: packet to send up | |
572 | **/ | |
573 | static void fm10k_receive_skb(struct fm10k_q_vector *q_vector, | |
574 | struct sk_buff *skb) | |
575 | { | |
576 | napi_gro_receive(&q_vector->napi, skb); | |
577 | } | |
578 | ||
32b3e08f JB |
579 | static int fm10k_clean_rx_irq(struct fm10k_q_vector *q_vector, |
580 | struct fm10k_ring *rx_ring, | |
581 | int budget) | |
b101c962 AD |
582 | { |
583 | struct sk_buff *skb = rx_ring->skb; | |
584 | unsigned int total_bytes = 0, total_packets = 0; | |
585 | u16 cleaned_count = fm10k_desc_unused(rx_ring); | |
586 | ||
59486329 | 587 | while (likely(total_packets < budget)) { |
b101c962 AD |
588 | union fm10k_rx_desc *rx_desc; |
589 | ||
590 | /* return some buffers to hardware, one at a time is too slow */ | |
591 | if (cleaned_count >= FM10K_RX_BUFFER_WRITE) { | |
592 | fm10k_alloc_rx_buffers(rx_ring, cleaned_count); | |
593 | cleaned_count = 0; | |
594 | } | |
595 | ||
596 | rx_desc = FM10K_RX_DESC(rx_ring, rx_ring->next_to_clean); | |
597 | ||
124b74c1 | 598 | if (!rx_desc->d.staterr) |
b101c962 AD |
599 | break; |
600 | ||
601 | /* This memory barrier is needed to keep us from reading | |
602 | * any other fields out of the rx_desc until we know the | |
124b74c1 | 603 | * descriptor has been written back |
b101c962 | 604 | */ |
124b74c1 | 605 | dma_rmb(); |
b101c962 AD |
606 | |
607 | /* retrieve a buffer from the ring */ | |
608 | skb = fm10k_fetch_rx_buffer(rx_ring, rx_desc, skb); | |
609 | ||
610 | /* exit if we failed to retrieve a buffer */ | |
611 | if (!skb) | |
612 | break; | |
613 | ||
614 | cleaned_count++; | |
615 | ||
616 | /* fetch next buffer in frame if non-eop */ | |
617 | if (fm10k_is_non_eop(rx_ring, rx_desc)) | |
618 | continue; | |
619 | ||
620 | /* verify the packet layout is correct */ | |
621 | if (fm10k_cleanup_headers(rx_ring, rx_desc, skb)) { | |
622 | skb = NULL; | |
623 | continue; | |
624 | } | |
625 | ||
626 | /* populate checksum, timestamp, VLAN, and protocol */ | |
627 | total_bytes += fm10k_process_skb_fields(rx_ring, rx_desc, skb); | |
628 | ||
629 | fm10k_receive_skb(q_vector, skb); | |
630 | ||
631 | /* reset skb pointer */ | |
632 | skb = NULL; | |
633 | ||
634 | /* update budget accounting */ | |
635 | total_packets++; | |
59486329 | 636 | } |
b101c962 AD |
637 | |
638 | /* place incomplete frames back on ring for completion */ | |
639 | rx_ring->skb = skb; | |
640 | ||
641 | u64_stats_update_begin(&rx_ring->syncp); | |
642 | rx_ring->stats.packets += total_packets; | |
643 | rx_ring->stats.bytes += total_bytes; | |
644 | u64_stats_update_end(&rx_ring->syncp); | |
645 | q_vector->rx.total_packets += total_packets; | |
646 | q_vector->rx.total_bytes += total_bytes; | |
647 | ||
32b3e08f | 648 | return total_packets; |
b101c962 AD |
649 | } |
650 | ||
76a540d4 AD |
651 | #define VXLAN_HLEN (sizeof(struct udphdr) + 8) |
652 | static struct ethhdr *fm10k_port_is_vxlan(struct sk_buff *skb) | |
653 | { | |
654 | struct fm10k_intfc *interface = netdev_priv(skb->dev); | |
655 | struct fm10k_vxlan_port *vxlan_port; | |
656 | ||
657 | /* we can only offload a vxlan if we recognize it as such */ | |
658 | vxlan_port = list_first_entry_or_null(&interface->vxlan_port, | |
659 | struct fm10k_vxlan_port, list); | |
660 | ||
661 | if (!vxlan_port) | |
662 | return NULL; | |
663 | if (vxlan_port->port != udp_hdr(skb)->dest) | |
664 | return NULL; | |
665 | ||
666 | /* return offset of udp_hdr plus 8 bytes for VXLAN header */ | |
667 | return (struct ethhdr *)(skb_transport_header(skb) + VXLAN_HLEN); | |
668 | } | |
669 | ||
670 | #define FM10K_NVGRE_RESERVED0_FLAGS htons(0x9FFF) | |
671 | #define NVGRE_TNI htons(0x2000) | |
672 | struct fm10k_nvgre_hdr { | |
673 | __be16 flags; | |
674 | __be16 proto; | |
675 | __be32 tni; | |
676 | }; | |
677 | ||
678 | static struct ethhdr *fm10k_gre_is_nvgre(struct sk_buff *skb) | |
679 | { | |
680 | struct fm10k_nvgre_hdr *nvgre_hdr; | |
681 | int hlen = ip_hdrlen(skb); | |
682 | ||
683 | /* currently only IPv4 is supported due to hlen above */ | |
684 | if (vlan_get_protocol(skb) != htons(ETH_P_IP)) | |
685 | return NULL; | |
686 | ||
687 | /* our transport header should be NVGRE */ | |
688 | nvgre_hdr = (struct fm10k_nvgre_hdr *)(skb_network_header(skb) + hlen); | |
689 | ||
690 | /* verify all reserved flags are 0 */ | |
691 | if (nvgre_hdr->flags & FM10K_NVGRE_RESERVED0_FLAGS) | |
692 | return NULL; | |
693 | ||
76a540d4 AD |
694 | /* report start of ethernet header */ |
695 | if (nvgre_hdr->flags & NVGRE_TNI) | |
696 | return (struct ethhdr *)(nvgre_hdr + 1); | |
697 | ||
698 | return (struct ethhdr *)(&nvgre_hdr->tni); | |
699 | } | |
700 | ||
5bf33dc6 | 701 | __be16 fm10k_tx_encap_offload(struct sk_buff *skb) |
76a540d4 | 702 | { |
8c1a90aa | 703 | u8 l4_hdr = 0, inner_l4_hdr = 0, inner_l4_hlen; |
76a540d4 | 704 | struct ethhdr *eth_hdr; |
76a540d4 | 705 | |
8c1a90aa MV |
706 | if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || |
707 | skb->inner_protocol != htons(ETH_P_TEB)) | |
b66b6d9f JS |
708 | return 0; |
709 | ||
76a540d4 AD |
710 | switch (vlan_get_protocol(skb)) { |
711 | case htons(ETH_P_IP): | |
712 | l4_hdr = ip_hdr(skb)->protocol; | |
713 | break; | |
714 | case htons(ETH_P_IPV6): | |
715 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
716 | break; | |
717 | default: | |
718 | return 0; | |
719 | } | |
720 | ||
721 | switch (l4_hdr) { | |
722 | case IPPROTO_UDP: | |
723 | eth_hdr = fm10k_port_is_vxlan(skb); | |
724 | break; | |
725 | case IPPROTO_GRE: | |
726 | eth_hdr = fm10k_gre_is_nvgre(skb); | |
727 | break; | |
728 | default: | |
729 | return 0; | |
730 | } | |
731 | ||
732 | if (!eth_hdr) | |
733 | return 0; | |
734 | ||
735 | switch (eth_hdr->h_proto) { | |
736 | case htons(ETH_P_IP): | |
8c1a90aa MV |
737 | inner_l4_hdr = inner_ip_hdr(skb)->protocol; |
738 | break; | |
76a540d4 | 739 | case htons(ETH_P_IPV6): |
8c1a90aa | 740 | inner_l4_hdr = inner_ipv6_hdr(skb)->nexthdr; |
76a540d4 AD |
741 | break; |
742 | default: | |
743 | return 0; | |
744 | } | |
745 | ||
8c1a90aa MV |
746 | switch (inner_l4_hdr) { |
747 | case IPPROTO_TCP: | |
748 | inner_l4_hlen = inner_tcp_hdrlen(skb); | |
749 | break; | |
750 | case IPPROTO_UDP: | |
751 | inner_l4_hlen = 8; | |
752 | break; | |
753 | default: | |
754 | return 0; | |
755 | } | |
756 | ||
757 | /* The hardware allows tunnel offloads only if the combined inner and | |
758 | * outer header is 184 bytes or less | |
759 | */ | |
760 | if (skb_inner_transport_header(skb) + inner_l4_hlen - | |
761 | skb_mac_header(skb) > FM10K_TUNNEL_HEADER_LENGTH) | |
762 | return 0; | |
763 | ||
76a540d4 AD |
764 | return eth_hdr->h_proto; |
765 | } | |
766 | ||
767 | static int fm10k_tso(struct fm10k_ring *tx_ring, | |
768 | struct fm10k_tx_buffer *first) | |
769 | { | |
770 | struct sk_buff *skb = first->skb; | |
771 | struct fm10k_tx_desc *tx_desc; | |
772 | unsigned char *th; | |
773 | u8 hdrlen; | |
774 | ||
775 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
776 | return 0; | |
777 | ||
778 | if (!skb_is_gso(skb)) | |
779 | return 0; | |
780 | ||
781 | /* compute header lengths */ | |
782 | if (skb->encapsulation) { | |
783 | if (!fm10k_tx_encap_offload(skb)) | |
784 | goto err_vxlan; | |
785 | th = skb_inner_transport_header(skb); | |
786 | } else { | |
787 | th = skb_transport_header(skb); | |
788 | } | |
789 | ||
790 | /* compute offset from SOF to transport header and add header len */ | |
791 | hdrlen = (th - skb->data) + (((struct tcphdr *)th)->doff << 2); | |
792 | ||
793 | first->tx_flags |= FM10K_TX_FLAGS_CSUM; | |
794 | ||
795 | /* update gso size and bytecount with header size */ | |
796 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
797 | first->bytecount += (first->gso_segs - 1) * hdrlen; | |
798 | ||
799 | /* populate Tx descriptor header size and mss */ | |
800 | tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); | |
801 | tx_desc->hdrlen = hdrlen; | |
802 | tx_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size); | |
803 | ||
804 | return 1; | |
805 | err_vxlan: | |
806 | tx_ring->netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL; | |
807 | if (!net_ratelimit()) | |
808 | netdev_err(tx_ring->netdev, | |
809 | "TSO requested for unsupported tunnel, disabling offload\n"); | |
810 | return -1; | |
811 | } | |
812 | ||
813 | static void fm10k_tx_csum(struct fm10k_ring *tx_ring, | |
814 | struct fm10k_tx_buffer *first) | |
815 | { | |
816 | struct sk_buff *skb = first->skb; | |
817 | struct fm10k_tx_desc *tx_desc; | |
818 | union { | |
819 | struct iphdr *ipv4; | |
820 | struct ipv6hdr *ipv6; | |
821 | u8 *raw; | |
822 | } network_hdr; | |
823 | __be16 protocol; | |
824 | u8 l4_hdr = 0; | |
825 | ||
826 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
827 | goto no_csum; | |
828 | ||
829 | if (skb->encapsulation) { | |
830 | protocol = fm10k_tx_encap_offload(skb); | |
831 | if (!protocol) { | |
832 | if (skb_checksum_help(skb)) { | |
833 | dev_warn(tx_ring->dev, | |
834 | "failed to offload encap csum!\n"); | |
835 | tx_ring->tx_stats.csum_err++; | |
836 | } | |
837 | goto no_csum; | |
838 | } | |
839 | network_hdr.raw = skb_inner_network_header(skb); | |
840 | } else { | |
841 | protocol = vlan_get_protocol(skb); | |
842 | network_hdr.raw = skb_network_header(skb); | |
843 | } | |
844 | ||
845 | switch (protocol) { | |
846 | case htons(ETH_P_IP): | |
847 | l4_hdr = network_hdr.ipv4->protocol; | |
848 | break; | |
849 | case htons(ETH_P_IPV6): | |
850 | l4_hdr = network_hdr.ipv6->nexthdr; | |
851 | break; | |
852 | default: | |
853 | if (unlikely(net_ratelimit())) { | |
854 | dev_warn(tx_ring->dev, | |
855 | "partial checksum but ip version=%x!\n", | |
856 | protocol); | |
857 | } | |
858 | tx_ring->tx_stats.csum_err++; | |
859 | goto no_csum; | |
860 | } | |
861 | ||
862 | switch (l4_hdr) { | |
863 | case IPPROTO_TCP: | |
864 | case IPPROTO_UDP: | |
865 | break; | |
866 | case IPPROTO_GRE: | |
867 | if (skb->encapsulation) | |
868 | break; | |
869 | default: | |
870 | if (unlikely(net_ratelimit())) { | |
871 | dev_warn(tx_ring->dev, | |
872 | "partial checksum but l4 proto=%x!\n", | |
873 | l4_hdr); | |
874 | } | |
875 | tx_ring->tx_stats.csum_err++; | |
876 | goto no_csum; | |
877 | } | |
878 | ||
879 | /* update TX checksum flag */ | |
880 | first->tx_flags |= FM10K_TX_FLAGS_CSUM; | |
80043f3b | 881 | tx_ring->tx_stats.csum_good++; |
76a540d4 AD |
882 | |
883 | no_csum: | |
884 | /* populate Tx descriptor header size and mss */ | |
885 | tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use); | |
886 | tx_desc->hdrlen = 0; | |
887 | tx_desc->mss = 0; | |
888 | } | |
889 | ||
890 | #define FM10K_SET_FLAG(_input, _flag, _result) \ | |
891 | ((_flag <= _result) ? \ | |
892 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
893 | ((u32)(_input & _flag) / (_flag / _result))) | |
894 | ||
895 | static u8 fm10k_tx_desc_flags(struct sk_buff *skb, u32 tx_flags) | |
896 | { | |
897 | /* set type for advanced descriptor with frame checksum insertion */ | |
898 | u32 desc_flags = 0; | |
899 | ||
900 | /* set checksum offload bits */ | |
901 | desc_flags |= FM10K_SET_FLAG(tx_flags, FM10K_TX_FLAGS_CSUM, | |
902 | FM10K_TXD_FLAG_CSUM); | |
903 | ||
904 | return desc_flags; | |
905 | } | |
906 | ||
b101c962 AD |
907 | static bool fm10k_tx_desc_push(struct fm10k_ring *tx_ring, |
908 | struct fm10k_tx_desc *tx_desc, u16 i, | |
909 | dma_addr_t dma, unsigned int size, u8 desc_flags) | |
910 | { | |
911 | /* set RS and INT for last frame in a cache line */ | |
912 | if ((++i & (FM10K_TXD_WB_FIFO_SIZE - 1)) == 0) | |
913 | desc_flags |= FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_INT; | |
914 | ||
915 | /* record values to descriptor */ | |
916 | tx_desc->buffer_addr = cpu_to_le64(dma); | |
917 | tx_desc->flags = desc_flags; | |
918 | tx_desc->buflen = cpu_to_le16(size); | |
919 | ||
920 | /* return true if we just wrapped the ring */ | |
921 | return i == tx_ring->count; | |
922 | } | |
923 | ||
2c2b2f0c AD |
924 | static int __fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) |
925 | { | |
926 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
927 | ||
eca32047 | 928 | /* Memory barrier before checking head and tail */ |
2c2b2f0c AD |
929 | smp_mb(); |
930 | ||
eca32047 | 931 | /* Check again in a case another CPU has just made room available */ |
2c2b2f0c AD |
932 | if (likely(fm10k_desc_unused(tx_ring) < size)) |
933 | return -EBUSY; | |
934 | ||
935 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
936 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
937 | ++tx_ring->tx_stats.restart_queue; | |
938 | return 0; | |
939 | } | |
940 | ||
941 | static inline int fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size) | |
942 | { | |
943 | if (likely(fm10k_desc_unused(tx_ring) >= size)) | |
944 | return 0; | |
945 | return __fm10k_maybe_stop_tx(tx_ring, size); | |
946 | } | |
947 | ||
b101c962 AD |
948 | static void fm10k_tx_map(struct fm10k_ring *tx_ring, |
949 | struct fm10k_tx_buffer *first) | |
950 | { | |
951 | struct sk_buff *skb = first->skb; | |
952 | struct fm10k_tx_buffer *tx_buffer; | |
953 | struct fm10k_tx_desc *tx_desc; | |
954 | struct skb_frag_struct *frag; | |
955 | unsigned char *data; | |
956 | dma_addr_t dma; | |
957 | unsigned int data_len, size; | |
76a540d4 | 958 | u32 tx_flags = first->tx_flags; |
b101c962 | 959 | u16 i = tx_ring->next_to_use; |
76a540d4 | 960 | u8 flags = fm10k_tx_desc_flags(skb, tx_flags); |
b101c962 AD |
961 | |
962 | tx_desc = FM10K_TX_DESC(tx_ring, i); | |
963 | ||
964 | /* add HW VLAN tag */ | |
df8a39de JP |
965 | if (skb_vlan_tag_present(skb)) |
966 | tx_desc->vlan = cpu_to_le16(skb_vlan_tag_get(skb)); | |
b101c962 AD |
967 | else |
968 | tx_desc->vlan = 0; | |
969 | ||
970 | size = skb_headlen(skb); | |
971 | data = skb->data; | |
972 | ||
973 | dma = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE); | |
974 | ||
975 | data_len = skb->data_len; | |
976 | tx_buffer = first; | |
977 | ||
978 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
979 | if (dma_mapping_error(tx_ring->dev, dma)) | |
980 | goto dma_error; | |
981 | ||
982 | /* record length, and DMA address */ | |
983 | dma_unmap_len_set(tx_buffer, len, size); | |
984 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
985 | ||
986 | while (unlikely(size > FM10K_MAX_DATA_PER_TXD)) { | |
987 | if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, dma, | |
988 | FM10K_MAX_DATA_PER_TXD, flags)) { | |
989 | tx_desc = FM10K_TX_DESC(tx_ring, 0); | |
990 | i = 0; | |
991 | } | |
992 | ||
993 | dma += FM10K_MAX_DATA_PER_TXD; | |
994 | size -= FM10K_MAX_DATA_PER_TXD; | |
995 | } | |
996 | ||
997 | if (likely(!data_len)) | |
998 | break; | |
999 | ||
1000 | if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, | |
1001 | dma, size, flags)) { | |
1002 | tx_desc = FM10K_TX_DESC(tx_ring, 0); | |
1003 | i = 0; | |
1004 | } | |
1005 | ||
1006 | size = skb_frag_size(frag); | |
1007 | data_len -= size; | |
1008 | ||
1009 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
1010 | DMA_TO_DEVICE); | |
1011 | ||
1012 | tx_buffer = &tx_ring->tx_buffer[i]; | |
1013 | } | |
1014 | ||
1015 | /* write last descriptor with LAST bit set */ | |
1016 | flags |= FM10K_TXD_FLAG_LAST; | |
1017 | ||
1018 | if (fm10k_tx_desc_push(tx_ring, tx_desc, i++, dma, size, flags)) | |
1019 | i = 0; | |
1020 | ||
1021 | /* record bytecount for BQL */ | |
1022 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); | |
1023 | ||
1024 | /* record SW timestamp if HW timestamp is not available */ | |
1025 | skb_tx_timestamp(first->skb); | |
1026 | ||
1027 | /* Force memory writes to complete before letting h/w know there | |
1028 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
1029 | * memory model archs, such as IA-64). | |
1030 | * | |
1031 | * We also need this memory barrier to make certain all of the | |
1032 | * status bits have been updated before next_to_watch is written. | |
1033 | */ | |
1034 | wmb(); | |
1035 | ||
1036 | /* set next_to_watch value indicating a packet is present */ | |
1037 | first->next_to_watch = tx_desc; | |
1038 | ||
1039 | tx_ring->next_to_use = i; | |
1040 | ||
2c2b2f0c AD |
1041 | /* Make sure there is space in the ring for the next send. */ |
1042 | fm10k_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
1043 | ||
b101c962 | 1044 | /* notify HW of packet */ |
2c2b2f0c AD |
1045 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { |
1046 | writel(i, tx_ring->tail); | |
b101c962 | 1047 | |
2c2b2f0c AD |
1048 | /* we need this if more than one processor can write to our tail |
1049 | * at a time, it synchronizes IO on IA64/Altix systems | |
1050 | */ | |
1051 | mmiowb(); | |
1052 | } | |
b101c962 AD |
1053 | |
1054 | return; | |
1055 | dma_error: | |
1056 | dev_err(tx_ring->dev, "TX DMA map failed\n"); | |
1057 | ||
1058 | /* clear dma mappings for failed tx_buffer map */ | |
1059 | for (;;) { | |
1060 | tx_buffer = &tx_ring->tx_buffer[i]; | |
1061 | fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
1062 | if (tx_buffer == first) | |
1063 | break; | |
1064 | if (i == 0) | |
1065 | i = tx_ring->count; | |
1066 | i--; | |
1067 | } | |
1068 | ||
1069 | tx_ring->next_to_use = i; | |
1070 | } | |
1071 | ||
b101c962 AD |
1072 | netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb, |
1073 | struct fm10k_ring *tx_ring) | |
1074 | { | |
03d13a51 | 1075 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
b101c962 | 1076 | struct fm10k_tx_buffer *first; |
b101c962 | 1077 | unsigned short f; |
03d13a51 JK |
1078 | u32 tx_flags = 0; |
1079 | int tso; | |
b101c962 AD |
1080 | |
1081 | /* need: 1 descriptor per page * PAGE_SIZE/FM10K_MAX_DATA_PER_TXD, | |
1082 | * + 1 desc for skb_headlen/FM10K_MAX_DATA_PER_TXD, | |
1083 | * + 2 desc gap to keep tail from touching head | |
1084 | * otherwise try next time | |
1085 | */ | |
b101c962 AD |
1086 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
1087 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
aae072e3 | 1088 | |
b101c962 AD |
1089 | if (fm10k_maybe_stop_tx(tx_ring, count + 3)) { |
1090 | tx_ring->tx_stats.tx_busy++; | |
1091 | return NETDEV_TX_BUSY; | |
1092 | } | |
1093 | ||
1094 | /* record the location of the first descriptor for this packet */ | |
1095 | first = &tx_ring->tx_buffer[tx_ring->next_to_use]; | |
1096 | first->skb = skb; | |
1097 | first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN); | |
1098 | first->gso_segs = 1; | |
1099 | ||
1100 | /* record initial flags and protocol */ | |
1101 | first->tx_flags = tx_flags; | |
1102 | ||
76a540d4 AD |
1103 | tso = fm10k_tso(tx_ring, first); |
1104 | if (tso < 0) | |
1105 | goto out_drop; | |
1106 | else if (!tso) | |
1107 | fm10k_tx_csum(tx_ring, first); | |
1108 | ||
b101c962 AD |
1109 | fm10k_tx_map(tx_ring, first); |
1110 | ||
76a540d4 AD |
1111 | return NETDEV_TX_OK; |
1112 | ||
1113 | out_drop: | |
1114 | dev_kfree_skb_any(first->skb); | |
1115 | first->skb = NULL; | |
1116 | ||
b101c962 AD |
1117 | return NETDEV_TX_OK; |
1118 | } | |
1119 | ||
1120 | static u64 fm10k_get_tx_completed(struct fm10k_ring *ring) | |
1121 | { | |
1122 | return ring->stats.packets; | |
1123 | } | |
1124 | ||
1125 | static u64 fm10k_get_tx_pending(struct fm10k_ring *ring) | |
1126 | { | |
1127 | /* use SW head and tail until we have real hardware */ | |
1128 | u32 head = ring->next_to_clean; | |
1129 | u32 tail = ring->next_to_use; | |
1130 | ||
1131 | return ((head <= tail) ? tail : tail + ring->count) - head; | |
1132 | } | |
1133 | ||
1134 | bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring) | |
1135 | { | |
1136 | u32 tx_done = fm10k_get_tx_completed(tx_ring); | |
1137 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
1138 | u32 tx_pending = fm10k_get_tx_pending(tx_ring); | |
1139 | ||
1140 | clear_check_for_tx_hang(tx_ring); | |
1141 | ||
1142 | /* Check for a hung queue, but be thorough. This verifies | |
1143 | * that a transmit has been completed since the previous | |
1144 | * check AND there is at least one packet pending. By | |
1145 | * requiring this to fail twice we avoid races with | |
1146 | * clearing the ARMED bit and conditions where we | |
1147 | * run the check_tx_hang logic with a transmit completion | |
1148 | * pending but without time to complete it yet. | |
1149 | */ | |
1150 | if (!tx_pending || (tx_done_old != tx_done)) { | |
1151 | /* update completed stats and continue */ | |
1152 | tx_ring->tx_stats.tx_done_old = tx_done; | |
1153 | /* reset the countdown */ | |
1154 | clear_bit(__FM10K_HANG_CHECK_ARMED, &tx_ring->state); | |
1155 | ||
1156 | return false; | |
1157 | } | |
1158 | ||
1159 | /* make sure it is true for two checks in a row */ | |
1160 | return test_and_set_bit(__FM10K_HANG_CHECK_ARMED, &tx_ring->state); | |
1161 | } | |
1162 | ||
1163 | /** | |
1164 | * fm10k_tx_timeout_reset - initiate reset due to Tx timeout | |
1165 | * @interface: driver private struct | |
1166 | **/ | |
1167 | void fm10k_tx_timeout_reset(struct fm10k_intfc *interface) | |
1168 | { | |
1169 | /* Do the reset outside of interrupt context */ | |
1170 | if (!test_bit(__FM10K_DOWN, &interface->state)) { | |
b101c962 AD |
1171 | interface->tx_timeout_count++; |
1172 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
1173 | fm10k_service_event_schedule(interface); | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * fm10k_clean_tx_irq - Reclaim resources after transmit completes | |
1179 | * @q_vector: structure containing interrupt and ring information | |
1180 | * @tx_ring: tx ring to clean | |
144d8305 | 1181 | * @napi_budget: Used to determine if we are in netpoll |
b101c962 AD |
1182 | **/ |
1183 | static bool fm10k_clean_tx_irq(struct fm10k_q_vector *q_vector, | |
144d8305 | 1184 | struct fm10k_ring *tx_ring, int napi_budget) |
b101c962 AD |
1185 | { |
1186 | struct fm10k_intfc *interface = q_vector->interface; | |
1187 | struct fm10k_tx_buffer *tx_buffer; | |
1188 | struct fm10k_tx_desc *tx_desc; | |
1189 | unsigned int total_bytes = 0, total_packets = 0; | |
1190 | unsigned int budget = q_vector->tx.work_limit; | |
1191 | unsigned int i = tx_ring->next_to_clean; | |
1192 | ||
1193 | if (test_bit(__FM10K_DOWN, &interface->state)) | |
1194 | return true; | |
1195 | ||
1196 | tx_buffer = &tx_ring->tx_buffer[i]; | |
1197 | tx_desc = FM10K_TX_DESC(tx_ring, i); | |
1198 | i -= tx_ring->count; | |
1199 | ||
1200 | do { | |
1201 | struct fm10k_tx_desc *eop_desc = tx_buffer->next_to_watch; | |
1202 | ||
1203 | /* if next_to_watch is not set then there is no work pending */ | |
1204 | if (!eop_desc) | |
1205 | break; | |
1206 | ||
1207 | /* prevent any other reads prior to eop_desc */ | |
1208 | read_barrier_depends(); | |
1209 | ||
1210 | /* if DD is not set pending work has not been completed */ | |
1211 | if (!(eop_desc->flags & FM10K_TXD_FLAG_DONE)) | |
1212 | break; | |
1213 | ||
1214 | /* clear next_to_watch to prevent false hangs */ | |
1215 | tx_buffer->next_to_watch = NULL; | |
1216 | ||
1217 | /* update the statistics for this packet */ | |
1218 | total_bytes += tx_buffer->bytecount; | |
1219 | total_packets += tx_buffer->gso_segs; | |
1220 | ||
1221 | /* free the skb */ | |
144d8305 | 1222 | napi_consume_skb(tx_buffer->skb, napi_budget); |
b101c962 AD |
1223 | |
1224 | /* unmap skb header data */ | |
1225 | dma_unmap_single(tx_ring->dev, | |
1226 | dma_unmap_addr(tx_buffer, dma), | |
1227 | dma_unmap_len(tx_buffer, len), | |
1228 | DMA_TO_DEVICE); | |
1229 | ||
1230 | /* clear tx_buffer data */ | |
1231 | tx_buffer->skb = NULL; | |
1232 | dma_unmap_len_set(tx_buffer, len, 0); | |
1233 | ||
1234 | /* unmap remaining buffers */ | |
1235 | while (tx_desc != eop_desc) { | |
1236 | tx_buffer++; | |
1237 | tx_desc++; | |
1238 | i++; | |
1239 | if (unlikely(!i)) { | |
1240 | i -= tx_ring->count; | |
1241 | tx_buffer = tx_ring->tx_buffer; | |
1242 | tx_desc = FM10K_TX_DESC(tx_ring, 0); | |
1243 | } | |
1244 | ||
1245 | /* unmap any remaining paged data */ | |
1246 | if (dma_unmap_len(tx_buffer, len)) { | |
1247 | dma_unmap_page(tx_ring->dev, | |
1248 | dma_unmap_addr(tx_buffer, dma), | |
1249 | dma_unmap_len(tx_buffer, len), | |
1250 | DMA_TO_DEVICE); | |
1251 | dma_unmap_len_set(tx_buffer, len, 0); | |
1252 | } | |
1253 | } | |
1254 | ||
1255 | /* move us one more past the eop_desc for start of next pkt */ | |
1256 | tx_buffer++; | |
1257 | tx_desc++; | |
1258 | i++; | |
1259 | if (unlikely(!i)) { | |
1260 | i -= tx_ring->count; | |
1261 | tx_buffer = tx_ring->tx_buffer; | |
1262 | tx_desc = FM10K_TX_DESC(tx_ring, 0); | |
1263 | } | |
1264 | ||
1265 | /* issue prefetch for next Tx descriptor */ | |
1266 | prefetch(tx_desc); | |
1267 | ||
1268 | /* update budget accounting */ | |
1269 | budget--; | |
1270 | } while (likely(budget)); | |
1271 | ||
1272 | i += tx_ring->count; | |
1273 | tx_ring->next_to_clean = i; | |
1274 | u64_stats_update_begin(&tx_ring->syncp); | |
1275 | tx_ring->stats.bytes += total_bytes; | |
1276 | tx_ring->stats.packets += total_packets; | |
1277 | u64_stats_update_end(&tx_ring->syncp); | |
1278 | q_vector->tx.total_bytes += total_bytes; | |
1279 | q_vector->tx.total_packets += total_packets; | |
1280 | ||
1281 | if (check_for_tx_hang(tx_ring) && fm10k_check_tx_hang(tx_ring)) { | |
1282 | /* schedule immediate reset if we believe we hung */ | |
1283 | struct fm10k_hw *hw = &interface->hw; | |
1284 | ||
1285 | netif_err(interface, drv, tx_ring->netdev, | |
1286 | "Detected Tx Unit Hang\n" | |
1287 | " Tx Queue <%d>\n" | |
1288 | " TDH, TDT <%x>, <%x>\n" | |
1289 | " next_to_use <%x>\n" | |
1290 | " next_to_clean <%x>\n", | |
1291 | tx_ring->queue_index, | |
1292 | fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)), | |
1293 | fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)), | |
1294 | tx_ring->next_to_use, i); | |
1295 | ||
1296 | netif_stop_subqueue(tx_ring->netdev, | |
1297 | tx_ring->queue_index); | |
1298 | ||
1299 | netif_info(interface, probe, tx_ring->netdev, | |
1300 | "tx hang %d detected on queue %d, resetting interface\n", | |
1301 | interface->tx_timeout_count + 1, | |
1302 | tx_ring->queue_index); | |
1303 | ||
1304 | fm10k_tx_timeout_reset(interface); | |
1305 | ||
1306 | /* the netdev is about to reset, no point in enabling stuff */ | |
1307 | return true; | |
1308 | } | |
1309 | ||
1310 | /* notify netdev of completed buffers */ | |
1311 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
1312 | total_packets, total_bytes); | |
1313 | ||
1314 | #define TX_WAKE_THRESHOLD min_t(u16, FM10K_MIN_TXD - 1, DESC_NEEDED * 2) | |
1315 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
1316 | (fm10k_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
1317 | /* Make sure that anybody stopping the queue after this | |
1318 | * sees the new next_to_clean. | |
1319 | */ | |
1320 | smp_mb(); | |
1321 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
1322 | tx_ring->queue_index) && | |
1323 | !test_bit(__FM10K_DOWN, &interface->state)) { | |
1324 | netif_wake_subqueue(tx_ring->netdev, | |
1325 | tx_ring->queue_index); | |
1326 | ++tx_ring->tx_stats.restart_queue; | |
1327 | } | |
1328 | } | |
1329 | ||
1330 | return !!budget; | |
1331 | } | |
1332 | ||
18283cad AD |
1333 | /** |
1334 | * fm10k_update_itr - update the dynamic ITR value based on packet size | |
1335 | * | |
1336 | * Stores a new ITR value based on strictly on packet size. The | |
1337 | * divisors and thresholds used by this function were determined based | |
1338 | * on theoretical maximum wire speed and testing data, in order to | |
1339 | * minimize response time while increasing bulk throughput. | |
1340 | * | |
1341 | * @ring_container: Container for rings to have ITR updated | |
1342 | **/ | |
1343 | static void fm10k_update_itr(struct fm10k_ring_container *ring_container) | |
1344 | { | |
242722dd | 1345 | unsigned int avg_wire_size, packets, itr_round; |
18283cad AD |
1346 | |
1347 | /* Only update ITR if we are using adaptive setting */ | |
584373f5 | 1348 | if (!ITR_IS_ADAPTIVE(ring_container->itr)) |
18283cad AD |
1349 | goto clear_counts; |
1350 | ||
1351 | packets = ring_container->total_packets; | |
1352 | if (!packets) | |
1353 | goto clear_counts; | |
1354 | ||
1355 | avg_wire_size = ring_container->total_bytes / packets; | |
1356 | ||
242722dd JK |
1357 | /* The following is a crude approximation of: |
1358 | * wmem_default / (size + overhead) = desired_pkts_per_int | |
1359 | * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate | |
1360 | * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value | |
1361 | * | |
1362 | * Assuming wmem_default is 212992 and overhead is 640 bytes per | |
1363 | * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the | |
1364 | * formula down to | |
1365 | * | |
1366 | * (34 * (size + 24)) / (size + 640) = ITR | |
1367 | * | |
1368 | * We first do some math on the packet size and then finally bitshift | |
1369 | * by 8 after rounding up. We also have to account for PCIe link speed | |
1370 | * difference as ITR scales based on this. | |
1371 | */ | |
1372 | if (avg_wire_size <= 360) { | |
1373 | /* Start at 250K ints/sec and gradually drop to 77K ints/sec */ | |
1374 | avg_wire_size *= 8; | |
1375 | avg_wire_size += 376; | |
1376 | } else if (avg_wire_size <= 1152) { | |
1377 | /* 77K ints/sec to 45K ints/sec */ | |
1378 | avg_wire_size *= 3; | |
1379 | avg_wire_size += 2176; | |
1380 | } else if (avg_wire_size <= 1920) { | |
1381 | /* 45K ints/sec to 38K ints/sec */ | |
1382 | avg_wire_size += 4480; | |
1383 | } else { | |
1384 | /* plateau at a limit of 38K ints/sec */ | |
1385 | avg_wire_size = 6656; | |
1386 | } | |
18283cad | 1387 | |
242722dd JK |
1388 | /* Perform final bitshift for division after rounding up to ensure |
1389 | * that the calculation will never get below a 1. The bit shift | |
1390 | * accounts for changes in the ITR due to PCIe link speed. | |
1391 | */ | |
1392 | itr_round = ACCESS_ONCE(ring_container->itr_scale) + 8; | |
fcdb0a99 | 1393 | avg_wire_size += BIT(itr_round) - 1; |
242722dd | 1394 | avg_wire_size >>= itr_round; |
18283cad AD |
1395 | |
1396 | /* write back value and retain adaptive flag */ | |
1397 | ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE; | |
1398 | ||
1399 | clear_counts: | |
1400 | ring_container->total_bytes = 0; | |
1401 | ring_container->total_packets = 0; | |
1402 | } | |
1403 | ||
1404 | static void fm10k_qv_enable(struct fm10k_q_vector *q_vector) | |
1405 | { | |
1406 | /* Enable auto-mask and clear the current mask */ | |
1407 | u32 itr = FM10K_ITR_ENABLE; | |
1408 | ||
1409 | /* Update Tx ITR */ | |
1410 | fm10k_update_itr(&q_vector->tx); | |
1411 | ||
1412 | /* Update Rx ITR */ | |
1413 | fm10k_update_itr(&q_vector->rx); | |
1414 | ||
1415 | /* Store Tx itr in timer slot 0 */ | |
1416 | itr |= (q_vector->tx.itr & FM10K_ITR_MAX); | |
1417 | ||
1418 | /* Shift Rx itr to timer slot 1 */ | |
1419 | itr |= (q_vector->rx.itr & FM10K_ITR_MAX) << FM10K_ITR_INTERVAL1_SHIFT; | |
1420 | ||
1421 | /* Write the final value to the ITR register */ | |
1422 | writel(itr, q_vector->itr); | |
1423 | } | |
1424 | ||
1425 | static int fm10k_poll(struct napi_struct *napi, int budget) | |
1426 | { | |
1427 | struct fm10k_q_vector *q_vector = | |
1428 | container_of(napi, struct fm10k_q_vector, napi); | |
b101c962 | 1429 | struct fm10k_ring *ring; |
32b3e08f | 1430 | int per_ring_budget, work_done = 0; |
b101c962 AD |
1431 | bool clean_complete = true; |
1432 | ||
144d8305 AD |
1433 | fm10k_for_each_ring(ring, q_vector->tx) { |
1434 | if (!fm10k_clean_tx_irq(q_vector, ring, budget)) | |
1435 | clean_complete = false; | |
1436 | } | |
b101c962 | 1437 | |
9f872986 AD |
1438 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1439 | if (budget <= 0) | |
1440 | return budget; | |
1441 | ||
b101c962 AD |
1442 | /* attempt to distribute budget to each queue fairly, but don't |
1443 | * allow the budget to go below 1 because we'll exit polling | |
1444 | */ | |
1445 | if (q_vector->rx.count > 1) | |
a4fcad65 | 1446 | per_ring_budget = max(budget / q_vector->rx.count, 1); |
b101c962 AD |
1447 | else |
1448 | per_ring_budget = budget; | |
1449 | ||
32b3e08f JB |
1450 | fm10k_for_each_ring(ring, q_vector->rx) { |
1451 | int work = fm10k_clean_rx_irq(q_vector, ring, per_ring_budget); | |
1452 | ||
1453 | work_done += work; | |
144d8305 AD |
1454 | if (work >= per_ring_budget) |
1455 | clean_complete = false; | |
32b3e08f | 1456 | } |
b101c962 AD |
1457 | |
1458 | /* If all work not completed, return budget and keep polling */ | |
1459 | if (!clean_complete) | |
1460 | return budget; | |
18283cad AD |
1461 | |
1462 | /* all work done, exit the polling mode */ | |
32b3e08f | 1463 | napi_complete_done(napi, work_done); |
18283cad AD |
1464 | |
1465 | /* re-enable the q_vector */ | |
1466 | fm10k_qv_enable(q_vector); | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | ||
aa3ac822 AD |
1471 | /** |
1472 | * fm10k_set_qos_queues: Allocate queues for a QOS-enabled device | |
1473 | * @interface: board private structure to initialize | |
1474 | * | |
1475 | * When QoS (Quality of Service) is enabled, allocate queues for | |
1476 | * each traffic class. If multiqueue isn't available,then abort QoS | |
1477 | * initialization. | |
1478 | * | |
1479 | * This function handles all combinations of Qos and RSS. | |
1480 | * | |
1481 | **/ | |
1482 | static bool fm10k_set_qos_queues(struct fm10k_intfc *interface) | |
1483 | { | |
1484 | struct net_device *dev = interface->netdev; | |
1485 | struct fm10k_ring_feature *f; | |
1486 | int rss_i, i; | |
1487 | int pcs; | |
1488 | ||
1489 | /* Map queue offset and counts onto allocated tx queues */ | |
1490 | pcs = netdev_get_num_tc(dev); | |
1491 | ||
1492 | if (pcs <= 1) | |
1493 | return false; | |
1494 | ||
1495 | /* set QoS mask and indices */ | |
1496 | f = &interface->ring_feature[RING_F_QOS]; | |
1497 | f->indices = pcs; | |
fcdb0a99 | 1498 | f->mask = BIT(fls(pcs - 1)) - 1; |
aa3ac822 AD |
1499 | |
1500 | /* determine the upper limit for our current DCB mode */ | |
1501 | rss_i = interface->hw.mac.max_queues / pcs; | |
fcdb0a99 | 1502 | rss_i = BIT(fls(rss_i) - 1); |
aa3ac822 AD |
1503 | |
1504 | /* set RSS mask and indices */ | |
1505 | f = &interface->ring_feature[RING_F_RSS]; | |
1506 | rss_i = min_t(u16, rss_i, f->limit); | |
1507 | f->indices = rss_i; | |
fcdb0a99 | 1508 | f->mask = BIT(fls(rss_i - 1)) - 1; |
aa3ac822 AD |
1509 | |
1510 | /* configure pause class to queue mapping */ | |
1511 | for (i = 0; i < pcs; i++) | |
1512 | netdev_set_tc_queue(dev, i, rss_i, rss_i * i); | |
1513 | ||
1514 | interface->num_rx_queues = rss_i * pcs; | |
1515 | interface->num_tx_queues = rss_i * pcs; | |
1516 | ||
1517 | return true; | |
1518 | } | |
1519 | ||
1520 | /** | |
1521 | * fm10k_set_rss_queues: Allocate queues for RSS | |
1522 | * @interface: board private structure to initialize | |
1523 | * | |
1524 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
1525 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
1526 | * | |
1527 | **/ | |
1528 | static bool fm10k_set_rss_queues(struct fm10k_intfc *interface) | |
1529 | { | |
1530 | struct fm10k_ring_feature *f; | |
1531 | u16 rss_i; | |
1532 | ||
1533 | f = &interface->ring_feature[RING_F_RSS]; | |
1534 | rss_i = min_t(u16, interface->hw.mac.max_queues, f->limit); | |
1535 | ||
1536 | /* record indices and power of 2 mask for RSS */ | |
1537 | f->indices = rss_i; | |
fcdb0a99 | 1538 | f->mask = BIT(fls(rss_i - 1)) - 1; |
aa3ac822 AD |
1539 | |
1540 | interface->num_rx_queues = rss_i; | |
1541 | interface->num_tx_queues = rss_i; | |
1542 | ||
1543 | return true; | |
1544 | } | |
1545 | ||
18283cad AD |
1546 | /** |
1547 | * fm10k_set_num_queues: Allocate queues for device, feature dependent | |
1548 | * @interface: board private structure to initialize | |
1549 | * | |
1550 | * This is the top level queue allocation routine. The order here is very | |
1551 | * important, starting with the "most" number of features turned on at once, | |
1552 | * and ending with the smallest set of features. This way large combinations | |
1553 | * can be allocated if they're turned on, and smaller combinations are the | |
1554 | * fallthrough conditions. | |
1555 | * | |
1556 | **/ | |
1557 | static void fm10k_set_num_queues(struct fm10k_intfc *interface) | |
1558 | { | |
b3525696 | 1559 | /* Attempt to setup QoS and RSS first */ |
aa3ac822 AD |
1560 | if (fm10k_set_qos_queues(interface)) |
1561 | return; | |
1562 | ||
b3525696 | 1563 | /* If we don't have QoS, just fallback to only RSS. */ |
aa3ac822 | 1564 | fm10k_set_rss_queues(interface); |
18283cad AD |
1565 | } |
1566 | ||
4be37c42 JK |
1567 | /** |
1568 | * fm10k_reset_num_queues - Reset the number of queues to zero | |
1569 | * @interface: board private structure | |
1570 | * | |
1571 | * This function should be called whenever we need to reset the number of | |
1572 | * queues after an error condition. | |
1573 | */ | |
1574 | static void fm10k_reset_num_queues(struct fm10k_intfc *interface) | |
1575 | { | |
1576 | interface->num_tx_queues = 0; | |
1577 | interface->num_rx_queues = 0; | |
1578 | interface->num_q_vectors = 0; | |
1579 | } | |
1580 | ||
18283cad AD |
1581 | /** |
1582 | * fm10k_alloc_q_vector - Allocate memory for a single interrupt vector | |
1583 | * @interface: board private structure to initialize | |
1584 | * @v_count: q_vectors allocated on interface, used for ring interleaving | |
1585 | * @v_idx: index of vector in interface struct | |
1586 | * @txr_count: total number of Tx rings to allocate | |
1587 | * @txr_idx: index of first Tx ring to allocate | |
1588 | * @rxr_count: total number of Rx rings to allocate | |
1589 | * @rxr_idx: index of first Rx ring to allocate | |
1590 | * | |
1591 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
1592 | **/ | |
1593 | static int fm10k_alloc_q_vector(struct fm10k_intfc *interface, | |
1594 | unsigned int v_count, unsigned int v_idx, | |
1595 | unsigned int txr_count, unsigned int txr_idx, | |
1596 | unsigned int rxr_count, unsigned int rxr_idx) | |
1597 | { | |
1598 | struct fm10k_q_vector *q_vector; | |
e27ef599 | 1599 | struct fm10k_ring *ring; |
18283cad AD |
1600 | int ring_count, size; |
1601 | ||
1602 | ring_count = txr_count + rxr_count; | |
e27ef599 AD |
1603 | size = sizeof(struct fm10k_q_vector) + |
1604 | (sizeof(struct fm10k_ring) * ring_count); | |
18283cad AD |
1605 | |
1606 | /* allocate q_vector and rings */ | |
1607 | q_vector = kzalloc(size, GFP_KERNEL); | |
1608 | if (!q_vector) | |
1609 | return -ENOMEM; | |
1610 | ||
1611 | /* initialize NAPI */ | |
1612 | netif_napi_add(interface->netdev, &q_vector->napi, | |
1613 | fm10k_poll, NAPI_POLL_WEIGHT); | |
1614 | ||
1615 | /* tie q_vector and interface together */ | |
1616 | interface->q_vector[v_idx] = q_vector; | |
1617 | q_vector->interface = interface; | |
1618 | q_vector->v_idx = v_idx; | |
1619 | ||
e27ef599 AD |
1620 | /* initialize pointer to rings */ |
1621 | ring = q_vector->ring; | |
1622 | ||
18283cad | 1623 | /* save Tx ring container info */ |
e27ef599 AD |
1624 | q_vector->tx.ring = ring; |
1625 | q_vector->tx.work_limit = FM10K_DEFAULT_TX_WORK; | |
18283cad | 1626 | q_vector->tx.itr = interface->tx_itr; |
242722dd | 1627 | q_vector->tx.itr_scale = interface->hw.mac.itr_scale; |
18283cad AD |
1628 | q_vector->tx.count = txr_count; |
1629 | ||
e27ef599 AD |
1630 | while (txr_count) { |
1631 | /* assign generic ring traits */ | |
1632 | ring->dev = &interface->pdev->dev; | |
1633 | ring->netdev = interface->netdev; | |
1634 | ||
1635 | /* configure backlink on ring */ | |
1636 | ring->q_vector = q_vector; | |
1637 | ||
1638 | /* apply Tx specific ring traits */ | |
1639 | ring->count = interface->tx_ring_count; | |
1640 | ring->queue_index = txr_idx; | |
1641 | ||
1642 | /* assign ring to interface */ | |
1643 | interface->tx_ring[txr_idx] = ring; | |
1644 | ||
1645 | /* update count and index */ | |
1646 | txr_count--; | |
1647 | txr_idx += v_count; | |
1648 | ||
1649 | /* push pointer to next ring */ | |
1650 | ring++; | |
1651 | } | |
1652 | ||
18283cad | 1653 | /* save Rx ring container info */ |
e27ef599 | 1654 | q_vector->rx.ring = ring; |
18283cad | 1655 | q_vector->rx.itr = interface->rx_itr; |
242722dd | 1656 | q_vector->rx.itr_scale = interface->hw.mac.itr_scale; |
18283cad AD |
1657 | q_vector->rx.count = rxr_count; |
1658 | ||
e27ef599 AD |
1659 | while (rxr_count) { |
1660 | /* assign generic ring traits */ | |
1661 | ring->dev = &interface->pdev->dev; | |
1662 | ring->netdev = interface->netdev; | |
5cd5e2e9 | 1663 | rcu_assign_pointer(ring->l2_accel, interface->l2_accel); |
e27ef599 AD |
1664 | |
1665 | /* configure backlink on ring */ | |
1666 | ring->q_vector = q_vector; | |
1667 | ||
1668 | /* apply Rx specific ring traits */ | |
1669 | ring->count = interface->rx_ring_count; | |
1670 | ring->queue_index = rxr_idx; | |
1671 | ||
1672 | /* assign ring to interface */ | |
1673 | interface->rx_ring[rxr_idx] = ring; | |
1674 | ||
1675 | /* update count and index */ | |
1676 | rxr_count--; | |
1677 | rxr_idx += v_count; | |
1678 | ||
1679 | /* push pointer to next ring */ | |
1680 | ring++; | |
1681 | } | |
1682 | ||
7461fd91 AD |
1683 | fm10k_dbg_q_vector_init(q_vector); |
1684 | ||
18283cad AD |
1685 | return 0; |
1686 | } | |
1687 | ||
1688 | /** | |
1689 | * fm10k_free_q_vector - Free memory allocated for specific interrupt vector | |
1690 | * @interface: board private structure to initialize | |
1691 | * @v_idx: Index of vector to be freed | |
1692 | * | |
1693 | * This function frees the memory allocated to the q_vector. In addition if | |
1694 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1695 | * to freeing the q_vector. | |
1696 | **/ | |
1697 | static void fm10k_free_q_vector(struct fm10k_intfc *interface, int v_idx) | |
1698 | { | |
1699 | struct fm10k_q_vector *q_vector = interface->q_vector[v_idx]; | |
e27ef599 AD |
1700 | struct fm10k_ring *ring; |
1701 | ||
7461fd91 AD |
1702 | fm10k_dbg_q_vector_exit(q_vector); |
1703 | ||
e27ef599 AD |
1704 | fm10k_for_each_ring(ring, q_vector->tx) |
1705 | interface->tx_ring[ring->queue_index] = NULL; | |
1706 | ||
1707 | fm10k_for_each_ring(ring, q_vector->rx) | |
1708 | interface->rx_ring[ring->queue_index] = NULL; | |
18283cad AD |
1709 | |
1710 | interface->q_vector[v_idx] = NULL; | |
1711 | netif_napi_del(&q_vector->napi); | |
1712 | kfree_rcu(q_vector, rcu); | |
1713 | } | |
1714 | ||
1715 | /** | |
1716 | * fm10k_alloc_q_vectors - Allocate memory for interrupt vectors | |
1717 | * @interface: board private structure to initialize | |
1718 | * | |
1719 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
1720 | * return -ENOMEM. | |
1721 | **/ | |
1722 | static int fm10k_alloc_q_vectors(struct fm10k_intfc *interface) | |
1723 | { | |
1724 | unsigned int q_vectors = interface->num_q_vectors; | |
1725 | unsigned int rxr_remaining = interface->num_rx_queues; | |
1726 | unsigned int txr_remaining = interface->num_tx_queues; | |
1727 | unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
1728 | int err; | |
1729 | ||
1730 | if (q_vectors >= (rxr_remaining + txr_remaining)) { | |
1731 | for (; rxr_remaining; v_idx++) { | |
1732 | err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, | |
1733 | 0, 0, 1, rxr_idx); | |
1734 | if (err) | |
1735 | goto err_out; | |
1736 | ||
1737 | /* update counts and index */ | |
1738 | rxr_remaining--; | |
1739 | rxr_idx++; | |
1740 | } | |
1741 | } | |
1742 | ||
1743 | for (; v_idx < q_vectors; v_idx++) { | |
1744 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); | |
1745 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); | |
1746 | ||
1747 | err = fm10k_alloc_q_vector(interface, q_vectors, v_idx, | |
1748 | tqpv, txr_idx, | |
1749 | rqpv, rxr_idx); | |
1750 | ||
1751 | if (err) | |
1752 | goto err_out; | |
1753 | ||
1754 | /* update counts and index */ | |
1755 | rxr_remaining -= rqpv; | |
1756 | txr_remaining -= tqpv; | |
1757 | rxr_idx++; | |
1758 | txr_idx++; | |
1759 | } | |
1760 | ||
1761 | return 0; | |
1762 | ||
1763 | err_out: | |
4be37c42 | 1764 | fm10k_reset_num_queues(interface); |
18283cad AD |
1765 | |
1766 | while (v_idx--) | |
1767 | fm10k_free_q_vector(interface, v_idx); | |
1768 | ||
1769 | return -ENOMEM; | |
1770 | } | |
1771 | ||
1772 | /** | |
1773 | * fm10k_free_q_vectors - Free memory allocated for interrupt vectors | |
1774 | * @interface: board private structure to initialize | |
1775 | * | |
1776 | * This function frees the memory allocated to the q_vectors. In addition if | |
1777 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
1778 | * to freeing the q_vector. | |
1779 | **/ | |
1780 | static void fm10k_free_q_vectors(struct fm10k_intfc *interface) | |
1781 | { | |
1782 | int v_idx = interface->num_q_vectors; | |
1783 | ||
4be37c42 | 1784 | fm10k_reset_num_queues(interface); |
18283cad AD |
1785 | |
1786 | while (v_idx--) | |
1787 | fm10k_free_q_vector(interface, v_idx); | |
1788 | } | |
1789 | ||
1790 | /** | |
1791 | * f10k_reset_msix_capability - reset MSI-X capability | |
1792 | * @interface: board private structure to initialize | |
1793 | * | |
1794 | * Reset the MSI-X capability back to its starting state | |
1795 | **/ | |
1796 | static void fm10k_reset_msix_capability(struct fm10k_intfc *interface) | |
1797 | { | |
1798 | pci_disable_msix(interface->pdev); | |
1799 | kfree(interface->msix_entries); | |
1800 | interface->msix_entries = NULL; | |
1801 | } | |
1802 | ||
1803 | /** | |
1804 | * f10k_init_msix_capability - configure MSI-X capability | |
1805 | * @interface: board private structure to initialize | |
1806 | * | |
1807 | * Attempt to configure the interrupts using the best available | |
1808 | * capabilities of the hardware and the kernel. | |
1809 | **/ | |
1810 | static int fm10k_init_msix_capability(struct fm10k_intfc *interface) | |
1811 | { | |
1812 | struct fm10k_hw *hw = &interface->hw; | |
1813 | int v_budget, vector; | |
1814 | ||
1815 | /* It's easy to be greedy for MSI-X vectors, but it really | |
1816 | * doesn't do us much good if we have a lot more vectors | |
1817 | * than CPU's. So let's be conservative and only ask for | |
1818 | * (roughly) the same number of vectors as there are CPU's. | |
1819 | * the default is to use pairs of vectors | |
1820 | */ | |
1821 | v_budget = max(interface->num_rx_queues, interface->num_tx_queues); | |
1822 | v_budget = min_t(u16, v_budget, num_online_cpus()); | |
1823 | ||
1824 | /* account for vectors not related to queues */ | |
1825 | v_budget += NON_Q_VECTORS(hw); | |
1826 | ||
1827 | /* At the same time, hardware can only support a maximum of | |
1828 | * hw.mac->max_msix_vectors vectors. With features | |
1829 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
1830 | * descriptor queues supported by our device. Thus, we cap it off in | |
1831 | * those rare cases where the cpu count also exceeds our vector limit. | |
1832 | */ | |
1833 | v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); | |
1834 | ||
1835 | /* A failure in MSI-X entry allocation is fatal. */ | |
1836 | interface->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), | |
1837 | GFP_KERNEL); | |
1838 | if (!interface->msix_entries) | |
1839 | return -ENOMEM; | |
1840 | ||
1841 | /* populate entry values */ | |
1842 | for (vector = 0; vector < v_budget; vector++) | |
1843 | interface->msix_entries[vector].entry = vector; | |
1844 | ||
1845 | /* Attempt to enable MSI-X with requested value */ | |
1846 | v_budget = pci_enable_msix_range(interface->pdev, | |
1847 | interface->msix_entries, | |
1848 | MIN_MSIX_COUNT(hw), | |
1849 | v_budget); | |
1850 | if (v_budget < 0) { | |
1851 | kfree(interface->msix_entries); | |
1852 | interface->msix_entries = NULL; | |
1853 | return -ENOMEM; | |
1854 | } | |
1855 | ||
1856 | /* record the number of queues available for q_vectors */ | |
1857 | interface->num_q_vectors = v_budget - NON_Q_VECTORS(hw); | |
1858 | ||
1859 | return 0; | |
1860 | } | |
1861 | ||
aa3ac822 AD |
1862 | /** |
1863 | * fm10k_cache_ring_qos - Descriptor ring to register mapping for QoS | |
1864 | * @interface: Interface structure continaining rings and devices | |
1865 | * | |
1866 | * Cache the descriptor ring offsets for Qos | |
1867 | **/ | |
1868 | static bool fm10k_cache_ring_qos(struct fm10k_intfc *interface) | |
1869 | { | |
1870 | struct net_device *dev = interface->netdev; | |
1871 | int pc, offset, rss_i, i, q_idx; | |
1872 | u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1; | |
1873 | u8 num_pcs = netdev_get_num_tc(dev); | |
1874 | ||
1875 | if (num_pcs <= 1) | |
1876 | return false; | |
1877 | ||
1878 | rss_i = interface->ring_feature[RING_F_RSS].indices; | |
1879 | ||
1880 | for (pc = 0, offset = 0; pc < num_pcs; pc++, offset += rss_i) { | |
1881 | q_idx = pc; | |
1882 | for (i = 0; i < rss_i; i++) { | |
1883 | interface->tx_ring[offset + i]->reg_idx = q_idx; | |
1884 | interface->tx_ring[offset + i]->qos_pc = pc; | |
1885 | interface->rx_ring[offset + i]->reg_idx = q_idx; | |
1886 | interface->rx_ring[offset + i]->qos_pc = pc; | |
1887 | q_idx += pc_stride; | |
1888 | } | |
1889 | } | |
1890 | ||
1891 | return true; | |
1892 | } | |
1893 | ||
1894 | /** | |
1895 | * fm10k_cache_ring_rss - Descriptor ring to register mapping for RSS | |
1896 | * @interface: Interface structure continaining rings and devices | |
1897 | * | |
1898 | * Cache the descriptor ring offsets for RSS | |
1899 | **/ | |
1900 | static void fm10k_cache_ring_rss(struct fm10k_intfc *interface) | |
1901 | { | |
1902 | int i; | |
1903 | ||
1904 | for (i = 0; i < interface->num_rx_queues; i++) | |
1905 | interface->rx_ring[i]->reg_idx = i; | |
1906 | ||
1907 | for (i = 0; i < interface->num_tx_queues; i++) | |
1908 | interface->tx_ring[i]->reg_idx = i; | |
1909 | } | |
1910 | ||
1911 | /** | |
1912 | * fm10k_assign_rings - Map rings to network devices | |
1913 | * @interface: Interface structure containing rings and devices | |
1914 | * | |
1915 | * This function is meant to go though and configure both the network | |
1916 | * devices so that they contain rings, and configure the rings so that | |
1917 | * they function with their network devices. | |
1918 | **/ | |
1919 | static void fm10k_assign_rings(struct fm10k_intfc *interface) | |
1920 | { | |
1921 | if (fm10k_cache_ring_qos(interface)) | |
1922 | return; | |
1923 | ||
1924 | fm10k_cache_ring_rss(interface); | |
1925 | } | |
1926 | ||
18283cad AD |
1927 | static void fm10k_init_reta(struct fm10k_intfc *interface) |
1928 | { | |
1929 | u16 i, rss_i = interface->ring_feature[RING_F_RSS].indices; | |
540a5d85 | 1930 | u32 reta; |
18283cad | 1931 | |
1012014e KJ |
1932 | /* If the Rx flow indirection table has been configured manually, we |
1933 | * need to maintain it when possible. | |
1934 | */ | |
1935 | if (netif_is_rxfh_configured(interface->netdev)) { | |
18283cad AD |
1936 | for (i = FM10K_RETA_SIZE; i--;) { |
1937 | reta = interface->reta[i]; | |
1938 | if ((((reta << 24) >> 24) < rss_i) && | |
1939 | (((reta << 16) >> 24) < rss_i) && | |
1940 | (((reta << 8) >> 24) < rss_i) && | |
1941 | (((reta) >> 24) < rss_i)) | |
1942 | continue; | |
1012014e KJ |
1943 | |
1944 | /* this should never happen */ | |
1945 | dev_err(&interface->pdev->dev, | |
1946 | "RSS indirection table assigned flows out of queue bounds. Reconfiguring.\n"); | |
18283cad AD |
1947 | goto repopulate_reta; |
1948 | } | |
1949 | ||
1950 | /* do nothing if all of the elements are in bounds */ | |
1951 | return; | |
1952 | } | |
1953 | ||
1954 | repopulate_reta: | |
540a5d85 | 1955 | fm10k_write_reta(interface, NULL); |
18283cad AD |
1956 | } |
1957 | ||
1958 | /** | |
1959 | * fm10k_init_queueing_scheme - Determine proper queueing scheme | |
1960 | * @interface: board private structure to initialize | |
1961 | * | |
1962 | * We determine which queueing scheme to use based on... | |
1963 | * - Hardware queue count (num_*_queues) | |
1964 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
1965 | **/ | |
1966 | int fm10k_init_queueing_scheme(struct fm10k_intfc *interface) | |
1967 | { | |
1968 | int err; | |
1969 | ||
1970 | /* Number of supported queues */ | |
1971 | fm10k_set_num_queues(interface); | |
1972 | ||
1973 | /* Configure MSI-X capability */ | |
1974 | err = fm10k_init_msix_capability(interface); | |
1975 | if (err) { | |
1976 | dev_err(&interface->pdev->dev, | |
1977 | "Unable to initialize MSI-X capability\n"); | |
4be37c42 | 1978 | goto err_init_msix; |
18283cad AD |
1979 | } |
1980 | ||
1981 | /* Allocate memory for queues */ | |
1982 | err = fm10k_alloc_q_vectors(interface); | |
587731e6 | 1983 | if (err) { |
4be37c42 JK |
1984 | dev_err(&interface->pdev->dev, |
1985 | "Unable to allocate queue vectors\n"); | |
1986 | goto err_alloc_q_vectors; | |
587731e6 | 1987 | } |
18283cad | 1988 | |
aa3ac822 AD |
1989 | /* Map rings to devices, and map devices to physical queues */ |
1990 | fm10k_assign_rings(interface); | |
1991 | ||
18283cad AD |
1992 | /* Initialize RSS redirection table */ |
1993 | fm10k_init_reta(interface); | |
1994 | ||
1995 | return 0; | |
4be37c42 JK |
1996 | |
1997 | err_alloc_q_vectors: | |
1998 | fm10k_reset_msix_capability(interface); | |
1999 | err_init_msix: | |
2000 | fm10k_reset_num_queues(interface); | |
2001 | return err; | |
18283cad AD |
2002 | } |
2003 | ||
2004 | /** | |
2005 | * fm10k_clear_queueing_scheme - Clear the current queueing scheme settings | |
2006 | * @interface: board private structure to clear queueing scheme on | |
2007 | * | |
2008 | * We go through and clear queueing specific resources and reset the structure | |
2009 | * to pre-load conditions | |
2010 | **/ | |
2011 | void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface) | |
2012 | { | |
2013 | fm10k_free_q_vectors(interface); | |
2014 | fm10k_reset_msix_capability(interface); | |
2015 | } |