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b3890e30 | 1 | /* Intel Ethernet Switch Host Interface Driver |
97c71e3c | 2 | * Copyright(c) 2013 - 2015 Intel Corporation. |
b3890e30 AD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
19ae1b3f | 22 | #include <linux/aer.h> |
b3890e30 AD |
23 | |
24 | #include "fm10k.h" | |
25 | ||
0e7b3644 AD |
26 | static const struct fm10k_info *fm10k_info_tbl[] = { |
27 | [fm10k_device_pf] = &fm10k_pf_info, | |
5cb8db4a | 28 | [fm10k_device_vf] = &fm10k_vf_info, |
0e7b3644 AD |
29 | }; |
30 | ||
b3890e30 AD |
31 | /** |
32 | * fm10k_pci_tbl - PCI Device ID Table | |
33 | * | |
34 | * Wildcard entries (PCI_ANY_ID) should come last | |
35 | * Last entry must be all 0s | |
36 | * | |
37 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
38 | * Class, Class Mask, private data (not used) } | |
39 | */ | |
40 | static const struct pci_device_id fm10k_pci_tbl[] = { | |
0e7b3644 | 41 | { PCI_VDEVICE(INTEL, FM10K_DEV_ID_PF), fm10k_device_pf }, |
5cb8db4a | 42 | { PCI_VDEVICE(INTEL, FM10K_DEV_ID_VF), fm10k_device_vf }, |
b3890e30 AD |
43 | /* required last entry */ |
44 | { 0, } | |
45 | }; | |
46 | MODULE_DEVICE_TABLE(pci, fm10k_pci_tbl); | |
47 | ||
04a5aefb AD |
48 | u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg) |
49 | { | |
50 | struct fm10k_intfc *interface = hw->back; | |
51 | u16 value = 0; | |
52 | ||
53 | if (FM10K_REMOVED(hw->hw_addr)) | |
54 | return ~value; | |
55 | ||
56 | pci_read_config_word(interface->pdev, reg, &value); | |
57 | if (value == 0xFFFF) | |
58 | fm10k_write_flush(hw); | |
59 | ||
60 | return value; | |
61 | } | |
62 | ||
63 | u32 fm10k_read_reg(struct fm10k_hw *hw, int reg) | |
64 | { | |
65 | u32 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); | |
66 | u32 value = 0; | |
67 | ||
68 | if (FM10K_REMOVED(hw_addr)) | |
69 | return ~value; | |
70 | ||
71 | value = readl(&hw_addr[reg]); | |
0e7b3644 AD |
72 | if (!(~value) && (!reg || !(~readl(hw_addr)))) { |
73 | struct fm10k_intfc *interface = hw->back; | |
74 | struct net_device *netdev = interface->netdev; | |
75 | ||
04a5aefb | 76 | hw->hw_addr = NULL; |
0e7b3644 AD |
77 | netif_device_detach(netdev); |
78 | netdev_err(netdev, "PCIe link lost, device now detached\n"); | |
79 | } | |
04a5aefb AD |
80 | |
81 | return value; | |
82 | } | |
83 | ||
0e7b3644 AD |
84 | static int fm10k_hw_ready(struct fm10k_intfc *interface) |
85 | { | |
86 | struct fm10k_hw *hw = &interface->hw; | |
87 | ||
88 | fm10k_write_flush(hw); | |
89 | ||
90 | return FM10K_REMOVED(hw->hw_addr) ? -ENODEV : 0; | |
91 | } | |
92 | ||
b7d8514c AD |
93 | void fm10k_service_event_schedule(struct fm10k_intfc *interface) |
94 | { | |
95 | if (!test_bit(__FM10K_SERVICE_DISABLE, &interface->state) && | |
96 | !test_and_set_bit(__FM10K_SERVICE_SCHED, &interface->state)) | |
97 | schedule_work(&interface->service_task); | |
98 | } | |
99 | ||
100 | static void fm10k_service_event_complete(struct fm10k_intfc *interface) | |
101 | { | |
102 | BUG_ON(!test_bit(__FM10K_SERVICE_SCHED, &interface->state)); | |
103 | ||
104 | /* flush memory to make sure state is correct before next watchog */ | |
105 | smp_mb__before_atomic(); | |
106 | clear_bit(__FM10K_SERVICE_SCHED, &interface->state); | |
107 | } | |
108 | ||
109 | /** | |
110 | * fm10k_service_timer - Timer Call-back | |
111 | * @data: pointer to interface cast into an unsigned long | |
112 | **/ | |
113 | static void fm10k_service_timer(unsigned long data) | |
114 | { | |
115 | struct fm10k_intfc *interface = (struct fm10k_intfc *)data; | |
116 | ||
117 | /* Reset the timer */ | |
118 | mod_timer(&interface->service_timer, (HZ * 2) + jiffies); | |
119 | ||
120 | fm10k_service_event_schedule(interface); | |
121 | } | |
122 | ||
123 | static void fm10k_detach_subtask(struct fm10k_intfc *interface) | |
124 | { | |
125 | struct net_device *netdev = interface->netdev; | |
126 | ||
127 | /* do nothing if device is still present or hw_addr is set */ | |
128 | if (netif_device_present(netdev) || interface->hw.hw_addr) | |
129 | return; | |
130 | ||
131 | rtnl_lock(); | |
132 | ||
133 | if (netif_running(netdev)) | |
134 | dev_close(netdev); | |
135 | ||
136 | rtnl_unlock(); | |
137 | } | |
138 | ||
139 | static void fm10k_reinit(struct fm10k_intfc *interface) | |
140 | { | |
141 | struct net_device *netdev = interface->netdev; | |
142 | struct fm10k_hw *hw = &interface->hw; | |
143 | int err; | |
144 | ||
145 | WARN_ON(in_interrupt()); | |
146 | ||
147 | /* put off any impending NetWatchDogTimeout */ | |
148 | netdev->trans_start = jiffies; | |
149 | ||
150 | while (test_and_set_bit(__FM10K_RESETTING, &interface->state)) | |
151 | usleep_range(1000, 2000); | |
152 | ||
153 | rtnl_lock(); | |
154 | ||
883a9ccb AD |
155 | fm10k_iov_suspend(interface->pdev); |
156 | ||
b7d8514c AD |
157 | if (netif_running(netdev)) |
158 | fm10k_close(netdev); | |
159 | ||
160 | fm10k_mbx_free_irq(interface); | |
161 | ||
162 | /* delay any future reset requests */ | |
163 | interface->last_reset = jiffies + (10 * HZ); | |
164 | ||
165 | /* reset and initialize the hardware so it is in a known state */ | |
166 | err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw); | |
167 | if (err) | |
168 | dev_err(&interface->pdev->dev, "init_hw failed: %d\n", err); | |
169 | ||
170 | /* reassociate interrupts */ | |
171 | fm10k_mbx_request_irq(interface); | |
172 | ||
a211e013 AD |
173 | /* reset clock */ |
174 | fm10k_ts_reset(interface); | |
175 | ||
b7d8514c AD |
176 | if (netif_running(netdev)) |
177 | fm10k_open(netdev); | |
178 | ||
883a9ccb AD |
179 | fm10k_iov_resume(interface->pdev); |
180 | ||
b7d8514c AD |
181 | rtnl_unlock(); |
182 | ||
183 | clear_bit(__FM10K_RESETTING, &interface->state); | |
184 | } | |
185 | ||
186 | static void fm10k_reset_subtask(struct fm10k_intfc *interface) | |
187 | { | |
188 | if (!(interface->flags & FM10K_FLAG_RESET_REQUESTED)) | |
189 | return; | |
190 | ||
191 | interface->flags &= ~FM10K_FLAG_RESET_REQUESTED; | |
192 | ||
193 | netdev_err(interface->netdev, "Reset interface\n"); | |
194 | interface->tx_timeout_count++; | |
195 | ||
196 | fm10k_reinit(interface); | |
197 | } | |
198 | ||
199 | /** | |
200 | * fm10k_configure_swpri_map - Configure Receive SWPRI to PC mapping | |
201 | * @interface: board private structure | |
202 | * | |
203 | * Configure the SWPRI to PC mapping for the port. | |
204 | **/ | |
205 | static void fm10k_configure_swpri_map(struct fm10k_intfc *interface) | |
206 | { | |
207 | struct net_device *netdev = interface->netdev; | |
208 | struct fm10k_hw *hw = &interface->hw; | |
209 | int i; | |
210 | ||
211 | /* clear flag indicating update is needed */ | |
212 | interface->flags &= ~FM10K_FLAG_SWPRI_CONFIG; | |
213 | ||
214 | /* these registers are only available on the PF */ | |
215 | if (hw->mac.type != fm10k_mac_pf) | |
216 | return; | |
217 | ||
218 | /* configure SWPRI to PC map */ | |
219 | for (i = 0; i < FM10K_SWPRI_MAX; i++) | |
220 | fm10k_write_reg(hw, FM10K_SWPRI_MAP(i), | |
221 | netdev_get_prio_tc_map(netdev, i)); | |
222 | } | |
223 | ||
224 | /** | |
225 | * fm10k_watchdog_update_host_state - Update the link status based on host. | |
226 | * @interface: board private structure | |
227 | **/ | |
228 | static void fm10k_watchdog_update_host_state(struct fm10k_intfc *interface) | |
229 | { | |
230 | struct fm10k_hw *hw = &interface->hw; | |
231 | s32 err; | |
232 | ||
233 | if (test_bit(__FM10K_LINK_DOWN, &interface->state)) { | |
234 | interface->host_ready = false; | |
235 | if (time_is_after_jiffies(interface->link_down_event)) | |
236 | return; | |
237 | clear_bit(__FM10K_LINK_DOWN, &interface->state); | |
238 | } | |
239 | ||
240 | if (interface->flags & FM10K_FLAG_SWPRI_CONFIG) { | |
241 | if (rtnl_trylock()) { | |
242 | fm10k_configure_swpri_map(interface); | |
243 | rtnl_unlock(); | |
244 | } | |
245 | } | |
246 | ||
247 | /* lock the mailbox for transmit and receive */ | |
248 | fm10k_mbx_lock(interface); | |
249 | ||
250 | err = hw->mac.ops.get_host_state(hw, &interface->host_ready); | |
251 | if (err && time_is_before_jiffies(interface->last_reset)) | |
252 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
253 | ||
254 | /* free the lock */ | |
255 | fm10k_mbx_unlock(interface); | |
256 | } | |
257 | ||
258 | /** | |
259 | * fm10k_mbx_subtask - Process upstream and downstream mailboxes | |
260 | * @interface: board private structure | |
261 | * | |
262 | * This function will process both the upstream and downstream mailboxes. | |
263 | * It is necessary for us to hold the rtnl_lock while doing this as the | |
264 | * mailbox accesses are protected by this lock. | |
265 | **/ | |
266 | static void fm10k_mbx_subtask(struct fm10k_intfc *interface) | |
267 | { | |
268 | /* process upstream mailbox and update device state */ | |
269 | fm10k_watchdog_update_host_state(interface); | |
883a9ccb AD |
270 | |
271 | /* process downstream mailboxes */ | |
272 | fm10k_iov_mbx(interface); | |
b7d8514c AD |
273 | } |
274 | ||
275 | /** | |
276 | * fm10k_watchdog_host_is_ready - Update netdev status based on host ready | |
277 | * @interface: board private structure | |
278 | **/ | |
279 | static void fm10k_watchdog_host_is_ready(struct fm10k_intfc *interface) | |
280 | { | |
281 | struct net_device *netdev = interface->netdev; | |
282 | ||
283 | /* only continue if link state is currently down */ | |
284 | if (netif_carrier_ok(netdev)) | |
285 | return; | |
286 | ||
287 | netif_info(interface, drv, netdev, "NIC Link is up\n"); | |
288 | ||
289 | netif_carrier_on(netdev); | |
290 | netif_tx_wake_all_queues(netdev); | |
291 | } | |
292 | ||
293 | /** | |
294 | * fm10k_watchdog_host_not_ready - Update netdev status based on host not ready | |
295 | * @interface: board private structure | |
296 | **/ | |
297 | static void fm10k_watchdog_host_not_ready(struct fm10k_intfc *interface) | |
298 | { | |
299 | struct net_device *netdev = interface->netdev; | |
300 | ||
301 | /* only continue if link state is currently up */ | |
302 | if (!netif_carrier_ok(netdev)) | |
303 | return; | |
304 | ||
305 | netif_info(interface, drv, netdev, "NIC Link is down\n"); | |
306 | ||
307 | netif_carrier_off(netdev); | |
308 | netif_tx_stop_all_queues(netdev); | |
309 | } | |
310 | ||
311 | /** | |
312 | * fm10k_update_stats - Update the board statistics counters. | |
313 | * @interface: board private structure | |
314 | **/ | |
315 | void fm10k_update_stats(struct fm10k_intfc *interface) | |
316 | { | |
317 | struct net_device_stats *net_stats = &interface->netdev->stats; | |
318 | struct fm10k_hw *hw = &interface->hw; | |
319 | u64 rx_errors = 0, rx_csum_errors = 0, tx_csum_errors = 0; | |
320 | u64 restart_queue = 0, tx_busy = 0, alloc_failed = 0; | |
321 | u64 rx_bytes_nic = 0, rx_pkts_nic = 0, rx_drops_nic = 0; | |
322 | u64 tx_bytes_nic = 0, tx_pkts_nic = 0; | |
323 | u64 bytes, pkts; | |
324 | int i; | |
325 | ||
326 | /* do not allow stats update via service task for next second */ | |
327 | interface->next_stats_update = jiffies + HZ; | |
328 | ||
329 | /* gather some stats to the interface struct that are per queue */ | |
330 | for (bytes = 0, pkts = 0, i = 0; i < interface->num_tx_queues; i++) { | |
331 | struct fm10k_ring *tx_ring = interface->tx_ring[i]; | |
332 | ||
333 | restart_queue += tx_ring->tx_stats.restart_queue; | |
334 | tx_busy += tx_ring->tx_stats.tx_busy; | |
335 | tx_csum_errors += tx_ring->tx_stats.csum_err; | |
336 | bytes += tx_ring->stats.bytes; | |
337 | pkts += tx_ring->stats.packets; | |
338 | } | |
339 | ||
340 | interface->restart_queue = restart_queue; | |
341 | interface->tx_busy = tx_busy; | |
342 | net_stats->tx_bytes = bytes; | |
343 | net_stats->tx_packets = pkts; | |
344 | interface->tx_csum_errors = tx_csum_errors; | |
345 | /* gather some stats to the interface struct that are per queue */ | |
346 | for (bytes = 0, pkts = 0, i = 0; i < interface->num_rx_queues; i++) { | |
347 | struct fm10k_ring *rx_ring = interface->rx_ring[i]; | |
348 | ||
349 | bytes += rx_ring->stats.bytes; | |
350 | pkts += rx_ring->stats.packets; | |
351 | alloc_failed += rx_ring->rx_stats.alloc_failed; | |
352 | rx_csum_errors += rx_ring->rx_stats.csum_err; | |
353 | rx_errors += rx_ring->rx_stats.errors; | |
354 | } | |
355 | ||
356 | net_stats->rx_bytes = bytes; | |
357 | net_stats->rx_packets = pkts; | |
358 | interface->alloc_failed = alloc_failed; | |
359 | interface->rx_csum_errors = rx_csum_errors; | |
b7d8514c AD |
360 | |
361 | hw->mac.ops.update_hw_stats(hw, &interface->stats); | |
362 | ||
363 | for (i = 0; i < FM10K_MAX_QUEUES_PF; i++) { | |
364 | struct fm10k_hw_stats_q *q = &interface->stats.q[i]; | |
365 | ||
366 | tx_bytes_nic += q->tx_bytes.count; | |
367 | tx_pkts_nic += q->tx_packets.count; | |
368 | rx_bytes_nic += q->rx_bytes.count; | |
369 | rx_pkts_nic += q->rx_packets.count; | |
370 | rx_drops_nic += q->rx_drops.count; | |
371 | } | |
372 | ||
373 | interface->tx_bytes_nic = tx_bytes_nic; | |
374 | interface->tx_packets_nic = tx_pkts_nic; | |
375 | interface->rx_bytes_nic = rx_bytes_nic; | |
376 | interface->rx_packets_nic = rx_pkts_nic; | |
377 | interface->rx_drops_nic = rx_drops_nic; | |
378 | ||
379 | /* Fill out the OS statistics structure */ | |
97c71e3c | 380 | net_stats->rx_errors = rx_errors; |
b7d8514c AD |
381 | net_stats->rx_dropped = interface->stats.nodesc_drop.count; |
382 | } | |
383 | ||
384 | /** | |
385 | * fm10k_watchdog_flush_tx - flush queues on host not ready | |
386 | * @interface - pointer to the device interface structure | |
387 | **/ | |
388 | static void fm10k_watchdog_flush_tx(struct fm10k_intfc *interface) | |
389 | { | |
390 | int some_tx_pending = 0; | |
391 | int i; | |
392 | ||
393 | /* nothing to do if carrier is up */ | |
394 | if (netif_carrier_ok(interface->netdev)) | |
395 | return; | |
396 | ||
397 | for (i = 0; i < interface->num_tx_queues; i++) { | |
398 | struct fm10k_ring *tx_ring = interface->tx_ring[i]; | |
399 | ||
400 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { | |
401 | some_tx_pending = 1; | |
402 | break; | |
403 | } | |
404 | } | |
405 | ||
406 | /* We've lost link, so the controller stops DMA, but we've got | |
407 | * queued Tx work that's never going to get done, so reset | |
408 | * controller to flush Tx. | |
409 | */ | |
410 | if (some_tx_pending) | |
411 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
412 | } | |
413 | ||
414 | /** | |
415 | * fm10k_watchdog_subtask - check and bring link up | |
416 | * @interface - pointer to the device interface structure | |
417 | **/ | |
418 | static void fm10k_watchdog_subtask(struct fm10k_intfc *interface) | |
419 | { | |
420 | /* if interface is down do nothing */ | |
421 | if (test_bit(__FM10K_DOWN, &interface->state) || | |
422 | test_bit(__FM10K_RESETTING, &interface->state)) | |
423 | return; | |
424 | ||
425 | if (interface->host_ready) | |
426 | fm10k_watchdog_host_is_ready(interface); | |
427 | else | |
428 | fm10k_watchdog_host_not_ready(interface); | |
429 | ||
430 | /* update stats only once every second */ | |
431 | if (time_is_before_jiffies(interface->next_stats_update)) | |
432 | fm10k_update_stats(interface); | |
433 | ||
434 | /* flush any uncompleted work */ | |
435 | fm10k_watchdog_flush_tx(interface); | |
436 | } | |
437 | ||
438 | /** | |
439 | * fm10k_check_hang_subtask - check for hung queues and dropped interrupts | |
440 | * @interface - pointer to the device interface structure | |
441 | * | |
442 | * This function serves two purposes. First it strobes the interrupt lines | |
443 | * in order to make certain interrupts are occurring. Secondly it sets the | |
444 | * bits needed to check for TX hangs. As a result we should immediately | |
445 | * determine if a hang has occurred. | |
446 | */ | |
447 | static void fm10k_check_hang_subtask(struct fm10k_intfc *interface) | |
448 | { | |
449 | int i; | |
450 | ||
451 | /* If we're down or resetting, just bail */ | |
452 | if (test_bit(__FM10K_DOWN, &interface->state) || | |
453 | test_bit(__FM10K_RESETTING, &interface->state)) | |
454 | return; | |
455 | ||
456 | /* rate limit tx hang checks to only once every 2 seconds */ | |
457 | if (time_is_after_eq_jiffies(interface->next_tx_hang_check)) | |
458 | return; | |
459 | interface->next_tx_hang_check = jiffies + (2 * HZ); | |
460 | ||
461 | if (netif_carrier_ok(interface->netdev)) { | |
462 | /* Force detection of hung controller */ | |
463 | for (i = 0; i < interface->num_tx_queues; i++) | |
464 | set_check_for_tx_hang(interface->tx_ring[i]); | |
465 | ||
466 | /* Rearm all in-use q_vectors for immediate firing */ | |
467 | for (i = 0; i < interface->num_q_vectors; i++) { | |
468 | struct fm10k_q_vector *qv = interface->q_vector[i]; | |
469 | ||
470 | if (!qv->tx.count && !qv->rx.count) | |
471 | continue; | |
472 | writel(FM10K_ITR_ENABLE | FM10K_ITR_PENDING2, qv->itr); | |
473 | } | |
474 | } | |
475 | } | |
476 | ||
477 | /** | |
478 | * fm10k_service_task - manages and runs subtasks | |
479 | * @work: pointer to work_struct containing our data | |
480 | **/ | |
481 | static void fm10k_service_task(struct work_struct *work) | |
482 | { | |
483 | struct fm10k_intfc *interface; | |
484 | ||
485 | interface = container_of(work, struct fm10k_intfc, service_task); | |
486 | ||
487 | /* tasks always capable of running, but must be rtnl protected */ | |
488 | fm10k_mbx_subtask(interface); | |
489 | fm10k_detach_subtask(interface); | |
490 | fm10k_reset_subtask(interface); | |
491 | ||
492 | /* tasks only run when interface is up */ | |
493 | fm10k_watchdog_subtask(interface); | |
494 | fm10k_check_hang_subtask(interface); | |
a211e013 | 495 | fm10k_ts_tx_subtask(interface); |
b7d8514c AD |
496 | |
497 | /* release lock on service events to allow scheduling next event */ | |
498 | fm10k_service_event_complete(interface); | |
499 | } | |
500 | ||
3abaae42 AD |
501 | /** |
502 | * fm10k_configure_tx_ring - Configure Tx ring after Reset | |
503 | * @interface: board private structure | |
504 | * @ring: structure containing ring specific data | |
505 | * | |
506 | * Configure the Tx descriptor ring after a reset. | |
507 | **/ | |
508 | static void fm10k_configure_tx_ring(struct fm10k_intfc *interface, | |
509 | struct fm10k_ring *ring) | |
510 | { | |
511 | struct fm10k_hw *hw = &interface->hw; | |
512 | u64 tdba = ring->dma; | |
513 | u32 size = ring->count * sizeof(struct fm10k_tx_desc); | |
514 | u32 txint = FM10K_INT_MAP_DISABLE; | |
515 | u32 txdctl = FM10K_TXDCTL_ENABLE | (1 << FM10K_TXDCTL_MAX_TIME_SHIFT); | |
516 | u8 reg_idx = ring->reg_idx; | |
517 | ||
518 | /* disable queue to avoid issues while updating state */ | |
519 | fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); | |
520 | fm10k_write_flush(hw); | |
521 | ||
522 | /* possible poll here to verify ring resources have been cleaned */ | |
523 | ||
524 | /* set location and size for descriptor ring */ | |
525 | fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); | |
526 | fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); | |
527 | fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); | |
528 | ||
529 | /* reset head and tail pointers */ | |
530 | fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); | |
531 | fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); | |
532 | ||
533 | /* store tail pointer */ | |
534 | ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)]; | |
535 | ||
536 | /* reset ntu and ntc to place SW in sync with hardwdare */ | |
537 | ring->next_to_clean = 0; | |
538 | ring->next_to_use = 0; | |
539 | ||
540 | /* Map interrupt */ | |
541 | if (ring->q_vector) { | |
542 | txint = ring->q_vector->v_idx + NON_Q_VECTORS(hw); | |
543 | txint |= FM10K_INT_MAP_TIMER0; | |
544 | } | |
545 | ||
546 | fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); | |
547 | ||
548 | /* enable use of FTAG bit in Tx descriptor, register is RO for VF */ | |
549 | fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), | |
550 | FM10K_PFVTCTL_FTAG_DESC_ENABLE); | |
551 | ||
552 | /* enable queue */ | |
553 | fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl); | |
554 | } | |
555 | ||
556 | /** | |
557 | * fm10k_enable_tx_ring - Verify Tx ring is enabled after configuration | |
558 | * @interface: board private structure | |
559 | * @ring: structure containing ring specific data | |
560 | * | |
561 | * Verify the Tx descriptor ring is ready for transmit. | |
562 | **/ | |
563 | static void fm10k_enable_tx_ring(struct fm10k_intfc *interface, | |
564 | struct fm10k_ring *ring) | |
565 | { | |
566 | struct fm10k_hw *hw = &interface->hw; | |
567 | int wait_loop = 10; | |
568 | u32 txdctl; | |
569 | u8 reg_idx = ring->reg_idx; | |
570 | ||
571 | /* if we are already enabled just exit */ | |
572 | if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE) | |
573 | return; | |
574 | ||
575 | /* poll to verify queue is enabled */ | |
576 | do { | |
577 | usleep_range(1000, 2000); | |
578 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)); | |
579 | } while (!(txdctl & FM10K_TXDCTL_ENABLE) && --wait_loop); | |
580 | if (!wait_loop) | |
581 | netif_err(interface, drv, interface->netdev, | |
582 | "Could not enable Tx Queue %d\n", reg_idx); | |
583 | } | |
584 | ||
585 | /** | |
586 | * fm10k_configure_tx - Configure Transmit Unit after Reset | |
587 | * @interface: board private structure | |
588 | * | |
589 | * Configure the Tx unit of the MAC after a reset. | |
590 | **/ | |
591 | static void fm10k_configure_tx(struct fm10k_intfc *interface) | |
592 | { | |
593 | int i; | |
594 | ||
595 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
596 | for (i = 0; i < interface->num_tx_queues; i++) | |
597 | fm10k_configure_tx_ring(interface, interface->tx_ring[i]); | |
598 | ||
599 | /* poll here to verify that Tx rings are now enabled */ | |
600 | for (i = 0; i < interface->num_tx_queues; i++) | |
601 | fm10k_enable_tx_ring(interface, interface->tx_ring[i]); | |
602 | } | |
603 | ||
604 | /** | |
605 | * fm10k_configure_rx_ring - Configure Rx ring after Reset | |
606 | * @interface: board private structure | |
607 | * @ring: structure containing ring specific data | |
608 | * | |
609 | * Configure the Rx descriptor ring after a reset. | |
610 | **/ | |
611 | static void fm10k_configure_rx_ring(struct fm10k_intfc *interface, | |
612 | struct fm10k_ring *ring) | |
613 | { | |
614 | u64 rdba = ring->dma; | |
615 | struct fm10k_hw *hw = &interface->hw; | |
616 | u32 size = ring->count * sizeof(union fm10k_rx_desc); | |
617 | u32 rxqctl = FM10K_RXQCTL_ENABLE | FM10K_RXQCTL_PF; | |
618 | u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY; | |
619 | u32 srrctl = FM10K_SRRCTL_BUFFER_CHAINING_EN; | |
620 | u32 rxint = FM10K_INT_MAP_DISABLE; | |
621 | u8 rx_pause = interface->rx_pause; | |
622 | u8 reg_idx = ring->reg_idx; | |
623 | ||
624 | /* disable queue to avoid issues while updating state */ | |
625 | fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), 0); | |
626 | fm10k_write_flush(hw); | |
627 | ||
628 | /* possible poll here to verify ring resources have been cleaned */ | |
629 | ||
630 | /* set location and size for descriptor ring */ | |
631 | fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32)); | |
632 | fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32); | |
633 | fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size); | |
634 | ||
635 | /* reset head and tail pointers */ | |
636 | fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0); | |
637 | fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0); | |
638 | ||
639 | /* store tail pointer */ | |
640 | ring->tail = &interface->uc_addr[FM10K_RDT(reg_idx)]; | |
641 | ||
642 | /* reset ntu and ntc to place SW in sync with hardwdare */ | |
643 | ring->next_to_clean = 0; | |
644 | ring->next_to_use = 0; | |
645 | ring->next_to_alloc = 0; | |
646 | ||
647 | /* Configure the Rx buffer size for one buff without split */ | |
648 | srrctl |= FM10K_RX_BUFSZ >> FM10K_SRRCTL_BSIZEPKT_SHIFT; | |
649 | ||
eca32047 | 650 | /* Configure the Rx ring to suppress loopback packets */ |
3abaae42 AD |
651 | srrctl |= FM10K_SRRCTL_LOOPBACK_SUPPRESS; |
652 | fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl); | |
653 | ||
654 | /* Enable drop on empty */ | |
9f801abc | 655 | #ifdef CONFIG_DCB |
3abaae42 AD |
656 | if (interface->pfc_en) |
657 | rx_pause = interface->pfc_en; | |
658 | #endif | |
659 | if (!(rx_pause & (1 << ring->qos_pc))) | |
660 | rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY; | |
661 | ||
662 | fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl); | |
663 | ||
664 | /* assign default VLAN to queue */ | |
665 | ring->vid = hw->mac.default_vid; | |
666 | ||
667 | /* Map interrupt */ | |
668 | if (ring->q_vector) { | |
669 | rxint = ring->q_vector->v_idx + NON_Q_VECTORS(hw); | |
670 | rxint |= FM10K_INT_MAP_TIMER1; | |
671 | } | |
672 | ||
673 | fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint); | |
674 | ||
675 | /* enable queue */ | |
676 | fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl); | |
b101c962 AD |
677 | |
678 | /* place buffers on ring for receive data */ | |
679 | fm10k_alloc_rx_buffers(ring, fm10k_desc_unused(ring)); | |
3abaae42 AD |
680 | } |
681 | ||
682 | /** | |
683 | * fm10k_update_rx_drop_en - Configures the drop enable bits for Rx rings | |
684 | * @interface: board private structure | |
685 | * | |
686 | * Configure the drop enable bits for the Rx rings. | |
687 | **/ | |
688 | void fm10k_update_rx_drop_en(struct fm10k_intfc *interface) | |
689 | { | |
690 | struct fm10k_hw *hw = &interface->hw; | |
691 | u8 rx_pause = interface->rx_pause; | |
692 | int i; | |
693 | ||
9f801abc | 694 | #ifdef CONFIG_DCB |
3abaae42 AD |
695 | if (interface->pfc_en) |
696 | rx_pause = interface->pfc_en; | |
697 | ||
698 | #endif | |
699 | for (i = 0; i < interface->num_rx_queues; i++) { | |
700 | struct fm10k_ring *ring = interface->rx_ring[i]; | |
701 | u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY; | |
702 | u8 reg_idx = ring->reg_idx; | |
703 | ||
704 | if (!(rx_pause & (1 << ring->qos_pc))) | |
705 | rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY; | |
706 | ||
707 | fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl); | |
708 | } | |
709 | } | |
710 | ||
711 | /** | |
712 | * fm10k_configure_dglort - Configure Receive DGLORT after reset | |
713 | * @interface: board private structure | |
714 | * | |
715 | * Configure the DGLORT description and RSS tables. | |
716 | **/ | |
717 | static void fm10k_configure_dglort(struct fm10k_intfc *interface) | |
718 | { | |
719 | struct fm10k_dglort_cfg dglort = { 0 }; | |
720 | struct fm10k_hw *hw = &interface->hw; | |
721 | int i; | |
722 | u32 mrqc; | |
723 | ||
724 | /* Fill out hash function seeds */ | |
725 | for (i = 0; i < FM10K_RSSRK_SIZE; i++) | |
726 | fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]); | |
727 | ||
728 | /* Write RETA table to hardware */ | |
729 | for (i = 0; i < FM10K_RETA_SIZE; i++) | |
730 | fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]); | |
731 | ||
732 | /* Generate RSS hash based on packet types, TCP/UDP | |
733 | * port numbers and/or IPv4/v6 src and dst addresses | |
734 | */ | |
735 | mrqc = FM10K_MRQC_IPV4 | | |
736 | FM10K_MRQC_TCP_IPV4 | | |
737 | FM10K_MRQC_IPV6 | | |
738 | FM10K_MRQC_TCP_IPV6; | |
739 | ||
740 | if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV4_UDP) | |
741 | mrqc |= FM10K_MRQC_UDP_IPV4; | |
742 | if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV6_UDP) | |
743 | mrqc |= FM10K_MRQC_UDP_IPV6; | |
744 | ||
745 | fm10k_write_reg(hw, FM10K_MRQC(0), mrqc); | |
746 | ||
747 | /* configure default DGLORT mapping for RSS/DCB */ | |
748 | dglort.inner_rss = 1; | |
749 | dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); | |
750 | dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); | |
751 | hw->mac.ops.configure_dglort_map(hw, &dglort); | |
752 | ||
753 | /* assign GLORT per queue for queue mapped testing */ | |
754 | if (interface->glort_count > 64) { | |
755 | memset(&dglort, 0, sizeof(dglort)); | |
756 | dglort.inner_rss = 1; | |
757 | dglort.glort = interface->glort + 64; | |
758 | dglort.idx = fm10k_dglort_pf_queue; | |
759 | dglort.queue_l = fls(interface->num_rx_queues - 1); | |
760 | hw->mac.ops.configure_dglort_map(hw, &dglort); | |
761 | } | |
762 | ||
763 | /* assign glort value for RSS/DCB specific to this interface */ | |
764 | memset(&dglort, 0, sizeof(dglort)); | |
765 | dglort.inner_rss = 1; | |
766 | dglort.glort = interface->glort; | |
767 | dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask); | |
768 | dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask); | |
769 | /* configure DGLORT mapping for RSS/DCB */ | |
770 | dglort.idx = fm10k_dglort_pf_rss; | |
5cd5e2e9 AD |
771 | if (interface->l2_accel) |
772 | dglort.shared_l = fls(interface->l2_accel->size); | |
3abaae42 AD |
773 | hw->mac.ops.configure_dglort_map(hw, &dglort); |
774 | } | |
775 | ||
776 | /** | |
777 | * fm10k_configure_rx - Configure Receive Unit after Reset | |
778 | * @interface: board private structure | |
779 | * | |
780 | * Configure the Rx unit of the MAC after a reset. | |
781 | **/ | |
782 | static void fm10k_configure_rx(struct fm10k_intfc *interface) | |
783 | { | |
784 | int i; | |
785 | ||
786 | /* Configure SWPRI to PC map */ | |
787 | fm10k_configure_swpri_map(interface); | |
788 | ||
789 | /* Configure RSS and DGLORT map */ | |
790 | fm10k_configure_dglort(interface); | |
791 | ||
792 | /* Setup the HW Rx Head and Tail descriptor pointers */ | |
793 | for (i = 0; i < interface->num_rx_queues; i++) | |
794 | fm10k_configure_rx_ring(interface, interface->rx_ring[i]); | |
795 | ||
796 | /* possible poll here to verify that Rx rings are now enabled */ | |
797 | } | |
798 | ||
18283cad AD |
799 | static void fm10k_napi_enable_all(struct fm10k_intfc *interface) |
800 | { | |
801 | struct fm10k_q_vector *q_vector; | |
802 | int q_idx; | |
803 | ||
804 | for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) { | |
805 | q_vector = interface->q_vector[q_idx]; | |
806 | napi_enable(&q_vector->napi); | |
807 | } | |
808 | } | |
809 | ||
810 | static irqreturn_t fm10k_msix_clean_rings(int irq, void *data) | |
811 | { | |
812 | struct fm10k_q_vector *q_vector = data; | |
813 | ||
814 | if (q_vector->rx.count || q_vector->tx.count) | |
815 | napi_schedule(&q_vector->napi); | |
816 | ||
817 | return IRQ_HANDLED; | |
818 | } | |
819 | ||
5cb8db4a AD |
820 | static irqreturn_t fm10k_msix_mbx_vf(int irq, void *data) |
821 | { | |
822 | struct fm10k_intfc *interface = data; | |
823 | struct fm10k_hw *hw = &interface->hw; | |
824 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
825 | ||
826 | /* re-enable mailbox interrupt and indicate 20us delay */ | |
827 | fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR), | |
828 | FM10K_ITR_ENABLE | FM10K_MBX_INT_DELAY); | |
829 | ||
830 | /* service upstream mailbox */ | |
831 | if (fm10k_mbx_trylock(interface)) { | |
832 | mbx->ops.process(hw, mbx); | |
833 | fm10k_mbx_unlock(interface); | |
834 | } | |
835 | ||
836 | hw->mac.get_host_state = 1; | |
837 | fm10k_service_event_schedule(interface); | |
838 | ||
839 | return IRQ_HANDLED; | |
840 | } | |
841 | ||
18283cad AD |
842 | #define FM10K_ERR_MSG(type) case (type): error = #type; break |
843 | static void fm10k_print_fault(struct fm10k_intfc *interface, int type, | |
844 | struct fm10k_fault *fault) | |
845 | { | |
846 | struct pci_dev *pdev = interface->pdev; | |
847 | char *error; | |
848 | ||
849 | switch (type) { | |
850 | case FM10K_PCA_FAULT: | |
851 | switch (fault->type) { | |
852 | default: | |
853 | error = "Unknown PCA error"; | |
854 | break; | |
855 | FM10K_ERR_MSG(PCA_NO_FAULT); | |
856 | FM10K_ERR_MSG(PCA_UNMAPPED_ADDR); | |
857 | FM10K_ERR_MSG(PCA_BAD_QACCESS_PF); | |
858 | FM10K_ERR_MSG(PCA_BAD_QACCESS_VF); | |
859 | FM10K_ERR_MSG(PCA_MALICIOUS_REQ); | |
860 | FM10K_ERR_MSG(PCA_POISONED_TLP); | |
861 | FM10K_ERR_MSG(PCA_TLP_ABORT); | |
862 | } | |
863 | break; | |
864 | case FM10K_THI_FAULT: | |
865 | switch (fault->type) { | |
866 | default: | |
867 | error = "Unknown THI error"; | |
868 | break; | |
869 | FM10K_ERR_MSG(THI_NO_FAULT); | |
870 | FM10K_ERR_MSG(THI_MAL_DIS_Q_FAULT); | |
871 | } | |
872 | break; | |
873 | case FM10K_FUM_FAULT: | |
874 | switch (fault->type) { | |
875 | default: | |
876 | error = "Unknown FUM error"; | |
877 | break; | |
878 | FM10K_ERR_MSG(FUM_NO_FAULT); | |
879 | FM10K_ERR_MSG(FUM_UNMAPPED_ADDR); | |
880 | FM10K_ERR_MSG(FUM_BAD_VF_QACCESS); | |
881 | FM10K_ERR_MSG(FUM_ADD_DECODE_ERR); | |
882 | FM10K_ERR_MSG(FUM_RO_ERROR); | |
883 | FM10K_ERR_MSG(FUM_QPRC_CRC_ERROR); | |
884 | FM10K_ERR_MSG(FUM_CSR_TIMEOUT); | |
885 | FM10K_ERR_MSG(FUM_INVALID_TYPE); | |
886 | FM10K_ERR_MSG(FUM_INVALID_LENGTH); | |
887 | FM10K_ERR_MSG(FUM_INVALID_BE); | |
888 | FM10K_ERR_MSG(FUM_INVALID_ALIGN); | |
889 | } | |
890 | break; | |
891 | default: | |
892 | error = "Undocumented fault"; | |
893 | break; | |
894 | } | |
895 | ||
896 | dev_warn(&pdev->dev, | |
897 | "%s Address: 0x%llx SpecInfo: 0x%x Func: %02x.%0x\n", | |
898 | error, fault->address, fault->specinfo, | |
899 | PCI_SLOT(fault->func), PCI_FUNC(fault->func)); | |
900 | } | |
901 | ||
902 | static void fm10k_report_fault(struct fm10k_intfc *interface, u32 eicr) | |
903 | { | |
904 | struct fm10k_hw *hw = &interface->hw; | |
905 | struct fm10k_fault fault = { 0 }; | |
906 | int type, err; | |
907 | ||
908 | for (eicr &= FM10K_EICR_FAULT_MASK, type = FM10K_PCA_FAULT; | |
909 | eicr; | |
910 | eicr >>= 1, type += FM10K_FAULT_SIZE) { | |
911 | /* only check if there is an error reported */ | |
912 | if (!(eicr & 0x1)) | |
913 | continue; | |
914 | ||
915 | /* retrieve fault info */ | |
916 | err = hw->mac.ops.get_fault(hw, type, &fault); | |
917 | if (err) { | |
918 | dev_err(&interface->pdev->dev, | |
919 | "error reading fault\n"); | |
920 | continue; | |
921 | } | |
922 | ||
923 | fm10k_print_fault(interface, type, &fault); | |
924 | } | |
925 | } | |
926 | ||
927 | static void fm10k_reset_drop_on_empty(struct fm10k_intfc *interface, u32 eicr) | |
928 | { | |
929 | struct fm10k_hw *hw = &interface->hw; | |
930 | const u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY; | |
931 | u32 maxholdq; | |
932 | int q; | |
933 | ||
934 | if (!(eicr & FM10K_EICR_MAXHOLDTIME)) | |
935 | return; | |
936 | ||
937 | maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(7)); | |
938 | if (maxholdq) | |
939 | fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq); | |
940 | for (q = 255;;) { | |
941 | if (maxholdq & (1 << 31)) { | |
942 | if (q < FM10K_MAX_QUEUES_PF) { | |
943 | interface->rx_overrun_pf++; | |
944 | fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl); | |
945 | } else { | |
946 | interface->rx_overrun_vf++; | |
947 | } | |
948 | } | |
949 | ||
950 | maxholdq *= 2; | |
951 | if (!maxholdq) | |
952 | q &= ~(32 - 1); | |
953 | ||
954 | if (!q) | |
955 | break; | |
956 | ||
957 | if (q-- % 32) | |
958 | continue; | |
959 | ||
960 | maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(q / 32)); | |
961 | if (maxholdq) | |
962 | fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq); | |
963 | } | |
964 | } | |
965 | ||
966 | static irqreturn_t fm10k_msix_mbx_pf(int irq, void *data) | |
967 | { | |
968 | struct fm10k_intfc *interface = data; | |
969 | struct fm10k_hw *hw = &interface->hw; | |
970 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
971 | u32 eicr; | |
972 | ||
973 | /* unmask any set bits related to this interrupt */ | |
974 | eicr = fm10k_read_reg(hw, FM10K_EICR); | |
975 | fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX | | |
976 | FM10K_EICR_SWITCHREADY | | |
977 | FM10K_EICR_SWITCHNOTREADY)); | |
978 | ||
979 | /* report any faults found to the message log */ | |
980 | fm10k_report_fault(interface, eicr); | |
981 | ||
982 | /* reset any queues disabled due to receiver overrun */ | |
983 | fm10k_reset_drop_on_empty(interface, eicr); | |
984 | ||
985 | /* service mailboxes */ | |
986 | if (fm10k_mbx_trylock(interface)) { | |
987 | mbx->ops.process(hw, mbx); | |
883a9ccb | 988 | fm10k_iov_event(interface); |
18283cad AD |
989 | fm10k_mbx_unlock(interface); |
990 | } | |
991 | ||
b7d8514c AD |
992 | /* if switch toggled state we should reset GLORTs */ |
993 | if (eicr & FM10K_EICR_SWITCHNOTREADY) { | |
994 | /* force link down for at least 4 seconds */ | |
995 | interface->link_down_event = jiffies + (4 * HZ); | |
996 | set_bit(__FM10K_LINK_DOWN, &interface->state); | |
997 | ||
998 | /* reset dglort_map back to no config */ | |
999 | hw->mac.dglort_map = FM10K_DGLORTMAP_NONE; | |
1000 | } | |
1001 | ||
1002 | /* we should validate host state after interrupt event */ | |
1003 | hw->mac.get_host_state = 1; | |
1004 | fm10k_service_event_schedule(interface); | |
1005 | ||
18283cad AD |
1006 | /* re-enable mailbox interrupt and indicate 20us delay */ |
1007 | fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR), | |
1008 | FM10K_ITR_ENABLE | FM10K_MBX_INT_DELAY); | |
1009 | ||
1010 | return IRQ_HANDLED; | |
1011 | } | |
1012 | ||
1013 | void fm10k_mbx_free_irq(struct fm10k_intfc *interface) | |
1014 | { | |
1015 | struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR]; | |
1016 | struct fm10k_hw *hw = &interface->hw; | |
1017 | int itr_reg; | |
1018 | ||
1019 | /* disconnect the mailbox */ | |
1020 | hw->mbx.ops.disconnect(hw, &hw->mbx); | |
1021 | ||
1022 | /* disable Mailbox cause */ | |
1023 | if (hw->mac.type == fm10k_mac_pf) { | |
1024 | fm10k_write_reg(hw, FM10K_EIMR, | |
1025 | FM10K_EIMR_DISABLE(PCA_FAULT) | | |
1026 | FM10K_EIMR_DISABLE(FUM_FAULT) | | |
1027 | FM10K_EIMR_DISABLE(MAILBOX) | | |
1028 | FM10K_EIMR_DISABLE(SWITCHREADY) | | |
1029 | FM10K_EIMR_DISABLE(SWITCHNOTREADY) | | |
1030 | FM10K_EIMR_DISABLE(SRAMERROR) | | |
1031 | FM10K_EIMR_DISABLE(VFLR) | | |
1032 | FM10K_EIMR_DISABLE(MAXHOLDTIME)); | |
1033 | itr_reg = FM10K_ITR(FM10K_MBX_VECTOR); | |
5cb8db4a AD |
1034 | } else { |
1035 | itr_reg = FM10K_VFITR(FM10K_MBX_VECTOR); | |
18283cad AD |
1036 | } |
1037 | ||
1038 | fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET); | |
1039 | ||
1040 | free_irq(entry->vector, interface); | |
1041 | } | |
1042 | ||
5cb8db4a AD |
1043 | static s32 fm10k_mbx_mac_addr(struct fm10k_hw *hw, u32 **results, |
1044 | struct fm10k_mbx_info *mbx) | |
1045 | { | |
1046 | bool vlan_override = hw->mac.vlan_override; | |
1047 | u16 default_vid = hw->mac.default_vid; | |
1048 | struct fm10k_intfc *interface; | |
1049 | s32 err; | |
1050 | ||
1051 | err = fm10k_msg_mac_vlan_vf(hw, results, mbx); | |
1052 | if (err) | |
1053 | return err; | |
1054 | ||
1055 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1056 | ||
1057 | /* MAC was changed so we need reset */ | |
1058 | if (is_valid_ether_addr(hw->mac.perm_addr) && | |
1059 | memcmp(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN)) | |
1060 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
1061 | ||
1062 | /* VLAN override was changed, or default VLAN changed */ | |
1063 | if ((vlan_override != hw->mac.vlan_override) || | |
1064 | (default_vid != hw->mac.default_vid)) | |
1065 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
a211e013 AD |
1070 | static s32 fm10k_1588_msg_vf(struct fm10k_hw *hw, u32 **results, |
1071 | struct fm10k_mbx_info *mbx) | |
1072 | { | |
1073 | struct fm10k_intfc *interface; | |
1074 | u64 timestamp; | |
1075 | s32 err; | |
1076 | ||
1077 | err = fm10k_tlv_attr_get_u64(results[FM10K_1588_MSG_TIMESTAMP], | |
1078 | ×tamp); | |
1079 | if (err) | |
1080 | return err; | |
1081 | ||
1082 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1083 | ||
1084 | fm10k_ts_tx_hwtstamp(interface, 0, timestamp); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
18283cad AD |
1089 | /* generic error handler for mailbox issues */ |
1090 | static s32 fm10k_mbx_error(struct fm10k_hw *hw, u32 **results, | |
1091 | struct fm10k_mbx_info *mbx) | |
1092 | { | |
1093 | struct fm10k_intfc *interface; | |
1094 | struct pci_dev *pdev; | |
1095 | ||
1096 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1097 | pdev = interface->pdev; | |
1098 | ||
1099 | dev_err(&pdev->dev, "Unknown message ID %u\n", | |
1100 | **results & FM10K_TLV_ID_MASK); | |
1101 | ||
1102 | return 0; | |
1103 | } | |
1104 | ||
5cb8db4a AD |
1105 | static const struct fm10k_msg_data vf_mbx_data[] = { |
1106 | FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test), | |
1107 | FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_mbx_mac_addr), | |
1108 | FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf), | |
a211e013 | 1109 | FM10K_VF_MSG_1588_HANDLER(fm10k_1588_msg_vf), |
5cb8db4a AD |
1110 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error), |
1111 | }; | |
1112 | ||
1113 | static int fm10k_mbx_request_irq_vf(struct fm10k_intfc *interface) | |
1114 | { | |
1115 | struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR]; | |
1116 | struct net_device *dev = interface->netdev; | |
1117 | struct fm10k_hw *hw = &interface->hw; | |
1118 | int err; | |
1119 | ||
1120 | /* Use timer0 for interrupt moderation on the mailbox */ | |
1121 | u32 itr = FM10K_INT_MAP_TIMER0 | entry->entry; | |
1122 | ||
1123 | /* register mailbox handlers */ | |
1124 | err = hw->mbx.ops.register_handlers(&hw->mbx, vf_mbx_data); | |
1125 | if (err) | |
1126 | return err; | |
1127 | ||
1128 | /* request the IRQ */ | |
1129 | err = request_irq(entry->vector, fm10k_msix_mbx_vf, 0, | |
1130 | dev->name, interface); | |
1131 | if (err) { | |
1132 | netif_err(interface, probe, dev, | |
1133 | "request_irq for msix_mbx failed: %d\n", err); | |
1134 | return err; | |
1135 | } | |
1136 | ||
1137 | /* map all of the interrupt sources */ | |
1138 | fm10k_write_reg(hw, FM10K_VFINT_MAP, itr); | |
1139 | ||
1140 | /* enable interrupt */ | |
1141 | fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE); | |
1142 | ||
1143 | return 0; | |
1144 | } | |
1145 | ||
18283cad AD |
1146 | static s32 fm10k_lport_map(struct fm10k_hw *hw, u32 **results, |
1147 | struct fm10k_mbx_info *mbx) | |
1148 | { | |
1149 | struct fm10k_intfc *interface; | |
1150 | u32 dglort_map = hw->mac.dglort_map; | |
1151 | s32 err; | |
1152 | ||
1153 | err = fm10k_msg_lport_map_pf(hw, results, mbx); | |
1154 | if (err) | |
1155 | return err; | |
1156 | ||
1157 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1158 | ||
1159 | /* we need to reset if port count was just updated */ | |
1160 | if (dglort_map != hw->mac.dglort_map) | |
1161 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static s32 fm10k_update_pvid(struct fm10k_hw *hw, u32 **results, | |
1167 | struct fm10k_mbx_info *mbx) | |
1168 | { | |
1169 | struct fm10k_intfc *interface; | |
1170 | u16 glort, pvid; | |
1171 | u32 pvid_update; | |
1172 | s32 err; | |
1173 | ||
1174 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], | |
1175 | &pvid_update); | |
1176 | if (err) | |
1177 | return err; | |
1178 | ||
1179 | /* extract values from the pvid update */ | |
1180 | glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); | |
1181 | pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); | |
1182 | ||
1183 | /* if glort is not valid return error */ | |
1184 | if (!fm10k_glort_valid_pf(hw, glort)) | |
1185 | return FM10K_ERR_PARAM; | |
1186 | ||
1187 | /* verify VID is valid */ | |
1188 | if (pvid >= FM10K_VLAN_TABLE_VID_MAX) | |
1189 | return FM10K_ERR_PARAM; | |
1190 | ||
1191 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1192 | ||
883a9ccb AD |
1193 | /* check to see if this belongs to one of the VFs */ |
1194 | err = fm10k_iov_update_pvid(interface, glort, pvid); | |
1195 | if (!err) | |
1196 | return 0; | |
1197 | ||
18283cad AD |
1198 | /* we need to reset if default VLAN was just updated */ |
1199 | if (pvid != hw->mac.default_vid) | |
1200 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
1201 | ||
1202 | hw->mac.default_vid = pvid; | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
a211e013 AD |
1207 | static s32 fm10k_1588_msg_pf(struct fm10k_hw *hw, u32 **results, |
1208 | struct fm10k_mbx_info *mbx) | |
1209 | { | |
1210 | struct fm10k_swapi_1588_timestamp timestamp; | |
1211 | struct fm10k_iov_data *iov_data; | |
1212 | struct fm10k_intfc *interface; | |
1213 | u16 sglort, vf_idx; | |
1214 | s32 err; | |
1215 | ||
1216 | err = fm10k_tlv_attr_get_le_struct( | |
1217 | results[FM10K_PF_ATTR_ID_1588_TIMESTAMP], | |
1218 | ×tamp, sizeof(timestamp)); | |
1219 | if (err) | |
1220 | return err; | |
1221 | ||
1222 | interface = container_of(hw, struct fm10k_intfc, hw); | |
1223 | ||
1224 | if (timestamp.dglort) { | |
1225 | fm10k_ts_tx_hwtstamp(interface, timestamp.dglort, | |
1226 | le64_to_cpu(timestamp.egress)); | |
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | /* either dglort or sglort must be set */ | |
1231 | if (!timestamp.sglort) | |
1232 | return FM10K_ERR_PARAM; | |
1233 | ||
1234 | /* verify GLORT is at least one of the ones we own */ | |
1235 | sglort = le16_to_cpu(timestamp.sglort); | |
1236 | if (!fm10k_glort_valid_pf(hw, sglort)) | |
1237 | return FM10K_ERR_PARAM; | |
1238 | ||
1239 | if (sglort == interface->glort) { | |
1240 | fm10k_ts_tx_hwtstamp(interface, 0, | |
1241 | le64_to_cpu(timestamp.ingress)); | |
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | /* if there is no iov_data then there is no mailboxes to process */ | |
1246 | if (!ACCESS_ONCE(interface->iov_data)) | |
1247 | return FM10K_ERR_PARAM; | |
1248 | ||
1249 | rcu_read_lock(); | |
1250 | ||
1251 | /* notify VF if this timestamp belongs to it */ | |
1252 | iov_data = interface->iov_data; | |
1253 | vf_idx = (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE) - sglort; | |
1254 | ||
1255 | if (!iov_data || vf_idx >= iov_data->num_vfs) { | |
1256 | err = FM10K_ERR_PARAM; | |
1257 | goto err_unlock; | |
1258 | } | |
1259 | ||
1260 | err = hw->iov.ops.report_timestamp(hw, &iov_data->vf_info[vf_idx], | |
1261 | le64_to_cpu(timestamp.ingress)); | |
1262 | ||
1263 | err_unlock: | |
1264 | rcu_read_unlock(); | |
1265 | ||
1266 | return err; | |
1267 | } | |
1268 | ||
18283cad AD |
1269 | static const struct fm10k_msg_data pf_mbx_data[] = { |
1270 | FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), | |
1271 | FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), | |
1272 | FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_lport_map), | |
1273 | FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), | |
1274 | FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), | |
1275 | FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_update_pvid), | |
a211e013 | 1276 | FM10K_PF_MSG_1588_TIMESTAMP_HANDLER(fm10k_1588_msg_pf), |
18283cad AD |
1277 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error), |
1278 | }; | |
1279 | ||
1280 | static int fm10k_mbx_request_irq_pf(struct fm10k_intfc *interface) | |
1281 | { | |
1282 | struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR]; | |
1283 | struct net_device *dev = interface->netdev; | |
1284 | struct fm10k_hw *hw = &interface->hw; | |
1285 | int err; | |
1286 | ||
1287 | /* Use timer0 for interrupt moderation on the mailbox */ | |
1288 | u32 mbx_itr = FM10K_INT_MAP_TIMER0 | entry->entry; | |
1289 | u32 other_itr = FM10K_INT_MAP_IMMEDIATE | entry->entry; | |
1290 | ||
1291 | /* register mailbox handlers */ | |
1292 | err = hw->mbx.ops.register_handlers(&hw->mbx, pf_mbx_data); | |
1293 | if (err) | |
1294 | return err; | |
1295 | ||
1296 | /* request the IRQ */ | |
1297 | err = request_irq(entry->vector, fm10k_msix_mbx_pf, 0, | |
1298 | dev->name, interface); | |
1299 | if (err) { | |
1300 | netif_err(interface, probe, dev, | |
1301 | "request_irq for msix_mbx failed: %d\n", err); | |
1302 | return err; | |
1303 | } | |
1304 | ||
1305 | /* Enable interrupts w/ no moderation for "other" interrupts */ | |
1306 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_PCIeFault), other_itr); | |
1307 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SwitchUpDown), other_itr); | |
1308 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SRAM), other_itr); | |
1309 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_MaxHoldTime), other_itr); | |
1310 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_VFLR), other_itr); | |
1311 | ||
1312 | /* Enable interrupts w/ moderation for mailbox */ | |
1313 | fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_Mailbox), mbx_itr); | |
1314 | ||
1315 | /* Enable individual interrupt causes */ | |
1316 | fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) | | |
1317 | FM10K_EIMR_ENABLE(FUM_FAULT) | | |
1318 | FM10K_EIMR_ENABLE(MAILBOX) | | |
1319 | FM10K_EIMR_ENABLE(SWITCHREADY) | | |
1320 | FM10K_EIMR_ENABLE(SWITCHNOTREADY) | | |
1321 | FM10K_EIMR_ENABLE(SRAMERROR) | | |
1322 | FM10K_EIMR_ENABLE(VFLR) | | |
1323 | FM10K_EIMR_ENABLE(MAXHOLDTIME)); | |
1324 | ||
1325 | /* enable interrupt */ | |
1326 | fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE); | |
1327 | ||
1328 | return 0; | |
1329 | } | |
1330 | ||
1331 | int fm10k_mbx_request_irq(struct fm10k_intfc *interface) | |
1332 | { | |
1333 | struct fm10k_hw *hw = &interface->hw; | |
1334 | int err; | |
1335 | ||
1336 | /* enable Mailbox cause */ | |
5cb8db4a AD |
1337 | if (hw->mac.type == fm10k_mac_pf) |
1338 | err = fm10k_mbx_request_irq_pf(interface); | |
1339 | else | |
1340 | err = fm10k_mbx_request_irq_vf(interface); | |
18283cad AD |
1341 | |
1342 | /* connect mailbox */ | |
1343 | if (!err) | |
1344 | err = hw->mbx.ops.connect(hw, &hw->mbx); | |
1345 | ||
1346 | return err; | |
1347 | } | |
1348 | ||
1349 | /** | |
1350 | * fm10k_qv_free_irq - release interrupts associated with queue vectors | |
1351 | * @interface: board private structure | |
1352 | * | |
1353 | * Release all interrupts associated with this interface | |
1354 | **/ | |
1355 | void fm10k_qv_free_irq(struct fm10k_intfc *interface) | |
1356 | { | |
1357 | int vector = interface->num_q_vectors; | |
1358 | struct fm10k_hw *hw = &interface->hw; | |
1359 | struct msix_entry *entry; | |
1360 | ||
1361 | entry = &interface->msix_entries[NON_Q_VECTORS(hw) + vector]; | |
1362 | ||
1363 | while (vector) { | |
1364 | struct fm10k_q_vector *q_vector; | |
1365 | ||
1366 | vector--; | |
1367 | entry--; | |
1368 | q_vector = interface->q_vector[vector]; | |
1369 | ||
1370 | if (!q_vector->tx.count && !q_vector->rx.count) | |
1371 | continue; | |
1372 | ||
1373 | /* disable interrupts */ | |
1374 | ||
1375 | writel(FM10K_ITR_MASK_SET, q_vector->itr); | |
1376 | ||
1377 | free_irq(entry->vector, q_vector); | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | /** | |
1382 | * fm10k_qv_request_irq - initialize interrupts for queue vectors | |
1383 | * @interface: board private structure | |
1384 | * | |
1385 | * Attempts to configure interrupts using the best available | |
1386 | * capabilities of the hardware and kernel. | |
1387 | **/ | |
1388 | int fm10k_qv_request_irq(struct fm10k_intfc *interface) | |
1389 | { | |
1390 | struct net_device *dev = interface->netdev; | |
1391 | struct fm10k_hw *hw = &interface->hw; | |
1392 | struct msix_entry *entry; | |
1393 | int ri = 0, ti = 0; | |
1394 | int vector, err; | |
1395 | ||
1396 | entry = &interface->msix_entries[NON_Q_VECTORS(hw)]; | |
1397 | ||
1398 | for (vector = 0; vector < interface->num_q_vectors; vector++) { | |
1399 | struct fm10k_q_vector *q_vector = interface->q_vector[vector]; | |
1400 | ||
1401 | /* name the vector */ | |
1402 | if (q_vector->tx.count && q_vector->rx.count) { | |
1403 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
1404 | "%s-TxRx-%d", dev->name, ri++); | |
1405 | ti++; | |
1406 | } else if (q_vector->rx.count) { | |
1407 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
1408 | "%s-rx-%d", dev->name, ri++); | |
1409 | } else if (q_vector->tx.count) { | |
1410 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, | |
1411 | "%s-tx-%d", dev->name, ti++); | |
1412 | } else { | |
1413 | /* skip this unused q_vector */ | |
1414 | continue; | |
1415 | } | |
1416 | ||
1417 | /* Assign ITR register to q_vector */ | |
5cb8db4a AD |
1418 | q_vector->itr = (hw->mac.type == fm10k_mac_pf) ? |
1419 | &interface->uc_addr[FM10K_ITR(entry->entry)] : | |
1420 | &interface->uc_addr[FM10K_VFITR(entry->entry)]; | |
18283cad AD |
1421 | |
1422 | /* request the IRQ */ | |
1423 | err = request_irq(entry->vector, &fm10k_msix_clean_rings, 0, | |
1424 | q_vector->name, q_vector); | |
1425 | if (err) { | |
1426 | netif_err(interface, probe, dev, | |
1427 | "request_irq failed for MSIX interrupt Error: %d\n", | |
1428 | err); | |
1429 | goto err_out; | |
1430 | } | |
1431 | ||
1432 | /* Enable q_vector */ | |
1433 | writel(FM10K_ITR_ENABLE, q_vector->itr); | |
1434 | ||
1435 | entry++; | |
1436 | } | |
1437 | ||
1438 | return 0; | |
1439 | ||
1440 | err_out: | |
1441 | /* wind through the ring freeing all entries and vectors */ | |
1442 | while (vector) { | |
1443 | struct fm10k_q_vector *q_vector; | |
1444 | ||
1445 | entry--; | |
1446 | vector--; | |
1447 | q_vector = interface->q_vector[vector]; | |
1448 | ||
1449 | if (!q_vector->tx.count && !q_vector->rx.count) | |
1450 | continue; | |
1451 | ||
1452 | /* disable interrupts */ | |
1453 | ||
1454 | writel(FM10K_ITR_MASK_SET, q_vector->itr); | |
1455 | ||
1456 | free_irq(entry->vector, q_vector); | |
1457 | } | |
1458 | ||
1459 | return err; | |
1460 | } | |
1461 | ||
504c5eac AD |
1462 | void fm10k_up(struct fm10k_intfc *interface) |
1463 | { | |
1464 | struct fm10k_hw *hw = &interface->hw; | |
1465 | ||
1466 | /* Enable Tx/Rx DMA */ | |
1467 | hw->mac.ops.start_hw(hw); | |
1468 | ||
3abaae42 AD |
1469 | /* configure Tx descriptor rings */ |
1470 | fm10k_configure_tx(interface); | |
1471 | ||
1472 | /* configure Rx descriptor rings */ | |
1473 | fm10k_configure_rx(interface); | |
1474 | ||
504c5eac AD |
1475 | /* configure interrupts */ |
1476 | hw->mac.ops.update_int_moderator(hw); | |
1477 | ||
1478 | /* clear down bit to indicate we are ready to go */ | |
1479 | clear_bit(__FM10K_DOWN, &interface->state); | |
1480 | ||
18283cad AD |
1481 | /* enable polling cleanups */ |
1482 | fm10k_napi_enable_all(interface); | |
1483 | ||
504c5eac AD |
1484 | /* re-establish Rx filters */ |
1485 | fm10k_restore_rx_state(interface); | |
1486 | ||
1487 | /* enable transmits */ | |
1488 | netif_tx_start_all_queues(interface->netdev); | |
b7d8514c AD |
1489 | |
1490 | /* kick off the service timer */ | |
4d419156 | 1491 | hw->mac.get_host_state = 1; |
b7d8514c | 1492 | mod_timer(&interface->service_timer, jiffies); |
504c5eac AD |
1493 | } |
1494 | ||
18283cad AD |
1495 | static void fm10k_napi_disable_all(struct fm10k_intfc *interface) |
1496 | { | |
1497 | struct fm10k_q_vector *q_vector; | |
1498 | int q_idx; | |
1499 | ||
1500 | for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) { | |
1501 | q_vector = interface->q_vector[q_idx]; | |
1502 | napi_disable(&q_vector->napi); | |
1503 | } | |
1504 | } | |
1505 | ||
504c5eac AD |
1506 | void fm10k_down(struct fm10k_intfc *interface) |
1507 | { | |
1508 | struct net_device *netdev = interface->netdev; | |
1509 | struct fm10k_hw *hw = &interface->hw; | |
1510 | ||
1511 | /* signal that we are down to the interrupt handler and service task */ | |
1512 | set_bit(__FM10K_DOWN, &interface->state); | |
1513 | ||
1514 | /* call carrier off first to avoid false dev_watchdog timeouts */ | |
1515 | netif_carrier_off(netdev); | |
1516 | ||
1517 | /* disable transmits */ | |
1518 | netif_tx_stop_all_queues(netdev); | |
1519 | netif_tx_disable(netdev); | |
1520 | ||
1521 | /* reset Rx filters */ | |
1522 | fm10k_reset_rx_state(interface); | |
1523 | ||
1524 | /* allow 10ms for device to quiesce */ | |
1525 | usleep_range(10000, 20000); | |
1526 | ||
18283cad AD |
1527 | /* disable polling routines */ |
1528 | fm10k_napi_disable_all(interface); | |
1529 | ||
b7d8514c AD |
1530 | del_timer_sync(&interface->service_timer); |
1531 | ||
1532 | /* capture stats one last time before stopping interface */ | |
1533 | fm10k_update_stats(interface); | |
1534 | ||
504c5eac AD |
1535 | /* Disable DMA engine for Tx/Rx */ |
1536 | hw->mac.ops.stop_hw(hw); | |
3abaae42 AD |
1537 | |
1538 | /* free any buffers still on the rings */ | |
1539 | fm10k_clean_all_tx_rings(interface); | |
504c5eac AD |
1540 | } |
1541 | ||
0e7b3644 AD |
1542 | /** |
1543 | * fm10k_sw_init - Initialize general software structures | |
1544 | * @interface: host interface private structure to initialize | |
1545 | * | |
1546 | * fm10k_sw_init initializes the interface private data structure. | |
1547 | * Fields are initialized based on PCI device information and | |
1548 | * OS network device settings (MTU size). | |
1549 | **/ | |
1550 | static int fm10k_sw_init(struct fm10k_intfc *interface, | |
1551 | const struct pci_device_id *ent) | |
1552 | { | |
0e7b3644 AD |
1553 | const struct fm10k_info *fi = fm10k_info_tbl[ent->driver_data]; |
1554 | struct fm10k_hw *hw = &interface->hw; | |
1555 | struct pci_dev *pdev = interface->pdev; | |
1556 | struct net_device *netdev = interface->netdev; | |
c41a4fba | 1557 | u32 rss_key[FM10K_RSSRK_SIZE]; |
0e7b3644 AD |
1558 | unsigned int rss; |
1559 | int err; | |
1560 | ||
1561 | /* initialize back pointer */ | |
1562 | hw->back = interface; | |
1563 | hw->hw_addr = interface->uc_addr; | |
1564 | ||
1565 | /* PCI config space info */ | |
1566 | hw->vendor_id = pdev->vendor; | |
1567 | hw->device_id = pdev->device; | |
1568 | hw->revision_id = pdev->revision; | |
1569 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
1570 | hw->subsystem_device_id = pdev->subsystem_device; | |
1571 | ||
1572 | /* Setup hw api */ | |
1573 | memcpy(&hw->mac.ops, fi->mac_ops, sizeof(hw->mac.ops)); | |
1574 | hw->mac.type = fi->mac; | |
1575 | ||
883a9ccb AD |
1576 | /* Setup IOV handlers */ |
1577 | if (fi->iov_ops) | |
1578 | memcpy(&hw->iov.ops, fi->iov_ops, sizeof(hw->iov.ops)); | |
1579 | ||
0e7b3644 AD |
1580 | /* Set common capability flags and settings */ |
1581 | rss = min_t(int, FM10K_MAX_RSS_INDICES, num_online_cpus()); | |
1582 | interface->ring_feature[RING_F_RSS].limit = rss; | |
1583 | fi->get_invariants(hw); | |
1584 | ||
1585 | /* pick up the PCIe bus settings for reporting later */ | |
1586 | if (hw->mac.ops.get_bus_info) | |
1587 | hw->mac.ops.get_bus_info(hw); | |
1588 | ||
1589 | /* limit the usable DMA range */ | |
1590 | if (hw->mac.ops.set_dma_mask) | |
1591 | hw->mac.ops.set_dma_mask(hw, dma_get_mask(&pdev->dev)); | |
1592 | ||
1593 | /* update netdev with DMA restrictions */ | |
1594 | if (dma_get_mask(&pdev->dev) > DMA_BIT_MASK(32)) { | |
1595 | netdev->features |= NETIF_F_HIGHDMA; | |
1596 | netdev->vlan_features |= NETIF_F_HIGHDMA; | |
1597 | } | |
1598 | ||
b7d8514c AD |
1599 | /* delay any future reset requests */ |
1600 | interface->last_reset = jiffies + (10 * HZ); | |
1601 | ||
0e7b3644 AD |
1602 | /* reset and initialize the hardware so it is in a known state */ |
1603 | err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw); | |
1604 | if (err) { | |
1605 | dev_err(&pdev->dev, "init_hw failed: %d\n", err); | |
1606 | return err; | |
1607 | } | |
1608 | ||
1609 | /* initialize hardware statistics */ | |
1610 | hw->mac.ops.update_hw_stats(hw, &interface->stats); | |
1611 | ||
883a9ccb AD |
1612 | /* Set upper limit on IOV VFs that can be allocated */ |
1613 | pci_sriov_set_totalvfs(pdev, hw->iov.total_vfs); | |
1614 | ||
0e7b3644 AD |
1615 | /* Start with random Ethernet address */ |
1616 | eth_random_addr(hw->mac.addr); | |
1617 | ||
1618 | /* Initialize MAC address from hardware */ | |
1619 | err = hw->mac.ops.read_mac_addr(hw); | |
1620 | if (err) { | |
1621 | dev_warn(&pdev->dev, | |
1622 | "Failed to obtain MAC address defaulting to random\n"); | |
1623 | /* tag address assignment as random */ | |
1624 | netdev->addr_assign_type |= NET_ADDR_RANDOM; | |
1625 | } | |
1626 | ||
1627 | memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); | |
1628 | memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); | |
1629 | ||
1630 | if (!is_valid_ether_addr(netdev->perm_addr)) { | |
1631 | dev_err(&pdev->dev, "Invalid MAC Address\n"); | |
1632 | return -EIO; | |
1633 | } | |
1634 | ||
a211e013 AD |
1635 | /* assign BAR 4 resources for use with PTP */ |
1636 | if (fm10k_read_reg(hw, FM10K_CTRL) & FM10K_CTRL_BAR4_ALLOWED) | |
1637 | interface->sw_addr = ioremap(pci_resource_start(pdev, 4), | |
1638 | pci_resource_len(pdev, 4)); | |
1639 | hw->sw_addr = interface->sw_addr; | |
1640 | ||
0e7b3644 AD |
1641 | /* Only the PF can support VXLAN and NVGRE offloads */ |
1642 | if (hw->mac.type != fm10k_mac_pf) { | |
1643 | netdev->hw_enc_features = 0; | |
1644 | netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL; | |
1645 | netdev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL; | |
1646 | } | |
1647 | ||
9f801abc AD |
1648 | /* initialize DCBNL interface */ |
1649 | fm10k_dcbnl_set_ops(netdev); | |
1650 | ||
b7d8514c AD |
1651 | /* Initialize service timer and service task */ |
1652 | set_bit(__FM10K_SERVICE_DISABLE, &interface->state); | |
1653 | setup_timer(&interface->service_timer, &fm10k_service_timer, | |
1654 | (unsigned long)interface); | |
1655 | INIT_WORK(&interface->service_task, fm10k_service_task); | |
1656 | ||
a211e013 AD |
1657 | /* Intitialize timestamp data */ |
1658 | fm10k_ts_init(interface); | |
1659 | ||
e27ef599 AD |
1660 | /* set default ring sizes */ |
1661 | interface->tx_ring_count = FM10K_DEFAULT_TXD; | |
1662 | interface->rx_ring_count = FM10K_DEFAULT_RXD; | |
1663 | ||
18283cad AD |
1664 | /* set default interrupt moderation */ |
1665 | interface->tx_itr = FM10K_ITR_10K; | |
1666 | interface->rx_itr = FM10K_ITR_ADAPTIVE | FM10K_ITR_20K; | |
1667 | ||
0e7b3644 AD |
1668 | /* initialize vxlan_port list */ |
1669 | INIT_LIST_HEAD(&interface->vxlan_port); | |
1670 | ||
c41a4fba ED |
1671 | netdev_rss_key_fill(rss_key, sizeof(rss_key)); |
1672 | memcpy(interface->rssrk, rss_key, sizeof(rss_key)); | |
0e7b3644 AD |
1673 | |
1674 | /* Start off interface as being down */ | |
1675 | set_bit(__FM10K_DOWN, &interface->state); | |
1676 | ||
1677 | return 0; | |
1678 | } | |
1679 | ||
1680 | static void fm10k_slot_warn(struct fm10k_intfc *interface) | |
1681 | { | |
1682 | struct device *dev = &interface->pdev->dev; | |
1683 | struct fm10k_hw *hw = &interface->hw; | |
1684 | ||
1685 | if (hw->mac.ops.is_slot_appropriate(hw)) | |
1686 | return; | |
1687 | ||
1688 | dev_warn(dev, | |
1689 | "For optimal performance, a %s %s slot is recommended.\n", | |
1690 | (hw->bus_caps.width == fm10k_bus_width_pcie_x1 ? "x1" : | |
1691 | hw->bus_caps.width == fm10k_bus_width_pcie_x4 ? "x4" : | |
1692 | "x8"), | |
1693 | (hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s" : | |
1694 | hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s" : | |
1695 | "8.0GT/s")); | |
1696 | dev_warn(dev, | |
1697 | "A slot with more lanes and/or higher speed is suggested.\n"); | |
1698 | } | |
1699 | ||
b3890e30 AD |
1700 | /** |
1701 | * fm10k_probe - Device Initialization Routine | |
1702 | * @pdev: PCI device information struct | |
1703 | * @ent: entry in fm10k_pci_tbl | |
1704 | * | |
1705 | * Returns 0 on success, negative on failure | |
1706 | * | |
1707 | * fm10k_probe initializes an interface identified by a pci_dev structure. | |
1708 | * The OS initialization, configuring of the interface private structure, | |
1709 | * and a hardware reset occur. | |
1710 | **/ | |
1711 | static int fm10k_probe(struct pci_dev *pdev, | |
1712 | const struct pci_device_id *ent) | |
1713 | { | |
0e7b3644 AD |
1714 | struct net_device *netdev; |
1715 | struct fm10k_intfc *interface; | |
1716 | struct fm10k_hw *hw; | |
b3890e30 AD |
1717 | int err; |
1718 | u64 dma_mask; | |
1719 | ||
1720 | err = pci_enable_device_mem(pdev); | |
1721 | if (err) | |
1722 | return err; | |
1723 | ||
1724 | /* By default fm10k only supports a 48 bit DMA mask */ | |
1725 | dma_mask = DMA_BIT_MASK(48) | dma_get_required_mask(&pdev->dev); | |
1726 | ||
1727 | if ((dma_mask <= DMA_BIT_MASK(32)) || | |
1728 | dma_set_mask_and_coherent(&pdev->dev, dma_mask)) { | |
1729 | dma_mask &= DMA_BIT_MASK(32); | |
1730 | ||
1731 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
1732 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); | |
1733 | if (err) { | |
1734 | err = dma_set_coherent_mask(&pdev->dev, | |
1735 | DMA_BIT_MASK(32)); | |
1736 | if (err) { | |
1737 | dev_err(&pdev->dev, | |
1738 | "No usable DMA configuration, aborting\n"); | |
1739 | goto err_dma; | |
1740 | } | |
1741 | } | |
1742 | } | |
1743 | ||
1744 | err = pci_request_selected_regions(pdev, | |
1745 | pci_select_bars(pdev, | |
1746 | IORESOURCE_MEM), | |
1747 | fm10k_driver_name); | |
1748 | if (err) { | |
1749 | dev_err(&pdev->dev, | |
1750 | "pci_request_selected_regions failed 0x%x\n", err); | |
1751 | goto err_pci_reg; | |
1752 | } | |
1753 | ||
19ae1b3f AD |
1754 | pci_enable_pcie_error_reporting(pdev); |
1755 | ||
b3890e30 AD |
1756 | pci_set_master(pdev); |
1757 | pci_save_state(pdev); | |
1758 | ||
0e7b3644 AD |
1759 | netdev = fm10k_alloc_netdev(); |
1760 | if (!netdev) { | |
1761 | err = -ENOMEM; | |
1762 | goto err_alloc_netdev; | |
1763 | } | |
1764 | ||
1765 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1766 | ||
1767 | interface = netdev_priv(netdev); | |
1768 | pci_set_drvdata(pdev, interface); | |
1769 | ||
1770 | interface->netdev = netdev; | |
1771 | interface->pdev = pdev; | |
1772 | hw = &interface->hw; | |
1773 | ||
1774 | interface->uc_addr = ioremap(pci_resource_start(pdev, 0), | |
1775 | FM10K_UC_ADDR_SIZE); | |
1776 | if (!interface->uc_addr) { | |
1777 | err = -EIO; | |
1778 | goto err_ioremap; | |
1779 | } | |
1780 | ||
1781 | err = fm10k_sw_init(interface, ent); | |
1782 | if (err) | |
1783 | goto err_sw_init; | |
1784 | ||
7461fd91 AD |
1785 | /* enable debugfs support */ |
1786 | fm10k_dbg_intfc_init(interface); | |
1787 | ||
18283cad AD |
1788 | err = fm10k_init_queueing_scheme(interface); |
1789 | if (err) | |
1790 | goto err_sw_init; | |
1791 | ||
1792 | err = fm10k_mbx_request_irq(interface); | |
1793 | if (err) | |
1794 | goto err_mbx_interrupt; | |
1795 | ||
0e7b3644 AD |
1796 | /* final check of hardware state before registering the interface */ |
1797 | err = fm10k_hw_ready(interface); | |
1798 | if (err) | |
1799 | goto err_register; | |
1800 | ||
1801 | err = register_netdev(netdev); | |
1802 | if (err) | |
1803 | goto err_register; | |
1804 | ||
1805 | /* carrier off reporting is important to ethtool even BEFORE open */ | |
1806 | netif_carrier_off(netdev); | |
1807 | ||
1808 | /* stop all the transmit queues from transmitting until link is up */ | |
1809 | netif_tx_stop_all_queues(netdev); | |
1810 | ||
a211e013 AD |
1811 | /* Register PTP interface */ |
1812 | fm10k_ptp_register(interface); | |
1813 | ||
0e7b3644 AD |
1814 | /* print bus type/speed/width info */ |
1815 | dev_info(&pdev->dev, "(PCI Express:%s Width: %s Payload: %s)\n", | |
1816 | (hw->bus.speed == fm10k_bus_speed_8000 ? "8.0GT/s" : | |
1817 | hw->bus.speed == fm10k_bus_speed_5000 ? "5.0GT/s" : | |
1818 | hw->bus.speed == fm10k_bus_speed_2500 ? "2.5GT/s" : | |
1819 | "Unknown"), | |
1820 | (hw->bus.width == fm10k_bus_width_pcie_x8 ? "x8" : | |
1821 | hw->bus.width == fm10k_bus_width_pcie_x4 ? "x4" : | |
1822 | hw->bus.width == fm10k_bus_width_pcie_x1 ? "x1" : | |
1823 | "Unknown"), | |
1824 | (hw->bus.payload == fm10k_bus_payload_128 ? "128B" : | |
1825 | hw->bus.payload == fm10k_bus_payload_256 ? "256B" : | |
1826 | hw->bus.payload == fm10k_bus_payload_512 ? "512B" : | |
1827 | "Unknown")); | |
1828 | ||
1829 | /* print warning for non-optimal configurations */ | |
1830 | fm10k_slot_warn(interface); | |
1831 | ||
883a9ccb AD |
1832 | /* enable SR-IOV after registering netdev to enforce PF/VF ordering */ |
1833 | fm10k_iov_configure(pdev, 0); | |
1834 | ||
b7d8514c AD |
1835 | /* clear the service task disable bit to allow service task to start */ |
1836 | clear_bit(__FM10K_SERVICE_DISABLE, &interface->state); | |
1837 | ||
b3890e30 AD |
1838 | return 0; |
1839 | ||
0e7b3644 | 1840 | err_register: |
18283cad AD |
1841 | fm10k_mbx_free_irq(interface); |
1842 | err_mbx_interrupt: | |
1843 | fm10k_clear_queueing_scheme(interface); | |
0e7b3644 | 1844 | err_sw_init: |
a211e013 AD |
1845 | if (interface->sw_addr) |
1846 | iounmap(interface->sw_addr); | |
0e7b3644 AD |
1847 | iounmap(interface->uc_addr); |
1848 | err_ioremap: | |
1849 | free_netdev(netdev); | |
1850 | err_alloc_netdev: | |
1851 | pci_release_selected_regions(pdev, | |
1852 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
b3890e30 AD |
1853 | err_pci_reg: |
1854 | err_dma: | |
1855 | pci_disable_device(pdev); | |
1856 | return err; | |
1857 | } | |
1858 | ||
1859 | /** | |
1860 | * fm10k_remove - Device Removal Routine | |
1861 | * @pdev: PCI device information struct | |
1862 | * | |
1863 | * fm10k_remove is called by the PCI subsystem to alert the driver | |
1864 | * that it should release a PCI device. The could be caused by a | |
1865 | * Hot-Plug event, or because the driver is going to be removed from | |
1866 | * memory. | |
1867 | **/ | |
1868 | static void fm10k_remove(struct pci_dev *pdev) | |
1869 | { | |
0e7b3644 AD |
1870 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); |
1871 | struct net_device *netdev = interface->netdev; | |
1872 | ||
b7d8514c AD |
1873 | set_bit(__FM10K_SERVICE_DISABLE, &interface->state); |
1874 | cancel_work_sync(&interface->service_task); | |
1875 | ||
0e7b3644 AD |
1876 | /* free netdev, this may bounce the interrupts due to setup_tc */ |
1877 | if (netdev->reg_state == NETREG_REGISTERED) | |
1878 | unregister_netdev(netdev); | |
1879 | ||
a211e013 AD |
1880 | /* cleanup timestamp handling */ |
1881 | fm10k_ptp_unregister(interface); | |
1882 | ||
883a9ccb AD |
1883 | /* release VFs */ |
1884 | fm10k_iov_disable(pdev); | |
1885 | ||
18283cad AD |
1886 | /* disable mailbox interrupt */ |
1887 | fm10k_mbx_free_irq(interface); | |
1888 | ||
1889 | /* free interrupts */ | |
1890 | fm10k_clear_queueing_scheme(interface); | |
1891 | ||
7461fd91 AD |
1892 | /* remove any debugfs interfaces */ |
1893 | fm10k_dbg_intfc_exit(interface); | |
1894 | ||
a211e013 AD |
1895 | if (interface->sw_addr) |
1896 | iounmap(interface->sw_addr); | |
0e7b3644 AD |
1897 | iounmap(interface->uc_addr); |
1898 | ||
1899 | free_netdev(netdev); | |
1900 | ||
b3890e30 AD |
1901 | pci_release_selected_regions(pdev, |
1902 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
1903 | ||
19ae1b3f AD |
1904 | pci_disable_pcie_error_reporting(pdev); |
1905 | ||
b3890e30 AD |
1906 | pci_disable_device(pdev); |
1907 | } | |
1908 | ||
19ae1b3f AD |
1909 | #ifdef CONFIG_PM |
1910 | /** | |
1911 | * fm10k_resume - Restore device to pre-sleep state | |
1912 | * @pdev: PCI device information struct | |
1913 | * | |
1914 | * fm10k_resume is called after the system has powered back up from a sleep | |
1915 | * state and is ready to resume operation. This function is meant to restore | |
1916 | * the device back to its pre-sleep state. | |
1917 | **/ | |
1918 | static int fm10k_resume(struct pci_dev *pdev) | |
1919 | { | |
1920 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); | |
1921 | struct net_device *netdev = interface->netdev; | |
1922 | struct fm10k_hw *hw = &interface->hw; | |
1923 | u32 err; | |
1924 | ||
1925 | pci_set_power_state(pdev, PCI_D0); | |
1926 | pci_restore_state(pdev); | |
1927 | ||
1928 | /* pci_restore_state clears dev->state_saved so call | |
1929 | * pci_save_state to restore it. | |
1930 | */ | |
1931 | pci_save_state(pdev); | |
1932 | ||
1933 | err = pci_enable_device_mem(pdev); | |
1934 | if (err) { | |
1935 | dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n"); | |
1936 | return err; | |
1937 | } | |
1938 | pci_set_master(pdev); | |
1939 | ||
1940 | pci_wake_from_d3(pdev, false); | |
1941 | ||
1942 | /* refresh hw_addr in case it was dropped */ | |
1943 | hw->hw_addr = interface->uc_addr; | |
1944 | ||
1945 | /* reset hardware to known state */ | |
1946 | err = hw->mac.ops.init_hw(&interface->hw); | |
1947 | if (err) | |
1948 | return err; | |
1949 | ||
1950 | /* reset statistics starting values */ | |
1951 | hw->mac.ops.rebind_hw_stats(hw, &interface->stats); | |
1952 | ||
a211e013 AD |
1953 | /* reset clock */ |
1954 | fm10k_ts_reset(interface); | |
1955 | ||
19ae1b3f AD |
1956 | rtnl_lock(); |
1957 | ||
1958 | err = fm10k_init_queueing_scheme(interface); | |
1959 | if (!err) { | |
1960 | fm10k_mbx_request_irq(interface); | |
1961 | if (netif_running(netdev)) | |
1962 | err = fm10k_open(netdev); | |
1963 | } | |
1964 | ||
1965 | rtnl_unlock(); | |
1966 | ||
1967 | if (err) | |
1968 | return err; | |
1969 | ||
883a9ccb AD |
1970 | /* restore SR-IOV interface */ |
1971 | fm10k_iov_resume(pdev); | |
1972 | ||
19ae1b3f AD |
1973 | netif_device_attach(netdev); |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | /** | |
1979 | * fm10k_suspend - Prepare the device for a system sleep state | |
1980 | * @pdev: PCI device information struct | |
1981 | * | |
1982 | * fm10k_suspend is meant to shutdown the device prior to the system entering | |
1983 | * a sleep state. The fm10k hardware does not support wake on lan so the | |
1984 | * driver simply needs to shut down the device so it is in a low power state. | |
1985 | **/ | |
1986 | static int fm10k_suspend(struct pci_dev *pdev, pm_message_t state) | |
1987 | { | |
1988 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); | |
1989 | struct net_device *netdev = interface->netdev; | |
1990 | int err = 0; | |
1991 | ||
1992 | netif_device_detach(netdev); | |
1993 | ||
883a9ccb AD |
1994 | fm10k_iov_suspend(pdev); |
1995 | ||
19ae1b3f AD |
1996 | rtnl_lock(); |
1997 | ||
1998 | if (netif_running(netdev)) | |
1999 | fm10k_close(netdev); | |
2000 | ||
2001 | fm10k_mbx_free_irq(interface); | |
2002 | ||
2003 | fm10k_clear_queueing_scheme(interface); | |
2004 | ||
2005 | rtnl_unlock(); | |
2006 | ||
2007 | err = pci_save_state(pdev); | |
2008 | if (err) | |
2009 | return err; | |
2010 | ||
2011 | pci_disable_device(pdev); | |
2012 | pci_wake_from_d3(pdev, false); | |
2013 | pci_set_power_state(pdev, PCI_D3hot); | |
2014 | ||
2015 | return 0; | |
2016 | } | |
2017 | ||
2018 | #endif /* CONFIG_PM */ | |
2019 | /** | |
2020 | * fm10k_io_error_detected - called when PCI error is detected | |
2021 | * @pdev: Pointer to PCI device | |
2022 | * @state: The current pci connection state | |
2023 | * | |
2024 | * This function is called after a PCI bus error affecting | |
2025 | * this device has been detected. | |
2026 | */ | |
2027 | static pci_ers_result_t fm10k_io_error_detected(struct pci_dev *pdev, | |
2028 | pci_channel_state_t state) | |
2029 | { | |
2030 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); | |
2031 | struct net_device *netdev = interface->netdev; | |
2032 | ||
2033 | netif_device_detach(netdev); | |
2034 | ||
2035 | if (state == pci_channel_io_perm_failure) | |
2036 | return PCI_ERS_RESULT_DISCONNECT; | |
2037 | ||
2038 | if (netif_running(netdev)) | |
2039 | fm10k_close(netdev); | |
2040 | ||
2041 | fm10k_mbx_free_irq(interface); | |
2042 | ||
2043 | pci_disable_device(pdev); | |
2044 | ||
2045 | /* Request a slot reset. */ | |
2046 | return PCI_ERS_RESULT_NEED_RESET; | |
2047 | } | |
2048 | ||
2049 | /** | |
2050 | * fm10k_io_slot_reset - called after the pci bus has been reset. | |
2051 | * @pdev: Pointer to PCI device | |
2052 | * | |
2053 | * Restart the card from scratch, as if from a cold-boot. | |
2054 | */ | |
2055 | static pci_ers_result_t fm10k_io_slot_reset(struct pci_dev *pdev) | |
2056 | { | |
2057 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); | |
2058 | pci_ers_result_t result; | |
2059 | ||
2060 | if (pci_enable_device_mem(pdev)) { | |
2061 | dev_err(&pdev->dev, | |
2062 | "Cannot re-enable PCI device after reset.\n"); | |
2063 | result = PCI_ERS_RESULT_DISCONNECT; | |
2064 | } else { | |
2065 | pci_set_master(pdev); | |
2066 | pci_restore_state(pdev); | |
2067 | ||
2068 | /* After second error pci->state_saved is false, this | |
2069 | * resets it so EEH doesn't break. | |
2070 | */ | |
2071 | pci_save_state(pdev); | |
2072 | ||
2073 | pci_wake_from_d3(pdev, false); | |
2074 | ||
2075 | /* refresh hw_addr in case it was dropped */ | |
2076 | interface->hw.hw_addr = interface->uc_addr; | |
2077 | ||
2078 | interface->flags |= FM10K_FLAG_RESET_REQUESTED; | |
2079 | fm10k_service_event_schedule(interface); | |
2080 | ||
2081 | result = PCI_ERS_RESULT_RECOVERED; | |
2082 | } | |
2083 | ||
2084 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2085 | ||
2086 | return result; | |
2087 | } | |
2088 | ||
2089 | /** | |
2090 | * fm10k_io_resume - called when traffic can start flowing again. | |
2091 | * @pdev: Pointer to PCI device | |
2092 | * | |
2093 | * This callback is called when the error recovery driver tells us that | |
2094 | * its OK to resume normal operation. | |
2095 | */ | |
2096 | static void fm10k_io_resume(struct pci_dev *pdev) | |
2097 | { | |
2098 | struct fm10k_intfc *interface = pci_get_drvdata(pdev); | |
2099 | struct net_device *netdev = interface->netdev; | |
2100 | struct fm10k_hw *hw = &interface->hw; | |
2101 | int err = 0; | |
2102 | ||
2103 | /* reset hardware to known state */ | |
2104 | hw->mac.ops.init_hw(&interface->hw); | |
2105 | ||
2106 | /* reset statistics starting values */ | |
2107 | hw->mac.ops.rebind_hw_stats(hw, &interface->stats); | |
2108 | ||
2109 | /* reassociate interrupts */ | |
2110 | fm10k_mbx_request_irq(interface); | |
2111 | ||
a211e013 AD |
2112 | /* reset clock */ |
2113 | fm10k_ts_reset(interface); | |
2114 | ||
19ae1b3f AD |
2115 | if (netif_running(netdev)) |
2116 | err = fm10k_open(netdev); | |
2117 | ||
2118 | /* final check of hardware state before registering the interface */ | |
2119 | err = err ? : fm10k_hw_ready(interface); | |
2120 | ||
2121 | if (!err) | |
2122 | netif_device_attach(netdev); | |
2123 | } | |
2124 | ||
2125 | static const struct pci_error_handlers fm10k_err_handler = { | |
2126 | .error_detected = fm10k_io_error_detected, | |
2127 | .slot_reset = fm10k_io_slot_reset, | |
2128 | .resume = fm10k_io_resume, | |
2129 | }; | |
2130 | ||
b3890e30 AD |
2131 | static struct pci_driver fm10k_driver = { |
2132 | .name = fm10k_driver_name, | |
2133 | .id_table = fm10k_pci_tbl, | |
2134 | .probe = fm10k_probe, | |
2135 | .remove = fm10k_remove, | |
19ae1b3f AD |
2136 | #ifdef CONFIG_PM |
2137 | .suspend = fm10k_suspend, | |
2138 | .resume = fm10k_resume, | |
2139 | #endif | |
883a9ccb | 2140 | .sriov_configure = fm10k_iov_configure, |
19ae1b3f | 2141 | .err_handler = &fm10k_err_handler |
b3890e30 AD |
2142 | }; |
2143 | ||
2144 | /** | |
2145 | * fm10k_register_pci_driver - register driver interface | |
2146 | * | |
2147 | * This funciton is called on module load in order to register the driver. | |
2148 | **/ | |
2149 | int fm10k_register_pci_driver(void) | |
2150 | { | |
2151 | return pci_register_driver(&fm10k_driver); | |
2152 | } | |
2153 | ||
2154 | /** | |
2155 | * fm10k_unregister_pci_driver - unregister driver interface | |
2156 | * | |
2157 | * This funciton is called on module unload in order to remove the driver. | |
2158 | **/ | |
2159 | void fm10k_unregister_pci_driver(void) | |
2160 | { | |
2161 | pci_unregister_driver(&fm10k_driver); | |
2162 | } |