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fm10k: Add support for SR-IOV to PF core files
[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k_pci.c
CommitLineData
b3890e30
AD		 1/* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#include <linux/module.h>
19ae1b3f 22#include <linux/aer.h>
b3890e30
AD		 23
24#include "fm10k.h"
25
0e7b3644
AD		 26static const struct fm10k_info *fm10k_info_tbl[] = {
27 [fm10k_device_pf] = &fm10k_pf_info,
5cb8db4a 28 [fm10k_device_vf] = &fm10k_vf_info,
0e7b3644
AD		 29};
30
b3890e30
AD		 31/**
32 * fm10k_pci_tbl - PCI Device ID Table
33 *
34 * Wildcard entries (PCI_ANY_ID) should come last
35 * Last entry must be all 0s
36 *
37 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
38 * Class, Class Mask, private data (not used) }
39 */
40static const struct pci_device_id fm10k_pci_tbl[] = {
0e7b3644 41 { PCI_VDEVICE(INTEL, FM10K_DEV_ID_PF), fm10k_device_pf },
5cb8db4a 42 { PCI_VDEVICE(INTEL, FM10K_DEV_ID_VF), fm10k_device_vf },
b3890e30
AD		 43 /* required last entry */
44 { 0, }
45};
46MODULE_DEVICE_TABLE(pci, fm10k_pci_tbl);
47
04a5aefb
AD		 48u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg)
49{
50 struct fm10k_intfc *interface = hw->back;
51 u16 value = 0;
52
53 if (FM10K_REMOVED(hw->hw_addr))
54 return ~value;
55
56 pci_read_config_word(interface->pdev, reg, &value);
57 if (value == 0xFFFF)
58 fm10k_write_flush(hw);
59
60 return value;
61}
62
63u32 fm10k_read_reg(struct fm10k_hw *hw, int reg)
64{
65 u32 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
66 u32 value = 0;
67
68 if (FM10K_REMOVED(hw_addr))
69 return ~value;
70
71 value = readl(&hw_addr[reg]);
0e7b3644
AD		 72 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
73 struct fm10k_intfc *interface = hw->back;
74 struct net_device *netdev = interface->netdev;
75
04a5aefb 76 hw->hw_addr = NULL;
0e7b3644
AD		 77 netif_device_detach(netdev);
78 netdev_err(netdev, "PCIe link lost, device now detached\n");
79 }
04a5aefb
AD		 80
81 return value;
82}
83
0e7b3644
AD		 84static int fm10k_hw_ready(struct fm10k_intfc *interface)
85{
86 struct fm10k_hw *hw = &interface->hw;
87
88 fm10k_write_flush(hw);
89
90 return FM10K_REMOVED(hw->hw_addr) ? -ENODEV : 0;
91}
92
b7d8514c
AD		 93void fm10k_service_event_schedule(struct fm10k_intfc *interface)
94{
95 if (!test_bit(__FM10K_SERVICE_DISABLE, &interface->state) &&
96 !test_and_set_bit(__FM10K_SERVICE_SCHED, &interface->state))
97 schedule_work(&interface->service_task);
98}
99
100static void fm10k_service_event_complete(struct fm10k_intfc *interface)
101{
102 BUG_ON(!test_bit(__FM10K_SERVICE_SCHED, &interface->state));
103
104 /* flush memory to make sure state is correct before next watchog */
105 smp_mb__before_atomic();
106 clear_bit(__FM10K_SERVICE_SCHED, &interface->state);
107}
108
109/**
110 * fm10k_service_timer - Timer Call-back
111 * @data: pointer to interface cast into an unsigned long
112 **/
113static void fm10k_service_timer(unsigned long data)
114{
115 struct fm10k_intfc *interface = (struct fm10k_intfc *)data;
116
117 /* Reset the timer */
118 mod_timer(&interface->service_timer, (HZ * 2) + jiffies);
119
120 fm10k_service_event_schedule(interface);
121}
122
123static void fm10k_detach_subtask(struct fm10k_intfc *interface)
124{
125 struct net_device *netdev = interface->netdev;
126
127 /* do nothing if device is still present or hw_addr is set */
128 if (netif_device_present(netdev) || interface->hw.hw_addr)
129 return;
130
131 rtnl_lock();
132
133 if (netif_running(netdev))
134 dev_close(netdev);
135
136 rtnl_unlock();
137}
138
139static void fm10k_reinit(struct fm10k_intfc *interface)
140{
141 struct net_device *netdev = interface->netdev;
142 struct fm10k_hw *hw = &interface->hw;
143 int err;
144
145 WARN_ON(in_interrupt());
146
147 /* put off any impending NetWatchDogTimeout */
148 netdev->trans_start = jiffies;
149
150 while (test_and_set_bit(__FM10K_RESETTING, &interface->state))
151 usleep_range(1000, 2000);
152
153 rtnl_lock();
154
155 if (netif_running(netdev))
156 fm10k_close(netdev);
157
158 fm10k_mbx_free_irq(interface);
159
160 /* delay any future reset requests */
161 interface->last_reset = jiffies + (10 * HZ);
162
163 /* reset and initialize the hardware so it is in a known state */
164 err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw);
165 if (err)
166 dev_err(&interface->pdev->dev, "init_hw failed: %d\n", err);
167
168 /* reassociate interrupts */
169 fm10k_mbx_request_irq(interface);
170
171 if (netif_running(netdev))
172 fm10k_open(netdev);
173
174 rtnl_unlock();
175
176 clear_bit(__FM10K_RESETTING, &interface->state);
177}
178
179static void fm10k_reset_subtask(struct fm10k_intfc *interface)
180{
181 if (!(interface->flags & FM10K_FLAG_RESET_REQUESTED))
182 return;
183
184 interface->flags &= ~FM10K_FLAG_RESET_REQUESTED;
185
186 netdev_err(interface->netdev, "Reset interface\n");
187 interface->tx_timeout_count++;
188
189 fm10k_reinit(interface);
190}
191
192/**
193 * fm10k_configure_swpri_map - Configure Receive SWPRI to PC mapping
194 * @interface: board private structure
195 *
196 * Configure the SWPRI to PC mapping for the port.
197 **/
198static void fm10k_configure_swpri_map(struct fm10k_intfc *interface)
199{
200 struct net_device *netdev = interface->netdev;
201 struct fm10k_hw *hw = &interface->hw;
202 int i;
203
204 /* clear flag indicating update is needed */
205 interface->flags &= ~FM10K_FLAG_SWPRI_CONFIG;
206
207 /* these registers are only available on the PF */
208 if (hw->mac.type != fm10k_mac_pf)
209 return;
210
211 /* configure SWPRI to PC map */
212 for (i = 0; i < FM10K_SWPRI_MAX; i++)
213 fm10k_write_reg(hw, FM10K_SWPRI_MAP(i),
214 netdev_get_prio_tc_map(netdev, i));
215}
216
217/**
218 * fm10k_watchdog_update_host_state - Update the link status based on host.
219 * @interface: board private structure
220 **/
221static void fm10k_watchdog_update_host_state(struct fm10k_intfc *interface)
222{
223 struct fm10k_hw *hw = &interface->hw;
224 s32 err;
225
226 if (test_bit(__FM10K_LINK_DOWN, &interface->state)) {
227 interface->host_ready = false;
228 if (time_is_after_jiffies(interface->link_down_event))
229 return;
230 clear_bit(__FM10K_LINK_DOWN, &interface->state);
231 }
232
233 if (interface->flags & FM10K_FLAG_SWPRI_CONFIG) {
234 if (rtnl_trylock()) {
235 fm10k_configure_swpri_map(interface);
236 rtnl_unlock();
237 }
238 }
239
240 /* lock the mailbox for transmit and receive */
241 fm10k_mbx_lock(interface);
242
243 err = hw->mac.ops.get_host_state(hw, &interface->host_ready);
244 if (err && time_is_before_jiffies(interface->last_reset))
245 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
246
247 /* free the lock */
248 fm10k_mbx_unlock(interface);
249}
250
251/**
252 * fm10k_mbx_subtask - Process upstream and downstream mailboxes
253 * @interface: board private structure
254 *
255 * This function will process both the upstream and downstream mailboxes.
256 * It is necessary for us to hold the rtnl_lock while doing this as the
257 * mailbox accesses are protected by this lock.
258 **/
259static void fm10k_mbx_subtask(struct fm10k_intfc *interface)
260{
261 /* process upstream mailbox and update device state */
262 fm10k_watchdog_update_host_state(interface);
263}
264
265/**
266 * fm10k_watchdog_host_is_ready - Update netdev status based on host ready
267 * @interface: board private structure
268 **/
269static void fm10k_watchdog_host_is_ready(struct fm10k_intfc *interface)
270{
271 struct net_device *netdev = interface->netdev;
272
273 /* only continue if link state is currently down */
274 if (netif_carrier_ok(netdev))
275 return;
276
277 netif_info(interface, drv, netdev, "NIC Link is up\n");
278
279 netif_carrier_on(netdev);
280 netif_tx_wake_all_queues(netdev);
281}
282
283/**
284 * fm10k_watchdog_host_not_ready - Update netdev status based on host not ready
285 * @interface: board private structure
286 **/
287static void fm10k_watchdog_host_not_ready(struct fm10k_intfc *interface)
288{
289 struct net_device *netdev = interface->netdev;
290
291 /* only continue if link state is currently up */
292 if (!netif_carrier_ok(netdev))
293 return;
294
295 netif_info(interface, drv, netdev, "NIC Link is down\n");
296
297 netif_carrier_off(netdev);
298 netif_tx_stop_all_queues(netdev);
299}
300
301/**
302 * fm10k_update_stats - Update the board statistics counters.
303 * @interface: board private structure
304 **/
305void fm10k_update_stats(struct fm10k_intfc *interface)
306{
307 struct net_device_stats *net_stats = &interface->netdev->stats;
308 struct fm10k_hw *hw = &interface->hw;
309 u64 rx_errors = 0, rx_csum_errors = 0, tx_csum_errors = 0;
310 u64 restart_queue = 0, tx_busy = 0, alloc_failed = 0;
311 u64 rx_bytes_nic = 0, rx_pkts_nic = 0, rx_drops_nic = 0;
312 u64 tx_bytes_nic = 0, tx_pkts_nic = 0;
313 u64 bytes, pkts;
314 int i;
315
316 /* do not allow stats update via service task for next second */
317 interface->next_stats_update = jiffies + HZ;
318
319 /* gather some stats to the interface struct that are per queue */
320 for (bytes = 0, pkts = 0, i = 0; i < interface->num_tx_queues; i++) {
321 struct fm10k_ring *tx_ring = interface->tx_ring[i];
322
323 restart_queue += tx_ring->tx_stats.restart_queue;
324 tx_busy += tx_ring->tx_stats.tx_busy;
325 tx_csum_errors += tx_ring->tx_stats.csum_err;
326 bytes += tx_ring->stats.bytes;
327 pkts += tx_ring->stats.packets;
328 }
329
330 interface->restart_queue = restart_queue;
331 interface->tx_busy = tx_busy;
332 net_stats->tx_bytes = bytes;
333 net_stats->tx_packets = pkts;
334 interface->tx_csum_errors = tx_csum_errors;
335 /* gather some stats to the interface struct that are per queue */
336 for (bytes = 0, pkts = 0, i = 0; i < interface->num_rx_queues; i++) {
337 struct fm10k_ring *rx_ring = interface->rx_ring[i];
338
339 bytes += rx_ring->stats.bytes;
340 pkts += rx_ring->stats.packets;
341 alloc_failed += rx_ring->rx_stats.alloc_failed;
342 rx_csum_errors += rx_ring->rx_stats.csum_err;
343 rx_errors += rx_ring->rx_stats.errors;
344 }
345
346 net_stats->rx_bytes = bytes;
347 net_stats->rx_packets = pkts;
348 interface->alloc_failed = alloc_failed;
349 interface->rx_csum_errors = rx_csum_errors;
350 interface->rx_errors = rx_errors;
351
352 hw->mac.ops.update_hw_stats(hw, &interface->stats);
353
354 for (i = 0; i < FM10K_MAX_QUEUES_PF; i++) {
355 struct fm10k_hw_stats_q *q = &interface->stats.q[i];
356
357 tx_bytes_nic += q->tx_bytes.count;
358 tx_pkts_nic += q->tx_packets.count;
359 rx_bytes_nic += q->rx_bytes.count;
360 rx_pkts_nic += q->rx_packets.count;
361 rx_drops_nic += q->rx_drops.count;
362 }
363
364 interface->tx_bytes_nic = tx_bytes_nic;
365 interface->tx_packets_nic = tx_pkts_nic;
366 interface->rx_bytes_nic = rx_bytes_nic;
367 interface->rx_packets_nic = rx_pkts_nic;
368 interface->rx_drops_nic = rx_drops_nic;
369
370 /* Fill out the OS statistics structure */
371 net_stats->rx_errors = interface->stats.xec.count;
372 net_stats->rx_dropped = interface->stats.nodesc_drop.count;
373}
374
375/**
376 * fm10k_watchdog_flush_tx - flush queues on host not ready
377 * @interface - pointer to the device interface structure
378 **/
379static void fm10k_watchdog_flush_tx(struct fm10k_intfc *interface)
380{
381 int some_tx_pending = 0;
382 int i;
383
384 /* nothing to do if carrier is up */
385 if (netif_carrier_ok(interface->netdev))
386 return;
387
388 for (i = 0; i < interface->num_tx_queues; i++) {
389 struct fm10k_ring *tx_ring = interface->tx_ring[i];
390
391 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
392 some_tx_pending = 1;
393 break;
394 }
395 }
396
397 /* We've lost link, so the controller stops DMA, but we've got
398 * queued Tx work that's never going to get done, so reset
399 * controller to flush Tx.
400 */
401 if (some_tx_pending)
402 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
403}
404
405/**
406 * fm10k_watchdog_subtask - check and bring link up
407 * @interface - pointer to the device interface structure
408 **/
409static void fm10k_watchdog_subtask(struct fm10k_intfc *interface)
410{
411 /* if interface is down do nothing */
412 if (test_bit(__FM10K_DOWN, &interface->state) ||
413 test_bit(__FM10K_RESETTING, &interface->state))
414 return;
415
416 if (interface->host_ready)
417 fm10k_watchdog_host_is_ready(interface);
418 else
419 fm10k_watchdog_host_not_ready(interface);
420
421 /* update stats only once every second */
422 if (time_is_before_jiffies(interface->next_stats_update))
423 fm10k_update_stats(interface);
424
425 /* flush any uncompleted work */
426 fm10k_watchdog_flush_tx(interface);
427}
428
429/**
430 * fm10k_check_hang_subtask - check for hung queues and dropped interrupts
431 * @interface - pointer to the device interface structure
432 *
433 * This function serves two purposes. First it strobes the interrupt lines
434 * in order to make certain interrupts are occurring. Secondly it sets the
435 * bits needed to check for TX hangs. As a result we should immediately
436 * determine if a hang has occurred.
437 */
438static void fm10k_check_hang_subtask(struct fm10k_intfc *interface)
439{
440 int i;
441
442 /* If we're down or resetting, just bail */
443 if (test_bit(__FM10K_DOWN, &interface->state) ||
444 test_bit(__FM10K_RESETTING, &interface->state))
445 return;
446
447 /* rate limit tx hang checks to only once every 2 seconds */
448 if (time_is_after_eq_jiffies(interface->next_tx_hang_check))
449 return;
450 interface->next_tx_hang_check = jiffies + (2 * HZ);
451
452 if (netif_carrier_ok(interface->netdev)) {
453 /* Force detection of hung controller */
454 for (i = 0; i < interface->num_tx_queues; i++)
455 set_check_for_tx_hang(interface->tx_ring[i]);
456
457 /* Rearm all in-use q_vectors for immediate firing */
458 for (i = 0; i < interface->num_q_vectors; i++) {
459 struct fm10k_q_vector *qv = interface->q_vector[i];
460
461 if (!qv->tx.count && !qv->rx.count)
462 continue;
463 writel(FM10K_ITR_ENABLE | FM10K_ITR_PENDING2, qv->itr);
464 }
465 }
466}
467
468/**
469 * fm10k_service_task - manages and runs subtasks
470 * @work: pointer to work_struct containing our data
471 **/
472static void fm10k_service_task(struct work_struct *work)
473{
474 struct fm10k_intfc *interface;
475
476 interface = container_of(work, struct fm10k_intfc, service_task);
477
478 /* tasks always capable of running, but must be rtnl protected */
479 fm10k_mbx_subtask(interface);
480 fm10k_detach_subtask(interface);
481 fm10k_reset_subtask(interface);
482
483 /* tasks only run when interface is up */
484 fm10k_watchdog_subtask(interface);
485 fm10k_check_hang_subtask(interface);
486
487 /* release lock on service events to allow scheduling next event */
488 fm10k_service_event_complete(interface);
489}
490
3abaae42
AD		 491/**
492 * fm10k_configure_tx_ring - Configure Tx ring after Reset
493 * @interface: board private structure
494 * @ring: structure containing ring specific data
495 *
496 * Configure the Tx descriptor ring after a reset.
497 **/
498static void fm10k_configure_tx_ring(struct fm10k_intfc *interface,
499 struct fm10k_ring *ring)
500{
501 struct fm10k_hw *hw = &interface->hw;
502 u64 tdba = ring->dma;
503 u32 size = ring->count * sizeof(struct fm10k_tx_desc);
504 u32 txint = FM10K_INT_MAP_DISABLE;
505 u32 txdctl = FM10K_TXDCTL_ENABLE | (1 << FM10K_TXDCTL_MAX_TIME_SHIFT);
506 u8 reg_idx = ring->reg_idx;
507
508 /* disable queue to avoid issues while updating state */
509 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
510 fm10k_write_flush(hw);
511
512 /* possible poll here to verify ring resources have been cleaned */
513
514 /* set location and size for descriptor ring */
515 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
516 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
517 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
518
519 /* reset head and tail pointers */
520 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
521 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
522
523 /* store tail pointer */
524 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)];
525
526 /* reset ntu and ntc to place SW in sync with hardwdare */
527 ring->next_to_clean = 0;
528 ring->next_to_use = 0;
529
530 /* Map interrupt */
531 if (ring->q_vector) {
532 txint = ring->q_vector->v_idx + NON_Q_VECTORS(hw);
533 txint |= FM10K_INT_MAP_TIMER0;
534 }
535
536 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);
537
538 /* enable use of FTAG bit in Tx descriptor, register is RO for VF */
539 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),
540 FM10K_PFVTCTL_FTAG_DESC_ENABLE);
541
542 /* enable queue */
543 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);
544}
545
546/**
547 * fm10k_enable_tx_ring - Verify Tx ring is enabled after configuration
548 * @interface: board private structure
549 * @ring: structure containing ring specific data
550 *
551 * Verify the Tx descriptor ring is ready for transmit.
552 **/
553static void fm10k_enable_tx_ring(struct fm10k_intfc *interface,
554 struct fm10k_ring *ring)
555{
556 struct fm10k_hw *hw = &interface->hw;
557 int wait_loop = 10;
558 u32 txdctl;
559 u8 reg_idx = ring->reg_idx;
560
561 /* if we are already enabled just exit */
562 if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE)
563 return;
564
565 /* poll to verify queue is enabled */
566 do {
567 usleep_range(1000, 2000);
568 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx));
569 } while (!(txdctl & FM10K_TXDCTL_ENABLE) && --wait_loop);
570 if (!wait_loop)
571 netif_err(interface, drv, interface->netdev,
572 "Could not enable Tx Queue %d\n", reg_idx);
573}
574
575/**
576 * fm10k_configure_tx - Configure Transmit Unit after Reset
577 * @interface: board private structure
578 *
579 * Configure the Tx unit of the MAC after a reset.
580 **/
581static void fm10k_configure_tx(struct fm10k_intfc *interface)
582{
583 int i;
584
585 /* Setup the HW Tx Head and Tail descriptor pointers */
586 for (i = 0; i < interface->num_tx_queues; i++)
587 fm10k_configure_tx_ring(interface, interface->tx_ring[i]);
588
589 /* poll here to verify that Tx rings are now enabled */
590 for (i = 0; i < interface->num_tx_queues; i++)
591 fm10k_enable_tx_ring(interface, interface->tx_ring[i]);
592}
593
594/**
595 * fm10k_configure_rx_ring - Configure Rx ring after Reset
596 * @interface: board private structure
597 * @ring: structure containing ring specific data
598 *
599 * Configure the Rx descriptor ring after a reset.
600 **/
601static void fm10k_configure_rx_ring(struct fm10k_intfc *interface,
602 struct fm10k_ring *ring)
603{
604 u64 rdba = ring->dma;
605 struct fm10k_hw *hw = &interface->hw;
606 u32 size = ring->count * sizeof(union fm10k_rx_desc);
607 u32 rxqctl = FM10K_RXQCTL_ENABLE | FM10K_RXQCTL_PF;
608 u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
609 u32 srrctl = FM10K_SRRCTL_BUFFER_CHAINING_EN;
610 u32 rxint = FM10K_INT_MAP_DISABLE;
611 u8 rx_pause = interface->rx_pause;
612 u8 reg_idx = ring->reg_idx;
613
614 /* disable queue to avoid issues while updating state */
615 fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), 0);
616 fm10k_write_flush(hw);
617
618 /* possible poll here to verify ring resources have been cleaned */
619
620 /* set location and size for descriptor ring */
621 fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
622 fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);
623 fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);
624
625 /* reset head and tail pointers */
626 fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);
627 fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);
628
629 /* store tail pointer */
630 ring->tail = &interface->uc_addr[FM10K_RDT(reg_idx)];
631
632 /* reset ntu and ntc to place SW in sync with hardwdare */
633 ring->next_to_clean = 0;
634 ring->next_to_use = 0;
635 ring->next_to_alloc = 0;
636
637 /* Configure the Rx buffer size for one buff without split */
638 srrctl |= FM10K_RX_BUFSZ >> FM10K_SRRCTL_BSIZEPKT_SHIFT;
639
640 /* Configure the Rx ring to supress loopback packets */
641 srrctl |= FM10K_SRRCTL_LOOPBACK_SUPPRESS;
642 fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);
643
644 /* Enable drop on empty */
645#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
646 if (interface->pfc_en)
647 rx_pause = interface->pfc_en;
648#endif
649 if (!(rx_pause & (1 << ring->qos_pc)))
650 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
651
652 fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
653
654 /* assign default VLAN to queue */
655 ring->vid = hw->mac.default_vid;
656
657 /* Map interrupt */
658 if (ring->q_vector) {
659 rxint = ring->q_vector->v_idx + NON_Q_VECTORS(hw);
660 rxint |= FM10K_INT_MAP_TIMER1;
661 }
662
663 fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);
664
665 /* enable queue */
666 fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
b101c962
AD		 667
668 /* place buffers on ring for receive data */
669 fm10k_alloc_rx_buffers(ring, fm10k_desc_unused(ring));
3abaae42
AD		 670}
671
672/**
673 * fm10k_update_rx_drop_en - Configures the drop enable bits for Rx rings
674 * @interface: board private structure
675 *
676 * Configure the drop enable bits for the Rx rings.
677 **/
678void fm10k_update_rx_drop_en(struct fm10k_intfc *interface)
679{
680 struct fm10k_hw *hw = &interface->hw;
681 u8 rx_pause = interface->rx_pause;
682 int i;
683
684#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
685 if (interface->pfc_en)
686 rx_pause = interface->pfc_en;
687
688#endif
689 for (i = 0; i < interface->num_rx_queues; i++) {
690 struct fm10k_ring *ring = interface->rx_ring[i];
691 u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
692 u8 reg_idx = ring->reg_idx;
693
694 if (!(rx_pause & (1 << ring->qos_pc)))
695 rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
696
697 fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
698 }
699}
700
701/**
702 * fm10k_configure_dglort - Configure Receive DGLORT after reset
703 * @interface: board private structure
704 *
705 * Configure the DGLORT description and RSS tables.
706 **/
707static void fm10k_configure_dglort(struct fm10k_intfc *interface)
708{
709 struct fm10k_dglort_cfg dglort = { 0 };
710 struct fm10k_hw *hw = &interface->hw;
711 int i;
712 u32 mrqc;
713
714 /* Fill out hash function seeds */
715 for (i = 0; i < FM10K_RSSRK_SIZE; i++)
716 fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]);
717
718 /* Write RETA table to hardware */
719 for (i = 0; i < FM10K_RETA_SIZE; i++)
720 fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]);
721
722 /* Generate RSS hash based on packet types, TCP/UDP
723 * port numbers and/or IPv4/v6 src and dst addresses
724 */
725 mrqc = FM10K_MRQC_IPV4 |
726 FM10K_MRQC_TCP_IPV4 |
727 FM10K_MRQC_IPV6 |
728 FM10K_MRQC_TCP_IPV6;
729
730 if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV4_UDP)
731 mrqc |= FM10K_MRQC_UDP_IPV4;
732 if (interface->flags & FM10K_FLAG_RSS_FIELD_IPV6_UDP)
733 mrqc |= FM10K_MRQC_UDP_IPV6;
734
735 fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);
736
737 /* configure default DGLORT mapping for RSS/DCB */
738 dglort.inner_rss = 1;
739 dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
740 dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
741 hw->mac.ops.configure_dglort_map(hw, &dglort);
742
743 /* assign GLORT per queue for queue mapped testing */
744 if (interface->glort_count > 64) {
745 memset(&dglort, 0, sizeof(dglort));
746 dglort.inner_rss = 1;
747 dglort.glort = interface->glort + 64;
748 dglort.idx = fm10k_dglort_pf_queue;
749 dglort.queue_l = fls(interface->num_rx_queues - 1);
750 hw->mac.ops.configure_dglort_map(hw, &dglort);
751 }
752
753 /* assign glort value for RSS/DCB specific to this interface */
754 memset(&dglort, 0, sizeof(dglort));
755 dglort.inner_rss = 1;
756 dglort.glort = interface->glort;
757 dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
758 dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
759 /* configure DGLORT mapping for RSS/DCB */
760 dglort.idx = fm10k_dglort_pf_rss;
5cd5e2e9
AD		 761 if (interface->l2_accel)
762 dglort.shared_l = fls(interface->l2_accel->size);
3abaae42
AD		 763 hw->mac.ops.configure_dglort_map(hw, &dglort);
764}
765
766/**
767 * fm10k_configure_rx - Configure Receive Unit after Reset
768 * @interface: board private structure
769 *
770 * Configure the Rx unit of the MAC after a reset.
771 **/
772static void fm10k_configure_rx(struct fm10k_intfc *interface)
773{
774 int i;
775
776 /* Configure SWPRI to PC map */
777 fm10k_configure_swpri_map(interface);
778
779 /* Configure RSS and DGLORT map */
780 fm10k_configure_dglort(interface);
781
782 /* Setup the HW Rx Head and Tail descriptor pointers */
783 for (i = 0; i < interface->num_rx_queues; i++)
784 fm10k_configure_rx_ring(interface, interface->rx_ring[i]);
785
786 /* possible poll here to verify that Rx rings are now enabled */
787}
788
18283cad
AD		 789static void fm10k_napi_enable_all(struct fm10k_intfc *interface)
790{
791 struct fm10k_q_vector *q_vector;
792 int q_idx;
793
794 for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) {
795 q_vector = interface->q_vector[q_idx];
796 napi_enable(&q_vector->napi);
797 }
798}
799
800static irqreturn_t fm10k_msix_clean_rings(int irq, void *data)
801{
802 struct fm10k_q_vector *q_vector = data;
803
804 if (q_vector->rx.count || q_vector->tx.count)
805 napi_schedule(&q_vector->napi);
806
807 return IRQ_HANDLED;
808}
809
5cb8db4a
AD		 810static irqreturn_t fm10k_msix_mbx_vf(int irq, void *data)
811{
812 struct fm10k_intfc *interface = data;
813 struct fm10k_hw *hw = &interface->hw;
814 struct fm10k_mbx_info *mbx = &hw->mbx;
815
816 /* re-enable mailbox interrupt and indicate 20us delay */
817 fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR),
818 FM10K_ITR_ENABLE | FM10K_MBX_INT_DELAY);
819
820 /* service upstream mailbox */
821 if (fm10k_mbx_trylock(interface)) {
822 mbx->ops.process(hw, mbx);
823 fm10k_mbx_unlock(interface);
824 }
825
826 hw->mac.get_host_state = 1;
827 fm10k_service_event_schedule(interface);
828
829 return IRQ_HANDLED;
830}
831
18283cad
AD		 832#define FM10K_ERR_MSG(type) case (type): error = #type; break
833static void fm10k_print_fault(struct fm10k_intfc *interface, int type,
834 struct fm10k_fault *fault)
835{
836 struct pci_dev *pdev = interface->pdev;
837 char *error;
838
839 switch (type) {
840 case FM10K_PCA_FAULT:
841 switch (fault->type) {
842 default:
843 error = "Unknown PCA error";
844 break;
845 FM10K_ERR_MSG(PCA_NO_FAULT);
846 FM10K_ERR_MSG(PCA_UNMAPPED_ADDR);
847 FM10K_ERR_MSG(PCA_BAD_QACCESS_PF);
848 FM10K_ERR_MSG(PCA_BAD_QACCESS_VF);
849 FM10K_ERR_MSG(PCA_MALICIOUS_REQ);
850 FM10K_ERR_MSG(PCA_POISONED_TLP);
851 FM10K_ERR_MSG(PCA_TLP_ABORT);
852 }
853 break;
854 case FM10K_THI_FAULT:
855 switch (fault->type) {
856 default:
857 error = "Unknown THI error";
858 break;
859 FM10K_ERR_MSG(THI_NO_FAULT);
860 FM10K_ERR_MSG(THI_MAL_DIS_Q_FAULT);
861 }
862 break;
863 case FM10K_FUM_FAULT:
864 switch (fault->type) {
865 default:
866 error = "Unknown FUM error";
867 break;
868 FM10K_ERR_MSG(FUM_NO_FAULT);
869 FM10K_ERR_MSG(FUM_UNMAPPED_ADDR);
870 FM10K_ERR_MSG(FUM_BAD_VF_QACCESS);
871 FM10K_ERR_MSG(FUM_ADD_DECODE_ERR);
872 FM10K_ERR_MSG(FUM_RO_ERROR);
873 FM10K_ERR_MSG(FUM_QPRC_CRC_ERROR);
874 FM10K_ERR_MSG(FUM_CSR_TIMEOUT);
875 FM10K_ERR_MSG(FUM_INVALID_TYPE);
876 FM10K_ERR_MSG(FUM_INVALID_LENGTH);
877 FM10K_ERR_MSG(FUM_INVALID_BE);
878 FM10K_ERR_MSG(FUM_INVALID_ALIGN);
879 }
880 break;
881 default:
882 error = "Undocumented fault";
883 break;
884 }
885
886 dev_warn(&pdev->dev,
887 "%s Address: 0x%llx SpecInfo: 0x%x Func: %02x.%0x\n",
888 error, fault->address, fault->specinfo,
889 PCI_SLOT(fault->func), PCI_FUNC(fault->func));
890}
891
892static void fm10k_report_fault(struct fm10k_intfc *interface, u32 eicr)
893{
894 struct fm10k_hw *hw = &interface->hw;
895 struct fm10k_fault fault = { 0 };
896 int type, err;
897
898 for (eicr &= FM10K_EICR_FAULT_MASK, type = FM10K_PCA_FAULT;
899 eicr;
900 eicr >>= 1, type += FM10K_FAULT_SIZE) {
901 /* only check if there is an error reported */
902 if (!(eicr & 0x1))
903 continue;
904
905 /* retrieve fault info */
906 err = hw->mac.ops.get_fault(hw, type, &fault);
907 if (err) {
908 dev_err(&interface->pdev->dev,
909 "error reading fault\n");
910 continue;
911 }
912
913 fm10k_print_fault(interface, type, &fault);
914 }
915}
916
917static void fm10k_reset_drop_on_empty(struct fm10k_intfc *interface, u32 eicr)
918{
919 struct fm10k_hw *hw = &interface->hw;
920 const u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
921 u32 maxholdq;
922 int q;
923
924 if (!(eicr & FM10K_EICR_MAXHOLDTIME))
925 return;
926
927 maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(7));
928 if (maxholdq)
929 fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq);
930 for (q = 255;;) {
931 if (maxholdq & (1 << 31)) {
932 if (q < FM10K_MAX_QUEUES_PF) {
933 interface->rx_overrun_pf++;
934 fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl);
935 } else {
936 interface->rx_overrun_vf++;
937 }
938 }
939
940 maxholdq *= 2;
941 if (!maxholdq)
942 q &= ~(32 - 1);
943
944 if (!q)
945 break;
946
947 if (q-- % 32)
948 continue;
949
950 maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(q / 32));
951 if (maxholdq)
952 fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq);
953 }
954}
955
956static irqreturn_t fm10k_msix_mbx_pf(int irq, void *data)
957{
958 struct fm10k_intfc *interface = data;
959 struct fm10k_hw *hw = &interface->hw;
960 struct fm10k_mbx_info *mbx = &hw->mbx;
961 u32 eicr;
962
963 /* unmask any set bits related to this interrupt */
964 eicr = fm10k_read_reg(hw, FM10K_EICR);
965 fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX |
966 FM10K_EICR_SWITCHREADY |
967 FM10K_EICR_SWITCHNOTREADY));
968
969 /* report any faults found to the message log */
970 fm10k_report_fault(interface, eicr);
971
972 /* reset any queues disabled due to receiver overrun */
973 fm10k_reset_drop_on_empty(interface, eicr);
974
975 /* service mailboxes */
976 if (fm10k_mbx_trylock(interface)) {
977 mbx->ops.process(hw, mbx);
978 fm10k_mbx_unlock(interface);
979 }
980
b7d8514c
AD		 981 /* if switch toggled state we should reset GLORTs */
982 if (eicr & FM10K_EICR_SWITCHNOTREADY) {
983 /* force link down for at least 4 seconds */
984 interface->link_down_event = jiffies + (4 * HZ);
985 set_bit(__FM10K_LINK_DOWN, &interface->state);
986
987 /* reset dglort_map back to no config */
988 hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
989 }
990
991 /* we should validate host state after interrupt event */
992 hw->mac.get_host_state = 1;
993 fm10k_service_event_schedule(interface);
994
18283cad
AD		 995 /* re-enable mailbox interrupt and indicate 20us delay */
996 fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR),
997 FM10K_ITR_ENABLE | FM10K_MBX_INT_DELAY);
998
999 return IRQ_HANDLED;
1000}
1001
1002void fm10k_mbx_free_irq(struct fm10k_intfc *interface)
1003{
1004 struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1005 struct fm10k_hw *hw = &interface->hw;
1006 int itr_reg;
1007
1008 /* disconnect the mailbox */
1009 hw->mbx.ops.disconnect(hw, &hw->mbx);
1010
1011 /* disable Mailbox cause */
1012 if (hw->mac.type == fm10k_mac_pf) {
1013 fm10k_write_reg(hw, FM10K_EIMR,
1014 FM10K_EIMR_DISABLE(PCA_FAULT) |
1015 FM10K_EIMR_DISABLE(FUM_FAULT) |
1016 FM10K_EIMR_DISABLE(MAILBOX) |
1017 FM10K_EIMR_DISABLE(SWITCHREADY) |
1018 FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
1019 FM10K_EIMR_DISABLE(SRAMERROR) |
1020 FM10K_EIMR_DISABLE(VFLR) |
1021 FM10K_EIMR_DISABLE(MAXHOLDTIME));
1022 itr_reg = FM10K_ITR(FM10K_MBX_VECTOR);
5cb8db4a
AD		 1023 } else {
1024 itr_reg = FM10K_VFITR(FM10K_MBX_VECTOR);
18283cad
AD		 1025 }
1026
1027 fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET);
1028
1029 free_irq(entry->vector, interface);
1030}
1031
5cb8db4a
AD		 1032static s32 fm10k_mbx_mac_addr(struct fm10k_hw *hw, u32 **results,
1033 struct fm10k_mbx_info *mbx)
1034{
1035 bool vlan_override = hw->mac.vlan_override;
1036 u16 default_vid = hw->mac.default_vid;
1037 struct fm10k_intfc *interface;
1038 s32 err;
1039
1040 err = fm10k_msg_mac_vlan_vf(hw, results, mbx);
1041 if (err)
1042 return err;
1043
1044 interface = container_of(hw, struct fm10k_intfc, hw);
1045
1046 /* MAC was changed so we need reset */
1047 if (is_valid_ether_addr(hw->mac.perm_addr) &&
1048 memcmp(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN))
1049 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
1050
1051 /* VLAN override was changed, or default VLAN changed */
1052 if ((vlan_override != hw->mac.vlan_override) ||
1053 (default_vid != hw->mac.default_vid))
1054 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
1055
1056 return 0;
1057}
1058
18283cad
AD		 1059/* generic error handler for mailbox issues */
1060static s32 fm10k_mbx_error(struct fm10k_hw *hw, u32 **results,
1061 struct fm10k_mbx_info *mbx)
1062{
1063 struct fm10k_intfc *interface;
1064 struct pci_dev *pdev;
1065
1066 interface = container_of(hw, struct fm10k_intfc, hw);
1067 pdev = interface->pdev;
1068
1069 dev_err(&pdev->dev, "Unknown message ID %u\n",
1070 **results & FM10K_TLV_ID_MASK);
1071
1072 return 0;
1073}
1074
5cb8db4a
AD		 1075static const struct fm10k_msg_data vf_mbx_data[] = {
1076 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1077 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_mbx_mac_addr),
1078 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
1079 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error),
1080};
1081
1082static int fm10k_mbx_request_irq_vf(struct fm10k_intfc *interface)
1083{
1084 struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1085 struct net_device *dev = interface->netdev;
1086 struct fm10k_hw *hw = &interface->hw;
1087 int err;
1088
1089 /* Use timer0 for interrupt moderation on the mailbox */
1090 u32 itr = FM10K_INT_MAP_TIMER0 | entry->entry;
1091
1092 /* register mailbox handlers */
1093 err = hw->mbx.ops.register_handlers(&hw->mbx, vf_mbx_data);
1094 if (err)
1095 return err;
1096
1097 /* request the IRQ */
1098 err = request_irq(entry->vector, fm10k_msix_mbx_vf, 0,
1099 dev->name, interface);
1100 if (err) {
1101 netif_err(interface, probe, dev,
1102 "request_irq for msix_mbx failed: %d\n", err);
1103 return err;
1104 }
1105
1106 /* map all of the interrupt sources */
1107 fm10k_write_reg(hw, FM10K_VFINT_MAP, itr);
1108
1109 /* enable interrupt */
1110 fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE);
1111
1112 return 0;
1113}
1114
18283cad
AD		 1115static s32 fm10k_lport_map(struct fm10k_hw *hw, u32 **results,
1116 struct fm10k_mbx_info *mbx)
1117{
1118 struct fm10k_intfc *interface;
1119 u32 dglort_map = hw->mac.dglort_map;
1120 s32 err;
1121
1122 err = fm10k_msg_lport_map_pf(hw, results, mbx);
1123 if (err)
1124 return err;
1125
1126 interface = container_of(hw, struct fm10k_intfc, hw);
1127
1128 /* we need to reset if port count was just updated */
1129 if (dglort_map != hw->mac.dglort_map)
1130 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
1131
1132 return 0;
1133}
1134
1135static s32 fm10k_update_pvid(struct fm10k_hw *hw, u32 **results,
1136 struct fm10k_mbx_info *mbx)
1137{
1138 struct fm10k_intfc *interface;
1139 u16 glort, pvid;
1140 u32 pvid_update;
1141 s32 err;
1142
1143 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1144 &pvid_update);
1145 if (err)
1146 return err;
1147
1148 /* extract values from the pvid update */
1149 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1150 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1151
1152 /* if glort is not valid return error */
1153 if (!fm10k_glort_valid_pf(hw, glort))
1154 return FM10K_ERR_PARAM;
1155
1156 /* verify VID is valid */
1157 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1158 return FM10K_ERR_PARAM;
1159
1160 interface = container_of(hw, struct fm10k_intfc, hw);
1161
1162 /* we need to reset if default VLAN was just updated */
1163 if (pvid != hw->mac.default_vid)
1164 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
1165
1166 hw->mac.default_vid = pvid;
1167
1168 return 0;
1169}
1170
1171static const struct fm10k_msg_data pf_mbx_data[] = {
1172 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1173 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1174 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_lport_map),
1175 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1176 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1177 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_update_pvid),
1178 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error),
1179};
1180
1181static int fm10k_mbx_request_irq_pf(struct fm10k_intfc *interface)
1182{
1183 struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1184 struct net_device *dev = interface->netdev;
1185 struct fm10k_hw *hw = &interface->hw;
1186 int err;
1187
1188 /* Use timer0 for interrupt moderation on the mailbox */
1189 u32 mbx_itr = FM10K_INT_MAP_TIMER0 | entry->entry;
1190 u32 other_itr = FM10K_INT_MAP_IMMEDIATE | entry->entry;
1191
1192 /* register mailbox handlers */
1193 err = hw->mbx.ops.register_handlers(&hw->mbx, pf_mbx_data);
1194 if (err)
1195 return err;
1196
1197 /* request the IRQ */
1198 err = request_irq(entry->vector, fm10k_msix_mbx_pf, 0,
1199 dev->name, interface);
1200 if (err) {
1201 netif_err(interface, probe, dev,
1202 "request_irq for msix_mbx failed: %d\n", err);
1203 return err;
1204 }
1205
1206 /* Enable interrupts w/ no moderation for "other" interrupts */
1207 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_PCIeFault), other_itr);
1208 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SwitchUpDown), other_itr);
1209 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_SRAM), other_itr);
1210 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_MaxHoldTime), other_itr);
1211 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_VFLR), other_itr);
1212
1213 /* Enable interrupts w/ moderation for mailbox */
1214 fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_Mailbox), mbx_itr);
1215
1216 /* Enable individual interrupt causes */
1217 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
1218 FM10K_EIMR_ENABLE(FUM_FAULT) |
1219 FM10K_EIMR_ENABLE(MAILBOX) |
1220 FM10K_EIMR_ENABLE(SWITCHREADY) |
1221 FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
1222 FM10K_EIMR_ENABLE(SRAMERROR) |
1223 FM10K_EIMR_ENABLE(VFLR) |
1224 FM10K_EIMR_ENABLE(MAXHOLDTIME));
1225
1226 /* enable interrupt */
1227 fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE);
1228
1229 return 0;
1230}
1231
1232int fm10k_mbx_request_irq(struct fm10k_intfc *interface)
1233{
1234 struct fm10k_hw *hw = &interface->hw;
1235 int err;
1236
1237 /* enable Mailbox cause */
5cb8db4a
AD		 1238 if (hw->mac.type == fm10k_mac_pf)
1239 err = fm10k_mbx_request_irq_pf(interface);
1240 else
1241 err = fm10k_mbx_request_irq_vf(interface);
18283cad
AD		 1242
1243 /* connect mailbox */
1244 if (!err)
1245 err = hw->mbx.ops.connect(hw, &hw->mbx);
1246
1247 return err;
1248}
1249
1250/**
1251 * fm10k_qv_free_irq - release interrupts associated with queue vectors
1252 * @interface: board private structure
1253 *
1254 * Release all interrupts associated with this interface
1255 **/
1256void fm10k_qv_free_irq(struct fm10k_intfc *interface)
1257{
1258 int vector = interface->num_q_vectors;
1259 struct fm10k_hw *hw = &interface->hw;
1260 struct msix_entry *entry;
1261
1262 entry = &interface->msix_entries[NON_Q_VECTORS(hw) + vector];
1263
1264 while (vector) {
1265 struct fm10k_q_vector *q_vector;
1266
1267 vector--;
1268 entry--;
1269 q_vector = interface->q_vector[vector];
1270
1271 if (!q_vector->tx.count && !q_vector->rx.count)
1272 continue;
1273
1274 /* disable interrupts */
1275
1276 writel(FM10K_ITR_MASK_SET, q_vector->itr);
1277
1278 free_irq(entry->vector, q_vector);
1279 }
1280}
1281
1282/**
1283 * fm10k_qv_request_irq - initialize interrupts for queue vectors
1284 * @interface: board private structure
1285 *
1286 * Attempts to configure interrupts using the best available
1287 * capabilities of the hardware and kernel.
1288 **/
1289int fm10k_qv_request_irq(struct fm10k_intfc *interface)
1290{
1291 struct net_device *dev = interface->netdev;
1292 struct fm10k_hw *hw = &interface->hw;
1293 struct msix_entry *entry;
1294 int ri = 0, ti = 0;
1295 int vector, err;
1296
1297 entry = &interface->msix_entries[NON_Q_VECTORS(hw)];
1298
1299 for (vector = 0; vector < interface->num_q_vectors; vector++) {
1300 struct fm10k_q_vector *q_vector = interface->q_vector[vector];
1301
1302 /* name the vector */
1303 if (q_vector->tx.count && q_vector->rx.count) {
1304 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
1305 "%s-TxRx-%d", dev->name, ri++);
1306 ti++;
1307 } else if (q_vector->rx.count) {
1308 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
1309 "%s-rx-%d", dev->name, ri++);
1310 } else if (q_vector->tx.count) {
1311 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
1312 "%s-tx-%d", dev->name, ti++);
1313 } else {
1314 /* skip this unused q_vector */
1315 continue;
1316 }
1317
1318 /* Assign ITR register to q_vector */
5cb8db4a
AD		 1319 q_vector->itr = (hw->mac.type == fm10k_mac_pf) ?
1320 &interface->uc_addr[FM10K_ITR(entry->entry)] :
1321 &interface->uc_addr[FM10K_VFITR(entry->entry)];
18283cad
AD		 1322
1323 /* request the IRQ */
1324 err = request_irq(entry->vector, &fm10k_msix_clean_rings, 0,
1325 q_vector->name, q_vector);
1326 if (err) {
1327 netif_err(interface, probe, dev,
1328 "request_irq failed for MSIX interrupt Error: %d\n",
1329 err);
1330 goto err_out;
1331 }
1332
1333 /* Enable q_vector */
1334 writel(FM10K_ITR_ENABLE, q_vector->itr);
1335
1336 entry++;
1337 }
1338
1339 return 0;
1340
1341err_out:
1342 /* wind through the ring freeing all entries and vectors */
1343 while (vector) {
1344 struct fm10k_q_vector *q_vector;
1345
1346 entry--;
1347 vector--;
1348 q_vector = interface->q_vector[vector];
1349
1350 if (!q_vector->tx.count && !q_vector->rx.count)
1351 continue;
1352
1353 /* disable interrupts */
1354
1355 writel(FM10K_ITR_MASK_SET, q_vector->itr);
1356
1357 free_irq(entry->vector, q_vector);
1358 }
1359
1360 return err;
1361}
1362
504c5eac
AD		 1363void fm10k_up(struct fm10k_intfc *interface)
1364{
1365 struct fm10k_hw *hw = &interface->hw;
1366
1367 /* Enable Tx/Rx DMA */
1368 hw->mac.ops.start_hw(hw);
1369
3abaae42
AD		 1370 /* configure Tx descriptor rings */
1371 fm10k_configure_tx(interface);
1372
1373 /* configure Rx descriptor rings */
1374 fm10k_configure_rx(interface);
1375
504c5eac
AD		 1376 /* configure interrupts */
1377 hw->mac.ops.update_int_moderator(hw);
1378
1379 /* clear down bit to indicate we are ready to go */
1380 clear_bit(__FM10K_DOWN, &interface->state);
1381
18283cad
AD		 1382 /* enable polling cleanups */
1383 fm10k_napi_enable_all(interface);
1384
504c5eac
AD		 1385 /* re-establish Rx filters */
1386 fm10k_restore_rx_state(interface);
1387
1388 /* enable transmits */
1389 netif_tx_start_all_queues(interface->netdev);
b7d8514c
AD		 1390
1391 /* kick off the service timer */
1392 mod_timer(&interface->service_timer, jiffies);
504c5eac
AD		 1393}
1394
18283cad
AD		 1395static void fm10k_napi_disable_all(struct fm10k_intfc *interface)
1396{
1397 struct fm10k_q_vector *q_vector;
1398 int q_idx;
1399
1400 for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) {
1401 q_vector = interface->q_vector[q_idx];
1402 napi_disable(&q_vector->napi);
1403 }
1404}
1405
504c5eac
AD		 1406void fm10k_down(struct fm10k_intfc *interface)
1407{
1408 struct net_device *netdev = interface->netdev;
1409 struct fm10k_hw *hw = &interface->hw;
1410
1411 /* signal that we are down to the interrupt handler and service task */
1412 set_bit(__FM10K_DOWN, &interface->state);
1413
1414 /* call carrier off first to avoid false dev_watchdog timeouts */
1415 netif_carrier_off(netdev);
1416
1417 /* disable transmits */
1418 netif_tx_stop_all_queues(netdev);
1419 netif_tx_disable(netdev);
1420
1421 /* reset Rx filters */
1422 fm10k_reset_rx_state(interface);
1423
1424 /* allow 10ms for device to quiesce */
1425 usleep_range(10000, 20000);
1426
18283cad
AD		 1427 /* disable polling routines */
1428 fm10k_napi_disable_all(interface);
1429
b7d8514c
AD		 1430 del_timer_sync(&interface->service_timer);
1431
1432 /* capture stats one last time before stopping interface */
1433 fm10k_update_stats(interface);
1434
504c5eac
AD		 1435 /* Disable DMA engine for Tx/Rx */
1436 hw->mac.ops.stop_hw(hw);
3abaae42
AD		 1437
1438 /* free any buffers still on the rings */
1439 fm10k_clean_all_tx_rings(interface);
504c5eac
AD		 1440}
1441
0e7b3644
AD		 1442/**
1443 * fm10k_sw_init - Initialize general software structures
1444 * @interface: host interface private structure to initialize
1445 *
1446 * fm10k_sw_init initializes the interface private data structure.
1447 * Fields are initialized based on PCI device information and
1448 * OS network device settings (MTU size).
1449 **/
1450static int fm10k_sw_init(struct fm10k_intfc *interface,
1451 const struct pci_device_id *ent)
1452{
1453 static const u32 seed[FM10K_RSSRK_SIZE] = { 0xda565a6d, 0xc20e5b25,
1454 0x3d256741, 0xb08fa343,
1455 0xcb2bcad0, 0xb4307bae,
1456 0xa32dcb77, 0x0cf23080,
1457 0x3bb7426a, 0xfa01acbe };
1458 const struct fm10k_info *fi = fm10k_info_tbl[ent->driver_data];
1459 struct fm10k_hw *hw = &interface->hw;
1460 struct pci_dev *pdev = interface->pdev;
1461 struct net_device *netdev = interface->netdev;
1462 unsigned int rss;
1463 int err;
1464
1465 /* initialize back pointer */
1466 hw->back = interface;
1467 hw->hw_addr = interface->uc_addr;
1468
1469 /* PCI config space info */
1470 hw->vendor_id = pdev->vendor;
1471 hw->device_id = pdev->device;
1472 hw->revision_id = pdev->revision;
1473 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1474 hw->subsystem_device_id = pdev->subsystem_device;
1475
1476 /* Setup hw api */
1477 memcpy(&hw->mac.ops, fi->mac_ops, sizeof(hw->mac.ops));
1478 hw->mac.type = fi->mac;
1479
1480 /* Set common capability flags and settings */
1481 rss = min_t(int, FM10K_MAX_RSS_INDICES, num_online_cpus());
1482 interface->ring_feature[RING_F_RSS].limit = rss;
1483 fi->get_invariants(hw);
1484
1485 /* pick up the PCIe bus settings for reporting later */
1486 if (hw->mac.ops.get_bus_info)
1487 hw->mac.ops.get_bus_info(hw);
1488
1489 /* limit the usable DMA range */
1490 if (hw->mac.ops.set_dma_mask)
1491 hw->mac.ops.set_dma_mask(hw, dma_get_mask(&pdev->dev));
1492
1493 /* update netdev with DMA restrictions */
1494 if (dma_get_mask(&pdev->dev) > DMA_BIT_MASK(32)) {
1495 netdev->features |= NETIF_F_HIGHDMA;
1496 netdev->vlan_features |= NETIF_F_HIGHDMA;
1497 }
1498
b7d8514c
AD		 1499 /* delay any future reset requests */
1500 interface->last_reset = jiffies + (10 * HZ);
1501
0e7b3644
AD		 1502 /* reset and initialize the hardware so it is in a known state */
1503 err = hw->mac.ops.reset_hw(hw) ? : hw->mac.ops.init_hw(hw);
1504 if (err) {
1505 dev_err(&pdev->dev, "init_hw failed: %d\n", err);
1506 return err;
1507 }
1508
1509 /* initialize hardware statistics */
1510 hw->mac.ops.update_hw_stats(hw, &interface->stats);
1511
1512 /* Start with random Ethernet address */
1513 eth_random_addr(hw->mac.addr);
1514
1515 /* Initialize MAC address from hardware */
1516 err = hw->mac.ops.read_mac_addr(hw);
1517 if (err) {
1518 dev_warn(&pdev->dev,
1519 "Failed to obtain MAC address defaulting to random\n");
1520 /* tag address assignment as random */
1521 netdev->addr_assign_type |= NET_ADDR_RANDOM;
1522 }
1523
1524 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1525 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1526
1527 if (!is_valid_ether_addr(netdev->perm_addr)) {
1528 dev_err(&pdev->dev, "Invalid MAC Address\n");
1529 return -EIO;
1530 }
1531
1532 /* Only the PF can support VXLAN and NVGRE offloads */
1533 if (hw->mac.type != fm10k_mac_pf) {
1534 netdev->hw_enc_features = 0;
1535 netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1536 netdev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
1537 }
1538
b7d8514c
AD		 1539 /* Initialize service timer and service task */
1540 set_bit(__FM10K_SERVICE_DISABLE, &interface->state);
1541 setup_timer(&interface->service_timer, &fm10k_service_timer,
1542 (unsigned long)interface);
1543 INIT_WORK(&interface->service_task, fm10k_service_task);
1544
e27ef599
AD		 1545 /* set default ring sizes */
1546 interface->tx_ring_count = FM10K_DEFAULT_TXD;
1547 interface->rx_ring_count = FM10K_DEFAULT_RXD;
1548
18283cad
AD		 1549 /* set default interrupt moderation */
1550 interface->tx_itr = FM10K_ITR_10K;
1551 interface->rx_itr = FM10K_ITR_ADAPTIVE | FM10K_ITR_20K;
1552
0e7b3644
AD		 1553 /* initialize vxlan_port list */
1554 INIT_LIST_HEAD(&interface->vxlan_port);
1555
1556 /* initialize RSS key */
1557 memcpy(interface->rssrk, seed, sizeof(seed));
1558
1559 /* Start off interface as being down */
1560 set_bit(__FM10K_DOWN, &interface->state);
1561
1562 return 0;
1563}
1564
1565static void fm10k_slot_warn(struct fm10k_intfc *interface)
1566{
1567 struct device *dev = &interface->pdev->dev;
1568 struct fm10k_hw *hw = &interface->hw;
1569
1570 if (hw->mac.ops.is_slot_appropriate(hw))
1571 return;
1572
1573 dev_warn(dev,
1574 "For optimal performance, a %s %s slot is recommended.\n",
1575 (hw->bus_caps.width == fm10k_bus_width_pcie_x1 ? "x1" :
1576 hw->bus_caps.width == fm10k_bus_width_pcie_x4 ? "x4" :
1577 "x8"),
1578 (hw->bus_caps.speed == fm10k_bus_speed_2500 ? "2.5GT/s" :
1579 hw->bus_caps.speed == fm10k_bus_speed_5000 ? "5.0GT/s" :
1580 "8.0GT/s"));
1581 dev_warn(dev,
1582 "A slot with more lanes and/or higher speed is suggested.\n");
1583}
1584
b3890e30
AD		 1585/**
1586 * fm10k_probe - Device Initialization Routine
1587 * @pdev: PCI device information struct
1588 * @ent: entry in fm10k_pci_tbl
1589 *
1590 * Returns 0 on success, negative on failure
1591 *
1592 * fm10k_probe initializes an interface identified by a pci_dev structure.
1593 * The OS initialization, configuring of the interface private structure,
1594 * and a hardware reset occur.
1595 **/
1596static int fm10k_probe(struct pci_dev *pdev,
1597 const struct pci_device_id *ent)
1598{
0e7b3644
AD		 1599 struct net_device *netdev;
1600 struct fm10k_intfc *interface;
1601 struct fm10k_hw *hw;
b3890e30
AD		 1602 int err;
1603 u64 dma_mask;
1604
1605 err = pci_enable_device_mem(pdev);
1606 if (err)
1607 return err;
1608
1609 /* By default fm10k only supports a 48 bit DMA mask */
1610 dma_mask = DMA_BIT_MASK(48) | dma_get_required_mask(&pdev->dev);
1611
1612 if ((dma_mask <= DMA_BIT_MASK(32)) ||
1613 dma_set_mask_and_coherent(&pdev->dev, dma_mask)) {
1614 dma_mask &= DMA_BIT_MASK(32);
1615
1616 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1617 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1618 if (err) {
1619 err = dma_set_coherent_mask(&pdev->dev,
1620 DMA_BIT_MASK(32));
1621 if (err) {
1622 dev_err(&pdev->dev,
1623 "No usable DMA configuration, aborting\n");
1624 goto err_dma;
1625 }
1626 }
1627 }
1628
1629 err = pci_request_selected_regions(pdev,
1630 pci_select_bars(pdev,
1631 IORESOURCE_MEM),
1632 fm10k_driver_name);
1633 if (err) {
1634 dev_err(&pdev->dev,
1635 "pci_request_selected_regions failed 0x%x\n", err);
1636 goto err_pci_reg;
1637 }
1638
19ae1b3f
AD		 1639 pci_enable_pcie_error_reporting(pdev);
1640
b3890e30
AD		 1641 pci_set_master(pdev);
1642 pci_save_state(pdev);
1643
0e7b3644
AD		 1644 netdev = fm10k_alloc_netdev();
1645 if (!netdev) {
1646 err = -ENOMEM;
1647 goto err_alloc_netdev;
1648 }
1649
1650 SET_NETDEV_DEV(netdev, &pdev->dev);
1651
1652 interface = netdev_priv(netdev);
1653 pci_set_drvdata(pdev, interface);
1654
1655 interface->netdev = netdev;
1656 interface->pdev = pdev;
1657 hw = &interface->hw;
1658
1659 interface->uc_addr = ioremap(pci_resource_start(pdev, 0),
1660 FM10K_UC_ADDR_SIZE);
1661 if (!interface->uc_addr) {
1662 err = -EIO;
1663 goto err_ioremap;
1664 }
1665
1666 err = fm10k_sw_init(interface, ent);
1667 if (err)
1668 goto err_sw_init;
1669
18283cad
AD		 1670 err = fm10k_init_queueing_scheme(interface);
1671 if (err)
1672 goto err_sw_init;
1673
1674 err = fm10k_mbx_request_irq(interface);
1675 if (err)
1676 goto err_mbx_interrupt;
1677
0e7b3644
AD		 1678 /* final check of hardware state before registering the interface */
1679 err = fm10k_hw_ready(interface);
1680 if (err)
1681 goto err_register;
1682
1683 err = register_netdev(netdev);
1684 if (err)
1685 goto err_register;
1686
1687 /* carrier off reporting is important to ethtool even BEFORE open */
1688 netif_carrier_off(netdev);
1689
1690 /* stop all the transmit queues from transmitting until link is up */
1691 netif_tx_stop_all_queues(netdev);
1692
1693 /* print bus type/speed/width info */
1694 dev_info(&pdev->dev, "(PCI Express:%s Width: %s Payload: %s)\n",
1695 (hw->bus.speed == fm10k_bus_speed_8000 ? "8.0GT/s" :
1696 hw->bus.speed == fm10k_bus_speed_5000 ? "5.0GT/s" :
1697 hw->bus.speed == fm10k_bus_speed_2500 ? "2.5GT/s" :
1698 "Unknown"),
1699 (hw->bus.width == fm10k_bus_width_pcie_x8 ? "x8" :
1700 hw->bus.width == fm10k_bus_width_pcie_x4 ? "x4" :
1701 hw->bus.width == fm10k_bus_width_pcie_x1 ? "x1" :
1702 "Unknown"),
1703 (hw->bus.payload == fm10k_bus_payload_128 ? "128B" :
1704 hw->bus.payload == fm10k_bus_payload_256 ? "256B" :
1705 hw->bus.payload == fm10k_bus_payload_512 ? "512B" :
1706 "Unknown"));
1707
1708 /* print warning for non-optimal configurations */
1709 fm10k_slot_warn(interface);
1710
b7d8514c
AD		 1711 /* clear the service task disable bit to allow service task to start */
1712 clear_bit(__FM10K_SERVICE_DISABLE, &interface->state);
1713
b3890e30
AD		 1714 return 0;
1715
0e7b3644 1716err_register:
18283cad
AD		 1717 fm10k_mbx_free_irq(interface);
1718err_mbx_interrupt:
1719 fm10k_clear_queueing_scheme(interface);
0e7b3644
AD		 1720err_sw_init:
1721 iounmap(interface->uc_addr);
1722err_ioremap:
1723 free_netdev(netdev);
1724err_alloc_netdev:
1725 pci_release_selected_regions(pdev,
1726 pci_select_bars(pdev, IORESOURCE_MEM));
b3890e30
AD		 1727err_pci_reg:
1728err_dma:
1729 pci_disable_device(pdev);
1730 return err;
1731}
1732
1733/**
1734 * fm10k_remove - Device Removal Routine
1735 * @pdev: PCI device information struct
1736 *
1737 * fm10k_remove is called by the PCI subsystem to alert the driver
1738 * that it should release a PCI device. The could be caused by a
1739 * Hot-Plug event, or because the driver is going to be removed from
1740 * memory.
1741 **/
1742static void fm10k_remove(struct pci_dev *pdev)
1743{
0e7b3644
AD		 1744 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1745 struct net_device *netdev = interface->netdev;
1746
b7d8514c
AD		 1747 set_bit(__FM10K_SERVICE_DISABLE, &interface->state);
1748 cancel_work_sync(&interface->service_task);
1749
0e7b3644
AD		 1750 /* free netdev, this may bounce the interrupts due to setup_tc */
1751 if (netdev->reg_state == NETREG_REGISTERED)
1752 unregister_netdev(netdev);
1753
18283cad
AD		 1754 /* disable mailbox interrupt */
1755 fm10k_mbx_free_irq(interface);
1756
1757 /* free interrupts */
1758 fm10k_clear_queueing_scheme(interface);
1759
0e7b3644
AD		 1760 iounmap(interface->uc_addr);
1761
1762 free_netdev(netdev);
1763
b3890e30
AD		 1764 pci_release_selected_regions(pdev,
1765 pci_select_bars(pdev, IORESOURCE_MEM));
1766
19ae1b3f
AD		 1767 pci_disable_pcie_error_reporting(pdev);
1768
b3890e30
AD		 1769 pci_disable_device(pdev);
1770}
1771
19ae1b3f
AD		 1772#ifdef CONFIG_PM
1773/**
1774 * fm10k_resume - Restore device to pre-sleep state
1775 * @pdev: PCI device information struct
1776 *
1777 * fm10k_resume is called after the system has powered back up from a sleep
1778 * state and is ready to resume operation. This function is meant to restore
1779 * the device back to its pre-sleep state.
1780 **/
1781static int fm10k_resume(struct pci_dev *pdev)
1782{
1783 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1784 struct net_device *netdev = interface->netdev;
1785 struct fm10k_hw *hw = &interface->hw;
1786 u32 err;
1787
1788 pci_set_power_state(pdev, PCI_D0);
1789 pci_restore_state(pdev);
1790
1791 /* pci_restore_state clears dev->state_saved so call
1792 * pci_save_state to restore it.
1793 */
1794 pci_save_state(pdev);
1795
1796 err = pci_enable_device_mem(pdev);
1797 if (err) {
1798 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
1799 return err;
1800 }
1801 pci_set_master(pdev);
1802
1803 pci_wake_from_d3(pdev, false);
1804
1805 /* refresh hw_addr in case it was dropped */
1806 hw->hw_addr = interface->uc_addr;
1807
1808 /* reset hardware to known state */
1809 err = hw->mac.ops.init_hw(&interface->hw);
1810 if (err)
1811 return err;
1812
1813 /* reset statistics starting values */
1814 hw->mac.ops.rebind_hw_stats(hw, &interface->stats);
1815
1816 rtnl_lock();
1817
1818 err = fm10k_init_queueing_scheme(interface);
1819 if (!err) {
1820 fm10k_mbx_request_irq(interface);
1821 if (netif_running(netdev))
1822 err = fm10k_open(netdev);
1823 }
1824
1825 rtnl_unlock();
1826
1827 if (err)
1828 return err;
1829
1830 netif_device_attach(netdev);
1831
1832 return 0;
1833}
1834
1835/**
1836 * fm10k_suspend - Prepare the device for a system sleep state
1837 * @pdev: PCI device information struct
1838 *
1839 * fm10k_suspend is meant to shutdown the device prior to the system entering
1840 * a sleep state. The fm10k hardware does not support wake on lan so the
1841 * driver simply needs to shut down the device so it is in a low power state.
1842 **/
1843static int fm10k_suspend(struct pci_dev *pdev, pm_message_t state)
1844{
1845 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1846 struct net_device *netdev = interface->netdev;
1847 int err = 0;
1848
1849 netif_device_detach(netdev);
1850
1851 rtnl_lock();
1852
1853 if (netif_running(netdev))
1854 fm10k_close(netdev);
1855
1856 fm10k_mbx_free_irq(interface);
1857
1858 fm10k_clear_queueing_scheme(interface);
1859
1860 rtnl_unlock();
1861
1862 err = pci_save_state(pdev);
1863 if (err)
1864 return err;
1865
1866 pci_disable_device(pdev);
1867 pci_wake_from_d3(pdev, false);
1868 pci_set_power_state(pdev, PCI_D3hot);
1869
1870 return 0;
1871}
1872
1873#endif /* CONFIG_PM */
1874/**
1875 * fm10k_io_error_detected - called when PCI error is detected
1876 * @pdev: Pointer to PCI device
1877 * @state: The current pci connection state
1878 *
1879 * This function is called after a PCI bus error affecting
1880 * this device has been detected.
1881 */
1882static pci_ers_result_t fm10k_io_error_detected(struct pci_dev *pdev,
1883 pci_channel_state_t state)
1884{
1885 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1886 struct net_device *netdev = interface->netdev;
1887
1888 netif_device_detach(netdev);
1889
1890 if (state == pci_channel_io_perm_failure)
1891 return PCI_ERS_RESULT_DISCONNECT;
1892
1893 if (netif_running(netdev))
1894 fm10k_close(netdev);
1895
1896 fm10k_mbx_free_irq(interface);
1897
1898 pci_disable_device(pdev);
1899
1900 /* Request a slot reset. */
1901 return PCI_ERS_RESULT_NEED_RESET;
1902}
1903
1904/**
1905 * fm10k_io_slot_reset - called after the pci bus has been reset.
1906 * @pdev: Pointer to PCI device
1907 *
1908 * Restart the card from scratch, as if from a cold-boot.
1909 */
1910static pci_ers_result_t fm10k_io_slot_reset(struct pci_dev *pdev)
1911{
1912 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1913 pci_ers_result_t result;
1914
1915 if (pci_enable_device_mem(pdev)) {
1916 dev_err(&pdev->dev,
1917 "Cannot re-enable PCI device after reset.\n");
1918 result = PCI_ERS_RESULT_DISCONNECT;
1919 } else {
1920 pci_set_master(pdev);
1921 pci_restore_state(pdev);
1922
1923 /* After second error pci->state_saved is false, this
1924 * resets it so EEH doesn't break.
1925 */
1926 pci_save_state(pdev);
1927
1928 pci_wake_from_d3(pdev, false);
1929
1930 /* refresh hw_addr in case it was dropped */
1931 interface->hw.hw_addr = interface->uc_addr;
1932
1933 interface->flags |= FM10K_FLAG_RESET_REQUESTED;
1934 fm10k_service_event_schedule(interface);
1935
1936 result = PCI_ERS_RESULT_RECOVERED;
1937 }
1938
1939 pci_cleanup_aer_uncorrect_error_status(pdev);
1940
1941 return result;
1942}
1943
1944/**
1945 * fm10k_io_resume - called when traffic can start flowing again.
1946 * @pdev: Pointer to PCI device
1947 *
1948 * This callback is called when the error recovery driver tells us that
1949 * its OK to resume normal operation.
1950 */
1951static void fm10k_io_resume(struct pci_dev *pdev)
1952{
1953 struct fm10k_intfc *interface = pci_get_drvdata(pdev);
1954 struct net_device *netdev = interface->netdev;
1955 struct fm10k_hw *hw = &interface->hw;
1956 int err = 0;
1957
1958 /* reset hardware to known state */
1959 hw->mac.ops.init_hw(&interface->hw);
1960
1961 /* reset statistics starting values */
1962 hw->mac.ops.rebind_hw_stats(hw, &interface->stats);
1963
1964 /* reassociate interrupts */
1965 fm10k_mbx_request_irq(interface);
1966
1967 if (netif_running(netdev))
1968 err = fm10k_open(netdev);
1969
1970 /* final check of hardware state before registering the interface */
1971 err = err ? : fm10k_hw_ready(interface);
1972
1973 if (!err)
1974 netif_device_attach(netdev);
1975}
1976
1977static const struct pci_error_handlers fm10k_err_handler = {
1978 .error_detected = fm10k_io_error_detected,
1979 .slot_reset = fm10k_io_slot_reset,
1980 .resume = fm10k_io_resume,
1981};
1982
b3890e30
AD		 1983static struct pci_driver fm10k_driver = {
1984 .name = fm10k_driver_name,
1985 .id_table = fm10k_pci_tbl,
1986 .probe = fm10k_probe,
1987 .remove = fm10k_remove,
19ae1b3f
AD		 1988#ifdef CONFIG_PM
1989 .suspend = fm10k_suspend,
1990 .resume = fm10k_resume,
1991#endif
1992 .err_handler = &fm10k_err_handler
b3890e30
AD		 1993};
1994
1995/**
1996 * fm10k_register_pci_driver - register driver interface
1997 *
1998 * This funciton is called on module load in order to register the driver.
1999 **/
2000int fm10k_register_pci_driver(void)
2001{
2002 return pci_register_driver(&fm10k_driver);
2003}
2004
2005/**
2006 * fm10k_unregister_pci_driver - unregister driver interface
2007 *
2008 * This funciton is called on module unload in order to remove the driver.
2009 **/
2010void fm10k_unregister_pci_driver(void)
2011{
2012 pci_unregister_driver(&fm10k_driver);
2013}
Linux kernel - Deliverables
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