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b6fec18f | 1 | /* Intel Ethernet Switch Host Interface Driver |
9d4955b4 | 2 | * Copyright(c) 2013 - 2015 Intel Corporation. |
b6fec18f AD |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
18 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
19 | */ | |
20 | ||
21 | #include "fm10k_pf.h" | |
c2653865 | 22 | #include "fm10k_vf.h" |
b6fec18f AD |
23 | |
24 | /** | |
25 | * fm10k_reset_hw_pf - PF hardware reset | |
26 | * @hw: pointer to hardware structure | |
27 | * | |
28 | * This function should return the hardware to a state similar to the | |
29 | * one it is in after being powered on. | |
30 | **/ | |
31 | static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw) | |
32 | { | |
33 | s32 err; | |
34 | u32 reg; | |
35 | u16 i; | |
36 | ||
37 | /* Disable interrupts */ | |
38 | fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL)); | |
39 | ||
40 | /* Lock ITR2 reg 0 into itself and disable interrupt moderation */ | |
41 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); | |
42 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); | |
43 | ||
44 | /* We assume here Tx and Rx queue 0 are owned by the PF */ | |
45 | ||
46 | /* Shut off VF access to their queues forcing them to queue 0 */ | |
47 | for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) { | |
48 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); | |
49 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); | |
50 | } | |
51 | ||
52 | /* shut down all rings */ | |
53 | err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES); | |
54 | if (err) | |
55 | return err; | |
56 | ||
57 | /* Verify that DMA is no longer active */ | |
58 | reg = fm10k_read_reg(hw, FM10K_DMA_CTRL); | |
59 | if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE)) | |
60 | return FM10K_ERR_DMA_PENDING; | |
61 | ||
ac981003 AD |
62 | /* verify the switch is ready for reset */ |
63 | reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2); | |
64 | if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY)) | |
65 | goto out; | |
66 | ||
b6fec18f AD |
67 | /* Inititate data path reset */ |
68 | reg |= FM10K_DMA_CTRL_DATAPATH_RESET; | |
69 | fm10k_write_reg(hw, FM10K_DMA_CTRL, reg); | |
70 | ||
71 | /* Flush write and allow 100us for reset to complete */ | |
72 | fm10k_write_flush(hw); | |
73 | udelay(FM10K_RESET_TIMEOUT); | |
74 | ||
75 | /* Verify we made it out of reset */ | |
76 | reg = fm10k_read_reg(hw, FM10K_IP); | |
77 | if (!(reg & FM10K_IP_NOTINRESET)) | |
78 | err = FM10K_ERR_RESET_FAILED; | |
79 | ||
ac981003 | 80 | out: |
b6fec18f AD |
81 | return err; |
82 | } | |
83 | ||
c2653865 AD |
84 | /** |
85 | * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support | |
86 | * @hw: pointer to hardware structure | |
87 | * | |
88 | * Looks at the ARI hierarchy bit to determine whether ARI is supported or not. | |
89 | **/ | |
90 | static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw) | |
91 | { | |
92 | u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL); | |
93 | ||
94 | return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI); | |
95 | } | |
96 | ||
b6fec18f AD |
97 | /** |
98 | * fm10k_init_hw_pf - PF hardware initialization | |
99 | * @hw: pointer to hardware structure | |
100 | * | |
101 | **/ | |
102 | static s32 fm10k_init_hw_pf(struct fm10k_hw *hw) | |
103 | { | |
104 | u32 dma_ctrl, txqctl; | |
105 | u16 i; | |
106 | ||
107 | /* Establish default VSI as valid */ | |
108 | fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0); | |
109 | fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default), | |
110 | FM10K_DGLORTMAP_ANY); | |
111 | ||
112 | /* Invalidate all other GLORT entries */ | |
113 | for (i = 1; i < FM10K_DGLORT_COUNT; i++) | |
114 | fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE); | |
115 | ||
116 | /* reset ITR2(0) to point to itself */ | |
117 | fm10k_write_reg(hw, FM10K_ITR2(0), 0); | |
118 | ||
119 | /* reset VF ITR2(0) to point to 0 avoid PF registers */ | |
120 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0); | |
121 | ||
122 | /* loop through all PF ITR2 registers pointing them to the previous */ | |
123 | for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++) | |
124 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); | |
125 | ||
126 | /* Enable interrupt moderator if not already enabled */ | |
127 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); | |
128 | ||
129 | /* compute the default txqctl configuration */ | |
130 | txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW | | |
131 | (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); | |
132 | ||
133 | for (i = 0; i < FM10K_MAX_QUEUES; i++) { | |
134 | /* configure rings for 256 Queue / 32 Descriptor cache mode */ | |
135 | fm10k_write_reg(hw, FM10K_TQDLOC(i), | |
136 | (i * FM10K_TQDLOC_BASE_32_DESC) | | |
137 | FM10K_TQDLOC_SIZE_32_DESC); | |
138 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); | |
139 | ||
140 | /* configure rings to provide TPH processing hints */ | |
141 | fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i), | |
142 | FM10K_TPH_TXCTRL_DESC_TPHEN | | |
143 | FM10K_TPH_TXCTRL_DESC_RROEN | | |
144 | FM10K_TPH_TXCTRL_DESC_WROEN | | |
145 | FM10K_TPH_TXCTRL_DATA_RROEN); | |
146 | fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i), | |
147 | FM10K_TPH_RXCTRL_DESC_TPHEN | | |
148 | FM10K_TPH_RXCTRL_DESC_RROEN | | |
149 | FM10K_TPH_RXCTRL_DATA_WROEN | | |
150 | FM10K_TPH_RXCTRL_HDR_WROEN); | |
151 | } | |
152 | ||
20076fa1 JK |
153 | /* set max hold interval to align with 1.024 usec in all modes and |
154 | * store ITR scale | |
155 | */ | |
b6fec18f AD |
156 | switch (hw->bus.speed) { |
157 | case fm10k_bus_speed_2500: | |
158 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1; | |
20076fa1 | 159 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1; |
b6fec18f AD |
160 | break; |
161 | case fm10k_bus_speed_5000: | |
162 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2; | |
20076fa1 | 163 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2; |
b6fec18f AD |
164 | break; |
165 | case fm10k_bus_speed_8000: | |
166 | dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3; | |
20076fa1 | 167 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; |
b6fec18f AD |
168 | break; |
169 | default: | |
170 | dma_ctrl = 0; | |
20076fa1 JK |
171 | /* just in case, assume Gen3 ITR scale */ |
172 | hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3; | |
b6fec18f AD |
173 | break; |
174 | } | |
175 | ||
176 | /* Configure TSO flags */ | |
177 | fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW); | |
178 | fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI); | |
179 | ||
180 | /* Enable DMA engine | |
181 | * Set Rx Descriptor size to 32 | |
182 | * Set Minimum MSS to 64 | |
183 | * Set Maximum number of Rx queues to 256 / 32 Descriptor | |
184 | */ | |
185 | dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE | | |
186 | FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 | | |
187 | FM10K_DMA_CTRL_32_DESC; | |
188 | ||
189 | fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl); | |
190 | ||
191 | /* record maximum queue count, we limit ourselves to 128 */ | |
192 | hw->mac.max_queues = FM10K_MAX_QUEUES_PF; | |
193 | ||
c2653865 AD |
194 | /* We support either 64 VFs or 7 VFs depending on if we have ARI */ |
195 | hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7; | |
196 | ||
b6fec18f AD |
197 | return 0; |
198 | } | |
199 | ||
401b5383 AD |
200 | /** |
201 | * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table | |
202 | * @hw: pointer to hardware structure | |
203 | * @vid: VLAN ID to add to table | |
204 | * @vsi: Index indicating VF ID or PF ID in table | |
205 | * @set: Indicates if this is a set or clear operation | |
206 | * | |
207 | * This function adds or removes the corresponding VLAN ID from the VLAN | |
208 | * filter table for the corresponding function. In addition to the | |
209 | * standard set/clear that supports one bit a multi-bit write is | |
210 | * supported to set 64 bits at a time. | |
211 | **/ | |
212 | static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set) | |
213 | { | |
214 | u32 vlan_table, reg, mask, bit, len; | |
215 | ||
216 | /* verify the VSI index is valid */ | |
217 | if (vsi > FM10K_VLAN_TABLE_VSI_MAX) | |
218 | return FM10K_ERR_PARAM; | |
219 | ||
220 | /* VLAN multi-bit write: | |
221 | * The multi-bit write has several parts to it. | |
222 | * 3 2 1 0 | |
223 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
224 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
225 | * | RSVD0 | Length |C|RSVD0| VLAN ID | | |
226 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
227 | * | |
228 | * VLAN ID: Vlan Starting value | |
229 | * RSVD0: Reserved section, must be 0 | |
230 | * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message) | |
231 | * Length: Number of times to repeat the bit being set | |
232 | */ | |
233 | len = vid >> 16; | |
234 | vid = (vid << 17) >> 17; | |
235 | ||
236 | /* verify the reserved 0 fields are 0 */ | |
eca32047 | 237 | if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX) |
401b5383 AD |
238 | return FM10K_ERR_PARAM; |
239 | ||
240 | /* Loop through the table updating all required VLANs */ | |
241 | for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32; | |
242 | len < FM10K_VLAN_TABLE_VID_MAX; | |
243 | len -= 32 - bit, reg++, bit = 0) { | |
244 | /* record the initial state of the register */ | |
245 | vlan_table = fm10k_read_reg(hw, reg); | |
246 | ||
247 | /* truncate mask if we are at the start or end of the run */ | |
248 | mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit; | |
249 | ||
250 | /* make necessary modifications to the register */ | |
251 | mask &= set ? ~vlan_table : vlan_table; | |
252 | if (mask) | |
253 | fm10k_write_reg(hw, reg, vlan_table ^ mask); | |
254 | } | |
255 | ||
256 | return 0; | |
257 | } | |
258 | ||
b6fec18f AD |
259 | /** |
260 | * fm10k_read_mac_addr_pf - Read device MAC address | |
261 | * @hw: pointer to the HW structure | |
262 | * | |
263 | * Reads the device MAC address from the SM_AREA and stores the value. | |
264 | **/ | |
265 | static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw) | |
266 | { | |
267 | u8 perm_addr[ETH_ALEN]; | |
268 | u32 serial_num; | |
b6fec18f AD |
269 | |
270 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1)); | |
271 | ||
272 | /* last byte should be all 1's */ | |
273 | if ((~serial_num) << 24) | |
274 | return FM10K_ERR_INVALID_MAC_ADDR; | |
275 | ||
276 | perm_addr[0] = (u8)(serial_num >> 24); | |
277 | perm_addr[1] = (u8)(serial_num >> 16); | |
278 | perm_addr[2] = (u8)(serial_num >> 8); | |
279 | ||
280 | serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0)); | |
281 | ||
282 | /* first byte should be all 1's */ | |
283 | if ((~serial_num) >> 24) | |
284 | return FM10K_ERR_INVALID_MAC_ADDR; | |
285 | ||
286 | perm_addr[3] = (u8)(serial_num >> 16); | |
287 | perm_addr[4] = (u8)(serial_num >> 8); | |
288 | perm_addr[5] = (u8)(serial_num); | |
289 | ||
f0cf5c98 JK |
290 | ether_addr_copy(hw->mac.perm_addr, perm_addr); |
291 | ether_addr_copy(hw->mac.addr, perm_addr); | |
b6fec18f AD |
292 | |
293 | return 0; | |
294 | } | |
295 | ||
401b5383 AD |
296 | /** |
297 | * fm10k_glort_valid_pf - Validate that the provided glort is valid | |
298 | * @hw: pointer to the HW structure | |
299 | * @glort: base glort to be validated | |
300 | * | |
301 | * This function will return an error if the provided glort is invalid | |
302 | **/ | |
303 | bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort) | |
304 | { | |
305 | glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT; | |
306 | ||
307 | return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE); | |
308 | } | |
309 | ||
310 | /** | |
eca32047 | 311 | * fm10k_update_xc_addr_pf - Update device addresses |
401b5383 AD |
312 | * @hw: pointer to the HW structure |
313 | * @glort: base resource tag for this request | |
314 | * @mac: MAC address to add/remove from table | |
315 | * @vid: VLAN ID to add/remove from table | |
316 | * @add: Indicates if this is an add or remove operation | |
317 | * @flags: flags field to indicate add and secure | |
318 | * | |
319 | * This function generates a message to the Switch API requesting | |
320 | * that the given logical port add/remove the given L2 MAC/VLAN address. | |
321 | **/ | |
322 | static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort, | |
323 | const u8 *mac, u16 vid, bool add, u8 flags) | |
324 | { | |
325 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
326 | struct fm10k_mac_update mac_update; | |
327 | u32 msg[5]; | |
328 | ||
b32d15b9 JK |
329 | /* clear set bit from VLAN ID */ |
330 | vid &= ~FM10K_VLAN_CLEAR; | |
331 | ||
aa502b4a | 332 | /* if glort or VLAN are not valid return error */ |
33a44c28 | 333 | if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX) |
401b5383 AD |
334 | return FM10K_ERR_PARAM; |
335 | ||
401b5383 AD |
336 | /* record fields */ |
337 | mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) | | |
338 | ((u32)mac[3] << 16) | | |
339 | ((u32)mac[4] << 8) | | |
340 | ((u32)mac[5])); | |
9d4955b4 JK |
341 | mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) | |
342 | ((u16)mac[1])); | |
401b5383 AD |
343 | mac_update.vlan = cpu_to_le16(vid); |
344 | mac_update.glort = cpu_to_le16(glort); | |
345 | mac_update.action = add ? 0 : 1; | |
346 | mac_update.flags = flags; | |
347 | ||
348 | /* populate mac_update fields */ | |
349 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE); | |
350 | fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE, | |
351 | &mac_update, sizeof(mac_update)); | |
352 | ||
353 | /* load onto outgoing mailbox */ | |
354 | return mbx->ops.enqueue_tx(hw, mbx, msg); | |
355 | } | |
356 | ||
357 | /** | |
eca32047 | 358 | * fm10k_update_uc_addr_pf - Update device unicast addresses |
401b5383 AD |
359 | * @hw: pointer to the HW structure |
360 | * @glort: base resource tag for this request | |
361 | * @mac: MAC address to add/remove from table | |
362 | * @vid: VLAN ID to add/remove from table | |
363 | * @add: Indicates if this is an add or remove operation | |
364 | * @flags: flags field to indicate add and secure | |
365 | * | |
366 | * This function is used to add or remove unicast addresses for | |
367 | * the PF. | |
368 | **/ | |
369 | static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort, | |
370 | const u8 *mac, u16 vid, bool add, u8 flags) | |
371 | { | |
372 | /* verify MAC address is valid */ | |
373 | if (!is_valid_ether_addr(mac)) | |
374 | return FM10K_ERR_PARAM; | |
375 | ||
376 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags); | |
377 | } | |
378 | ||
379 | /** | |
380 | * fm10k_update_mc_addr_pf - Update device multicast addresses | |
381 | * @hw: pointer to the HW structure | |
382 | * @glort: base resource tag for this request | |
383 | * @mac: MAC address to add/remove from table | |
384 | * @vid: VLAN ID to add/remove from table | |
385 | * @add: Indicates if this is an add or remove operation | |
386 | * | |
387 | * This function is used to add or remove multicast MAC addresses for | |
388 | * the PF. | |
389 | **/ | |
390 | static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort, | |
391 | const u8 *mac, u16 vid, bool add) | |
392 | { | |
393 | /* verify multicast address is valid */ | |
394 | if (!is_multicast_ether_addr(mac)) | |
395 | return FM10K_ERR_PARAM; | |
396 | ||
397 | return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0); | |
398 | } | |
399 | ||
400 | /** | |
401 | * fm10k_update_xcast_mode_pf - Request update of multicast mode | |
402 | * @hw: pointer to hardware structure | |
403 | * @glort: base resource tag for this request | |
404 | * @mode: integer value indicating mode being requested | |
405 | * | |
406 | * This function will attempt to request a higher mode for the port | |
407 | * so that it can enable either multicast, multicast promiscuous, or | |
408 | * promiscuous mode of operation. | |
409 | **/ | |
410 | static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode) | |
411 | { | |
412 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
413 | u32 msg[3], xcast_mode; | |
414 | ||
415 | if (mode > FM10K_XCAST_MODE_NONE) | |
416 | return FM10K_ERR_PARAM; | |
a4fcad65 | 417 | |
401b5383 AD |
418 | /* if glort is not valid return error */ |
419 | if (!fm10k_glort_valid_pf(hw, glort)) | |
420 | return FM10K_ERR_PARAM; | |
421 | ||
422 | /* write xcast mode as a single u32 value, | |
423 | * lower 16 bits: glort | |
424 | * upper 16 bits: mode | |
425 | */ | |
426 | xcast_mode = ((u32)mode << 16) | glort; | |
427 | ||
428 | /* generate message requesting to change xcast mode */ | |
429 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES); | |
430 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode); | |
431 | ||
432 | /* load onto outgoing mailbox */ | |
433 | return mbx->ops.enqueue_tx(hw, mbx, msg); | |
434 | } | |
435 | ||
436 | /** | |
437 | * fm10k_update_int_moderator_pf - Update interrupt moderator linked list | |
438 | * @hw: pointer to hardware structure | |
439 | * | |
440 | * This function walks through the MSI-X vector table to determine the | |
441 | * number of active interrupts and based on that information updates the | |
442 | * interrupt moderator linked list. | |
443 | **/ | |
444 | static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw) | |
445 | { | |
446 | u32 i; | |
447 | ||
448 | /* Disable interrupt moderator */ | |
449 | fm10k_write_reg(hw, FM10K_INT_CTRL, 0); | |
450 | ||
451 | /* loop through PF from last to first looking enabled vectors */ | |
452 | for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) { | |
453 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) | |
454 | break; | |
455 | } | |
456 | ||
eca32047 | 457 | /* always reset VFITR2[0] to point to last enabled PF vector */ |
401b5383 AD |
458 | fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i); |
459 | ||
460 | /* reset ITR2[0] to point to last enabled PF vector */ | |
c2653865 AD |
461 | if (!hw->iov.num_vfs) |
462 | fm10k_write_reg(hw, FM10K_ITR2(0), i); | |
401b5383 AD |
463 | |
464 | /* Enable interrupt moderator */ | |
465 | fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR); | |
466 | } | |
467 | ||
468 | /** | |
469 | * fm10k_update_lport_state_pf - Notify the switch of a change in port state | |
470 | * @hw: pointer to the HW structure | |
471 | * @glort: base resource tag for this request | |
472 | * @count: number of logical ports being updated | |
473 | * @enable: boolean value indicating enable or disable | |
474 | * | |
475 | * This function is used to add/remove a logical port from the switch. | |
476 | **/ | |
477 | static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort, | |
478 | u16 count, bool enable) | |
479 | { | |
480 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
481 | u32 msg[3], lport_msg; | |
482 | ||
483 | /* do nothing if we are being asked to create or destroy 0 ports */ | |
484 | if (!count) | |
485 | return 0; | |
486 | ||
487 | /* if glort is not valid return error */ | |
488 | if (!fm10k_glort_valid_pf(hw, glort)) | |
489 | return FM10K_ERR_PARAM; | |
490 | ||
491 | /* construct the lport message from the 2 pieces of data we have */ | |
492 | lport_msg = ((u32)count << 16) | glort; | |
493 | ||
494 | /* generate lport create/delete message */ | |
495 | fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE : | |
496 | FM10K_PF_MSG_ID_LPORT_DELETE); | |
497 | fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg); | |
498 | ||
499 | /* load onto outgoing mailbox */ | |
500 | return mbx->ops.enqueue_tx(hw, mbx, msg); | |
501 | } | |
502 | ||
503 | /** | |
504 | * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues | |
505 | * @hw: pointer to hardware structure | |
506 | * @dglort: pointer to dglort configuration structure | |
507 | * | |
508 | * Reads the configuration structure contained in dglort_cfg and uses | |
509 | * that information to then populate a DGLORTMAP/DEC entry and the queues | |
510 | * to which it has been assigned. | |
511 | **/ | |
512 | static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw, | |
513 | struct fm10k_dglort_cfg *dglort) | |
514 | { | |
515 | u16 glort, queue_count, vsi_count, pc_count; | |
516 | u16 vsi, queue, pc, q_idx; | |
517 | u32 txqctl, dglortdec, dglortmap; | |
518 | ||
519 | /* verify the dglort pointer */ | |
520 | if (!dglort) | |
521 | return FM10K_ERR_PARAM; | |
522 | ||
523 | /* verify the dglort values */ | |
524 | if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) || | |
525 | (dglort->vsi_l > 6) || (dglort->vsi_b > 64) || | |
526 | (dglort->queue_l > 8) || (dglort->queue_b >= 256)) | |
527 | return FM10K_ERR_PARAM; | |
528 | ||
529 | /* determine count of VSIs and queues */ | |
530 | queue_count = 1 << (dglort->rss_l + dglort->pc_l); | |
531 | vsi_count = 1 << (dglort->vsi_l + dglort->queue_l); | |
532 | glort = dglort->glort; | |
533 | q_idx = dglort->queue_b; | |
534 | ||
535 | /* configure SGLORT for queues */ | |
536 | for (vsi = 0; vsi < vsi_count; vsi++, glort++) { | |
537 | for (queue = 0; queue < queue_count; queue++, q_idx++) { | |
538 | if (q_idx >= FM10K_MAX_QUEUES) | |
539 | break; | |
540 | ||
541 | fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort); | |
542 | fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort); | |
543 | } | |
544 | } | |
545 | ||
546 | /* determine count of PCs and queues */ | |
547 | queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l); | |
548 | pc_count = 1 << dglort->pc_l; | |
549 | ||
550 | /* configure PC for Tx queues */ | |
551 | for (pc = 0; pc < pc_count; pc++) { | |
552 | q_idx = pc + dglort->queue_b; | |
553 | for (queue = 0; queue < queue_count; queue++) { | |
554 | if (q_idx >= FM10K_MAX_QUEUES) | |
555 | break; | |
556 | ||
557 | txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx)); | |
558 | txqctl &= ~FM10K_TXQCTL_PC_MASK; | |
559 | txqctl |= pc << FM10K_TXQCTL_PC_SHIFT; | |
560 | fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl); | |
561 | ||
562 | q_idx += pc_count; | |
563 | } | |
564 | } | |
565 | ||
566 | /* configure DGLORTDEC */ | |
567 | dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) | | |
568 | ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) | | |
569 | ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) | | |
570 | ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) | | |
571 | ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) | | |
572 | ((u32)(dglort->queue_l)); | |
573 | if (dglort->inner_rss) | |
574 | dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE; | |
575 | ||
576 | /* configure DGLORTMAP */ | |
577 | dglortmap = (dglort->idx == fm10k_dglort_default) ? | |
578 | FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO; | |
579 | dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l; | |
580 | dglortmap |= dglort->glort; | |
581 | ||
582 | /* write values to hardware */ | |
583 | fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec); | |
584 | fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
c2653865 AD |
589 | u16 fm10k_queues_per_pool(struct fm10k_hw *hw) |
590 | { | |
591 | u16 num_pools = hw->iov.num_pools; | |
592 | ||
593 | return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ? | |
594 | 8 : FM10K_MAX_QUEUES_POOL; | |
595 | } | |
596 | ||
597 | u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx) | |
598 | { | |
599 | u16 num_vfs = hw->iov.num_vfs; | |
600 | u16 vf_q_idx = FM10K_MAX_QUEUES; | |
601 | ||
602 | vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx); | |
603 | ||
604 | return vf_q_idx; | |
605 | } | |
606 | ||
607 | static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw) | |
608 | { | |
609 | u16 num_pools = hw->iov.num_pools; | |
610 | ||
611 | return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 : | |
612 | FM10K_MAX_VECTORS_POOL; | |
613 | } | |
614 | ||
615 | static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx) | |
616 | { | |
617 | u16 vf_v_idx = FM10K_MAX_VECTORS_PF; | |
618 | ||
619 | vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx; | |
620 | ||
621 | return vf_v_idx; | |
622 | } | |
623 | ||
624 | /** | |
625 | * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization | |
626 | * @hw: pointer to the HW structure | |
627 | * @num_vfs: number of VFs to be allocated | |
628 | * @num_pools: number of virtualization pools to be allocated | |
629 | * | |
630 | * Allocates queues and traffic classes to virtualization entities to prepare | |
631 | * the PF for SR-IOV and VMDq | |
632 | **/ | |
633 | static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs, | |
634 | u16 num_pools) | |
635 | { | |
636 | u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx; | |
637 | u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT; | |
638 | int i, j; | |
639 | ||
640 | /* hardware only supports up to 64 pools */ | |
641 | if (num_pools > 64) | |
642 | return FM10K_ERR_PARAM; | |
643 | ||
644 | /* the number of VFs cannot exceed the number of pools */ | |
645 | if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs)) | |
646 | return FM10K_ERR_PARAM; | |
647 | ||
648 | /* record number of virtualization entities */ | |
649 | hw->iov.num_vfs = num_vfs; | |
650 | hw->iov.num_pools = num_pools; | |
651 | ||
652 | /* determine qmap offsets and counts */ | |
653 | qmap_stride = (num_vfs > 8) ? 32 : 256; | |
654 | qpp = fm10k_queues_per_pool(hw); | |
655 | vpp = fm10k_vectors_per_pool(hw); | |
656 | ||
657 | /* calculate starting index for queues */ | |
658 | vf_q_idx = fm10k_vf_queue_index(hw, 0); | |
659 | qmap_idx = 0; | |
660 | ||
661 | /* establish TCs with -1 credits and no quanta to prevent transmit */ | |
662 | for (i = 0; i < num_vfs; i++) { | |
663 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0); | |
664 | fm10k_write_reg(hw, FM10K_TC_RATE(i), 0); | |
665 | fm10k_write_reg(hw, FM10K_TC_CREDIT(i), | |
666 | FM10K_TC_CREDIT_CREDIT_MASK); | |
667 | } | |
668 | ||
669 | /* zero out all mbmem registers */ | |
670 | for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;) | |
671 | fm10k_write_reg(hw, FM10K_MBMEM(i), 0); | |
672 | ||
673 | /* clear event notification of VF FLR */ | |
674 | fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0); | |
675 | fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0); | |
676 | ||
677 | /* loop through unallocated rings assigning them back to PF */ | |
678 | for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) { | |
679 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); | |
ded8b20d JK |
680 | fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | |
681 | FM10K_TXQCTL_UNLIMITED_BW | vid); | |
c2653865 AD |
682 | fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF); |
683 | } | |
684 | ||
685 | /* PF should have already updated VFITR2[0] */ | |
686 | ||
687 | /* update all ITR registers to flow to VFITR2[0] */ | |
688 | for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) { | |
689 | if (!(i & (vpp - 1))) | |
690 | fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp); | |
691 | else | |
692 | fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); | |
693 | } | |
694 | ||
695 | /* update PF ITR2[0] to reference the last vector */ | |
696 | fm10k_write_reg(hw, FM10K_ITR2(0), | |
697 | fm10k_vf_vector_index(hw, num_vfs - 1)); | |
698 | ||
699 | /* loop through rings populating rings and TCs */ | |
700 | for (i = 0; i < num_vfs; i++) { | |
701 | /* record index for VF queue 0 for use in end of loop */ | |
702 | vf_q_idx0 = vf_q_idx; | |
703 | ||
704 | for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) { | |
705 | /* assign VF and locked TC to queues */ | |
706 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); | |
707 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx), | |
708 | (i << FM10K_TXQCTL_TC_SHIFT) | i | | |
709 | FM10K_TXQCTL_VF | vid); | |
710 | fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx), | |
711 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | | |
712 | FM10K_RXDCTL_DROP_ON_EMPTY); | |
713 | fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx), | |
714 | FM10K_RXQCTL_VF | | |
715 | (i << FM10K_RXQCTL_VF_SHIFT)); | |
716 | ||
717 | /* map queue pair to VF */ | |
718 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); | |
719 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx); | |
720 | } | |
721 | ||
722 | /* repeat the first ring for all of the remaining VF rings */ | |
723 | for (; j < qmap_stride; j++, qmap_idx++) { | |
724 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0); | |
725 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0); | |
726 | } | |
727 | } | |
728 | ||
729 | /* loop through remaining indexes assigning all to queue 0 */ | |
730 | while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) { | |
731 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); | |
732 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0); | |
733 | qmap_idx++; | |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
739 | /** | |
740 | * fm10k_iov_configure_tc_pf - Configure the shaping group for VF | |
741 | * @hw: pointer to the HW structure | |
742 | * @vf_idx: index of VF receiving GLORT | |
743 | * @rate: Rate indicated in Mb/s | |
744 | * | |
745 | * Configured the TC for a given VF to allow only up to a given number | |
746 | * of Mb/s of outgoing Tx throughput. | |
747 | **/ | |
748 | static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate) | |
749 | { | |
750 | /* configure defaults */ | |
751 | u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3; | |
752 | u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK; | |
753 | ||
754 | /* verify vf is in range */ | |
755 | if (vf_idx >= hw->iov.num_vfs) | |
756 | return FM10K_ERR_PARAM; | |
757 | ||
758 | /* set interval to align with 4.096 usec in all modes */ | |
759 | switch (hw->bus.speed) { | |
760 | case fm10k_bus_speed_2500: | |
761 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN1; | |
762 | break; | |
763 | case fm10k_bus_speed_5000: | |
764 | interval = FM10K_TC_RATE_INTERVAL_4US_GEN2; | |
765 | break; | |
766 | default: | |
767 | break; | |
768 | } | |
769 | ||
770 | if (rate) { | |
771 | if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN) | |
772 | return FM10K_ERR_PARAM; | |
773 | ||
774 | /* The quanta is measured in Bytes per 4.096 or 8.192 usec | |
775 | * The rate is provided in Mbits per second | |
776 | * To tralslate from rate to quanta we need to multiply the | |
777 | * rate by 8.192 usec and divide by 8 bits/byte. To avoid | |
778 | * dealing with floating point we can round the values up | |
779 | * to the nearest whole number ratio which gives us 128 / 125. | |
780 | */ | |
781 | tc_rate = (rate * 128) / 125; | |
782 | ||
783 | /* try to keep the rate limiting accurate by increasing | |
784 | * the number of credits and interval for rates less than 4Gb/s | |
785 | */ | |
786 | if (rate < 4000) | |
787 | interval <<= 1; | |
788 | else | |
789 | tc_rate >>= 1; | |
790 | } | |
791 | ||
792 | /* update rate limiter with new values */ | |
793 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval); | |
794 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); | |
795 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | /** | |
801 | * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list | |
802 | * @hw: pointer to the HW structure | |
803 | * @vf_idx: index of VF receiving GLORT | |
804 | * | |
805 | * Update the interrupt moderator linked list to include any MSI-X | |
806 | * interrupts which the VF has enabled in the MSI-X vector table. | |
807 | **/ | |
808 | static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx) | |
809 | { | |
810 | u16 vf_v_idx, vf_v_limit, i; | |
811 | ||
812 | /* verify vf is in range */ | |
813 | if (vf_idx >= hw->iov.num_vfs) | |
814 | return FM10K_ERR_PARAM; | |
815 | ||
eca32047 | 816 | /* determine vector offset and count */ |
c2653865 AD |
817 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
818 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); | |
819 | ||
820 | /* search for first vector that is not masked */ | |
821 | for (i = vf_v_limit - 1; i > vf_v_idx; i--) { | |
822 | if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i))) | |
823 | break; | |
824 | } | |
825 | ||
826 | /* reset linked list so it now includes our active vectors */ | |
827 | if (vf_idx == (hw->iov.num_vfs - 1)) | |
828 | fm10k_write_reg(hw, FM10K_ITR2(0), i); | |
829 | else | |
830 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i); | |
831 | ||
832 | return 0; | |
833 | } | |
834 | ||
835 | /** | |
836 | * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF | |
837 | * @hw: pointer to the HW structure | |
838 | * @vf_info: pointer to VF information structure | |
839 | * | |
840 | * Assign a MAC address and default VLAN to a VF and notify it of the update | |
841 | **/ | |
842 | static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw, | |
843 | struct fm10k_vf_info *vf_info) | |
844 | { | |
845 | u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i; | |
846 | u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0; | |
847 | s32 err = 0; | |
848 | u16 vf_idx, vf_vid; | |
849 | ||
850 | /* verify vf is in range */ | |
851 | if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs) | |
852 | return FM10K_ERR_PARAM; | |
853 | ||
854 | /* determine qmap offsets and counts */ | |
855 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; | |
856 | queues_per_pool = fm10k_queues_per_pool(hw); | |
857 | ||
858 | /* calculate starting index for queues */ | |
859 | vf_idx = vf_info->vf_idx; | |
860 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); | |
861 | qmap_idx = qmap_stride * vf_idx; | |
862 | ||
863 | /* MAP Tx queue back to 0 temporarily, and disable it */ | |
864 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0); | |
865 | fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0); | |
866 | ||
867 | /* determine correct default VLAN ID */ | |
868 | if (vf_info->pf_vid) | |
869 | vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR; | |
870 | else | |
871 | vf_vid = vf_info->sw_vid; | |
872 | ||
873 | /* generate MAC_ADDR request */ | |
874 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN); | |
875 | fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC, | |
876 | vf_info->mac, vf_vid); | |
877 | ||
878 | /* load onto outgoing mailbox, ignore any errors on enqueue */ | |
879 | if (vf_info->mbx.ops.enqueue_tx) | |
880 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); | |
881 | ||
882 | /* verify ring has disabled before modifying base address registers */ | |
883 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); | |
884 | for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) { | |
885 | /* limit ourselves to a 1ms timeout */ | |
886 | if (timeout == 10) { | |
887 | err = FM10K_ERR_DMA_PENDING; | |
888 | goto err_out; | |
889 | } | |
890 | ||
891 | usleep_range(100, 200); | |
892 | txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx)); | |
893 | } | |
894 | ||
895 | /* Update base address registers to contain MAC address */ | |
896 | if (is_valid_ether_addr(vf_info->mac)) { | |
897 | tdbal = (((u32)vf_info->mac[3]) << 24) | | |
898 | (((u32)vf_info->mac[4]) << 16) | | |
899 | (((u32)vf_info->mac[5]) << 8); | |
900 | ||
901 | tdbah = (((u32)0xFF) << 24) | | |
902 | (((u32)vf_info->mac[0]) << 16) | | |
903 | (((u32)vf_info->mac[1]) << 8) | | |
904 | ((u32)vf_info->mac[2]); | |
905 | } | |
906 | ||
907 | /* Record the base address into queue 0 */ | |
908 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal); | |
909 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah); | |
910 | ||
20076fa1 JK |
911 | /* Provide the VF the ITR scale, using software-defined fields in TDLEN |
912 | * to pass the information during VF initialization. See definition of | |
913 | * FM10K_TDLEN_ITR_SCALE_SHIFT for more details. | |
914 | */ | |
915 | fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale << | |
916 | FM10K_TDLEN_ITR_SCALE_SHIFT); | |
917 | ||
c2653865 AD |
918 | err_out: |
919 | /* configure Queue control register */ | |
920 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) & | |
921 | FM10K_TXQCTL_VID_MASK; | |
922 | txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) | | |
923 | FM10K_TXQCTL_VF | vf_idx; | |
924 | ||
aa502b4a | 925 | /* assign VLAN ID */ |
c2653865 AD |
926 | for (i = 0; i < queues_per_pool; i++) |
927 | fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl); | |
928 | ||
929 | /* restore the queue back to VF ownership */ | |
930 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx); | |
931 | return err; | |
932 | } | |
933 | ||
934 | /** | |
935 | * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF | |
936 | * @hw: pointer to the HW structure | |
937 | * @vf_info: pointer to VF information structure | |
938 | * | |
939 | * Reassign the interrupts and queues to a VF following an FLR | |
940 | **/ | |
941 | static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw, | |
942 | struct fm10k_vf_info *vf_info) | |
943 | { | |
944 | u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx; | |
945 | u32 tdbal = 0, tdbah = 0, txqctl, rxqctl; | |
946 | u16 vf_v_idx, vf_v_limit, vf_vid; | |
947 | u8 vf_idx = vf_info->vf_idx; | |
948 | int i; | |
949 | ||
950 | /* verify vf is in range */ | |
951 | if (vf_idx >= hw->iov.num_vfs) | |
952 | return FM10K_ERR_PARAM; | |
953 | ||
954 | /* clear event notification of VF FLR */ | |
955 | fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32)); | |
956 | ||
957 | /* force timeout and then disconnect the mailbox */ | |
958 | vf_info->mbx.timeout = 0; | |
959 | if (vf_info->mbx.ops.disconnect) | |
960 | vf_info->mbx.ops.disconnect(hw, &vf_info->mbx); | |
961 | ||
eca32047 | 962 | /* determine vector offset and count */ |
c2653865 AD |
963 | vf_v_idx = fm10k_vf_vector_index(hw, vf_idx); |
964 | vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw); | |
965 | ||
966 | /* determine qmap offsets and counts */ | |
967 | qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256; | |
968 | queues_per_pool = fm10k_queues_per_pool(hw); | |
969 | qmap_idx = qmap_stride * vf_idx; | |
970 | ||
971 | /* make all the queues inaccessible to the VF */ | |
972 | for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) { | |
973 | fm10k_write_reg(hw, FM10K_TQMAP(i), 0); | |
974 | fm10k_write_reg(hw, FM10K_RQMAP(i), 0); | |
975 | } | |
976 | ||
977 | /* calculate starting index for queues */ | |
978 | vf_q_idx = fm10k_vf_queue_index(hw, vf_idx); | |
979 | ||
980 | /* determine correct default VLAN ID */ | |
981 | if (vf_info->pf_vid) | |
982 | vf_vid = vf_info->pf_vid; | |
983 | else | |
984 | vf_vid = vf_info->sw_vid; | |
985 | ||
986 | /* configure Queue control register */ | |
987 | txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) | | |
988 | (vf_idx << FM10K_TXQCTL_TC_SHIFT) | | |
989 | FM10K_TXQCTL_VF | vf_idx; | |
990 | rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT); | |
991 | ||
992 | /* stop further DMA and reset queue ownership back to VF */ | |
993 | for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) { | |
994 | fm10k_write_reg(hw, FM10K_TXDCTL(i), 0); | |
995 | fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl); | |
996 | fm10k_write_reg(hw, FM10K_RXDCTL(i), | |
997 | FM10K_RXDCTL_WRITE_BACK_MIN_DELAY | | |
998 | FM10K_RXDCTL_DROP_ON_EMPTY); | |
999 | fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl); | |
1000 | } | |
1001 | ||
1002 | /* reset TC with -1 credits and no quanta to prevent transmit */ | |
1003 | fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0); | |
1004 | fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0); | |
1005 | fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), | |
1006 | FM10K_TC_CREDIT_CREDIT_MASK); | |
1007 | ||
1008 | /* update our first entry in the table based on previous VF */ | |
1009 | if (!vf_idx) | |
1010 | hw->mac.ops.update_int_moderator(hw); | |
1011 | else | |
1012 | hw->iov.ops.assign_int_moderator(hw, vf_idx - 1); | |
1013 | ||
1014 | /* reset linked list so it now includes our active vectors */ | |
1015 | if (vf_idx == (hw->iov.num_vfs - 1)) | |
1016 | fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx); | |
1017 | else | |
1018 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx); | |
1019 | ||
1020 | /* link remaining vectors so that next points to previous */ | |
1021 | for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++) | |
1022 | fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1); | |
1023 | ||
1024 | /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */ | |
1025 | for (i = FM10K_VFMBMEM_LEN; i--;) | |
1026 | fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0); | |
1027 | for (i = FM10K_VLAN_TABLE_SIZE; i--;) | |
1028 | fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0); | |
1029 | for (i = FM10K_RETA_SIZE; i--;) | |
1030 | fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0); | |
1031 | for (i = FM10K_RSSRK_SIZE; i--;) | |
1032 | fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0); | |
1033 | fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0); | |
1034 | ||
1035 | /* Update base address registers to contain MAC address */ | |
1036 | if (is_valid_ether_addr(vf_info->mac)) { | |
1037 | tdbal = (((u32)vf_info->mac[3]) << 24) | | |
1038 | (((u32)vf_info->mac[4]) << 16) | | |
1039 | (((u32)vf_info->mac[5]) << 8); | |
1040 | tdbah = (((u32)0xFF) << 24) | | |
1041 | (((u32)vf_info->mac[0]) << 16) | | |
1042 | (((u32)vf_info->mac[1]) << 8) | | |
1043 | ((u32)vf_info->mac[2]); | |
1044 | } | |
1045 | ||
eca32047 | 1046 | /* map queue pairs back to VF from last to first */ |
c2653865 AD |
1047 | for (i = queues_per_pool; i--;) { |
1048 | fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal); | |
1049 | fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah); | |
20076fa1 JK |
1050 | /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an |
1051 | * explanation of how TDLEN is used. | |
1052 | */ | |
1053 | fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i), | |
1054 | hw->mac.itr_scale << | |
1055 | FM10K_TDLEN_ITR_SCALE_SHIFT); | |
c2653865 AD |
1056 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i); |
1057 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i); | |
1058 | } | |
1059 | ||
fba341d5 JK |
1060 | /* repeat the first ring for all the remaining VF rings */ |
1061 | for (i = queues_per_pool; i < qmap_stride; i++) { | |
1062 | fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx); | |
1063 | fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx); | |
1064 | } | |
1065 | ||
c2653865 AD |
1066 | return 0; |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF | |
1071 | * @hw: pointer to hardware structure | |
1072 | * @vf_info: pointer to VF information structure | |
1073 | * @lport_idx: Logical port offset from the hardware glort | |
1074 | * @flags: Set of capability flags to extend port beyond basic functionality | |
1075 | * | |
1076 | * This function allows enabling a VF port by assigning it a GLORT and | |
1077 | * setting the flags so that it can enable an Rx mode. | |
1078 | **/ | |
1079 | static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw, | |
1080 | struct fm10k_vf_info *vf_info, | |
1081 | u16 lport_idx, u8 flags) | |
1082 | { | |
1083 | u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE; | |
1084 | ||
1085 | /* if glort is not valid return error */ | |
1086 | if (!fm10k_glort_valid_pf(hw, glort)) | |
1087 | return FM10K_ERR_PARAM; | |
1088 | ||
1089 | vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE; | |
1090 | vf_info->glort = glort; | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | /** | |
1096 | * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF | |
1097 | * @hw: pointer to hardware structure | |
1098 | * @vf_info: pointer to VF information structure | |
1099 | * | |
1100 | * This function disables a VF port by stripping it of a GLORT and | |
1101 | * setting the flags so that it cannot enable any Rx mode. | |
1102 | **/ | |
1103 | static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw, | |
1104 | struct fm10k_vf_info *vf_info) | |
1105 | { | |
1106 | u32 msg[1]; | |
1107 | ||
1108 | /* need to disable the port if it is already enabled */ | |
1109 | if (FM10K_VF_FLAG_ENABLED(vf_info)) { | |
1110 | /* notify switch that this port has been disabled */ | |
1111 | fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false); | |
1112 | ||
1113 | /* generate port state response to notify VF it is not ready */ | |
1114 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); | |
1115 | vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); | |
1116 | } | |
1117 | ||
1118 | /* clear flags and glort if it exists */ | |
1119 | vf_info->vf_flags = 0; | |
1120 | vf_info->glort = 0; | |
1121 | } | |
1122 | ||
1123 | /** | |
1124 | * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs | |
1125 | * @hw: pointer to hardware structure | |
1126 | * @q: stats for all queues of a VF | |
1127 | * @vf_idx: index of VF | |
1128 | * | |
1129 | * This function collects queue stats for VFs. | |
1130 | **/ | |
1131 | static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw, | |
1132 | struct fm10k_hw_stats_q *q, | |
1133 | u16 vf_idx) | |
1134 | { | |
1135 | u32 idx, qpp; | |
1136 | ||
1137 | /* get stats for all of the queues */ | |
1138 | qpp = fm10k_queues_per_pool(hw); | |
1139 | idx = fm10k_vf_queue_index(hw, vf_idx); | |
1140 | fm10k_update_hw_stats_q(hw, q, idx, qpp); | |
1141 | } | |
1142 | ||
5f226ddb AD |
1143 | static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw, |
1144 | struct fm10k_vf_info *vf_info, | |
1145 | u64 timestamp) | |
1146 | { | |
1147 | u32 msg[4]; | |
1148 | ||
1149 | /* generate port state response to notify VF it is not ready */ | |
1150 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588); | |
1151 | fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp); | |
1152 | ||
1153 | return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg); | |
1154 | } | |
1155 | ||
c2653865 AD |
1156 | /** |
1157 | * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF | |
1158 | * @hw: Pointer to hardware structure | |
1159 | * @results: Pointer array to message, results[0] is pointer to message | |
1160 | * @mbx: Pointer to mailbox information structure | |
1161 | * | |
1162 | * This function is a default handler for MSI-X requests from the VF. The | |
1163 | * assumption is that in this case it is acceptable to just directly | |
eca32047 | 1164 | * hand off the message from the VF to the underlying shared code. |
c2653865 AD |
1165 | **/ |
1166 | s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results, | |
1167 | struct fm10k_mbx_info *mbx) | |
1168 | { | |
1169 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; | |
1170 | u8 vf_idx = vf_info->vf_idx; | |
1171 | ||
1172 | return hw->iov.ops.assign_int_moderator(hw, vf_idx); | |
1173 | } | |
1174 | ||
9adbac59 | 1175 | /** |
aa502b4a | 1176 | * fm10k_iov_select_vid - Select correct default VLAN ID |
9adbac59 | 1177 | * @hw: Pointer to hardware structure |
aa502b4a | 1178 | * @vid: VLAN ID to correct |
9adbac59 | 1179 | * |
aa502b4a JK |
1180 | * Will report an error if the VLAN ID is out of range. For VID = 0, it will |
1181 | * return either the pf_vid or sw_vid depending on which one is set. | |
9adbac59 | 1182 | */ |
e214d85b | 1183 | static s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid) |
9adbac59 JK |
1184 | { |
1185 | if (!vid) | |
1186 | return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid; | |
1187 | else if (vf_info->pf_vid && vid != vf_info->pf_vid) | |
1188 | return FM10K_ERR_PARAM; | |
1189 | else | |
1190 | return vid; | |
1191 | } | |
1192 | ||
c2653865 AD |
1193 | /** |
1194 | * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF | |
1195 | * @hw: Pointer to hardware structure | |
1196 | * @results: Pointer array to message, results[0] is pointer to message | |
1197 | * @mbx: Pointer to mailbox information structure | |
1198 | * | |
1199 | * This function is a default handler for MAC/VLAN requests from the VF. | |
1200 | * The assumption is that in this case it is acceptable to just directly | |
eca32047 | 1201 | * hand off the message from the VF to the underlying shared code. |
c2653865 AD |
1202 | **/ |
1203 | s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results, | |
1204 | struct fm10k_mbx_info *mbx) | |
1205 | { | |
1206 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; | |
c2653865 AD |
1207 | u8 mac[ETH_ALEN]; |
1208 | u32 *result; | |
9adbac59 JK |
1209 | int err = 0; |
1210 | bool set; | |
c2653865 AD |
1211 | u16 vlan; |
1212 | u32 vid; | |
1213 | ||
1214 | /* we shouldn't be updating rules on a disabled interface */ | |
1215 | if (!FM10K_VF_FLAG_ENABLED(vf_info)) | |
1216 | err = FM10K_ERR_PARAM; | |
1217 | ||
1218 | if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) { | |
1219 | result = results[FM10K_MAC_VLAN_MSG_VLAN]; | |
1220 | ||
1221 | /* record VLAN id requested */ | |
1222 | err = fm10k_tlv_attr_get_u32(result, &vid); | |
1223 | if (err) | |
1224 | return err; | |
1225 | ||
9adbac59 JK |
1226 | set = !(vid & FM10K_VLAN_CLEAR); |
1227 | vid &= ~FM10K_VLAN_CLEAR; | |
1228 | ||
f808c5db JK |
1229 | /* if the length field has been set, this is a multi-bit |
1230 | * update request. For multi-bit requests, simply disallow | |
1231 | * them when the pf_vid has been set. In this case, the PF | |
1232 | * should have already cleared the VLAN_TABLE, and if we | |
1233 | * allowed them, it could allow a rogue VF to receive traffic | |
1234 | * on a VLAN it was not assigned. In the single-bit case, we | |
1235 | * need to modify requests for VLAN 0 to use the default PF or | |
1236 | * SW vid when assigned. | |
1237 | */ | |
4ab0f79b | 1238 | |
f808c5db JK |
1239 | if (vid >> 16) { |
1240 | /* prevent multi-bit requests when PF has | |
1241 | * administratively set the VLAN for this VF | |
1242 | */ | |
1243 | if (vf_info->pf_vid) | |
1244 | return FM10K_ERR_PARAM; | |
1245 | } else { | |
1246 | err = fm10k_iov_select_vid(vf_info, (u16)vid); | |
1247 | if (err < 0) | |
1248 | return err; | |
1249 | ||
1250 | vid = err; | |
1251 | } | |
c2653865 AD |
1252 | |
1253 | /* update VSI info for VF in regards to VLAN table */ | |
9adbac59 | 1254 | err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set); |
c2653865 AD |
1255 | } |
1256 | ||
1257 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) { | |
1258 | result = results[FM10K_MAC_VLAN_MSG_MAC]; | |
1259 | ||
1260 | /* record unicast MAC address requested */ | |
1261 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); | |
1262 | if (err) | |
1263 | return err; | |
1264 | ||
1265 | /* block attempts to set MAC for a locked device */ | |
1266 | if (is_valid_ether_addr(vf_info->mac) && | |
6186ddf0 | 1267 | !ether_addr_equal(mac, vf_info->mac)) |
c2653865 AD |
1268 | return FM10K_ERR_PARAM; |
1269 | ||
9adbac59 JK |
1270 | set = !(vlan & FM10K_VLAN_CLEAR); |
1271 | vlan &= ~FM10K_VLAN_CLEAR; | |
1272 | ||
1273 | err = fm10k_iov_select_vid(vf_info, vlan); | |
1274 | if (err < 0) | |
1275 | return err; | |
4ab0f79b JK |
1276 | |
1277 | vlan = (u16)err; | |
c2653865 AD |
1278 | |
1279 | /* notify switch of request for new unicast address */ | |
9adbac59 JK |
1280 | err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, |
1281 | mac, vlan, set, 0); | |
c2653865 AD |
1282 | } |
1283 | ||
1284 | if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) { | |
1285 | result = results[FM10K_MAC_VLAN_MSG_MULTICAST]; | |
1286 | ||
1287 | /* record multicast MAC address requested */ | |
1288 | err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan); | |
1289 | if (err) | |
1290 | return err; | |
1291 | ||
1292 | /* verify that the VF is allowed to request multicast */ | |
1293 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED)) | |
1294 | return FM10K_ERR_PARAM; | |
1295 | ||
9adbac59 JK |
1296 | set = !(vlan & FM10K_VLAN_CLEAR); |
1297 | vlan &= ~FM10K_VLAN_CLEAR; | |
1298 | ||
1299 | err = fm10k_iov_select_vid(vf_info, vlan); | |
1300 | if (err < 0) | |
1301 | return err; | |
4ab0f79b JK |
1302 | |
1303 | vlan = (u16)err; | |
c2653865 AD |
1304 | |
1305 | /* notify switch of request for new multicast address */ | |
9adbac59 JK |
1306 | err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, |
1307 | mac, vlan, set); | |
c2653865 AD |
1308 | } |
1309 | ||
1310 | return err; | |
1311 | } | |
1312 | ||
1313 | /** | |
1314 | * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode | |
1315 | * @vf_info: VF info structure containing capability flags | |
1316 | * @mode: Requested xcast mode | |
1317 | * | |
1318 | * This function outputs the mode that most closely matches the requested | |
1319 | * mode. If not modes match it will request we disable the port | |
1320 | **/ | |
1321 | static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info, | |
1322 | u8 mode) | |
1323 | { | |
1324 | u8 vf_flags = vf_info->vf_flags; | |
1325 | ||
1326 | /* match up mode to capabilities as best as possible */ | |
1327 | switch (mode) { | |
1328 | case FM10K_XCAST_MODE_PROMISC: | |
1329 | if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE) | |
1330 | return FM10K_XCAST_MODE_PROMISC; | |
1331 | /* fallthough */ | |
1332 | case FM10K_XCAST_MODE_ALLMULTI: | |
1333 | if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE) | |
1334 | return FM10K_XCAST_MODE_ALLMULTI; | |
1335 | /* fallthough */ | |
1336 | case FM10K_XCAST_MODE_MULTI: | |
1337 | if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE) | |
1338 | return FM10K_XCAST_MODE_MULTI; | |
1339 | /* fallthough */ | |
1340 | case FM10K_XCAST_MODE_NONE: | |
1341 | if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE) | |
1342 | return FM10K_XCAST_MODE_NONE; | |
1343 | /* fallthough */ | |
1344 | default: | |
1345 | break; | |
1346 | } | |
1347 | ||
1348 | /* disable interface as it should not be able to request any */ | |
1349 | return FM10K_XCAST_MODE_DISABLE; | |
1350 | } | |
1351 | ||
1352 | /** | |
1353 | * fm10k_iov_msg_lport_state_pf - Message handler for port state requests | |
1354 | * @hw: Pointer to hardware structure | |
1355 | * @results: Pointer array to message, results[0] is pointer to message | |
1356 | * @mbx: Pointer to mailbox information structure | |
1357 | * | |
1358 | * This function is a default handler for port state requests. The port | |
1359 | * state requests for now are basic and consist of enabling or disabling | |
1360 | * the port. | |
1361 | **/ | |
1362 | s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results, | |
1363 | struct fm10k_mbx_info *mbx) | |
1364 | { | |
1365 | struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx; | |
1366 | u32 *result; | |
1367 | s32 err = 0; | |
1368 | u32 msg[2]; | |
1369 | u8 mode = 0; | |
1370 | ||
1371 | /* verify VF is allowed to enable even minimal mode */ | |
1372 | if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)) | |
1373 | return FM10K_ERR_PARAM; | |
1374 | ||
1375 | if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) { | |
1376 | result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE]; | |
1377 | ||
1378 | /* XCAST mode update requested */ | |
1379 | err = fm10k_tlv_attr_get_u8(result, &mode); | |
1380 | if (err) | |
1381 | return FM10K_ERR_PARAM; | |
1382 | ||
1383 | /* prep for possible demotion depending on capabilities */ | |
1384 | mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode); | |
1385 | ||
1386 | /* if mode is not currently enabled, enable it */ | |
1387 | if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode))) | |
1388 | fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode); | |
1389 | ||
1390 | /* swap mode back to a bit flag */ | |
1391 | mode = FM10K_VF_FLAG_SET_MODE(mode); | |
1392 | } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) { | |
1393 | /* need to disable the port if it is already enabled */ | |
1394 | if (FM10K_VF_FLAG_ENABLED(vf_info)) | |
1395 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, | |
1396 | 1, false); | |
1397 | ||
ee4373e7 JK |
1398 | /* we need to clear VF_FLAG_ENABLED flags in order to ensure |
1399 | * that we actually re-enable the LPORT state below. Note that | |
1400 | * this has no impact if the VF is already disabled, as the | |
1401 | * flags are already cleared. | |
1402 | */ | |
1403 | if (!err) | |
1404 | vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info); | |
1405 | ||
c2653865 AD |
1406 | /* when enabling the port we should reset the rate limiters */ |
1407 | hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate); | |
1408 | ||
1409 | /* set mode for minimal functionality */ | |
1410 | mode = FM10K_VF_FLAG_SET_MODE_NONE; | |
1411 | ||
1412 | /* generate port state response to notify VF it is ready */ | |
1413 | fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); | |
1414 | fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY); | |
1415 | mbx->ops.enqueue_tx(hw, mbx, msg); | |
1416 | } | |
1417 | ||
1418 | /* if enable state toggled note the update */ | |
1419 | if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode)) | |
1420 | err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1, | |
1421 | !!mode); | |
1422 | ||
1423 | /* if state change succeeded, then update our stored state */ | |
1424 | mode |= FM10K_VF_FLAG_CAPABLE(vf_info); | |
1425 | if (!err) | |
1426 | vf_info->vf_flags = mode; | |
1427 | ||
1428 | return err; | |
1429 | } | |
1430 | ||
b6fec18f AD |
1431 | /** |
1432 | * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF | |
1433 | * @hw: pointer to hardware structure | |
1434 | * @stats: pointer to the stats structure to update | |
1435 | * | |
1436 | * This function collects and aggregates global and per queue hardware | |
1437 | * statistics. | |
1438 | **/ | |
1439 | static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw, | |
1440 | struct fm10k_hw_stats *stats) | |
1441 | { | |
1442 | u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop; | |
1443 | u32 id, id_prev; | |
1444 | ||
1445 | /* Use Tx queue 0 as a canary to detect a reset */ | |
1446 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); | |
1447 | ||
1448 | /* Read Global Statistics */ | |
1449 | do { | |
1450 | timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT, | |
1451 | &stats->timeout); | |
1452 | ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur); | |
1453 | ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca); | |
1454 | um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um); | |
1455 | xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec); | |
1456 | vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP, | |
1457 | &stats->vlan_drop); | |
3d02b3df BA |
1458 | loopback_drop = |
1459 | fm10k_read_hw_stats_32b(hw, | |
1460 | FM10K_STATS_LOOPBACK_DROP, | |
1461 | &stats->loopback_drop); | |
b6fec18f AD |
1462 | nodesc_drop = fm10k_read_hw_stats_32b(hw, |
1463 | FM10K_STATS_NODESC_DROP, | |
1464 | &stats->nodesc_drop); | |
1465 | ||
1466 | /* if value has not changed then we have consistent data */ | |
1467 | id_prev = id; | |
1468 | id = fm10k_read_reg(hw, FM10K_TXQCTL(0)); | |
1469 | } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK); | |
1470 | ||
1471 | /* drop non-ID bits and set VALID ID bit */ | |
1472 | id &= FM10K_TXQCTL_ID_MASK; | |
1473 | id |= FM10K_STAT_VALID; | |
1474 | ||
1475 | /* Update Global Statistics */ | |
1476 | if (stats->stats_idx == id) { | |
1477 | stats->timeout.count += timeout; | |
1478 | stats->ur.count += ur; | |
1479 | stats->ca.count += ca; | |
1480 | stats->um.count += um; | |
1481 | stats->xec.count += xec; | |
1482 | stats->vlan_drop.count += vlan_drop; | |
1483 | stats->loopback_drop.count += loopback_drop; | |
1484 | stats->nodesc_drop.count += nodesc_drop; | |
1485 | } | |
1486 | ||
1487 | /* Update bases and record current PF id */ | |
1488 | fm10k_update_hw_base_32b(&stats->timeout, timeout); | |
1489 | fm10k_update_hw_base_32b(&stats->ur, ur); | |
1490 | fm10k_update_hw_base_32b(&stats->ca, ca); | |
1491 | fm10k_update_hw_base_32b(&stats->um, um); | |
1492 | fm10k_update_hw_base_32b(&stats->xec, xec); | |
1493 | fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop); | |
1494 | fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop); | |
1495 | fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop); | |
1496 | stats->stats_idx = id; | |
1497 | ||
1498 | /* Update Queue Statistics */ | |
1499 | fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues); | |
1500 | } | |
1501 | ||
1502 | /** | |
1503 | * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF | |
1504 | * @hw: pointer to hardware structure | |
1505 | * @stats: pointer to the stats structure to update | |
1506 | * | |
1507 | * This function resets the base for global and per queue hardware | |
1508 | * statistics. | |
1509 | **/ | |
1510 | static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw, | |
1511 | struct fm10k_hw_stats *stats) | |
1512 | { | |
1513 | /* Unbind Global Statistics */ | |
1514 | fm10k_unbind_hw_stats_32b(&stats->timeout); | |
1515 | fm10k_unbind_hw_stats_32b(&stats->ur); | |
1516 | fm10k_unbind_hw_stats_32b(&stats->ca); | |
1517 | fm10k_unbind_hw_stats_32b(&stats->um); | |
1518 | fm10k_unbind_hw_stats_32b(&stats->xec); | |
1519 | fm10k_unbind_hw_stats_32b(&stats->vlan_drop); | |
1520 | fm10k_unbind_hw_stats_32b(&stats->loopback_drop); | |
1521 | fm10k_unbind_hw_stats_32b(&stats->nodesc_drop); | |
1522 | ||
1523 | /* Unbind Queue Statistics */ | |
1524 | fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues); | |
1525 | ||
1526 | /* Reinitialize bases for all stats */ | |
1527 | fm10k_update_hw_stats_pf(hw, stats); | |
1528 | } | |
1529 | ||
401b5383 AD |
1530 | /** |
1531 | * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system | |
1532 | * @hw: pointer to hardware structure | |
1533 | * @dma_mask: 64 bit DMA mask required for platform | |
1534 | * | |
1535 | * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order | |
1536 | * to limit the access to memory beyond what is physically in the system. | |
1537 | **/ | |
1538 | static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask) | |
1539 | { | |
1540 | /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */ | |
1541 | u32 phyaddr = (u32)(dma_mask >> 32); | |
1542 | ||
1543 | fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr); | |
1544 | } | |
1545 | ||
b6fec18f AD |
1546 | /** |
1547 | * fm10k_get_fault_pf - Record a fault in one of the interface units | |
1548 | * @hw: pointer to hardware structure | |
1549 | * @type: pointer to fault type register offset | |
1550 | * @fault: pointer to memory location to record the fault | |
1551 | * | |
1552 | * Record the fault register contents to the fault data structure and | |
1553 | * clear the entry from the register. | |
1554 | * | |
1555 | * Returns ERR_PARAM if invalid register is specified or no error is present. | |
1556 | **/ | |
1557 | static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type, | |
1558 | struct fm10k_fault *fault) | |
1559 | { | |
1560 | u32 func; | |
1561 | ||
1562 | /* verify the fault register is in range and is aligned */ | |
1563 | switch (type) { | |
1564 | case FM10K_PCA_FAULT: | |
1565 | case FM10K_THI_FAULT: | |
1566 | case FM10K_FUM_FAULT: | |
1567 | break; | |
1568 | default: | |
1569 | return FM10K_ERR_PARAM; | |
1570 | } | |
1571 | ||
1572 | /* only service faults that are valid */ | |
1573 | func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC); | |
1574 | if (!(func & FM10K_FAULT_FUNC_VALID)) | |
1575 | return FM10K_ERR_PARAM; | |
1576 | ||
1577 | /* read remaining fields */ | |
1578 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI); | |
1579 | fault->address <<= 32; | |
1580 | fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO); | |
1581 | fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO); | |
1582 | ||
1583 | /* clear valid bit to allow for next error */ | |
1584 | fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID); | |
1585 | ||
1586 | /* Record which function triggered the error */ | |
1587 | if (func & FM10K_FAULT_FUNC_PF) | |
1588 | fault->func = 0; | |
1589 | else | |
1590 | fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >> | |
1591 | FM10K_FAULT_FUNC_VF_SHIFT); | |
1592 | ||
1593 | /* record fault type */ | |
1594 | fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK; | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
401b5383 AD |
1599 | /** |
1600 | * fm10k_request_lport_map_pf - Request LPORT map from the switch API | |
1601 | * @hw: pointer to hardware structure | |
1602 | * | |
1603 | **/ | |
1604 | static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw) | |
1605 | { | |
1606 | struct fm10k_mbx_info *mbx = &hw->mbx; | |
1607 | u32 msg[1]; | |
1608 | ||
1609 | /* issue request asking for LPORT map */ | |
1610 | fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP); | |
1611 | ||
1612 | /* load onto outgoing mailbox */ | |
1613 | return mbx->ops.enqueue_tx(hw, mbx, msg); | |
1614 | } | |
1615 | ||
1616 | /** | |
1617 | * fm10k_get_host_state_pf - Returns the state of the switch and mailbox | |
1618 | * @hw: pointer to hardware structure | |
1619 | * @switch_ready: pointer to boolean value that will record switch state | |
1620 | * | |
1621 | * This funciton will check the DMA_CTRL2 register and mailbox in order | |
1622 | * to determine if the switch is ready for the PF to begin requesting | |
1623 | * addresses and mapping traffic to the local interface. | |
1624 | **/ | |
1625 | static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready) | |
1626 | { | |
1627 | s32 ret_val = 0; | |
1628 | u32 dma_ctrl2; | |
1629 | ||
eca32047 | 1630 | /* verify the switch is ready for interaction */ |
401b5383 AD |
1631 | dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2); |
1632 | if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY)) | |
1633 | goto out; | |
1634 | ||
1635 | /* retrieve generic host state info */ | |
1636 | ret_val = fm10k_get_host_state_generic(hw, switch_ready); | |
1637 | if (ret_val) | |
1638 | goto out; | |
1639 | ||
1640 | /* interface cannot receive traffic without logical ports */ | |
1641 | if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE) | |
1642 | ret_val = fm10k_request_lport_map_pf(hw); | |
1643 | ||
1644 | out: | |
1645 | return ret_val; | |
1646 | } | |
1647 | ||
1648 | /* This structure defines the attibutes to be parsed below */ | |
1649 | const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = { | |
1650 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP), | |
1651 | FM10K_TLV_ATTR_LAST | |
1652 | }; | |
1653 | ||
1654 | /** | |
1655 | * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM | |
1656 | * @hw: Pointer to hardware structure | |
1657 | * @results: pointer array containing parsed data | |
1658 | * @mbx: Pointer to mailbox information structure | |
1659 | * | |
1660 | * This handler configures the lport mapping based on the reply from the | |
1661 | * switch API. | |
1662 | **/ | |
1663 | s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results, | |
1664 | struct fm10k_mbx_info *mbx) | |
1665 | { | |
1666 | u16 glort, mask; | |
1667 | u32 dglort_map; | |
1668 | s32 err; | |
1669 | ||
1670 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP], | |
1671 | &dglort_map); | |
1672 | if (err) | |
1673 | return err; | |
1674 | ||
1675 | /* extract values out of the header */ | |
1676 | glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT); | |
1677 | mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK); | |
1678 | ||
1679 | /* verify mask is set and none of the masked bits in glort are set */ | |
1680 | if (!mask || (glort & ~mask)) | |
1681 | return FM10K_ERR_PARAM; | |
1682 | ||
1683 | /* verify the mask is contiguous, and that it is 1's followed by 0's */ | |
1684 | if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE) | |
1685 | return FM10K_ERR_PARAM; | |
1686 | ||
1687 | /* record the glort, mask, and port count */ | |
1688 | hw->mac.dglort_map = dglort_map; | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = { | |
1694 | FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID), | |
1695 | FM10K_TLV_ATTR_LAST | |
1696 | }; | |
1697 | ||
1698 | /** | |
1699 | * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM | |
1700 | * @hw: Pointer to hardware structure | |
1701 | * @results: pointer array containing parsed data | |
1702 | * @mbx: Pointer to mailbox information structure | |
1703 | * | |
1704 | * This handler configures the default VLAN for the PF | |
1705 | **/ | |
bb269e8b BA |
1706 | static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results, |
1707 | struct fm10k_mbx_info *mbx) | |
401b5383 AD |
1708 | { |
1709 | u16 glort, pvid; | |
1710 | u32 pvid_update; | |
1711 | s32 err; | |
1712 | ||
1713 | err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID], | |
1714 | &pvid_update); | |
1715 | if (err) | |
1716 | return err; | |
1717 | ||
1718 | /* extract values from the pvid update */ | |
1719 | glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT); | |
1720 | pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID); | |
1721 | ||
1722 | /* if glort is not valid return error */ | |
1723 | if (!fm10k_glort_valid_pf(hw, glort)) | |
1724 | return FM10K_ERR_PARAM; | |
1725 | ||
aa502b4a | 1726 | /* verify VLAN ID is valid */ |
401b5383 AD |
1727 | if (pvid >= FM10K_VLAN_TABLE_VID_MAX) |
1728 | return FM10K_ERR_PARAM; | |
1729 | ||
1730 | /* record the port VLAN ID value */ | |
1731 | hw->mac.default_vid = pvid; | |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | /** | |
1737 | * fm10k_record_global_table_data - Move global table data to swapi table info | |
1738 | * @from: pointer to source table data structure | |
1739 | * @to: pointer to destination table info structure | |
1740 | * | |
1741 | * This function is will copy table_data to the table_info contained in | |
1742 | * the hw struct. | |
1743 | **/ | |
1744 | static void fm10k_record_global_table_data(struct fm10k_global_table_data *from, | |
1745 | struct fm10k_swapi_table_info *to) | |
1746 | { | |
1747 | /* convert from le32 struct to CPU byte ordered values */ | |
1748 | to->used = le32_to_cpu(from->used); | |
1749 | to->avail = le32_to_cpu(from->avail); | |
1750 | } | |
1751 | ||
1752 | const struct fm10k_tlv_attr fm10k_err_msg_attr[] = { | |
1753 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR, | |
1754 | sizeof(struct fm10k_swapi_error)), | |
1755 | FM10K_TLV_ATTR_LAST | |
1756 | }; | |
1757 | ||
1758 | /** | |
1759 | * fm10k_msg_err_pf - Message handler for error reply | |
1760 | * @hw: Pointer to hardware structure | |
1761 | * @results: pointer array containing parsed data | |
1762 | * @mbx: Pointer to mailbox information structure | |
1763 | * | |
1764 | * This handler will capture the data for any error replies to previous | |
1765 | * messages that the PF has sent. | |
1766 | **/ | |
1767 | s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results, | |
1768 | struct fm10k_mbx_info *mbx) | |
1769 | { | |
1770 | struct fm10k_swapi_error err_msg; | |
1771 | s32 err; | |
1772 | ||
1773 | /* extract structure from message */ | |
1774 | err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR], | |
1775 | &err_msg, sizeof(err_msg)); | |
1776 | if (err) | |
1777 | return err; | |
1778 | ||
1779 | /* record table status */ | |
1780 | fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac); | |
1781 | fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop); | |
1782 | fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu); | |
1783 | ||
1784 | /* record SW API status value */ | |
1785 | hw->swapi.status = le32_to_cpu(err_msg.status); | |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
5f226ddb AD |
1790 | const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = { |
1791 | FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP, | |
1792 | sizeof(struct fm10k_swapi_1588_timestamp)), | |
1793 | FM10K_TLV_ATTR_LAST | |
1794 | }; | |
1795 | ||
1796 | /* currently there is no shared 1588 timestamp handler */ | |
1797 | ||
1798 | /** | |
1799 | * fm10k_adjust_systime_pf - Adjust systime frequency | |
1800 | * @hw: pointer to hardware structure | |
1801 | * @ppb: adjustment rate in parts per billion | |
1802 | * | |
1803 | * This function will adjust the SYSTIME_CFG register contained in BAR 4 | |
1804 | * if this function is supported for BAR 4 access. The adjustment amount | |
1805 | * is based on the parts per billion value provided and adjusted to a | |
1806 | * value based on parts per 2^48 clock cycles. | |
1807 | * | |
1808 | * If adjustment is not supported or the requested value is too large | |
1809 | * we will return an error. | |
1810 | **/ | |
1811 | static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb) | |
1812 | { | |
1813 | u64 systime_adjust; | |
1814 | ||
1815 | /* if sw_addr is not set we don't have switch register access */ | |
1816 | if (!hw->sw_addr) | |
1817 | return ppb ? FM10K_ERR_PARAM : 0; | |
1818 | ||
1819 | /* we must convert the value from parts per billion to parts per | |
1820 | * 2^48 cycles. In addition I have opted to only use the 30 most | |
1821 | * significant bits of the adjustment value as the 8 least | |
1822 | * significant bits are located in another register and represent | |
1823 | * a value significantly less than a part per billion, the result | |
1824 | * of dropping the 8 least significant bits is that the adjustment | |
1825 | * value is effectively multiplied by 2^8 when we write it. | |
1826 | * | |
1827 | * As a result of all this the math for this breaks down as follows: | |
1828 | * ppb / 10^9 == adjust * 2^8 / 2^48 | |
1829 | * If we solve this for adjust, and simplify it comes out as: | |
1830 | * ppb * 2^31 / 5^9 == adjust | |
1831 | */ | |
1832 | systime_adjust = (ppb < 0) ? -ppb : ppb; | |
1833 | systime_adjust <<= 31; | |
1834 | do_div(systime_adjust, 1953125); | |
1835 | ||
1836 | /* verify the requested adjustment value is in range */ | |
1837 | if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK) | |
1838 | return FM10K_ERR_PARAM; | |
1839 | ||
646725a7 JK |
1840 | if (ppb > 0) |
1841 | systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE; | |
5f226ddb AD |
1842 | |
1843 | fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust); | |
1844 | ||
1845 | return 0; | |
1846 | } | |
1847 | ||
1848 | /** | |
1849 | * fm10k_read_systime_pf - Reads value of systime registers | |
1850 | * @hw: pointer to the hardware structure | |
1851 | * | |
1852 | * Function reads the content of 2 registers, combined to represent a 64 bit | |
1853 | * value measured in nanosecods. In order to guarantee the value is accurate | |
1854 | * we check the 32 most significant bits both before and after reading the | |
1855 | * 32 least significant bits to verify they didn't change as we were reading | |
1856 | * the registers. | |
1857 | **/ | |
1858 | static u64 fm10k_read_systime_pf(struct fm10k_hw *hw) | |
1859 | { | |
1860 | u32 systime_l, systime_h, systime_tmp; | |
1861 | ||
1862 | systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); | |
1863 | ||
1864 | do { | |
1865 | systime_tmp = systime_h; | |
1866 | systime_l = fm10k_read_reg(hw, FM10K_SYSTIME); | |
1867 | systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1); | |
1868 | } while (systime_tmp != systime_h); | |
1869 | ||
1870 | return ((u64)systime_h << 32) | systime_l; | |
1871 | } | |
1872 | ||
401b5383 AD |
1873 | static const struct fm10k_msg_data fm10k_msg_data_pf[] = { |
1874 | FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf), | |
1875 | FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf), | |
1876 | FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf), | |
1877 | FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf), | |
1878 | FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf), | |
1879 | FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf), | |
1880 | FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error), | |
1881 | }; | |
1882 | ||
f329ad73 | 1883 | static const struct fm10k_mac_ops mac_ops_pf = { |
4e458cfb BA |
1884 | .get_bus_info = fm10k_get_bus_info_generic, |
1885 | .reset_hw = fm10k_reset_hw_pf, | |
1886 | .init_hw = fm10k_init_hw_pf, | |
1887 | .start_hw = fm10k_start_hw_generic, | |
1888 | .stop_hw = fm10k_stop_hw_generic, | |
1889 | .update_vlan = fm10k_update_vlan_pf, | |
1890 | .read_mac_addr = fm10k_read_mac_addr_pf, | |
1891 | .update_uc_addr = fm10k_update_uc_addr_pf, | |
1892 | .update_mc_addr = fm10k_update_mc_addr_pf, | |
1893 | .update_xcast_mode = fm10k_update_xcast_mode_pf, | |
1894 | .update_int_moderator = fm10k_update_int_moderator_pf, | |
1895 | .update_lport_state = fm10k_update_lport_state_pf, | |
1896 | .update_hw_stats = fm10k_update_hw_stats_pf, | |
1897 | .rebind_hw_stats = fm10k_rebind_hw_stats_pf, | |
1898 | .configure_dglort_map = fm10k_configure_dglort_map_pf, | |
1899 | .set_dma_mask = fm10k_set_dma_mask_pf, | |
1900 | .get_fault = fm10k_get_fault_pf, | |
1901 | .get_host_state = fm10k_get_host_state_pf, | |
1902 | .adjust_systime = fm10k_adjust_systime_pf, | |
1903 | .read_systime = fm10k_read_systime_pf, | |
b6fec18f AD |
1904 | }; |
1905 | ||
f329ad73 | 1906 | static const struct fm10k_iov_ops iov_ops_pf = { |
4e458cfb BA |
1907 | .assign_resources = fm10k_iov_assign_resources_pf, |
1908 | .configure_tc = fm10k_iov_configure_tc_pf, | |
1909 | .assign_int_moderator = fm10k_iov_assign_int_moderator_pf, | |
c2653865 | 1910 | .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf, |
4e458cfb BA |
1911 | .reset_resources = fm10k_iov_reset_resources_pf, |
1912 | .set_lport = fm10k_iov_set_lport_pf, | |
1913 | .reset_lport = fm10k_iov_reset_lport_pf, | |
1914 | .update_stats = fm10k_iov_update_stats_pf, | |
1915 | .report_timestamp = fm10k_iov_report_timestamp_pf, | |
c2653865 AD |
1916 | }; |
1917 | ||
401b5383 AD |
1918 | static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw) |
1919 | { | |
1920 | fm10k_get_invariants_generic(hw); | |
1921 | ||
1922 | return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf); | |
1923 | } | |
1924 | ||
f329ad73 | 1925 | const struct fm10k_info fm10k_pf_info = { |
b6fec18f | 1926 | .mac = fm10k_mac_pf, |
4e458cfb | 1927 | .get_invariants = fm10k_get_invariants_pf, |
b6fec18f | 1928 | .mac_ops = &mac_ops_pf, |
c2653865 | 1929 | .iov_ops = &iov_ops_pf, |
b6fec18f | 1930 | }; |