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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / ethernet / intel / fm10k / fm10k_pf.c
CommitLineData
b6fec18f
AD		 1/* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
19 */
20
21#include "fm10k_pf.h"
c2653865 22#include "fm10k_vf.h"
b6fec18f
AD		 23
24/**
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
27 *
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
30 **/
31static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
32{
33 s32 err;
34 u32 reg;
35 u16 i;
36
37 /* Disable interrupts */
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
39
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
43
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
45
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
50 }
51
52 /* shut down all rings */
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
54 if (err)
55 return err;
56
57 /* Verify that DMA is no longer active */
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
61
62 /* Inititate data path reset */
63 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
64 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
65
66 /* Flush write and allow 100us for reset to complete */
67 fm10k_write_flush(hw);
68 udelay(FM10K_RESET_TIMEOUT);
69
70 /* Verify we made it out of reset */
71 reg = fm10k_read_reg(hw, FM10K_IP);
72 if (!(reg & FM10K_IP_NOTINRESET))
73 err = FM10K_ERR_RESET_FAILED;
74
75 return err;
76}
77
c2653865
AD		 78/**
79 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
80 * @hw: pointer to hardware structure
81 *
82 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
83 **/
84static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
85{
86 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
87
88 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
89}
90
b6fec18f
AD		 91/**
92 * fm10k_init_hw_pf - PF hardware initialization
93 * @hw: pointer to hardware structure
94 *
95 **/
96static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
97{
98 u32 dma_ctrl, txqctl;
99 u16 i;
100
101 /* Establish default VSI as valid */
102 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
103 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
104 FM10K_DGLORTMAP_ANY);
105
106 /* Invalidate all other GLORT entries */
107 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
108 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
109
110 /* reset ITR2(0) to point to itself */
111 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
112
113 /* reset VF ITR2(0) to point to 0 avoid PF registers */
114 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
115
116 /* loop through all PF ITR2 registers pointing them to the previous */
117 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
118 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
119
120 /* Enable interrupt moderator if not already enabled */
121 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
122
123 /* compute the default txqctl configuration */
124 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
125 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
126
127 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
128 /* configure rings for 256 Queue / 32 Descriptor cache mode */
129 fm10k_write_reg(hw, FM10K_TQDLOC(i),
130 (i * FM10K_TQDLOC_BASE_32_DESC) |
131 FM10K_TQDLOC_SIZE_32_DESC);
132 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
133
134 /* configure rings to provide TPH processing hints */
135 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
136 FM10K_TPH_TXCTRL_DESC_TPHEN |
137 FM10K_TPH_TXCTRL_DESC_RROEN |
138 FM10K_TPH_TXCTRL_DESC_WROEN |
139 FM10K_TPH_TXCTRL_DATA_RROEN);
140 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
141 FM10K_TPH_RXCTRL_DESC_TPHEN |
142 FM10K_TPH_RXCTRL_DESC_RROEN |
143 FM10K_TPH_RXCTRL_DATA_WROEN |
144 FM10K_TPH_RXCTRL_HDR_WROEN);
145 }
146
147 /* set max hold interval to align with 1.024 usec in all modes */
148 switch (hw->bus.speed) {
149 case fm10k_bus_speed_2500:
150 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
151 break;
152 case fm10k_bus_speed_5000:
153 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
154 break;
155 case fm10k_bus_speed_8000:
156 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
157 break;
158 default:
159 dma_ctrl = 0;
160 break;
161 }
162
163 /* Configure TSO flags */
164 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
165 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
166
167 /* Enable DMA engine
168 * Set Rx Descriptor size to 32
169 * Set Minimum MSS to 64
170 * Set Maximum number of Rx queues to 256 / 32 Descriptor
171 */
172 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
173 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
174 FM10K_DMA_CTRL_32_DESC;
175
176 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
177
178 /* record maximum queue count, we limit ourselves to 128 */
179 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
180
c2653865
AD		 181 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
182 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
183
b6fec18f
AD		 184 return 0;
185}
186
187/**
188 * fm10k_is_slot_appropriate_pf - Indicate appropriate slot for this SKU
189 * @hw: pointer to hardware structure
190 *
191 * Looks at the PCIe bus info to confirm whether or not this slot can support
192 * the necessary bandwidth for this device.
193 **/
194static bool fm10k_is_slot_appropriate_pf(struct fm10k_hw *hw)
195{
196 return (hw->bus.speed == hw->bus_caps.speed) &&
197 (hw->bus.width == hw->bus_caps.width);
198}
199
401b5383
AD		 200/**
201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
202 * @hw: pointer to hardware structure
203 * @vid: VLAN ID to add to table
204 * @vsi: Index indicating VF ID or PF ID in table
205 * @set: Indicates if this is a set or clear operation
206 *
207 * This function adds or removes the corresponding VLAN ID from the VLAN
208 * filter table for the corresponding function. In addition to the
209 * standard set/clear that supports one bit a multi-bit write is
210 * supported to set 64 bits at a time.
211 **/
212static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
213{
214 u32 vlan_table, reg, mask, bit, len;
215
216 /* verify the VSI index is valid */
217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
218 return FM10K_ERR_PARAM;
219
220 /* VLAN multi-bit write:
221 * The multi-bit write has several parts to it.
222 * 3 2 1 0
223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 * | RSVD0 | Length |C|RSVD0| VLAN ID |
226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
227 *
228 * VLAN ID: Vlan Starting value
229 * RSVD0: Reserved section, must be 0
230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
231 * Length: Number of times to repeat the bit being set
232 */
233 len = vid >> 16;
234 vid = (vid << 17) >> 17;
235
236 /* verify the reserved 0 fields are 0 */
eca32047 237 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
401b5383
AD		 238 return FM10K_ERR_PARAM;
239
240 /* Loop through the table updating all required VLANs */
241 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
242 len < FM10K_VLAN_TABLE_VID_MAX;
243 len -= 32 - bit, reg++, bit = 0) {
244 /* record the initial state of the register */
245 vlan_table = fm10k_read_reg(hw, reg);
246
247 /* truncate mask if we are at the start or end of the run */
248 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
249
250 /* make necessary modifications to the register */
251 mask &= set ? ~vlan_table : vlan_table;
252 if (mask)
253 fm10k_write_reg(hw, reg, vlan_table ^ mask);
254 }
255
256 return 0;
257}
258
b6fec18f
AD		 259/**
260 * fm10k_read_mac_addr_pf - Read device MAC address
261 * @hw: pointer to the HW structure
262 *
263 * Reads the device MAC address from the SM_AREA and stores the value.
264 **/
265static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
266{
267 u8 perm_addr[ETH_ALEN];
268 u32 serial_num;
269 int i;
270
271 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
272
273 /* last byte should be all 1's */
274 if ((~serial_num) << 24)
275 return FM10K_ERR_INVALID_MAC_ADDR;
276
277 perm_addr[0] = (u8)(serial_num >> 24);
278 perm_addr[1] = (u8)(serial_num >> 16);
279 perm_addr[2] = (u8)(serial_num >> 8);
280
281 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
282
283 /* first byte should be all 1's */
284 if ((~serial_num) >> 24)
285 return FM10K_ERR_INVALID_MAC_ADDR;
286
287 perm_addr[3] = (u8)(serial_num >> 16);
288 perm_addr[4] = (u8)(serial_num >> 8);
289 perm_addr[5] = (u8)(serial_num);
290
291 for (i = 0; i < ETH_ALEN; i++) {
292 hw->mac.perm_addr[i] = perm_addr[i];
293 hw->mac.addr[i] = perm_addr[i];
294 }
295
296 return 0;
297}
298
401b5383
AD		 299/**
300 * fm10k_glort_valid_pf - Validate that the provided glort is valid
301 * @hw: pointer to the HW structure
302 * @glort: base glort to be validated
303 *
304 * This function will return an error if the provided glort is invalid
305 **/
306bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
307{
308 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
309
310 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
311}
312
313/**
eca32047 314 * fm10k_update_xc_addr_pf - Update device addresses
401b5383
AD		 315 * @hw: pointer to the HW structure
316 * @glort: base resource tag for this request
317 * @mac: MAC address to add/remove from table
318 * @vid: VLAN ID to add/remove from table
319 * @add: Indicates if this is an add or remove operation
320 * @flags: flags field to indicate add and secure
321 *
322 * This function generates a message to the Switch API requesting
323 * that the given logical port add/remove the given L2 MAC/VLAN address.
324 **/
325static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
326 const u8 *mac, u16 vid, bool add, u8 flags)
327{
328 struct fm10k_mbx_info *mbx = &hw->mbx;
329 struct fm10k_mac_update mac_update;
330 u32 msg[5];
331
33a44c28
MV		 332 /* if glort or vlan are not valid return error */
333 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
401b5383
AD		 334 return FM10K_ERR_PARAM;
335
401b5383
AD		 336 /* record fields */
337 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
338 ((u32)mac[3] << 16) |
339 ((u32)mac[4] << 8) |
340 ((u32)mac[5]));
341 mac_update.mac_upper = cpu_to_le16(((u32)mac[0] << 8) |
342 ((u32)mac[1]));
343 mac_update.vlan = cpu_to_le16(vid);
344 mac_update.glort = cpu_to_le16(glort);
345 mac_update.action = add ? 0 : 1;
346 mac_update.flags = flags;
347
348 /* populate mac_update fields */
349 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
350 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
351 &mac_update, sizeof(mac_update));
352
353 /* load onto outgoing mailbox */
354 return mbx->ops.enqueue_tx(hw, mbx, msg);
355}
356
357/**
eca32047 358 * fm10k_update_uc_addr_pf - Update device unicast addresses
401b5383
AD		 359 * @hw: pointer to the HW structure
360 * @glort: base resource tag for this request
361 * @mac: MAC address to add/remove from table
362 * @vid: VLAN ID to add/remove from table
363 * @add: Indicates if this is an add or remove operation
364 * @flags: flags field to indicate add and secure
365 *
366 * This function is used to add or remove unicast addresses for
367 * the PF.
368 **/
369static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
370 const u8 *mac, u16 vid, bool add, u8 flags)
371{
372 /* verify MAC address is valid */
373 if (!is_valid_ether_addr(mac))
374 return FM10K_ERR_PARAM;
375
376 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
377}
378
379/**
380 * fm10k_update_mc_addr_pf - Update device multicast addresses
381 * @hw: pointer to the HW structure
382 * @glort: base resource tag for this request
383 * @mac: MAC address to add/remove from table
384 * @vid: VLAN ID to add/remove from table
385 * @add: Indicates if this is an add or remove operation
386 *
387 * This function is used to add or remove multicast MAC addresses for
388 * the PF.
389 **/
390static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
391 const u8 *mac, u16 vid, bool add)
392{
393 /* verify multicast address is valid */
394 if (!is_multicast_ether_addr(mac))
395 return FM10K_ERR_PARAM;
396
397 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
398}
399
400/**
401 * fm10k_update_xcast_mode_pf - Request update of multicast mode
402 * @hw: pointer to hardware structure
403 * @glort: base resource tag for this request
404 * @mode: integer value indicating mode being requested
405 *
406 * This function will attempt to request a higher mode for the port
407 * so that it can enable either multicast, multicast promiscuous, or
408 * promiscuous mode of operation.
409 **/
410static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
411{
412 struct fm10k_mbx_info *mbx = &hw->mbx;
413 u32 msg[3], xcast_mode;
414
415 if (mode > FM10K_XCAST_MODE_NONE)
416 return FM10K_ERR_PARAM;
417 /* if glort is not valid return error */
418 if (!fm10k_glort_valid_pf(hw, glort))
419 return FM10K_ERR_PARAM;
420
421 /* write xcast mode as a single u32 value,
422 * lower 16 bits: glort
423 * upper 16 bits: mode
424 */
425 xcast_mode = ((u32)mode << 16) | glort;
426
427 /* generate message requesting to change xcast mode */
428 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
429 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
430
431 /* load onto outgoing mailbox */
432 return mbx->ops.enqueue_tx(hw, mbx, msg);
433}
434
435/**
436 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
437 * @hw: pointer to hardware structure
438 *
439 * This function walks through the MSI-X vector table to determine the
440 * number of active interrupts and based on that information updates the
441 * interrupt moderator linked list.
442 **/
443static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
444{
445 u32 i;
446
447 /* Disable interrupt moderator */
448 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
449
450 /* loop through PF from last to first looking enabled vectors */
451 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
452 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
453 break;
454 }
455
eca32047 456 /* always reset VFITR2[0] to point to last enabled PF vector */
401b5383
AD		 457 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
458
459 /* reset ITR2[0] to point to last enabled PF vector */
c2653865
AD		 460 if (!hw->iov.num_vfs)
461 fm10k_write_reg(hw, FM10K_ITR2(0), i);
401b5383
AD		 462
463 /* Enable interrupt moderator */
464 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
465}
466
467/**
468 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
469 * @hw: pointer to the HW structure
470 * @glort: base resource tag for this request
471 * @count: number of logical ports being updated
472 * @enable: boolean value indicating enable or disable
473 *
474 * This function is used to add/remove a logical port from the switch.
475 **/
476static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
477 u16 count, bool enable)
478{
479 struct fm10k_mbx_info *mbx = &hw->mbx;
480 u32 msg[3], lport_msg;
481
482 /* do nothing if we are being asked to create or destroy 0 ports */
483 if (!count)
484 return 0;
485
486 /* if glort is not valid return error */
487 if (!fm10k_glort_valid_pf(hw, glort))
488 return FM10K_ERR_PARAM;
489
490 /* construct the lport message from the 2 pieces of data we have */
491 lport_msg = ((u32)count << 16) | glort;
492
493 /* generate lport create/delete message */
494 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
495 FM10K_PF_MSG_ID_LPORT_DELETE);
496 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
497
498 /* load onto outgoing mailbox */
499 return mbx->ops.enqueue_tx(hw, mbx, msg);
500}
501
502/**
503 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
504 * @hw: pointer to hardware structure
505 * @dglort: pointer to dglort configuration structure
506 *
507 * Reads the configuration structure contained in dglort_cfg and uses
508 * that information to then populate a DGLORTMAP/DEC entry and the queues
509 * to which it has been assigned.
510 **/
511static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
512 struct fm10k_dglort_cfg *dglort)
513{
514 u16 glort, queue_count, vsi_count, pc_count;
515 u16 vsi, queue, pc, q_idx;
516 u32 txqctl, dglortdec, dglortmap;
517
518 /* verify the dglort pointer */
519 if (!dglort)
520 return FM10K_ERR_PARAM;
521
522 /* verify the dglort values */
523 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
524 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
525 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
526 return FM10K_ERR_PARAM;
527
528 /* determine count of VSIs and queues */
529 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
530 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
531 glort = dglort->glort;
532 q_idx = dglort->queue_b;
533
534 /* configure SGLORT for queues */
535 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
536 for (queue = 0; queue < queue_count; queue++, q_idx++) {
537 if (q_idx >= FM10K_MAX_QUEUES)
538 break;
539
540 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
541 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
542 }
543 }
544
545 /* determine count of PCs and queues */
546 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
547 pc_count = 1 << dglort->pc_l;
548
549 /* configure PC for Tx queues */
550 for (pc = 0; pc < pc_count; pc++) {
551 q_idx = pc + dglort->queue_b;
552 for (queue = 0; queue < queue_count; queue++) {
553 if (q_idx >= FM10K_MAX_QUEUES)
554 break;
555
556 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
557 txqctl &= ~FM10K_TXQCTL_PC_MASK;
558 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
559 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
560
561 q_idx += pc_count;
562 }
563 }
564
565 /* configure DGLORTDEC */
566 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
567 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
568 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
569 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
570 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
571 ((u32)(dglort->queue_l));
572 if (dglort->inner_rss)
573 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
574
575 /* configure DGLORTMAP */
576 dglortmap = (dglort->idx == fm10k_dglort_default) ?
577 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
578 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
579 dglortmap |= dglort->glort;
580
581 /* write values to hardware */
582 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
583 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
584
585 return 0;
586}
587
c2653865
AD		 588u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
589{
590 u16 num_pools = hw->iov.num_pools;
591
592 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
593 8 : FM10K_MAX_QUEUES_POOL;
594}
595
596u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
597{
598 u16 num_vfs = hw->iov.num_vfs;
599 u16 vf_q_idx = FM10K_MAX_QUEUES;
600
601 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
602
603 return vf_q_idx;
604}
605
606static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
607{
608 u16 num_pools = hw->iov.num_pools;
609
610 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
611 FM10K_MAX_VECTORS_POOL;
612}
613
614static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
615{
616 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
617
618 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
619
620 return vf_v_idx;
621}
622
623/**
624 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
625 * @hw: pointer to the HW structure
626 * @num_vfs: number of VFs to be allocated
627 * @num_pools: number of virtualization pools to be allocated
628 *
629 * Allocates queues and traffic classes to virtualization entities to prepare
630 * the PF for SR-IOV and VMDq
631 **/
632static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
633 u16 num_pools)
634{
635 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
636 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
637 int i, j;
638
639 /* hardware only supports up to 64 pools */
640 if (num_pools > 64)
641 return FM10K_ERR_PARAM;
642
643 /* the number of VFs cannot exceed the number of pools */
644 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
645 return FM10K_ERR_PARAM;
646
647 /* record number of virtualization entities */
648 hw->iov.num_vfs = num_vfs;
649 hw->iov.num_pools = num_pools;
650
651 /* determine qmap offsets and counts */
652 qmap_stride = (num_vfs > 8) ? 32 : 256;
653 qpp = fm10k_queues_per_pool(hw);
654 vpp = fm10k_vectors_per_pool(hw);
655
656 /* calculate starting index for queues */
657 vf_q_idx = fm10k_vf_queue_index(hw, 0);
658 qmap_idx = 0;
659
660 /* establish TCs with -1 credits and no quanta to prevent transmit */
661 for (i = 0; i < num_vfs; i++) {
662 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
663 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
664 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
665 FM10K_TC_CREDIT_CREDIT_MASK);
666 }
667
668 /* zero out all mbmem registers */
669 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
670 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
671
672 /* clear event notification of VF FLR */
673 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
674 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
675
676 /* loop through unallocated rings assigning them back to PF */
677 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
678 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
679 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF | vid);
680 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
681 }
682
683 /* PF should have already updated VFITR2[0] */
684
685 /* update all ITR registers to flow to VFITR2[0] */
686 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
687 if (!(i & (vpp - 1)))
688 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
689 else
690 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
691 }
692
693 /* update PF ITR2[0] to reference the last vector */
694 fm10k_write_reg(hw, FM10K_ITR2(0),
695 fm10k_vf_vector_index(hw, num_vfs - 1));
696
697 /* loop through rings populating rings and TCs */
698 for (i = 0; i < num_vfs; i++) {
699 /* record index for VF queue 0 for use in end of loop */
700 vf_q_idx0 = vf_q_idx;
701
702 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
703 /* assign VF and locked TC to queues */
704 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
705 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
706 (i << FM10K_TXQCTL_TC_SHIFT) | i |
707 FM10K_TXQCTL_VF | vid);
708 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
709 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
710 FM10K_RXDCTL_DROP_ON_EMPTY);
711 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
712 FM10K_RXQCTL_VF |
713 (i << FM10K_RXQCTL_VF_SHIFT));
714
715 /* map queue pair to VF */
716 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
717 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
718 }
719
720 /* repeat the first ring for all of the remaining VF rings */
721 for (; j < qmap_stride; j++, qmap_idx++) {
722 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
723 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
724 }
725 }
726
727 /* loop through remaining indexes assigning all to queue 0 */
728 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
729 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
730 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
731 qmap_idx++;
732 }
733
734 return 0;
735}
736
737/**
738 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
739 * @hw: pointer to the HW structure
740 * @vf_idx: index of VF receiving GLORT
741 * @rate: Rate indicated in Mb/s
742 *
743 * Configured the TC for a given VF to allow only up to a given number
744 * of Mb/s of outgoing Tx throughput.
745 **/
746static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
747{
748 /* configure defaults */
749 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
750 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
751
752 /* verify vf is in range */
753 if (vf_idx >= hw->iov.num_vfs)
754 return FM10K_ERR_PARAM;
755
756 /* set interval to align with 4.096 usec in all modes */
757 switch (hw->bus.speed) {
758 case fm10k_bus_speed_2500:
759 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
760 break;
761 case fm10k_bus_speed_5000:
762 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
763 break;
764 default:
765 break;
766 }
767
768 if (rate) {
769 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
770 return FM10K_ERR_PARAM;
771
772 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
773 * The rate is provided in Mbits per second
774 * To tralslate from rate to quanta we need to multiply the
775 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
776 * dealing with floating point we can round the values up
777 * to the nearest whole number ratio which gives us 128 / 125.
778 */
779 tc_rate = (rate * 128) / 125;
780
781 /* try to keep the rate limiting accurate by increasing
782 * the number of credits and interval for rates less than 4Gb/s
783 */
784 if (rate < 4000)
785 interval <<= 1;
786 else
787 tc_rate >>= 1;
788 }
789
790 /* update rate limiter with new values */
791 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
792 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
793 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
794
795 return 0;
796}
797
798/**
799 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
800 * @hw: pointer to the HW structure
801 * @vf_idx: index of VF receiving GLORT
802 *
803 * Update the interrupt moderator linked list to include any MSI-X
804 * interrupts which the VF has enabled in the MSI-X vector table.
805 **/
806static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
807{
808 u16 vf_v_idx, vf_v_limit, i;
809
810 /* verify vf is in range */
811 if (vf_idx >= hw->iov.num_vfs)
812 return FM10K_ERR_PARAM;
813
eca32047 814 /* determine vector offset and count */
c2653865
AD		 815 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
816 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
817
818 /* search for first vector that is not masked */
819 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
820 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
821 break;
822 }
823
824 /* reset linked list so it now includes our active vectors */
825 if (vf_idx == (hw->iov.num_vfs - 1))
826 fm10k_write_reg(hw, FM10K_ITR2(0), i);
827 else
828 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
829
830 return 0;
831}
832
833/**
834 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
835 * @hw: pointer to the HW structure
836 * @vf_info: pointer to VF information structure
837 *
838 * Assign a MAC address and default VLAN to a VF and notify it of the update
839 **/
840static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
841 struct fm10k_vf_info *vf_info)
842{
843 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
844 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
845 s32 err = 0;
846 u16 vf_idx, vf_vid;
847
848 /* verify vf is in range */
849 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
850 return FM10K_ERR_PARAM;
851
852 /* determine qmap offsets and counts */
853 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
854 queues_per_pool = fm10k_queues_per_pool(hw);
855
856 /* calculate starting index for queues */
857 vf_idx = vf_info->vf_idx;
858 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
859 qmap_idx = qmap_stride * vf_idx;
860
861 /* MAP Tx queue back to 0 temporarily, and disable it */
862 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
863 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
864
865 /* determine correct default VLAN ID */
866 if (vf_info->pf_vid)
867 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
868 else
869 vf_vid = vf_info->sw_vid;
870
871 /* generate MAC_ADDR request */
872 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
873 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
874 vf_info->mac, vf_vid);
875
876 /* load onto outgoing mailbox, ignore any errors on enqueue */
877 if (vf_info->mbx.ops.enqueue_tx)
878 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
879
880 /* verify ring has disabled before modifying base address registers */
881 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
882 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
883 /* limit ourselves to a 1ms timeout */
884 if (timeout == 10) {
885 err = FM10K_ERR_DMA_PENDING;
886 goto err_out;
887 }
888
889 usleep_range(100, 200);
890 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
891 }
892
893 /* Update base address registers to contain MAC address */
894 if (is_valid_ether_addr(vf_info->mac)) {
895 tdbal = (((u32)vf_info->mac[3]) << 24) |
896 (((u32)vf_info->mac[4]) << 16) |
897 (((u32)vf_info->mac[5]) << 8);
898
899 tdbah = (((u32)0xFF) << 24) |
900 (((u32)vf_info->mac[0]) << 16) |
901 (((u32)vf_info->mac[1]) << 8) |
902 ((u32)vf_info->mac[2]);
903 }
904
905 /* Record the base address into queue 0 */
906 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
907 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
908
909err_out:
910 /* configure Queue control register */
911 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
912 FM10K_TXQCTL_VID_MASK;
913 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
914 FM10K_TXQCTL_VF | vf_idx;
915
916 /* assign VID */
917 for (i = 0; i < queues_per_pool; i++)
918 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
919
920 /* restore the queue back to VF ownership */
921 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
922 return err;
923}
924
925/**
926 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
927 * @hw: pointer to the HW structure
928 * @vf_info: pointer to VF information structure
929 *
930 * Reassign the interrupts and queues to a VF following an FLR
931 **/
932static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
933 struct fm10k_vf_info *vf_info)
934{
935 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
936 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
937 u16 vf_v_idx, vf_v_limit, vf_vid;
938 u8 vf_idx = vf_info->vf_idx;
939 int i;
940
941 /* verify vf is in range */
942 if (vf_idx >= hw->iov.num_vfs)
943 return FM10K_ERR_PARAM;
944
945 /* clear event notification of VF FLR */
946 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
947
948 /* force timeout and then disconnect the mailbox */
949 vf_info->mbx.timeout = 0;
950 if (vf_info->mbx.ops.disconnect)
951 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
952
eca32047 953 /* determine vector offset and count */
c2653865
AD		 954 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
955 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
956
957 /* determine qmap offsets and counts */
958 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
959 queues_per_pool = fm10k_queues_per_pool(hw);
960 qmap_idx = qmap_stride * vf_idx;
961
962 /* make all the queues inaccessible to the VF */
963 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
964 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
965 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
966 }
967
968 /* calculate starting index for queues */
969 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
970
971 /* determine correct default VLAN ID */
972 if (vf_info->pf_vid)
973 vf_vid = vf_info->pf_vid;
974 else
975 vf_vid = vf_info->sw_vid;
976
977 /* configure Queue control register */
978 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
979 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
980 FM10K_TXQCTL_VF | vf_idx;
981 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
982
983 /* stop further DMA and reset queue ownership back to VF */
984 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
985 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
986 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
987 fm10k_write_reg(hw, FM10K_RXDCTL(i),
988 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
989 FM10K_RXDCTL_DROP_ON_EMPTY);
990 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
991 }
992
993 /* reset TC with -1 credits and no quanta to prevent transmit */
994 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
995 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
996 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
997 FM10K_TC_CREDIT_CREDIT_MASK);
998
999 /* update our first entry in the table based on previous VF */
1000 if (!vf_idx)
1001 hw->mac.ops.update_int_moderator(hw);
1002 else
1003 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1004
1005 /* reset linked list so it now includes our active vectors */
1006 if (vf_idx == (hw->iov.num_vfs - 1))
1007 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1008 else
1009 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1010
1011 /* link remaining vectors so that next points to previous */
1012 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1013 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1014
1015 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1016 for (i = FM10K_VFMBMEM_LEN; i--;)
1017 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1018 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1019 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1020 for (i = FM10K_RETA_SIZE; i--;)
1021 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1022 for (i = FM10K_RSSRK_SIZE; i--;)
1023 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1024 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1025
1026 /* Update base address registers to contain MAC address */
1027 if (is_valid_ether_addr(vf_info->mac)) {
1028 tdbal = (((u32)vf_info->mac[3]) << 24) |
1029 (((u32)vf_info->mac[4]) << 16) |
1030 (((u32)vf_info->mac[5]) << 8);
1031 tdbah = (((u32)0xFF) << 24) |
1032 (((u32)vf_info->mac[0]) << 16) |
1033 (((u32)vf_info->mac[1]) << 8) |
1034 ((u32)vf_info->mac[2]);
1035 }
1036
eca32047 1037 /* map queue pairs back to VF from last to first */
c2653865
AD		 1038 for (i = queues_per_pool; i--;) {
1039 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1040 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1041 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1042 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1043 }
1044
1045 return 0;
1046}
1047
1048/**
1049 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1050 * @hw: pointer to hardware structure
1051 * @vf_info: pointer to VF information structure
1052 * @lport_idx: Logical port offset from the hardware glort
1053 * @flags: Set of capability flags to extend port beyond basic functionality
1054 *
1055 * This function allows enabling a VF port by assigning it a GLORT and
1056 * setting the flags so that it can enable an Rx mode.
1057 **/
1058static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1059 struct fm10k_vf_info *vf_info,
1060 u16 lport_idx, u8 flags)
1061{
1062 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1063
1064 /* if glort is not valid return error */
1065 if (!fm10k_glort_valid_pf(hw, glort))
1066 return FM10K_ERR_PARAM;
1067
1068 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1069 vf_info->glort = glort;
1070
1071 return 0;
1072}
1073
1074/**
1075 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1076 * @hw: pointer to hardware structure
1077 * @vf_info: pointer to VF information structure
1078 *
1079 * This function disables a VF port by stripping it of a GLORT and
1080 * setting the flags so that it cannot enable any Rx mode.
1081 **/
1082static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1083 struct fm10k_vf_info *vf_info)
1084{
1085 u32 msg[1];
1086
1087 /* need to disable the port if it is already enabled */
1088 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1089 /* notify switch that this port has been disabled */
1090 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1091
1092 /* generate port state response to notify VF it is not ready */
1093 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1094 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1095 }
1096
1097 /* clear flags and glort if it exists */
1098 vf_info->vf_flags = 0;
1099 vf_info->glort = 0;
1100}
1101
1102/**
1103 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1104 * @hw: pointer to hardware structure
1105 * @q: stats for all queues of a VF
1106 * @vf_idx: index of VF
1107 *
1108 * This function collects queue stats for VFs.
1109 **/
1110static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1111 struct fm10k_hw_stats_q *q,
1112 u16 vf_idx)
1113{
1114 u32 idx, qpp;
1115
1116 /* get stats for all of the queues */
1117 qpp = fm10k_queues_per_pool(hw);
1118 idx = fm10k_vf_queue_index(hw, vf_idx);
1119 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1120}
1121
5f226ddb
AD		 1122static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1123 struct fm10k_vf_info *vf_info,
1124 u64 timestamp)
1125{
1126 u32 msg[4];
1127
1128 /* generate port state response to notify VF it is not ready */
1129 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1130 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1131
1132 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1133}
1134
c2653865
AD		 1135/**
1136 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1137 * @hw: Pointer to hardware structure
1138 * @results: Pointer array to message, results[0] is pointer to message
1139 * @mbx: Pointer to mailbox information structure
1140 *
1141 * This function is a default handler for MSI-X requests from the VF. The
1142 * assumption is that in this case it is acceptable to just directly
eca32047 1143 * hand off the message from the VF to the underlying shared code.
c2653865
AD		 1144 **/
1145s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1146 struct fm10k_mbx_info *mbx)
1147{
1148 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1149 u8 vf_idx = vf_info->vf_idx;
1150
1151 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1152}
1153
1154/**
1155 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1156 * @hw: Pointer to hardware structure
1157 * @results: Pointer array to message, results[0] is pointer to message
1158 * @mbx: Pointer to mailbox information structure
1159 *
1160 * This function is a default handler for MAC/VLAN requests from the VF.
1161 * The assumption is that in this case it is acceptable to just directly
eca32047 1162 * hand off the message from the VF to the underlying shared code.
c2653865
AD		 1163 **/
1164s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1165 struct fm10k_mbx_info *mbx)
1166{
1167 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1168 int err = 0;
1169 u8 mac[ETH_ALEN];
1170 u32 *result;
1171 u16 vlan;
1172 u32 vid;
1173
1174 /* we shouldn't be updating rules on a disabled interface */
1175 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1176 err = FM10K_ERR_PARAM;
1177
1178 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1179 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1180
1181 /* record VLAN id requested */
1182 err = fm10k_tlv_attr_get_u32(result, &vid);
1183 if (err)
1184 return err;
1185
1186 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1187 if (!vid || (vid == FM10K_VLAN_CLEAR)) {
1188 if (vf_info->pf_vid)
1189 vid |= vf_info->pf_vid;
1190 else
1191 vid |= vf_info->sw_vid;
1192 } else if (vid != vf_info->pf_vid) {
1193 return FM10K_ERR_PARAM;
1194 }
1195
1196 /* update VSI info for VF in regards to VLAN table */
1197 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi,
1198 !(vid & FM10K_VLAN_CLEAR));
1199 }
1200
1201 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1202 result = results[FM10K_MAC_VLAN_MSG_MAC];
1203
1204 /* record unicast MAC address requested */
1205 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1206 if (err)
1207 return err;
1208
1209 /* block attempts to set MAC for a locked device */
1210 if (is_valid_ether_addr(vf_info->mac) &&
1211 memcmp(mac, vf_info->mac, ETH_ALEN))
1212 return FM10K_ERR_PARAM;
1213
1214 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1215 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1216 if (vf_info->pf_vid)
1217 vlan |= vf_info->pf_vid;
1218 else
1219 vlan |= vf_info->sw_vid;
1220 } else if (vf_info->pf_vid) {
1221 return FM10K_ERR_PARAM;
1222 }
1223
1224 /* notify switch of request for new unicast address */
1225 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort, mac, vlan,
1226 !(vlan & FM10K_VLAN_CLEAR), 0);
1227 }
1228
1229 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1230 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1231
1232 /* record multicast MAC address requested */
1233 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1234 if (err)
1235 return err;
1236
1237 /* verify that the VF is allowed to request multicast */
1238 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1239 return FM10K_ERR_PARAM;
1240
1241 /* if VLAN ID is 0, set the default VLAN ID instead of 0 */
1242 if (!vlan || (vlan == FM10K_VLAN_CLEAR)) {
1243 if (vf_info->pf_vid)
1244 vlan |= vf_info->pf_vid;
1245 else
1246 vlan |= vf_info->sw_vid;
1247 } else if (vf_info->pf_vid) {
1248 return FM10K_ERR_PARAM;
1249 }
1250
1251 /* notify switch of request for new multicast address */
1252 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort, mac,
1253 !(vlan & FM10K_VLAN_CLEAR), 0);
1254 }
1255
1256 return err;
1257}
1258
1259/**
1260 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1261 * @vf_info: VF info structure containing capability flags
1262 * @mode: Requested xcast mode
1263 *
1264 * This function outputs the mode that most closely matches the requested
1265 * mode. If not modes match it will request we disable the port
1266 **/
1267static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1268 u8 mode)
1269{
1270 u8 vf_flags = vf_info->vf_flags;
1271
1272 /* match up mode to capabilities as best as possible */
1273 switch (mode) {
1274 case FM10K_XCAST_MODE_PROMISC:
1275 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1276 return FM10K_XCAST_MODE_PROMISC;
1277 /* fallthough */
1278 case FM10K_XCAST_MODE_ALLMULTI:
1279 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1280 return FM10K_XCAST_MODE_ALLMULTI;
1281 /* fallthough */
1282 case FM10K_XCAST_MODE_MULTI:
1283 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1284 return FM10K_XCAST_MODE_MULTI;
1285 /* fallthough */
1286 case FM10K_XCAST_MODE_NONE:
1287 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1288 return FM10K_XCAST_MODE_NONE;
1289 /* fallthough */
1290 default:
1291 break;
1292 }
1293
1294 /* disable interface as it should not be able to request any */
1295 return FM10K_XCAST_MODE_DISABLE;
1296}
1297
1298/**
1299 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1300 * @hw: Pointer to hardware structure
1301 * @results: Pointer array to message, results[0] is pointer to message
1302 * @mbx: Pointer to mailbox information structure
1303 *
1304 * This function is a default handler for port state requests. The port
1305 * state requests for now are basic and consist of enabling or disabling
1306 * the port.
1307 **/
1308s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1309 struct fm10k_mbx_info *mbx)
1310{
1311 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1312 u32 *result;
1313 s32 err = 0;
1314 u32 msg[2];
1315 u8 mode = 0;
1316
1317 /* verify VF is allowed to enable even minimal mode */
1318 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1319 return FM10K_ERR_PARAM;
1320
1321 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1322 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1323
1324 /* XCAST mode update requested */
1325 err = fm10k_tlv_attr_get_u8(result, &mode);
1326 if (err)
1327 return FM10K_ERR_PARAM;
1328
1329 /* prep for possible demotion depending on capabilities */
1330 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1331
1332 /* if mode is not currently enabled, enable it */
1333 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1334 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1335
1336 /* swap mode back to a bit flag */
1337 mode = FM10K_VF_FLAG_SET_MODE(mode);
1338 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1339 /* need to disable the port if it is already enabled */
1340 if (FM10K_VF_FLAG_ENABLED(vf_info))
1341 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1342 1, false);
1343
1344 /* when enabling the port we should reset the rate limiters */
1345 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1346
1347 /* set mode for minimal functionality */
1348 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1349
1350 /* generate port state response to notify VF it is ready */
1351 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1352 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1353 mbx->ops.enqueue_tx(hw, mbx, msg);
1354 }
1355
1356 /* if enable state toggled note the update */
1357 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1358 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1359 !!mode);
1360
1361 /* if state change succeeded, then update our stored state */
1362 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1363 if (!err)
1364 vf_info->vf_flags = mode;
1365
1366 return err;
1367}
1368
1369const struct fm10k_msg_data fm10k_iov_msg_data_pf[] = {
1370 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1371 FM10K_VF_MSG_MSIX_HANDLER(fm10k_iov_msg_msix_pf),
1372 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_iov_msg_mac_vlan_pf),
1373 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_iov_msg_lport_state_pf),
1374 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1375};
1376
b6fec18f
AD		 1377/**
1378 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1379 * @hw: pointer to hardware structure
1380 * @stats: pointer to the stats structure to update
1381 *
1382 * This function collects and aggregates global and per queue hardware
1383 * statistics.
1384 **/
1385static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1386 struct fm10k_hw_stats *stats)
1387{
1388 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1389 u32 id, id_prev;
1390
1391 /* Use Tx queue 0 as a canary to detect a reset */
1392 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1393
1394 /* Read Global Statistics */
1395 do {
1396 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1397 &stats->timeout);
1398 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1399 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1400 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1401 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1402 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1403 &stats->vlan_drop);
1404 loopback_drop = fm10k_read_hw_stats_32b(hw,
1405 FM10K_STATS_LOOPBACK_DROP,
eca32047 1406 &stats->loopback_drop);
b6fec18f
AD		 1407 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1408 FM10K_STATS_NODESC_DROP,
1409 &stats->nodesc_drop);
1410
1411 /* if value has not changed then we have consistent data */
1412 id_prev = id;
1413 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1414 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1415
1416 /* drop non-ID bits and set VALID ID bit */
1417 id &= FM10K_TXQCTL_ID_MASK;
1418 id |= FM10K_STAT_VALID;
1419
1420 /* Update Global Statistics */
1421 if (stats->stats_idx == id) {
1422 stats->timeout.count += timeout;
1423 stats->ur.count += ur;
1424 stats->ca.count += ca;
1425 stats->um.count += um;
1426 stats->xec.count += xec;
1427 stats->vlan_drop.count += vlan_drop;
1428 stats->loopback_drop.count += loopback_drop;
1429 stats->nodesc_drop.count += nodesc_drop;
1430 }
1431
1432 /* Update bases and record current PF id */
1433 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1434 fm10k_update_hw_base_32b(&stats->ur, ur);
1435 fm10k_update_hw_base_32b(&stats->ca, ca);
1436 fm10k_update_hw_base_32b(&stats->um, um);
1437 fm10k_update_hw_base_32b(&stats->xec, xec);
1438 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1439 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1440 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1441 stats->stats_idx = id;
1442
1443 /* Update Queue Statistics */
1444 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1445}
1446
1447/**
1448 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1449 * @hw: pointer to hardware structure
1450 * @stats: pointer to the stats structure to update
1451 *
1452 * This function resets the base for global and per queue hardware
1453 * statistics.
1454 **/
1455static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1456 struct fm10k_hw_stats *stats)
1457{
1458 /* Unbind Global Statistics */
1459 fm10k_unbind_hw_stats_32b(&stats->timeout);
1460 fm10k_unbind_hw_stats_32b(&stats->ur);
1461 fm10k_unbind_hw_stats_32b(&stats->ca);
1462 fm10k_unbind_hw_stats_32b(&stats->um);
1463 fm10k_unbind_hw_stats_32b(&stats->xec);
1464 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1465 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1466 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1467
1468 /* Unbind Queue Statistics */
1469 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1470
1471 /* Reinitialize bases for all stats */
1472 fm10k_update_hw_stats_pf(hw, stats);
1473}
1474
401b5383
AD		 1475/**
1476 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1477 * @hw: pointer to hardware structure
1478 * @dma_mask: 64 bit DMA mask required for platform
1479 *
1480 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1481 * to limit the access to memory beyond what is physically in the system.
1482 **/
1483static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1484{
1485 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1486 u32 phyaddr = (u32)(dma_mask >> 32);
1487
1488 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1489}
1490
b6fec18f
AD		 1491/**
1492 * fm10k_get_fault_pf - Record a fault in one of the interface units
1493 * @hw: pointer to hardware structure
1494 * @type: pointer to fault type register offset
1495 * @fault: pointer to memory location to record the fault
1496 *
1497 * Record the fault register contents to the fault data structure and
1498 * clear the entry from the register.
1499 *
1500 * Returns ERR_PARAM if invalid register is specified or no error is present.
1501 **/
1502static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1503 struct fm10k_fault *fault)
1504{
1505 u32 func;
1506
1507 /* verify the fault register is in range and is aligned */
1508 switch (type) {
1509 case FM10K_PCA_FAULT:
1510 case FM10K_THI_FAULT:
1511 case FM10K_FUM_FAULT:
1512 break;
1513 default:
1514 return FM10K_ERR_PARAM;
1515 }
1516
1517 /* only service faults that are valid */
1518 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1519 if (!(func & FM10K_FAULT_FUNC_VALID))
1520 return FM10K_ERR_PARAM;
1521
1522 /* read remaining fields */
1523 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1524 fault->address <<= 32;
1525 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1526 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1527
1528 /* clear valid bit to allow for next error */
1529 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1530
1531 /* Record which function triggered the error */
1532 if (func & FM10K_FAULT_FUNC_PF)
1533 fault->func = 0;
1534 else
1535 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1536 FM10K_FAULT_FUNC_VF_SHIFT);
1537
1538 /* record fault type */
1539 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1540
1541 return 0;
1542}
1543
401b5383
AD		 1544/**
1545 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1546 * @hw: pointer to hardware structure
1547 *
1548 **/
1549static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1550{
1551 struct fm10k_mbx_info *mbx = &hw->mbx;
1552 u32 msg[1];
1553
1554 /* issue request asking for LPORT map */
1555 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1556
1557 /* load onto outgoing mailbox */
1558 return mbx->ops.enqueue_tx(hw, mbx, msg);
1559}
1560
1561/**
1562 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1563 * @hw: pointer to hardware structure
1564 * @switch_ready: pointer to boolean value that will record switch state
1565 *
1566 * This funciton will check the DMA_CTRL2 register and mailbox in order
1567 * to determine if the switch is ready for the PF to begin requesting
1568 * addresses and mapping traffic to the local interface.
1569 **/
1570static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1571{
1572 s32 ret_val = 0;
1573 u32 dma_ctrl2;
1574
eca32047 1575 /* verify the switch is ready for interaction */
401b5383
AD		 1576 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1577 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1578 goto out;
1579
1580 /* retrieve generic host state info */
1581 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1582 if (ret_val)
1583 goto out;
1584
1585 /* interface cannot receive traffic without logical ports */
1586 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1587 ret_val = fm10k_request_lport_map_pf(hw);
1588
1589out:
1590 return ret_val;
1591}
1592
1593/* This structure defines the attibutes to be parsed below */
1594const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1595 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1596 FM10K_TLV_ATTR_LAST
1597};
1598
1599/**
1600 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1601 * @hw: Pointer to hardware structure
1602 * @results: pointer array containing parsed data
1603 * @mbx: Pointer to mailbox information structure
1604 *
1605 * This handler configures the lport mapping based on the reply from the
1606 * switch API.
1607 **/
1608s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1609 struct fm10k_mbx_info *mbx)
1610{
1611 u16 glort, mask;
1612 u32 dglort_map;
1613 s32 err;
1614
1615 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1616 &dglort_map);
1617 if (err)
1618 return err;
1619
1620 /* extract values out of the header */
1621 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1622 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1623
1624 /* verify mask is set and none of the masked bits in glort are set */
1625 if (!mask || (glort & ~mask))
1626 return FM10K_ERR_PARAM;
1627
1628 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1629 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1630 return FM10K_ERR_PARAM;
1631
1632 /* record the glort, mask, and port count */
1633 hw->mac.dglort_map = dglort_map;
1634
1635 return 0;
1636}
1637
1638const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1639 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1640 FM10K_TLV_ATTR_LAST
1641};
1642
1643/**
1644 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1645 * @hw: Pointer to hardware structure
1646 * @results: pointer array containing parsed data
1647 * @mbx: Pointer to mailbox information structure
1648 *
1649 * This handler configures the default VLAN for the PF
1650 **/
1651s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1652 struct fm10k_mbx_info *mbx)
1653{
1654 u16 glort, pvid;
1655 u32 pvid_update;
1656 s32 err;
1657
1658 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1659 &pvid_update);
1660 if (err)
1661 return err;
1662
1663 /* extract values from the pvid update */
1664 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1665 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1666
1667 /* if glort is not valid return error */
1668 if (!fm10k_glort_valid_pf(hw, glort))
1669 return FM10K_ERR_PARAM;
1670
1671 /* verify VID is valid */
1672 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1673 return FM10K_ERR_PARAM;
1674
1675 /* record the port VLAN ID value */
1676 hw->mac.default_vid = pvid;
1677
1678 return 0;
1679}
1680
1681/**
1682 * fm10k_record_global_table_data - Move global table data to swapi table info
1683 * @from: pointer to source table data structure
1684 * @to: pointer to destination table info structure
1685 *
1686 * This function is will copy table_data to the table_info contained in
1687 * the hw struct.
1688 **/
1689static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1690 struct fm10k_swapi_table_info *to)
1691{
1692 /* convert from le32 struct to CPU byte ordered values */
1693 to->used = le32_to_cpu(from->used);
1694 to->avail = le32_to_cpu(from->avail);
1695}
1696
1697const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1698 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1699 sizeof(struct fm10k_swapi_error)),
1700 FM10K_TLV_ATTR_LAST
1701};
1702
1703/**
1704 * fm10k_msg_err_pf - Message handler for error reply
1705 * @hw: Pointer to hardware structure
1706 * @results: pointer array containing parsed data
1707 * @mbx: Pointer to mailbox information structure
1708 *
1709 * This handler will capture the data for any error replies to previous
1710 * messages that the PF has sent.
1711 **/
1712s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1713 struct fm10k_mbx_info *mbx)
1714{
1715 struct fm10k_swapi_error err_msg;
1716 s32 err;
1717
1718 /* extract structure from message */
1719 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1720 &err_msg, sizeof(err_msg));
1721 if (err)
1722 return err;
1723
1724 /* record table status */
1725 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1726 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1727 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1728
1729 /* record SW API status value */
1730 hw->swapi.status = le32_to_cpu(err_msg.status);
1731
1732 return 0;
1733}
1734
5f226ddb
AD		 1735const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1736 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1737 sizeof(struct fm10k_swapi_1588_timestamp)),
1738 FM10K_TLV_ATTR_LAST
1739};
1740
1741/* currently there is no shared 1588 timestamp handler */
1742
1743/**
1744 * fm10k_adjust_systime_pf - Adjust systime frequency
1745 * @hw: pointer to hardware structure
1746 * @ppb: adjustment rate in parts per billion
1747 *
1748 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1749 * if this function is supported for BAR 4 access. The adjustment amount
1750 * is based on the parts per billion value provided and adjusted to a
1751 * value based on parts per 2^48 clock cycles.
1752 *
1753 * If adjustment is not supported or the requested value is too large
1754 * we will return an error.
1755 **/
1756static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1757{
1758 u64 systime_adjust;
1759
1760 /* if sw_addr is not set we don't have switch register access */
1761 if (!hw->sw_addr)
1762 return ppb ? FM10K_ERR_PARAM : 0;
1763
1764 /* we must convert the value from parts per billion to parts per
1765 * 2^48 cycles. In addition I have opted to only use the 30 most
1766 * significant bits of the adjustment value as the 8 least
1767 * significant bits are located in another register and represent
1768 * a value significantly less than a part per billion, the result
1769 * of dropping the 8 least significant bits is that the adjustment
1770 * value is effectively multiplied by 2^8 when we write it.
1771 *
1772 * As a result of all this the math for this breaks down as follows:
1773 * ppb / 10^9 == adjust * 2^8 / 2^48
1774 * If we solve this for adjust, and simplify it comes out as:
1775 * ppb * 2^31 / 5^9 == adjust
1776 */
1777 systime_adjust = (ppb < 0) ? -ppb : ppb;
1778 systime_adjust <<= 31;
1779 do_div(systime_adjust, 1953125);
1780
1781 /* verify the requested adjustment value is in range */
1782 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1783 return FM10K_ERR_PARAM;
1784
1785 if (ppb < 0)
1786 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_NEGATIVE;
1787
1788 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1789
1790 return 0;
1791}
1792
1793/**
1794 * fm10k_read_systime_pf - Reads value of systime registers
1795 * @hw: pointer to the hardware structure
1796 *
1797 * Function reads the content of 2 registers, combined to represent a 64 bit
1798 * value measured in nanosecods. In order to guarantee the value is accurate
1799 * we check the 32 most significant bits both before and after reading the
1800 * 32 least significant bits to verify they didn't change as we were reading
1801 * the registers.
1802 **/
1803static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1804{
1805 u32 systime_l, systime_h, systime_tmp;
1806
1807 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1808
1809 do {
1810 systime_tmp = systime_h;
1811 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1812 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1813 } while (systime_tmp != systime_h);
1814
1815 return ((u64)systime_h << 32) | systime_l;
1816}
1817
401b5383
AD		 1818static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1819 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1820 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1821 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1822 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1823 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1824 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1825 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1826};
1827
b6fec18f
AD		 1828static struct fm10k_mac_ops mac_ops_pf = {
1829 .get_bus_info = &fm10k_get_bus_info_generic,
1830 .reset_hw = &fm10k_reset_hw_pf,
1831 .init_hw = &fm10k_init_hw_pf,
1832 .start_hw = &fm10k_start_hw_generic,
1833 .stop_hw = &fm10k_stop_hw_generic,
1834 .is_slot_appropriate = &fm10k_is_slot_appropriate_pf,
401b5383 1835 .update_vlan = &fm10k_update_vlan_pf,
b6fec18f 1836 .read_mac_addr = &fm10k_read_mac_addr_pf,
401b5383
AD		 1837 .update_uc_addr = &fm10k_update_uc_addr_pf,
1838 .update_mc_addr = &fm10k_update_mc_addr_pf,
1839 .update_xcast_mode = &fm10k_update_xcast_mode_pf,
1840 .update_int_moderator = &fm10k_update_int_moderator_pf,
1841 .update_lport_state = &fm10k_update_lport_state_pf,
b6fec18f
AD		 1842 .update_hw_stats = &fm10k_update_hw_stats_pf,
1843 .rebind_hw_stats = &fm10k_rebind_hw_stats_pf,
401b5383
AD		 1844 .configure_dglort_map = &fm10k_configure_dglort_map_pf,
1845 .set_dma_mask = &fm10k_set_dma_mask_pf,
b6fec18f 1846 .get_fault = &fm10k_get_fault_pf,
401b5383 1847 .get_host_state = &fm10k_get_host_state_pf,
5f226ddb
AD		 1848 .adjust_systime = &fm10k_adjust_systime_pf,
1849 .read_systime = &fm10k_read_systime_pf,
b6fec18f
AD		 1850};
1851
c2653865
AD		 1852static struct fm10k_iov_ops iov_ops_pf = {
1853 .assign_resources = &fm10k_iov_assign_resources_pf,
1854 .configure_tc = &fm10k_iov_configure_tc_pf,
1855 .assign_int_moderator = &fm10k_iov_assign_int_moderator_pf,
1856 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1857 .reset_resources = &fm10k_iov_reset_resources_pf,
1858 .set_lport = &fm10k_iov_set_lport_pf,
1859 .reset_lport = &fm10k_iov_reset_lport_pf,
1860 .update_stats = &fm10k_iov_update_stats_pf,
5f226ddb 1861 .report_timestamp = &fm10k_iov_report_timestamp_pf,
c2653865
AD		 1862};
1863
401b5383
AD		 1864static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1865{
1866 fm10k_get_invariants_generic(hw);
1867
1868 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1869}
1870
b6fec18f
AD		 1871struct fm10k_info fm10k_pf_info = {
1872 .mac = fm10k_mac_pf,
401b5383 1873 .get_invariants = &fm10k_get_invariants_pf,
b6fec18f 1874 .mac_ops = &mac_ops_pf,
c2653865 1875 .iov_ops = &iov_ops_pf,
b6fec18f 1876};
Linux kernel - Deliverables
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