i40e: move sync_vsi_filters up in service_task
[deliverable/linux.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
88eee9bc 4 * Copyright(c) 2013 - 2015 Intel Corporation.
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5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
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15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
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17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
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32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
2bc7ee8a 39#include <linux/iommu.h>
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40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
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45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
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48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
51616018 52#include <linux/if_bridge.h>
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53#include <linux/clocksource.h>
54#include <linux/net_tstamp.h>
55#include <linux/ptp_clock_kernel.h>
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56#include "i40e_type.h"
57#include "i40e_prototype.h"
38e00438
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58#ifdef I40E_FCOE
59#include "i40e_fcoe.h"
60#endif
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61#include "i40e_virtchnl.h"
62#include "i40e_virtchnl_pf.h"
63#include "i40e_txrx.h"
4e3b35b0 64#include "i40e_dcb.h"
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65
66/* Useful i40e defaults */
67#define I40E_BASE_PF_SEID 16
68#define I40E_BASE_VSI_SEID 512
69#define I40E_BASE_VEB_SEID 288
70#define I40E_MAX_VEB 16
71
72#define I40E_MAX_NUM_DESCRIPTORS 4096
232f4706 73#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
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74#define I40E_DEFAULT_NUM_DESCRIPTORS 512
75#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
76#define I40E_MIN_NUM_DESCRIPTORS 64
77#define I40E_MIN_MSIX 2
78#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 79#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
e25d00b8
ASJ
80/* max 16 qps */
81#define i40e_default_queues_per_vmdq(pf) \
82 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
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83#define I40E_DEFAULT_QUEUES_PER_VF 4
84#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
e25d00b8
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85#define i40e_pf_get_max_q_per_tc(pf) \
86 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
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87#define I40E_FDIR_RING 0
88#define I40E_FDIR_RING_COUNT 32
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89#ifdef I40E_FCOE
90#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
91#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
92#endif /* I40E_FCOE */
7daa6bf3 93#define I40E_MAX_AQ_BUF_SIZE 4096
07574897 94#define I40E_AQ_LEN 256
628f096d 95#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
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96#define I40E_MAX_USER_PRIORITY 8
97#define I40E_DEFAULT_MSG_ENABLE 4
23527308 98#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
fba52e21 99#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 100
7e45ab44 101/* Ethtool Private Flags */
41a1d04b 102#define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0)
9ac77266 103#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
ef17178c 104#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
1cdfd88f 105#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
827de392 106#define I40E_PRIV_FLAGS_PS BIT(4)
72b74869 107#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(5)
7e45ab44 108
7daa6bf3 109#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 110#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
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111#define I40E_NVM_VERSION_HI_SHIFT 12
112#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
2efaad86 113#define I40E_OEM_VER_BUILD_MASK 0xffff
f0b44440 114#define I40E_OEM_VER_PATCH_MASK 0xff
2efaad86
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115#define I40E_OEM_VER_BUILD_SHIFT 8
116#define I40E_OEM_VER_SHIFT 24
fe310704
AS
117
118/* The values in here are decimal coded as hex as is the case in the NVM map*/
119#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 120#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 121
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122/* magic for getting defines into strings */
123#define STRINGIFY(foo) #foo
124#define XSTRINGIFY(bar) STRINGIFY(bar)
125
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126#define I40E_RX_DESC(R, i) \
127 ((ring_is_16byte_desc_enabled(R)) \
128 ? (union i40e_32byte_rx_desc *) \
129 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
130 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
131#define I40E_TX_DESC(R, i) \
132 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
133#define I40E_TX_CTXTDESC(R, i) \
134 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
135#define I40E_TX_FDIRDESC(R, i) \
136 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
137
138/* default to trying for four seconds */
139#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
140
141/* driver state flags */
142enum i40e_state_t {
143 __I40E_TESTING,
144 __I40E_CONFIG_BUSY,
145 __I40E_CONFIG_DONE,
146 __I40E_DOWN,
147 __I40E_NEEDS_RESTART,
148 __I40E_SERVICE_SCHED,
149 __I40E_ADMINQ_EVENT_PENDING,
150 __I40E_MDD_EVENT_PENDING,
151 __I40E_VFLR_EVENT_PENDING,
152 __I40E_RESET_RECOVERY_PENDING,
153 __I40E_RESET_INTR_RECEIVED,
154 __I40E_REINIT_REQUESTED,
155 __I40E_PF_RESET_REQUESTED,
156 __I40E_CORE_RESET_REQUESTED,
157 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 158 __I40E_EMP_RESET_REQUESTED,
9df42d1a 159 __I40E_EMP_RESET_INTR_RECEIVED,
7daa6bf3 160 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 161 __I40E_SUSPENDED,
9ce34f02 162 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 163 __I40E_BAD_EEPROM,
b5d06f05 164 __I40E_DOWN_REQUESTED,
1e1be8f6 165 __I40E_FD_FLUSH_REQUESTED,
a316f651 166 __I40E_RESET_FAILED,
69129dc3 167 __I40E_PORT_TX_SUSPENDED,
3ba9bcb4 168 __I40E_VF_DISABLE,
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169};
170
171enum i40e_interrupt_policy {
172 I40E_INTERRUPT_BEST_CASE,
173 I40E_INTERRUPT_MEDIUM,
174 I40E_INTERRUPT_LOWEST
175};
176
177struct i40e_lump_tracking {
178 u16 num_entries;
179 u16 search_hint;
180 u16 list[0];
181#define I40E_PILE_VALID_BIT 0x8000
182};
183
184#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
55a5e60b
ASJ
185#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
186#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 187#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 188#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 189
b29e13bb 190#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
e69ff813 191#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
b29e13bb 192
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193enum i40e_fd_stat_idx {
194 I40E_FD_STAT_ATR,
195 I40E_FD_STAT_SB,
60ccd45c 196 I40E_FD_STAT_ATR_TUNNEL,
433c47de
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197 I40E_FD_STAT_PF_COUNT
198};
199#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
200#define I40E_FD_ATR_STAT_IDX(pf_id) \
201 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
202#define I40E_FD_SB_STAT_IDX(pf_id) \
203 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
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204#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
205 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 206
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JG
207struct i40e_fdir_filter {
208 struct hlist_node fdir_node;
209 /* filter ipnut set */
210 u8 flow_type;
211 u8 ip4_proto;
04b73bd7 212 /* TX packet view of src and dst */
17a73f6b
JG
213 __be32 dst_ip[4];
214 __be32 src_ip[4];
215 __be16 src_port;
216 __be16 dst_port;
217 __be32 sctp_v_tag;
218 /* filter control */
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219 u16 q_index;
220 u8 flex_off;
221 u8 pctype;
222 u16 dest_vsi;
223 u8 dest_ctl;
224 u8 fd_status;
225 u16 cnt_index;
226 u32 fd_id;
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227};
228
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NP
229#define I40E_ETH_P_LLDP 0x88cc
230
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231#define I40E_DCB_PRIO_TYPE_STRICT 0
232#define I40E_DCB_PRIO_TYPE_ETS 1
233#define I40E_DCB_STRICT_PRIO_CREDITS 127
234#define I40E_MAX_USER_PRIORITY 8
235/* DCB per TC information data structure */
236struct i40e_tc_info {
237 u16 qoffset; /* Queue offset from base queue */
238 u16 qcount; /* Total Queues */
239 u8 netdev_tc; /* Netdev TC index if netdev associated */
240};
241
242/* TC configuration data structure */
243struct i40e_tc_configuration {
244 u8 numtc; /* Total number of enabled TCs */
245 u8 enabled_tc; /* TC map */
246 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
247};
248
6a899024
SA
249struct i40e_udp_port_config {
250 __be16 index;
251 u8 type;
252};
253
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254/* struct that defines the Ethernet device */
255struct i40e_pf {
256 struct pci_dev *pdev;
257 struct i40e_hw hw;
258 unsigned long state;
7daa6bf3 259 struct msix_entry *msix_entries;
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260 bool fc_autoneg_status;
261
262 u16 eeprom_version;
b40c82e6 263 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
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264 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
265 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
b40c82e6
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266 u16 num_req_vfs; /* num VFs requested for this VF */
267 u16 num_vf_qps; /* num queue pairs per VF */
38e00438 268#ifdef I40E_FCOE
b40c82e6 269 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
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270 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
271#endif /* I40E_FCOE */
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272 u16 num_lan_qps; /* num lan queues this PF has set up */
273 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
f8ff1464 274 int queues_left; /* queues left unclaimed */
acd65448 275 u16 alloc_rss_size; /* allocated RSS queues */
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276 u16 rss_size_max; /* HW defined max RSS queues */
277 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 278 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 279 u8 atr_sample_rate;
8e2773ae 280 bool wol_en;
7daa6bf3 281
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JG
282 struct hlist_head fdir_filter_list;
283 u16 fdir_pf_active_filters;
1e1be8f6 284 unsigned long fd_flush_timestamp;
60793f4a 285 u32 fd_flush_cnt;
1e1be8f6
ASJ
286 u32 fd_add_err;
287 u32 fd_atr_cnt;
288 u32 fd_tcp_rule;
17a73f6b 289
6a899024
SA
290 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
291 u16 pending_udp_bitmap;
a1c9a9d9 292
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JB
293 enum i40e_interrupt_policy int_policy;
294 u16 rx_itr_default;
295 u16 tx_itr_default;
71e6163a 296 u32 msg_enable;
b294ac70 297 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 298 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN
299 unsigned long service_timer_period;
300 unsigned long service_timer_previous;
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JB
301 struct timer_list service_timer;
302 struct work_struct service_task;
303
304 u64 flags;
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JB
305#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
306#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
307#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
308#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
309#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
310#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
311#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
312#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
313#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
d502ce01 314#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
38e00438 315#ifdef I40E_FCOE
41a1d04b 316#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
38e00438 317#endif /* I40E_FCOE */
41a1d04b
JB
318#define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13)
319#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
320#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
321#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
322#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
323#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
324#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
325#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
326#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
327#define I40E_FLAG_PTP BIT_ULL(25)
328#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
6a899024 329#define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
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JB
330#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
331#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
d502ce01
ASJ
332#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
333#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
334#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
335#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
336#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
d1a8d275 337#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
d502ce01 338#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
9ac77266 339#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
fc60861e 340#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
6a899024 341#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
3fced535 342#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
48b1804e 343#define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43)
8eed76fa 344#define I40E_FLAG_RESTART_AUTONEG BIT_ULL(44)
b499ffb0 345#define I40E_FLAG_PF_MAC BIT_ULL(50)
7daa6bf3 346
61dade7e
ASJ
347 /* tracks features that get auto disabled by errors */
348 u64 auto_disable_flags;
349
38e00438
VD
350#ifdef I40E_FCOE
351 struct i40e_fcoe fcoe;
352
353#endif /* I40E_FCOE */
7daa6bf3
JB
354 bool stat_offsets_loaded;
355 struct i40e_hw_port_stats stats;
356 struct i40e_hw_port_stats stats_offsets;
357 u32 tx_timeout_count;
358 u32 tx_timeout_recovery_level;
359 unsigned long tx_timeout_last_recovery;
810b3ae4 360 u32 tx_sluggish_count;
7daa6bf3
JB
361 u32 hw_csum_rx_error;
362 u32 led_status;
363 u16 corer_count; /* Core reset count */
364 u16 globr_count; /* Global reset count */
365 u16 empr_count; /* EMP reset count */
366 u16 pfr_count; /* PF reset count */
cd92e72f 367 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB
368
369 struct mutex switch_mutex;
370 u16 lan_vsi; /* our default LAN VSI */
371 u16 lan_veb; /* initial relay, if exists */
372#define I40E_NO_VEB 0xffff
373#define I40E_NO_VSI 0xffff
374 u16 next_vsi; /* Next unallocated VSI - 0-based! */
375 struct i40e_vsi **vsi;
376 struct i40e_veb *veb[I40E_MAX_VEB];
377
378 struct i40e_lump_tracking *qp_pile;
379 struct i40e_lump_tracking *irq_pile;
380
381 /* switch config info */
382 u16 pf_seid;
383 u16 main_vsi_seid;
384 u16 mac_seid;
7daa6bf3
JB
385 struct kobject *switch_kobj;
386#ifdef CONFIG_DEBUG_FS
387 struct dentry *i40e_dbg_pf;
388#endif /* CONFIG_DEBUG_FS */
92faef85 389 bool cur_promisc;
7daa6bf3 390
93cd765b
ASJ
391 u16 instance; /* A unique number per i40e_pf instance in the system */
392
7daa6bf3
JB
393 /* sr-iov config info */
394 struct i40e_vf *vf;
395 int num_alloc_vfs; /* actual number of VFs allocated */
396 u32 vf_aq_requests;
1d0a4ada 397 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
7daa6bf3
JB
398
399 /* DCBx/DCBNL capability for PF that indicates
400 * whether DCBx is managed by firmware or host
401 * based agent (LLDPAD). Also, indicates what
402 * flavor of DCBx protocol (IEEE/CEE) is supported
403 * by the device. For now we're supporting IEEE
404 * mode only.
405 */
406 u16 dcbx_cap;
407
408 u32 fcoe_hmc_filt_num;
409 u32 fcoe_hmc_cntx_num;
410 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK
411
412 struct ptp_clock *ptp_clock;
413 struct ptp_clock_info ptp_caps;
414 struct sk_buff *ptp_tx_skb;
beb0dff1 415 struct hwtstamp_config tstamp_config;
beb0dff1
JK
416 unsigned long last_rx_ptp_check;
417 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
418 u64 ptp_base_adj;
419 u32 tx_hwtstamp_timeouts;
420 u32 rx_hwtstamp_cleared;
421 bool ptp_tx;
422 bool ptp_rx;
acd65448 423 u16 rss_table_size; /* HW RSS table size */
f4492db1
GR
424 /* These are only valid in NPAR modes */
425 u32 npar_max_bw;
426 u32 npar_min_bw;
2ac8b675
SN
427
428 u32 ioremap_len;
3487b6c3 429 u32 fd_inv;
7daa6bf3
JB
430};
431
432struct i40e_mac_filter {
433 struct list_head list;
434 u8 macaddr[ETH_ALEN];
435#define I40E_VLAN_ANY -1
436 s16 vlan;
437 u8 counter; /* number of instances of this filter */
438 bool is_vf; /* filter belongs to a VF */
439 bool is_netdev; /* filter belongs to a netdev */
440 bool changed; /* filter needs to be sync'd to the HW */
6252c7e4 441 bool is_laa; /* filter is a Locally Administered Address */
7daa6bf3
JB
442};
443
444struct i40e_veb {
445 struct i40e_pf *pf;
446 u16 idx;
447 u16 veb_idx; /* index of VEB parent */
448 u16 seid;
449 u16 uplink_seid;
450 u16 stats_idx; /* index of VEB parent */
451 u8 enabled_tc;
51616018 452 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB
453 u16 flags;
454 u16 bw_limit;
455 u8 bw_max_quanta;
456 bool is_abs_credits;
457 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
458 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
459 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
460 struct kobject *kobj;
461 bool stat_offsets_loaded;
462 struct i40e_eth_stats stats;
463 struct i40e_eth_stats stats_offsets;
fe860afb
NP
464 struct i40e_veb_tc_stats tc_stats;
465 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB
466};
467
468/* struct that defines a VSI, associated with a dev */
469struct i40e_vsi {
470 struct net_device *netdev;
471 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
472 bool netdev_registered;
473 bool stat_offsets_loaded;
474
475 u32 current_netdev_flags;
476 unsigned long state;
41a1d04b
JB
477#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
478#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB
479 unsigned long flags;
480
21659035
KP
481 /* Per VSI lock to protect elements/list (MAC filter) */
482 spinlock_t mac_filter_list_lock;
7daa6bf3
JB
483 struct list_head mac_filter_list;
484
485 /* VSI stats */
486 struct rtnl_link_stats64 net_stats;
487 struct rtnl_link_stats64 net_stats_offsets;
488 struct i40e_eth_stats eth_stats;
489 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD
490#ifdef I40E_FCOE
491 struct i40e_fcoe_stats fcoe_stats;
492 struct i40e_fcoe_stats fcoe_stats_offsets;
493 bool fcoe_stat_offsets_loaded;
494#endif
7daa6bf3
JB
495 u32 tx_restart;
496 u32 tx_busy;
2fc3d715 497 u64 tx_linearize;
164c9f54 498 u64 tx_force_wb;
7daa6bf3
JB
499 u32 rx_buf_failed;
500 u32 rx_page_failed;
501
9f65e15b
AD
502 /* These are containers of ring pointers, allocated at run-time */
503 struct i40e_ring **rx_rings;
504 struct i40e_ring **tx_rings;
7daa6bf3
JB
505
506 u16 work_limit;
507 /* high bit set means dynamic, use accessor routines to read/write.
508 * hardware only supports 2us resolution for the ITR registers.
509 * these values always store the USER setting, and must be converted
510 * before programming to a register.
511 */
512 u16 rx_itr_setting;
513 u16 tx_itr_setting;
ac26fc13 514 u16 int_rate_limit; /* value in usecs */
7daa6bf3 515
acd65448
HZ
516 u16 rss_table_size; /* HW RSS table size */
517 u16 rss_size; /* Allocated RSS queues */
28c5869f
HZ
518 u8 *rss_hkey_user; /* User configured hash keys */
519 u8 *rss_lut_user; /* User configured lookup table entries */
5db4cb59 520
7daa6bf3
JB
521 u16 max_frame;
522 u16 rx_hdr_len;
523 u16 rx_buf_len;
524 u8 dtype;
525
526 /* List of q_vectors allocated to this VSI */
493fb300 527 struct i40e_q_vector **q_vectors;
7daa6bf3
JB
528 int num_q_vectors;
529 int base_vector;
63741846 530 bool irqs_ready;
7daa6bf3
JB
531
532 u16 seid; /* HW index of this VSI (absolute index) */
533 u16 id; /* VSI number */
534 u16 uplink_seid;
535
536 u16 base_queue; /* vsi's first queue in hw array */
537 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
9a3bd2f1 538 u16 req_queue_pairs; /* User requested queue pairs */
7daa6bf3
JB
539 u16 num_queue_pairs; /* Used tx and rx pairs */
540 u16 num_desc;
541 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
542 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
543
544 struct i40e_tc_configuration tc_config;
545 struct i40e_aqc_vsi_properties_data info;
546
547 /* VSI BW limit (absolute across all TCs) */
548 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
549 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
550
551 /* Relative TC credits across VSIs */
552 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
553 /* TC BW limit credits within VSI */
554 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
555 /* TC BW limit max quanta within VSI */
556 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
557
558 struct i40e_pf *back; /* Backreference to associated PF */
559 u16 idx; /* index in pf->vsi[] */
560 u16 veb_idx; /* index of VEB parent */
561 struct kobject *kobj; /* sysfs object */
c156f856 562 bool current_isup; /* Sync 'link up' logging */
7daa6bf3
JB
563
564 /* VSI specific handlers */
565 irqreturn_t (*irq_handler)(int irq, void *data);
88eee9bc
CW
566
567 /* current rxnfc data */
568 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
7daa6bf3
JB
569} ____cacheline_internodealigned_in_smp;
570
571struct i40e_netdev_priv {
572 struct i40e_vsi *vsi;
573};
574
575/* struct that defines an interrupt vector */
576struct i40e_q_vector {
577 struct i40e_vsi *vsi;
578
579 u16 v_idx; /* index in the vsi->q_vector array. */
580 u16 reg_idx; /* register index of the interrupt */
581
582 struct napi_struct napi;
583
584 struct i40e_ring_container rx;
585 struct i40e_ring_container tx;
586
587 u8 num_ringpairs; /* total number of ring pairs in vector */
588
9c6c1259
KP
589#define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
590 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
591
7daa6bf3 592 cpumask_t affinity_mask;
493fb300 593 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 594 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 595 bool arm_wb_state;
ee2319cf
JB
596#define ITR_COUNTDOWN_START 100
597 u8 itr_countdown; /* when 0 should adjust ITR */
7daa6bf3
JB
598} ____cacheline_internodealigned_in_smp;
599
600/* lan device */
601struct i40e_device {
602 struct list_head list;
603 struct i40e_pf *pf;
604};
605
606/**
6dec1017 607 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB
608 * @hw: ptr to the hardware info
609 **/
6dec1017 610static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB
611{
612 static char buf[32];
2efaad86
CW
613 u32 full_ver;
614 u8 ver, patch;
615 u16 build;
616
617 full_ver = hw->nvm.oem_ver;
618 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
4eeb1fff
JB
619 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
620 I40E_OEM_VER_BUILD_MASK);
2efaad86 621 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
7daa6bf3
JB
622
623 snprintf(buf, sizeof(buf),
f0b44440 624 "%x.%02x 0x%x %d.%d.%d",
ff80301e
JB
625 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
626 I40E_NVM_VERSION_HI_SHIFT,
627 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
628 I40E_NVM_VERSION_LO_SHIFT,
2efaad86 629 hw->nvm.eetrack, ver, build, patch);
7daa6bf3
JB
630
631 return buf;
632}
633
634/**
635 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
636 * @netdev: the corresponding netdev
637 *
638 * Return the PF struct for the given netdev
639 **/
640static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
641{
642 struct i40e_netdev_priv *np = netdev_priv(netdev);
643 struct i40e_vsi *vsi = np->vsi;
644
645 return vsi->back;
646}
647
648static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
649 irqreturn_t (*irq_handler)(int, void *))
650{
651 vsi->irq_handler = irq_handler;
652}
653
654/**
655 * i40e_rx_is_programming_status - check for programming status descriptor
656 * @qw: the first quad word of the program status descriptor
657 *
658 * The value of in the descriptor length field indicate if this
659 * is a programming status descriptor for flow director or FCoE
660 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
661 * it is a packet descriptor.
662 **/
663static inline bool i40e_rx_is_programming_status(u64 qw)
664{
665 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
666 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
667}
668
082def10
ASJ
669/**
670 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 671 * @pf: pointer to the PF struct
082def10
ASJ
672 **/
673static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
674{
675 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
676}
677
7daa6bf3
JB
678/* needed by i40e_ethtool.c */
679int i40e_up(struct i40e_vsi *vsi);
680void i40e_down(struct i40e_vsi *vsi);
681extern const char i40e_driver_name[];
682extern const char i40e_driver_version_str[];
23326186 683void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3 684void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
043dd650
HZ
685int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
686int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
fdf0e0bf 687struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
7daa6bf3
JB
688void i40e_update_stats(struct i40e_vsi *vsi);
689void i40e_update_eth_stats(struct i40e_vsi *vsi);
690struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
691int i40e_fetch_switch_configuration(struct i40e_pf *pf,
692 bool printconfig);
693
17a73f6b 694int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 695 struct i40e_pf *pf, bool add);
17a73f6b
JG
696int i40e_add_del_fdir(struct i40e_vsi *vsi,
697 struct i40e_fdir_filter *input, bool add);
55a5e60b 698void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ
699u32 i40e_get_current_fd_count(struct i40e_pf *pf);
700u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
701u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
702u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 703bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB
704void i40e_set_ethtool_ops(struct net_device *netdev);
705struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
706 u8 *macaddr, s16 vlan,
707 bool is_vf, bool is_netdev);
708void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
709 bool is_vf, bool is_netdev);
17652c63 710int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
7daa6bf3
JB
711struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
712 u16 uplink, u32 param1);
713int i40e_vsi_release(struct i40e_vsi *vsi);
714struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
715 struct i40e_vsi *start_vsi);
38e00438
VD
716#ifdef I40E_FCOE
717void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
718 struct i40e_vsi_context *ctxt,
719 u8 enabled_tc, bool is_add);
720#endif
fc18eaa0 721int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 722int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB
723struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
724 u16 downlink_seid, u8 enabled_tc);
725void i40e_veb_release(struct i40e_veb *veb);
726
4e3b35b0 727int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
4eeb1fff 728int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
7daa6bf3
JB
729void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
730void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
731void i40e_pf_reset_stats(struct i40e_pf *pf);
732#ifdef CONFIG_DEBUG_FS
733void i40e_dbg_pf_init(struct i40e_pf *pf);
734void i40e_dbg_pf_exit(struct i40e_pf *pf);
735void i40e_dbg_init(void);
736void i40e_dbg_exit(void);
737#else
738static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
739static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
740static inline void i40e_dbg_init(void) {}
741static inline void i40e_dbg_exit(void) {}
742#endif /* CONFIG_DEBUG_FS*/
02d109be
JB
743/**
744 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
745 * @vsi: pointer to a vsi
746 * @vector: enable a particular Hw Interrupt vector, without base_vector
747 **/
748static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
749{
750 struct i40e_pf *pf = vsi->back;
751 struct i40e_hw *hw = &pf->hw;
752 u32 val;
753
754 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
755 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
756 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
757 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
758 /* skip the flush */
759}
760
2ef28cfb 761void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
116a57d4 762void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
38e00438
VD
763#ifdef I40E_FCOE
764struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
765 struct net_device *netdev,
766 struct rtnl_link_stats64 *storage);
767int i40e_set_mac(struct net_device *netdev, void *p);
768void i40e_set_rx_mode(struct net_device *netdev);
769#endif
7daa6bf3 770int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD
771#ifdef I40E_FCOE
772void i40e_tx_timeout(struct net_device *netdev);
773int i40e_vlan_rx_add_vid(struct net_device *netdev,
774 __always_unused __be16 proto, u16 vid);
775int i40e_vlan_rx_kill_vid(struct net_device *netdev,
776 __always_unused __be16 proto, u16 vid);
777#endif
96664483 778int i40e_open(struct net_device *netdev);
6c167f58 779int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB
780void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
781int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
782int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
783struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
784 bool is_vf, bool is_netdev);
b36e9ab5
MW
785int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
786 bool is_vf, bool is_netdev);
7daa6bf3
JB
787bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
788struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
789 bool is_vf, bool is_netdev);
38e00438 790#ifdef I40E_FCOE
38e00438 791int i40e_close(struct net_device *netdev);
16e5cc64
JF
792int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
793 struct tc_to_netdev *tc);
38e00438
VD
794void i40e_netpoll(struct net_device *netdev);
795int i40e_fcoe_enable(struct net_device *netdev);
796int i40e_fcoe_disable(struct net_device *netdev);
797int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
798u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
799void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
800void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
21364bcf 801void i40e_init_pf_fcoe(struct i40e_pf *pf);
38e00438
VD
802int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
803void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
804int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
805 union i40e_rx_desc *rx_desc,
806 struct sk_buff *skb);
807void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
808 union i40e_rx_desc *rx_desc, u8 prog_id);
809#endif /* I40E_FCOE */
7daa6bf3 810void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP
811#ifdef CONFIG_I40E_DCB
812void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 813 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP
814 struct i40e_dcbx_config *new_cfg);
815void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
816void i40e_dcbnl_setup(struct i40e_vsi *vsi);
817bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
818 struct i40e_dcbx_config *old_cfg,
819 struct i40e_dcbx_config *new_cfg);
820#endif /* CONFIG_I40E_DCB */
beb0dff1
JK
821void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
822void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
823void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
824void i40e_ptp_set_increment(struct i40e_pf *pf);
825int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
826int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
827void i40e_ptp_init(struct i40e_pf *pf);
828void i40e_ptp_stop(struct i40e_pf *pf);
51616018 829int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
f4492db1
GR
830i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
831i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
832i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
c156f856 833void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
7daa6bf3 834#endif /* _I40E_H_ */
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